/usr/bin/java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data -s ../../../trunk/examples/settings/automizer/mcr/svcomp-Reach-32bit-Automizer_Default-noMmResRef-FA-McrAutomaton-WP.epf -tc ../../../trunk/examples/toolchains/AutomizerBplInline.xml -i ../../../trunk/examples/concurrent/bpl/weaver-benchmarks/generated/popl20/prod-cons3.wvr.bpl -------------------------------------------------------------------------------- This is Ultimate 0.2.2-wip.dk.mcr-reduction-c7b2d19 [2022-03-15 21:34:50,548 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-03-15 21:34:50,550 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-03-15 21:34:50,587 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... 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[2022-03-15 21:34:50,621 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-03-15 21:34:50,622 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-03-15 21:34:50,622 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-03-15 21:34:50,623 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/automizer/mcr/svcomp-Reach-32bit-Automizer_Default-noMmResRef-FA-McrAutomaton-WP.epf [2022-03-15 21:34:50,639 INFO L113 SettingsManager]: Loading preferences was successful [2022-03-15 21:34:50,640 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-03-15 21:34:50,640 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-03-15 21:34:50,640 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-03-15 21:34:50,641 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-03-15 21:34:50,641 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-03-15 21:34:50,641 INFO L138 SettingsManager]: * Use SBE=true [2022-03-15 21:34:50,641 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-03-15 21:34:50,641 INFO L138 SettingsManager]: * sizeof long=4 [2022-03-15 21:34:50,641 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-03-15 21:34:50,641 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-03-15 21:34:50,641 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-03-15 21:34:50,641 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-03-15 21:34:50,641 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-03-15 21:34:50,641 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-03-15 21:34:50,642 INFO L138 SettingsManager]: * sizeof long double=12 [2022-03-15 21:34:50,642 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-03-15 21:34:50,642 INFO L138 SettingsManager]: * Use constant arrays=true [2022-03-15 21:34:50,642 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-03-15 21:34:50,642 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-03-15 21:34:50,642 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-03-15 21:34:50,642 INFO L138 SettingsManager]: * To the following directory=./dump/ [2022-03-15 21:34:50,642 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-03-15 21:34:50,642 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-03-15 21:34:50,642 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-03-15 21:34:50,642 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=Craig_NestedInterpolation [2022-03-15 21:34:50,643 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-03-15 21:34:50,643 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-03-15 21:34:50,643 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-03-15 21:34:50,643 INFO L138 SettingsManager]: * Override the interpolant automaton setting of the refinement strategy=true [2022-03-15 21:34:50,643 INFO L138 SettingsManager]: * Large block encoding in concurrent analysis=VARIABLE_BASED_MOVER_CHECK [2022-03-15 21:34:50,643 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-03-15 21:34:50,643 INFO L138 SettingsManager]: * Interpolant automaton=MCR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release [2022-03-15 21:34:50,832 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-03-15 21:34:50,848 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-03-15 21:34:50,850 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-03-15 21:34:50,850 INFO L271 PluginConnector]: Initializing Boogie PL CUP Parser... [2022-03-15 21:34:50,851 INFO L275 PluginConnector]: Boogie PL CUP Parser initialized [2022-03-15 21:34:50,852 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/concurrent/bpl/weaver-benchmarks/generated/popl20/prod-cons3.wvr.bpl [2022-03-15 21:34:50,852 INFO L110 BoogieParser]: Parsing: '/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/concurrent/bpl/weaver-benchmarks/generated/popl20/prod-cons3.wvr.bpl' [2022-03-15 21:34:50,871 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-03-15 21:34:50,872 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2022-03-15 21:34:50,872 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-03-15 21:34:50,872 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-03-15 21:34:50,872 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-03-15 21:34:50,880 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "prod-cons3.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 15.03 09:34:50" (1/1) ... [2022-03-15 21:34:50,885 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "prod-cons3.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 15.03 09:34:50" (1/1) ... [2022-03-15 21:34:50,889 INFO L137 Inliner]: procedures = 5, calls = 4, calls flagged for inlining = 0, calls inlined = 0, statements flattened = 0 [2022-03-15 21:34:50,890 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-03-15 21:34:50,892 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-03-15 21:34:50,893 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-03-15 21:34:50,893 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-03-15 21:34:50,898 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "prod-cons3.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 15.03 09:34:50" (1/1) ... [2022-03-15 21:34:50,898 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "prod-cons3.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 15.03 09:34:50" (1/1) ... [2022-03-15 21:34:50,899 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "prod-cons3.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 15.03 09:34:50" (1/1) ... [2022-03-15 21:34:50,899 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "prod-cons3.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 15.03 09:34:50" (1/1) ... [2022-03-15 21:34:50,901 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "prod-cons3.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 15.03 09:34:50" (1/1) ... [2022-03-15 21:34:50,903 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "prod-cons3.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 15.03 09:34:50" (1/1) ... [2022-03-15 21:34:50,903 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "prod-cons3.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 15.03 09:34:50" (1/1) ... [2022-03-15 21:34:50,904 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-03-15 21:34:50,904 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-03-15 21:34:50,905 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-03-15 21:34:50,905 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-03-15 21:34:50,920 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "prod-cons3.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 15.03 09:34:50" (1/1) ... [2022-03-15 21:34:50,937 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-03-15 21:34:50,943 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:34:50,954 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-03-15 21:34:50,972 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-03-15 21:34:50,984 INFO L124 BoogieDeclarations]: Specification and implementation of procedure thread1 given in one single declaration [2022-03-15 21:34:50,984 INFO L130 BoogieDeclarations]: Found specification of procedure thread1 [2022-03-15 21:34:50,984 INFO L138 BoogieDeclarations]: Found implementation of procedure thread1 [2022-03-15 21:34:50,984 INFO L124 BoogieDeclarations]: Specification and implementation of procedure thread2 given in one single declaration [2022-03-15 21:34:50,984 INFO L130 BoogieDeclarations]: Found specification of procedure thread2 [2022-03-15 21:34:50,984 INFO L138 BoogieDeclarations]: Found implementation of procedure thread2 [2022-03-15 21:34:50,984 INFO L124 BoogieDeclarations]: Specification and implementation of procedure ULTIMATE.start given in one single declaration [2022-03-15 21:34:50,984 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-03-15 21:34:50,984 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-03-15 21:34:50,984 INFO L124 BoogieDeclarations]: Specification and implementation of procedure thread3 given in one single declaration [2022-03-15 21:34:50,984 INFO L130 BoogieDeclarations]: Found specification of procedure thread3 [2022-03-15 21:34:50,985 INFO L138 BoogieDeclarations]: Found implementation of procedure thread3 [2022-03-15 21:34:50,985 INFO L124 BoogieDeclarations]: Specification and implementation of procedure thread4 given in one single declaration [2022-03-15 21:34:50,985 INFO L130 BoogieDeclarations]: Found specification of procedure thread4 [2022-03-15 21:34:50,985 INFO L138 BoogieDeclarations]: Found implementation of procedure thread4 [2022-03-15 21:34:50,985 WARN L208 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2022-03-15 21:34:51,022 INFO L234 CfgBuilder]: Building ICFG [2022-03-15 21:34:51,023 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-03-15 21:34:51,120 INFO L275 CfgBuilder]: Performing block encoding [2022-03-15 21:34:51,137 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-03-15 21:34:51,138 INFO L299 CfgBuilder]: Removed 0 assume(true) statements. [2022-03-15 21:34:51,139 INFO L202 PluginConnector]: Adding new model prod-cons3.wvr.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.03 09:34:51 BoogieIcfgContainer [2022-03-15 21:34:51,147 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-03-15 21:34:51,149 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-03-15 21:34:51,149 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-03-15 21:34:51,165 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-03-15 21:34:51,165 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "prod-cons3.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 15.03 09:34:50" (1/2) ... [2022-03-15 21:34:51,166 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@cbb8aa and model type prod-cons3.wvr.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 15.03 09:34:51, skipping insertion in model container [2022-03-15 21:34:51,166 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "prod-cons3.wvr.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.03 09:34:51" (2/2) ... [2022-03-15 21:34:51,167 INFO L111 eAbstractionObserver]: Analyzing ICFG prod-cons3.wvr.bpl [2022-03-15 21:34:51,170 WARN L150 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2022-03-15 21:34:51,171 INFO L205 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:Craig_NestedInterpolation Determinization: PREDICATE_ABSTRACTION [2022-03-15 21:34:51,171 INFO L164 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-03-15 21:34:51,171 INFO L534 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2022-03-15 21:34:51,224 INFO L148 ThreadInstanceAdder]: Constructed 4 joinOtherThreadTransitions. [2022-03-15 21:34:51,256 INFO L338 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-03-15 21:34:51,261 INFO L339 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=Craig_NestedInterpolation, mInterpolantAutomaton=MCR, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=FINITE_AUTOMATA, mLazyFiniteAutomaton=false, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=true, mMcrInterpolantMethod=WP, mLoopAccelerationTechnique=FAST_UPR, mMcrOptimizeForkJoin=true, mMcrOverapproximateWrwc=true [2022-03-15 21:34:51,261 INFO L340 AbstractCegarLoop]: Starting to check reachability of 5 error locations. [2022-03-15 21:34:51,284 INFO L126 etLargeBlockEncoding]: Petri net LBE is using variable-based independence relation. [2022-03-15 21:34:51,290 INFO L133 etLargeBlockEncoding]: Starting large block encoding on Petri net that has 50 places, 40 transitions, 112 flow [2022-03-15 21:34:51,298 INFO L110 LiptonReduction]: Starting Lipton reduction on Petri net that has 50 places, 40 transitions, 112 flow [2022-03-15 21:34:51,300 INFO L74 FinitePrefix]: Start finitePrefix. Operand has 50 places, 40 transitions, 112 flow [2022-03-15 21:34:51,336 INFO L129 PetriNetUnfolder]: 3/36 cut-off events. [2022-03-15 21:34:51,336 INFO L130 PetriNetUnfolder]: For 4/4 co-relation queries the response was YES. [2022-03-15 21:34:51,338 INFO L84 FinitePrefix]: Finished finitePrefix Result has 53 conditions, 36 events. 3/36 cut-off events. For 4/4 co-relation queries the response was YES. Maximal size of possible extension queue 5. Compared 60 event pairs, 0 based on Foata normal form. 0/32 useless extension candidates. Maximal degree in co-relation 31. Up to 2 conditions per place. [2022-03-15 21:34:51,342 INFO L116 LiptonReduction]: Number of co-enabled transitions 342 [2022-03-15 21:34:51,620 INFO L131 LiptonReduction]: Checked pairs total: 896 [2022-03-15 21:34:51,620 INFO L133 LiptonReduction]: Total number of compositions: 14 [2022-03-15 21:34:51,632 INFO L111 iNet2FiniteAutomaton]: Start petriNet2FiniteAutomaton. Operand has 37 places, 27 transitions, 86 flow [2022-03-15 21:34:51,664 INFO L133 iNet2FiniteAutomaton]: Finished petriNet2FiniteAutomaton. Result has 205 states, 204 states have (on average 3.4754901960784315) internal successors, (709), 204 states have internal predecessors, (709), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:51,666 INFO L276 IsEmpty]: Start isEmpty. Operand has 205 states, 204 states have (on average 3.4754901960784315) internal successors, (709), 204 states have internal predecessors, (709), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:51,672 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2022-03-15 21:34:51,672 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:34:51,673 INFO L514 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:34:51,673 INFO L402 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION (and 1 more)] === [2022-03-15 21:34:51,676 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:34:51,676 INFO L85 PathProgramCache]: Analyzing trace with hash -1245275209, now seen corresponding path program 1 times [2022-03-15 21:34:51,688 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:34:51,688 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1257833833] [2022-03-15 21:34:51,689 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:34:51,689 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:34:51,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:34:51,785 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:34:51,785 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:34:51,786 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1257833833] [2022-03-15 21:34:51,786 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1257833833] provided 1 perfect and 0 imperfect interpolant sequences [2022-03-15 21:34:51,786 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-03-15 21:34:51,786 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-03-15 21:34:51,787 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [570122180] [2022-03-15 21:34:51,788 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:34:51,792 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:34:51,842 INFO L252 McrAutomatonBuilder]: Finished intersection with 37 states and 66 transitions. [2022-03-15 21:34:51,842 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:34:51,952 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 0 new interpolants: [] [2022-03-15 21:34:51,953 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-03-15 21:34:51,953 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:34:51,970 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-03-15 21:34:51,971 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-03-15 21:34:51,972 INFO L87 Difference]: Start difference. First operand has 205 states, 204 states have (on average 3.4754901960784315) internal successors, (709), 204 states have internal predecessors, (709), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 7.666666666666667) internal successors, (23), 2 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:52,018 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:34:52,019 INFO L93 Difference]: Finished difference Result 218 states and 659 transitions. [2022-03-15 21:34:52,020 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-03-15 21:34:52,021 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 7.666666666666667) internal successors, (23), 2 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 14 [2022-03-15 21:34:52,022 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:34:52,030 INFO L225 Difference]: With dead ends: 218 [2022-03-15 21:34:52,030 INFO L226 Difference]: Without dead ends: 148 [2022-03-15 21:34:52,031 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 23 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-03-15 21:34:52,033 INFO L933 BasicCegarLoop]: 1 mSDtfsCounter, 10 mSDsluCounter, 9 mSDsCounter, 0 mSdLazyCounter, 37 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 10 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 41 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 37 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-03-15 21:34:52,034 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [10 Valid, 2 Invalid, 41 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 37 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-03-15 21:34:52,045 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148 states. [2022-03-15 21:34:52,059 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148 to 148. [2022-03-15 21:34:52,060 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 148 states, 147 states have (on average 3.0) internal successors, (441), 147 states have internal predecessors, (441), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:52,061 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148 states to 148 states and 441 transitions. [2022-03-15 21:34:52,062 INFO L78 Accepts]: Start accepts. Automaton has 148 states and 441 transitions. Word has length 14 [2022-03-15 21:34:52,063 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:34:52,063 INFO L470 AbstractCegarLoop]: Abstraction has 148 states and 441 transitions. [2022-03-15 21:34:52,063 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 7.666666666666667) internal successors, (23), 2 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:52,063 INFO L276 IsEmpty]: Start isEmpty. Operand 148 states and 441 transitions. [2022-03-15 21:34:52,064 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2022-03-15 21:34:52,064 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:34:52,064 INFO L514 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:34:52,065 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-03-15 21:34:52,065 INFO L402 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION (and 1 more)] === [2022-03-15 21:34:52,065 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:34:52,065 INFO L85 PathProgramCache]: Analyzing trace with hash 1808142103, now seen corresponding path program 2 times [2022-03-15 21:34:52,066 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:34:52,066 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [305263355] [2022-03-15 21:34:52,066 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:34:52,066 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:34:52,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:34:52,093 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:34:52,093 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:34:52,093 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [305263355] [2022-03-15 21:34:52,093 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [305263355] provided 1 perfect and 0 imperfect interpolant sequences [2022-03-15 21:34:52,093 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-03-15 21:34:52,094 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-03-15 21:34:52,094 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1637171149] [2022-03-15 21:34:52,094 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:34:52,095 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:34:52,097 INFO L252 McrAutomatonBuilder]: Finished intersection with 24 states and 33 transitions. [2022-03-15 21:34:52,097 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:34:52,150 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 0 new interpolants: [] [2022-03-15 21:34:52,158 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-03-15 21:34:52,158 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:34:52,158 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-03-15 21:34:52,158 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-03-15 21:34:52,159 INFO L87 Difference]: Start difference. First operand 148 states and 441 transitions. Second operand has 4 states, 4 states have (on average 5.25) internal successors, (21), 3 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:52,216 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:34:52,216 INFO L93 Difference]: Finished difference Result 259 states and 785 transitions. [2022-03-15 21:34:52,217 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-03-15 21:34:52,217 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 5.25) internal successors, (21), 3 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 14 [2022-03-15 21:34:52,217 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:34:52,219 INFO L225 Difference]: With dead ends: 259 [2022-03-15 21:34:52,219 INFO L226 Difference]: Without dead ends: 211 [2022-03-15 21:34:52,219 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 10 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-03-15 21:34:52,220 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 29 mSDsluCounter, 21 mSDsCounter, 0 mSdLazyCounter, 53 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 29 SdHoareTripleChecker+Valid, 1 SdHoareTripleChecker+Invalid, 56 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 53 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-03-15 21:34:52,220 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [29 Valid, 1 Invalid, 56 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 53 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-03-15 21:34:52,221 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 211 states. [2022-03-15 21:34:52,230 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 211 to 211. [2022-03-15 21:34:52,230 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 211 states, 210 states have (on average 3.1285714285714286) internal successors, (657), 210 states have internal predecessors, (657), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:52,231 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 211 states to 211 states and 657 transitions. [2022-03-15 21:34:52,231 INFO L78 Accepts]: Start accepts. Automaton has 211 states and 657 transitions. Word has length 14 [2022-03-15 21:34:52,232 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:34:52,232 INFO L470 AbstractCegarLoop]: Abstraction has 211 states and 657 transitions. [2022-03-15 21:34:52,232 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 5.25) internal successors, (21), 3 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:52,232 INFO L276 IsEmpty]: Start isEmpty. Operand 211 states and 657 transitions. [2022-03-15 21:34:52,233 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2022-03-15 21:34:52,233 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:34:52,233 INFO L514 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:34:52,233 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-03-15 21:34:52,234 INFO L402 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION (and 1 more)] === [2022-03-15 21:34:52,234 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:34:52,234 INFO L85 PathProgramCache]: Analyzing trace with hash 1780120023, now seen corresponding path program 1 times [2022-03-15 21:34:52,235 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:34:52,235 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [809931690] [2022-03-15 21:34:52,235 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:34:52,235 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:34:52,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:34:52,260 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:34:52,260 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:34:52,260 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [809931690] [2022-03-15 21:34:52,260 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [809931690] provided 1 perfect and 0 imperfect interpolant sequences [2022-03-15 21:34:52,261 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-03-15 21:34:52,261 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-03-15 21:34:52,261 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [668649524] [2022-03-15 21:34:52,261 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:34:52,262 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:34:52,266 INFO L252 McrAutomatonBuilder]: Finished intersection with 39 states and 63 transitions. [2022-03-15 21:34:52,266 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:34:52,394 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 0 new interpolants: [] [2022-03-15 21:34:52,395 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-03-15 21:34:52,395 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:34:52,395 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-03-15 21:34:52,395 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-03-15 21:34:52,395 INFO L87 Difference]: Start difference. First operand 211 states and 657 transitions. Second operand has 3 states, 3 states have (on average 6.666666666666667) internal successors, (20), 2 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:52,422 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:34:52,422 INFO L93 Difference]: Finished difference Result 262 states and 807 transitions. [2022-03-15 21:34:52,422 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-03-15 21:34:52,422 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 6.666666666666667) internal successors, (20), 2 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 17 [2022-03-15 21:34:52,423 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:34:52,425 INFO L225 Difference]: With dead ends: 262 [2022-03-15 21:34:52,425 INFO L226 Difference]: Without dead ends: 262 [2022-03-15 21:34:52,425 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 15 SyntacticMatches, 7 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-03-15 21:34:52,427 INFO L933 BasicCegarLoop]: 4 mSDtfsCounter, 4 mSDsluCounter, 17 mSDsCounter, 0 mSdLazyCounter, 33 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4 SdHoareTripleChecker+Valid, 8 SdHoareTripleChecker+Invalid, 33 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 33 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-03-15 21:34:52,428 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [4 Valid, 8 Invalid, 33 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 33 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-03-15 21:34:52,430 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 262 states. [2022-03-15 21:34:52,452 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 262 to 262. [2022-03-15 21:34:52,453 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 262 states, 261 states have (on average 3.0919540229885056) internal successors, (807), 261 states have internal predecessors, (807), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:52,454 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 262 states to 262 states and 807 transitions. [2022-03-15 21:34:52,454 INFO L78 Accepts]: Start accepts. Automaton has 262 states and 807 transitions. Word has length 17 [2022-03-15 21:34:52,454 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:34:52,454 INFO L470 AbstractCegarLoop]: Abstraction has 262 states and 807 transitions. [2022-03-15 21:34:52,454 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 6.666666666666667) internal successors, (20), 2 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:52,454 INFO L276 IsEmpty]: Start isEmpty. Operand 262 states and 807 transitions. [2022-03-15 21:34:52,458 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2022-03-15 21:34:52,458 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:34:52,458 INFO L514 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:34:52,458 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2022-03-15 21:34:52,458 INFO L402 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION (and 1 more)] === [2022-03-15 21:34:52,459 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:34:52,459 INFO L85 PathProgramCache]: Analyzing trace with hash 937756758, now seen corresponding path program 1 times [2022-03-15 21:34:52,460 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:34:52,460 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [433164228] [2022-03-15 21:34:52,460 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:34:52,460 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:34:52,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:34:52,484 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-03-15 21:34:52,484 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:34:52,484 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [433164228] [2022-03-15 21:34:52,484 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [433164228] provided 1 perfect and 0 imperfect interpolant sequences [2022-03-15 21:34:52,484 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-03-15 21:34:52,484 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-03-15 21:34:52,484 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [793354714] [2022-03-15 21:34:52,484 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:34:52,486 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:34:52,494 INFO L252 McrAutomatonBuilder]: Finished intersection with 75 states and 153 transitions. [2022-03-15 21:34:52,494 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:34:52,775 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 1 new interpolants: [2459#(<= back1 front1)] [2022-03-15 21:34:52,775 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-03-15 21:34:52,775 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:34:52,775 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-03-15 21:34:52,776 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2022-03-15 21:34:52,776 INFO L87 Difference]: Start difference. First operand 262 states and 807 transitions. Second operand has 4 states, 4 states have (on average 7.5) internal successors, (30), 3 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:52,805 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:34:52,805 INFO L93 Difference]: Finished difference Result 299 states and 896 transitions. [2022-03-15 21:34:52,805 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-03-15 21:34:52,806 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 7.5) internal successors, (30), 3 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 20 [2022-03-15 21:34:52,806 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:34:52,807 INFO L225 Difference]: With dead ends: 299 [2022-03-15 21:34:52,807 INFO L226 Difference]: Without dead ends: 284 [2022-03-15 21:34:52,808 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 56 GetRequests, 54 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2022-03-15 21:34:52,810 INFO L933 BasicCegarLoop]: 4 mSDtfsCounter, 8 mSDsluCounter, 18 mSDsCounter, 0 mSdLazyCounter, 34 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 8 SdHoareTripleChecker+Valid, 8 SdHoareTripleChecker+Invalid, 35 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 34 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-03-15 21:34:52,811 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [8 Valid, 8 Invalid, 35 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 34 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-03-15 21:34:52,812 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 284 states. [2022-03-15 21:34:52,816 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 284 to 284. [2022-03-15 21:34:52,817 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 284 states, 283 states have (on average 3.0424028268551235) internal successors, (861), 283 states have internal predecessors, (861), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:52,817 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 284 states to 284 states and 861 transitions. [2022-03-15 21:34:52,818 INFO L78 Accepts]: Start accepts. Automaton has 284 states and 861 transitions. Word has length 20 [2022-03-15 21:34:52,818 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:34:52,818 INFO L470 AbstractCegarLoop]: Abstraction has 284 states and 861 transitions. [2022-03-15 21:34:52,818 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 7.5) internal successors, (30), 3 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:52,818 INFO L276 IsEmpty]: Start isEmpty. Operand 284 states and 861 transitions. [2022-03-15 21:34:52,819 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2022-03-15 21:34:52,819 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:34:52,819 INFO L514 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:34:52,819 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3 [2022-03-15 21:34:52,819 INFO L402 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION (and 1 more)] === [2022-03-15 21:34:52,821 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:34:52,822 INFO L85 PathProgramCache]: Analyzing trace with hash -2130678481, now seen corresponding path program 1 times [2022-03-15 21:34:52,822 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:34:52,822 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [484570213] [2022-03-15 21:34:52,822 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:34:52,822 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:34:52,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:34:52,983 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:34:52,984 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:34:52,984 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [484570213] [2022-03-15 21:34:52,984 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [484570213] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:34:52,984 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1507640371] [2022-03-15 21:34:52,984 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:34:52,984 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:34:52,985 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:34:52,999 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:34:53,020 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-03-15 21:34:53,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:34:53,052 INFO L263 TraceCheckSpWp]: Trace formula consists of 87 conjuncts, 15 conjunts are in the unsatisfiable core [2022-03-15 21:34:53,056 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:34:53,239 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2022-03-15 21:34:53,295 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2022-03-15 21:34:53,351 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:34:53,351 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:34:53,384 INFO L353 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-03-15 21:34:53,384 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 18 treesize of output 22 [2022-03-15 21:34:53,451 INFO L353 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-03-15 21:34:53,453 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 21 treesize of output 25 [2022-03-15 21:34:53,562 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:34:53,562 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1507640371] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:34:53,562 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:34:53,563 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9] total 20 [2022-03-15 21:34:53,563 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [354988516] [2022-03-15 21:34:53,564 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:34:53,565 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:34:53,575 INFO L252 McrAutomatonBuilder]: Finished intersection with 97 states and 207 transitions. [2022-03-15 21:34:53,575 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:34:55,639 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 13 new interpolants: [3480#(or (<= (+ d2 (select queue2 front2)) (* 2 W)) (not v_assert)), 3481#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (<= (+ 2 d2) (* 2 W))) (or (not v_assert) (= (+ (- 1) temp1) 0))), 3482#(and (or (<= (+ d2 temp2) (* 2 W)) v_assert) (or (<= (+ d2 temp2) (* 2 W)) (< 0 w))), 3486#(and (or (not v_assert) (= (+ (- 1) temp1) 0) (< 0 w)) (or (not v_assert) (< 0 w) (<= (+ 2 d2) (* 2 W))) (or (not v_assert) (< 0 w) (= front2 back2))), 3484#(and (or (= (+ (- 1) temp1) 0) (< 0 w)) (or (< 0 w) (= front2 back2)) (or v_assert (<= (+ 2 d2) (* 2 W))) (or (< 0 w) (<= (+ 2 d2) (* 2 W))) (or v_assert (= front2 back2)) (or v_assert (= (+ (- 1) temp1) 0))), 3474#(and (or (<= d2 (* 2 W)) v_assert) (or (<= d2 (* 2 W)) (< 0 w))), 3485#(or (<= (+ d2 (select queue2 front2)) (* 2 W)) (not v_assert) (< 0 w)), 3477#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (<= (+ 2 d2) (* 2 W))) (or (not v_assert) (= (select queue1 front1) 1))), 3476#(and (or (<= back1 front1) (not v_assert) (= (+ (- 1) (select queue1 front1)) 0)) (or (<= back1 front1) (not v_assert) (= front2 back2)) (or (<= back1 front1) (not v_assert) (<= (+ 2 d2) (* 2 W)))), 3475#(and (or (<= back1 front1) (= front2 back2)) (or (<= back1 front1) (= (+ (- 1) (select queue1 front1)) 0)) (or (<= back1 front1) (<= (+ 2 d2) (* 2 W)))), 3483#(and (or (<= (+ d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ d2 (select queue2 front2)) (* 2 W)) v_assert)), 3479#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (= front1 back1)) (or (not v_assert) (<= d2 0)) (or (not v_assert) (= (+ (* (- 1) w) W) 0))), 3478#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (<= (+ 2 d2) (* 2 w))) (or (not v_assert) (= front1 back1)) (or (not v_assert) (= (+ (* (- 1) w) W) 0)))] [2022-03-15 21:34:55,640 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 23 states [2022-03-15 21:34:55,640 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:34:55,641 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2022-03-15 21:34:55,641 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=140, Invalid=982, Unknown=0, NotChecked=0, Total=1122 [2022-03-15 21:34:55,642 INFO L87 Difference]: Start difference. First operand 284 states and 861 transitions. Second operand has 23 states, 23 states have (on average 4.260869565217392) internal successors, (98), 22 states have internal predecessors, (98), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:56,946 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:34:56,946 INFO L93 Difference]: Finished difference Result 612 states and 1890 transitions. [2022-03-15 21:34:56,946 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2022-03-15 21:34:56,946 INFO L78 Accepts]: Start accepts. Automaton has has 23 states, 23 states have (on average 4.260869565217392) internal successors, (98), 22 states have internal predecessors, (98), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 22 [2022-03-15 21:34:56,946 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:34:56,949 INFO L225 Difference]: With dead ends: 612 [2022-03-15 21:34:56,949 INFO L226 Difference]: Without dead ends: 540 [2022-03-15 21:34:56,950 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 150 GetRequests, 88 SyntacticMatches, 5 SemanticMatches, 57 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 856 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=473, Invalid=2949, Unknown=0, NotChecked=0, Total=3422 [2022-03-15 21:34:56,950 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 336 mSDsluCounter, 288 mSDsCounter, 0 mSdLazyCounter, 875 mSolverCounterSat, 139 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 336 SdHoareTripleChecker+Valid, 1 SdHoareTripleChecker+Invalid, 1014 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 139 IncrementalHoareTripleChecker+Valid, 875 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-03-15 21:34:56,950 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [336 Valid, 1 Invalid, 1014 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [139 Valid, 875 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2022-03-15 21:34:56,951 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 540 states. [2022-03-15 21:34:56,956 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 540 to 347. [2022-03-15 21:34:56,957 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 347 states, 346 states have (on average 3.11271676300578) internal successors, (1077), 346 states have internal predecessors, (1077), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:56,958 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 347 states to 347 states and 1077 transitions. [2022-03-15 21:34:56,958 INFO L78 Accepts]: Start accepts. Automaton has 347 states and 1077 transitions. Word has length 22 [2022-03-15 21:34:56,958 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:34:56,958 INFO L470 AbstractCegarLoop]: Abstraction has 347 states and 1077 transitions. [2022-03-15 21:34:56,959 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 23 states, 23 states have (on average 4.260869565217392) internal successors, (98), 22 states have internal predecessors, (98), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:56,959 INFO L276 IsEmpty]: Start isEmpty. Operand 347 states and 1077 transitions. [2022-03-15 21:34:56,959 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2022-03-15 21:34:56,959 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:34:56,960 INFO L514 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:34:56,978 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Forceful destruction successful, exit code 0 [2022-03-15 21:34:57,175 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4,2 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:34:57,176 INFO L402 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION (and 1 more)] === [2022-03-15 21:34:57,176 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:34:57,176 INFO L85 PathProgramCache]: Analyzing trace with hash 934593077, now seen corresponding path program 2 times [2022-03-15 21:34:57,177 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:34:57,177 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [317449257] [2022-03-15 21:34:57,177 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:34:57,177 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:34:57,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:34:57,204 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-03-15 21:34:57,204 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:34:57,204 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [317449257] [2022-03-15 21:34:57,204 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [317449257] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:34:57,204 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1363349463] [2022-03-15 21:34:57,204 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-03-15 21:34:57,204 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:34:57,205 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:34:57,205 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:34:57,206 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-03-15 21:34:57,238 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-03-15 21:34:57,238 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:34:57,239 INFO L263 TraceCheckSpWp]: Trace formula consists of 95 conjuncts, 4 conjunts are in the unsatisfiable core [2022-03-15 21:34:57,240 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:34:57,271 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-03-15 21:34:57,271 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-03-15 21:34:57,272 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1363349463] provided 1 perfect and 0 imperfect interpolant sequences [2022-03-15 21:34:57,273 INFO L191 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-03-15 21:34:57,273 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [4] total 4 [2022-03-15 21:34:57,273 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [144796766] [2022-03-15 21:34:57,273 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:34:57,276 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:34:57,289 INFO L252 McrAutomatonBuilder]: Finished intersection with 112 states and 237 transitions. [2022-03-15 21:34:57,289 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:34:57,742 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 0 new interpolants: [] [2022-03-15 21:34:57,742 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-03-15 21:34:57,742 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:34:57,743 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-03-15 21:34:57,743 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2022-03-15 21:34:57,743 INFO L87 Difference]: Start difference. First operand 347 states and 1077 transitions. Second operand has 4 states, 4 states have (on average 8.0) internal successors, (32), 3 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:57,779 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:34:57,779 INFO L93 Difference]: Finished difference Result 834 states and 2577 transitions. [2022-03-15 21:34:57,779 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-03-15 21:34:57,779 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 8.0) internal successors, (32), 3 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 25 [2022-03-15 21:34:57,779 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:34:57,783 INFO L225 Difference]: With dead ends: 834 [2022-03-15 21:34:57,783 INFO L226 Difference]: Without dead ends: 825 [2022-03-15 21:34:57,783 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 114 GetRequests, 111 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2022-03-15 21:34:57,783 INFO L933 BasicCegarLoop]: 4 mSDtfsCounter, 33 mSDsluCounter, 34 mSDsCounter, 0 mSdLazyCounter, 47 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 33 SdHoareTripleChecker+Valid, 12 SdHoareTripleChecker+Invalid, 49 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 47 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-03-15 21:34:57,784 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [33 Valid, 12 Invalid, 49 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 47 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-03-15 21:34:57,785 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 825 states. [2022-03-15 21:34:57,794 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 825 to 700. [2022-03-15 21:34:57,795 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 700 states, 699 states have (on average 3.284692417739628) internal successors, (2296), 699 states have internal predecessors, (2296), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:57,797 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 700 states to 700 states and 2296 transitions. [2022-03-15 21:34:57,797 INFO L78 Accepts]: Start accepts. Automaton has 700 states and 2296 transitions. Word has length 25 [2022-03-15 21:34:57,797 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:34:57,798 INFO L470 AbstractCegarLoop]: Abstraction has 700 states and 2296 transitions. [2022-03-15 21:34:57,798 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 8.0) internal successors, (32), 3 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:57,798 INFO L276 IsEmpty]: Start isEmpty. Operand 700 states and 2296 transitions. [2022-03-15 21:34:57,799 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2022-03-15 21:34:57,799 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:34:57,799 INFO L514 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:34:57,819 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2022-03-15 21:34:58,015 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable5 [2022-03-15 21:34:58,015 INFO L402 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION (and 1 more)] === [2022-03-15 21:34:58,015 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:34:58,016 INFO L85 PathProgramCache]: Analyzing trace with hash 1026519232, now seen corresponding path program 3 times [2022-03-15 21:34:58,016 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:34:58,016 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1796056010] [2022-03-15 21:34:58,016 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:34:58,017 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:34:58,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:34:58,041 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 6 proven. 2 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2022-03-15 21:34:58,042 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:34:58,042 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1796056010] [2022-03-15 21:34:58,042 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1796056010] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:34:58,042 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [958704402] [2022-03-15 21:34:58,042 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-03-15 21:34:58,042 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:34:58,042 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:34:58,043 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:34:58,044 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-03-15 21:34:58,074 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2022-03-15 21:34:58,074 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:34:58,074 INFO L263 TraceCheckSpWp]: Trace formula consists of 107 conjuncts, 4 conjunts are in the unsatisfiable core [2022-03-15 21:34:58,075 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:34:58,106 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 6 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-03-15 21:34:58,107 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:34:58,143 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 6 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-03-15 21:34:58,143 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [958704402] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:34:58,143 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:34:58,143 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 3, 3] total 4 [2022-03-15 21:34:58,143 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1681172042] [2022-03-15 21:34:58,143 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:34:58,147 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:34:58,169 INFO L252 McrAutomatonBuilder]: Finished intersection with 181 states and 427 transitions. [2022-03-15 21:34:58,169 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:34:58,921 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 0 new interpolants: [] [2022-03-15 21:34:58,921 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-03-15 21:34:58,921 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:34:58,922 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-03-15 21:34:58,922 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2022-03-15 21:34:58,922 INFO L87 Difference]: Start difference. First operand 700 states and 2296 transitions. Second operand has 5 states, 5 states have (on average 8.4) internal successors, (42), 4 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:58,960 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:34:58,960 INFO L93 Difference]: Finished difference Result 2015 states and 6469 transitions. [2022-03-15 21:34:58,961 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-03-15 21:34:58,961 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 8.4) internal successors, (42), 4 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 28 [2022-03-15 21:34:58,961 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:34:58,969 INFO L225 Difference]: With dead ends: 2015 [2022-03-15 21:34:58,969 INFO L226 Difference]: Without dead ends: 1882 [2022-03-15 21:34:58,969 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 210 GetRequests, 191 SyntacticMatches, 16 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 30 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2022-03-15 21:34:58,970 INFO L933 BasicCegarLoop]: 4 mSDtfsCounter, 36 mSDsluCounter, 43 mSDsCounter, 0 mSdLazyCounter, 59 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 36 SdHoareTripleChecker+Valid, 12 SdHoareTripleChecker+Invalid, 62 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 59 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-03-15 21:34:58,970 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [36 Valid, 12 Invalid, 62 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 59 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-03-15 21:34:58,973 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1882 states. [2022-03-15 21:34:58,997 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1882 to 1744. [2022-03-15 21:34:59,000 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1744 states, 1743 states have (on average 3.316695352839931) internal successors, (5781), 1743 states have internal predecessors, (5781), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:59,006 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1744 states to 1744 states and 5781 transitions. [2022-03-15 21:34:59,006 INFO L78 Accepts]: Start accepts. Automaton has 1744 states and 5781 transitions. Word has length 28 [2022-03-15 21:34:59,006 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:34:59,006 INFO L470 AbstractCegarLoop]: Abstraction has 1744 states and 5781 transitions. [2022-03-15 21:34:59,007 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 8.4) internal successors, (42), 4 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:34:59,007 INFO L276 IsEmpty]: Start isEmpty. Operand 1744 states and 5781 transitions. [2022-03-15 21:34:59,010 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2022-03-15 21:34:59,010 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:34:59,010 INFO L514 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:34:59,029 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2022-03-15 21:34:59,226 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6,4 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:34:59,227 INFO L402 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION (and 1 more)] === [2022-03-15 21:34:59,227 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:34:59,227 INFO L85 PathProgramCache]: Analyzing trace with hash -1812629169, now seen corresponding path program 4 times [2022-03-15 21:34:59,228 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:34:59,228 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1525967608] [2022-03-15 21:34:59,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:34:59,228 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:34:59,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:34:59,491 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:34:59,492 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:34:59,492 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1525967608] [2022-03-15 21:34:59,492 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1525967608] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:34:59,492 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1613585433] [2022-03-15 21:34:59,492 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-03-15 21:34:59,492 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:34:59,492 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:34:59,493 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:34:59,494 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2022-03-15 21:34:59,522 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-03-15 21:34:59,522 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:34:59,523 INFO L263 TraceCheckSpWp]: Trace formula consists of 115 conjuncts, 29 conjunts are in the unsatisfiable core [2022-03-15 21:34:59,524 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:34:59,889 INFO L353 Elim1Store]: treesize reduction 9, result has 10.0 percent of original size [2022-03-15 21:34:59,889 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 31 treesize of output 19 [2022-03-15 21:34:59,964 INFO L353 Elim1Store]: treesize reduction 9, result has 10.0 percent of original size [2022-03-15 21:34:59,964 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 13 [2022-03-15 21:35:00,019 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:35:00,019 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:35:00,259 INFO L353 Elim1Store]: treesize reduction 24, result has 60.7 percent of original size [2022-03-15 21:35:00,260 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 34 treesize of output 58 [2022-03-15 21:35:00,441 INFO L353 Elim1Store]: treesize reduction 24, result has 60.7 percent of original size [2022-03-15 21:35:00,441 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 34 treesize of output 58 [2022-03-15 21:35:00,665 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:35:00,665 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1613585433] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:35:00,665 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:35:00,665 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14] total 35 [2022-03-15 21:35:00,665 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [589288043] [2022-03-15 21:35:00,665 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:35:00,667 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:35:00,702 INFO L252 McrAutomatonBuilder]: Finished intersection with 231 states and 569 transitions. [2022-03-15 21:35:00,702 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:35:10,704 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 34 new interpolants: [13064#(and (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (= (+ (- 1) (* (- 1) front1) back1) 0)) (or (not v_assert) (<= (+ 2 d2 (* 2 w)) (* 2 W))) (or (not v_assert) (= (+ back2 (* (- 1) front2)) 0))), 13060#(and (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (+ back2 1) (+ front2 1))) (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))))), 13042#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (<= (+ 2 d2 temp2) (* 2 W))) (or (not v_assert) (= (select queue1 front1) 1))), 13036#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= (+ 2 d2) (* 2 W)))), 13052#(or (not v_assert) (<= (+ d2 temp2 (select queue2 front2)) (* 2 W)) (< 0 w)), 13066#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (<= (+ d2 temp2 (* 2 w)) (* 2 W))) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 13062#(and (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= (+ 2 d2 (* 2 w)) (* 2 W))) (or (not v_assert) (= (+ back2 (* (- 1) front2)) 0)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 13047#(and (or (<= (+ d2 temp2) (* 2 W)) v_assert) (or (<= (+ d2 temp2) (* 2 W)) (< 0 w))), 13049#(or (<= (+ d2 (select queue2 front2)) (* 2 W)) (not v_assert) (< 0 w)), 13056#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (<= (+ 2 d2 temp2) (* 2 W))) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 13041#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (<= (+ 2 d2) (* 2 W))) (or (not v_assert) (= (select queue1 front1) 1))), 13063#(and (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (< front1 back1)) (not (< front2 (+ back2 1))) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (not (< front2 (+ back2 1))) (= (+ back2 1) (+ front2 1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (= (+ (- 1) (* (- 1) front1) back1) 0) (not (< front2 (+ back2 1))) (not (= (+ (select queue1 front1) 1) (select queue2 back2))))), 13045#(and (or (not v_assert) (= back2 (+ front2 1)) (not (< front2 back2))) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (not (< front2 back2)) (= (select queue1 front1) 1))), 13057#(and (or (not v_assert) (= back2 (+ front2 1)) (not (< front2 back2))) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0) (not (< front2 back2))) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (< front2 back2)))), 13050#(and (or (< 0 w) (= front2 back2)) (or v_assert (<= (+ 2 d2) (* 2 W))) (or (= temp1 1) (< 0 w)) (or (= temp1 1) v_assert) (or (< 0 w) (<= (+ 2 d2) (* 2 W))) (or v_assert (= front2 back2))), 13065#(and (or (not v_assert) (= front2 back2)) (or (<= (+ d2 (* 2 w)) (* 2 W)) (not v_assert)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 13053#(and (or (not v_assert) (< 0 w) (<= (+ 2 d2 temp2) (* 2 W))) (or (not v_assert) (= temp1 1) (< 0 w)) (or (not v_assert) (< 0 w) (= front2 back2))), 13061#(and (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (+ back2 1) (+ front2 1))) (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (+ (* (- 1) front1) back1) 0)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))))), 13039#(and (or (<= back1 front1) (not v_assert) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (= front2 back2)) (or (<= back1 front1) (not v_assert) (<= (+ 2 d2) (* 2 W)))), 13048#(and (or (<= (+ d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ d2 (select queue2 front2)) (* 2 W)) v_assert)), 13040#(and (or (<= back1 front1) (not v_assert) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (= front2 back2)) (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 temp2) (* 2 W)))), 13054#(and (or (not v_assert) (= back2 (+ front2 1)) (< 0 w) (not (< front2 back2))) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (< 0 w) (not (< front2 back2))) (or (not v_assert) (= temp1 1) (< 0 w) (not (< front2 back2)))), 13059#(and (or (<= back1 front1) (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (+ back2 1) (+ front2 1))) (or (<= back1 front1) (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))))), 13043#(and (or (not v_assert) (= back2 (+ front2 1)) (not (< front2 back2))) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (= temp1 1) (not (< front2 back2)))), 13051#(and (or (not v_assert) (< 0 w) (<= (+ 2 d2) (* 2 W))) (or (not v_assert) (= temp1 1) (< 0 w)) (or (not v_assert) (< 0 w) (= front2 back2))), 13044#(and (or (<= back1 front1) (not v_assert) (= back2 (+ front2 1)) (not (< front2 back2))) (or (<= back1 front1) (not v_assert) (not (< front2 back2)) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (< front2 back2)))), 13058#(and (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 13067#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (= front1 back1)) (or (not v_assert) (= W w)) (or (not v_assert) (<= d2 0))), 13055#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (<= (+ 2 d2) (* 2 W))) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 13035#(or (not v_assert) (<= (+ d2 temp2 (select queue2 front2)) (* 2 W))), 13046#(and (or (<= d2 (* 2 W)) v_assert) (or (<= d2 (* 2 W)) (< 0 w))), 13038#(and (or (<= back1 front1) (= front2 back2)) (or (<= back1 front1) (<= (+ 2 d2) (* 2 W))) (or (<= back1 front1) (= (select queue1 front1) 1))), 13034#(or (<= (+ d2 (select queue2 front2)) (* 2 W)) (not v_assert)), 13037#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= (+ 2 d2 temp2) (* 2 W))))] [2022-03-15 21:35:10,705 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 49 states [2022-03-15 21:35:10,705 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:35:10,705 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2022-03-15 21:35:10,706 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=503, Invalid=4327, Unknown=0, NotChecked=0, Total=4830 [2022-03-15 21:35:10,706 INFO L87 Difference]: Start difference. First operand 1744 states and 5781 transitions. Second operand has 49 states, 49 states have (on average 4.428571428571429) internal successors, (217), 48 states have internal predecessors, (217), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:35:17,232 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:35:17,233 INFO L93 Difference]: Finished difference Result 7901 states and 26974 transitions. [2022-03-15 21:35:17,233 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2022-03-15 21:35:17,233 INFO L78 Accepts]: Start accepts. Automaton has has 49 states, 49 states have (on average 4.428571428571429) internal successors, (217), 48 states have internal predecessors, (217), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 30 [2022-03-15 21:35:17,233 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:35:17,265 INFO L225 Difference]: With dead ends: 7901 [2022-03-15 21:35:17,265 INFO L226 Difference]: Without dead ends: 7226 [2022-03-15 21:35:17,269 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 361 GetRequests, 149 SyntacticMatches, 55 SemanticMatches, 157 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10066 ImplicationChecksByTransitivity, 7.9s TimeCoverageRelationStatistics Valid=3199, Invalid=21923, Unknown=0, NotChecked=0, Total=25122 [2022-03-15 21:35:17,270 INFO L933 BasicCegarLoop]: 1 mSDtfsCounter, 1067 mSDsluCounter, 921 mSDsCounter, 0 mSdLazyCounter, 3364 mSolverCounterSat, 700 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1067 SdHoareTripleChecker+Valid, 3 SdHoareTripleChecker+Invalid, 4064 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 700 IncrementalHoareTripleChecker+Valid, 3364 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.8s IncrementalHoareTripleChecker+Time [2022-03-15 21:35:17,270 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [1067 Valid, 3 Invalid, 4064 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [700 Valid, 3364 Invalid, 0 Unknown, 0 Unchecked, 1.8s Time] [2022-03-15 21:35:17,278 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7226 states. [2022-03-15 21:35:17,337 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7226 to 2087. [2022-03-15 21:35:17,341 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2087 states, 2086 states have (on average 3.3072866730584853) internal successors, (6899), 2086 states have internal predecessors, (6899), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:35:17,346 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2087 states to 2087 states and 6899 transitions. [2022-03-15 21:35:17,346 INFO L78 Accepts]: Start accepts. Automaton has 2087 states and 6899 transitions. Word has length 30 [2022-03-15 21:35:17,348 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:35:17,348 INFO L470 AbstractCegarLoop]: Abstraction has 2087 states and 6899 transitions. [2022-03-15 21:35:17,348 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 49 states, 49 states have (on average 4.428571428571429) internal successors, (217), 48 states have internal predecessors, (217), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:35:17,348 INFO L276 IsEmpty]: Start isEmpty. Operand 2087 states and 6899 transitions. [2022-03-15 21:35:17,351 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2022-03-15 21:35:17,351 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:35:17,352 INFO L514 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:35:17,380 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2022-03-15 21:35:17,567 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7,5 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:35:17,567 INFO L402 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION (and 1 more)] === [2022-03-15 21:35:17,568 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:35:17,568 INFO L85 PathProgramCache]: Analyzing trace with hash 937043521, now seen corresponding path program 5 times [2022-03-15 21:35:17,568 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:35:17,568 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [492203642] [2022-03-15 21:35:17,568 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:35:17,568 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:35:17,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:35:17,762 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:35:17,762 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:35:17,763 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [492203642] [2022-03-15 21:35:17,763 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [492203642] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:35:17,763 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1953674318] [2022-03-15 21:35:17,763 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-03-15 21:35:17,763 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:35:17,763 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:35:17,764 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:35:17,765 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2022-03-15 21:35:17,796 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) [2022-03-15 21:35:17,796 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:35:17,797 INFO L263 TraceCheckSpWp]: Trace formula consists of 115 conjuncts, 34 conjunts are in the unsatisfiable core [2022-03-15 21:35:17,798 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:35:18,056 INFO L353 Elim1Store]: treesize reduction 9, result has 10.0 percent of original size [2022-03-15 21:35:18,056 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 31 treesize of output 19 [2022-03-15 21:35:18,183 INFO L353 Elim1Store]: treesize reduction 9, result has 10.0 percent of original size [2022-03-15 21:35:18,183 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 13 [2022-03-15 21:35:18,247 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:35:18,248 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:35:18,411 INFO L353 Elim1Store]: treesize reduction 24, result has 60.7 percent of original size [2022-03-15 21:35:18,411 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 34 treesize of output 58 [2022-03-15 21:35:18,625 INFO L353 Elim1Store]: treesize reduction 24, result has 60.7 percent of original size [2022-03-15 21:35:18,626 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 34 treesize of output 58 [2022-03-15 21:35:18,845 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:35:18,845 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1953674318] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:35:18,845 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:35:18,845 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14] total 33 [2022-03-15 21:35:18,845 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [167125569] [2022-03-15 21:35:18,845 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:35:18,848 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:35:18,872 INFO L252 McrAutomatonBuilder]: Finished intersection with 174 states and 397 transitions. [2022-03-15 21:35:18,872 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:35:24,826 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 22 new interpolants: [25535#(and (or (<= (+ d2 temp2) (* 2 W)) v_assert) (or (<= (+ d2 temp2) (* 2 W)) (< 0 w))), 25543#(and (or (<= back1 front1) (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (<= back1 front1) (not v_assert) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1)))) (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1))))), 25529#(or (not v_assert) (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))), 25532#(and (or (<= back1 front1) (not v_assert) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W))) (or (<= back1 front1) (not v_assert) (<= back2 (+ front2 1))) (or (<= back1 front1) (not v_assert) (<= (+ front2 1) back2))), 25530#(and (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)))), 25533#(and (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)))), 25548#(and (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= (+ 2 d2 (* 2 w)) (* 2 W))) (or (not v_assert) (= (+ back2 (* (- 1) front2)) 0)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 25550#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (= front1 back1)) (or (not v_assert) (= W w)) (or (not v_assert) (<= d2 0))), 25549#(and (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (= (+ (- 1) (* (- 1) front1) back1) 0)) (or (not v_assert) (<= (+ 2 d2 (* 2 w)) (* 2 W))) (or (not v_assert) (= (+ back2 (* (- 1) front2)) 0))), 25546#(and (or (not v_assert) (not (< front1 back1)) (= (+ (- 1) (* (- 1) front1) back1) 0) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (<= front2 back2) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (<= back2 front2) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (< front1 back1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2))))), 25531#(and (or (<= back1 front1) (<= (+ 2 d2 (select queue2 front2)) (* 2 W))) (or (<= back1 front1) (<= (+ front2 1) back2)) (or (<= back1 front1) (<= back2 (+ front2 1))) (or (<= back1 front1) (= (select queue1 front1) 1))), 25536#(and (or (<= (+ d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ d2 (select queue2 front2)) (* 2 W)) v_assert)), 25547#(and (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 25541#(and (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (not v_assert) (<= back2 (+ front2 1)) (< 0 w)) (or (not v_assert) (= temp1 1) (< 0 w)) (or (not v_assert) (<= (+ front2 1) back2) (< 0 w))), 25537#(and (or (<= (+ d2 temp2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ d2 temp2 (select queue2 front2)) (* 2 W)) v_assert)), 25538#(and (or (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) v_assert)), 25534#(and (or (<= d2 (* 2 W)) v_assert) (or (<= d2 (* 2 W)) (< 0 w))), 25542#(and (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W))) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 25539#(or (not v_assert) (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w)), 25544#(and (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (not v_assert) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1))))), 25545#(and (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (= (+ (* (- 1) front1) back1) 0))), 25540#(and (or (<= back2 (+ front2 1)) (< 0 w)) (or (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or v_assert (<= (+ front2 1) back2)) (or (<= (+ front2 1) back2) (< 0 w)) (or (<= back2 (+ front2 1)) v_assert) (or (= temp1 1) (< 0 w)) (or (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) v_assert) (or (= temp1 1) v_assert))] [2022-03-15 21:35:24,827 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 37 states [2022-03-15 21:35:24,827 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:35:24,827 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2022-03-15 21:35:24,828 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=276, Invalid=2804, Unknown=0, NotChecked=0, Total=3080 [2022-03-15 21:35:24,828 INFO L87 Difference]: Start difference. First operand 2087 states and 6899 transitions. Second operand has 37 states, 37 states have (on average 4.4324324324324325) internal successors, (164), 36 states have internal predecessors, (164), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:35:28,896 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:35:28,896 INFO L93 Difference]: Finished difference Result 6420 states and 21502 transitions. [2022-03-15 21:35:28,896 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2022-03-15 21:35:28,896 INFO L78 Accepts]: Start accepts. Automaton has has 37 states, 37 states have (on average 4.4324324324324325) internal successors, (164), 36 states have internal predecessors, (164), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 30 [2022-03-15 21:35:28,897 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:35:28,932 INFO L225 Difference]: With dead ends: 6420 [2022-03-15 21:35:28,932 INFO L226 Difference]: Without dead ends: 6320 [2022-03-15 21:35:28,934 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 268 GetRequests, 146 SyntacticMatches, 15 SemanticMatches, 107 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3766 ImplicationChecksByTransitivity, 4.5s TimeCoverageRelationStatistics Valid=1390, Invalid=10382, Unknown=0, NotChecked=0, Total=11772 [2022-03-15 21:35:28,935 INFO L933 BasicCegarLoop]: 1 mSDtfsCounter, 522 mSDsluCounter, 810 mSDsCounter, 0 mSdLazyCounter, 2486 mSolverCounterSat, 194 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.8s Time, 0 mProtectedPredicate, 0 mProtectedAction, 522 SdHoareTripleChecker+Valid, 3 SdHoareTripleChecker+Invalid, 2680 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 194 IncrementalHoareTripleChecker+Valid, 2486 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.0s IncrementalHoareTripleChecker+Time [2022-03-15 21:35:28,936 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [522 Valid, 3 Invalid, 2680 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [194 Valid, 2486 Invalid, 0 Unknown, 0 Unchecked, 1.0s Time] [2022-03-15 21:35:28,943 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6320 states. [2022-03-15 21:35:29,007 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6320 to 2398. [2022-03-15 21:35:29,012 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2398 states, 2397 states have (on average 3.292866082603254) internal successors, (7893), 2397 states have internal predecessors, (7893), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:35:29,020 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2398 states to 2398 states and 7893 transitions. [2022-03-15 21:35:29,020 INFO L78 Accepts]: Start accepts. Automaton has 2398 states and 7893 transitions. Word has length 30 [2022-03-15 21:35:29,020 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:35:29,020 INFO L470 AbstractCegarLoop]: Abstraction has 2398 states and 7893 transitions. [2022-03-15 21:35:29,020 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 37 states, 37 states have (on average 4.4324324324324325) internal successors, (164), 36 states have internal predecessors, (164), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:35:29,021 INFO L276 IsEmpty]: Start isEmpty. Operand 2398 states and 7893 transitions. [2022-03-15 21:35:29,024 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2022-03-15 21:35:29,025 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:35:29,025 INFO L514 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:35:29,043 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Forceful destruction successful, exit code 0 [2022-03-15 21:35:29,241 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8,6 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:35:29,241 INFO L402 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION (and 1 more)] === [2022-03-15 21:35:29,242 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:35:29,242 INFO L85 PathProgramCache]: Analyzing trace with hash -1254825637, now seen corresponding path program 6 times [2022-03-15 21:35:29,242 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:35:29,242 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [847966306] [2022-03-15 21:35:29,243 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:35:29,243 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:35:29,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:35:29,429 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:35:29,429 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:35:29,429 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [847966306] [2022-03-15 21:35:29,429 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [847966306] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:35:29,429 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1517957414] [2022-03-15 21:35:29,430 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-03-15 21:35:29,430 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:35:29,430 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:35:29,431 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:35:29,431 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2022-03-15 21:35:29,464 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2022-03-15 21:35:29,464 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:35:29,465 INFO L263 TraceCheckSpWp]: Trace formula consists of 115 conjuncts, 29 conjunts are in the unsatisfiable core [2022-03-15 21:35:29,466 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:35:29,710 INFO L353 Elim1Store]: treesize reduction 9, result has 10.0 percent of original size [2022-03-15 21:35:29,711 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 31 treesize of output 19 [2022-03-15 21:35:29,859 INFO L353 Elim1Store]: treesize reduction 9, result has 10.0 percent of original size [2022-03-15 21:35:29,859 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 13 [2022-03-15 21:35:29,919 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:35:29,919 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:35:30,027 INFO L353 Elim1Store]: treesize reduction 24, result has 60.7 percent of original size [2022-03-15 21:35:30,027 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 34 treesize of output 58 [2022-03-15 21:35:30,271 INFO L353 Elim1Store]: treesize reduction 24, result has 60.7 percent of original size [2022-03-15 21:35:30,272 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 34 treesize of output 58 [2022-03-15 21:35:30,450 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:35:30,450 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1517957414] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:35:30,450 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:35:30,451 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14] total 34 [2022-03-15 21:35:30,451 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1578162036] [2022-03-15 21:35:30,451 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:35:30,453 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:35:30,485 INFO L252 McrAutomatonBuilder]: Finished intersection with 203 states and 481 transitions. [2022-03-15 21:35:30,485 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:35:37,008 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 30 new interpolants: [37098#(or (<= back1 front1) (<= (+ d2 (select queue2 front2)) (* 2 W)) (not v_assert) (< 0 w) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))), 37097#(and (or (<= back1 front1) (<= (+ d2 (select queue2 front2)) (* 2 W)) (< 0 w) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (<= back1 front1) (<= (+ d2 (select queue2 front2)) (* 2 W)) v_assert (not (= (+ (select queue1 front1) 1) (select queue2 back2))))), 37109#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (<= back1 (+ front1 1))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ front1 1) back1)) (or (not v_assert) (<= (+ d2 4) (* 2 W)))), 37093#(and (or (<= d2 (* 2 W)) v_assert) (or (<= d2 (* 2 W)) (< 0 w))), 37085#(or (<= back1 front1) (<= (+ d2 (select queue2 front2)) (* 2 W)) (not v_assert) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))), 37099#(and (or (<= (+ d2 temp2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ d2 temp2 (select queue2 front2)) (* 2 W)) v_assert)), 37100#(and (or (< 0 w) (= front2 back2)) (or (= temp1 1) (< 0 w)) (or v_assert (<= (+ 2 d2 temp2) (* 2 W))) (or (= temp1 1) v_assert) (or v_assert (= front2 back2)) (or (< 0 w) (<= (+ 2 d2 temp2) (* 2 W)))), 37101#(and (or (<= back1 front1) (< 0 w) (<= (+ 2 d2 temp2) (* 2 W))) (or (<= back1 front1) (< 0 w) (= (select queue1 front1) 1)) (or (<= back1 front1) (< 0 w) (= front2 back2)) (or (<= back1 front1) v_assert (<= (+ 2 d2 temp2) (* 2 W))) (or (<= back1 front1) v_assert (= front2 back2)) (or (<= back1 front1) v_assert (= (select queue1 front1) 1))), 37110#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (<= back1 (+ front1 1))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ 2 d2 (* 2 w)) (* 2 W))) (or (not v_assert) (<= (+ front1 1) back1))), 37088#(and (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)))), 37104#(and (or (<= back2 (+ front2 1)) (< 0 w)) (or (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (< 0 w) (= (select queue1 front1) 1)) (or v_assert (<= (+ front2 1) back2)) (or (<= (+ front2 1) back2) (< 0 w)) (or v_assert (= (select queue1 front1) 1)) (or (<= back2 (+ front2 1)) v_assert) (or (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) v_assert)), 37082#(and (or (not (< front1 back1)) (= (select queue1 (+ front1 1)) 1)) (or (not (< front1 back1)) (<= (+ d2 4) (* 2 W))) (or (not (< front1 back1)) (= front2 back2)) (or (not (< front1 back1)) (= (select queue1 front1) 1))), 37108#(and (or (not v_assert) (< 0 w) (<= (+ d2 4) (* 2 W))) (or (not v_assert) (< 0 w) (= (select queue1 front1) 1)) (or (not v_assert) (= temp1 1) (< 0 w)) (or (not v_assert) (< 0 w) (= front2 back2))), 37087#(and (or (<= back1 front1) (= front2 back2)) (or (<= back1 front1) (<= (+ 2 d2 temp2) (* 2 W))) (or (<= back1 front1) (= (select queue1 front1) 1))), 37107#(and (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (not v_assert) (<= back2 (+ front2 1)) (< 0 w)) (or (not v_assert) (< 0 w) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ front2 1) back2) (< 0 w))), 37105#(and (or (< 0 w) (= (select queue1 front1) 1)) (or (< 0 w) (= front2 back2)) (or (< 0 w) (<= (+ d2 4) (* 2 W))) (or v_assert (= (select queue1 front1) 1)) (or (= temp1 1) (< 0 w)) (or (= temp1 1) v_assert) (or v_assert (<= (+ d2 4) (* 2 W))) (or v_assert (= front2 back2))), 37111#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (= front1 back1)) (or (not v_assert) (= W w)) (or (not v_assert) (<= d2 0))), 37094#(and (or (<= (+ d2 temp2) (* 2 W)) v_assert) (or (<= (+ d2 temp2) (* 2 W)) (< 0 w))), 37092#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (= (select queue1 (+ front1 1)) 1)) (or (not v_assert) (<= (+ d2 4) (* 2 W)))), 37084#(or (<= back1 front1) (<= (+ d2 (select queue2 front2)) (* 2 W)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))), 37086#(and (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)))), 37083#(or (<= (+ d2 (select queue2 front2)) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1)))), 37089#(and (or (<= back1 front1) (not v_assert) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (= front2 back2)) (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 temp2) (* 2 W)))), 37102#(and (or (<= back1 front1) (not v_assert) (< 0 w) (<= (+ 2 d2 temp2) (* 2 W))) (or (<= back1 front1) (not v_assert) (< 0 w) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (< 0 w) (= front2 back2))), 37096#(and (or (<= (+ d2 (select queue2 front2)) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1))) (< 0 w)) (or (<= (+ d2 (select queue2 front2)) (* 2 W)) v_assert (not (= (select queue2 back2) (+ temp1 1))))), 37103#(and (or (<= back2 (+ front2 1)) (< 0 w)) (or (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or v_assert (<= (+ front2 1) back2)) (or (<= (+ front2 1) back2) (< 0 w)) (or (<= back2 (+ front2 1)) v_assert) (or (= temp1 1) (< 0 w)) (or (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) v_assert) (or (= temp1 1) v_assert)), 37106#(and (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (not v_assert) (<= back2 (+ front2 1)) (< 0 w)) (or (not v_assert) (= temp1 1) (< 0 w)) (or (not v_assert) (<= (+ front2 1) back2) (< 0 w))), 37091#(and (or (not v_assert) (not (< front1 back1)) (= (select queue1 (+ front1 1)) 1)) (or (not v_assert) (not (< front1 back1)) (= (select queue1 front1) 1)) (or (not v_assert) (not (< front1 back1)) (= front2 back2)) (or (not v_assert) (not (< front1 back1)) (<= (+ d2 4) (* 2 W)))), 37090#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (= temp1 1)) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ d2 4) (* 2 W)))), 37095#(and (or (<= (+ d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ d2 (select queue2 front2)) (* 2 W)) v_assert))] [2022-03-15 21:35:37,009 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 45 states [2022-03-15 21:35:37,009 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:35:37,009 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2022-03-15 21:35:37,010 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=385, Invalid=3775, Unknown=0, NotChecked=0, Total=4160 [2022-03-15 21:35:37,010 INFO L87 Difference]: Start difference. First operand 2398 states and 7893 transitions. Second operand has 45 states, 45 states have (on average 4.444444444444445) internal successors, (200), 44 states have internal predecessors, (200), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:35:39,729 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:35:39,730 INFO L93 Difference]: Finished difference Result 4234 states and 13966 transitions. [2022-03-15 21:35:39,730 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2022-03-15 21:35:39,730 INFO L78 Accepts]: Start accepts. Automaton has has 45 states, 45 states have (on average 4.444444444444445) internal successors, (200), 44 states have internal predecessors, (200), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 30 [2022-03-15 21:35:39,730 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:35:39,740 INFO L225 Difference]: With dead ends: 4234 [2022-03-15 21:35:39,740 INFO L226 Difference]: Without dead ends: 4178 [2022-03-15 21:35:39,742 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 277 GetRequests, 178 SyntacticMatches, 3 SemanticMatches, 96 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2451 ImplicationChecksByTransitivity, 3.2s TimeCoverageRelationStatistics Valid=1146, Invalid=8360, Unknown=0, NotChecked=0, Total=9506 [2022-03-15 21:35:39,743 INFO L933 BasicCegarLoop]: 1 mSDtfsCounter, 655 mSDsluCounter, 923 mSDsCounter, 0 mSdLazyCounter, 2755 mSolverCounterSat, 259 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 655 SdHoareTripleChecker+Valid, 3 SdHoareTripleChecker+Invalid, 3014 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 259 IncrementalHoareTripleChecker+Valid, 2755 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.0s IncrementalHoareTripleChecker+Time [2022-03-15 21:35:39,743 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [655 Valid, 3 Invalid, 3014 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [259 Valid, 2755 Invalid, 0 Unknown, 0 Unchecked, 1.0s Time] [2022-03-15 21:35:39,748 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4178 states. [2022-03-15 21:35:39,787 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4178 to 2474. [2022-03-15 21:35:39,791 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2474 states, 2473 states have (on average 3.2976142337242216) internal successors, (8155), 2473 states have internal predecessors, (8155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:35:39,797 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2474 states to 2474 states and 8155 transitions. [2022-03-15 21:35:39,798 INFO L78 Accepts]: Start accepts. Automaton has 2474 states and 8155 transitions. Word has length 30 [2022-03-15 21:35:39,798 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:35:39,798 INFO L470 AbstractCegarLoop]: Abstraction has 2474 states and 8155 transitions. [2022-03-15 21:35:39,799 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 45 states, 45 states have (on average 4.444444444444445) internal successors, (200), 44 states have internal predecessors, (200), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:35:39,799 INFO L276 IsEmpty]: Start isEmpty. Operand 2474 states and 8155 transitions. [2022-03-15 21:35:39,803 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2022-03-15 21:35:39,803 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:35:39,804 INFO L514 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:35:39,827 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Forceful destruction successful, exit code 0 [2022-03-15 21:35:40,019 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9,7 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:35:40,019 INFO L402 AbstractCegarLoop]: === Iteration 11 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION (and 1 more)] === [2022-03-15 21:35:40,020 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:35:40,020 INFO L85 PathProgramCache]: Analyzing trace with hash 152851613, now seen corresponding path program 7 times [2022-03-15 21:35:40,020 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:35:40,020 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [149001064] [2022-03-15 21:35:40,021 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:35:40,021 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:35:40,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:35:40,200 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:35:40,200 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:35:40,200 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [149001064] [2022-03-15 21:35:40,200 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [149001064] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:35:40,200 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [627260173] [2022-03-15 21:35:40,200 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-03-15 21:35:40,200 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:35:40,200 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:35:40,202 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:35:40,202 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2022-03-15 21:35:40,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:35:40,233 INFO L263 TraceCheckSpWp]: Trace formula consists of 115 conjuncts, 29 conjunts are in the unsatisfiable core [2022-03-15 21:35:40,234 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:35:40,485 INFO L353 Elim1Store]: treesize reduction 9, result has 10.0 percent of original size [2022-03-15 21:35:40,486 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 31 treesize of output 19 [2022-03-15 21:35:40,603 INFO L353 Elim1Store]: treesize reduction 9, result has 10.0 percent of original size [2022-03-15 21:35:40,603 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 13 [2022-03-15 21:35:40,660 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:35:40,660 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:35:40,767 INFO L353 Elim1Store]: treesize reduction 24, result has 60.7 percent of original size [2022-03-15 21:35:40,767 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 34 treesize of output 58 [2022-03-15 21:35:41,022 INFO L353 Elim1Store]: treesize reduction 24, result has 60.7 percent of original size [2022-03-15 21:35:41,022 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 34 treesize of output 58 [2022-03-15 21:35:41,225 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:35:41,225 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [627260173] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:35:41,225 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:35:41,225 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14] total 33 [2022-03-15 21:35:41,226 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [595655985] [2022-03-15 21:35:41,226 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:35:41,228 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:35:41,251 INFO L252 McrAutomatonBuilder]: Finished intersection with 170 states and 381 transitions. [2022-03-15 21:35:41,251 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:35:46,255 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 22 new interpolants: [46571#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (= temp1 1)) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ d2 4) (* 2 W)))), 46570#(and (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)))), 46587#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (<= back1 (+ front1 1))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ front1 1) back1)) (or (not v_assert) (<= (+ d2 4) (* 2 W)))), 46572#(and (or (<= d2 (* 2 W)) v_assert) (or (<= d2 (* 2 W)) (< 0 w))), 46574#(and (or (<= (+ d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ d2 (select queue2 front2)) (* 2 W)) v_assert)), 46584#(and (or (not (< front1 back1)) (= (select queue1 (+ front1 1)) 1)) (or (not (< front1 back1)) (<= (+ d2 4) (* 2 W))) (or (not (< front1 back1)) (= front2 back2)) (or (not (< front1 back1)) (= (select queue1 front1) 1))), 46589#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (= front1 back1)) (or (not v_assert) (= W w)) (or (not v_assert) (<= d2 0))), 46577#(and (or (<= back2 (+ front2 1)) (< 0 w)) (or (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or v_assert (<= (+ front2 1) back2)) (or (<= (+ front2 1) back2) (< 0 w)) (or (<= back2 (+ front2 1)) v_assert) (or (= temp1 1) (< 0 w)) (or (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) v_assert) (or (= temp1 1) v_assert)), 46583#(and (or (not v_assert) (< 0 w) (<= (+ d2 4) (* 2 W))) (or (not v_assert) (< 0 w) (= (select queue1 front1) 1)) (or (not v_assert) (= temp1 1) (< 0 w)) (or (not v_assert) (< 0 w) (= front2 back2))), 46576#(and (or (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) v_assert)), 46575#(and (or (<= (+ d2 temp2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ d2 temp2 (select queue2 front2)) (* 2 W)) v_assert)), 46568#(or (not v_assert) (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))), 46586#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (= (select queue1 (+ front1 1)) 1)) (or (not v_assert) (<= (+ d2 4) (* 2 W)))), 46573#(and (or (<= (+ d2 temp2) (* 2 W)) v_assert) (or (<= (+ d2 temp2) (* 2 W)) (< 0 w))), 46585#(and (or (not v_assert) (not (< front1 back1)) (= (select queue1 (+ front1 1)) 1)) (or (not v_assert) (not (< front1 back1)) (= (select queue1 front1) 1)) (or (not v_assert) (not (< front1 back1)) (= front2 back2)) (or (not v_assert) (not (< front1 back1)) (<= (+ d2 4) (* 2 W)))), 46588#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (<= back1 (+ front1 1))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ 2 d2 (* 2 w)) (* 2 W))) (or (not v_assert) (<= (+ front1 1) back1))), 46581#(and (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (not v_assert) (<= back2 (+ front2 1)) (< 0 w)) (or (not v_assert) (= temp1 1) (< 0 w)) (or (not v_assert) (<= (+ front2 1) back2) (< 0 w))), 46579#(and (or (< 0 w) (= (select queue1 front1) 1)) (or (< 0 w) (= front2 back2)) (or (< 0 w) (<= (+ d2 4) (* 2 W))) (or v_assert (= (select queue1 front1) 1)) (or (= temp1 1) (< 0 w)) (or (= temp1 1) v_assert) (or v_assert (<= (+ d2 4) (* 2 W))) (or v_assert (= front2 back2))), 46578#(and (or (<= back2 (+ front2 1)) (< 0 w)) (or (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (< 0 w) (= (select queue1 front1) 1)) (or v_assert (<= (+ front2 1) back2)) (or (<= (+ front2 1) back2) (< 0 w)) (or v_assert (= (select queue1 front1) 1)) (or (<= back2 (+ front2 1)) v_assert) (or (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) v_assert)), 46582#(and (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (not v_assert) (<= back2 (+ front2 1)) (< 0 w)) (or (not v_assert) (< 0 w) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ front2 1) back2) (< 0 w))), 46580#(or (not v_assert) (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w)), 46569#(and (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W))))] [2022-03-15 21:35:46,256 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 37 states [2022-03-15 21:35:46,256 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:35:46,256 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2022-03-15 21:35:46,256 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=237, Invalid=2843, Unknown=0, NotChecked=0, Total=3080 [2022-03-15 21:35:46,256 INFO L87 Difference]: Start difference. First operand 2474 states and 8155 transitions. Second operand has 37 states, 37 states have (on average 4.4324324324324325) internal successors, (164), 36 states have internal predecessors, (164), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:35:48,336 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:35:48,336 INFO L93 Difference]: Finished difference Result 3325 states and 10959 transitions. [2022-03-15 21:35:48,336 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2022-03-15 21:35:48,337 INFO L78 Accepts]: Start accepts. Automaton has has 37 states, 37 states have (on average 4.4324324324324325) internal successors, (164), 36 states have internal predecessors, (164), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 30 [2022-03-15 21:35:48,337 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:35:48,344 INFO L225 Difference]: With dead ends: 3325 [2022-03-15 21:35:48,345 INFO L226 Difference]: Without dead ends: 3277 [2022-03-15 21:35:48,345 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 238 GetRequests, 156 SyntacticMatches, 1 SemanticMatches, 81 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1498 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=719, Invalid=6087, Unknown=0, NotChecked=0, Total=6806 [2022-03-15 21:35:48,345 INFO L933 BasicCegarLoop]: 1 mSDtfsCounter, 457 mSDsluCounter, 814 mSDsCounter, 0 mSdLazyCounter, 2552 mSolverCounterSat, 160 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 457 SdHoareTripleChecker+Valid, 3 SdHoareTripleChecker+Invalid, 2712 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 160 IncrementalHoareTripleChecker+Valid, 2552 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.9s IncrementalHoareTripleChecker+Time [2022-03-15 21:35:48,346 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [457 Valid, 3 Invalid, 2712 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [160 Valid, 2552 Invalid, 0 Unknown, 0 Unchecked, 0.9s Time] [2022-03-15 21:35:48,349 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3277 states. [2022-03-15 21:35:48,381 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3277 to 2459. [2022-03-15 21:35:48,385 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2459 states, 2458 states have (on average 3.3006509357200975) internal successors, (8113), 2458 states have internal predecessors, (8113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:35:48,391 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2459 states to 2459 states and 8113 transitions. [2022-03-15 21:35:48,392 INFO L78 Accepts]: Start accepts. Automaton has 2459 states and 8113 transitions. Word has length 30 [2022-03-15 21:35:48,392 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:35:48,392 INFO L470 AbstractCegarLoop]: Abstraction has 2459 states and 8113 transitions. [2022-03-15 21:35:48,392 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 37 states, 37 states have (on average 4.4324324324324325) internal successors, (164), 36 states have internal predecessors, (164), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:35:48,392 INFO L276 IsEmpty]: Start isEmpty. Operand 2459 states and 8113 transitions. [2022-03-15 21:35:48,396 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2022-03-15 21:35:48,396 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:35:48,396 INFO L514 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:35:48,431 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Forceful destruction successful, exit code 0 [2022-03-15 21:35:48,611 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10,8 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:35:48,611 INFO L402 AbstractCegarLoop]: === Iteration 12 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION (and 1 more)] === [2022-03-15 21:35:48,612 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:35:48,612 INFO L85 PathProgramCache]: Analyzing trace with hash 543239978, now seen corresponding path program 8 times [2022-03-15 21:35:48,612 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:35:48,612 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [449434] [2022-03-15 21:35:48,612 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:35:48,612 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:35:48,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:35:48,816 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 2 proven. 17 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:35:48,816 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:35:48,816 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [449434] [2022-03-15 21:35:48,816 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [449434] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:35:48,816 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1842361332] [2022-03-15 21:35:48,816 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-03-15 21:35:48,816 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:35:48,816 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:35:48,817 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:35:48,818 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2022-03-15 21:35:48,845 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-03-15 21:35:48,845 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:35:48,845 INFO L263 TraceCheckSpWp]: Trace formula consists of 123 conjuncts, 30 conjunts are in the unsatisfiable core [2022-03-15 21:35:48,846 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:35:49,199 INFO L353 Elim1Store]: treesize reduction 9, result has 10.0 percent of original size [2022-03-15 21:35:49,200 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 31 treesize of output 19 [2022-03-15 21:35:49,272 INFO L353 Elim1Store]: treesize reduction 9, result has 10.0 percent of original size [2022-03-15 21:35:49,272 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 13 [2022-03-15 21:35:49,330 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 2 proven. 17 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:35:49,330 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:35:49,571 INFO L353 Elim1Store]: treesize reduction 24, result has 60.7 percent of original size [2022-03-15 21:35:49,571 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 34 treesize of output 58 [2022-03-15 21:35:49,828 INFO L353 Elim1Store]: treesize reduction 24, result has 60.7 percent of original size [2022-03-15 21:35:49,828 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 34 treesize of output 58 [2022-03-15 21:35:50,012 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 3 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:35:50,013 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1842361332] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:35:50,013 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:35:50,013 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14] total 38 [2022-03-15 21:35:50,013 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1042821738] [2022-03-15 21:35:50,013 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:35:50,015 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:35:50,053 INFO L252 McrAutomatonBuilder]: Finished intersection with 253 states and 623 transitions. [2022-03-15 21:35:50,053 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:36:00,089 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 31 new interpolants: [55116#(or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W))), 55135#(and (or (not v_assert) (not (< front1 back1)) (not (< front2 (+ back2 1))) (= (+ back2 1) (+ front2 1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (= (select queue1 (+ front1 1)) 1) (not (< front2 (+ back2 1))) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (not (< front2 (+ back2 1))) (<= (+ d2 (select queue2 front2) 4) (* 2 W)) (not (= (+ (select queue1 front1) 1) (select queue2 back2))))), 55125#(and (or (< 0 w) (= front2 back2)) (or (< 0 w) (<= (+ d2 4) (* 2 W))) (or (= temp1 1) (< 0 w)) (or (= temp1 1) v_assert) (or v_assert (<= (+ d2 4) (* 2 W))) (or v_assert (= front2 back2))), 55117#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (<= (+ d2 temp2 4) (* 2 W))) (or (not v_assert) (= temp1 1))), 55120#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (<= (+ d2 temp2 4) (* 2 W))) (or (not v_assert) (= (select queue1 front1) 1))), 55138#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ d2 4 (* 2 w)) (* 2 W))) (or (not v_assert) (= (select queue1 (+ front1 1)) 1))), 55140#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (<= (+ 2 d2 temp2 (* 2 w)) (* 2 W))) (or (not v_assert) (= (select queue1 front1) 1))), 55121#(and (or v_assert (<= (+ 2 d2) (* 2 W))) (or (< 0 w) (<= (+ 2 d2) (* 2 W)))), 55130#(and (or (not v_assert) (<= (+ d2 (select queue2 front2) 4) (* 2 W)) (< 0 w) (not (< front2 back2))) (or (not v_assert) (= back2 (+ front2 1)) (< 0 w) (not (< front2 back2))) (or (not v_assert) (= temp1 1) (< 0 w) (not (< front2 back2)))), 55131#(and (or (<= back1 front1) (not v_assert) (= back2 (+ front2 1)) (not (< front2 back2))) (or (<= back1 front1) (not v_assert) (not (< front2 back2)) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (<= (+ d2 (select queue2 front2) 4) (* 2 W)) (not (< front2 back2)))), 55139#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ 2 d2 (* 2 w)) (* 2 W)))), 55141#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (<= back1 (+ front1 1))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ 2 d2 (* 2 w)) (* 2 W))) (or (not v_assert) (<= (+ front1 1) back1))), 55137#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (= temp1 1)) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ d2 4 (* 2 w)) (* 2 W)))), 55124#(or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (< 0 w)), 55115#(and (or (<= back1 front1) (not v_assert) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (<= (+ d2 4) (* 2 W))) (or (<= back1 front1) (not v_assert) (= front2 back2))), 55123#(and (or (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) v_assert)), 55113#(or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W))), 55112#(and (or (<= back1 front1) (= front2 back2)) (or (<= back1 front1) (<= (+ d2 4) (* 2 W))) (or (<= back1 front1) (= (select queue1 front1) 1))), 55128#(and (or (not v_assert) (<= (+ d2 temp2 4) (* 2 W)) (< 0 w)) (or (not v_assert) (= temp1 1) (< 0 w)) (or (not v_assert) (< 0 w) (= front2 back2))), 55132#(and (or (not v_assert) (= back2 (+ front2 1)) (not (< front2 back2))) (or (not v_assert) (<= (+ d2 (select queue2 front2) 4) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (not (< front2 back2)) (= (select queue1 front1) 1))), 55127#(or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (< 0 w)), 55126#(and (or (not v_assert) (< 0 w) (<= (+ d2 4) (* 2 W))) (or (not v_assert) (= temp1 1) (< 0 w)) (or (not v_assert) (< 0 w) (= front2 back2))), 55118#(and (or (<= back1 front1) (not v_assert) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (<= (+ d2 temp2 4) (* 2 W))) (or (<= back1 front1) (not v_assert) (= front2 back2))), 55129#(and (or (not v_assert) (= back2 (+ front2 1)) (not (< front2 back2))) (or (not v_assert) (<= (+ d2 (select queue2 front2) 4) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (= temp1 1) (not (< front2 back2)))), 55133#(and (or (<= back1 front1) (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (+ back2 1) (+ front2 1))) (or (<= back1 front1) (not v_assert) (not (< front2 (+ back2 1))) (<= (+ d2 (select queue2 front2) 4) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1)))) (or (<= back1 front1) (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1))), 55114#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= (+ d2 4) (* 2 W)))), 55142#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (= front1 back1)) (or (not v_assert) (= W w)) (or (not v_assert) (<= d2 0))), 55119#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ d2 4) (* 2 W)))), 55134#(and (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (+ back2 1) (+ front2 1))) (or (not v_assert) (not (< front2 (+ back2 1))) (<= (+ d2 (select queue2 front2) 4) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1))), 55122#(and (or v_assert (<= (+ 2 d2 temp2) (* 2 W))) (or (< 0 w) (<= (+ 2 d2 temp2) (* 2 W)))), 55136#(and (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2) (* 2 w)) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)))] [2022-03-15 21:36:00,098 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 46 states [2022-03-15 21:36:00,098 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:36:00,099 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2022-03-15 21:36:00,099 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=380, Invalid=4450, Unknown=0, NotChecked=0, Total=4830 [2022-03-15 21:36:00,099 INFO L87 Difference]: Start difference. First operand 2459 states and 8113 transitions. Second operand has 46 states, 46 states have (on average 4.586956521739131) internal successors, (211), 45 states have internal predecessors, (211), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:36:08,054 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:36:08,054 INFO L93 Difference]: Finished difference Result 8738 states and 29159 transitions. [2022-03-15 21:36:08,055 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 111 states. [2022-03-15 21:36:08,055 INFO L78 Accepts]: Start accepts. Automaton has has 46 states, 46 states have (on average 4.586956521739131) internal successors, (211), 45 states have internal predecessors, (211), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 32 [2022-03-15 21:36:08,055 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:36:08,076 INFO L225 Difference]: With dead ends: 8738 [2022-03-15 21:36:08,076 INFO L226 Difference]: Without dead ends: 8619 [2022-03-15 21:36:08,078 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 400 GetRequests, 196 SyntacticMatches, 32 SemanticMatches, 172 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8876 ImplicationChecksByTransitivity, 9.1s TimeCoverageRelationStatistics Valid=3633, Invalid=26469, Unknown=0, NotChecked=0, Total=30102 [2022-03-15 21:36:08,079 INFO L933 BasicCegarLoop]: 1 mSDtfsCounter, 804 mSDsluCounter, 1217 mSDsCounter, 0 mSdLazyCounter, 4153 mSolverCounterSat, 435 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 804 SdHoareTripleChecker+Valid, 3 SdHoareTripleChecker+Invalid, 4588 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 435 IncrementalHoareTripleChecker+Valid, 4153 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.7s IncrementalHoareTripleChecker+Time [2022-03-15 21:36:08,079 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [804 Valid, 3 Invalid, 4588 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [435 Valid, 4153 Invalid, 0 Unknown, 0 Unchecked, 1.7s Time] [2022-03-15 21:36:08,088 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8619 states. [2022-03-15 21:36:08,153 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8619 to 2405. [2022-03-15 21:36:08,166 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2405 states, 2404 states have (on average 3.291181364392679) internal successors, (7912), 2404 states have internal predecessors, (7912), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:36:08,172 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2405 states to 2405 states and 7912 transitions. [2022-03-15 21:36:08,172 INFO L78 Accepts]: Start accepts. Automaton has 2405 states and 7912 transitions. Word has length 32 [2022-03-15 21:36:08,172 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:36:08,172 INFO L470 AbstractCegarLoop]: Abstraction has 2405 states and 7912 transitions. [2022-03-15 21:36:08,173 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 46 states, 46 states have (on average 4.586956521739131) internal successors, (211), 45 states have internal predecessors, (211), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:36:08,173 INFO L276 IsEmpty]: Start isEmpty. Operand 2405 states and 7912 transitions. [2022-03-15 21:36:08,177 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2022-03-15 21:36:08,177 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:36:08,177 INFO L514 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:36:08,207 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Forceful destruction successful, exit code 0 [2022-03-15 21:36:08,388 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable11 [2022-03-15 21:36:08,388 INFO L402 AbstractCegarLoop]: === Iteration 13 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION (and 1 more)] === [2022-03-15 21:36:08,388 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:36:08,388 INFO L85 PathProgramCache]: Analyzing trace with hash -1168336925, now seen corresponding path program 9 times [2022-03-15 21:36:08,389 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:36:08,389 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1596238175] [2022-03-15 21:36:08,389 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:36:08,390 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:36:08,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:36:08,412 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 12 proven. 8 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-03-15 21:36:08,412 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:36:08,413 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1596238175] [2022-03-15 21:36:08,413 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1596238175] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:36:08,413 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [973698534] [2022-03-15 21:36:08,413 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-03-15 21:36:08,413 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:36:08,413 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:36:08,416 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:36:08,419 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2022-03-15 21:36:08,449 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2022-03-15 21:36:08,449 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:36:08,450 INFO L263 TraceCheckSpWp]: Trace formula consists of 123 conjuncts, 6 conjunts are in the unsatisfiable core [2022-03-15 21:36:08,450 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:36:08,499 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 12 proven. 7 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-03-15 21:36:08,500 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:36:08,537 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 12 proven. 7 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-03-15 21:36:08,537 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [973698534] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:36:08,537 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:36:08,537 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 4, 4] total 5 [2022-03-15 21:36:08,538 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [848901097] [2022-03-15 21:36:08,538 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:36:08,540 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:36:08,571 INFO L252 McrAutomatonBuilder]: Finished intersection with 189 states and 427 transitions. [2022-03-15 21:36:08,571 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:36:09,394 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 0 new interpolants: [] [2022-03-15 21:36:09,394 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-03-15 21:36:09,395 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:36:09,395 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-03-15 21:36:09,395 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2022-03-15 21:36:09,395 INFO L87 Difference]: Start difference. First operand 2405 states and 7912 transitions. Second operand has 6 states, 6 states have (on average 8.833333333333334) internal successors, (53), 5 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:36:09,461 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:36:09,461 INFO L93 Difference]: Finished difference Result 4396 states and 14400 transitions. [2022-03-15 21:36:09,461 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-03-15 21:36:09,462 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 8.833333333333334) internal successors, (53), 5 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 33 [2022-03-15 21:36:09,462 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:36:09,472 INFO L225 Difference]: With dead ends: 4396 [2022-03-15 21:36:09,472 INFO L226 Difference]: Without dead ends: 4331 [2022-03-15 21:36:09,472 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 225 GetRequests, 191 SyntacticMatches, 30 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 91 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2022-03-15 21:36:09,474 INFO L933 BasicCegarLoop]: 4 mSDtfsCounter, 41 mSDsluCounter, 82 mSDsCounter, 0 mSdLazyCounter, 92 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 41 SdHoareTripleChecker+Valid, 20 SdHoareTripleChecker+Invalid, 96 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 92 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-03-15 21:36:09,474 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [41 Valid, 20 Invalid, 96 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 92 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-03-15 21:36:09,478 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4331 states. [2022-03-15 21:36:09,544 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4331 to 3116. [2022-03-15 21:36:09,549 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3116 states, 3115 states have (on average 3.331621187800963) internal successors, (10378), 3115 states have internal predecessors, (10378), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:36:09,557 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3116 states to 3116 states and 10378 transitions. [2022-03-15 21:36:09,557 INFO L78 Accepts]: Start accepts. Automaton has 3116 states and 10378 transitions. Word has length 33 [2022-03-15 21:36:09,557 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:36:09,557 INFO L470 AbstractCegarLoop]: Abstraction has 3116 states and 10378 transitions. [2022-03-15 21:36:09,557 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 8.833333333333334) internal successors, (53), 5 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:36:09,557 INFO L276 IsEmpty]: Start isEmpty. Operand 3116 states and 10378 transitions. [2022-03-15 21:36:09,562 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-03-15 21:36:09,562 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:36:09,562 INFO L514 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:36:09,581 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Forceful destruction successful, exit code 0 [2022-03-15 21:36:09,779 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable12 [2022-03-15 21:36:09,779 INFO L402 AbstractCegarLoop]: === Iteration 14 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION (and 1 more)] === [2022-03-15 21:36:09,780 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:36:09,780 INFO L85 PathProgramCache]: Analyzing trace with hash -1385261722, now seen corresponding path program 10 times [2022-03-15 21:36:09,780 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:36:09,780 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [55551634] [2022-03-15 21:36:09,780 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:36:09,780 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:36:09,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:36:09,811 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 15 proven. 6 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2022-03-15 21:36:09,811 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:36:09,811 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [55551634] [2022-03-15 21:36:09,811 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [55551634] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:36:09,812 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1941269997] [2022-03-15 21:36:09,812 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-03-15 21:36:09,812 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:36:09,812 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:36:09,813 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:36:09,814 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2022-03-15 21:36:09,840 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-03-15 21:36:09,840 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:36:09,840 INFO L263 TraceCheckSpWp]: Trace formula consists of 135 conjuncts, 6 conjunts are in the unsatisfiable core [2022-03-15 21:36:09,841 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:36:09,885 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 15 proven. 5 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2022-03-15 21:36:09,885 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:36:09,930 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 15 proven. 5 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2022-03-15 21:36:09,930 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1941269997] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:36:09,930 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:36:09,930 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 4, 4] total 5 [2022-03-15 21:36:09,930 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1217688030] [2022-03-15 21:36:09,931 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:36:09,934 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:36:09,979 INFO L252 McrAutomatonBuilder]: Finished intersection with 263 states and 631 transitions. [2022-03-15 21:36:09,979 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:36:11,086 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 0 new interpolants: [] [2022-03-15 21:36:11,087 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-03-15 21:36:11,087 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:36:11,087 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-03-15 21:36:11,087 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2022-03-15 21:36:11,087 INFO L87 Difference]: Start difference. First operand 3116 states and 10378 transitions. Second operand has 6 states, 6 states have (on average 9.0) internal successors, (54), 5 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:36:11,159 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:36:11,159 INFO L93 Difference]: Finished difference Result 6397 states and 21174 transitions. [2022-03-15 21:36:11,160 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-03-15 21:36:11,160 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 9.0) internal successors, (54), 5 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 36 [2022-03-15 21:36:11,160 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:36:11,174 INFO L225 Difference]: With dead ends: 6397 [2022-03-15 21:36:11,174 INFO L226 Difference]: Without dead ends: 6159 [2022-03-15 21:36:11,175 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 302 GetRequests, 282 SyntacticMatches, 16 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 49 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2022-03-15 21:36:11,175 INFO L933 BasicCegarLoop]: 4 mSDtfsCounter, 54 mSDsluCounter, 63 mSDsCounter, 0 mSdLazyCounter, 78 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 54 SdHoareTripleChecker+Valid, 16 SdHoareTripleChecker+Invalid, 82 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 78 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-03-15 21:36:11,175 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [54 Valid, 16 Invalid, 82 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 78 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-03-15 21:36:11,183 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6159 states. [2022-03-15 21:36:11,243 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6159 to 4204. [2022-03-15 21:36:11,249 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4204 states, 4203 states have (on average 3.3659290982631456) internal successors, (14147), 4203 states have internal predecessors, (14147), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:36:11,258 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4204 states to 4204 states and 14147 transitions. [2022-03-15 21:36:11,258 INFO L78 Accepts]: Start accepts. Automaton has 4204 states and 14147 transitions. Word has length 36 [2022-03-15 21:36:11,258 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:36:11,258 INFO L470 AbstractCegarLoop]: Abstraction has 4204 states and 14147 transitions. [2022-03-15 21:36:11,258 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 9.0) internal successors, (54), 5 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:36:11,259 INFO L276 IsEmpty]: Start isEmpty. Operand 4204 states and 14147 transitions. [2022-03-15 21:36:11,265 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2022-03-15 21:36:11,265 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:36:11,265 INFO L514 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:36:11,281 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Forceful destruction successful, exit code 0 [2022-03-15 21:36:11,478 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable13 [2022-03-15 21:36:11,478 INFO L402 AbstractCegarLoop]: === Iteration 15 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION (and 1 more)] === [2022-03-15 21:36:11,479 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:36:11,479 INFO L85 PathProgramCache]: Analyzing trace with hash 1133580897, now seen corresponding path program 11 times [2022-03-15 21:36:11,479 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:36:11,479 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1574483555] [2022-03-15 21:36:11,479 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:36:11,480 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:36:11,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:36:11,788 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 3 proven. 27 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2022-03-15 21:36:11,788 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:36:11,788 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1574483555] [2022-03-15 21:36:11,788 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1574483555] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:36:11,788 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1806789416] [2022-03-15 21:36:11,789 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-03-15 21:36:11,789 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:36:11,789 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:36:11,790 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:36:11,790 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2022-03-15 21:36:11,822 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2022-03-15 21:36:11,822 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:36:11,823 INFO L263 TraceCheckSpWp]: Trace formula consists of 143 conjuncts, 45 conjunts are in the unsatisfiable core [2022-03-15 21:36:11,824 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:36:12,350 INFO L353 Elim1Store]: treesize reduction 32, result has 3.0 percent of original size [2022-03-15 21:36:12,351 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 51 treesize of output 31 [2022-03-15 21:36:12,516 INFO L353 Elim1Store]: treesize reduction 32, result has 3.0 percent of original size [2022-03-15 21:36:12,517 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 38 treesize of output 18 [2022-03-15 21:36:12,576 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 3 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:36:12,577 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:36:13,013 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:13,014 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:13,014 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:13,015 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:13,016 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:13,036 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:13,036 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:13,036 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:13,037 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:13,066 INFO L353 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-03-15 21:36:13,066 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 9 disjoint index pairs (out of 15 index pairs), introduced 6 new quantified variables, introduced 6 case distinctions, treesize of input 52 treesize of output 96 [2022-03-15 21:36:13,413 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:13,414 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:13,415 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:13,416 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:13,416 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:13,416 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:13,417 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:13,418 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:13,418 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:13,435 INFO L353 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-03-15 21:36:13,435 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 9 disjoint index pairs (out of 15 index pairs), introduced 6 new quantified variables, introduced 6 case distinctions, treesize of input 47 treesize of output 91 [2022-03-15 21:36:13,841 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 9 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:36:13,842 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1806789416] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:36:13,842 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:36:13,842 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 19, 19] total 45 [2022-03-15 21:36:13,842 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1436403499] [2022-03-15 21:36:13,842 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:36:13,845 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:36:13,916 INFO L252 McrAutomatonBuilder]: Finished intersection with 325 states and 812 transitions. [2022-03-15 21:36:13,916 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:36:30,838 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 49 new interpolants: [95041#(and (or (<= back1 front1) (not v_assert) (= (+ (- 1) (select queue1 front1)) 0) (not (= (select queue2 back2) (+ temp1 1))) (not (< front2 back2))) (or (<= back1 front1) (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (<= back1 front1) (not v_assert) (<= back2 (+ front2 1)) (not (= (select queue2 back2) (+ temp1 1))))), 95016#(and (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)))), 95031#(or (not v_assert) (<= (+ d2 temp2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w)), 95022#(and (or (= (+ (- 1) temp1) 0) (< 0 w)) (or (<= back2 (+ front2 1)) (< 0 w)) (or (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or v_assert (<= (+ front2 1) back2)) (or (<= (+ front2 1) back2) (< 0 w)) (or (<= back2 (+ front2 1)) v_assert) (or (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) v_assert) (or v_assert (= (+ (- 1) temp1) 0))), 95059#(and (or (not v_assert) (= (+ back2 (* (- 1) front2)) 0) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 front2) (* 2 w)) (* 2 W))) (or (not v_assert) (= (+ (- 1) (* (- 1) front1) back1) 0) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1))), 95033#(and (or (<= back1 front1) (not v_assert) (= (+ (- 1) (select queue1 front1)) 0) (not (= (select queue2 back2) (+ temp1 1)))) (or (<= back1 front1) (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (<= back1 front1) (not v_assert) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1)))) (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1))))), 95017#(and (or (<= d2 (* 2 W)) v_assert) (or (<= d2 (* 2 W)) (< 0 w))), 95047#(and (or (not v_assert) (<= (+ 2 d2 temp2 (* 2 w)) (* 2 W))) (or (not v_assert) (= temp1 1)) (or (not v_assert) (= (+ back2 (* (- 1) front2)) 0)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 95037#(and (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1)))) (or (<= back1 front1) (not v_assert) (= (+ (- 1) (select queue1 front1)) 0) (not (= (select queue2 back2) (+ temp1 1)))) (or (<= back1 front1) (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (<= back1 front1) (not v_assert) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1))))), 95050#(and (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (= (+ (- 1) (* (- 1) front1) back1) 0)) (or (not v_assert) (<= (+ 2 d2 (* 2 w)) (* 2 W))) (or (not v_assert) (= (+ back2 (* (- 1) front2)) 0))), 95029#(or (not v_assert) (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w)), 95055#(and (or (not v_assert) (not (< front1 back1)) (<= back2 (+ front2 1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (not (= (+ (select queue1 front1) 1) (select queue2 back2))) (not (< front2 back2))) (or (not v_assert) (not (< front1 back1)) (= back1 (+ front1 1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2))) (not (< front2 back2)))), 95052#(and (or (not v_assert) (not (< front1 back1)) (<= front2 back2) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (= back1 (+ front1 1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (<= back2 front2) (not (= (+ (select queue1 front1) 1) (select queue2 back2))))), 95053#(and (or (not v_assert) (<= (+ 2 d2 temp2 (* 2 w)) (* 2 W))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (= (+ (- 1) (* (- 1) front1) back1) 0)) (or (not v_assert) (= (+ back2 (* (- 1) front2)) 0))), 95043#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (= front1 back1) (not (= (select queue2 back2) (+ temp1 1))) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1)) (not (= (select queue2 back2) (+ temp1 1))))), 95062#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (= front1 back1)) (or (not v_assert) (= W w)) (or (not v_assert) (<= d2 0))), 95042#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1)) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (not (< front2 back2)) (= (select queue1 front1) 1))), 95026#(and (or (not v_assert) (= (+ (- 1) temp1) 0)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)))), 95039#(and (or (not v_assert) (= front1 back1)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)))), 95028#(and (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)))), 95035#(and (or (not v_assert) (= front1 back1)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)))), 95019#(and (or (<= (+ d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ d2 (select queue2 front2)) (* 2 W)) v_assert)), 95054#(and (or (not v_assert) (<= (+ d2 temp2 (* 2 w)) (* 2 W))) (or (not v_assert) (<= back2 front2)) (or (not v_assert) (<= front2 back2)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 95025#(or (not v_assert) (<= (+ d2 temp2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))), 95018#(and (or (<= (+ d2 temp2) (* 2 W)) v_assert) (or (<= (+ d2 temp2) (* 2 W)) (< 0 w))), 95051#(and (or (not v_assert) (<= back2 front2)) (or (not v_assert) (<= front2 back2)) (or (<= (+ d2 (* 2 w)) (* 2 W)) (not v_assert)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 95058#(and (or (not v_assert) (not (< front1 back1)) (not (= (+ (select queue1 front1) 1) (select queue2 (+ back2 1)))) (= back1 (+ front1 1)) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (< front1 back1)) (not (= (+ (select queue1 front1) 1) (select queue2 (+ back2 1)))) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))) (or (not v_assert) (not (< front1 back1)) (not (= (+ (select queue1 front1) 1) (select queue2 (+ back2 1)))) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2))), 95038#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (not v_assert) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1))))), 95030#(and (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (not v_assert) (<= back2 (+ front2 1)) (< 0 w)) (or (not v_assert) (= (+ (- 1) temp1) 0) (< 0 w)) (or (not v_assert) (<= (+ front2 1) back2) (< 0 w))), 95044#(and (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 95023#(or (not v_assert) (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))), 95061#(and (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert) (not (< front1 back1)) (not (< front2 (+ back2 1))) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (= (+ (- 1) (* (- 1) front1) back1) 0) (not (< front2 (+ back2 1))) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (<= back2 front2) (not (= (+ (select queue1 front1) 1) (select queue2 back2))))), 95036#(and (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (= front1 back1) (not (= (select queue2 back2) (+ temp1 1))))), 95021#(and (or (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) v_assert)), 95049#(and (or (not v_assert) (not (< front1 back1)) (<= front2 back2) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (= back1 (+ front1 1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (<= back2 front2) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (< front1 back1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2))))), 95040#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (= front1 back1) (not (= (select queue2 back2) (+ temp1 1))))), 95027#(and (or (<= back1 front1) (not v_assert) (= (+ (- 1) (select queue1 front1)) 0)) (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W))) (or (<= back1 front1) (not v_assert) (<= back2 (+ front2 1))) (or (<= back1 front1) (not v_assert) (<= (+ front2 1) back2))), 95034#(and (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (not v_assert) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1))))), 95056#(and (or (not v_assert) (= 0 (+ (- 1) back2 (* (- 1) front2))) (not (< front2 back2))) (or (not v_assert) (= (+ (- 1) (* (- 1) front1) back1) 0) (not (< front2 back2))) (or (not v_assert) (not (< front2 back2)) (= (select queue1 front1) 1)) (or (not v_assert) (not (< front2 back2)) (<= (+ 2 d2 (select queue2 front2) (* 2 w)) (* 2 W)))), 95024#(and (or (not v_assert) (= (+ (- 1) temp1) 0)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)))), 95032#(and (or (not v_assert) (<= back2 (+ front2 1)) (< 0 w)) (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (not v_assert) (= (+ (- 1) temp1) 0) (< 0 w)) (or (not v_assert) (<= (+ front2 1) back2) (< 0 w))), 95060#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (+ (* (- 1) front1) back1) 0))), 95014#(and (or (<= back1 front1) (<= (+ 2 d2 (select queue2 front2)) (* 2 W))) (or (<= back1 front1) (<= (+ front2 1) back2)) (or (<= back1 front1) (<= back2 (+ front2 1))) (or (<= back1 front1) (= (+ (- 1) (select queue1 front1)) 0))), 95046#(and (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (<= (+ d2 temp2 (select queue2 front2) (* 2 w)) (* 2 W))) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 95045#(and (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= (+ 2 d2 (* 2 w)) (* 2 W))) (or (not v_assert) (= (+ back2 (* (- 1) front2)) 0)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 95015#(and (or (<= back1 front1) (not v_assert) (= (+ (- 1) (select queue1 front1)) 0)) (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W))) (or (<= back1 front1) (not v_assert) (<= back2 (+ front2 1))) (or (<= back1 front1) (not v_assert) (<= (+ front2 1) back2))), 95057#(and (or (not v_assert) (= (+ (* (- 1) front1) back1) 0) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1))) (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert) (not (< front2 back2)))), 95020#(and (or (<= (+ d2 temp2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ d2 temp2 (select queue2 front2)) (* 2 W)) v_assert)), 95048#(and (or (not v_assert) (= 0 (+ (- 1) back2 (* (- 1) front2))) (not (< front2 back2))) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0) (not (< front2 back2))) (or (not v_assert) (= temp1 1) (not (< front2 back2))) (or (not v_assert) (not (< front2 back2)) (<= (+ 2 d2 (select queue2 front2) (* 2 w)) (* 2 W))))] [2022-03-15 21:36:30,839 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 66 states [2022-03-15 21:36:30,839 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:36:30,839 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 66 interpolants. [2022-03-15 21:36:30,840 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=816, Invalid=8114, Unknown=0, NotChecked=0, Total=8930 [2022-03-15 21:36:30,840 INFO L87 Difference]: Start difference. First operand 4204 states and 14147 transitions. Second operand has 66 states, 66 states have (on average 4.484848484848484) internal successors, (296), 65 states have internal predecessors, (296), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:36:46,147 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:36:46,147 INFO L93 Difference]: Finished difference Result 29096 states and 99843 transitions. [2022-03-15 21:36:46,147 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 140 states. [2022-03-15 21:36:46,147 INFO L78 Accepts]: Start accepts. Automaton has has 66 states, 66 states have (on average 4.484848484848484) internal successors, (296), 65 states have internal predecessors, (296), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 38 [2022-03-15 21:36:46,147 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:36:46,216 INFO L225 Difference]: With dead ends: 29096 [2022-03-15 21:36:46,216 INFO L226 Difference]: Without dead ends: 28182 [2022-03-15 21:36:46,218 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 514 GetRequests, 220 SyntacticMatches, 66 SemanticMatches, 228 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21184 ImplicationChecksByTransitivity, 17.0s TimeCoverageRelationStatistics Valid=5644, Invalid=47026, Unknown=0, NotChecked=0, Total=52670 [2022-03-15 21:36:46,218 INFO L933 BasicCegarLoop]: 1 mSDtfsCounter, 1390 mSDsluCounter, 2335 mSDsCounter, 0 mSdLazyCounter, 8617 mSolverCounterSat, 761 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 3.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1390 SdHoareTripleChecker+Valid, 3 SdHoareTripleChecker+Invalid, 9378 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 761 IncrementalHoareTripleChecker+Valid, 8617 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 3.6s IncrementalHoareTripleChecker+Time [2022-03-15 21:36:46,218 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [1390 Valid, 3 Invalid, 9378 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [761 Valid, 8617 Invalid, 0 Unknown, 0 Unchecked, 3.6s Time] [2022-03-15 21:36:46,247 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28182 states. [2022-03-15 21:36:46,460 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28182 to 4673. [2022-03-15 21:36:46,467 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4673 states, 4672 states have (on average 3.3698630136986303) internal successors, (15744), 4672 states have internal predecessors, (15744), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:36:46,478 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4673 states to 4673 states and 15744 transitions. [2022-03-15 21:36:46,478 INFO L78 Accepts]: Start accepts. Automaton has 4673 states and 15744 transitions. Word has length 38 [2022-03-15 21:36:46,478 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:36:46,478 INFO L470 AbstractCegarLoop]: Abstraction has 4673 states and 15744 transitions. [2022-03-15 21:36:46,479 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 66 states, 66 states have (on average 4.484848484848484) internal successors, (296), 65 states have internal predecessors, (296), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:36:46,479 INFO L276 IsEmpty]: Start isEmpty. Operand 4673 states and 15744 transitions. [2022-03-15 21:36:46,486 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2022-03-15 21:36:46,486 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:36:46,487 INFO L514 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:36:46,515 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Ended with exit code 0 [2022-03-15 21:36:46,716 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable14 [2022-03-15 21:36:46,716 INFO L402 AbstractCegarLoop]: === Iteration 16 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION (and 1 more)] === [2022-03-15 21:36:46,717 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:36:46,717 INFO L85 PathProgramCache]: Analyzing trace with hash -1058288261, now seen corresponding path program 12 times [2022-03-15 21:36:46,717 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:36:46,717 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1448053157] [2022-03-15 21:36:46,717 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:36:46,717 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:36:46,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:36:47,071 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 3 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:36:47,071 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:36:47,071 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1448053157] [2022-03-15 21:36:47,071 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1448053157] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:36:47,071 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [866980938] [2022-03-15 21:36:47,071 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-03-15 21:36:47,072 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:36:47,072 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:36:47,073 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:36:47,073 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2022-03-15 21:36:47,107 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 6 check-sat command(s) [2022-03-15 21:36:47,108 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:36:47,109 INFO L263 TraceCheckSpWp]: Trace formula consists of 143 conjuncts, 43 conjunts are in the unsatisfiable core [2022-03-15 21:36:47,110 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:36:47,851 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:36:47,852 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:36:47,853 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:36:47,853 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:36:47,854 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:47,854 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 3 disjoint index pairs (out of 6 index pairs), introduced 3 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 29 [2022-03-15 21:36:48,089 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:48,090 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:36:48,090 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:36:48,091 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:36:48,092 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 3 disjoint index pairs (out of 6 index pairs), introduced 3 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 18 [2022-03-15 21:36:48,163 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 3 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:36:48,163 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:36:49,114 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:49,116 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:49,116 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:49,119 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:49,119 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:49,119 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:49,120 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:49,144 INFO L353 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-03-15 21:36:49,145 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 7 disjoint index pairs (out of 15 index pairs), introduced 6 new quantified variables, introduced 8 case distinctions, treesize of input 48 treesize of output 110 [2022-03-15 21:36:49,871 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:49,872 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:49,873 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:49,873 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:49,875 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:49,876 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:49,878 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:36:49,913 INFO L353 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-03-15 21:36:49,914 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 7 disjoint index pairs (out of 15 index pairs), introduced 6 new quantified variables, introduced 8 case distinctions, treesize of input 43 treesize of output 101 [2022-03-15 21:36:50,385 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 3 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:36:50,386 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [866980938] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:36:50,386 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:36:50,386 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 19, 19] total 48 [2022-03-15 21:36:50,386 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [160186858] [2022-03-15 21:36:50,386 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:36:50,389 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:36:50,467 INFO L252 McrAutomatonBuilder]: Finished intersection with 375 states and 961 transitions. [2022-03-15 21:36:50,467 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:37:11,821 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 57 new interpolants: [134098#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (+ (* (- 1) front1) back1) 0))), 134078#(and (or (<= back1 front1) (not v_assert) (= (+ (- 1) (select queue1 front1)) 0) (< 0 w)) (or (<= back1 front1) (not v_assert) (< 0 w) (<= (+ 2 d2 temp2) (* 2 W))) (or (<= back1 front1) (not v_assert) (< 0 w) (= front2 back2))), 134050#(and (or (not v_assert) (not (< front1 back1)) (<= back2 front2)) (or (not v_assert) (not (< front1 back1)) (<= front2 back2)) (or (not v_assert) (not (< front1 back1)) (= (select queue1 (+ front1 1)) 1)) (or (not v_assert) (not (< front1 back1)) (= (select queue1 front1) 1)) (or (not v_assert) (not (< front1 back1)) (<= (+ d2 4) (* 2 W)))), 134071#(and (or (<= back1 front1) (<= (+ d2 (select queue2 front2)) (* 2 W)) (< 0 w) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (<= back1 front1) (<= (+ d2 (select queue2 front2)) (* 2 W)) v_assert (not (= (+ (select queue1 front1) 1) (select queue2 back2))))), 134091#(and (or (not v_assert) (<= back2 front2)) (or (not v_assert) (<= front2 back2)) (or (<= (+ d2 (* 2 w)) (* 2 W)) (not v_assert)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 134072#(and (or (<= back1 front1) (< 0 w) (<= (+ 2 d2 temp2) (* 2 W))) (or (<= back1 front1) (< 0 w) (= front2 back2)) (or (<= back1 front1) (= (+ (- 1) (select queue1 front1)) 0) v_assert) (or (<= back1 front1) v_assert (<= (+ 2 d2 temp2) (* 2 W))) (or (<= back1 front1) (= (+ (- 1) (select queue1 front1)) 0) (< 0 w)) (or (<= back1 front1) v_assert (= front2 back2))), 134101#(and (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 134070#(and (or (= (+ (- 1) temp1) 0) (< 0 w)) (or (< 0 w) (= front2 back2)) (or v_assert (<= (+ 2 d2 temp2) (* 2 W))) (or v_assert (= front2 back2)) (or (< 0 w) (<= (+ 2 d2 temp2) (* 2 W))) (or v_assert (= (+ (- 1) temp1) 0))), 134089#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (<= (+ 2 d2 temp2 (* 2 w)) (* 2 W))) (or (not v_assert) (<= back1 (+ front1 1))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ front1 1) back1))), 134088#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (<= back1 (+ front1 1))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ 2 d2 (* 2 w)) (* 2 W))) (or (not v_assert) (<= (+ front1 1) back1))), 134102#(and (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= (+ 2 d2 (* 2 w)) (* 2 W))) (or (not v_assert) (= (+ back2 (* (- 1) front2)) 0)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 134065#(and (or (<= d2 (* 2 W)) v_assert) (or (<= d2 (* 2 W)) (< 0 w))), 134054#(and (or (not v_assert) (not (< front1 back1)) (<= back2 front2)) (or (not v_assert) (<= (+ d2 temp2 4) (* 2 W)) (not (< front1 back1))) (or (not v_assert) (not (< front1 back1)) (<= front2 back2)) (or (not v_assert) (not (< front1 back1)) (= (select queue1 (+ front1 1)) 1)) (or (not v_assert) (not (< front1 back1)) (= (select queue1 front1) 1))), 134076#(and (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (not v_assert) (<= back2 (+ front2 1)) (< 0 w)) (or (not v_assert) (< 0 w) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ front2 1) back2) (< 0 w))), 134049#(and (or (not (< front1 back1)) (<= front2 back2)) (or (not (< front1 back1)) (= (select queue1 (+ front1 1)) 1)) (or (not (< front1 back1)) (<= (+ d2 4) (* 2 W))) (or (not (< front1 back1)) (<= back2 front2)) (or (not (< front1 back1)) (= (select queue1 front1) 1))), 134079#(and (or (<= back2 front2) (< 0 w)) (or (< 0 w) (= (select queue1 front1) 1)) (or v_assert (<= back2 front2)) (or (< 0 w) (<= (+ d2 4) (* 2 W))) (or v_assert (= (select queue1 front1) 1)) (or (= temp1 1) (< 0 w)) (or v_assert (<= front2 back2)) (or (= temp1 1) v_assert) (or (<= front2 back2) (< 0 w)) (or v_assert (<= (+ d2 4) (* 2 W)))), 134056#(and (or (not v_assert) (not (< front1 back1)) (= (select queue1 (+ front1 1)) 1) (not (< front2 back2))) (or (not v_assert) (not (< front1 back1)) (<= (+ d2 (select queue2 front2) 4) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (not (< front1 back1)) (not (< front2 back2)) (= (select queue1 front1) 1)) (or (not v_assert) (not (< front1 back1)) (<= back2 (+ front2 1)))), 134053#(and (or (not v_assert) (<= (+ d2 temp2 4) (* 2 W))) (or (not v_assert) (= temp1 1)) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= back2 front2)) (or (not v_assert) (<= front2 back2))), 134062#(and (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= back2 front2)) (or (not v_assert) (<= front2 back2)) (or (not v_assert) (= (select queue1 (+ front1 1)) 1)) (or (not v_assert) (<= (+ d2 4) (* 2 W)))), 134087#(and (or (not v_assert) (<= (+ front1 1) back1) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ d2 (select queue2 front2) 4) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (not (< front2 back2)) (= (select queue1 front1) 1)) (or (not v_assert) (<= back1 (+ front1 1)) (not (< front2 back2)))), 134074#(and (or (<= back2 (+ front2 1)) (< 0 w)) (or (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (< 0 w) (= (select queue1 front1) 1)) (or v_assert (<= (+ front2 1) back2)) (or (<= (+ front2 1) back2) (< 0 w)) (or v_assert (= (select queue1 front1) 1)) (or (<= back2 (+ front2 1)) v_assert) (or (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) v_assert)), 134077#(or (<= back1 front1) (<= (+ d2 (select queue2 front2)) (* 2 W)) (not v_assert) (< 0 w) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))), 134052#(and (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)))), 134080#(and (or (not v_assert) (<= back2 front2) (< 0 w)) (or (not v_assert) (< 0 w) (<= (+ d2 4) (* 2 W))) (or (not v_assert) (<= front2 back2) (< 0 w)) (or (not v_assert) (< 0 w) (= (select queue1 front1) 1)) (or (not v_assert) (= temp1 1) (< 0 w))), 134083#(and (or (not v_assert) (<= back2 front2) (< 0 w)) (or (not v_assert) (<= (+ d2 temp2 4) (* 2 W)) (< 0 w)) (or (not v_assert) (<= front2 back2) (< 0 w)) (or (not v_assert) (< 0 w) (= (select queue1 front1) 1)) (or (not v_assert) (= temp1 1) (< 0 w))), 134092#(and (or (not v_assert) (<= (+ d2 temp2 (* 2 w)) (* 2 W))) (or (not v_assert) (<= back2 front2)) (or (not v_assert) (<= front2 back2)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 134086#(and (or (not v_assert) (<= (+ d2 temp2 4) (* 2 W))) (or (not v_assert) (<= back1 (+ front1 1))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= back2 front2)) (or (not v_assert) (<= (+ front1 1) back1)) (or (not v_assert) (<= front2 back2))), 134059#(or (<= back1 front1) (<= (+ d2 (select queue2 front2)) (* 2 W)) (not v_assert) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))), 134067#(and (or (<= (+ d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ d2 (select queue2 front2)) (* 2 W)) v_assert)), 134055#(and (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ d2 (select queue2 front2) 4) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (not (< front2 back2)) (= (select queue1 front1) 1)) (or (not v_assert) (= temp1 1) (not (< front2 back2)))), 134046#(and (or (not v_assert) (= (+ (- 1) temp1) 0)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)))), 134061#(and (or (<= back1 front1) (not v_assert) (= (+ (- 1) (select queue1 front1)) 0)) (or (<= back1 front1) (not v_assert) (= front2 back2)) (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 temp2) (* 2 W)))), 134093#(and (or (not v_assert) (= (+ (* (- 1) front1) back1) 0) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1))) (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert) (not (< front2 back2)))), 134097#(and (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (+ back2 1) (+ front2 1))) (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 front2) (* 2 w)) (* 2 W))) (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (<= back1 (+ front1 1))) (or (not v_assert) (not (< front2 (+ back2 1))) (<= (+ front1 1) back1) (not (= (select queue2 back2) (+ temp1 1))))), 134047#(and (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)))), 134064#(and (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ d2 (select queue2 front2) 4) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (not (< front2 back2)) (= (select queue1 front1) 1)) (or (not v_assert) (= (select queue1 (+ front1 1)) 1) (not (< front2 back2)))), 134069#(and (or (<= (+ d2 (select queue2 front2)) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1))) (< 0 w)) (or (<= (+ d2 (select queue2 front2)) (* 2 W)) v_assert (not (= (select queue2 back2) (+ temp1 1))))), 134099#(and (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert) (not (< front1 back1)) (not (< front2 (+ back2 1))) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (= (+ (- 1) (* (- 1) front1) back1) 0) (not (< front2 (+ back2 1))) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (<= back2 front2) (not (= (+ (select queue1 front1) 1) (select queue2 back2))))), 134081#(and (or (not v_assert) (<= back2 (+ front2 1)) (< 0 w)) (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (not v_assert) (= (+ (- 1) temp1) 0) (< 0 w)) (or (not v_assert) (<= (+ front2 1) back2) (< 0 w))), 134090#(and (or (not v_assert) (= back2 (+ front2 1)) (not (< front2 back2))) (or (not v_assert) (<= (+ front1 1) back1) (not (< front2 back2))) (or (not v_assert) (not (< front2 back2)) (= (select queue1 front1) 1)) (or (not v_assert) (<= back1 (+ front1 1)) (not (< front2 back2))) (or (not v_assert) (not (< front2 back2)) (<= (+ 2 d2 (select queue2 front2) (* 2 w)) (* 2 W)))), 134075#(and (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (not v_assert) (<= back2 (+ front2 1)) (< 0 w)) (or (not v_assert) (= (+ (- 1) temp1) 0) (< 0 w)) (or (not v_assert) (<= (+ front2 1) back2) (< 0 w))), 134082#(and (or (not v_assert) (<= back2 (+ front2 1)) (< 0 w)) (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (not v_assert) (< 0 w) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ front2 1) back2) (< 0 w))), 134094#(and (or (not v_assert) (not (< front1 back1)) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (not v_assert) (not (< front1 back1)) (= (select queue1 (+ front1 1)) 1) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (< front1 back1)) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (not (< front1 back1)) (not (< front2 (+ back2 1))) (<= (+ d2 (select queue2 front2) 4) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1))))), 134085#(and (or (not v_assert) (<= back1 (+ front1 1))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= back2 front2)) (or (not v_assert) (<= (+ front1 1) back1)) (or (not v_assert) (<= front2 back2)) (or (not v_assert) (<= (+ d2 4) (* 2 W)))), 134095#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (= (select queue1 (+ front1 1)) 1) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (< front2 (+ back2 1))) (<= (+ d2 (select queue2 front2) 4) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1))), 134066#(and (or (<= (+ d2 temp2) (* 2 W)) v_assert) (or (<= (+ d2 temp2) (* 2 W)) (< 0 w))), 134060#(and (or (<= back1 front1) (= front2 back2)) (or (<= back1 front1) (<= (+ 2 d2 temp2) (* 2 W))) (or (<= back1 front1) (= (+ (- 1) (select queue1 front1)) 0))), 134096#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (not (< front2 (+ back2 1))) (<= (+ d2 (select queue2 front2) 4) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (<= back1 (+ front1 1))) (or (not v_assert) (not (< front2 (+ back2 1))) (<= (+ front1 1) back1) (not (= (select queue2 back2) (+ temp1 1))))), 134084#(and (or (not v_assert) (< 0 w) (not (< front2 back2)) (= (select queue1 front1) 1)) (or (not v_assert) (<= back2 (+ front2 1)) (< 0 w)) (or (not v_assert) (<= (+ d2 (select queue2 front2) 4) (* 2 W)) (< 0 w) (not (< front2 back2))) (or (not v_assert) (= temp1 1) (< 0 w) (not (< front2 back2)))), 134073#(and (or (= (+ (- 1) temp1) 0) (< 0 w)) (or (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (= back2 (+ front2 1)) (< 0 w)) (or (= back2 (+ front2 1)) v_assert) (or (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) v_assert) (or v_assert (= (+ (- 1) temp1) 0))), 134057#(or (<= (+ d2 (select queue2 front2)) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1)))), 134063#(and (or (not v_assert) (<= (+ d2 temp2 4) (* 2 W))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= back2 front2)) (or (not v_assert) (<= front2 back2)) (or (not v_assert) (= (select queue1 (+ front1 1)) 1))), 134100#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (= front1 back1)) (or (not v_assert) (= W w)) (or (not v_assert) (<= d2 0))), 134051#(and (or (not v_assert) (= (+ (- 1) temp1) 0)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)))), 134048#(and (or (not v_assert) (= temp1 1)) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= back2 front2)) (or (not v_assert) (<= front2 back2)) (or (not v_assert) (<= (+ d2 4) (* 2 W)))), 134068#(and (or (<= (+ d2 temp2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ d2 temp2 (select queue2 front2)) (* 2 W)) v_assert)), 134058#(or (<= back1 front1) (<= (+ d2 (select queue2 front2)) (* 2 W)) (not (= (+ (select queue1 front1) 1) (select queue2 back2))))] [2022-03-15 21:37:11,821 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 76 states [2022-03-15 21:37:11,822 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:37:11,822 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 76 interpolants. [2022-03-15 21:37:11,823 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1049, Invalid=10081, Unknown=0, NotChecked=0, Total=11130 [2022-03-15 21:37:11,823 INFO L87 Difference]: Start difference. First operand 4673 states and 15744 transitions. Second operand has 76 states, 76 states have (on average 4.5394736842105265) internal successors, (345), 75 states have internal predecessors, (345), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:37:25,955 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:37:25,955 INFO L93 Difference]: Finished difference Result 16072 states and 54117 transitions. [2022-03-15 21:37:25,956 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 102 states. [2022-03-15 21:37:25,956 INFO L78 Accepts]: Start accepts. Automaton has has 76 states, 76 states have (on average 4.5394736842105265) internal successors, (345), 75 states have internal predecessors, (345), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 38 [2022-03-15 21:37:25,956 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:37:25,990 INFO L225 Difference]: With dead ends: 16072 [2022-03-15 21:37:25,990 INFO L226 Difference]: Without dead ends: 15713 [2022-03-15 21:37:25,992 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 528 GetRequests, 269 SyntacticMatches, 56 SemanticMatches, 203 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16156 ImplicationChecksByTransitivity, 17.1s TimeCoverageRelationStatistics Valid=5078, Invalid=36742, Unknown=0, NotChecked=0, Total=41820 [2022-03-15 21:37:25,992 INFO L933 BasicCegarLoop]: 1 mSDtfsCounter, 2120 mSDsluCounter, 2322 mSDsCounter, 0 mSdLazyCounter, 8133 mSolverCounterSat, 1347 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 3.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2120 SdHoareTripleChecker+Valid, 3 SdHoareTripleChecker+Invalid, 9480 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1347 IncrementalHoareTripleChecker+Valid, 8133 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 3.5s IncrementalHoareTripleChecker+Time [2022-03-15 21:37:25,992 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [2120 Valid, 3 Invalid, 9480 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1347 Valid, 8133 Invalid, 0 Unknown, 0 Unchecked, 3.5s Time] [2022-03-15 21:37:26,005 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15713 states. [2022-03-15 21:37:26,111 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15713 to 5414. [2022-03-15 21:37:26,119 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5414 states, 5413 states have (on average 3.369480879364493) internal successors, (18239), 5413 states have internal predecessors, (18239), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:37:26,131 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5414 states to 5414 states and 18239 transitions. [2022-03-15 21:37:26,132 INFO L78 Accepts]: Start accepts. Automaton has 5414 states and 18239 transitions. Word has length 38 [2022-03-15 21:37:26,132 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:37:26,132 INFO L470 AbstractCegarLoop]: Abstraction has 5414 states and 18239 transitions. [2022-03-15 21:37:26,132 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 76 states, 76 states have (on average 4.5394736842105265) internal successors, (345), 75 states have internal predecessors, (345), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:37:26,132 INFO L276 IsEmpty]: Start isEmpty. Operand 5414 states and 18239 transitions. [2022-03-15 21:37:26,141 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2022-03-15 21:37:26,141 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:37:26,141 INFO L514 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:37:26,159 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Forceful destruction successful, exit code 0 [2022-03-15 21:37:26,359 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable15 [2022-03-15 21:37:26,360 INFO L402 AbstractCegarLoop]: === Iteration 17 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION (and 1 more)] === [2022-03-15 21:37:26,360 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:37:26,360 INFO L85 PathProgramCache]: Analyzing trace with hash 349388989, now seen corresponding path program 13 times [2022-03-15 21:37:26,361 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:37:26,362 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [467345823] [2022-03-15 21:37:26,362 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:37:26,362 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:37:26,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:37:26,669 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 3 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:37:26,669 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:37:26,669 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [467345823] [2022-03-15 21:37:26,669 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [467345823] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:37:26,669 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [292095800] [2022-03-15 21:37:26,670 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-03-15 21:37:26,670 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:37:26,670 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:37:26,671 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:37:26,671 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2022-03-15 21:37:26,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:37:26,703 INFO L263 TraceCheckSpWp]: Trace formula consists of 143 conjuncts, 43 conjunts are in the unsatisfiable core [2022-03-15 21:37:26,704 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:37:27,254 INFO L353 Elim1Store]: treesize reduction 32, result has 3.0 percent of original size [2022-03-15 21:37:27,255 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 49 treesize of output 29 [2022-03-15 21:37:27,423 INFO L353 Elim1Store]: treesize reduction 32, result has 3.0 percent of original size [2022-03-15 21:37:27,424 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 38 treesize of output 18 [2022-03-15 21:37:27,493 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 3 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:37:27,493 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:37:28,005 INFO L353 Elim1Store]: treesize reduction 76, result has 52.8 percent of original size [2022-03-15 21:37:28,005 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 0 disjoint index pairs (out of 15 index pairs), introduced 6 new quantified variables, introduced 15 case distinctions, treesize of input 52 treesize of output 116 [2022-03-15 21:37:28,597 INFO L353 Elim1Store]: treesize reduction 76, result has 52.8 percent of original size [2022-03-15 21:37:28,598 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 0 disjoint index pairs (out of 15 index pairs), introduced 6 new quantified variables, introduced 15 case distinctions, treesize of input 47 treesize of output 111 [2022-03-15 21:37:29,291 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 9 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:37:29,291 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [292095800] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:37:29,291 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:37:29,291 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 19, 19] total 47 [2022-03-15 21:37:29,291 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [120953601] [2022-03-15 21:37:29,291 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:37:29,294 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:37:29,360 INFO L252 McrAutomatonBuilder]: Finished intersection with 345 states and 871 transitions. [2022-03-15 21:37:29,360 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:37:49,176 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 51 new interpolants: [161484#(and (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= back2 front2)) (or (not v_assert) (<= front2 back2)) (or (not v_assert) (= (select queue1 (+ front1 1)) 1)) (or (not v_assert) (<= (+ d2 4) (* 2 W)))), 161485#(and (or (not v_assert) (<= (+ d2 temp2 4) (* 2 W))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= back2 front2)) (or (not v_assert) (<= front2 back2)) (or (not v_assert) (= (select queue1 (+ front1 1)) 1))), 161478#(and (or (not v_assert) (= (+ (- 1) temp1) 0)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)))), 161476#(and (or (not v_assert) (= temp1 1)) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= back2 front2)) (or (not v_assert) (<= front2 back2)) (or (not v_assert) (<= (+ d2 4) (* 2 W)))), 161518#(and (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert) (not (< front1 back1)) (not (< front2 (+ back2 1))) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (= (+ (- 1) (* (- 1) front1) back1) 0) (not (< front2 (+ back2 1))) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (<= back2 front2) (not (= (+ (select queue1 front1) 1) (select queue2 back2))))), 161471#(and (or (not (< front1 back1)) (<= front2 back2)) (or (not (< front1 back1)) (= (select queue1 (+ front1 1)) 1)) (or (not (< front1 back1)) (<= (+ d2 4) (* 2 W))) (or (not (< front1 back1)) (<= back2 front2)) (or (not (< front1 back1)) (= (select queue1 front1) 1))), 161515#(and (or (not v_assert) (<= (+ d2 temp2 (* 2 w)) (* 2 W))) (or (not v_assert) (<= back2 front2)) (or (not v_assert) (<= front2 back2)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 161509#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (not (< front2 (+ back2 1))) (<= (+ d2 (select queue2 front2) 4) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (<= back1 (+ front1 1))) (or (not v_assert) (not (< front2 (+ back2 1))) (<= (+ front1 1) back1) (not (= (select queue2 back2) (+ temp1 1))))), 161506#(and (or (not v_assert) (<= (+ front1 1) back1) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ d2 (select queue2 front2) 4) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (not (< front2 back2)) (= (select queue1 front1) 1)) (or (not v_assert) (<= back1 (+ front1 1)) (not (< front2 back2)))), 161508#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (= (select queue1 (+ front1 1)) 1) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (< front2 (+ back2 1))) (<= (+ d2 (select queue2 front2) 4) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1))), 161516#(and (or (not v_assert) (= (+ (* (- 1) front1) back1) 0) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1))) (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert) (not (< front2 back2)))), 161475#(and (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)))), 161490#(and (or (<= (+ d2 temp2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ d2 temp2 (select queue2 front2)) (* 2 W)) v_assert)), 161513#(and (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (+ back2 1) (+ front2 1))) (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 front2) (* 2 w)) (* 2 W))) (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (<= back1 (+ front1 1))) (or (not v_assert) (not (< front2 (+ back2 1))) (<= (+ front1 1) back1) (not (= (select queue2 back2) (+ temp1 1))))), 161520#(and (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 161479#(and (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)))), 161499#(or (not v_assert) (<= (+ d2 temp2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w)), 161494#(or (not v_assert) (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w)), 161507#(and (or (not v_assert) (not (< front1 back1)) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (not v_assert) (not (< front1 back1)) (= (select queue1 (+ front1 1)) 1) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (< front1 back1)) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (not (< front1 back1)) (not (< front2 (+ back2 1))) (<= (+ d2 (select queue2 front2) 4) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1))))), 161487#(and (or (<= d2 (* 2 W)) v_assert) (or (<= d2 (* 2 W)) (< 0 w))), 161511#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (<= (+ 2 d2 temp2 (* 2 w)) (* 2 W))) (or (not v_assert) (<= back1 (+ front1 1))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ front1 1) back1))), 161497#(and (or (<= back2 front2) (< 0 w)) (or (< 0 w) (= (select queue1 front1) 1)) (or v_assert (<= back2 front2)) (or (< 0 w) (<= (+ d2 4) (* 2 W))) (or v_assert (= (select queue1 front1) 1)) (or (= temp1 1) (< 0 w)) (or v_assert (<= front2 back2)) (or (= temp1 1) v_assert) (or (<= front2 back2) (< 0 w)) (or v_assert (<= (+ d2 4) (* 2 W)))), 161504#(and (or (not v_assert) (<= back1 (+ front1 1))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= back2 front2)) (or (not v_assert) (<= (+ front1 1) back1)) (or (not v_assert) (<= front2 back2)) (or (not v_assert) (<= (+ d2 4) (* 2 W)))), 161474#(and (or (not v_assert) (= (+ (- 1) temp1) 0)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)))), 161500#(and (or (not v_assert) (<= back2 (+ front2 1)) (< 0 w)) (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (not v_assert) (= (+ (- 1) temp1) 0) (< 0 w)) (or (not v_assert) (<= (+ front2 1) back2) (< 0 w))), 161483#(and (or (not v_assert) (not (< front1 back1)) (= (select queue1 (+ front1 1)) 1) (not (< front2 back2))) (or (not v_assert) (not (< front1 back1)) (<= (+ d2 (select queue2 front2) 4) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (not (< front1 back1)) (not (< front2 back2)) (= (select queue1 front1) 1)) (or (not v_assert) (not (< front1 back1)) (<= back2 (+ front2 1)))), 161521#(and (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= (+ 2 d2 (* 2 w)) (* 2 W))) (or (not v_assert) (= (+ back2 (* (- 1) front2)) 0)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 161473#(or (not v_assert) (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))), 161505#(and (or (not v_assert) (<= (+ d2 temp2 4) (* 2 W))) (or (not v_assert) (<= back1 (+ front1 1))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= back2 front2)) (or (not v_assert) (<= (+ front1 1) back1)) (or (not v_assert) (<= front2 back2))), 161477#(or (not v_assert) (<= (+ d2 temp2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))), 161482#(and (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ d2 (select queue2 front2) 4) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (not (< front2 back2)) (= (select queue1 front1) 1)) (or (not v_assert) (= temp1 1) (not (< front2 back2)))), 161480#(and (or (not v_assert) (<= (+ d2 temp2 4) (* 2 W))) (or (not v_assert) (= temp1 1)) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= back2 front2)) (or (not v_assert) (<= front2 back2))), 161495#(and (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (not v_assert) (<= back2 (+ front2 1)) (< 0 w)) (or (not v_assert) (= (+ (- 1) temp1) 0) (< 0 w)) (or (not v_assert) (<= (+ front2 1) back2) (< 0 w))), 161519#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (= front1 back1)) (or (not v_assert) (= W w)) (or (not v_assert) (<= d2 0))), 161501#(and (or (not v_assert) (<= back2 (+ front2 1)) (< 0 w)) (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (not v_assert) (< 0 w) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ front2 1) back2) (< 0 w))), 161493#(and (or (<= back2 (+ front2 1)) (< 0 w)) (or (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (< 0 w) (= (select queue1 front1) 1)) (or v_assert (<= (+ front2 1) back2)) (or (<= (+ front2 1) back2) (< 0 w)) (or v_assert (= (select queue1 front1) 1)) (or (<= back2 (+ front2 1)) v_assert) (or (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) v_assert)), 161491#(and (or (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) v_assert)), 161498#(and (or (not v_assert) (<= back2 front2) (< 0 w)) (or (not v_assert) (< 0 w) (<= (+ d2 4) (* 2 W))) (or (not v_assert) (<= front2 back2) (< 0 w)) (or (not v_assert) (< 0 w) (= (select queue1 front1) 1)) (or (not v_assert) (= temp1 1) (< 0 w))), 161503#(and (or (not v_assert) (< 0 w) (not (< front2 back2)) (= (select queue1 front1) 1)) (or (not v_assert) (<= back2 (+ front2 1)) (< 0 w)) (or (not v_assert) (<= (+ d2 (select queue2 front2) 4) (* 2 W)) (< 0 w) (not (< front2 back2))) (or (not v_assert) (= temp1 1) (< 0 w) (not (< front2 back2)))), 161514#(and (or (not v_assert) (<= back2 front2)) (or (not v_assert) (<= front2 back2)) (or (<= (+ d2 (* 2 w)) (* 2 W)) (not v_assert)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 161488#(and (or (<= (+ d2 temp2) (* 2 W)) v_assert) (or (<= (+ d2 temp2) (* 2 W)) (< 0 w))), 161510#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (<= back1 (+ front1 1))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ 2 d2 (* 2 w)) (* 2 W))) (or (not v_assert) (<= (+ front1 1) back1))), 161512#(and (or (not v_assert) (= back2 (+ front2 1)) (not (< front2 back2))) (or (not v_assert) (<= (+ front1 1) back1) (not (< front2 back2))) (or (not v_assert) (not (< front2 back2)) (= (select queue1 front1) 1)) (or (not v_assert) (<= back1 (+ front1 1)) (not (< front2 back2))) (or (not v_assert) (not (< front2 back2)) (<= (+ 2 d2 (select queue2 front2) (* 2 w)) (* 2 W)))), 161502#(and (or (not v_assert) (<= back2 front2) (< 0 w)) (or (not v_assert) (<= (+ d2 temp2 4) (* 2 W)) (< 0 w)) (or (not v_assert) (<= front2 back2) (< 0 w)) (or (not v_assert) (< 0 w) (= (select queue1 front1) 1)) (or (not v_assert) (= temp1 1) (< 0 w))), 161489#(and (or (<= (+ d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ d2 (select queue2 front2)) (* 2 W)) v_assert)), 161481#(and (or (not v_assert) (not (< front1 back1)) (<= back2 front2)) (or (not v_assert) (<= (+ d2 temp2 4) (* 2 W)) (not (< front1 back1))) (or (not v_assert) (not (< front1 back1)) (<= front2 back2)) (or (not v_assert) (not (< front1 back1)) (= (select queue1 (+ front1 1)) 1)) (or (not v_assert) (not (< front1 back1)) (= (select queue1 front1) 1))), 161496#(and (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (not v_assert) (<= back2 (+ front2 1)) (< 0 w)) (or (not v_assert) (< 0 w) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ front2 1) back2) (< 0 w))), 161486#(and (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ d2 (select queue2 front2) 4) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (not (< front2 back2)) (= (select queue1 front1) 1)) (or (not v_assert) (= (select queue1 (+ front1 1)) 1) (not (< front2 back2)))), 161472#(and (or (not v_assert) (not (< front1 back1)) (<= back2 front2)) (or (not v_assert) (not (< front1 back1)) (<= front2 back2)) (or (not v_assert) (not (< front1 back1)) (= (select queue1 (+ front1 1)) 1)) (or (not v_assert) (not (< front1 back1)) (= (select queue1 front1) 1)) (or (not v_assert) (not (< front1 back1)) (<= (+ d2 4) (* 2 W)))), 161517#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (+ (* (- 1) front1) back1) 0))), 161492#(and (or (= (+ (- 1) temp1) 0) (< 0 w)) (or (<= back2 (+ front2 1)) (< 0 w)) (or (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or v_assert (<= (+ front2 1) back2)) (or (<= (+ front2 1) back2) (< 0 w)) (or (<= back2 (+ front2 1)) v_assert) (or (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) v_assert) (or v_assert (= (+ (- 1) temp1) 0)))] [2022-03-15 21:37:49,177 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 70 states [2022-03-15 21:37:49,177 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:37:49,177 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2022-03-15 21:37:49,177 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=705, Invalid=8997, Unknown=0, NotChecked=0, Total=9702 [2022-03-15 21:37:49,178 INFO L87 Difference]: Start difference. First operand 5414 states and 18239 transitions. Second operand has 70 states, 70 states have (on average 4.5) internal successors, (315), 69 states have internal predecessors, (315), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:38:01,530 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:38:01,530 INFO L93 Difference]: Finished difference Result 13634 states and 45906 transitions. [2022-03-15 21:38:01,531 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 90 states. [2022-03-15 21:38:01,531 INFO L78 Accepts]: Start accepts. Automaton has has 70 states, 70 states have (on average 4.5) internal successors, (315), 69 states have internal predecessors, (315), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 38 [2022-03-15 21:38:01,531 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:38:01,565 INFO L225 Difference]: With dead ends: 13634 [2022-03-15 21:38:01,565 INFO L226 Difference]: Without dead ends: 13477 [2022-03-15 21:38:01,567 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 486 GetRequests, 248 SyntacticMatches, 54 SemanticMatches, 184 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12539 ImplicationChecksByTransitivity, 14.4s TimeCoverageRelationStatistics Valid=3437, Invalid=30973, Unknown=0, NotChecked=0, Total=34410 [2022-03-15 21:38:01,568 INFO L933 BasicCegarLoop]: 1 mSDtfsCounter, 1627 mSDsluCounter, 2712 mSDsCounter, 0 mSdLazyCounter, 9425 mSolverCounterSat, 952 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 3.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1627 SdHoareTripleChecker+Valid, 3 SdHoareTripleChecker+Invalid, 10377 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 952 IncrementalHoareTripleChecker+Valid, 9425 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 3.8s IncrementalHoareTripleChecker+Time [2022-03-15 21:38:01,568 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [1627 Valid, 3 Invalid, 10377 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [952 Valid, 9425 Invalid, 0 Unknown, 0 Unchecked, 3.8s Time] [2022-03-15 21:38:01,583 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13477 states. [2022-03-15 21:38:01,690 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13477 to 5092. [2022-03-15 21:38:01,697 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5092 states, 5091 states have (on average 3.374779021803182) internal successors, (17181), 5091 states have internal predecessors, (17181), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:38:01,752 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5092 states to 5092 states and 17181 transitions. [2022-03-15 21:38:01,753 INFO L78 Accepts]: Start accepts. Automaton has 5092 states and 17181 transitions. Word has length 38 [2022-03-15 21:38:01,753 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:38:01,753 INFO L470 AbstractCegarLoop]: Abstraction has 5092 states and 17181 transitions. [2022-03-15 21:38:01,753 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 70 states, 70 states have (on average 4.5) internal successors, (315), 69 states have internal predecessors, (315), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:38:01,753 INFO L276 IsEmpty]: Start isEmpty. Operand 5092 states and 17181 transitions. [2022-03-15 21:38:01,761 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2022-03-15 21:38:01,761 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:38:01,761 INFO L514 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:38:01,780 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Forceful destruction successful, exit code 0 [2022-03-15 21:38:01,962 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 14 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable16 [2022-03-15 21:38:01,962 INFO L402 AbstractCegarLoop]: === Iteration 18 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION (and 1 more)] === [2022-03-15 21:38:01,963 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:38:01,963 INFO L85 PathProgramCache]: Analyzing trace with hash -117159065, now seen corresponding path program 14 times [2022-03-15 21:38:01,963 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:38:01,963 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1625420085] [2022-03-15 21:38:01,963 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:38:01,963 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:38:01,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:38:02,315 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 3 proven. 29 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-03-15 21:38:02,316 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:38:02,316 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1625420085] [2022-03-15 21:38:02,316 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1625420085] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:38:02,316 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [701454887] [2022-03-15 21:38:02,316 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-03-15 21:38:02,316 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:38:02,316 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:38:02,317 INFO L229 MonitoredProcess]: Starting monitored process 15 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:38:02,317 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2022-03-15 21:38:02,350 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-03-15 21:38:02,350 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:38:02,351 INFO L263 TraceCheckSpWp]: Trace formula consists of 143 conjuncts, 43 conjunts are in the unsatisfiable core [2022-03-15 21:38:02,352 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:38:03,093 INFO L353 Elim1Store]: treesize reduction 32, result has 3.0 percent of original size [2022-03-15 21:38:03,094 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 51 treesize of output 31 [2022-03-15 21:38:03,188 INFO L353 Elim1Store]: treesize reduction 32, result has 3.0 percent of original size [2022-03-15 21:38:03,188 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 38 treesize of output 18 [2022-03-15 21:38:03,254 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 8 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:38:03,254 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:38:03,827 INFO L353 Elim1Store]: treesize reduction 76, result has 52.8 percent of original size [2022-03-15 21:38:03,827 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 0 disjoint index pairs (out of 15 index pairs), introduced 6 new quantified variables, introduced 15 case distinctions, treesize of input 52 treesize of output 116 [2022-03-15 21:38:04,640 INFO L353 Elim1Store]: treesize reduction 76, result has 52.8 percent of original size [2022-03-15 21:38:04,640 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 0 disjoint index pairs (out of 15 index pairs), introduced 6 new quantified variables, introduced 15 case distinctions, treesize of input 47 treesize of output 111 [2022-03-15 21:38:05,224 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 4 proven. 29 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:38:05,225 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [701454887] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:38:05,225 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:38:05,225 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 19, 19] total 48 [2022-03-15 21:38:05,225 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [161753448] [2022-03-15 21:38:05,225 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:38:05,228 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:38:05,308 INFO L252 McrAutomatonBuilder]: Finished intersection with 379 states and 974 transitions. [2022-03-15 21:38:05,308 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:38:30,054 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 62 new interpolants: [185796#(and (or (<= back1 front1) (not v_assert) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (< front2 (+ back2 1))) (or (<= back1 front1) (not v_assert) (<= back2 front2)) (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 temp2) (* 2 W)))), 185821#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (not (< front2 (+ back2 1))) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (+ (* (- 1) front1) back1) 0))), 185823#(and (or (= (+ (* (- 1) front1) back1) 0) (not (< front2 back2))) (or (not (< front2 back2)) (<= (+ 2 d2 (select queue2 front2) (* 2 w)) (* 2 W))) (<= back2 (+ front2 1)) (or (= temp1 1) (not (< front2 back2)))), 185810#(or (<= (+ d2 (select queue2 front2)) (* 2 W)) (not v_assert) (< 0 w)), 185812#(or (not v_assert) (<= (+ d2 temp2 (select queue2 front2)) (* 2 W)) (< 0 w)), 185845#(and (or (<= back1 front1) (not v_assert) (not (< 0 w)) (not (= (select queue1 back1) 1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (<= (+ d2 (select queue2 front2) (* 2 w)) (+ (* 2 W) 2)) (not (< 0 w)) (<= (+ back1 1) front1) (not (= (select queue1 back1) 1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< 0 w)) (<= (+ back1 1) front1) (not (= (select queue1 back1) 1)) (<= back2 front2) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< 0 w)) (<= (+ back1 1) front1) (not (= (select queue1 back1) 1)) (<= front2 back2) (not (= (+ (select queue1 front1) 1) (select queue2 back2))))), 185818#(and (or (not v_assert) (= (+ (* (- 1) front1) back1) 0) (not (< front2 back2))) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1)))), 185836#(and (or (not v_assert) (<= (+ front1 1) back1) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (not (< front2 back2)) (= (select queue1 front1) 1)) (or (not v_assert) (<= back1 (+ front1 1)) (not (< front2 back2))) (or (not v_assert) (not (< front2 back2)) (<= (+ 2 d2 (select queue2 front2) (* 2 w)) (* 2 W)))), 185817#(and (or (not v_assert) (<= (+ 2 d2 temp2) (* 2 W))) (or (not v_assert) (< front2 (+ back2 1))) (or (not v_assert) (<= back2 front2)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 185822#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (= front1 back1) (not (= (select queue2 back2) (+ temp1 1))) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1)) (not (= (select queue2 back2) (+ temp1 1))))), 185795#(and (or (<= back1 front1) (not v_assert) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (< front2 (+ back2 1))) (or (<= back1 front1) (not v_assert) (<= (+ 2 d2) (* 2 W))) (or (<= back1 front1) (not v_assert) (<= back2 front2))), 185805#(and (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (not (< front2 back2)) (= (select queue1 front1) 1))), 185844#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (<= back1 (+ front1 1))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ 2 d2 (* 2 w)) (* 2 W))) (or (not v_assert) (<= (+ front1 1) back1))), 185785#(and (or (<= d2 (* 2 W)) v_assert) (or (<= d2 (* 2 W)) (< 0 w))), 185841#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1)))) (or (<= back1 front1) (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (< front2 (+ back2 1))) (<= front1 back1) (not (= (select queue2 back2) (+ temp1 1))))), 185786#(and (or (<= (+ d2 temp2) (* 2 W)) v_assert) (or (<= (+ d2 temp2) (* 2 W)) (< 0 w))), 185809#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1)) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (not (< front2 back2)) (= (select queue1 front1) 1))), 185787#(and (or (<= (+ d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ d2 (select queue2 front2)) (* 2 W)) v_assert)), 185793#(and (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (= temp1 1) (not (< front2 back2)))), 185816#(and (or (not v_assert) (<= (+ 2 d2) (* 2 W))) (or (not v_assert) (< front2 (+ back2 1))) (or (not v_assert) (<= back2 front2)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 185837#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 front2) (* 2 w)) (* 2 W))) (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (<= back1 (+ front1 1))) (or (not v_assert) (not (< front2 (+ back2 1))) (<= (+ front1 1) back1) (not (= (select queue2 back2) (+ temp1 1))))), 185835#(and (or (not v_assert) (<= (+ 2 d2 temp2 (* 2 w)) (* 2 W))) (or (not v_assert) (<= back1 (+ front1 1))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= back2 front2)) (or (not v_assert) (<= (+ front1 1) back1)) (or (not v_assert) (<= front2 back2))), 185801#(and (or (<= back1 front1) (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (<= back1 front1) (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (not (< front2 (+ back2 1))) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1))))), 185804#(and (or (not v_assert) (<= (+ 2 d2 temp2) (* 2 W))) (or (not v_assert) (< front2 (+ back2 1))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= back2 front2))), 185830#(and (or (not v_assert) (not (< front1 back1)) (not (< front2 (+ back2 1))) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (= (+ (- 1) (* (- 1) front1) back1) 0) (not (< front2 (+ back2 1))) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (<= back2 front2) (not (= (+ (select queue1 front1) 1) (select queue2 back2))))), 185792#(and (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= (+ 2 d2 temp2) (* 2 W))) (or (not v_assert) (< front2 (+ back2 1))) (or (not v_assert) (<= back2 front2))), 185798#(and (or (<= back1 front1) (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (<= back1 front1) (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))))), 185802#(and (or (<= back1 front1) (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (<= back1 front1) (not v_assert) (<= back2 (+ front2 1)) (not (= (select queue2 back2) (+ temp1 1)))) (or (<= back1 front1) (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (not (< front2 back2)) (= (select queue1 front1) 1))), 185832#(and (or (not v_assert) (not (< front1 back1)) (not (= (+ (select queue1 front1) 1) (select queue2 (+ back2 1)))) (= back1 (+ front1 1)) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (< front1 back1)) (not (= (+ (select queue1 front1) 1) (select queue2 (+ back2 1)))) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))) (or (not v_assert) (not (< front1 back1)) (not (= (+ (select queue1 front1) 1) (select queue2 (+ back2 1)))) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2))), 185843#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= (+ 2 d2 (* 2 w)) (* 2 W))) (or (not v_assert) (<= front1 back1)) (or (<= back1 front1) (not v_assert))), 185794#(and (or (<= back1 front1) (< front2 (+ back2 1))) (or (<= back1 front1) (<= (+ 2 d2) (* 2 W))) (or (<= back1 front1) (<= back2 front2)) (or (<= back1 front1) (= (select queue1 front1) 1))), 185790#(and (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= (+ 2 d2) (* 2 W))) (or (not v_assert) (< front2 (+ back2 1))) (or (not v_assert) (<= back2 front2))), 185846#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (= front1 back1)) (or (not v_assert) (= W w)) (or (not v_assert) (<= d2 0))), 185840#(and (or (not v_assert) (<= front1 back1) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1))) (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert) (not (< front2 back2))) (or (<= back1 front1) (not v_assert) (not (< front2 back2)))), 185813#(and (or (not v_assert) (<= back2 front2) (< 0 w)) (or (not v_assert) (< front2 (+ back2 1)) (< 0 w)) (or (not v_assert) (< 0 w) (<= (+ 2 d2 temp2) (* 2 W))) (or (not v_assert) (= temp1 1) (< 0 w))), 185827#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert) (not (= (select queue2 back2) (+ temp1 1)))) (or (<= back1 front1) (not v_assert) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (<= front1 back1) (not (= (select queue2 back2) (+ temp1 1))))), 185803#(and (or (not v_assert) (<= (+ 2 d2) (* 2 W))) (or (not v_assert) (< front2 (+ back2 1))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= back2 front2))), 185797#(and (or (<= back1 front1) (not v_assert) (not (< front2 back2)) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (<= back2 (+ front2 1))) (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (< front2 back2)))), 185826#(and (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= front1 back1)) (or (not v_assert) (<= (+ front2 1) back2)) (or (<= back1 front1) (not v_assert))), 185806#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))))), 185788#(and (or (<= back2 front2) (< 0 w)) (or (< front2 (+ back2 1)) v_assert) (or v_assert (<= back2 front2)) (or v_assert (<= (+ 2 d2) (* 2 W))) (or (< front2 (+ back2 1)) (< 0 w)) (or (= temp1 1) (< 0 w)) (or (= temp1 1) v_assert) (or (< 0 w) (<= (+ 2 d2) (* 2 W)))), 185833#(and (or (not (< front2 back2)) (<= (+ 2 d2 (select queue2 front2) (* 2 w)) (* 2 W))) (or (<= (+ front1 1) back1) (not (< front2 back2))) (<= back2 (+ front2 1)) (or (not (< front2 back2)) (= (select queue1 front1) 1)) (or (<= back1 (+ front1 1)) (not (< front2 back2)))), 185831#(and (or (not v_assert) (not (< front1 back1)) (<= back2 (+ front2 1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (not (= (+ (select queue1 front1) 1) (select queue2 back2))) (not (< front2 back2))) (or (not v_assert) (not (< front1 back1)) (= back1 (+ front1 1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2))) (not (< front2 back2)))), 185808#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (not v_assert) (not (< front2 (+ back2 1))) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1))))), 185791#(or (not v_assert) (<= (+ d2 temp2 (select queue2 front2)) (* 2 W))), 185820#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (+ (* (- 1) front1) back1) 0)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))))), 185825#(and (or (not v_assert) (<= (+ d2 temp2 (* 2 w)) (* 2 W))) (or (not v_assert) (<= back2 front2)) (or (not v_assert) (<= front1 back1)) (or (not v_assert) (<= front2 back2)) (or (<= back1 front1) (not v_assert))), 185815#(and (or (not v_assert) (<= back2 (+ front2 1)) (< 0 w)) (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (< 0 w) (not (< front2 back2))) (or (not v_assert) (= temp1 1) (< 0 w) (not (< front2 back2)))), 185811#(and (or (not v_assert) (<= back2 front2) (< 0 w)) (or (not v_assert) (< front2 (+ back2 1)) (< 0 w)) (or (not v_assert) (< 0 w) (<= (+ 2 d2) (* 2 W))) (or (not v_assert) (= temp1 1) (< 0 w))), 185807#(and (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (not (< front2 back2)) (= (select queue1 front1) 1))), 185828#(and (or (not v_assert) (= (+ (* (- 1) front1) back1) 0) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (= temp1 1) (not (< front2 back2))) (or (not v_assert) (not (< front2 back2)) (<= (+ 2 d2 (select queue2 front2) (* 2 w)) (* 2 W)))), 185819#(and (or (not v_assert) (= (+ (* (- 1) front1) back1) 0) (not (< front2 back2))) (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1)))), 185834#(and (or (not v_assert) (not (< front1 back1)) (<= front2 back2) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (<= back1 (+ front1 1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert) (not (< front1 back1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (<= back2 front2) (not (= (+ (select queue1 front1) 1) (select queue2 back2))))), 185814#(and (or (not v_assert) (<= back2 (+ front2 1)) (< 0 w)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (< 0 w) (not (< front2 back2))) (or (not v_assert) (= temp1 1) (< 0 w) (not (< front2 back2)))), 185842#(and (or (not v_assert) (<= (+ back2 1) front2) (<= back1 (+ front1 1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert) (not (< front1 back1)) (not (< front2 (+ back2 1))) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (<= back2 front2) (not (= (+ (select queue1 front1) 1) (select queue2 back2))))), 185799#(and (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (= temp1 1) (not (< front2 back2)))), 185824#(and (or (not v_assert) (< front2 (+ back2 1))) (or (not v_assert) (<= back2 front2)) (or (<= (+ d2 (* 2 w)) (* 2 W)) (not v_assert)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 185789#(or (<= (+ d2 (select queue2 front2)) (* 2 W)) (not v_assert)), 185838#(and (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not (< front2 back2))) (<= back2 (+ front2 1)) (or (<= back1 front1) (not (< front2 back2))) (or (<= front1 back1) (not (< front2 back2)))), 185800#(and (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (<= back1 front1) (not v_assert) (not (< front2 back2)) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (<= back2 (+ front2 1)))), 185839#(and (or (not v_assert) (not (= (select queue1 back1) 1)) (<= front2 back2) (not (< front1 (+ back1 1))) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (<= back1 front1) (not v_assert) (not (= (select queue1 back1) 1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (<= (+ d2 (select queue2 front2) (* 2 w)) (+ (* 2 W) 2)) (not (= (select queue1 back1) 1)) (not (< front1 (+ back1 1))) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (= (select queue1 back1) 1)) (<= back2 front2) (not (< front1 (+ back1 1))) (not (= (+ (select queue1 front1) 1) (select queue2 back2))))), 185829#(and (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (< front1 back1)) (not (< front2 (+ back2 1))) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (= (+ (- 1) (* (- 1) front1) back1) 0) (not (< front2 (+ back2 1))) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (<= back2 front2) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))))] [2022-03-15 21:38:30,054 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 80 states [2022-03-15 21:38:30,054 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:38:30,054 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 80 interpolants. [2022-03-15 21:38:30,055 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1448, Invalid=10762, Unknown=0, NotChecked=0, Total=12210 [2022-03-15 21:38:30,055 INFO L87 Difference]: Start difference. First operand 5092 states and 17181 transitions. Second operand has 80 states, 80 states have (on average 4.5375) internal successors, (363), 79 states have internal predecessors, (363), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:38:48,730 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:38:48,730 INFO L93 Difference]: Finished difference Result 23900 states and 78755 transitions. [2022-03-15 21:38:48,731 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 185 states. [2022-03-15 21:38:48,731 INFO L78 Accepts]: Start accepts. Automaton has has 80 states, 80 states have (on average 4.5375) internal successors, (363), 79 states have internal predecessors, (363), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 38 [2022-03-15 21:38:48,731 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:38:48,780 INFO L225 Difference]: With dead ends: 23900 [2022-03-15 21:38:48,780 INFO L226 Difference]: Without dead ends: 23395 [2022-03-15 21:38:48,783 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 610 GetRequests, 240 SyntacticMatches, 84 SemanticMatches, 286 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 33784 ImplicationChecksByTransitivity, 23.0s TimeCoverageRelationStatistics Valid=9127, Invalid=73529, Unknown=0, NotChecked=0, Total=82656 [2022-03-15 21:38:48,783 INFO L933 BasicCegarLoop]: 1 mSDtfsCounter, 1721 mSDsluCounter, 2332 mSDsCounter, 0 mSdLazyCounter, 8001 mSolverCounterSat, 994 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 3.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1721 SdHoareTripleChecker+Valid, 3 SdHoareTripleChecker+Invalid, 8995 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 994 IncrementalHoareTripleChecker+Valid, 8001 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 3.8s IncrementalHoareTripleChecker+Time [2022-03-15 21:38:48,783 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [1721 Valid, 3 Invalid, 8995 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [994 Valid, 8001 Invalid, 0 Unknown, 0 Unchecked, 3.8s Time] [2022-03-15 21:38:48,806 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23395 states. [2022-03-15 21:38:48,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23395 to 4809. [2022-03-15 21:38:49,012 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4809 states, 4808 states have (on average 3.3733361064891847) internal successors, (16219), 4808 states have internal predecessors, (16219), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:38:49,023 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4809 states to 4809 states and 16219 transitions. [2022-03-15 21:38:49,023 INFO L78 Accepts]: Start accepts. Automaton has 4809 states and 16219 transitions. Word has length 38 [2022-03-15 21:38:49,023 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:38:49,023 INFO L470 AbstractCegarLoop]: Abstraction has 4809 states and 16219 transitions. [2022-03-15 21:38:49,023 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 80 states, 80 states have (on average 4.5375) internal successors, (363), 79 states have internal predecessors, (363), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:38:49,023 INFO L276 IsEmpty]: Start isEmpty. Operand 4809 states and 16219 transitions. [2022-03-15 21:38:49,030 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2022-03-15 21:38:49,031 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:38:49,031 INFO L514 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:38:49,057 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Forceful destruction successful, exit code 0 [2022-03-15 21:38:49,247 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable17,15 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:38:49,249 INFO L402 AbstractCegarLoop]: === Iteration 19 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION (and 1 more)] === [2022-03-15 21:38:49,250 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:38:49,250 INFO L85 PathProgramCache]: Analyzing trace with hash 1609870639, now seen corresponding path program 15 times [2022-03-15 21:38:49,250 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:38:49,250 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1425965344] [2022-03-15 21:38:49,250 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:38:49,251 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:38:49,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:38:49,620 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 3 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:38:49,620 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:38:49,620 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1425965344] [2022-03-15 21:38:49,620 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1425965344] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:38:49,620 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1945896371] [2022-03-15 21:38:49,620 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-03-15 21:38:49,621 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:38:49,621 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:38:49,621 INFO L229 MonitoredProcess]: Starting monitored process 16 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:38:49,622 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2022-03-15 21:38:49,666 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2022-03-15 21:38:49,666 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:38:49,667 INFO L263 TraceCheckSpWp]: Trace formula consists of 143 conjuncts, 44 conjunts are in the unsatisfiable core [2022-03-15 21:38:49,668 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:38:50,408 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:38:50,409 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:38:50,410 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:38:50,410 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:38:50,410 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:38:50,411 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 3 disjoint index pairs (out of 6 index pairs), introduced 3 new quantified variables, introduced 0 case distinctions, treesize of input 51 treesize of output 31 [2022-03-15 21:38:50,511 INFO L353 Elim1Store]: treesize reduction 32, result has 3.0 percent of original size [2022-03-15 21:38:50,511 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 38 treesize of output 18 [2022-03-15 21:38:50,585 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 3 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:38:50,586 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:38:51,311 INFO L353 Elim1Store]: treesize reduction 76, result has 52.8 percent of original size [2022-03-15 21:38:51,312 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 0 disjoint index pairs (out of 15 index pairs), introduced 6 new quantified variables, introduced 15 case distinctions, treesize of input 50 treesize of output 114 [2022-03-15 21:38:52,012 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:38:52,013 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:38:52,014 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:38:52,014 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:38:52,015 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:38:52,018 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:38:52,018 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:38:52,019 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:38:52,020 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:38:52,040 INFO L353 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-03-15 21:38:52,040 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 9 disjoint index pairs (out of 15 index pairs), introduced 6 new quantified variables, introduced 6 case distinctions, treesize of input 45 treesize of output 85 [2022-03-15 21:38:52,441 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 4 proven. 29 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:38:52,441 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1945896371] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:38:52,441 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:38:52,441 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 19, 19] total 49 [2022-03-15 21:38:52,441 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [369179990] [2022-03-15 21:38:52,441 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:38:52,444 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:38:52,546 INFO L252 McrAutomatonBuilder]: Finished intersection with 360 states and 916 transitions. [2022-03-15 21:38:52,546 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:39:12,798 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 52 new interpolants: [220024#(and (or (not v_assert) (not (< (+ front2 1) back2)) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 2))) (or (not v_assert) (not (< (+ front2 1) back2)) (= (+ (* (- 1) front1) back1) 0))), 220023#(and (or (not v_assert) (= (+ (* (- 1) front1) back1) 0) (not (< front2 back2))) (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1)))), 220030#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1)) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (not (< front2 back2)) (= (select queue1 front1) 1))), 220007#(and (or (not v_assert) (<= (+ 2 d2) (* 2 W))) (or (not v_assert) (< front2 (+ back2 1))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= back2 front2))), 220008#(and (or (not v_assert) (<= (+ 2 d2) (* 2 W))) (or (not v_assert) (< front2 (+ back2 1))) (or (not v_assert) (<= back2 front2)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 220021#(and (or (not v_assert) (<= (+ 2 d2 temp2) (* 2 W))) (or (not v_assert) (< front2 (+ back2 1))) (or (not v_assert) (<= back2 front2)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 220033#(and (or (not v_assert) (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2) (* 2 w)) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 2))) (or (not v_assert) (<= (+ front2 2) back2)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 219996#(and (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= (+ 2 d2) (* 2 W))) (or (not v_assert) (< front2 (+ back2 1))) (or (not v_assert) (<= back2 front2))), 219992#(and (or (<= (+ d2 temp2) (* 2 W)) v_assert) (or (<= (+ d2 temp2) (* 2 W)) (< 0 w))), 220025#(and (or (not v_assert) (< front2 (+ back2 1))) (or (not v_assert) (<= back2 front2)) (or (<= (+ d2 (* 2 w)) (* 2 W)) (not v_assert)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 220004#(and (or (not v_assert) (<= back2 (+ front2 1)) (< 0 w)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (< 0 w) (not (< front2 back2))) (or (not v_assert) (= temp1 1) (< 0 w) (not (< front2 back2)))), 220019#(and (or (<= back1 front1) (not v_assert) (not (< (+ front2 1) back2)) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (<= back2 (+ front2 2))) (or (<= back1 front1) (not v_assert) (not (< (+ front2 1) back2)) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)))), 219991#(and (or (<= d2 (* 2 W)) v_assert) (or (<= d2 (* 2 W)) (< 0 w))), 220009#(and (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (= temp1 1) (not (< front2 back2)))), 220003#(and (or (not v_assert) (<= back2 front2) (< 0 w)) (or (not v_assert) (< front2 (+ back2 1)) (< 0 w)) (or (not v_assert) (< 0 w) (<= (+ 2 d2 temp2) (* 2 W))) (or (not v_assert) (= temp1 1) (< 0 w))), 220012#(and (or (not v_assert) (not (< (+ front2 1) back2)) (= temp1 1) (< 0 w)) (or (not v_assert) (not (< (+ front2 1) back2)) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w)) (or (not v_assert) (<= back2 (+ front2 2)) (< 0 w))), 220005#(and (or (<= back1 front1) (< front2 (+ back2 1))) (or (<= back1 front1) (<= (+ 2 d2) (* 2 W))) (or (<= back1 front1) (<= back2 front2)) (or (<= back1 front1) (= (select queue1 front1) 1))), 220000#(or (<= (+ d2 (select queue2 front2)) (* 2 W)) (not v_assert) (< 0 w)), 220031#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1)) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (= (+ (* (- 1) front1) back1) 0) (not (< front2 back2)))), 220032#(and (or (not v_assert) (not (< front1 back1)) (<= back2 (+ front2 1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (not (= (+ (select queue1 front1) 1) (select queue2 back2))) (not (< front2 back2))) (or (not v_assert) (not (< front1 back1)) (= (+ (- 1) (* (- 1) front1) back1) 0) (not (= (+ (select queue1 front1) 1) (select queue2 back2))) (not (< front2 back2)))), 220014#(and (or (<= back1 front1) (not v_assert) (not (< front2 back2)) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (<= back2 (+ front2 1))) (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (< front2 back2)))), 220026#(and (or (not v_assert) (<= (+ d2 temp2 (* 2 w)) (* 2 W))) (or (not v_assert) (< front2 (+ back2 1))) (or (not v_assert) (<= back2 front2)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 220036#(and (or (not v_assert) (not (< front1 back1)) (not (= (+ (select queue1 front1) 1) (select queue2 (+ back2 1)))) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))) (or (not v_assert) (not (< front1 back1)) (not (= (+ (select queue1 front1) 1) (select queue2 (+ back2 1)))) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (not (< front1 back1)) (not (= (+ (select queue1 front1) 1) (select queue2 (+ back2 1)))) (= (+ (- 1) (* (- 1) front1) back1) 0) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))))), 219998#(and (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= (+ 2 d2 temp2) (* 2 W))) (or (not v_assert) (< front2 (+ back2 1))) (or (not v_assert) (<= back2 front2))), 220034#(and (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2) (* 2 w)) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 220042#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (= front1 back1)) (or (not v_assert) (= W w)) (or (not v_assert) (<= d2 0))), 220002#(or (not v_assert) (<= (+ d2 temp2 (select queue2 front2)) (* 2 W)) (< 0 w)), 220028#(and (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (<= (+ d2 temp2 (select queue2 front2) (* 2 w)) (* 2 W))) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 220011#(and (or (not v_assert) (<= back2 (+ front2 1)) (< 0 w)) (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (< 0 w) (not (< front2 back2))) (or (not v_assert) (= temp1 1) (< 0 w) (not (< front2 back2)))), 220038#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (= (+ (* (- 1) front1) back1) 0))), 220020#(and (or (not v_assert) (not (< (+ front2 1) back2)) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 2))) (or (not v_assert) (not (< (+ front2 1) back2)) (= (select queue1 front1) 1))), 219993#(and (or (<= (+ d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ d2 (select queue2 front2)) (* 2 W)) v_assert)), 220018#(and (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (not (< front2 back2)) (= (select queue1 front1) 1))), 220017#(and (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (<= back1 front1) (not v_assert) (not (< front2 back2)) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (<= back2 (+ front2 1)))), 220010#(and (or (not v_assert) (not (< (+ front2 1) back2)) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 2))) (or (not v_assert) (not (< (+ front2 1) back2)) (= temp1 1))), 220013#(and (or (<= back1 front1) (not v_assert) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (< front2 (+ back2 1))) (or (<= back1 front1) (not v_assert) (<= back2 front2)) (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 temp2) (* 2 W)))), 220016#(and (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (not (< front2 back2)) (= (select queue1 front1) 1))), 220001#(and (or (not v_assert) (<= back2 front2) (< 0 w)) (or (not v_assert) (< front2 (+ back2 1)) (< 0 w)) (or (not v_assert) (< 0 w) (<= (+ 2 d2) (* 2 W))) (or (not v_assert) (= temp1 1) (< 0 w))), 219999#(and (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (= temp1 1) (not (< front2 back2)))), 220029#(and (or (<= back1 front1) (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (<= back1 front1) (not v_assert) (<= back2 (+ front2 1)) (not (= (select queue2 back2) (+ temp1 1)))) (or (<= back1 front1) (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (not (< front2 back2)) (= (select queue1 front1) 1))), 220039#(and (or (not v_assert) (not (< front1 back1)) (= (+ (- 1) (* (- 1) front1) back1) 0) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (<= front2 back2) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert) (not (< front1 back1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (<= back2 front2) (not (= (+ (select queue1 front1) 1) (select queue2 back2))))), 220027#(and (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 219997#(or (not v_assert) (<= (+ d2 temp2 (select queue2 front2)) (* 2 W))), 220015#(and (or (not v_assert) (<= (+ 2 d2 temp2) (* 2 W))) (or (not v_assert) (< front2 (+ back2 1))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= back2 front2))), 220040#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (<= back1 (+ front1 1))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ 2 d2 (* 2 w)) (* 2 W))) (or (not v_assert) (<= (+ front1 1) back1))), 220041#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= (+ 2 d2 (* 2 w)) (* 2 W))) (or (not v_assert) (<= front1 back1)) (or (<= back1 front1) (not v_assert))), 219994#(and (or (<= back2 front2) (< 0 w)) (or (< front2 (+ back2 1)) v_assert) (or v_assert (<= back2 front2)) (or v_assert (<= (+ 2 d2) (* 2 W))) (or (< front2 (+ back2 1)) (< 0 w)) (or (= temp1 1) (< 0 w)) (or (= temp1 1) v_assert) (or (< 0 w) (<= (+ 2 d2) (* 2 W)))), 220037#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (not v_assert) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 front2) (* 2 w)) (* 2 W))) (or (not v_assert) (= (+ (- 1) (* (- 1) front1) back1) 0) (not (= (select queue2 back2) (+ temp1 1))))), 220022#(and (or (not v_assert) (= (+ (* (- 1) front1) back1) 0) (not (< front2 back2))) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1)))), 220006#(and (or (<= back1 front1) (not v_assert) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (< front2 (+ back2 1))) (or (<= back1 front1) (not v_assert) (<= (+ 2 d2) (* 2 W))) (or (<= back1 front1) (not v_assert) (<= back2 front2))), 219995#(or (<= (+ d2 (select queue2 front2)) (* 2 W)) (not v_assert)), 220035#(and (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (= (+ (- 1) (* (- 1) front1) back1) 0)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2) (* 2 w)) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)))] [2022-03-15 21:39:12,799 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 71 states [2022-03-15 21:39:12,799 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:39:12,799 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 71 interpolants. [2022-03-15 21:39:12,799 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1278, Invalid=9024, Unknown=0, NotChecked=0, Total=10302 [2022-03-15 21:39:12,800 INFO L87 Difference]: Start difference. First operand 4809 states and 16219 transitions. Second operand has 71 states, 71 states have (on average 4.577464788732394) internal successors, (325), 70 states have internal predecessors, (325), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:40:19,729 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:40:19,729 INFO L93 Difference]: Finished difference Result 66039 states and 223709 transitions. [2022-03-15 21:40:19,729 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 581 states. [2022-03-15 21:40:19,729 INFO L78 Accepts]: Start accepts. Automaton has has 71 states, 71 states have (on average 4.577464788732394) internal successors, (325), 70 states have internal predecessors, (325), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 38 [2022-03-15 21:40:19,729 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:40:19,912 INFO L225 Difference]: With dead ends: 66039 [2022-03-15 21:40:19,912 INFO L226 Difference]: Without dead ends: 63550 [2022-03-15 21:40:19,930 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 977 GetRequests, 229 SyntacticMatches, 85 SemanticMatches, 663 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 204618 ImplicationChecksByTransitivity, 68.3s TimeCoverageRelationStatistics Valid=54546, Invalid=387014, Unknown=0, NotChecked=0, Total=441560 [2022-03-15 21:40:19,931 INFO L933 BasicCegarLoop]: 1 mSDtfsCounter, 3079 mSDsluCounter, 2203 mSDsCounter, 0 mSdLazyCounter, 8941 mSolverCounterSat, 3015 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 4.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 3079 SdHoareTripleChecker+Valid, 3 SdHoareTripleChecker+Invalid, 11956 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3015 IncrementalHoareTripleChecker+Valid, 8941 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 5.2s IncrementalHoareTripleChecker+Time [2022-03-15 21:40:19,931 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [3079 Valid, 3 Invalid, 11956 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3015 Valid, 8941 Invalid, 0 Unknown, 0 Unchecked, 5.2s Time] [2022-03-15 21:40:20,000 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63550 states. [2022-03-15 21:40:20,524 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63550 to 5970. [2022-03-15 21:40:20,531 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5970 states, 5969 states have (on average 3.368403417657899) internal successors, (20106), 5969 states have internal predecessors, (20106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:40:20,545 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5970 states to 5970 states and 20106 transitions. [2022-03-15 21:40:20,545 INFO L78 Accepts]: Start accepts. Automaton has 5970 states and 20106 transitions. Word has length 38 [2022-03-15 21:40:20,545 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:40:20,545 INFO L470 AbstractCegarLoop]: Abstraction has 5970 states and 20106 transitions. [2022-03-15 21:40:20,545 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 71 states, 71 states have (on average 4.577464788732394) internal successors, (325), 70 states have internal predecessors, (325), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:40:20,546 INFO L276 IsEmpty]: Start isEmpty. Operand 5970 states and 20106 transitions. [2022-03-15 21:40:20,555 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2022-03-15 21:40:20,555 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:40:20,555 INFO L514 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:40:20,573 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Ended with exit code 0 [2022-03-15 21:40:20,771 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable18,16 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:40:20,771 INFO L402 AbstractCegarLoop]: === Iteration 20 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION (and 1 more)] === [2022-03-15 21:40:20,772 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:40:20,772 INFO L85 PathProgramCache]: Analyzing trace with hash 64576033, now seen corresponding path program 16 times [2022-03-15 21:40:20,772 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:40:20,772 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1854830151] [2022-03-15 21:40:20,772 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:40:20,772 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:40:20,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:40:21,098 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 3 proven. 29 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-03-15 21:40:21,098 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:40:21,098 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1854830151] [2022-03-15 21:40:21,098 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1854830151] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:40:21,098 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [285302887] [2022-03-15 21:40:21,098 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-03-15 21:40:21,098 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:40:21,098 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:40:21,099 INFO L229 MonitoredProcess]: Starting monitored process 17 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:40:21,100 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2022-03-15 21:40:21,130 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-03-15 21:40:21,130 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:40:21,131 INFO L263 TraceCheckSpWp]: Trace formula consists of 143 conjuncts, 43 conjunts are in the unsatisfiable core [2022-03-15 21:40:21,132 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:40:21,738 INFO L353 Elim1Store]: treesize reduction 32, result has 3.0 percent of original size [2022-03-15 21:40:21,738 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 51 treesize of output 31 [2022-03-15 21:40:21,921 INFO L353 Elim1Store]: treesize reduction 32, result has 3.0 percent of original size [2022-03-15 21:40:21,921 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 38 treesize of output 18 [2022-03-15 21:40:21,987 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 3 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:40:21,987 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:40:22,478 INFO L353 Elim1Store]: treesize reduction 76, result has 52.8 percent of original size [2022-03-15 21:40:22,478 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 0 disjoint index pairs (out of 15 index pairs), introduced 6 new quantified variables, introduced 15 case distinctions, treesize of input 52 treesize of output 116 [2022-03-15 21:40:23,105 INFO L353 Elim1Store]: treesize reduction 76, result has 52.8 percent of original size [2022-03-15 21:40:23,105 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 0 disjoint index pairs (out of 15 index pairs), introduced 6 new quantified variables, introduced 15 case distinctions, treesize of input 47 treesize of output 111 [2022-03-15 21:40:23,654 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 5 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:40:23,654 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [285302887] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:40:23,654 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:40:23,654 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 19, 19] total 47 [2022-03-15 21:40:23,654 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [906103890] [2022-03-15 21:40:23,654 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:40:23,659 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:40:23,716 INFO L252 McrAutomatonBuilder]: Finished intersection with 306 states and 754 transitions. [2022-03-15 21:40:23,716 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:40:42,388 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 42 new interpolants: [299440#(and (or (not v_assert) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w) (not (< front2 back2))) (or (not v_assert) (<= (+ front2 2) back2) (< 0 w) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 2)) (< 0 w)) (or (not v_assert) (= temp1 1) (< 0 w) (not (< front2 back2)))), 299449#(and (or (not v_assert) (not (< front1 back1)) (not (< front2 (+ 2 back2))) (not (= (+ (select queue1 front1) 1) (select queue2 (+ back2 1)))) (= (+ (- 1) (* (- 1) front1) back1) 0) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (< front1 back1)) (not (< front2 (+ 2 back2))) (not (= (+ (select queue1 front1) 1) (select queue2 (+ back2 1)))) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))) (or (not v_assert) (not (< front1 back1)) (not (< front2 (+ 2 back2))) (not (= (+ (select queue1 front1) 1) (select queue2 (+ back2 1)))) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (< front1 back1)) (not (= (+ (select queue1 front1) 1) (select queue2 (+ back2 1)))) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2))), 299430#(and (or (<= d2 (* 2 W)) v_assert) (or (<= d2 (* 2 W)) (< 0 w))), 299445#(and (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 1)) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (not v_assert) (not (< front2 (+ back2 1))) (<= (+ front2 1) back2) (not (= (select queue2 back2) (+ temp1 1))))), 299448#(and (or (not v_assert) (<= back1 (+ front1 1))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2) (* 2 w)) (* 2 W))) (or (not v_assert) (<= (+ front1 1) back1)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2))), 299431#(and (or (<= (+ d2 temp2) (* 2 W)) v_assert) (or (<= (+ d2 temp2) (* 2 W)) (< 0 w))), 299456#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= (+ 2 d2 (* 2 w)) (* 2 W))) (or (not v_assert) (<= front1 back1)) (or (<= back1 front1) (not v_assert))), 299459#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (= front1 back1)) (or (not v_assert) (= W w)) (or (not v_assert) (<= d2 0))), 299441#(and (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W))) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 299450#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back1 (+ front1 1))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (not v_assert) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 front2) (* 2 w)) (* 2 W))) (or (not v_assert) (<= (+ front1 1) back1) (not (= (select queue2 back2) (+ temp1 1))))), 299418#(or (not v_assert) (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))), 299426#(and (or (<= back1 front1) (not v_assert) (<= (+ front2 2) back2) (not (< front2 back2))) (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (<= back1 front1) (not v_assert) (<= back2 (+ front2 2))) (or (<= back1 front1) (not v_assert) (not (< front2 back2)) (= (select queue1 front1) 1))), 299455#(and (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2) (* 2 w)) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 299457#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (<= back1 (+ front1 1))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ 2 d2 (* 2 w)) (* 2 W))) (or (not v_assert) (<= (+ front1 1) back1))), 299423#(and (or (<= back1 front1) (<= (+ 2 d2 (select queue2 front2)) (* 2 W))) (or (<= back1 front1) (<= (+ front2 1) back2)) (or (<= back1 front1) (<= back2 (+ front2 1))) (or (<= back1 front1) (= (select queue1 front1) 1))), 299428#(and (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)))), 299433#(and (or (<= (+ d2 temp2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ d2 temp2 (select queue2 front2)) (* 2 W)) v_assert)), 299458#(and (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= front1 back1)) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (<= (+ d2 temp2 (select queue2 front2) (* 2 w)) (* 2 W))) (or (<= back1 front1) (not v_assert))), 299434#(and (or (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) v_assert)), 299438#(and (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (not v_assert) (<= back2 (+ front2 1)) (< 0 w)) (or (not v_assert) (= temp1 1) (< 0 w)) (or (not v_assert) (<= (+ front2 1) back2) (< 0 w))), 299442#(and (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W))) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 299420#(and (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)))), 299444#(and (or (<= back1 front1) (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (<= back2 (+ front2 1)) (not (= (select queue2 back2) (+ temp1 1)))) (or (<= back1 front1) (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))) (or (<= back1 front1) (not v_assert) (not (< front2 (+ back2 1))) (<= (+ front2 1) back2) (not (= (select queue2 back2) (+ temp1 1))))), 299424#(and (or (<= back1 front1) (not v_assert) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W))) (or (<= back1 front1) (not v_assert) (<= back2 (+ front2 1))) (or (<= back1 front1) (not v_assert) (<= (+ front2 1) back2))), 299432#(and (or (<= (+ d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ d2 (select queue2 front2)) (* 2 W)) v_assert)), 299422#(and (or (not v_assert) (<= back2 (+ front2 2))) (or (not v_assert) (<= (+ front2 2) back2) (not (< front2 back2))) (or (not v_assert) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (= temp1 1) (not (< front2 back2)))), 299452#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert) (not (= (select queue2 back2) (+ temp1 1)))) (or (<= back1 front1) (not v_assert) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (<= front1 back1) (not (= (select queue2 back2) (+ temp1 1))))), 299435#(or (not v_assert) (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w)), 299436#(or (not v_assert) (<= (+ d2 temp2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w)), 299454#(and (or (not v_assert) (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2) (* 2 w)) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 2))) (or (not v_assert) (<= (+ front2 2) back2)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 299437#(and (or (<= back2 (+ front2 1)) (< 0 w)) (or (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or v_assert (<= (+ front2 1) back2)) (or (<= (+ front2 1) back2) (< 0 w)) (or (<= back2 (+ front2 1)) v_assert) (or (= temp1 1) (< 0 w)) (or (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) v_assert) (or (= temp1 1) v_assert)), 299429#(and (or (not v_assert) (<= back2 (+ front2 2))) (or (not v_assert) (<= (+ front2 2) back2) (not (< front2 back2))) (or (not v_assert) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (not (< front2 back2)) (= (select queue1 front1) 1))), 299427#(and (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)))), 299439#(and (or (not v_assert) (<= back2 (+ front2 1)) (< 0 w)) (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (not v_assert) (= temp1 1) (< 0 w)) (or (not v_assert) (<= (+ front2 1) back2) (< 0 w))), 299451#(and (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= front1 back1)) (or (not v_assert) (<= (+ front2 1) back2)) (or (<= back1 front1) (not v_assert))), 299443#(and (or (not v_assert) (<= back2 (+ front2 2))) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0) (not (< front2 back2))) (or (not v_assert) (<= (+ front2 2) back2) (not (< front2 back2))) (or (not v_assert) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (not (< front2 back2)))), 299447#(and (or (not v_assert) (not (< front1 back1)) (<= back2 (+ front2 1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (not (< front2 (+ back2 1))) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (not (< front2 (+ back2 1))) (<= (+ front2 1) back2) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (= (+ (- 1) (* (- 1) front1) back1) 0) (not (< front2 (+ back2 1))) (not (= (+ (select queue1 front1) 1) (select queue2 back2))))), 299421#(and (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)))), 299419#(or (not v_assert) (<= (+ d2 temp2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))), 299453#(and (or (not v_assert) (not (< front1 back1)) (<= front2 back2) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (<= back1 (+ front1 1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert) (not (< front1 back1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (<= back2 front2) (not (= (+ (select queue1 front1) 1) (select queue2 back2))))), 299446#(and (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 1)) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (+ (* (- 1) front1) back1) 0)) (or (not v_assert) (not (< front2 (+ back2 1))) (<= (+ front2 1) back2) (not (= (select queue2 back2) (+ temp1 1))))), 299425#(and (or (<= back1 front1) (not v_assert) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W))) (or (<= back1 front1) (not v_assert) (<= back2 (+ front2 1))) (or (<= back1 front1) (not v_assert) (<= (+ front2 1) back2)))] [2022-03-15 21:40:42,388 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 61 states [2022-03-15 21:40:42,388 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:40:42,388 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 61 interpolants. [2022-03-15 21:40:42,388 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=573, Invalid=7437, Unknown=0, NotChecked=0, Total=8010 [2022-03-15 21:40:42,389 INFO L87 Difference]: Start difference. First operand 5970 states and 20106 transitions. Second operand has 61 states, 61 states have (on average 4.557377049180328) internal successors, (278), 60 states have internal predecessors, (278), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:40:59,446 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:40:59,446 INFO L93 Difference]: Finished difference Result 22250 states and 75028 transitions. [2022-03-15 21:40:59,446 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 167 states. [2022-03-15 21:40:59,447 INFO L78 Accepts]: Start accepts. Automaton has has 61 states, 61 states have (on average 4.557377049180328) internal successors, (278), 60 states have internal predecessors, (278), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 38 [2022-03-15 21:40:59,447 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:40:59,504 INFO L225 Difference]: With dead ends: 22250 [2022-03-15 21:40:59,504 INFO L226 Difference]: Without dead ends: 21859 [2022-03-15 21:40:59,506 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 524 GetRequests, 215 SyntacticMatches, 57 SemanticMatches, 252 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23689 ImplicationChecksByTransitivity, 19.2s TimeCoverageRelationStatistics Valid=5339, Invalid=58923, Unknown=0, NotChecked=0, Total=64262 [2022-03-15 21:40:59,506 INFO L933 BasicCegarLoop]: 1 mSDtfsCounter, 1351 mSDsluCounter, 2300 mSDsCounter, 0 mSdLazyCounter, 7472 mSolverCounterSat, 682 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 2.8s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1351 SdHoareTripleChecker+Valid, 3 SdHoareTripleChecker+Invalid, 8154 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 682 IncrementalHoareTripleChecker+Valid, 7472 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 3.2s IncrementalHoareTripleChecker+Time [2022-03-15 21:40:59,507 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [1351 Valid, 3 Invalid, 8154 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [682 Valid, 7472 Invalid, 0 Unknown, 0 Unchecked, 3.2s Time] [2022-03-15 21:40:59,530 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21859 states. [2022-03-15 21:40:59,702 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21859 to 6314. [2022-03-15 21:40:59,710 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6314 states, 6313 states have (on average 3.3654364010771425) internal successors, (21246), 6313 states have internal predecessors, (21246), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:40:59,726 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6314 states to 6314 states and 21246 transitions. [2022-03-15 21:40:59,726 INFO L78 Accepts]: Start accepts. Automaton has 6314 states and 21246 transitions. Word has length 38 [2022-03-15 21:40:59,726 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:40:59,726 INFO L470 AbstractCegarLoop]: Abstraction has 6314 states and 21246 transitions. [2022-03-15 21:40:59,727 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 61 states, 61 states have (on average 4.557377049180328) internal successors, (278), 60 states have internal predecessors, (278), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:40:59,727 INFO L276 IsEmpty]: Start isEmpty. Operand 6314 states and 21246 transitions. [2022-03-15 21:40:59,737 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2022-03-15 21:40:59,737 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:40:59,737 INFO L514 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:40:59,752 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Forceful destruction successful, exit code 0 [2022-03-15 21:40:59,937 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable19,17 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:40:59,938 INFO L402 AbstractCegarLoop]: === Iteration 21 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION (and 1 more)] === [2022-03-15 21:40:59,938 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:40:59,938 INFO L85 PathProgramCache]: Analyzing trace with hash 1947414511, now seen corresponding path program 17 times [2022-03-15 21:40:59,939 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:40:59,939 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1832395720] [2022-03-15 21:40:59,939 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:40:59,939 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:40:59,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:41:00,293 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 3 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:41:00,293 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:41:00,293 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1832395720] [2022-03-15 21:41:00,293 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1832395720] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:41:00,293 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [731611852] [2022-03-15 21:41:00,293 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-03-15 21:41:00,293 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:41:00,293 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:41:00,294 INFO L229 MonitoredProcess]: Starting monitored process 18 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:41:00,295 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2022-03-15 21:41:00,332 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2022-03-15 21:41:00,333 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:41:00,334 INFO L263 TraceCheckSpWp]: Trace formula consists of 143 conjuncts, 44 conjunts are in the unsatisfiable core [2022-03-15 21:41:00,334 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:41:00,837 INFO L353 Elim1Store]: treesize reduction 32, result has 3.0 percent of original size [2022-03-15 21:41:00,837 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 49 treesize of output 29 [2022-03-15 21:41:04,192 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:41:04,193 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:41:04,193 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:41:04,194 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:41:04,194 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:41:04,195 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:41:04,195 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 3 disjoint index pairs (out of 10 index pairs), introduced 3 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 18 [2022-03-15 21:41:04,275 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 3 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:41:04,275 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:41:04,908 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:41:04,909 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:41:04,911 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:41:04,912 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:41:04,912 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:41:04,912 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:41:04,913 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:41:04,938 INFO L353 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-03-15 21:41:04,938 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 7 disjoint index pairs (out of 15 index pairs), introduced 6 new quantified variables, introduced 8 case distinctions, treesize of input 50 treesize of output 110 [2022-03-15 21:41:06,075 INFO L353 Elim1Store]: treesize reduction 76, result has 52.8 percent of original size [2022-03-15 21:41:06,075 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 0 disjoint index pairs (out of 15 index pairs), introduced 6 new quantified variables, introduced 15 case distinctions, treesize of input 47 treesize of output 111 [2022-03-15 21:41:06,949 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 4 proven. 29 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:41:06,949 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [731611852] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:41:06,949 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:41:06,949 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 51 [2022-03-15 21:41:06,949 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [406781645] [2022-03-15 21:41:06,949 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:41:06,953 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:41:07,001 INFO L252 McrAutomatonBuilder]: Finished intersection with 249 states and 582 transitions. [2022-03-15 21:41:07,002 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:41:19,598 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 31 new interpolants: [334950#(and (or (not v_assert) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 2))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ front2 2) back2))), 334947#(and (or (<= (+ front2 2) back2) v_assert) (or v_assert (<= back2 (+ front2 2))) (or (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w)) (or v_assert (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))) (or (= temp1 1) (< 0 w)) (or (<= back2 (+ front2 2)) (< 0 w)) (or (= temp1 1) v_assert) (or (<= (+ front2 2) back2) (< 0 w))), 334963#(and (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= front1 back1)) (or (not v_assert) (<= (+ front2 1) back2)) (or (<= back1 front1) (not v_assert))), 334959#(and (or (not v_assert) (<= (+ front2 2) back2) (< 0 w)) (or (not v_assert) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w)) (or (not v_assert) (= temp1 1) (< 0 w)) (or (not v_assert) (<= back2 (+ front2 2)) (< 0 w))), 334960#(and (or (not v_assert) (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2) (* 2 w)) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 2))) (or (not v_assert) (<= (+ front2 2) back2)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 334945#(and (or (<= (+ d2 temp2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) v_assert) (or (<= (+ d2 temp2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w))), 334954#(and (or (not v_assert) (<= (+ front2 1) back2) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 1)) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (= (+ (* (- 1) front1) back1) 0))), 334965#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (not v_assert) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 front2) (* 2 w)) (* 2 W))) (or (not v_assert) (= (+ (- 1) (* (- 1) front1) back1) 0) (not (= (select queue2 back2) (+ temp1 1))))), 334955#(and (or (not v_assert) (not (< front1 back1)) (<= (+ front2 1) back2) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (<= back2 (+ front2 1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (= (+ (- 1) (* (- 1) front1) back1) 0) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (not (= (+ (select queue1 front1) 1) (select queue2 back2))))), 334940#(and (or (<= d2 (* 2 W)) v_assert) (or (<= d2 (* 2 W)) (< 0 w))), 334944#(and (or (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) v_assert)), 334962#(and (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (= (+ (- 1) (* (- 1) front1) back1) 0)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2) (* 2 w)) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2))), 334952#(and (or (<= back1 front1) (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))) (or (<= back1 front1) (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (<= (+ front2 1) back2) (not (= (select queue2 back2) (+ temp1 1)))) (or (<= back1 front1) (not v_assert) (<= back2 (+ front2 1)) (not (= (select queue2 back2) (+ temp1 1))))), 334953#(and (or (not v_assert) (<= (+ front2 1) back2) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 1)) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1))), 334949#(and (or (<= back1 front1) (not v_assert) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (<= back2 (+ front2 2))) (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))) (or (<= back1 front1) (not v_assert) (<= (+ front2 2) back2))), 334964#(and (or (not v_assert) (not (< front1 back1)) (not (= (+ (select queue1 front1) 1) (select queue2 (+ back2 1)))) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))) (or (not v_assert) (not (< front1 back1)) (not (= (+ (select queue1 front1) 1) (select queue2 (+ back2 1)))) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (< front1 back1)) (not (= (+ (select queue1 front1) 1) (select queue2 (+ back2 1)))) (= (+ (- 1) (* (- 1) front1) back1) 0) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (< front1 back1)) (not (= (+ (select queue1 front1) 1) (select queue2 (+ back2 1)))) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2))), 334942#(and (or (<= (+ d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ d2 (select queue2 front2)) (* 2 W)) v_assert)), 334969#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= (+ 2 d2 (* 2 w)) (* 2 W))) (or (not v_assert) (<= front1 back1)) (or (<= back1 front1) (not v_assert))), 334948#(and (or (<= back1 front1) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))) (or (<= back1 front1) (<= back2 (+ front2 2))) (or (<= back1 front1) (<= (+ front2 2) back2)) (or (<= back1 front1) (= (select queue1 front1) 1))), 334958#(or (not v_assert) (<= (+ (select queue2 (+ front2 2)) d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w)), 334951#(and (or (not v_assert) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 2))) (or (not v_assert) (<= (+ front2 2) back2)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 334943#(and (or (<= (+ d2 temp2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ d2 temp2 (select queue2 front2)) (* 2 W)) v_assert)), 334957#(and (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 2))) (or (not v_assert) (<= (+ front2 2) back2))), 334968#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (<= back1 (+ front1 1))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ 2 d2 (* 2 w)) (* 2 W))) (or (not v_assert) (<= (+ front1 1) back1))), 334970#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (= front1 back1)) (or (not v_assert) (= W w)) (or (not v_assert) (<= d2 0))), 334956#(or (not v_assert) (<= (+ (select queue2 (+ front2 2)) d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))), 334961#(and (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2) (* 2 w)) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 334967#(and (or (not v_assert) (not (< front1 back1)) (<= front2 back2) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (<= back1 (+ front1 1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert) (not (< front1 back1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (<= back2 front2) (not (= (+ (select queue1 front1) 1) (select queue2 back2))))), 334941#(and (or (<= (+ d2 temp2) (* 2 W)) v_assert) (or (<= (+ d2 temp2) (* 2 W)) (< 0 w))), 334966#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert) (not (= (select queue2 back2) (+ temp1 1)))) (or (<= back1 front1) (not v_assert) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (<= front1 back1) (not (= (select queue2 back2) (+ temp1 1))))), 334946#(and (or (<= (+ (select queue2 (+ front2 2)) d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ (select queue2 (+ front2 2)) d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) v_assert))] [2022-03-15 21:41:19,598 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 51 states [2022-03-15 21:41:19,598 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:41:19,599 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2022-03-15 21:41:19,599 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=574, Invalid=6231, Unknown=1, NotChecked=0, Total=6806 [2022-03-15 21:41:19,599 INFO L87 Difference]: Start difference. First operand 6314 states and 21246 transitions. Second operand has 51 states, 51 states have (on average 4.490196078431373) internal successors, (229), 50 states have internal predecessors, (229), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:41:36,549 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:41:36,550 INFO L93 Difference]: Finished difference Result 25084 states and 84832 transitions. [2022-03-15 21:41:36,550 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 153 states. [2022-03-15 21:41:36,550 INFO L78 Accepts]: Start accepts. Automaton has has 51 states, 51 states have (on average 4.490196078431373) internal successors, (229), 50 states have internal predecessors, (229), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 38 [2022-03-15 21:41:36,550 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:41:36,613 INFO L225 Difference]: With dead ends: 25084 [2022-03-15 21:41:36,613 INFO L226 Difference]: Without dead ends: 24968 [2022-03-15 21:41:36,616 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 452 GetRequests, 197 SyntacticMatches, 25 SemanticMatches, 230 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17658 ImplicationChecksByTransitivity, 21.3s TimeCoverageRelationStatistics Valid=5353, Invalid=48238, Unknown=1, NotChecked=0, Total=53592 [2022-03-15 21:41:36,617 INFO L933 BasicCegarLoop]: 1 mSDtfsCounter, 852 mSDsluCounter, 1674 mSDsCounter, 0 mSdLazyCounter, 5370 mSolverCounterSat, 416 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 2.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 852 SdHoareTripleChecker+Valid, 3 SdHoareTripleChecker+Invalid, 5786 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 416 IncrementalHoareTripleChecker+Valid, 5370 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 2.5s IncrementalHoareTripleChecker+Time [2022-03-15 21:41:36,617 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [852 Valid, 3 Invalid, 5786 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [416 Valid, 5370 Invalid, 0 Unknown, 0 Unchecked, 2.5s Time] [2022-03-15 21:41:36,640 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24968 states. [2022-03-15 21:41:36,821 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24968 to 6667. [2022-03-15 21:41:36,829 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6667 states, 6666 states have (on average 3.3616861686168615) internal successors, (22409), 6666 states have internal predecessors, (22409), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:41:36,846 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6667 states to 6667 states and 22409 transitions. [2022-03-15 21:41:36,846 INFO L78 Accepts]: Start accepts. Automaton has 6667 states and 22409 transitions. Word has length 38 [2022-03-15 21:41:36,846 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:41:36,846 INFO L470 AbstractCegarLoop]: Abstraction has 6667 states and 22409 transitions. [2022-03-15 21:41:36,846 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 51 states, 51 states have (on average 4.490196078431373) internal successors, (229), 50 states have internal predecessors, (229), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:41:36,846 INFO L276 IsEmpty]: Start isEmpty. Operand 6667 states and 22409 transitions. [2022-03-15 21:41:36,857 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2022-03-15 21:41:36,857 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:41:36,857 INFO L514 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:41:36,873 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Forceful destruction successful, exit code 0 [2022-03-15 21:41:37,057 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable20,18 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:41:37,058 INFO L402 AbstractCegarLoop]: === Iteration 22 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION (and 1 more)] === [2022-03-15 21:41:37,058 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:41:37,058 INFO L85 PathProgramCache]: Analyzing trace with hash 361129621, now seen corresponding path program 18 times [2022-03-15 21:41:37,059 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:41:37,059 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [210742506] [2022-03-15 21:41:37,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:41:37,059 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:41:37,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:41:37,386 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 3 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:41:37,386 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:41:37,386 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [210742506] [2022-03-15 21:41:37,386 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [210742506] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:41:37,386 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [513431773] [2022-03-15 21:41:37,386 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-03-15 21:41:37,386 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:41:37,387 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:41:37,387 INFO L229 MonitoredProcess]: Starting monitored process 19 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:41:37,388 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2022-03-15 21:41:37,423 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 6 check-sat command(s) [2022-03-15 21:41:37,423 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:41:37,424 INFO L263 TraceCheckSpWp]: Trace formula consists of 143 conjuncts, 43 conjunts are in the unsatisfiable core [2022-03-15 21:41:37,426 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:41:37,944 INFO L353 Elim1Store]: treesize reduction 32, result has 3.0 percent of original size [2022-03-15 21:41:37,944 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 49 treesize of output 29 [2022-03-15 21:41:38,219 INFO L353 Elim1Store]: treesize reduction 32, result has 3.0 percent of original size [2022-03-15 21:41:38,219 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 38 treesize of output 18 [2022-03-15 21:41:38,288 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 3 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:41:38,289 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:41:38,758 INFO L353 Elim1Store]: treesize reduction 76, result has 52.8 percent of original size [2022-03-15 21:41:38,758 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 0 disjoint index pairs (out of 15 index pairs), introduced 6 new quantified variables, introduced 15 case distinctions, treesize of input 52 treesize of output 116 [2022-03-15 21:41:39,397 INFO L353 Elim1Store]: treesize reduction 76, result has 52.8 percent of original size [2022-03-15 21:41:39,397 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 0 disjoint index pairs (out of 15 index pairs), introduced 6 new quantified variables, introduced 15 case distinctions, treesize of input 47 treesize of output 111 [2022-03-15 21:41:40,040 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 9 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:41:40,040 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [513431773] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:41:40,040 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:41:40,040 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 47 [2022-03-15 21:41:40,040 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [2116382011] [2022-03-15 21:41:40,040 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:41:40,044 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:41:40,131 INFO L252 McrAutomatonBuilder]: Finished intersection with 288 states and 697 transitions. [2022-03-15 21:41:40,131 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:41:55,332 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 41 new interpolants: [373979#(and (or (<= back1 front1) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= back1 front1) (< 0 w) (= (select queue1 front1) 1)) (or (<= back1 front1) v_assert (<= (+ front2 1) back2)) (or (<= back1 front1) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) v_assert) (or (<= back1 front1) (<= back2 (+ front2 1)) (< 0 w)) (or (<= back1 front1) (<= (+ front2 1) back2) (< 0 w)) (or (<= back1 front1) (<= back2 (+ front2 1)) v_assert) (or (<= back1 front1) v_assert (= (select queue1 front1) 1))), 373976#(and (or (<= back1 front1) (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) v_assert (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (<= back1 front1) (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w) (not (= (+ (select queue1 front1) 1) (select queue2 back2))))), 373973#(and (or (<= (+ d2 temp2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ d2 temp2 (select queue2 front2)) (* 2 W)) v_assert)), 373974#(and (or (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) v_assert)), 373960#(and (or (not v_assert) (<= back1 (+ front1 1))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ front1 1) back1)) (or (not v_assert) (<= (+ d2 (select queue2 front2) 4) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2))), 373970#(and (or (<= d2 (* 2 W)) v_assert) (or (<= d2 (* 2 W)) (< 0 w))), 373992#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back1 (+ front1 1))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (not v_assert) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 front2) (* 2 w)) (* 2 W))) (or (not v_assert) (<= (+ front1 1) back1) (not (= (select queue2 back2) (+ temp1 1))))), 373993#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert) (not (= (select queue2 back2) (+ temp1 1)))) (or (<= back1 front1) (not v_assert) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (<= front1 back1) (not (= (select queue2 back2) (+ temp1 1))))), 373987#(and (or (not v_assert) (<= (+ d2 (select queue2 front2) 4) (* 2 W)) (< 0 w)) (or (not v_assert) (<= back2 (+ front2 1)) (< 0 w)) (or (not v_assert) (= (+ (- 1) temp1) 0) (< 0 w)) (or (not v_assert) (< 0 w) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ front2 1) back2) (< 0 w))), 373991#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back1 (+ front1 1))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (not v_assert) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (<= (+ front1 1) back1) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (<= (+ d2 (select queue2 front2) 4) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1))))), 373980#(and (or (<= (+ front2 2) back2) v_assert) (or v_assert (<= back2 (+ front2 2))) (or (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w)) (or v_assert (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))) (or (= temp1 1) (< 0 w)) (or (<= back2 (+ front2 2)) (< 0 w)) (or (= temp1 1) v_assert) (or (<= (+ front2 2) back2) (< 0 w))), 373972#(and (or (<= (+ d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ d2 (select queue2 front2)) (* 2 W)) v_assert)), 373971#(and (or (<= (+ d2 temp2) (* 2 W)) v_assert) (or (<= (+ d2 temp2) (* 2 W)) (< 0 w))), 373975#(and (or (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1))) (< 0 w)) (or (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) v_assert (not (= (select queue2 back2) (+ temp1 1))))), 373997#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (= front1 back1)) (or (not v_assert) (= W w)) (or (not v_assert) (<= d2 0))), 373966#(or (<= back1 front1) (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))), 373983#(and (or (<= back1 front1) (not v_assert) (<= back2 (+ front2 1)) (< 0 w)) (or (<= back1 front1) (not v_assert) (< 0 w) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= back1 front1) (not v_assert) (<= (+ front2 1) back2) (< 0 w))), 373990#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (= (select queue1 (+ front1 1)) 1) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (not v_assert) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (<= (+ d2 (select queue2 front2) 4) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1))))), 373967#(and (or (<= back1 front1) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W))) (or (<= back1 front1) (<= (+ front2 1) back2)) (or (<= back1 front1) (<= back2 (+ front2 1))) (or (<= back1 front1) (= (select queue1 front1) 1))), 373989#(and (or (not v_assert) (not (< front1 back1)) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (not (< front1 back1)) (= (+ (- 1) (select queue1 front1)) 0) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (< front1 back1)) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (< front1 back1)) (<= (+ d2 (select queue2 front2) 4) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (< front1 back1)) (= (select queue1 (+ front1 1)) 1) (not (= (select queue2 back2) (+ temp1 1))))), 373965#(or (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1)))), 373964#(and (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (= (+ (- 1) temp1) 0)) (or (not v_assert) (<= (+ d2 (select queue2 front2) 4) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2))), 373958#(and (or (not v_assert) (not (< front1 back1)) (= (+ (- 1) (select queue1 front1)) 0)) (or (not v_assert) (not (< front1 back1)) (<= (+ d2 (select queue2 front2) 4) (* 2 W))) (or (not v_assert) (not (< front1 back1)) (= (select queue1 (+ front1 1)) 1)) (or (not v_assert) (not (< front1 back1)) (<= back2 (+ front2 1))) (or (not v_assert) (not (< front1 back1)) (<= (+ front2 1) back2))), 373984#(and (or (not v_assert) (<= (+ front2 2) back2) (< 0 w)) (or (not v_assert) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w)) (or (not v_assert) (= temp1 1) (< 0 w)) (or (not v_assert) (<= back2 (+ front2 2)) (< 0 w))), 373995#(and (or (not v_assert) (not (< front1 back1)) (<= front2 back2) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (<= back1 (+ front1 1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert) (not (< front1 back1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (<= back2 front2) (not (= (+ (select queue1 front1) 1) (select queue2 back2))))), 373963#(and (or (not v_assert) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 2))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ front2 2) back2))), 373996#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (<= back1 (+ front1 1))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ 2 d2 (* 2 w)) (* 2 W))) (or (not v_assert) (<= (+ front1 1) back1))), 373968#(or (<= back1 front1) (not v_assert) (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))), 373981#(and (or (<= (+ front2 2) back2) v_assert) (or v_assert (<= back2 (+ front2 2))) (or (< 0 w) (= (select queue1 front1) 1)) (or (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w)) (or v_assert (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))) (or v_assert (= (select queue1 front1) 1)) (or (<= back2 (+ front2 2)) (< 0 w)) (or (<= (+ front2 2) back2) (< 0 w))), 373977#(and (or (<= (+ d2 temp2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) v_assert) (or (<= (+ d2 temp2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w))), 373962#(and (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 2))) (or (not v_assert) (<= (+ front2 2) back2))), 373957#(and (or (not (< front1 back1)) (<= (+ front2 1) back2)) (or (not (< front1 back1)) (<= back2 (+ front2 1))) (or (not (< front1 back1)) (<= (+ d2 (select queue2 front2) 4) (* 2 W))) (or (not (< front1 back1)) (= (+ (- 1) (select queue1 front1)) 0)) (or (not (< front1 back1)) (= (select queue1 (+ front1 1)) 1))), 373978#(and (or (<= back2 (+ front2 1)) (< 0 w)) (or v_assert (<= (+ front2 1) back2)) (or (<= (+ front2 1) back2) (< 0 w)) (or (<= back2 (+ front2 1)) v_assert) (or (= temp1 1) (< 0 w)) (or (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (= temp1 1) v_assert) (or (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) v_assert)), 373961#(and (or (not v_assert) (<= back1 (+ front1 1))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2) (* 2 w)) (* 2 W))) (or (not v_assert) (<= (+ front1 1) back1)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2))), 373986#(and (or (= (+ (- 1) temp1) 0) (< 0 w)) (or (<= (+ d2 (select queue2 front2) 4) (* 2 W)) (< 0 w)) (or (<= back2 (+ front2 1)) (< 0 w)) (or (< 0 w) (= (select queue1 front1) 1)) (or v_assert (<= (+ front2 1) back2)) (or (<= (+ front2 1) back2) (< 0 w)) (or v_assert (= (select queue1 front1) 1)) (or (<= back2 (+ front2 1)) v_assert) (or (<= (+ d2 (select queue2 front2) 4) (* 2 W)) v_assert) (or v_assert (= (+ (- 1) temp1) 0))), 373994#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= (+ 2 d2 (* 2 w)) (* 2 W))) (or (not v_assert) (<= front1 back1)) (or (<= back1 front1) (not v_assert))), 373959#(and (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ d2 (select queue2 front2) 4) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (= (select queue1 (+ front1 1)) 1))), 373985#(and (or (not v_assert) (<= (+ front2 2) back2) (< 0 w)) (or (not v_assert) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w)) (or (not v_assert) (< 0 w) (= (select queue1 front1) 1)) (or (not v_assert) (<= back2 (+ front2 2)) (< 0 w))), 373982#(or (<= back1 front1) (not v_assert) (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))), 373988#(and (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= front1 back1)) (or (not v_assert) (<= (+ front2 1) back2)) (or (<= back1 front1) (not v_assert))), 373969#(and (or (<= back1 front1) (not v_assert) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W))) (or (<= back1 front1) (not v_assert) (<= back2 (+ front2 1))) (or (<= back1 front1) (not v_assert) (<= (+ front2 1) back2)))] [2022-03-15 21:41:55,332 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 61 states [2022-03-15 21:41:55,332 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:41:55,333 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 61 interpolants. [2022-03-15 21:41:55,333 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=584, Invalid=7248, Unknown=0, NotChecked=0, Total=7832 [2022-03-15 21:41:55,333 INFO L87 Difference]: Start difference. First operand 6667 states and 22409 transitions. Second operand has 61 states, 61 states have (on average 4.475409836065574) internal successors, (273), 60 states have internal predecessors, (273), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:42:05,661 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:42:05,661 INFO L93 Difference]: Finished difference Result 17935 states and 60339 transitions. [2022-03-15 21:42:05,661 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 73 states. [2022-03-15 21:42:05,661 INFO L78 Accepts]: Start accepts. Automaton has has 61 states, 61 states have (on average 4.475409836065574) internal successors, (273), 60 states have internal predecessors, (273), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 38 [2022-03-15 21:42:05,661 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:42:05,735 INFO L225 Difference]: With dead ends: 17935 [2022-03-15 21:42:05,735 INFO L226 Difference]: Without dead ends: 17850 [2022-03-15 21:42:05,740 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 412 GetRequests, 246 SyntacticMatches, 9 SemanticMatches, 157 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6822 ImplicationChecksByTransitivity, 11.0s TimeCoverageRelationStatistics Valid=2590, Invalid=22532, Unknown=0, NotChecked=0, Total=25122 [2022-03-15 21:42:05,740 INFO L933 BasicCegarLoop]: 1 mSDtfsCounter, 838 mSDsluCounter, 1988 mSDsCounter, 0 mSdLazyCounter, 6773 mSolverCounterSat, 418 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 2.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 838 SdHoareTripleChecker+Valid, 3 SdHoareTripleChecker+Invalid, 7191 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 418 IncrementalHoareTripleChecker+Valid, 6773 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 3.0s IncrementalHoareTripleChecker+Time [2022-03-15 21:42:05,740 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [838 Valid, 3 Invalid, 7191 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [418 Valid, 6773 Invalid, 0 Unknown, 0 Unchecked, 3.0s Time] [2022-03-15 21:42:05,755 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17850 states. [2022-03-15 21:42:05,871 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17850 to 7173. [2022-03-15 21:42:05,879 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7173 states, 7172 states have (on average 3.3601505856107083) internal successors, (24099), 7172 states have internal predecessors, (24099), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:42:05,897 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7173 states to 7173 states and 24099 transitions. [2022-03-15 21:42:05,897 INFO L78 Accepts]: Start accepts. Automaton has 7173 states and 24099 transitions. Word has length 38 [2022-03-15 21:42:05,897 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:42:05,897 INFO L470 AbstractCegarLoop]: Abstraction has 7173 states and 24099 transitions. [2022-03-15 21:42:05,897 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 61 states, 61 states have (on average 4.475409836065574) internal successors, (273), 60 states have internal predecessors, (273), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:42:05,897 INFO L276 IsEmpty]: Start isEmpty. Operand 7173 states and 24099 transitions. [2022-03-15 21:42:05,909 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2022-03-15 21:42:05,909 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:42:05,909 INFO L514 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:42:05,925 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Forceful destruction successful, exit code 0 [2022-03-15 21:42:06,110 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable21,19 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:42:06,110 INFO L402 AbstractCegarLoop]: === Iteration 23 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION (and 1 more)] === [2022-03-15 21:42:06,111 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:42:06,111 INFO L85 PathProgramCache]: Analyzing trace with hash -1442443621, now seen corresponding path program 19 times [2022-03-15 21:42:06,111 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:42:06,111 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1828266920] [2022-03-15 21:42:06,112 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:42:06,112 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:42:06,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:42:06,435 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 3 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:42:06,435 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:42:06,435 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1828266920] [2022-03-15 21:42:06,435 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1828266920] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:42:06,435 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [956086159] [2022-03-15 21:42:06,435 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-03-15 21:42:06,435 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:42:06,436 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:42:06,436 INFO L229 MonitoredProcess]: Starting monitored process 20 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:42:06,438 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2022-03-15 21:42:06,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:42:06,469 INFO L263 TraceCheckSpWp]: Trace formula consists of 143 conjuncts, 45 conjunts are in the unsatisfiable core [2022-03-15 21:42:06,470 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:42:06,954 INFO L353 Elim1Store]: treesize reduction 36, result has 2.7 percent of original size [2022-03-15 21:42:06,954 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 53 treesize of output 29 [2022-03-15 21:42:07,250 INFO L353 Elim1Store]: treesize reduction 32, result has 3.0 percent of original size [2022-03-15 21:42:07,250 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 38 treesize of output 18 [2022-03-15 21:42:07,320 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 3 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:42:07,320 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:42:07,851 INFO L353 Elim1Store]: treesize reduction 76, result has 52.8 percent of original size [2022-03-15 21:42:07,852 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 0 disjoint index pairs (out of 15 index pairs), introduced 6 new quantified variables, introduced 15 case distinctions, treesize of input 52 treesize of output 116 [2022-03-15 21:42:08,452 INFO L353 Elim1Store]: treesize reduction 76, result has 52.8 percent of original size [2022-03-15 21:42:08,453 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 0 disjoint index pairs (out of 15 index pairs), introduced 6 new quantified variables, introduced 15 case distinctions, treesize of input 47 treesize of output 111 [2022-03-15 21:42:08,939 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 9 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:42:08,939 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [956086159] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:42:08,939 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:42:08,939 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 49 [2022-03-15 21:42:08,939 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [180434342] [2022-03-15 21:42:08,939 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:42:08,943 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:42:09,003 INFO L252 McrAutomatonBuilder]: Finished intersection with 318 states and 787 transitions. [2022-03-15 21:42:09,004 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:42:27,133 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 49 new interpolants: [406710#(or (<= back1 front1) (<= (+ d2 (select queue2 front2)) (* 2 W)) (not v_assert) (< 0 w) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))), 406700#(and (or (<= d2 (* 2 W)) v_assert) (or (<= d2 (* 2 W)) (< 0 w))), 406719#(and (or (not v_assert) (not (< front1 back1)) (= (+ (- 1) (select queue1 front1)) 0)) (or (not v_assert) (not (< front1 back1)) (<= (+ d2 (select queue2 front2) 4) (* 2 W))) (or (not v_assert) (not (< front1 back1)) (= (select queue1 (+ front1 1)) 1)) (or (not v_assert) (not (< front1 back1)) (<= back2 (+ front2 1))) (or (not v_assert) (not (< front1 back1)) (<= (+ front2 1) back2))), 406694#(and (or (<= back1 front1) (<= (+ 2 d2 (select queue2 front2)) (* 2 W))) (or (<= back1 front1) (<= (+ front2 1) back2)) (or (<= back1 front1) (<= back2 (+ front2 1))) (or (<= back1 front1) (= (select queue1 front1) 1))), 406707#(and (or (<= back1 front1) (<= (+ d2 (select queue2 front2)) (* 2 W)) (< 0 w) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (<= back1 front1) (<= (+ d2 (select queue2 front2)) (* 2 W)) v_assert (not (= (+ (select queue1 front1) 1) (select queue2 back2))))), 406691#(or (<= (+ d2 (select queue2 front2)) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1)))), 406696#(or (<= back1 front1) (<= (+ d2 (select queue2 front2)) (* 2 W)) (not v_assert) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))), 406715#(and (or (<= back1 front1) (not v_assert) (<= back2 (+ front2 1)) (< 0 w)) (or (<= back1 front1) (not v_assert) (< 0 w) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= back1 front1) (not v_assert) (<= (+ front2 1) back2) (< 0 w))), 406705#(and (or (<= back2 front2) (< 0 w)) (or (< front2 (+ back2 1)) v_assert) (or v_assert (<= back2 front2)) (or (< front2 (+ back2 1)) (< 0 w)) (or (= temp1 1) (< 0 w)) (or v_assert (<= (+ 2 d2 temp2) (* 2 W))) (or (= temp1 1) v_assert) (or (< 0 w) (<= (+ 2 d2 temp2) (* 2 W)))), 406726#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back1 (+ front1 1))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (not v_assert) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (<= (+ front1 1) back1) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (<= (+ d2 (select queue2 front2) 4) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1))))), 406717#(and (or (<= (+ front2 2) back2) v_assert) (or v_assert (<= back2 (+ front2 2))) (or (< 0 w) (= (select queue1 front1) 1)) (or (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w)) (or v_assert (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))) (or v_assert (= (select queue1 front1) 1)) (or (<= back2 (+ front2 2)) (< 0 w)) (or (<= (+ front2 2) back2) (< 0 w))), 406738#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (= front1 back1)) (or (not v_assert) (= W w)) (or (not v_assert) (<= d2 0))), 406720#(and (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ d2 (select queue2 front2) 4) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (= (select queue1 (+ front1 1)) 1))), 406697#(and (or (<= back1 front1) (not v_assert) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (< front2 (+ back2 1))) (or (<= back1 front1) (not v_assert) (<= back2 front2)) (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 temp2) (* 2 W)))), 406706#(and (or (<= back2 (+ front2 1)) (< 0 w)) (or (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or v_assert (<= (+ front2 1) back2)) (or (<= (+ front2 1) back2) (< 0 w)) (or (<= back2 (+ front2 1)) v_assert) (or (= temp1 1) (< 0 w)) (or (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) v_assert) (or (= temp1 1) v_assert)), 406693#(and (or (<= back1 front1) (< front2 (+ back2 1))) (or (<= back1 front1) (<= (+ 2 d2 temp2) (* 2 W))) (or (<= back1 front1) (<= back2 front2)) (or (<= back1 front1) (= (select queue1 front1) 1))), 406733#(and (or (not v_assert) (<= (+ front2 2) back2) (< 0 w)) (or (not v_assert) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w)) (or (not v_assert) (< 0 w) (= (select queue1 front1) 1)) (or (not v_assert) (<= back2 (+ front2 2)) (< 0 w))), 406736#(and (or (not v_assert) (not (< front1 back1)) (<= front2 back2) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (<= back1 (+ front1 1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert) (not (< front1 back1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (<= back2 front2) (not (= (+ (select queue1 front1) 1) (select queue2 back2))))), 406735#(and (or (not v_assert) (<= (+ d2 (select queue2 front2) 4) (* 2 W)) (< 0 w)) (or (not v_assert) (<= back2 (+ front2 1)) (< 0 w)) (or (not v_assert) (= (+ (- 1) temp1) 0) (< 0 w)) (or (not v_assert) (< 0 w) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ front2 1) back2) (< 0 w))), 406703#(and (or (<= (+ d2 (select queue2 front2)) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1))) (< 0 w)) (or (<= (+ d2 (select queue2 front2)) (* 2 W)) v_assert (not (= (select queue2 back2) (+ temp1 1))))), 406725#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (= (select queue1 (+ front1 1)) 1) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (not v_assert) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (<= (+ d2 (select queue2 front2) 4) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1))))), 406695#(and (or (<= back1 front1) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W))) (or (<= back1 front1) (<= (+ front2 1) back2)) (or (<= back1 front1) (<= back2 (+ front2 1))) (or (<= back1 front1) (= (select queue1 front1) 1))), 406712#(and (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= back1 front1) (not v_assert) (<= back2 (+ front2 1)) (< 0 w)) (or (<= back1 front1) (not v_assert) (< 0 w) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (<= (+ front2 1) back2) (< 0 w))), 406716#(and (or (<= (+ front2 2) back2) v_assert) (or v_assert (<= back2 (+ front2 2))) (or (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w)) (or v_assert (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))) (or (= temp1 1) (< 0 w)) (or (<= back2 (+ front2 2)) (< 0 w)) (or (= temp1 1) v_assert) (or (<= (+ front2 2) back2) (< 0 w))), 406727#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back1 (+ front1 1))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (not v_assert) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 front2) (* 2 w)) (* 2 W))) (or (not v_assert) (<= (+ front1 1) back1) (not (= (select queue2 back2) (+ temp1 1))))), 406709#(and (or (<= back1 front1) (< 0 w) (= (select queue1 front1) 1)) (or (<= back1 front1) v_assert (<= (+ front2 1) back2)) (or (<= back1 front1) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= back1 front1) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) v_assert) (or (<= back1 front1) (<= back2 (+ front2 1)) (< 0 w)) (or (<= back1 front1) (<= (+ front2 1) back2) (< 0 w)) (or (<= back1 front1) (<= back2 (+ front2 1)) v_assert) (or (<= back1 front1) v_assert (= (select queue1 front1) 1))), 406698#(and (or (<= back1 front1) (not v_assert) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W))) (or (<= back1 front1) (not v_assert) (<= back2 (+ front2 1))) (or (<= back1 front1) (not v_assert) (<= (+ front2 1) back2))), 406702#(and (or (<= (+ d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ d2 (select queue2 front2)) (* 2 W)) v_assert)), 406737#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (<= back1 (+ front1 1))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ 2 d2 (* 2 w)) (* 2 W))) (or (not v_assert) (<= (+ front1 1) back1))), 406724#(and (or (not v_assert) (not (< front1 back1)) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (not (< front1 back1)) (= (+ (- 1) (select queue1 front1)) 0) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (< front1 back1)) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (< front1 back1)) (<= (+ d2 (select queue2 front2) 4) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (< front1 back1)) (= (select queue1 (+ front1 1)) 1) (not (= (select queue2 back2) (+ temp1 1))))), 406728#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert) (not (= (select queue2 back2) (+ temp1 1)))) (or (<= back1 front1) (not v_assert) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (<= front1 back1) (not (= (select queue2 back2) (+ temp1 1))))), 406721#(and (or (not v_assert) (<= back1 (+ front1 1))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ front1 1) back1)) (or (not v_assert) (<= (+ d2 (select queue2 front2) 4) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2))), 406730#(and (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 2))) (or (not v_assert) (<= (+ front2 2) back2))), 406732#(and (or (not v_assert) (<= (+ front2 2) back2) (< 0 w)) (or (not v_assert) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w)) (or (not v_assert) (= temp1 1) (< 0 w)) (or (not v_assert) (<= back2 (+ front2 2)) (< 0 w))), 406718#(and (or (not (< front1 back1)) (<= (+ front2 1) back2)) (or (not (< front1 back1)) (<= back2 (+ front2 1))) (or (not (< front1 back1)) (<= (+ d2 (select queue2 front2) 4) (* 2 W))) (or (not (< front1 back1)) (= (+ (- 1) (select queue1 front1)) 0)) (or (not (< front1 back1)) (= (select queue1 (+ front1 1)) 1))), 406692#(or (<= back1 front1) (<= (+ d2 (select queue2 front2)) (* 2 W)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))), 406708#(and (or (<= back1 front1) (< 0 w) (<= (+ 2 d2 temp2) (* 2 W))) (or (<= back1 front1) (<= back2 front2) (< 0 w)) (or (<= back1 front1) (< 0 w) (= (select queue1 front1) 1)) (or (<= back1 front1) v_assert (<= (+ 2 d2 temp2) (* 2 W))) (or (<= back1 front1) v_assert (<= back2 front2)) (or (<= back1 front1) (< front2 (+ back2 1)) v_assert) (or (<= back1 front1) (< front2 (+ back2 1)) (< 0 w)) (or (<= back1 front1) v_assert (= (select queue1 front1) 1))), 406722#(and (or (not v_assert) (<= back1 (+ front1 1))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2) (* 2 w)) (* 2 W))) (or (not v_assert) (<= (+ front1 1) back1)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2))), 406701#(and (or (<= (+ d2 temp2) (* 2 W)) v_assert) (or (<= (+ d2 temp2) (* 2 W)) (< 0 w))), 406729#(and (or (= (+ (- 1) temp1) 0) (< 0 w)) (or (<= (+ d2 (select queue2 front2) 4) (* 2 W)) (< 0 w)) (or (<= back2 (+ front2 1)) (< 0 w)) (or (< 0 w) (= (select queue1 front1) 1)) (or v_assert (<= (+ front2 1) back2)) (or (<= (+ front2 1) back2) (< 0 w)) (or v_assert (= (select queue1 front1) 1)) (or (<= back2 (+ front2 1)) v_assert) (or (<= (+ d2 (select queue2 front2) 4) (* 2 W)) v_assert) (or v_assert (= (+ (- 1) temp1) 0))), 406731#(and (or (not v_assert) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 2))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ front2 2) back2))), 406699#(and (or (<= back1 front1) (not v_assert) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W))) (or (<= back1 front1) (not v_assert) (<= back2 (+ front2 1))) (or (<= back1 front1) (not v_assert) (<= (+ front2 1) back2))), 406704#(and (or (<= (+ d2 temp2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ d2 temp2 (select queue2 front2)) (* 2 W)) v_assert)), 406711#(and (or (<= back1 front1) (not v_assert) (<= back2 front2) (< 0 w)) (or (<= back1 front1) (not v_assert) (< front2 (+ back2 1)) (< 0 w)) (or (<= back1 front1) (not v_assert) (< 0 w) (<= (+ 2 d2 temp2) (* 2 W))) (or (<= back1 front1) (not v_assert) (< 0 w) (= (select queue1 front1) 1))), 406723#(and (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= front1 back1)) (or (not v_assert) (<= (+ front2 1) back2)) (or (<= back1 front1) (not v_assert))), 406739#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= (+ 2 d2 (* 2 w)) (* 2 W))) (or (not v_assert) (<= front1 back1)) (or (<= back1 front1) (not v_assert))), 406734#(and (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (= (+ (- 1) temp1) 0)) (or (not v_assert) (<= (+ d2 (select queue2 front2) 4) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2))), 406714#(and (or (<= back1 front1) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= back1 front1) (< 0 w) (= (select queue1 front1) 1)) (or (<= back1 front1) v_assert (<= (+ front2 1) back2)) (or (<= back1 front1) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) v_assert) (or (<= back1 front1) (<= back2 (+ front2 1)) (< 0 w)) (or (<= back1 front1) (<= (+ front2 1) back2) (< 0 w)) (or (<= back1 front1) (<= back2 (+ front2 1)) v_assert) (or (<= back1 front1) v_assert (= (select queue1 front1) 1))), 406713#(and (or (<= back2 (+ front2 1)) (< 0 w)) (or v_assert (<= (+ front2 1) back2)) (or (<= (+ front2 1) back2) (< 0 w)) (or (<= back2 (+ front2 1)) v_assert) (or (= temp1 1) (< 0 w)) (or (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (= temp1 1) v_assert) (or (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) v_assert))] [2022-03-15 21:42:27,133 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 69 states [2022-03-15 21:42:27,133 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:42:27,133 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2022-03-15 21:42:27,134 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=717, Invalid=8985, Unknown=0, NotChecked=0, Total=9702 [2022-03-15 21:42:27,134 INFO L87 Difference]: Start difference. First operand 7173 states and 24099 transitions. Second operand has 69 states, 69 states have (on average 4.478260869565218) internal successors, (309), 68 states have internal predecessors, (309), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:42:37,830 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:42:37,830 INFO L93 Difference]: Finished difference Result 17795 states and 59671 transitions. [2022-03-15 21:42:37,831 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 79 states. [2022-03-15 21:42:37,831 INFO L78 Accepts]: Start accepts. Automaton has has 69 states, 69 states have (on average 4.478260869565218) internal successors, (309), 68 states have internal predecessors, (309), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 38 [2022-03-15 21:42:37,831 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:42:37,872 INFO L225 Difference]: With dead ends: 17795 [2022-03-15 21:42:37,872 INFO L226 Difference]: Without dead ends: 17665 [2022-03-15 21:42:37,873 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 448 GetRequests, 266 SyntacticMatches, 9 SemanticMatches, 173 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8633 ImplicationChecksByTransitivity, 12.1s TimeCoverageRelationStatistics Valid=3409, Invalid=27041, Unknown=0, NotChecked=0, Total=30450 [2022-03-15 21:42:37,873 INFO L933 BasicCegarLoop]: 1 mSDtfsCounter, 1050 mSDsluCounter, 1877 mSDsCounter, 0 mSdLazyCounter, 6325 mSolverCounterSat, 481 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 2.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1050 SdHoareTripleChecker+Valid, 3 SdHoareTripleChecker+Invalid, 6806 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 481 IncrementalHoareTripleChecker+Valid, 6325 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 2.8s IncrementalHoareTripleChecker+Time [2022-03-15 21:42:37,873 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [1050 Valid, 3 Invalid, 6806 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [481 Valid, 6325 Invalid, 0 Unknown, 0 Unchecked, 2.8s Time] [2022-03-15 21:42:37,889 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17665 states. [2022-03-15 21:42:38,018 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17665 to 6975. [2022-03-15 21:42:38,026 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6975 states, 6974 states have (on average 3.370232291367938) internal successors, (23504), 6974 states have internal predecessors, (23504), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:42:38,043 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6975 states to 6975 states and 23504 transitions. [2022-03-15 21:42:38,043 INFO L78 Accepts]: Start accepts. Automaton has 6975 states and 23504 transitions. Word has length 38 [2022-03-15 21:42:38,043 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:42:38,043 INFO L470 AbstractCegarLoop]: Abstraction has 6975 states and 23504 transitions. [2022-03-15 21:42:38,043 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 69 states, 69 states have (on average 4.478260869565218) internal successors, (309), 68 states have internal predecessors, (309), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:42:38,043 INFO L276 IsEmpty]: Start isEmpty. Operand 6975 states and 23504 transitions. [2022-03-15 21:42:38,054 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2022-03-15 21:42:38,054 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:42:38,054 INFO L514 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:42:38,069 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Ended with exit code 0 [2022-03-15 21:42:38,254 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable22,20 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:42:38,254 INFO L402 AbstractCegarLoop]: === Iteration 24 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION (and 1 more)] === [2022-03-15 21:42:38,255 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:42:38,255 INFO L85 PathProgramCache]: Analyzing trace with hash 413406227, now seen corresponding path program 20 times [2022-03-15 21:42:38,255 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:42:38,255 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [838167189] [2022-03-15 21:42:38,255 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:42:38,256 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:42:38,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:42:38,570 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 3 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:42:38,570 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:42:38,570 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [838167189] [2022-03-15 21:42:38,570 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [838167189] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:42:38,570 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [938771543] [2022-03-15 21:42:38,570 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-03-15 21:42:38,570 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:42:38,571 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:42:38,571 INFO L229 MonitoredProcess]: Starting monitored process 21 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:42:38,572 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2022-03-15 21:42:38,603 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-03-15 21:42:38,603 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:42:38,604 INFO L263 TraceCheckSpWp]: Trace formula consists of 143 conjuncts, 45 conjunts are in the unsatisfiable core [2022-03-15 21:42:38,605 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:42:39,103 INFO L353 Elim1Store]: treesize reduction 36, result has 2.7 percent of original size [2022-03-15 21:42:39,104 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 53 treesize of output 29 [2022-03-15 21:42:39,372 INFO L353 Elim1Store]: treesize reduction 32, result has 3.0 percent of original size [2022-03-15 21:42:39,372 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 38 treesize of output 18 [2022-03-15 21:42:39,441 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 3 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:42:39,441 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:42:39,889 INFO L353 Elim1Store]: treesize reduction 76, result has 52.8 percent of original size [2022-03-15 21:42:39,889 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 0 disjoint index pairs (out of 15 index pairs), introduced 6 new quantified variables, introduced 15 case distinctions, treesize of input 52 treesize of output 116 [2022-03-15 21:42:40,709 INFO L353 Elim1Store]: treesize reduction 76, result has 52.8 percent of original size [2022-03-15 21:42:40,710 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 0 disjoint index pairs (out of 15 index pairs), introduced 6 new quantified variables, introduced 15 case distinctions, treesize of input 47 treesize of output 111 [2022-03-15 21:42:41,280 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 10 proven. 23 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:42:41,280 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [938771543] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:42:41,280 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:42:41,280 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 46 [2022-03-15 21:42:41,280 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [430665406] [2022-03-15 21:42:41,281 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:42:41,284 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:42:41,332 INFO L252 McrAutomatonBuilder]: Finished intersection with 255 states and 597 transitions. [2022-03-15 21:42:41,333 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:42:54,694 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 33 new interpolants: [438921#(and (or (<= d2 (* 2 W)) v_assert) (or (<= d2 (* 2 W)) (< 0 w))), 438922#(and (or (<= (+ d2 temp2) (* 2 W)) v_assert) (or (<= (+ d2 temp2) (* 2 W)) (< 0 w))), 438906#(and (or (not (< front1 back1)) (<= (+ front2 1) back2)) (or (not (< front1 back1)) (<= back2 (+ front2 1))) (or (not (< front1 back1)) (<= (+ d2 (select queue2 front2) 4) (* 2 W))) (or (not (< front1 back1)) (= (+ (- 1) (select queue1 front1)) 0)) (or (not (< front1 back1)) (= (select queue1 (+ front1 1)) 1))), 438937#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (<= back1 (+ front1 1))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ 2 d2 (* 2 w)) (* 2 W))) (or (not v_assert) (<= (+ front1 1) back1))), 438924#(and (or (<= (+ d2 temp2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ d2 temp2 (select queue2 front2)) (* 2 W)) v_assert)), 438925#(and (or (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) v_assert)), 438909#(and (or (not v_assert) (not (< front1 back1)) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (not (< front1 back1)) (= (+ (- 1) (select queue1 front1)) 0) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (< front1 back1)) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (< front1 back1)) (<= (+ d2 (select queue2 front2) 4) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (< front1 back1)) (= (select queue1 (+ front1 1)) 1) (not (= (select queue2 back2) (+ temp1 1))))), 438907#(and (or (not v_assert) (not (< front1 back1)) (= (+ (- 1) (select queue1 front1)) 0)) (or (not v_assert) (not (< front1 back1)) (<= (+ d2 (select queue2 front2) 4) (* 2 W))) (or (not v_assert) (not (< front1 back1)) (= (select queue1 (+ front1 1)) 1)) (or (not v_assert) (not (< front1 back1)) (<= back2 (+ front2 1))) (or (not v_assert) (not (< front1 back1)) (<= (+ front2 1) back2))), 438936#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= (+ 2 d2 (* 2 w)) (* 2 W))) (or (not v_assert) (<= front1 back1)) (or (<= back1 front1) (not v_assert))), 438928#(and (or (<= (+ front2 2) back2) v_assert) (or v_assert (<= back2 (+ front2 2))) (or (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w)) (or v_assert (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))) (or (= temp1 1) (< 0 w)) (or (<= back2 (+ front2 2)) (< 0 w)) (or (= temp1 1) v_assert) (or (<= (+ front2 2) back2) (< 0 w))), 438911#(or (not v_assert) (<= (+ (select queue2 (+ front2 2)) d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))), 438926#(and (or (<= (+ d2 temp2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) v_assert) (or (<= (+ d2 temp2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w))), 438914#(and (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (= (+ (- 1) temp1) 0)) (or (not v_assert) (<= (+ d2 (select queue2 front2) 4) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2))), 438913#(and (or (not v_assert) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 2))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ front2 2) back2))), 438938#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (= front1 back1)) (or (not v_assert) (= W w)) (or (not v_assert) (<= d2 0))), 438908#(and (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ d2 (select queue2 front2) 4) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (= (select queue1 (+ front1 1)) 1))), 438927#(and (or (<= (+ (select queue2 (+ front2 2)) d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ (select queue2 (+ front2 2)) d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) v_assert)), 438934#(and (or (not v_assert) (<= (+ d2 (select queue2 front2) 4) (* 2 W)) (< 0 w)) (or (not v_assert) (<= back2 (+ front2 1)) (< 0 w)) (or (not v_assert) (= (+ (- 1) temp1) 0) (< 0 w)) (or (not v_assert) (< 0 w) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ front2 1) back2) (< 0 w))), 438923#(and (or (<= (+ d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ d2 (select queue2 front2)) (* 2 W)) v_assert)), 438918#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back1 (+ front1 1))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (not v_assert) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 front2) (* 2 w)) (* 2 W))) (or (not v_assert) (<= (+ front1 1) back1) (not (= (select queue2 back2) (+ temp1 1))))), 438930#(and (or (= (+ (- 1) temp1) 0) (< 0 w)) (or (<= (+ d2 (select queue2 front2) 4) (* 2 W)) (< 0 w)) (or (<= back2 (+ front2 1)) (< 0 w)) (or (< 0 w) (= (select queue1 front1) 1)) (or v_assert (<= (+ front2 1) back2)) (or (<= (+ front2 1) back2) (< 0 w)) (or v_assert (= (select queue1 front1) 1)) (or (<= back2 (+ front2 1)) v_assert) (or (<= (+ d2 (select queue2 front2) 4) (* 2 W)) v_assert) (or v_assert (= (+ (- 1) temp1) 0))), 438917#(and (or (not v_assert) (<= back1 (+ front1 1))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2) (* 2 w)) (* 2 W))) (or (not v_assert) (<= (+ front1 1) back1)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2))), 438935#(and (or (not v_assert) (not (< front1 back1)) (<= front2 back2) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (<= back1 (+ front1 1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert) (not (< front1 back1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (<= back2 front2) (not (= (+ (select queue1 front1) 1) (select queue2 back2))))), 438919#(and (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= front1 back1)) (or (not v_assert) (<= (+ front2 1) back2)) (or (<= back1 front1) (not v_assert))), 438916#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back1 (+ front1 1))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (not v_assert) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (<= (+ front1 1) back1) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (<= (+ d2 (select queue2 front2) 4) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1))))), 438910#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (= (select queue1 (+ front1 1)) 1) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (not v_assert) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (<= (+ d2 (select queue2 front2) 4) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1))))), 438915#(and (or (not v_assert) (<= back1 (+ front1 1))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ front1 1) back1)) (or (not v_assert) (<= (+ d2 (select queue2 front2) 4) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2))), 438929#(and (or (<= (+ front2 2) back2) v_assert) (or v_assert (<= back2 (+ front2 2))) (or (< 0 w) (= (select queue1 front1) 1)) (or (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w)) (or v_assert (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))) (or v_assert (= (select queue1 front1) 1)) (or (<= back2 (+ front2 2)) (< 0 w)) (or (<= (+ front2 2) back2) (< 0 w))), 438933#(and (or (not v_assert) (<= (+ front2 2) back2) (< 0 w)) (or (not v_assert) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w)) (or (not v_assert) (< 0 w) (= (select queue1 front1) 1)) (or (not v_assert) (<= back2 (+ front2 2)) (< 0 w))), 438931#(or (not v_assert) (<= (+ (select queue2 (+ front2 2)) d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w)), 438912#(and (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 2))) (or (not v_assert) (<= (+ front2 2) back2))), 438920#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert) (not (= (select queue2 back2) (+ temp1 1)))) (or (<= back1 front1) (not v_assert) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (<= front1 back1) (not (= (select queue2 back2) (+ temp1 1))))), 438932#(and (or (not v_assert) (<= (+ front2 2) back2) (< 0 w)) (or (not v_assert) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w)) (or (not v_assert) (= temp1 1) (< 0 w)) (or (not v_assert) (<= back2 (+ front2 2)) (< 0 w)))] [2022-03-15 21:42:54,694 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 53 states [2022-03-15 21:42:54,694 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:42:54,694 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2022-03-15 21:42:54,694 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=404, Invalid=5916, Unknown=0, NotChecked=0, Total=6320 [2022-03-15 21:42:54,695 INFO L87 Difference]: Start difference. First operand 6975 states and 23504 transitions. Second operand has 53 states, 53 states have (on average 4.471698113207547) internal successors, (237), 52 states have internal predecessors, (237), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:43:02,242 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:43:02,243 INFO L93 Difference]: Finished difference Result 14440 states and 48392 transitions. [2022-03-15 21:43:02,243 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2022-03-15 21:43:02,243 INFO L78 Accepts]: Start accepts. Automaton has has 53 states, 53 states have (on average 4.471698113207547) internal successors, (237), 52 states have internal predecessors, (237), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 38 [2022-03-15 21:43:02,243 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:43:02,276 INFO L225 Difference]: With dead ends: 14440 [2022-03-15 21:43:02,276 INFO L226 Difference]: Without dead ends: 14388 [2022-03-15 21:43:02,277 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 366 GetRequests, 222 SyntacticMatches, 9 SemanticMatches, 135 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4877 ImplicationChecksByTransitivity, 8.3s TimeCoverageRelationStatistics Valid=1664, Invalid=16968, Unknown=0, NotChecked=0, Total=18632 [2022-03-15 21:43:02,277 INFO L933 BasicCegarLoop]: 1 mSDtfsCounter, 676 mSDsluCounter, 1688 mSDsCounter, 0 mSdLazyCounter, 5479 mSolverCounterSat, 300 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 2.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 676 SdHoareTripleChecker+Valid, 3 SdHoareTripleChecker+Invalid, 5779 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 300 IncrementalHoareTripleChecker+Valid, 5479 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 2.3s IncrementalHoareTripleChecker+Time [2022-03-15 21:43:02,277 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [676 Valid, 3 Invalid, 5779 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [300 Valid, 5479 Invalid, 0 Unknown, 0 Unchecked, 2.3s Time] [2022-03-15 21:43:02,290 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14388 states. [2022-03-15 21:43:02,398 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14388 to 6936. [2022-03-15 21:43:02,406 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6936 states, 6935 states have (on average 3.3749098774333093) internal successors, (23405), 6935 states have internal predecessors, (23405), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:43:02,422 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6936 states to 6936 states and 23405 transitions. [2022-03-15 21:43:02,422 INFO L78 Accepts]: Start accepts. Automaton has 6936 states and 23405 transitions. Word has length 38 [2022-03-15 21:43:02,422 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:43:02,422 INFO L470 AbstractCegarLoop]: Abstraction has 6936 states and 23405 transitions. [2022-03-15 21:43:02,422 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 53 states, 53 states have (on average 4.471698113207547) internal successors, (237), 52 states have internal predecessors, (237), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:43:02,422 INFO L276 IsEmpty]: Start isEmpty. Operand 6936 states and 23405 transitions. [2022-03-15 21:43:02,432 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2022-03-15 21:43:02,433 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:43:02,433 INFO L514 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:43:02,448 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Forceful destruction successful, exit code 0 [2022-03-15 21:43:02,641 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 21 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable23 [2022-03-15 21:43:02,642 INFO L402 AbstractCegarLoop]: === Iteration 25 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION (and 1 more)] === [2022-03-15 21:43:02,642 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:43:02,642 INFO L85 PathProgramCache]: Analyzing trace with hash -913751949, now seen corresponding path program 21 times [2022-03-15 21:43:02,642 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:43:02,643 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1301200051] [2022-03-15 21:43:02,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:43:02,643 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:43:02,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:43:03,027 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 3 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:43:03,027 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:43:03,027 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1301200051] [2022-03-15 21:43:03,027 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1301200051] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:43:03,027 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1101745691] [2022-03-15 21:43:03,028 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-03-15 21:43:03,028 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:43:03,028 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:43:03,029 INFO L229 MonitoredProcess]: Starting monitored process 22 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:43:03,032 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2022-03-15 21:43:03,063 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2022-03-15 21:43:03,063 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:43:03,064 INFO L263 TraceCheckSpWp]: Trace formula consists of 143 conjuncts, 46 conjunts are in the unsatisfiable core [2022-03-15 21:43:03,064 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:43:03,863 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:43:03,864 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:43:03,864 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:43:03,864 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:03,865 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-03-15 21:43:03,865 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 3 disjoint index pairs (out of 6 index pairs), introduced 3 new quantified variables, introduced 0 case distinctions, treesize of input 51 treesize of output 31 [2022-03-15 21:43:03,976 INFO L353 Elim1Store]: treesize reduction 32, result has 3.0 percent of original size [2022-03-15 21:43:03,976 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 38 treesize of output 18 [2022-03-15 21:43:04,055 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 3 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:43:04,055 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:43:04,734 INFO L353 Elim1Store]: treesize reduction 76, result has 52.8 percent of original size [2022-03-15 21:43:04,734 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 0 disjoint index pairs (out of 15 index pairs), introduced 6 new quantified variables, introduced 15 case distinctions, treesize of input 50 treesize of output 114 [2022-03-15 21:43:05,476 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:05,476 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:05,478 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:05,479 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:05,479 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:05,479 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:05,480 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:05,481 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:05,481 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:43:05,500 INFO L353 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-03-15 21:43:05,500 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 9 disjoint index pairs (out of 15 index pairs), introduced 6 new quantified variables, introduced 6 case distinctions, treesize of input 45 treesize of output 85 [2022-03-15 21:43:05,891 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 3 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:43:05,891 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1101745691] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:43:05,891 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:43:05,891 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 50 [2022-03-15 21:43:05,891 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1731434907] [2022-03-15 21:43:05,891 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:43:05,895 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:43:05,962 INFO L252 McrAutomatonBuilder]: Finished intersection with 347 states and 876 transitions. [2022-03-15 21:43:05,962 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:43:29,792 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 56 new interpolants: [467652#(and (or (<= back1 front1) (< front2 (+ back2 1))) (or (<= back1 front1) (<= (+ 2 d2) (* 2 W))) (or (<= back1 front1) (<= back2 front2)) (or (<= back1 front1) (= (select queue1 front1) 1))), 467676#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1)) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (not (< front2 back2)) (= (select queue1 front1) 1))), 467687#(and (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 (+ back2 1)) (+ (select queue1 (+ front1 1)) 1))) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (not (< (+ front1 1) back1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 (+ back2 1)) (+ (select queue1 (+ front1 1)) 1))) (not (< (+ front1 1) back1)) (= back1 (+ front1 2)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (= (select queue2 (+ back2 1)) (+ (select queue1 (+ front1 1)) 1))) (<= back2 front2) (not (< (+ front1 1) back1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2))))), 467649#(or (not v_assert) (<= (+ d2 temp2 (select queue2 front2)) (* 2 W)) (< 0 w)), 467688#(and (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2) (* 2 w)) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 467673#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (+ (* (- 1) front1) back1) 0)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))))), 467664#(and (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (not (< front2 back2)) (= (select queue1 front1) 1))), 467685#(and (or (not (< front1 back1)) (= (+ (- 1) (* (- 1) front1) back1) 0)) (or (not (< front1 back1)) (<= front2 back2)) (or (not (< front1 back1)) (<= back2 front2)) (or (not (< front1 back1)) (= (select queue1 front1) 1)) (or (not (< front1 back1)) (<= (+ 2 d2 temp2 (* 2 w)) (* 2 W)))), 467654#(and (or (not v_assert) (<= (+ 2 d2) (* 2 W))) (or (not v_assert) (< front2 (+ back2 1))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= back2 front2))), 467655#(and (or (not v_assert) (<= (+ 2 d2) (* 2 W))) (or (not v_assert) (< front2 (+ back2 1))) (or (not v_assert) (<= back2 front2)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 467662#(and (or (not v_assert) (<= back2 (+ front2 1)) (< 0 w)) (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (< 0 w) (not (< front2 back2))) (or (not v_assert) (= temp1 1) (< 0 w) (not (< front2 back2)))), 467666#(and (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (not (< front2 back2)) (= (select queue1 front1) 1))), 467667#(and (or (not v_assert) (= (+ (* (- 1) front1) back1) 0) (not (< front2 back2))) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1)))), 467671#(and (or (<= back1 front1) (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (<= back1 front1) (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (not (< front2 (+ back2 1))) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1))))), 467651#(and (or (not v_assert) (<= back2 (+ front2 1)) (< 0 w)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (< 0 w) (not (< front2 back2))) (or (not v_assert) (= temp1 1) (< 0 w) (not (< front2 back2)))), 467692#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (<= back1 (+ front1 1))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ 2 d2 (* 2 w)) (* 2 W))) (or (not v_assert) (<= (+ front1 1) back1))), 467648#(and (or (not v_assert) (<= back2 front2) (< 0 w)) (or (not v_assert) (< front2 (+ back2 1)) (< 0 w)) (or (not v_assert) (< 0 w) (<= (+ 2 d2) (* 2 W))) (or (not v_assert) (= temp1 1) (< 0 w))), 467641#(and (or (<= back2 front2) (< 0 w)) (or (< front2 (+ back2 1)) v_assert) (or v_assert (<= back2 front2)) (or v_assert (<= (+ 2 d2) (* 2 W))) (or (< front2 (+ back2 1)) (< 0 w)) (or (= temp1 1) (< 0 w)) (or (= temp1 1) v_assert) (or (< 0 w) (<= (+ 2 d2) (* 2 W)))), 467661#(and (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (= temp1 1) (not (< front2 back2)))), 467665#(and (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (<= back1 front1) (not v_assert) (not (< front2 back2)) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (<= back2 (+ front2 1)))), 467646#(and (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (= temp1 1) (not (< front2 back2)))), 467691#(and (or (not v_assert) (<= (+ front1 2) back1)) (or (not v_assert) (= front2 back2)) (or (not v_assert) (<= back1 (+ front1 2))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ d2 4 (* 2 w)) (* 2 W))) (or (not v_assert) (= (select queue1 (+ front1 1)) 1))), 467679#(and (or (not v_assert) (not (< front1 back1)) (not (< front2 (+ back2 1))) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (= (+ (- 1) (* (- 1) front1) back1) 0) (not (< front2 (+ back2 1))) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (<= back2 front2) (not (= (+ (select queue1 front1) 1) (select queue2 back2))))), 467677#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (= front1 back1) (not (= (select queue2 back2) (+ temp1 1))) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1)) (not (= (select queue2 back2) (+ temp1 1))))), 467690#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (<= back1 (+ front1 1))) (or (not v_assert) (= temp1 1)) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ front1 1) back1)) (or (not v_assert) (<= (+ d2 4 (* 2 w)) (* 2 W)))), 467642#(or (<= (+ d2 (select queue2 front2)) (* 2 W)) (not v_assert)), 467650#(and (or (not v_assert) (<= back2 front2) (< 0 w)) (or (not v_assert) (< front2 (+ back2 1)) (< 0 w)) (or (not v_assert) (< 0 w) (<= (+ 2 d2 temp2) (* 2 W))) (or (not v_assert) (= temp1 1) (< 0 w))), 467689#(and (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (= (+ (- 1) (* (- 1) front1) back1) 0)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2) (* 2 w)) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2))), 467656#(and (or (not v_assert) (< front2 (+ back2 1))) (or (not v_assert) (<= back2 front2)) (or (<= (+ d2 (* 2 w)) (* 2 W)) (not v_assert)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 467675#(and (or (<= back1 front1) (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (<= back1 front1) (not v_assert) (<= back2 (+ front2 1)) (not (= (select queue2 back2) (+ temp1 1)))) (or (<= back1 front1) (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (not (< front2 back2)) (= (select queue1 front1) 1))), 467686#(and (or (not v_assert) (not (< front1 back1)) (<= back2 front2)) (or (not v_assert) (not (< front1 back1)) (<= front2 back2)) (or (not v_assert) (not (< front1 back1)) (<= (+ 2 d2 temp2 (* 2 w)) (* 2 W))) (or (not v_assert) (not (< front1 back1)) (= (select queue1 front1) 1)) (or (not v_assert) (not (< front1 back1)) (= (+ (- 1) (* (- 1) front1) back1) 0))), 467639#(and (or (<= (+ d2 temp2) (* 2 W)) v_assert) (or (<= (+ d2 temp2) (* 2 W)) (< 0 w))), 467693#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (= front1 back1)) (or (not v_assert) (= W w)) (or (not v_assert) (<= d2 0))), 467647#(or (<= (+ d2 (select queue2 front2)) (* 2 W)) (not v_assert) (< 0 w)), 467684#(and (or (not v_assert) (not (< front1 back1)) (= (+ (- 1) (* (- 1) front1) back1) 0) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (<= front2 back2) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert) (not (< front1 back1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (<= back2 front2) (not (= (+ (select queue1 front1) 1) (select queue2 back2))))), 467638#(and (or (<= d2 (* 2 W)) v_assert) (or (<= d2 (* 2 W)) (< 0 w))), 467660#(and (or (not v_assert) (<= (+ d2 temp2 (* 2 w)) (* 2 W))) (or (not v_assert) (< front2 (+ back2 1))) (or (not v_assert) (<= back2 front2)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 467678#(and (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (< front1 back1)) (not (< front2 (+ back2 1))) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (= (+ (- 1) (* (- 1) front1) back1) 0) (not (< front2 (+ back2 1))) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (<= back2 front2) (not (= (+ (select queue1 front1) 1) (select queue2 back2))))), 467670#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))))), 467669#(and (or (<= back1 front1) (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (<= back1 front1) (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))))), 467653#(and (or (<= back1 front1) (not v_assert) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (< front2 (+ back2 1))) (or (<= back1 front1) (not v_assert) (<= (+ 2 d2) (* 2 W))) (or (<= back1 front1) (not v_assert) (<= back2 front2))), 467657#(and (or (<= back1 front1) (not v_assert) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (< front2 (+ back2 1))) (or (<= back1 front1) (not v_assert) (<= back2 front2)) (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 temp2) (* 2 W)))), 467672#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (not v_assert) (not (< front2 (+ back2 1))) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1))))), 467683#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (= (+ (* (- 1) front1) back1) 0))), 467644#(or (not v_assert) (<= (+ d2 temp2 (select queue2 front2)) (* 2 W))), 467658#(and (or (not v_assert) (<= (+ 2 d2 temp2) (* 2 W))) (or (not v_assert) (< front2 (+ back2 1))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= back2 front2))), 467674#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (not (< front2 (+ back2 1))) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (= (+ (* (- 1) front1) back1) 0))), 467681#(and (or (not v_assert) (not (< front1 back1)) (not (= (+ (select queue1 front1) 1) (select queue2 (+ back2 1)))) (= back1 (+ front1 1)) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (< front1 back1)) (not (= (+ (select queue1 front1) 1) (select queue2 (+ back2 1)))) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))) (or (not v_assert) (not (< front1 back1)) (not (= (+ (select queue1 front1) 1) (select queue2 (+ back2 1)))) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2))), 467680#(and (or (not v_assert) (not (< front1 back1)) (<= back2 (+ front2 1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (not (= (+ (select queue1 front1) 1) (select queue2 back2))) (not (< front2 back2))) (or (not v_assert) (not (< front1 back1)) (= back1 (+ front1 1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2))) (not (< front2 back2)))), 467659#(and (or (not v_assert) (<= (+ 2 d2 temp2) (* 2 W))) (or (not v_assert) (< front2 (+ back2 1))) (or (not v_assert) (<= back2 front2)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 467643#(and (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= (+ 2 d2) (* 2 W))) (or (not v_assert) (< front2 (+ back2 1))) (or (not v_assert) (<= back2 front2))), 467640#(and (or (<= (+ d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ d2 (select queue2 front2)) (* 2 W)) v_assert)), 467682#(and (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 467668#(and (or (not v_assert) (= (+ (* (- 1) front1) back1) 0) (not (< front2 back2))) (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1)))), 467645#(and (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= (+ 2 d2 temp2) (* 2 W))) (or (not v_assert) (< front2 (+ back2 1))) (or (not v_assert) (<= back2 front2))), 467663#(and (or (<= back1 front1) (not v_assert) (not (< front2 back2)) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (<= back2 (+ front2 1))) (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (< front2 back2))))] [2022-03-15 21:43:29,793 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 76 states [2022-03-15 21:43:29,793 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:43:29,793 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 76 interpolants. [2022-03-15 21:43:29,793 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1287, Invalid=10055, Unknown=0, NotChecked=0, Total=11342 [2022-03-15 21:43:29,794 INFO L87 Difference]: Start difference. First operand 6936 states and 23405 transitions. Second operand has 76 states, 76 states have (on average 4.328947368421052) internal successors, (329), 75 states have internal predecessors, (329), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:44:22,189 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:44:22,189 INFO L93 Difference]: Finished difference Result 51684 states and 173570 transitions. [2022-03-15 21:44:22,190 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 383 states. [2022-03-15 21:44:22,190 INFO L78 Accepts]: Start accepts. Automaton has has 76 states, 76 states have (on average 4.328947368421052) internal successors, (329), 75 states have internal predecessors, (329), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 38 [2022-03-15 21:44:22,190 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:44:22,357 INFO L225 Difference]: With dead ends: 51684 [2022-03-15 21:44:22,358 INFO L226 Difference]: Without dead ends: 49766 [2022-03-15 21:44:22,366 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 775 GetRequests, 226 SyntacticMatches, 70 SemanticMatches, 479 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 92007 ImplicationChecksByTransitivity, 53.7s TimeCoverageRelationStatistics Valid=22158, Invalid=208722, Unknown=0, NotChecked=0, Total=230880 [2022-03-15 21:44:22,366 INFO L933 BasicCegarLoop]: 1 mSDtfsCounter, 2878 mSDsluCounter, 2921 mSDsCounter, 0 mSdLazyCounter, 11137 mSolverCounterSat, 2497 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 5.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2878 SdHoareTripleChecker+Valid, 3 SdHoareTripleChecker+Invalid, 13634 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2497 IncrementalHoareTripleChecker+Valid, 11137 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 6.4s IncrementalHoareTripleChecker+Time [2022-03-15 21:44:22,366 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [2878 Valid, 3 Invalid, 13634 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2497 Valid, 11137 Invalid, 0 Unknown, 0 Unchecked, 6.4s Time] [2022-03-15 21:44:22,426 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49766 states. [2022-03-15 21:44:22,908 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49766 to 8075. [2022-03-15 21:44:22,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8075 states, 8074 states have (on average 3.3506316571711667) internal successors, (27053), 8074 states have internal predecessors, (27053), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:44:22,941 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8075 states to 8075 states and 27053 transitions. [2022-03-15 21:44:22,941 INFO L78 Accepts]: Start accepts. Automaton has 8075 states and 27053 transitions. Word has length 38 [2022-03-15 21:44:22,941 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:44:22,941 INFO L470 AbstractCegarLoop]: Abstraction has 8075 states and 27053 transitions. [2022-03-15 21:44:22,941 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 76 states, 76 states have (on average 4.328947368421052) internal successors, (329), 75 states have internal predecessors, (329), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:44:22,941 INFO L276 IsEmpty]: Start isEmpty. Operand 8075 states and 27053 transitions. [2022-03-15 21:44:22,954 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2022-03-15 21:44:22,954 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:44:22,955 INFO L514 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:44:22,973 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Forceful destruction successful, exit code 0 [2022-03-15 21:44:23,155 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 22 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable24 [2022-03-15 21:44:23,155 INFO L402 AbstractCegarLoop]: === Iteration 26 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION (and 1 more)] === [2022-03-15 21:44:23,156 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:44:23,156 INFO L85 PathProgramCache]: Analyzing trace with hash 1835920741, now seen corresponding path program 22 times [2022-03-15 21:44:23,157 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:44:23,157 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [550304027] [2022-03-15 21:44:23,157 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:44:23,157 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:44:23,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:44:23,506 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 3 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:44:23,507 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:44:23,507 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [550304027] [2022-03-15 21:44:23,507 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [550304027] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:44:23,507 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1060872367] [2022-03-15 21:44:23,507 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-03-15 21:44:23,507 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:44:23,507 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:44:23,508 INFO L229 MonitoredProcess]: Starting monitored process 23 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:44:23,509 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2022-03-15 21:44:23,541 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-03-15 21:44:23,541 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:44:23,542 INFO L263 TraceCheckSpWp]: Trace formula consists of 143 conjuncts, 43 conjunts are in the unsatisfiable core [2022-03-15 21:44:23,543 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:44:24,232 INFO L353 Elim1Store]: treesize reduction 32, result has 3.0 percent of original size [2022-03-15 21:44:24,232 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 49 treesize of output 29 [2022-03-15 21:44:24,431 INFO L353 Elim1Store]: treesize reduction 32, result has 3.0 percent of original size [2022-03-15 21:44:24,431 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 38 treesize of output 18 [2022-03-15 21:44:24,505 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 3 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:44:24,506 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:44:25,000 INFO L353 Elim1Store]: treesize reduction 76, result has 52.8 percent of original size [2022-03-15 21:44:25,001 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 0 disjoint index pairs (out of 15 index pairs), introduced 6 new quantified variables, introduced 15 case distinctions, treesize of input 52 treesize of output 116 [2022-03-15 21:44:25,832 INFO L353 Elim1Store]: treesize reduction 76, result has 52.8 percent of original size [2022-03-15 21:44:25,832 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 0 disjoint index pairs (out of 15 index pairs), introduced 6 new quantified variables, introduced 15 case distinctions, treesize of input 47 treesize of output 111 [2022-03-15 21:44:26,550 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 4 proven. 29 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:44:26,550 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1060872367] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:44:26,550 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:44:26,550 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 48 [2022-03-15 21:44:26,550 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [1974531748] [2022-03-15 21:44:26,551 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:44:26,554 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:44:26,618 INFO L252 McrAutomatonBuilder]: Finished intersection with 293 states and 714 transitions. [2022-03-15 21:44:26,618 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:44:45,814 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 46 new interpolants: [536559#(and (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)))), 536574#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (not v_assert) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1))))), 536565#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (= (+ (* (- 1) front1) back1) 0))), 536587#(and (or (not v_assert) (<= (+ front1 2) back1)) (or (not v_assert) (= front2 back2)) (or (not v_assert) (<= back1 (+ front1 2))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ d2 4 (* 2 w)) (* 2 W))) (or (not v_assert) (= (select queue1 (+ front1 1)) 1))), 536552#(and (or (<= back2 (+ front2 1)) (< 0 w)) (or (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or v_assert (<= (+ front2 1) back2)) (or (<= (+ front2 1) back2) (< 0 w)) (or (<= back2 (+ front2 1)) v_assert) (or (= temp1 1) (< 0 w)) (or (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) v_assert) (or (= temp1 1) v_assert)), 536573#(and (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1)))) (or (<= back1 front1) (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (<= back1 front1) (not v_assert) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1))))), 536582#(and (or (not (< front1 back1)) (= (+ (- 1) (* (- 1) front1) back1) 0)) (or (not (< front1 back1)) (<= front2 back2)) (or (not (< front1 back1)) (<= back2 front2)) (or (not (< front1 back1)) (= (select queue1 front1) 1)) (or (not (< front1 back1)) (<= (+ 2 d2 temp2 (* 2 w)) (* 2 W)))), 536566#(or (not v_assert) (<= (+ d2 temp2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))), 536569#(and (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)))), 536590#(and (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2) (* 2 w)) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 536556#(and (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (not v_assert) (<= back2 (+ front2 1)) (< 0 w)) (or (not v_assert) (= temp1 1) (< 0 w)) (or (not v_assert) (<= (+ front2 1) back2) (< 0 w))), 536581#(and (or (not v_assert) (not (< front1 back1)) (= (+ (- 1) (* (- 1) front1) back1) 0) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (<= front2 back2) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert) (not (< front1 back1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (<= back2 front2) (not (= (+ (select queue1 front1) 1) (select queue2 back2))))), 536567#(and (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)))), 536571#(and (or (not v_assert) (<= back2 (+ front2 1)) (< 0 w)) (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (not v_assert) (= temp1 1) (< 0 w)) (or (not v_assert) (<= (+ front2 1) back2) (< 0 w))), 536547#(and (or (<= d2 (* 2 W)) v_assert) (or (<= d2 (* 2 W)) (< 0 w))), 536554#(or (not v_assert) (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w)), 536549#(and (or (<= (+ d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ d2 (select queue2 front2)) (* 2 W)) v_assert)), 536578#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1)) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (= (+ (* (- 1) front1) back1) 0) (not (< front2 back2)))), 536584#(and (or (not v_assert) (not (< front1 back1)) (<= back2 front2)) (or (not v_assert) (not (< front1 back1)) (<= front2 back2)) (or (not v_assert) (not (< front1 back1)) (<= (+ 2 d2 temp2 (* 2 w)) (* 2 W))) (or (not v_assert) (not (< front1 back1)) (= (select queue1 front1) 1)) (or (not v_assert) (not (< front1 back1)) (= (+ (- 1) (* (- 1) front1) back1) 0))), 536550#(and (or (<= (+ d2 temp2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ d2 temp2 (select queue2 front2)) (* 2 W)) v_assert)), 536572#(and (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W))) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 536555#(and (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)))), 536591#(and (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (= (+ (- 1) (* (- 1) front1) back1) 0)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2) (* 2 w)) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2))), 536588#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (<= back1 (+ front1 1))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ 2 d2 (* 2 w)) (* 2 W))) (or (not v_assert) (<= (+ front1 1) back1))), 536548#(and (or (<= (+ d2 temp2) (* 2 W)) v_assert) (or (<= (+ d2 temp2) (* 2 W)) (< 0 w))), 536576#(and (or (<= back1 front1) (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (<= back1 front1) (not v_assert) (<= back2 (+ front2 1)) (not (= (select queue2 back2) (+ temp1 1)))) (or (<= back1 front1) (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (not (< front2 back2)) (= (select queue1 front1) 1))), 536560#(and (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W))) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 536558#(and (or (<= back1 front1) (not v_assert) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W))) (or (<= back1 front1) (not v_assert) (<= back2 (+ front2 1))) (or (<= back1 front1) (not v_assert) (<= (+ front2 1) back2))), 536568#(and (or (<= back1 front1) (not v_assert) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W))) (or (<= back1 front1) (not v_assert) (<= back2 (+ front2 1))) (or (<= back1 front1) (not v_assert) (<= (+ front2 1) back2))), 536580#(and (or (not v_assert) (not (< front1 back1)) (= (+ (- 1) (* (- 1) front1) back1) 0) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (<= front2 back2) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (<= back2 front2) (not (= (+ (select queue1 front1) 1) (select queue2 back2))))), 536585#(and (or (<= back1 front1) (not v_assert) (not (= (+ (select queue1 front1) 1) (select queue2 (+ back2 1)))) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (not (< front1 back1)) (not (= (+ (select queue1 front1) 1) (select queue2 (+ back2 1)))) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))) (or (not v_assert) (not (< front1 back1)) (not (= (+ (select queue1 front1) 1) (select queue2 (+ back2 1)))) (= (+ (- 1) (* (- 1) front1) back1) 0) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))))), 536586#(and (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 (+ back2 1)) (+ (select queue1 (+ front1 1)) 1))) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (not (< (+ front1 1) back1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (= (select queue2 (+ back2 1)) (+ (select queue1 (+ front1 1)) 1))) (<= back1 (+ front1 1)) (<= back2 front2) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front2 (+ back2 1))) (= (+ (- 2) (* (- 1) front1) back1) 0) (not (= (select queue2 (+ back2 1)) (+ (select queue1 (+ front1 1)) 1))) (not (< (+ front1 1) back1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2))))), 536583#(and (or (not v_assert) (not (< front1 back1)) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (not (= (+ (select queue1 front1) 1) (select queue2 back2))) (not (< front2 back2))) (or (<= back1 front1) (not v_assert) (<= back2 (+ front2 1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (= (+ (- 1) (* (- 1) front1) back1) 0) (not (= (+ (select queue1 front1) 1) (select queue2 back2))) (not (< front2 back2)))), 536562#(and (or (<= back1 front1) (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (<= back1 front1) (not v_assert) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1)))) (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1))))), 536553#(or (not v_assert) (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))), 536561#(and (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 536577#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1)) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (not (< front2 back2)) (= (select queue1 front1) 1))), 536592#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (<= back1 (+ front1 1))) (or (not v_assert) (= temp1 1)) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ front1 1) back1)) (or (not v_assert) (<= (+ d2 4 (* 2 w)) (* 2 W)))), 536589#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (= front1 back1)) (or (not v_assert) (= W w)) (or (not v_assert) (<= d2 0))), 536564#(and (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (= (+ (* (- 1) front1) back1) 0))), 536551#(and (or (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) v_assert)), 536575#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (= (+ (* (- 1) front1) back1) 0)) (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1))))), 536557#(and (or (<= back1 front1) (<= (+ 2 d2 (select queue2 front2)) (* 2 W))) (or (<= back1 front1) (<= (+ front2 1) back2)) (or (<= back1 front1) (<= back2 (+ front2 1))) (or (<= back1 front1) (= (select queue1 front1) 1))), 536579#(and (or (not v_assert) (not (< front1 back1)) (= (+ (- 1) (* (- 1) front1) back1) 0) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (<= front2 back2) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (<= back2 front2) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (< front1 back1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2))))), 536563#(and (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (= (select queue1 front1) 1)) (or (not v_assert) (<= front2 back2) (not (= (select queue2 back2) (+ temp1 1))))), 536570#(or (not v_assert) (<= (+ d2 temp2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w))] [2022-03-15 21:44:45,814 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 66 states [2022-03-15 21:44:45,814 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:44:45,815 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 66 interpolants. [2022-03-15 21:44:45,815 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=673, Invalid=8257, Unknown=0, NotChecked=0, Total=8930 [2022-03-15 21:44:45,815 INFO L87 Difference]: Start difference. First operand 8075 states and 27053 transitions. Second operand has 66 states, 66 states have (on average 4.2727272727272725) internal successors, (282), 65 states have internal predecessors, (282), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:45:55,511 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-03-15 21:45:55,512 INFO L93 Difference]: Finished difference Result 46252 states and 153863 transitions. [2022-03-15 21:45:55,512 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 508 states. [2022-03-15 21:45:55,512 INFO L78 Accepts]: Start accepts. Automaton has has 66 states, 66 states have (on average 4.2727272727272725) internal successors, (282), 65 states have internal predecessors, (282), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 38 [2022-03-15 21:45:55,512 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-03-15 21:45:55,655 INFO L225 Difference]: With dead ends: 46252 [2022-03-15 21:45:55,655 INFO L226 Difference]: Without dead ends: 45657 [2022-03-15 21:45:55,670 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 850 GetRequests, 218 SyntacticMatches, 36 SemanticMatches, 596 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 148902 ImplicationChecksByTransitivity, 67.9s TimeCoverageRelationStatistics Valid=24017, Invalid=332989, Unknown=0, NotChecked=0, Total=357006 [2022-03-15 21:45:55,670 INFO L933 BasicCegarLoop]: 1 mSDtfsCounter, 1969 mSDsluCounter, 3540 mSDsCounter, 0 mSdLazyCounter, 11646 mSolverCounterSat, 1620 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 5.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1969 SdHoareTripleChecker+Valid, 2 SdHoareTripleChecker+Invalid, 13266 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1620 IncrementalHoareTripleChecker+Valid, 11646 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 6.3s IncrementalHoareTripleChecker+Time [2022-03-15 21:45:55,670 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [1969 Valid, 2 Invalid, 13266 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1620 Valid, 11646 Invalid, 0 Unknown, 0 Unchecked, 6.3s Time] [2022-03-15 21:45:55,724 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45657 states. [2022-03-15 21:45:56,162 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45657 to 8195. [2022-03-15 21:45:56,173 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8195 states, 8194 states have (on average 3.348425677324872) internal successors, (27437), 8194 states have internal predecessors, (27437), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:45:56,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8195 states to 8195 states and 27437 transitions. [2022-03-15 21:45:56,196 INFO L78 Accepts]: Start accepts. Automaton has 8195 states and 27437 transitions. Word has length 38 [2022-03-15 21:45:56,196 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-03-15 21:45:56,196 INFO L470 AbstractCegarLoop]: Abstraction has 8195 states and 27437 transitions. [2022-03-15 21:45:56,196 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 66 states, 66 states have (on average 4.2727272727272725) internal successors, (282), 65 states have internal predecessors, (282), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-03-15 21:45:56,196 INFO L276 IsEmpty]: Start isEmpty. Operand 8195 states and 27437 transitions. [2022-03-15 21:45:56,210 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2022-03-15 21:45:56,210 INFO L506 BasicCegarLoop]: Found error trace [2022-03-15 21:45:56,210 INFO L514 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-03-15 21:45:56,227 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Forceful destruction successful, exit code 0 [2022-03-15 21:45:56,417 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 23 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable25 [2022-03-15 21:45:56,417 INFO L402 AbstractCegarLoop]: === Iteration 27 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATION, ULTIMATE.startErr1INUSE_VIOLATION, ULTIMATE.startErr2INUSE_VIOLATION (and 1 more)] === [2022-03-15 21:45:56,418 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-03-15 21:45:56,418 INFO L85 PathProgramCache]: Analyzing trace with hash -124985275, now seen corresponding path program 23 times [2022-03-15 21:45:56,419 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-03-15 21:45:56,419 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [184218962] [2022-03-15 21:45:56,419 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-03-15 21:45:56,419 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-03-15 21:45:56,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-03-15 21:45:56,828 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 3 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:45:56,828 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-03-15 21:45:56,828 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [184218962] [2022-03-15 21:45:56,828 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [184218962] provided 0 perfect and 1 imperfect interpolant sequences [2022-03-15 21:45:56,828 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2073980258] [2022-03-15 21:45:56,828 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-03-15 21:45:56,828 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:45:56,828 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-03-15 21:45:56,829 INFO L229 MonitoredProcess]: Starting monitored process 24 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-03-15 21:45:56,830 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2022-03-15 21:45:56,864 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2022-03-15 21:45:56,864 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-03-15 21:45:56,865 INFO L263 TraceCheckSpWp]: Trace formula consists of 143 conjuncts, 44 conjunts are in the unsatisfiable core [2022-03-15 21:45:56,866 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-03-15 21:45:57,761 INFO L353 Elim1Store]: treesize reduction 32, result has 3.0 percent of original size [2022-03-15 21:45:57,762 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 51 treesize of output 31 [2022-03-15 21:45:57,866 INFO L353 Elim1Store]: treesize reduction 32, result has 3.0 percent of original size [2022-03-15 21:45:57,867 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 38 treesize of output 18 [2022-03-15 21:45:57,941 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 3 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:45:57,942 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-03-15 21:45:58,455 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:58,456 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:58,456 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:58,456 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:58,458 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:58,460 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:58,461 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:58,461 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:58,462 INFO L173 IndexEqualityManager]: detected equality via solver [2022-03-15 21:45:58,480 INFO L353 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-03-15 21:45:58,481 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 9 disjoint index pairs (out of 15 index pairs), introduced 6 new quantified variables, introduced 6 case distinctions, treesize of input 52 treesize of output 96 [2022-03-15 21:45:58,996 INFO L353 Elim1Store]: treesize reduction 76, result has 52.8 percent of original size [2022-03-15 21:45:58,996 INFO L387 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 0 disjoint index pairs (out of 15 index pairs), introduced 6 new quantified variables, introduced 15 case distinctions, treesize of input 47 treesize of output 111 [2022-03-15 21:45:59,804 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 4 proven. 29 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-03-15 21:45:59,804 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2073980258] provided 0 perfect and 2 imperfect interpolant sequences [2022-03-15 21:45:59,804 INFO L191 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-03-15 21:45:59,804 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 50 [2022-03-15 21:45:59,804 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleMcr [393647881] [2022-03-15 21:45:59,804 INFO L194 McrAutomatonBuilder]: Constructing automaton for MCR equivalence class. [2022-03-15 21:45:59,808 INFO L249 McrAutomatonBuilder]: Started intersection. [2022-03-15 21:45:59,889 INFO L252 McrAutomatonBuilder]: Finished intersection with 352 states and 890 transitions. [2022-03-15 21:45:59,889 INFO L276 McrAutomatonBuilder]: Constructing interpolant automaton by labelling MCR automaton with interpolants from WpInterpolantProvider [2022-03-15 21:46:20,678 INFO L301 McrAutomatonBuilder]: Construction finished. MCR generated 51 new interpolants: [600564#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (= front1 back1)) (or (not v_assert) (= W w)) (or (not v_assert) (<= d2 0))), 600555#(and (or (<= (+ d2 (select queue2 front2) (* 2 w)) (* 2 W)) (not v_assert)) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 600552#(and (or (not v_assert) (not (< front1 back1)) (not (= (+ (select queue1 front1) 1) (select queue2 (+ back2 1)))) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))) (or (not v_assert) (not (< front1 back1)) (not (= (+ (select queue1 front1) 1) (select queue2 (+ back2 1)))) (not (= (select queue2 back2) (+ temp1 1))) (<= back2 front2)) (or (not v_assert) (not (< front1 back1)) (not (= (+ (select queue1 front1) 1) (select queue2 (+ back2 1)))) (= (+ (- 1) (* (- 1) front1) back1) 0) (not (< front2 (+ back2 1))) (not (= (select queue2 back2) (+ temp1 1))))), 600537#(and (or (<= back1 front1) (not v_assert) (not (< front2 back2)) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (<= back2 (+ front2 1))) (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (< front2 back2)))), 600527#(and (or (not v_assert) (<= back2 (+ front2 1)) (< 0 w)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (< 0 w) (not (< front2 back2))) (or (not v_assert) (= temp1 1) (< 0 w) (not (< front2 back2)))), 600536#(and (or (<= back1 front1) (not v_assert) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (< front2 (+ back2 1))) (or (<= back1 front1) (not v_assert) (<= back2 front2)) (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 temp2) (* 2 W)))), 600522#(and (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (= temp1 1) (not (< front2 back2)))), 600546#(and (or (not v_assert) (<= (+ 2 d2 temp2) (* 2 W))) (or (not v_assert) (< front2 (+ back2 1))) (or (not v_assert) (<= back2 front2)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 600548#(and (or (not v_assert) (= (+ (* (- 1) front1) back1) 0) (not (< front2 back2))) (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1)))), 600523#(or (<= (+ d2 (select queue2 front2)) (* 2 W)) (not v_assert) (< 0 w)), 600561#(and (or (not v_assert) (not (< front2 (+ back2 1))) (not (= (select queue2 (+ back2 1)) (+ (select queue1 (+ front1 1)) 1))) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (not (< (+ front1 1) back1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front2 (+ back2 1))) (= (+ (- 2) (* (- 1) front1) back1) 0) (not (= (select queue2 (+ back2 1)) (+ (select queue1 (+ front1 1)) 1))) (not (< (+ front1 1) back1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (= (select queue2 (+ back2 1)) (+ (select queue1 (+ front1 1)) 1))) (<= back2 front2) (not (< (+ front1 1) back1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2))))), 600531#(and (or (not v_assert) (<= (+ 2 d2) (* 2 W))) (or (not v_assert) (< front2 (+ back2 1))) (or (not v_assert) (<= back2 front2)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 600549#(and (or (not v_assert) (not (< (+ front2 1) back2)) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 2))) (or (not v_assert) (not (< (+ front2 1) back2)) (= (+ (* (- 1) front1) back1) 0))), 600517#(and (or (<= back2 front2) (< 0 w)) (or (< front2 (+ back2 1)) v_assert) (or v_assert (<= back2 front2)) (or v_assert (<= (+ 2 d2) (* 2 W))) (or (< front2 (+ back2 1)) (< 0 w)) (or (= temp1 1) (< 0 w)) (or (= temp1 1) v_assert) (or (< 0 w) (<= (+ 2 d2) (* 2 W)))), 600521#(and (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= (+ 2 d2 temp2) (* 2 W))) (or (not v_assert) (< front2 (+ back2 1))) (or (not v_assert) (<= back2 front2))), 600530#(and (or (not v_assert) (<= (+ 2 d2) (* 2 W))) (or (not v_assert) (< front2 (+ back2 1))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= back2 front2))), 600514#(and (or (<= d2 (* 2 W)) v_assert) (or (<= d2 (* 2 W)) (< 0 w))), 600516#(and (or (<= (+ d2 (select queue2 front2)) (* 2 W)) (< 0 w)) (or (<= (+ d2 (select queue2 front2)) (* 2 W)) v_assert)), 600550#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1)) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (= (+ (* (- 1) front1) back1) 0) (not (< front2 back2)))), 600515#(and (or (<= (+ d2 temp2) (* 2 W)) v_assert) (or (<= (+ d2 temp2) (* 2 W)) (< 0 w))), 600525#(or (not v_assert) (<= (+ d2 temp2 (select queue2 front2)) (* 2 W)) (< 0 w)), 600538#(and (or (not v_assert) (<= (+ 2 d2 temp2) (* 2 W))) (or (not v_assert) (< front2 (+ back2 1))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= back2 front2))), 600551#(and (or (not v_assert) (not (< front1 back1)) (<= back2 (+ front2 1)) (not (= (+ (select queue1 front1) 1) (select queue2 back2)))) (or (not v_assert) (not (< front1 back1)) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (not (= (+ (select queue1 front1) 1) (select queue2 back2))) (not (< front2 back2))) (or (not v_assert) (not (< front1 back1)) (= (+ (- 1) (* (- 1) front1) back1) 0) (not (= (+ (select queue1 front1) 1) (select queue2 back2))) (not (< front2 back2)))), 600519#(and (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= (+ 2 d2) (* 2 W))) (or (not v_assert) (< front2 (+ back2 1))) (or (not v_assert) (<= back2 front2))), 600524#(and (or (not v_assert) (<= back2 front2) (< 0 w)) (or (not v_assert) (< front2 (+ back2 1)) (< 0 w)) (or (not v_assert) (< 0 w) (<= (+ 2 d2) (* 2 W))) (or (not v_assert) (= temp1 1) (< 0 w))), 600556#(and (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (<= (+ d2 temp2 (select queue2 front2) (* 2 w)) (* 2 W))) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 600539#(and (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (not (< front2 back2)) (= (select queue1 front1) 1))), 600557#(and (or (not v_assert) (<= (+ d2 (select queue2 (+ front2 1)) (select queue2 front2) (* 2 w)) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 2))) (or (not v_assert) (<= (+ front2 2) back2)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 600528#(and (or (<= back1 front1) (< front2 (+ back2 1))) (or (<= back1 front1) (<= (+ 2 d2) (* 2 W))) (or (<= back1 front1) (<= back2 front2)) (or (<= back1 front1) (= (select queue1 front1) 1))), 600526#(and (or (not v_assert) (<= back2 front2) (< 0 w)) (or (not v_assert) (< front2 (+ back2 1)) (< 0 w)) (or (not v_assert) (< 0 w) (<= (+ 2 d2 temp2) (* 2 W))) (or (not v_assert) (= temp1 1) (< 0 w))), 600534#(and (or (not v_assert) (<= back2 (+ front2 1)) (< 0 w)) (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (< 0 w) (not (< front2 back2))) (or (not v_assert) (= temp1 1) (< 0 w) (not (< front2 back2)))), 600560#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (<= back1 (+ front1 1))) (or (not v_assert) (= temp1 1)) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ front1 1) back1)) (or (not v_assert) (<= (+ d2 4 (* 2 w)) (* 2 W)))), 600554#(and (or (not v_assert) (<= (+ d2 temp2 (* 2 w)) (* 2 W))) (or (not v_assert) (< front2 (+ back2 1))) (or (not v_assert) (<= back2 front2)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 600532#(and (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (= temp1 1) (not (< front2 back2)))), 600544#(and (or (<= back1 front1) (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (<= back1 front1) (not v_assert) (<= back2 (+ front2 1)) (not (= (select queue2 back2) (+ temp1 1)))) (or (<= back1 front1) (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (not (< front2 back2)) (= (select queue1 front1) 1))), 600520#(or (not v_assert) (<= (+ d2 temp2 (select queue2 front2)) (* 2 W))), 600562#(and (or (not v_assert) (<= (+ front1 2) back1)) (or (not v_assert) (= front2 back2)) (or (not v_assert) (<= back1 (+ front1 2))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ d2 4 (* 2 w)) (* 2 W))) (or (not v_assert) (= (select queue1 (+ front1 1)) 1))), 600553#(and (or (not v_assert) (< front2 (+ back2 1))) (or (not v_assert) (<= back2 front2)) (or (<= (+ d2 (* 2 w)) (* 2 W)) (not v_assert)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 600533#(and (or (not v_assert) (not (< (+ front2 1) back2)) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 2))) (or (not v_assert) (not (< (+ front2 1) back2)) (= temp1 1))), 600542#(and (or (<= back1 front1) (not v_assert) (not (< (+ front2 1) back2)) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (<= back2 (+ front2 2))) (or (<= back1 front1) (not v_assert) (not (< (+ front2 1) back2)) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)))), 600529#(and (or (<= back1 front1) (not v_assert) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (< front2 (+ back2 1))) (or (<= back1 front1) (not v_assert) (<= (+ 2 d2) (* 2 W))) (or (<= back1 front1) (not v_assert) (<= back2 front2))), 600547#(and (or (not v_assert) (= (+ (* (- 1) front1) back1) 0) (not (< front2 back2))) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1)))), 600535#(and (or (not v_assert) (not (< (+ front2 1) back2)) (= temp1 1) (< 0 w)) (or (not v_assert) (not (< (+ front2 1) back2)) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (< 0 w)) (or (not v_assert) (<= back2 (+ front2 2)) (< 0 w))), 600545#(and (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1)) (not (= (select queue2 back2) (+ temp1 1)))) (or (not v_assert) (not (= (select queue2 back2) (+ temp1 1))) (not (< front2 back2)) (= (select queue1 front1) 1))), 600559#(and (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (= (+ (- 1) (* (- 1) front1) back1) 0)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2) (* 2 w)) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2))), 600543#(and (or (not v_assert) (not (< (+ front2 1) back2)) (<= (+ 2 d2 (select queue2 (+ front2 1)) (select queue2 front2)) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 2))) (or (not v_assert) (not (< (+ front2 1) back2)) (= (select queue1 front1) 1))), 600563#(and (or (not v_assert) (= front2 back2)) (or (not v_assert) (<= back1 (+ front1 1))) (or (not v_assert) (= (select queue1 front1) 1)) (or (not v_assert) (<= (+ 2 d2 (* 2 w)) (* 2 W))) (or (not v_assert) (<= (+ front1 1) back1))), 600541#(and (or (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (not (< front2 back2)) (= (select queue1 front1) 1))), 600518#(or (<= (+ d2 (select queue2 front2)) (* 2 W)) (not v_assert)), 600558#(and (or (not v_assert) (= temp1 1)) (or (not v_assert) (<= (+ 2 d2 (select queue2 front2) (* 2 w)) (* 2 W))) (or (not v_assert) (<= back2 (+ front2 1))) (or (not v_assert) (<= (+ front2 1) back2)) (or (not v_assert) (= (+ (* (- 1) front1) back1) 0))), 600540#(and (or (<= back1 front1) (not v_assert) (<= (+ 2 d2 temp2 (select queue2 front2)) (* 2 W)) (not (< front2 back2))) (or (<= back1 front1) (not v_assert) (not (< front2 back2)) (= (select queue1 front1) 1)) (or (<= back1 front1) (not v_assert) (<= back2 (+ front2 1))))] [2022-03-15 21:46:20,679 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 71 states [2022-03-15 21:46:20,679 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-03-15 21:46:20,679 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 71 interpolants. [2022-03-15 21:46:20,680 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1364, Invalid=8938, Unknown=0, NotChecked=0, Total=10302 [2022-03-15 21:46:20,680 INFO L87 Difference]: Start difference. First operand 8195 states and 27437 transitions. Second operand has 71 states, 71 states have (on average 4.464788732394366) internal successors, (317), 70 states have internal predecessors, (317), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Received shutdown request... [2022-03-15 21:47:04,443 WARN L244 SmtUtils]: Removed 13 from assertion stack [2022-03-15 21:47:04,443 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 339 states. [2022-03-15 21:47:04,451 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 743 GetRequests, 225 SyntacticMatches, 81 SemanticMatches, 436 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 80796 ImplicationChecksByTransitivity, 47.0s TimeCoverageRelationStatistics Valid=22046, Invalid=169360, Unknown=0, NotChecked=0, Total=191406 [2022-03-15 21:47:04,451 INFO L933 BasicCegarLoop]: 0 mSDtfsCounter, 1442 mSDsluCounter, 2171 mSDsCounter, 0 mSdLazyCounter, 7272 mSolverCounterSat, 1171 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 3.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1442 SdHoareTripleChecker+Valid, 0 SdHoareTripleChecker+Invalid, 8443 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1171 IncrementalHoareTripleChecker+Valid, 7272 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 4.0s IncrementalHoareTripleChecker+Time [2022-03-15 21:47:04,451 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [1442 Valid, 0 Invalid, 8443 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1171 Valid, 7272 Invalid, 0 Unknown, 0 Unchecked, 4.0s Time] [2022-03-15 21:47:04,452 INFO L764 garLoopResultBuilder]: Registering result TIMEOUT for location ULTIMATE.startErr0ASSERT_VIOLATIONASSERT (4 of 5 remaining) [2022-03-15 21:47:04,458 WARN L340 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Timeout while monitored process is still running, waiting 1000 ms for graceful end [2022-03-15 21:47:04,458 WARN L340 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Timeout while monitored process is still running, waiting 1000 ms for graceful end [2022-03-15 21:47:04,470 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Forceful destruction successful, exit code 0 [2022-03-15 21:47:04,653 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable26,24 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-03-15 21:47:04,653 WARN L594 AbstractCegarLoop]: Verification canceled: while BasicCegarLoop was constructing difference of abstraction (8195states) and FLOYD_HOARE automaton (currently 339 states, 71 states before enhancement),while PredicateUnifier was unifying predicates,while SimplifyDDAWithTimeout was simplifying term of DAG size 63 for 30ms.. [2022-03-15 21:47:04,654 INFO L764 garLoopResultBuilder]: Registering result TIMEOUT for location ULTIMATE.startErr0INUSE_VIOLATION (3 of 5 remaining) [2022-03-15 21:47:04,654 INFO L764 garLoopResultBuilder]: Registering result TIMEOUT for location ULTIMATE.startErr1INUSE_VIOLATION (2 of 5 remaining) [2022-03-15 21:47:04,654 INFO L764 garLoopResultBuilder]: Registering result TIMEOUT for location ULTIMATE.startErr2INUSE_VIOLATION (1 of 5 remaining) [2022-03-15 21:47:04,654 INFO L764 garLoopResultBuilder]: Registering result TIMEOUT for location ULTIMATE.startErr3INUSE_VIOLATION (0 of 5 remaining) [2022-03-15 21:47:04,656 INFO L732 BasicCegarLoop]: Path program histogram: [23, 2, 1, 1] [2022-03-15 21:47:04,657 INFO L230 ceAbstractionStarter]: Analysis of concurrent program completed with 1 thread instances [2022-03-15 21:47:04,657 INFO L180 ceAbstractionStarter]: Computing trace abstraction results [2022-03-15 21:47:04,658 INFO L202 PluginConnector]: Adding new model prod-cons3.wvr.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 15.03 09:47:04 BasicIcfg [2022-03-15 21:47:04,659 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2022-03-15 21:47:04,659 INFO L158 Benchmark]: Toolchain (without parser) took 733787.25ms. Allocated memory was 172.0MB in the beginning and 910.2MB in the end (delta: 738.2MB). Free memory was 132.7MB in the beginning and 169.9MB in the end (delta: -37.2MB). Peak memory consumption was 703.0MB. Max. memory is 8.0GB. [2022-03-15 21:47:04,659 INFO L158 Benchmark]: Boogie PL CUP Parser took 0.09ms. Allocated memory is still 172.0MB. Free memory is still 133.9MB. There was no memory consumed. Max. memory is 8.0GB. [2022-03-15 21:47:04,659 INFO L158 Benchmark]: Boogie Procedure Inliner took 18.10ms. Allocated memory is still 172.0MB. Free memory was 132.6MB in the beginning and 131.1MB in the end (delta: 1.5MB). Peak memory consumption was 1.0MB. Max. memory is 8.0GB. [2022-03-15 21:47:04,659 INFO L158 Benchmark]: Boogie Preprocessor took 11.78ms. Allocated memory is still 172.0MB. Free memory was 131.1MB in the beginning and 130.0MB in the end (delta: 1.0MB). Peak memory consumption was 1.0MB. Max. memory is 8.0GB. [2022-03-15 21:47:04,659 INFO L158 Benchmark]: RCFGBuilder took 242.75ms. Allocated memory is still 172.0MB. Free memory was 130.0MB in the beginning and 120.1MB in the end (delta: 9.9MB). Peak memory consumption was 9.4MB. Max. memory is 8.0GB. [2022-03-15 21:47:04,659 INFO L158 Benchmark]: TraceAbstraction took 733509.99ms. Allocated memory was 172.0MB in the beginning and 910.2MB in the end (delta: 738.2MB). Free memory was 119.7MB in the beginning and 169.9MB in the end (delta: -50.3MB). Peak memory consumption was 688.3MB. Max. memory is 8.0GB. [2022-03-15 21:47:04,660 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * Boogie PL CUP Parser took 0.09ms. Allocated memory is still 172.0MB. Free memory is still 133.9MB. There was no memory consumed. Max. memory is 8.0GB. * Boogie Procedure Inliner took 18.10ms. Allocated memory is still 172.0MB. Free memory was 132.6MB in the beginning and 131.1MB in the end (delta: 1.5MB). Peak memory consumption was 1.0MB. Max. memory is 8.0GB. * Boogie Preprocessor took 11.78ms. Allocated memory is still 172.0MB. Free memory was 131.1MB in the beginning and 130.0MB in the end (delta: 1.0MB). Peak memory consumption was 1.0MB. Max. memory is 8.0GB. * RCFGBuilder took 242.75ms. Allocated memory is still 172.0MB. Free memory was 130.0MB in the beginning and 120.1MB in the end (delta: 9.9MB). Peak memory consumption was 9.4MB. Max. memory is 8.0GB. * TraceAbstraction took 733509.99ms. Allocated memory was 172.0MB in the beginning and 910.2MB in the end (delta: 738.2MB). Free memory was 119.7MB in the beginning and 169.9MB in the end (delta: -50.3MB). Peak memory consumption was 688.3MB. Max. memory is 8.0GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: PetriNetLargeBlockEncoding benchmarks Lipton Reduction Statistics: ReductionTime: 0.3s, 50 PlacesBefore, 37 PlacesAfterwards, 40 TransitionsBefore, 27 TransitionsAfterwards, 342 CoEnabledTransitionPairs, 3 FixpointIterations, 8 TrivialSequentialCompositions, 6 ConcurrentSequentialCompositions, 0 TrivialYvCompositions, 0 ConcurrentYvCompositions, 0 ChoiceCompositions, 14 TotalNumberOfCompositions, 896 MoverChecksTotal, Independence Relation Statistics: CachedIndependenceRelation.Independence Queries: [ total: 432, positive: 376, positive conditional: 0, positive unconditional: 376, negative: 56, negative conditional: 0, negative unconditional: 56, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , CachedIndependenceRelation.Statistics on underlying relation: SyntacticIndependenceRelation.Independence Queries: [ total: 165, positive: 147, positive conditional: 0, positive unconditional: 147, negative: 18, negative conditional: 0, negative unconditional: 18, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , Cache Queries: [ total: 432, positive: 229, positive conditional: 0, positive unconditional: 229, negative: 38, negative conditional: 0, negative unconditional: 38, unknown: 165, unknown conditional: 0, unknown unconditional: 165] , Statistics on independence cache: Total cache size (in pairs): 63, Positive cache size: 54, Positive conditional cache size: 0, Positive unconditional cache size: 54, Negative cache size: 9, Negative conditional cache size: 0, Negative unconditional cache size: 9 - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - TimeoutResultAtElement [Line: 89]: Timeout (TraceAbstraction) Unable to prove that assertion always holds Cancelled while BasicCegarLoop was constructing difference of abstraction (8195states) and FLOYD_HOARE automaton (currently 339 states, 71 states before enhancement),while PredicateUnifier was unifying predicates,while SimplifyDDAWithTimeout was simplifying term of DAG size 63 for 30ms.. - TimeoutResultAtElement [Line: 80]: Timeout (TraceAbstraction) Unable to prove that petrification did provide enough thread instances (tool internal message, not intended for end users) Cancelled while BasicCegarLoop was constructing difference of abstraction (8195states) and FLOYD_HOARE automaton (currently 339 states, 71 states before enhancement),while PredicateUnifier was unifying predicates,while SimplifyDDAWithTimeout was simplifying term of DAG size 63 for 30ms.. - TimeoutResultAtElement [Line: 80]: Timeout (TraceAbstraction) Unable to prove that petrification did provide enough thread instances (tool internal message, not intended for end users) Cancelled while BasicCegarLoop was constructing difference of abstraction (8195states) and FLOYD_HOARE automaton (currently 339 states, 71 states before enhancement),while PredicateUnifier was unifying predicates,while SimplifyDDAWithTimeout was simplifying term of DAG size 63 for 30ms.. - TimeoutResultAtElement [Line: 81]: Timeout (TraceAbstraction) Unable to prove that petrification did provide enough thread instances (tool internal message, not intended for end users) Cancelled while BasicCegarLoop was constructing difference of abstraction (8195states) and FLOYD_HOARE automaton (currently 339 states, 71 states before enhancement),while PredicateUnifier was unifying predicates,while SimplifyDDAWithTimeout was simplifying term of DAG size 63 for 30ms.. - TimeoutResultAtElement [Line: 82]: Timeout (TraceAbstraction) Unable to prove that petrification did provide enough thread instances (tool internal message, not intended for end users) Cancelled while BasicCegarLoop was constructing difference of abstraction (8195states) and FLOYD_HOARE automaton (currently 339 states, 71 states before enhancement),while PredicateUnifier was unifying predicates,while SimplifyDDAWithTimeout was simplifying term of DAG size 63 for 30ms.. - StatisticsResult: Ultimate Automizer benchmark data with 1 thread instances CFG has 9 procedures, 61 locations, 5 error locations. Started 1 CEGAR loops. OverallTime: 733.4s, OverallIterations: 27, TraceHistogramMax: 3, PathProgramHistogramMax: 23, EmptinessCheckTime: 0.2s, AutomataDifference: 382.1s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.4s, PartialOrderReductionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 25049 SdHoareTripleChecker+Valid, 57.7s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 25049 mSDsluCounter, 130 SdHoareTripleChecker+Invalid, 48.9s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 35323 mSDsCounter, 16562 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 121209 IncrementalHoareTripleChecker+Invalid, 137771 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 16562 mSolverCounterUnsat, 42 mSDtfsCounter, 121209 mSolverCounterSat, 0.4s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 10346 GetRequests, 4811 SyntacticMatches, 821 SemanticMatches, 4713 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 699348 ImplicationChecksByTransitivity, 408.7s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=8195occurred in iteration=26, InterpolantAutomatonStates: 2913, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 4.1s AutomataMinimizationTime, 26 MinimizatonAttempts, 281600 StatesRemovedByMinimization, 22 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.1s SsaConstructionTime, 0.6s SatisfiabilityAnalysisTime, 50.8s InterpolantComputationTime, 1645 NumberOfCodeBlocks, 1645 NumberOfCodeBlocksAsserted, 98 NumberOfCheckSat, 2338 ConstructedInterpolants, 46 QuantifiedInterpolants, 43646 SizeOfPredicates, 260 NumberOfNonLiveVariables, 2989 ConjunctsInSsa, 757 ConjunctsInUnsatCore, 72 InterpolantComputations, 5 PerfectInterpolantSequences, 357/1718 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: Timeout Completed graceful shutdown