/usr/bin/java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/BuchiAutomizerCInline.xml -s ../../../trunk/examples/settings/buchiAutomizer/concurrent-automaton-noLbe.epf -i ../../../trunk/examples/svcomp/pthread-atomic/lamport-b.i -------------------------------------------------------------------------------- This is Ultimate 0.2.2-dev-0d686a6 [2022-07-26 13:22:10,804 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-07-26 13:22:10,806 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-07-26 13:22:10,865 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-07-26 13:22:10,866 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-07-26 13:22:10,867 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-07-26 13:22:10,868 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-07-26 13:22:10,870 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-07-26 13:22:10,871 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-07-26 13:22:10,872 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-07-26 13:22:10,873 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-07-26 13:22:10,874 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... 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[2022-07-26 13:22:10,907 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/buchiAutomizer/concurrent-automaton-noLbe.epf [2022-07-26 13:22:10,931 INFO L113 SettingsManager]: Loading preferences was successful [2022-07-26 13:22:10,932 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-07-26 13:22:10,932 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-07-26 13:22:10,932 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-07-26 13:22:10,933 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-07-26 13:22:10,933 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-07-26 13:22:10,933 INFO L138 SettingsManager]: * Use SBE=true [2022-07-26 13:22:10,933 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-07-26 13:22:10,934 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-07-26 13:22:10,934 INFO L138 SettingsManager]: * Use old map elimination=false [2022-07-26 13:22:10,934 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-07-26 13:22:10,935 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-07-26 13:22:10,935 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-07-26 13:22:10,935 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-07-26 13:22:10,935 INFO L138 SettingsManager]: * sizeof long=4 [2022-07-26 13:22:10,935 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-07-26 13:22:10,935 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-07-26 13:22:10,935 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-07-26 13:22:10,936 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-07-26 13:22:10,936 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-07-26 13:22:10,937 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-07-26 13:22:10,937 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-07-26 13:22:10,937 INFO L138 SettingsManager]: * sizeof long double=12 [2022-07-26 13:22:10,937 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-07-26 13:22:10,937 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-07-26 13:22:10,937 INFO L138 SettingsManager]: * Use constant arrays=true [2022-07-26 13:22:10,937 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-07-26 13:22:10,937 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-07-26 13:22:10,938 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-07-26 13:22:10,938 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-07-26 13:22:10,938 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-07-26 13:22:10,938 INFO L138 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2022-07-26 13:22:10,939 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-07-26 13:22:10,939 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release [2022-07-26 13:22:11,145 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-07-26 13:22:11,162 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-07-26 13:22:11,164 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-07-26 13:22:11,164 INFO L271 PluginConnector]: Initializing CDTParser... [2022-07-26 13:22:11,165 INFO L275 PluginConnector]: CDTParser initialized [2022-07-26 13:22:11,166 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/pthread-atomic/lamport-b.i [2022-07-26 13:22:11,236 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c8bf14f36/eabc0b355860405ba078a701947b29f2/FLAGc1008d5a1 [2022-07-26 13:22:11,650 INFO L306 CDTParser]: Found 1 translation units. [2022-07-26 13:22:11,650 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/pthread-atomic/lamport-b.i [2022-07-26 13:22:11,660 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c8bf14f36/eabc0b355860405ba078a701947b29f2/FLAGc1008d5a1 [2022-07-26 13:22:11,672 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c8bf14f36/eabc0b355860405ba078a701947b29f2 [2022-07-26 13:22:11,674 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-07-26 13:22:11,676 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2022-07-26 13:22:11,679 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-07-26 13:22:11,679 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-07-26 13:22:11,682 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-07-26 13:22:11,683 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.07 01:22:11" (1/1) ... [2022-07-26 13:22:11,683 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6c460e5e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.07 01:22:11, skipping insertion in model container [2022-07-26 13:22:11,684 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.07 01:22:11" (1/1) ... [2022-07-26 13:22:11,689 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-07-26 13:22:11,751 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-07-26 13:22:12,048 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/pthread-atomic/lamport-b.i[30203,30216] [2022-07-26 13:22:12,053 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/pthread-atomic/lamport-b.i[30581,30594] [2022-07-26 13:22:12,061 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-26 13:22:12,071 INFO L203 MainTranslator]: Completed pre-run [2022-07-26 13:22:12,110 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/pthread-atomic/lamport-b.i[30203,30216] [2022-07-26 13:22:12,112 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/pthread-atomic/lamport-b.i[30581,30594] [2022-07-26 13:22:12,117 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-26 13:22:12,144 INFO L208 MainTranslator]: Completed translation [2022-07-26 13:22:12,145 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.07 01:22:12 WrapperNode [2022-07-26 13:22:12,145 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-07-26 13:22:12,146 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-07-26 13:22:12,146 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-07-26 13:22:12,146 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-07-26 13:22:12,156 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.07 01:22:12" (1/1) ... [2022-07-26 13:22:12,170 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.07 01:22:12" (1/1) ... [2022-07-26 13:22:12,190 INFO L137 Inliner]: procedures = 167, calls = 18, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 44 [2022-07-26 13:22:12,190 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-07-26 13:22:12,191 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-07-26 13:22:12,191 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-07-26 13:22:12,191 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-07-26 13:22:12,198 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.07 01:22:12" (1/1) ... [2022-07-26 13:22:12,199 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.07 01:22:12" (1/1) ... [2022-07-26 13:22:12,201 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.07 01:22:12" (1/1) ... [2022-07-26 13:22:12,201 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.07 01:22:12" (1/1) ... [2022-07-26 13:22:12,206 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.07 01:22:12" (1/1) ... [2022-07-26 13:22:12,211 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.07 01:22:12" (1/1) ... [2022-07-26 13:22:12,212 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.07 01:22:12" (1/1) ... [2022-07-26 13:22:12,215 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-07-26 13:22:12,216 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-07-26 13:22:12,216 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-07-26 13:22:12,216 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-07-26 13:22:12,217 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.07 01:22:12" (1/1) ... [2022-07-26 13:22:12,227 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-26 13:22:12,235 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-26 13:22:12,245 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-26 13:22:12,247 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-07-26 13:22:12,274 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-07-26 13:22:12,274 INFO L130 BoogieDeclarations]: Found specification of procedure thr2 [2022-07-26 13:22:12,274 INFO L138 BoogieDeclarations]: Found implementation of procedure thr2 [2022-07-26 13:22:12,275 INFO L130 BoogieDeclarations]: Found specification of procedure thr1 [2022-07-26 13:22:12,275 INFO L138 BoogieDeclarations]: Found implementation of procedure thr1 [2022-07-26 13:22:12,275 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-07-26 13:22:12,275 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-07-26 13:22:12,275 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-07-26 13:22:12,279 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-07-26 13:22:12,279 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-07-26 13:22:12,279 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-07-26 13:22:12,279 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-07-26 13:22:12,281 WARN L208 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2022-07-26 13:22:12,373 INFO L234 CfgBuilder]: Building ICFG [2022-07-26 13:22:12,374 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-07-26 13:22:12,563 INFO L275 CfgBuilder]: Performing block encoding [2022-07-26 13:22:12,569 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-07-26 13:22:12,569 INFO L299 CfgBuilder]: Removed 8 assume(true) statements. [2022-07-26 13:22:12,571 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.07 01:22:12 BoogieIcfgContainer [2022-07-26 13:22:12,571 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-07-26 13:22:12,572 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-07-26 13:22:12,572 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-07-26 13:22:12,578 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-07-26 13:22:12,579 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-26 13:22:12,579 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 26.07 01:22:11" (1/3) ... [2022-07-26 13:22:12,580 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@240fdb2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.07 01:22:12, skipping insertion in model container [2022-07-26 13:22:12,580 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-26 13:22:12,580 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.07 01:22:12" (2/3) ... [2022-07-26 13:22:12,581 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@240fdb2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.07 01:22:12, skipping insertion in model container [2022-07-26 13:22:12,581 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-26 13:22:12,581 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.07 01:22:12" (3/3) ... [2022-07-26 13:22:12,582 INFO L322 chiAutomizerObserver]: Analyzing ICFG lamport-b.i [2022-07-26 13:22:12,644 INFO L144 ThreadInstanceAdder]: Constructed 2 joinOtherThreadTransitions. [2022-07-26 13:22:12,688 INFO L74 FinitePrefix]: Start finitePrefix. Operand has 98 places, 117 transitions, 250 flow [2022-07-26 13:22:12,758 INFO L129 PetriNetUnfolder]: 24/113 cut-off events. [2022-07-26 13:22:12,758 INFO L130 PetriNetUnfolder]: For 2/2 co-relation queries the response was YES. [2022-07-26 13:22:12,763 INFO L84 FinitePrefix]: Finished finitePrefix Result has 122 conditions, 113 events. 24/113 cut-off events. For 2/2 co-relation queries the response was YES. Maximal size of possible extension queue 6. Compared 179 event pairs, 0 based on Foata normal form. 0/89 useless extension candidates. Maximal degree in co-relation 79. Up to 5 conditions per place. [2022-07-26 13:22:12,763 INFO L82 GeneralOperation]: Start removeDead. Operand has 98 places, 117 transitions, 250 flow [2022-07-26 13:22:12,774 INFO L88 GeneralOperation]: Finished RemoveDead, result has has 96 places, 113 transitions, 238 flow [2022-07-26 13:22:12,786 INFO L301 stractBuchiCegarLoop]: Interprodecural is true [2022-07-26 13:22:12,786 INFO L302 stractBuchiCegarLoop]: Hoare is false [2022-07-26 13:22:12,786 INFO L303 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-07-26 13:22:12,787 INFO L304 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-07-26 13:22:12,787 INFO L305 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-07-26 13:22:12,787 INFO L306 stractBuchiCegarLoop]: Difference is false [2022-07-26 13:22:12,787 INFO L307 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-07-26 13:22:12,788 INFO L311 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-07-26 13:22:12,790 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand currently 0 states, but on-demand construction may add more states [2022-07-26 13:22:13,072 INFO L131 ngComponentsAnalysis]: Automaton has 101 accepting balls. 1740 [2022-07-26 13:22:13,073 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-26 13:22:13,073 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-26 13:22:13,080 INFO L150 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-26 13:22:13,080 INFO L151 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1] [2022-07-26 13:22:13,080 INFO L333 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-07-26 13:22:13,080 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand currently 2355 states, but on-demand construction may add more states [2022-07-26 13:22:13,139 INFO L131 ngComponentsAnalysis]: Automaton has 101 accepting balls. 1740 [2022-07-26 13:22:13,139 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-26 13:22:13,139 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-26 13:22:13,140 INFO L150 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-26 13:22:13,140 INFO L151 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1] [2022-07-26 13:22:13,145 INFO L733 eck$LassoCheckResult]: Stem: 101#[ULTIMATE.startENTRY]don't care [296] ULTIMATE.startENTRY-->L-1: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 104#[L-1]don't care [276] L-1-->L-1-1: Formula: (and (= |v_#NULL.base_1| 0) (= |v_#NULL.offset_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] 106#[L-1-1]don't care [304] L-1-1-->L-1-2: Formula: (= (select |v_#valid_8| 0) 0) InVars {#valid=|v_#valid_8|} OutVars{#valid=|v_#valid_8|} AuxVars[] AssignedVars[] 108#[L-1-2]don't care [307] L-1-2-->L12: Formula: (< 0 |v_#StackHeapBarrier_1|) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|} AuxVars[] AssignedVars[] 110#[L12]don't care [246] L12-->L12-1: Formula: (and (= 2 (select |v_#length_4| 1)) (= (select |v_#valid_9| 1) 1)) InVars {#length=|v_#length_4|, #valid=|v_#valid_9|} OutVars{#length=|v_#length_4|, #valid=|v_#valid_9|} AuxVars[] AssignedVars[] 112#[L12-1]don't care [273] L12-1-->L12-2: Formula: (= (select (select |v_#memory_int_5| 1) 0) 48) InVars {#memory_int=|v_#memory_int_5|} OutVars{#memory_int=|v_#memory_int_5|} AuxVars[] AssignedVars[] 114#[L12-2]don't care [271] L12-2-->L12-3: Formula: (= (select (select |v_#memory_int_6| 1) 1) 0) InVars {#memory_int=|v_#memory_int_6|} OutVars{#memory_int=|v_#memory_int_6|} AuxVars[] AssignedVars[] 116#[L12-3]don't care [297] L12-3-->L12-4: Formula: (and (= (select |v_#valid_10| 2) 1) (= (select |v_#length_5| 2) 10)) InVars {#length=|v_#length_5|, #valid=|v_#valid_10|} OutVars{#length=|v_#length_5|, #valid=|v_#valid_10|} AuxVars[] AssignedVars[] 118#[L12-4]don't care [285] L12-4-->L684: Formula: (= v_~x~0_7 0) InVars {} OutVars{~x~0=v_~x~0_7} AuxVars[] AssignedVars[~x~0] 120#[L684]don't care [220] L684-->L685: Formula: (= v_~y~0_21 0) InVars {} OutVars{~y~0=v_~y~0_21} AuxVars[] AssignedVars[~y~0] 122#[L685]don't care [245] L685-->L685-1: Formula: (= v_~b1~0_7 0) InVars {} OutVars{~b1~0=v_~b1~0_7} AuxVars[] AssignedVars[~b1~0] 124#[L685-1]don't care [288] L685-1-->L686: Formula: (= v_~b2~0_7 0) InVars {} OutVars{~b2~0=v_~b2~0_7} AuxVars[] AssignedVars[~b2~0] 126#[L686]don't care [321] L686-->L-1-3: Formula: (= v_~X~0_7 0) InVars {} OutVars{~X~0=v_~X~0_7} AuxVars[] AssignedVars[~X~0] 128#[L-1-3]don't care [312] L-1-3-->L-1-4: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 130#[L-1-4]don't care [284] L-1-4-->L-1-5: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 132#[L-1-5]don't care [244] L-1-5-->L-1-6: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res#1=|v_ULTIMATE.start_main_#res#1_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res#1] 134#[L-1-6]don't care [282] L-1-6-->L740: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_4|, ULTIMATE.start_main_#t~nondet4#1=|v_ULTIMATE.start_main_#t~nondet4#1_2|, ULTIMATE.start_main_#t~mem7#1=|v_ULTIMATE.start_main_#t~mem7#1_3|, ULTIMATE.start_main_#t~mem8#1=|v_ULTIMATE.start_main_#t~mem8#1_3|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_5|, ULTIMATE.start_main_#t~nondet6#1=|v_ULTIMATE.start_main_#t~nondet6#1_2|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_4|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_4|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_2|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_5|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre5#1, ULTIMATE.start_main_#t~nondet4#1, ULTIMATE.start_main_#t~mem7#1, ULTIMATE.start_main_#t~mem8#1, ULTIMATE.start_main_~#t2~0#1.offset, ULTIMATE.start_main_#t~nondet6#1, ULTIMATE.start_main_~#t1~0#1.base, ULTIMATE.start_main_~#t1~0#1.offset, ULTIMATE.start_main_#t~pre3#1, ULTIMATE.start_main_~#t2~0#1.base] 136#[L740]don't care [286] L740-->L740-1: Formula: (and (= (select |v_#valid_12| |v_ULTIMATE.start_main_~#t1~0#1.base_5|) 0) (< |v_#StackHeapBarrier_2| |v_ULTIMATE.start_main_~#t1~0#1.base_5|) (= (store |v_#valid_12| |v_ULTIMATE.start_main_~#t1~0#1.base_5| 1) |v_#valid_11|) (not (= |v_ULTIMATE.start_main_~#t1~0#1.base_5| 0)) (= |v_#length_6| (store |v_#length_7| |v_ULTIMATE.start_main_~#t1~0#1.base_5| 4)) (= |v_ULTIMATE.start_main_~#t1~0#1.offset_5| 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_7|, #valid=|v_#valid_12|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_6|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_5|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_5|, #valid=|v_#valid_11|} AuxVars[] AssignedVars[#valid, #length, ULTIMATE.start_main_~#t1~0#1.base, ULTIMATE.start_main_~#t1~0#1.offset] 138#[L740-1]don't care [293] L740-1-->L740-2: Formula: (and (= |v_#valid_13| (store |v_#valid_14| |v_ULTIMATE.start_main_~#t2~0#1.base_6| 1)) (not (= |v_ULTIMATE.start_main_~#t2~0#1.base_6| 0)) (= |v_#length_8| (store |v_#length_9| |v_ULTIMATE.start_main_~#t2~0#1.base_6| 4)) (< |v_#StackHeapBarrier_3| |v_ULTIMATE.start_main_~#t2~0#1.base_6|) (= (select |v_#valid_14| |v_ULTIMATE.start_main_~#t2~0#1.base_6|) 0) (= 0 |v_ULTIMATE.start_main_~#t2~0#1.offset_6|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_3|, #length=|v_#length_9|, #valid=|v_#valid_14|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_3|, #length=|v_#length_8|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_6|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_6|, #valid=|v_#valid_13|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2~0#1.offset, #valid, #length, ULTIMATE.start_main_~#t2~0#1.base] 140#[L740-2]don't care [263] L740-2-->L741: Formula: (= |v_ULTIMATE.start_main_#t~pre3#1_3| |v_#pthreadsForks_4|) InVars {#pthreadsForks=|v_#pthreadsForks_4|} OutVars{#pthreadsForks=|v_#pthreadsForks_4|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre3#1] 142#[L741]don't care [298] L741-->L741-1: Formula: (= (+ 1 |v_#pthreadsForks_6|) |v_#pthreadsForks_5|) InVars {#pthreadsForks=|v_#pthreadsForks_6|} OutVars{#pthreadsForks=|v_#pthreadsForks_5|} AuxVars[] AssignedVars[#pthreadsForks] 144#[L741-1]don't care [294] L741-1-->L741-2: Formula: (and (<= 0 |v_ULTIMATE.start_main_~#t1~0#1.offset_6|) (<= (+ |v_ULTIMATE.start_main_~#t1~0#1.offset_6| 4) (select |v_#length_10| |v_ULTIMATE.start_main_~#t1~0#1.base_6|)) (= (store |v_#memory_int_8| |v_ULTIMATE.start_main_~#t1~0#1.base_6| (store (select |v_#memory_int_8| |v_ULTIMATE.start_main_~#t1~0#1.base_6|) |v_ULTIMATE.start_main_~#t1~0#1.offset_6| |v_ULTIMATE.start_main_#t~pre3#1_4|)) |v_#memory_int_7|) (= (select |v_#valid_15| |v_ULTIMATE.start_main_~#t1~0#1.base_6|) 1)) InVars {#valid=|v_#valid_15|, #memory_int=|v_#memory_int_8|, #length=|v_#length_10|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_6|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_6|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_4|} OutVars{#valid=|v_#valid_15|, #memory_int=|v_#memory_int_7|, #length=|v_#length_10|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_6|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_6|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_4|} AuxVars[] AssignedVars[#memory_int] 146#[L741-2]don't care [401] L741-2-->thr1ENTRY: Formula: (and (= v_thr1Thread1of1ForFork1_thidvar1_2 0) (= |v_ULTIMATE.start_main_#t~pre3#1_6| v_thr1Thread1of1ForFork1_thidvar0_2) (= |v_thr1Thread1of1ForFork1_#in~_.base_4| 0) (= |v_thr1Thread1of1ForFork1_#in~_.offset_4| 0)) InVars {ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_6|} OutVars{thr1Thread1of1ForFork1_#in~_.offset=|v_thr1Thread1of1ForFork1_#in~_.offset_4|, thr1Thread1of1ForFork1_~_.base=v_thr1Thread1of1ForFork1_~_.base_4, thr1Thread1of1ForFork1_#res.base=|v_thr1Thread1of1ForFork1_#res.base_4|, thr1Thread1of1ForFork1_#in~_.base=|v_thr1Thread1of1ForFork1_#in~_.base_4|, thr1Thread1of1ForFork1_~_.offset=v_thr1Thread1of1ForFork1_~_.offset_4, thr1Thread1of1ForFork1_#res.offset=|v_thr1Thread1of1ForFork1_#res.offset_4|, thr1Thread1of1ForFork1_thidvar1=v_thr1Thread1of1ForFork1_thidvar1_2, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_6|, thr1Thread1of1ForFork1_thidvar0=v_thr1Thread1of1ForFork1_thidvar0_2} AuxVars[] AssignedVars[thr1Thread1of1ForFork1_#in~_.offset, thr1Thread1of1ForFork1_~_.base, thr1Thread1of1ForFork1_#res.base, thr1Thread1of1ForFork1_#in~_.base, thr1Thread1of1ForFork1_~_.offset, thr1Thread1of1ForFork1_#res.offset, thr1Thread1of1ForFork1_thidvar1, thr1Thread1of1ForFork1_thidvar0] 148#[L741-3, thr1ENTRY]don't care [362] thr1ENTRY-->L688loopEntry: Formula: (and (= v_thr1Thread1of1ForFork1_~_.base_1 |v_thr1Thread1of1ForFork1_#in~_.base_1|) (= |v_thr1Thread1of1ForFork1_#in~_.offset_1| v_thr1Thread1of1ForFork1_~_.offset_1)) InVars {thr1Thread1of1ForFork1_#in~_.offset=|v_thr1Thread1of1ForFork1_#in~_.offset_1|, thr1Thread1of1ForFork1_#in~_.base=|v_thr1Thread1of1ForFork1_#in~_.base_1|} OutVars{thr1Thread1of1ForFork1_#in~_.offset=|v_thr1Thread1of1ForFork1_#in~_.offset_1|, thr1Thread1of1ForFork1_#in~_.base=|v_thr1Thread1of1ForFork1_#in~_.base_1|, thr1Thread1of1ForFork1_~_.offset=v_thr1Thread1of1ForFork1_~_.offset_1, thr1Thread1of1ForFork1_~_.base=v_thr1Thread1of1ForFork1_~_.base_1} AuxVars[] AssignedVars[thr1Thread1of1ForFork1_~_.base, thr1Thread1of1ForFork1_~_.offset] 150#[L741-3, L688loopEntry]don't care [363] L688loopEntry-->L701-3: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 156#[L701-3, L741-3]don't care [2022-07-26 13:22:13,146 INFO L735 eck$LassoCheckResult]: Loop: 156#[L701-3, L741-3]don't care [366] L701-3-->L689: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 168#[L741-3, L689]don't care [368] L689-->L690: Formula: (= v_~b1~0_3 1) InVars {} OutVars{~b1~0=v_~b1~0_3} AuxVars[] AssignedVars[~b1~0] 184#[L690, L741-3]don't care [371] L690-->L691: Formula: (= v_~x~0_5 1) InVars {} OutVars{~x~0=v_~x~0_5} AuxVars[] AssignedVars[~x~0] 208#[L691, L741-3]don't care [374] L691-->L692: Formula: (not (= v_~y~0_15 0)) InVars {~y~0=v_~y~0_15} OutVars{~y~0=v_~y~0_15} AuxVars[] AssignedVars[] 238#[L692, L741-3]don't care [378] L692-->L693-2: Formula: (= v_~b1~0_4 0) InVars {} OutVars{~b1~0=v_~b1~0_4} AuxVars[] AssignedVars[~b1~0] 274#[L693-2, L741-3]don't care [381] L693-2-->L701-3: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] 156#[L701-3, L741-3]don't care [2022-07-26 13:22:13,150 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:13,151 INFO L85 PathProgramCache]: Analyzing trace with hash -813792526, now seen corresponding path program 1 times [2022-07-26 13:22:13,158 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:13,158 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1698396247] [2022-07-26 13:22:13,159 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:13,159 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:13,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:13,270 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-26 13:22:13,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:13,309 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-26 13:22:13,312 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:13,312 INFO L85 PathProgramCache]: Analyzing trace with hash -1167849239, now seen corresponding path program 1 times [2022-07-26 13:22:13,312 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:13,313 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [299348037] [2022-07-26 13:22:13,313 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:13,313 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:13,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-26 13:22:13,372 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-26 13:22:13,372 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-26 13:22:13,372 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [299348037] [2022-07-26 13:22:13,373 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [299348037] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-26 13:22:13,373 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-26 13:22:13,373 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2022-07-26 13:22:13,373 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [959517531] [2022-07-26 13:22:13,374 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-26 13:22:13,379 INFO L750 eck$LassoCheckResult]: loop already infeasible [2022-07-26 13:22:13,380 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-26 13:22:13,405 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-07-26 13:22:13,406 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-07-26 13:22:13,408 INFO L87 Difference]: Start difference. First operand currently 2355 states, but on-demand construction may add more states Second operand has 2 states, 1 states have (on average 6.0) internal successors, (6), 2 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-26 13:22:13,466 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-26 13:22:13,466 INFO L93 Difference]: Finished difference Result 2167 states and 6678 transitions. [2022-07-26 13:22:13,467 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2167 states and 6678 transitions. [2022-07-26 13:22:13,494 INFO L131 ngComponentsAnalysis]: Automaton has 93 accepting balls. 1644 [2022-07-26 13:22:13,526 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2167 states to 1877 states and 5849 transitions. [2022-07-26 13:22:13,528 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1877 [2022-07-26 13:22:13,532 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1877 [2022-07-26 13:22:13,533 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1877 states and 5849 transitions. [2022-07-26 13:22:13,544 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-26 13:22:13,545 INFO L220 hiAutomatonCegarLoop]: Abstraction has 1877 states and 5849 transitions. [2022-07-26 13:22:13,572 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1877 states and 5849 transitions. [2022-07-26 13:22:13,680 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1877 to 1877. [2022-07-26 13:22:13,690 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1877 states, 1877 states have (on average 3.116142781033564) internal successors, (5849), 1876 states have internal predecessors, (5849), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-26 13:22:13,705 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1877 states to 1877 states and 5849 transitions. [2022-07-26 13:22:13,706 INFO L242 hiAutomatonCegarLoop]: Abstraction has 1877 states and 5849 transitions. [2022-07-26 13:22:13,708 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-07-26 13:22:13,714 INFO L426 stractBuchiCegarLoop]: Abstraction has 1877 states and 5849 transitions. [2022-07-26 13:22:13,715 INFO L333 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-07-26 13:22:13,715 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1877 states and 5849 transitions. [2022-07-26 13:22:13,731 INFO L131 ngComponentsAnalysis]: Automaton has 93 accepting balls. 1644 [2022-07-26 13:22:13,731 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-26 13:22:13,731 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-26 13:22:13,732 INFO L150 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-26 13:22:13,733 INFO L151 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1] [2022-07-26 13:22:13,736 INFO L733 eck$LassoCheckResult]: Stem: 9346#[ULTIMATE.startENTRY]don't care [296] ULTIMATE.startENTRY-->L-1: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 9348#[L-1]don't care [276] L-1-->L-1-1: Formula: (and (= |v_#NULL.base_1| 0) (= |v_#NULL.offset_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] 9358#[L-1-1]don't care [304] L-1-1-->L-1-2: Formula: (= (select |v_#valid_8| 0) 0) InVars {#valid=|v_#valid_8|} OutVars{#valid=|v_#valid_8|} AuxVars[] AssignedVars[] 9360#[L-1-2]don't care [307] L-1-2-->L12: Formula: (< 0 |v_#StackHeapBarrier_1|) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|} AuxVars[] AssignedVars[] 10454#[L12]don't care [246] L12-->L12-1: Formula: (and (= 2 (select |v_#length_4| 1)) (= (select |v_#valid_9| 1) 1)) InVars {#length=|v_#length_4|, #valid=|v_#valid_9|} OutVars{#length=|v_#length_4|, #valid=|v_#valid_9|} AuxVars[] AssignedVars[] 10670#[L12-1]don't care [273] L12-1-->L12-2: Formula: (= (select (select |v_#memory_int_5| 1) 0) 48) InVars {#memory_int=|v_#memory_int_5|} OutVars{#memory_int=|v_#memory_int_5|} AuxVars[] AssignedVars[] 9676#[L12-2]don't care [271] L12-2-->L12-3: Formula: (= (select (select |v_#memory_int_6| 1) 1) 0) InVars {#memory_int=|v_#memory_int_6|} OutVars{#memory_int=|v_#memory_int_6|} AuxVars[] AssignedVars[] 9678#[L12-3]don't care [297] L12-3-->L12-4: Formula: (and (= (select |v_#valid_10| 2) 1) (= (select |v_#length_5| 2) 10)) InVars {#length=|v_#length_5|, #valid=|v_#valid_10|} OutVars{#length=|v_#length_5|, #valid=|v_#valid_10|} AuxVars[] AssignedVars[] 8932#[L12-4]don't care [285] L12-4-->L684: Formula: (= v_~x~0_7 0) InVars {} OutVars{~x~0=v_~x~0_7} AuxVars[] AssignedVars[~x~0] 8934#[L684]don't care [220] L684-->L685: Formula: (= v_~y~0_21 0) InVars {} OutVars{~y~0=v_~y~0_21} AuxVars[] AssignedVars[~y~0] 10322#[L685]don't care [245] L685-->L685-1: Formula: (= v_~b1~0_7 0) InVars {} OutVars{~b1~0=v_~b1~0_7} AuxVars[] AssignedVars[~b1~0] 10270#[L685-1]don't care [288] L685-1-->L686: Formula: (= v_~b2~0_7 0) InVars {} OutVars{~b2~0=v_~b2~0_7} AuxVars[] AssignedVars[~b2~0] 10272#[L686]don't care [321] L686-->L-1-3: Formula: (= v_~X~0_7 0) InVars {} OutVars{~X~0=v_~X~0_7} AuxVars[] AssignedVars[~X~0] 10034#[L-1-3]don't care [312] L-1-3-->L-1-4: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 7354#[L-1-4]don't care [284] L-1-4-->L-1-5: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 7356#[L-1-5]don't care [244] L-1-5-->L-1-6: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res#1=|v_ULTIMATE.start_main_#res#1_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res#1] 8412#[L-1-6]don't care [282] L-1-6-->L740: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_4|, ULTIMATE.start_main_#t~nondet4#1=|v_ULTIMATE.start_main_#t~nondet4#1_2|, ULTIMATE.start_main_#t~mem7#1=|v_ULTIMATE.start_main_#t~mem7#1_3|, ULTIMATE.start_main_#t~mem8#1=|v_ULTIMATE.start_main_#t~mem8#1_3|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_5|, ULTIMATE.start_main_#t~nondet6#1=|v_ULTIMATE.start_main_#t~nondet6#1_2|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_4|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_4|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_2|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_5|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre5#1, ULTIMATE.start_main_#t~nondet4#1, ULTIMATE.start_main_#t~mem7#1, ULTIMATE.start_main_#t~mem8#1, ULTIMATE.start_main_~#t2~0#1.offset, ULTIMATE.start_main_#t~nondet6#1, ULTIMATE.start_main_~#t1~0#1.base, ULTIMATE.start_main_~#t1~0#1.offset, ULTIMATE.start_main_#t~pre3#1, ULTIMATE.start_main_~#t2~0#1.base] 8414#[L740]don't care [286] L740-->L740-1: Formula: (and (= (select |v_#valid_12| |v_ULTIMATE.start_main_~#t1~0#1.base_5|) 0) (< |v_#StackHeapBarrier_2| |v_ULTIMATE.start_main_~#t1~0#1.base_5|) (= (store |v_#valid_12| |v_ULTIMATE.start_main_~#t1~0#1.base_5| 1) |v_#valid_11|) (not (= |v_ULTIMATE.start_main_~#t1~0#1.base_5| 0)) (= |v_#length_6| (store |v_#length_7| |v_ULTIMATE.start_main_~#t1~0#1.base_5| 4)) (= |v_ULTIMATE.start_main_~#t1~0#1.offset_5| 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_7|, #valid=|v_#valid_12|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_6|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_5|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_5|, #valid=|v_#valid_11|} AuxVars[] AssignedVars[#valid, #length, ULTIMATE.start_main_~#t1~0#1.base, ULTIMATE.start_main_~#t1~0#1.offset] 9728#[L740-1]don't care [293] L740-1-->L740-2: Formula: (and (= |v_#valid_13| (store |v_#valid_14| |v_ULTIMATE.start_main_~#t2~0#1.base_6| 1)) (not (= |v_ULTIMATE.start_main_~#t2~0#1.base_6| 0)) (= |v_#length_8| (store |v_#length_9| |v_ULTIMATE.start_main_~#t2~0#1.base_6| 4)) (< |v_#StackHeapBarrier_3| |v_ULTIMATE.start_main_~#t2~0#1.base_6|) (= (select |v_#valid_14| |v_ULTIMATE.start_main_~#t2~0#1.base_6|) 0) (= 0 |v_ULTIMATE.start_main_~#t2~0#1.offset_6|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_3|, #length=|v_#length_9|, #valid=|v_#valid_14|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_3|, #length=|v_#length_8|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_6|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_6|, #valid=|v_#valid_13|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2~0#1.offset, #valid, #length, ULTIMATE.start_main_~#t2~0#1.base] 9730#[L740-2]don't care [263] L740-2-->L741: Formula: (= |v_ULTIMATE.start_main_#t~pre3#1_3| |v_#pthreadsForks_4|) InVars {#pthreadsForks=|v_#pthreadsForks_4|} OutVars{#pthreadsForks=|v_#pthreadsForks_4|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre3#1] 7770#[L741]don't care [298] L741-->L741-1: Formula: (= (+ 1 |v_#pthreadsForks_6|) |v_#pthreadsForks_5|) InVars {#pthreadsForks=|v_#pthreadsForks_6|} OutVars{#pthreadsForks=|v_#pthreadsForks_5|} AuxVars[] AssignedVars[#pthreadsForks] 7772#[L741-1]don't care [294] L741-1-->L741-2: Formula: (and (<= 0 |v_ULTIMATE.start_main_~#t1~0#1.offset_6|) (<= (+ |v_ULTIMATE.start_main_~#t1~0#1.offset_6| 4) (select |v_#length_10| |v_ULTIMATE.start_main_~#t1~0#1.base_6|)) (= (store |v_#memory_int_8| |v_ULTIMATE.start_main_~#t1~0#1.base_6| (store (select |v_#memory_int_8| |v_ULTIMATE.start_main_~#t1~0#1.base_6|) |v_ULTIMATE.start_main_~#t1~0#1.offset_6| |v_ULTIMATE.start_main_#t~pre3#1_4|)) |v_#memory_int_7|) (= (select |v_#valid_15| |v_ULTIMATE.start_main_~#t1~0#1.base_6|) 1)) InVars {#valid=|v_#valid_15|, #memory_int=|v_#memory_int_8|, #length=|v_#length_10|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_6|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_6|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_4|} OutVars{#valid=|v_#valid_15|, #memory_int=|v_#memory_int_7|, #length=|v_#length_10|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_6|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_6|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_4|} AuxVars[] AssignedVars[#memory_int] 10706#[L741-2]don't care [401] L741-2-->thr1ENTRY: Formula: (and (= v_thr1Thread1of1ForFork1_thidvar1_2 0) (= |v_ULTIMATE.start_main_#t~pre3#1_6| v_thr1Thread1of1ForFork1_thidvar0_2) (= |v_thr1Thread1of1ForFork1_#in~_.base_4| 0) (= |v_thr1Thread1of1ForFork1_#in~_.offset_4| 0)) InVars {ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_6|} OutVars{thr1Thread1of1ForFork1_#in~_.offset=|v_thr1Thread1of1ForFork1_#in~_.offset_4|, thr1Thread1of1ForFork1_~_.base=v_thr1Thread1of1ForFork1_~_.base_4, thr1Thread1of1ForFork1_#res.base=|v_thr1Thread1of1ForFork1_#res.base_4|, thr1Thread1of1ForFork1_#in~_.base=|v_thr1Thread1of1ForFork1_#in~_.base_4|, thr1Thread1of1ForFork1_~_.offset=v_thr1Thread1of1ForFork1_~_.offset_4, thr1Thread1of1ForFork1_#res.offset=|v_thr1Thread1of1ForFork1_#res.offset_4|, thr1Thread1of1ForFork1_thidvar1=v_thr1Thread1of1ForFork1_thidvar1_2, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_6|, thr1Thread1of1ForFork1_thidvar0=v_thr1Thread1of1ForFork1_thidvar0_2} AuxVars[] AssignedVars[thr1Thread1of1ForFork1_#in~_.offset, thr1Thread1of1ForFork1_~_.base, thr1Thread1of1ForFork1_#res.base, thr1Thread1of1ForFork1_#in~_.base, thr1Thread1of1ForFork1_~_.offset, thr1Thread1of1ForFork1_#res.offset, thr1Thread1of1ForFork1_thidvar1, thr1Thread1of1ForFork1_thidvar0] 9454#[L741-3, thr1ENTRY]don't care [362] thr1ENTRY-->L688loopEntry: Formula: (and (= v_thr1Thread1of1ForFork1_~_.base_1 |v_thr1Thread1of1ForFork1_#in~_.base_1|) (= |v_thr1Thread1of1ForFork1_#in~_.offset_1| v_thr1Thread1of1ForFork1_~_.offset_1)) InVars {thr1Thread1of1ForFork1_#in~_.offset=|v_thr1Thread1of1ForFork1_#in~_.offset_1|, thr1Thread1of1ForFork1_#in~_.base=|v_thr1Thread1of1ForFork1_#in~_.base_1|} OutVars{thr1Thread1of1ForFork1_#in~_.offset=|v_thr1Thread1of1ForFork1_#in~_.offset_1|, thr1Thread1of1ForFork1_#in~_.base=|v_thr1Thread1of1ForFork1_#in~_.base_1|, thr1Thread1of1ForFork1_~_.offset=v_thr1Thread1of1ForFork1_~_.offset_1, thr1Thread1of1ForFork1_~_.base=v_thr1Thread1of1ForFork1_~_.base_1} AuxVars[] AssignedVars[thr1Thread1of1ForFork1_~_.base, thr1Thread1of1ForFork1_~_.offset] 9456#[L741-3, L688loopEntry]don't care [363] L688loopEntry-->L701-3: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 10336#[L701-3, L741-3]don't care [2022-07-26 13:22:13,737 INFO L735 eck$LassoCheckResult]: Loop: 10336#[L701-3, L741-3]don't care [366] L701-3-->L689: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 10734#[L741-3, L689]don't care [368] L689-->L690: Formula: (= v_~b1~0_3 1) InVars {} OutVars{~b1~0=v_~b1~0_3} AuxVars[] AssignedVars[~b1~0] 9012#[L690, L741-3]don't care [371] L690-->L691: Formula: (= v_~x~0_5 1) InVars {} OutVars{~x~0=v_~x~0_5} AuxVars[] AssignedVars[~x~0] 9014#[L691, L741-3]don't care [374] L691-->L692: Formula: (not (= v_~y~0_15 0)) InVars {~y~0=v_~y~0_15} OutVars{~y~0=v_~y~0_15} AuxVars[] AssignedVars[] 10566#[L692, L741-3]don't care [378] L692-->L693-2: Formula: (= v_~b1~0_4 0) InVars {} OutVars{~b1~0=v_~b1~0_4} AuxVars[] AssignedVars[~b1~0] 10396#[L693-2, L741-3]don't care [382] L693-2-->L701-3: Formula: (= v_~y~0_17 0) InVars {~y~0=v_~y~0_17} OutVars{~y~0=v_~y~0_17} AuxVars[] AssignedVars[] 10336#[L701-3, L741-3]don't care [2022-07-26 13:22:13,739 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:13,739 INFO L85 PathProgramCache]: Analyzing trace with hash -813792526, now seen corresponding path program 2 times [2022-07-26 13:22:13,740 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:13,740 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2056666294] [2022-07-26 13:22:13,742 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:13,747 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:13,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:13,797 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-26 13:22:13,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:13,833 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-26 13:22:13,834 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:13,834 INFO L85 PathProgramCache]: Analyzing trace with hash -1167849238, now seen corresponding path program 1 times [2022-07-26 13:22:13,834 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:13,834 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [605026093] [2022-07-26 13:22:13,834 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:13,835 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:13,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-26 13:22:13,865 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-26 13:22:13,865 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-26 13:22:13,865 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [605026093] [2022-07-26 13:22:13,866 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [605026093] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-26 13:22:13,866 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-26 13:22:13,866 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-26 13:22:13,866 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1124777405] [2022-07-26 13:22:13,866 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-26 13:22:13,866 INFO L750 eck$LassoCheckResult]: loop already infeasible [2022-07-26 13:22:13,867 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-26 13:22:13,867 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-26 13:22:13,867 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-26 13:22:13,867 INFO L87 Difference]: Start difference. First operand 1877 states and 5849 transitions. cyclomatic complexity: 4065 Second operand has 3 states, 2 states have (on average 3.0) internal successors, (6), 3 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-26 13:22:13,967 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-26 13:22:13,967 INFO L93 Difference]: Finished difference Result 2122 states and 6098 transitions. [2022-07-26 13:22:13,967 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2122 states and 6098 transitions. [2022-07-26 13:22:13,991 INFO L131 ngComponentsAnalysis]: Automaton has 554 accepting balls. 554 [2022-07-26 13:22:14,014 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2122 states to 2122 states and 6098 transitions. [2022-07-26 13:22:14,015 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2122 [2022-07-26 13:22:14,018 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2122 [2022-07-26 13:22:14,019 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2122 states and 6098 transitions. [2022-07-26 13:22:14,025 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-26 13:22:14,025 INFO L220 hiAutomatonCegarLoop]: Abstraction has 2122 states and 6098 transitions. [2022-07-26 13:22:14,033 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2122 states and 6098 transitions. [2022-07-26 13:22:14,112 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2122 to 2122. [2022-07-26 13:22:14,118 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2122 states, 2122 states have (on average 2.8737040527803956) internal successors, (6098), 2121 states have internal predecessors, (6098), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-26 13:22:14,127 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2122 states to 2122 states and 6098 transitions. [2022-07-26 13:22:14,128 INFO L242 hiAutomatonCegarLoop]: Abstraction has 2122 states and 6098 transitions. [2022-07-26 13:22:14,129 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-26 13:22:14,130 INFO L426 stractBuchiCegarLoop]: Abstraction has 2122 states and 6098 transitions. [2022-07-26 13:22:14,130 INFO L333 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-07-26 13:22:14,130 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2122 states and 6098 transitions. [2022-07-26 13:22:14,146 INFO L131 ngComponentsAnalysis]: Automaton has 554 accepting balls. 554 [2022-07-26 13:22:14,146 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-26 13:22:14,146 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-26 13:22:14,147 INFO L150 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-26 13:22:14,147 INFO L151 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-07-26 13:22:14,150 INFO L733 eck$LassoCheckResult]: Stem: 15166#[ULTIMATE.startENTRY]don't care [296] ULTIMATE.startENTRY-->L-1: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 15168#[L-1]don't care [276] L-1-->L-1-1: Formula: (and (= |v_#NULL.base_1| 0) (= |v_#NULL.offset_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] 15178#[L-1-1]don't care [304] L-1-1-->L-1-2: Formula: (= (select |v_#valid_8| 0) 0) InVars {#valid=|v_#valid_8|} OutVars{#valid=|v_#valid_8|} AuxVars[] AssignedVars[] 15180#[L-1-2]don't care [307] L-1-2-->L12: Formula: (< 0 |v_#StackHeapBarrier_1|) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|} AuxVars[] AssignedVars[] 16336#[L12]don't care [246] L12-->L12-1: Formula: (and (= 2 (select |v_#length_4| 1)) (= (select |v_#valid_9| 1) 1)) InVars {#length=|v_#length_4|, #valid=|v_#valid_9|} OutVars{#length=|v_#length_4|, #valid=|v_#valid_9|} AuxVars[] AssignedVars[] 16604#[L12-1]don't care [273] L12-1-->L12-2: Formula: (= (select (select |v_#memory_int_5| 1) 0) 48) InVars {#memory_int=|v_#memory_int_5|} OutVars{#memory_int=|v_#memory_int_5|} AuxVars[] AssignedVars[] 15500#[L12-2]don't care [271] L12-2-->L12-3: Formula: (= (select (select |v_#memory_int_6| 1) 1) 0) InVars {#memory_int=|v_#memory_int_6|} OutVars{#memory_int=|v_#memory_int_6|} AuxVars[] AssignedVars[] 15502#[L12-3]don't care [297] L12-3-->L12-4: Formula: (and (= (select |v_#valid_10| 2) 1) (= (select |v_#length_5| 2) 10)) InVars {#length=|v_#length_5|, #valid=|v_#valid_10|} OutVars{#length=|v_#length_5|, #valid=|v_#valid_10|} AuxVars[] AssignedVars[] 14762#[L12-4]don't care [285] L12-4-->L684: Formula: (= v_~x~0_7 0) InVars {} OutVars{~x~0=v_~x~0_7} AuxVars[] AssignedVars[~x~0] 14764#[L684]don't care [220] L684-->L685: Formula: (= v_~y~0_21 0) InVars {} OutVars{~y~0=v_~y~0_21} AuxVars[] AssignedVars[~y~0] 16174#[L685]don't care [245] L685-->L685-1: Formula: (= v_~b1~0_7 0) InVars {} OutVars{~b1~0=v_~b1~0_7} AuxVars[] AssignedVars[~b1~0] 16120#[L685-1]don't care [288] L685-1-->L686: Formula: (= v_~b2~0_7 0) InVars {} OutVars{~b2~0=v_~b2~0_7} AuxVars[] AssignedVars[~b2~0] 16122#[L686]don't care [321] L686-->L-1-3: Formula: (= v_~X~0_7 0) InVars {} OutVars{~X~0=v_~X~0_7} AuxVars[] AssignedVars[~X~0] 15876#[L-1-3]don't care [312] L-1-3-->L-1-4: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 13220#[L-1-4]don't care [284] L-1-4-->L-1-5: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 13222#[L-1-5]don't care [244] L-1-5-->L-1-6: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res#1=|v_ULTIMATE.start_main_#res#1_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res#1] 14240#[L-1-6]don't care [282] L-1-6-->L740: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_4|, ULTIMATE.start_main_#t~nondet4#1=|v_ULTIMATE.start_main_#t~nondet4#1_2|, ULTIMATE.start_main_#t~mem7#1=|v_ULTIMATE.start_main_#t~mem7#1_3|, ULTIMATE.start_main_#t~mem8#1=|v_ULTIMATE.start_main_#t~mem8#1_3|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_5|, ULTIMATE.start_main_#t~nondet6#1=|v_ULTIMATE.start_main_#t~nondet6#1_2|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_4|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_4|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_2|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_5|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre5#1, ULTIMATE.start_main_#t~nondet4#1, ULTIMATE.start_main_#t~mem7#1, ULTIMATE.start_main_#t~mem8#1, ULTIMATE.start_main_~#t2~0#1.offset, ULTIMATE.start_main_#t~nondet6#1, ULTIMATE.start_main_~#t1~0#1.base, ULTIMATE.start_main_~#t1~0#1.offset, ULTIMATE.start_main_#t~pre3#1, ULTIMATE.start_main_~#t2~0#1.base] 14242#[L740]don't care [286] L740-->L740-1: Formula: (and (= (select |v_#valid_12| |v_ULTIMATE.start_main_~#t1~0#1.base_5|) 0) (< |v_#StackHeapBarrier_2| |v_ULTIMATE.start_main_~#t1~0#1.base_5|) (= (store |v_#valid_12| |v_ULTIMATE.start_main_~#t1~0#1.base_5| 1) |v_#valid_11|) (not (= |v_ULTIMATE.start_main_~#t1~0#1.base_5| 0)) (= |v_#length_6| (store |v_#length_7| |v_ULTIMATE.start_main_~#t1~0#1.base_5| 4)) (= |v_ULTIMATE.start_main_~#t1~0#1.offset_5| 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_7|, #valid=|v_#valid_12|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_6|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_5|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_5|, #valid=|v_#valid_11|} AuxVars[] AssignedVars[#valid, #length, ULTIMATE.start_main_~#t1~0#1.base, ULTIMATE.start_main_~#t1~0#1.offset] 15548#[L740-1]don't care [293] L740-1-->L740-2: Formula: (and (= |v_#valid_13| (store |v_#valid_14| |v_ULTIMATE.start_main_~#t2~0#1.base_6| 1)) (not (= |v_ULTIMATE.start_main_~#t2~0#1.base_6| 0)) (= |v_#length_8| (store |v_#length_9| |v_ULTIMATE.start_main_~#t2~0#1.base_6| 4)) (< |v_#StackHeapBarrier_3| |v_ULTIMATE.start_main_~#t2~0#1.base_6|) (= (select |v_#valid_14| |v_ULTIMATE.start_main_~#t2~0#1.base_6|) 0) (= 0 |v_ULTIMATE.start_main_~#t2~0#1.offset_6|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_3|, #length=|v_#length_9|, #valid=|v_#valid_14|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_3|, #length=|v_#length_8|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_6|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_6|, #valid=|v_#valid_13|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2~0#1.offset, #valid, #length, ULTIMATE.start_main_~#t2~0#1.base] 15550#[L740-2]don't care [263] L740-2-->L741: Formula: (= |v_ULTIMATE.start_main_#t~pre3#1_3| |v_#pthreadsForks_4|) InVars {#pthreadsForks=|v_#pthreadsForks_4|} OutVars{#pthreadsForks=|v_#pthreadsForks_4|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre3#1] 13624#[L741]don't care [298] L741-->L741-1: Formula: (= (+ 1 |v_#pthreadsForks_6|) |v_#pthreadsForks_5|) InVars {#pthreadsForks=|v_#pthreadsForks_6|} OutVars{#pthreadsForks=|v_#pthreadsForks_5|} AuxVars[] AssignedVars[#pthreadsForks] 13626#[L741-1]don't care [294] L741-1-->L741-2: Formula: (and (<= 0 |v_ULTIMATE.start_main_~#t1~0#1.offset_6|) (<= (+ |v_ULTIMATE.start_main_~#t1~0#1.offset_6| 4) (select |v_#length_10| |v_ULTIMATE.start_main_~#t1~0#1.base_6|)) (= (store |v_#memory_int_8| |v_ULTIMATE.start_main_~#t1~0#1.base_6| (store (select |v_#memory_int_8| |v_ULTIMATE.start_main_~#t1~0#1.base_6|) |v_ULTIMATE.start_main_~#t1~0#1.offset_6| |v_ULTIMATE.start_main_#t~pre3#1_4|)) |v_#memory_int_7|) (= (select |v_#valid_15| |v_ULTIMATE.start_main_~#t1~0#1.base_6|) 1)) InVars {#valid=|v_#valid_15|, #memory_int=|v_#memory_int_8|, #length=|v_#length_10|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_6|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_6|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_4|} OutVars{#valid=|v_#valid_15|, #memory_int=|v_#memory_int_7|, #length=|v_#length_10|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_6|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_6|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_4|} AuxVars[] AssignedVars[#memory_int] 16652#[L741-2]don't care [401] L741-2-->thr1ENTRY: Formula: (and (= v_thr1Thread1of1ForFork1_thidvar1_2 0) (= |v_ULTIMATE.start_main_#t~pre3#1_6| v_thr1Thread1of1ForFork1_thidvar0_2) (= |v_thr1Thread1of1ForFork1_#in~_.base_4| 0) (= |v_thr1Thread1of1ForFork1_#in~_.offset_4| 0)) InVars {ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_6|} OutVars{thr1Thread1of1ForFork1_#in~_.offset=|v_thr1Thread1of1ForFork1_#in~_.offset_4|, thr1Thread1of1ForFork1_~_.base=v_thr1Thread1of1ForFork1_~_.base_4, thr1Thread1of1ForFork1_#res.base=|v_thr1Thread1of1ForFork1_#res.base_4|, thr1Thread1of1ForFork1_#in~_.base=|v_thr1Thread1of1ForFork1_#in~_.base_4|, thr1Thread1of1ForFork1_~_.offset=v_thr1Thread1of1ForFork1_~_.offset_4, thr1Thread1of1ForFork1_#res.offset=|v_thr1Thread1of1ForFork1_#res.offset_4|, thr1Thread1of1ForFork1_thidvar1=v_thr1Thread1of1ForFork1_thidvar1_2, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_6|, thr1Thread1of1ForFork1_thidvar0=v_thr1Thread1of1ForFork1_thidvar0_2} AuxVars[] AssignedVars[thr1Thread1of1ForFork1_#in~_.offset, thr1Thread1of1ForFork1_~_.base, thr1Thread1of1ForFork1_#res.base, thr1Thread1of1ForFork1_#in~_.base, thr1Thread1of1ForFork1_~_.offset, thr1Thread1of1ForFork1_#res.offset, thr1Thread1of1ForFork1_thidvar1, thr1Thread1of1ForFork1_thidvar0] 15268#[L741-3, thr1ENTRY]don't care [362] thr1ENTRY-->L688loopEntry: Formula: (and (= v_thr1Thread1of1ForFork1_~_.base_1 |v_thr1Thread1of1ForFork1_#in~_.base_1|) (= |v_thr1Thread1of1ForFork1_#in~_.offset_1| v_thr1Thread1of1ForFork1_~_.offset_1)) InVars {thr1Thread1of1ForFork1_#in~_.offset=|v_thr1Thread1of1ForFork1_#in~_.offset_1|, thr1Thread1of1ForFork1_#in~_.base=|v_thr1Thread1of1ForFork1_#in~_.base_1|} OutVars{thr1Thread1of1ForFork1_#in~_.offset=|v_thr1Thread1of1ForFork1_#in~_.offset_1|, thr1Thread1of1ForFork1_#in~_.base=|v_thr1Thread1of1ForFork1_#in~_.base_1|, thr1Thread1of1ForFork1_~_.offset=v_thr1Thread1of1ForFork1_~_.offset_1, thr1Thread1of1ForFork1_~_.base=v_thr1Thread1of1ForFork1_~_.base_1} AuxVars[] AssignedVars[thr1Thread1of1ForFork1_~_.base, thr1Thread1of1ForFork1_~_.offset] 15270#[L741-3, L688loopEntry]don't care [363] L688loopEntry-->L701-3: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 16236#[L701-3, L741-3]don't care [366] L701-3-->L689: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 16704#[L741-3, L689]don't care [368] L689-->L690: Formula: (= v_~b1~0_3 1) InVars {} OutVars{~b1~0=v_~b1~0_3} AuxVars[] AssignedVars[~b1~0] 14836#[L690, L741-3]don't care [371] L690-->L691: Formula: (= v_~x~0_5 1) InVars {} OutVars{~x~0=v_~x~0_5} AuxVars[] AssignedVars[~x~0] 14838#[L691, L741-3]don't care [374] L691-->L692: Formula: (not (= v_~y~0_15 0)) InVars {~y~0=v_~y~0_15} OutVars{~y~0=v_~y~0_15} AuxVars[] AssignedVars[] 16482#[L692, L741-3]don't care [378] L692-->L693-2: Formula: (= v_~b1~0_4 0) InVars {} OutVars{~b1~0=v_~b1~0_4} AuxVars[] AssignedVars[~b1~0] 16262#[L693-2, L741-3]don't care [2022-07-26 13:22:14,150 INFO L735 eck$LassoCheckResult]: Loop: 16262#[L693-2, L741-3]don't care [383] L693-2-->L693-2: Formula: (not (= v_~y~0_18 0)) InVars {~y~0=v_~y~0_18} OutVars{~y~0=v_~y~0_18} AuxVars[] AssignedVars[] 16262#[L693-2, L741-3]don't care [2022-07-26 13:22:14,152 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:14,152 INFO L85 PathProgramCache]: Analyzing trace with hash -1224079677, now seen corresponding path program 1 times [2022-07-26 13:22:14,152 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:14,152 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [765974657] [2022-07-26 13:22:14,152 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:14,152 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:14,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-26 13:22:14,215 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-26 13:22:14,216 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-26 13:22:14,216 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [765974657] [2022-07-26 13:22:14,216 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [765974657] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-26 13:22:14,216 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-26 13:22:14,216 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-26 13:22:14,217 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2003431833] [2022-07-26 13:22:14,217 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-26 13:22:14,217 INFO L738 eck$LassoCheckResult]: stem already infeasible [2022-07-26 13:22:14,217 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:14,218 INFO L85 PathProgramCache]: Analyzing trace with hash 414, now seen corresponding path program 1 times [2022-07-26 13:22:14,218 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:14,218 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1516873874] [2022-07-26 13:22:14,218 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:14,218 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:14,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:14,223 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-26 13:22:14,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:14,226 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-26 13:22:14,238 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-26 13:22:14,239 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-26 13:22:14,239 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-26 13:22:14,239 INFO L87 Difference]: Start difference. First operand 2122 states and 6098 transitions. cyclomatic complexity: 4530 Second operand has 3 states, 3 states have (on average 10.0) internal successors, (30), 3 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-26 13:22:14,287 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-26 13:22:14,288 INFO L93 Difference]: Finished difference Result 1912 states and 5383 transitions. [2022-07-26 13:22:14,288 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1912 states and 5383 transitions. [2022-07-26 13:22:14,305 INFO L131 ngComponentsAnalysis]: Automaton has 445 accepting balls. 445 [2022-07-26 13:22:14,322 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1912 states to 1912 states and 5383 transitions. [2022-07-26 13:22:14,322 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1912 [2022-07-26 13:22:14,325 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1912 [2022-07-26 13:22:14,325 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1912 states and 5383 transitions. [2022-07-26 13:22:14,328 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-26 13:22:14,329 INFO L220 hiAutomatonCegarLoop]: Abstraction has 1912 states and 5383 transitions. [2022-07-26 13:22:14,335 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1912 states and 5383 transitions. [2022-07-26 13:22:14,375 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1912 to 1912. [2022-07-26 13:22:14,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1912 states, 1912 states have (on average 2.815376569037657) internal successors, (5383), 1911 states have internal predecessors, (5383), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-26 13:22:14,389 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1912 states to 1912 states and 5383 transitions. [2022-07-26 13:22:14,390 INFO L242 hiAutomatonCegarLoop]: Abstraction has 1912 states and 5383 transitions. [2022-07-26 13:22:14,390 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-26 13:22:14,391 INFO L426 stractBuchiCegarLoop]: Abstraction has 1912 states and 5383 transitions. [2022-07-26 13:22:14,392 INFO L333 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-07-26 13:22:14,392 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1912 states and 5383 transitions. [2022-07-26 13:22:14,406 INFO L131 ngComponentsAnalysis]: Automaton has 445 accepting balls. 445 [2022-07-26 13:22:14,406 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-26 13:22:14,406 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-26 13:22:14,408 INFO L150 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-26 13:22:14,408 INFO L151 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-07-26 13:22:14,409 INFO L733 eck$LassoCheckResult]: Stem: 21126#[ULTIMATE.startENTRY]don't care [296] ULTIMATE.startENTRY-->L-1: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 21128#[L-1]don't care [276] L-1-->L-1-1: Formula: (and (= |v_#NULL.base_1| 0) (= |v_#NULL.offset_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] 21138#[L-1-1]don't care [304] L-1-1-->L-1-2: Formula: (= (select |v_#valid_8| 0) 0) InVars {#valid=|v_#valid_8|} OutVars{#valid=|v_#valid_8|} AuxVars[] AssignedVars[] 21140#[L-1-2]don't care [307] L-1-2-->L12: Formula: (< 0 |v_#StackHeapBarrier_1|) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|} AuxVars[] AssignedVars[] 22224#[L12]don't care [246] L12-->L12-1: Formula: (and (= 2 (select |v_#length_4| 1)) (= (select |v_#valid_9| 1) 1)) InVars {#length=|v_#length_4|, #valid=|v_#valid_9|} OutVars{#length=|v_#length_4|, #valid=|v_#valid_9|} AuxVars[] AssignedVars[] 22466#[L12-1]don't care [273] L12-1-->L12-2: Formula: (= (select (select |v_#memory_int_5| 1) 0) 48) InVars {#memory_int=|v_#memory_int_5|} OutVars{#memory_int=|v_#memory_int_5|} AuxVars[] AssignedVars[] 21448#[L12-2]don't care [271] L12-2-->L12-3: Formula: (= (select (select |v_#memory_int_6| 1) 1) 0) InVars {#memory_int=|v_#memory_int_6|} OutVars{#memory_int=|v_#memory_int_6|} AuxVars[] AssignedVars[] 21450#[L12-3]don't care [297] L12-3-->L12-4: Formula: (and (= (select |v_#valid_10| 2) 1) (= (select |v_#length_5| 2) 10)) InVars {#length=|v_#length_5|, #valid=|v_#valid_10|} OutVars{#length=|v_#length_5|, #valid=|v_#valid_10|} AuxVars[] AssignedVars[] 20776#[L12-4]don't care [285] L12-4-->L684: Formula: (= v_~x~0_7 0) InVars {} OutVars{~x~0=v_~x~0_7} AuxVars[] AssignedVars[~x~0] 20778#[L684]don't care [220] L684-->L685: Formula: (= v_~y~0_21 0) InVars {} OutVars{~y~0=v_~y~0_21} AuxVars[] AssignedVars[~y~0] 22066#[L685]don't care [245] L685-->L685-1: Formula: (= v_~b1~0_7 0) InVars {} OutVars{~b1~0=v_~b1~0_7} AuxVars[] AssignedVars[~b1~0] 22006#[L685-1]don't care [288] L685-1-->L686: Formula: (= v_~b2~0_7 0) InVars {} OutVars{~b2~0=v_~b2~0_7} AuxVars[] AssignedVars[~b2~0] 22008#[L686]don't care [321] L686-->L-1-3: Formula: (= v_~X~0_7 0) InVars {} OutVars{~X~0=v_~X~0_7} AuxVars[] AssignedVars[~X~0] 21782#[L-1-3]don't care [312] L-1-3-->L-1-4: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 19364#[L-1-4]don't care [284] L-1-4-->L-1-5: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 19366#[L-1-5]don't care [244] L-1-5-->L-1-6: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res#1=|v_ULTIMATE.start_main_#res#1_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res#1] 20326#[L-1-6]don't care [282] L-1-6-->L740: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_4|, ULTIMATE.start_main_#t~nondet4#1=|v_ULTIMATE.start_main_#t~nondet4#1_2|, ULTIMATE.start_main_#t~mem7#1=|v_ULTIMATE.start_main_#t~mem7#1_3|, ULTIMATE.start_main_#t~mem8#1=|v_ULTIMATE.start_main_#t~mem8#1_3|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_5|, ULTIMATE.start_main_#t~nondet6#1=|v_ULTIMATE.start_main_#t~nondet6#1_2|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_4|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_4|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_2|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_5|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre5#1, ULTIMATE.start_main_#t~nondet4#1, ULTIMATE.start_main_#t~mem7#1, ULTIMATE.start_main_#t~mem8#1, ULTIMATE.start_main_~#t2~0#1.offset, ULTIMATE.start_main_#t~nondet6#1, ULTIMATE.start_main_~#t1~0#1.base, ULTIMATE.start_main_~#t1~0#1.offset, ULTIMATE.start_main_#t~pre3#1, ULTIMATE.start_main_~#t2~0#1.base] 20328#[L740]don't care [286] L740-->L740-1: Formula: (and (= (select |v_#valid_12| |v_ULTIMATE.start_main_~#t1~0#1.base_5|) 0) (< |v_#StackHeapBarrier_2| |v_ULTIMATE.start_main_~#t1~0#1.base_5|) (= (store |v_#valid_12| |v_ULTIMATE.start_main_~#t1~0#1.base_5| 1) |v_#valid_11|) (not (= |v_ULTIMATE.start_main_~#t1~0#1.base_5| 0)) (= |v_#length_6| (store |v_#length_7| |v_ULTIMATE.start_main_~#t1~0#1.base_5| 4)) (= |v_ULTIMATE.start_main_~#t1~0#1.offset_5| 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_7|, #valid=|v_#valid_12|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_6|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_5|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_5|, #valid=|v_#valid_11|} AuxVars[] AssignedVars[#valid, #length, ULTIMATE.start_main_~#t1~0#1.base, ULTIMATE.start_main_~#t1~0#1.offset] 21494#[L740-1]don't care [293] L740-1-->L740-2: Formula: (and (= |v_#valid_13| (store |v_#valid_14| |v_ULTIMATE.start_main_~#t2~0#1.base_6| 1)) (not (= |v_ULTIMATE.start_main_~#t2~0#1.base_6| 0)) (= |v_#length_8| (store |v_#length_9| |v_ULTIMATE.start_main_~#t2~0#1.base_6| 4)) (< |v_#StackHeapBarrier_3| |v_ULTIMATE.start_main_~#t2~0#1.base_6|) (= (select |v_#valid_14| |v_ULTIMATE.start_main_~#t2~0#1.base_6|) 0) (= 0 |v_ULTIMATE.start_main_~#t2~0#1.offset_6|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_3|, #length=|v_#length_9|, #valid=|v_#valid_14|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_3|, #length=|v_#length_8|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_6|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_6|, #valid=|v_#valid_13|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2~0#1.offset, #valid, #length, ULTIMATE.start_main_~#t2~0#1.base] 21496#[L740-2]don't care [263] L740-2-->L741: Formula: (= |v_ULTIMATE.start_main_#t~pre3#1_3| |v_#pthreadsForks_4|) InVars {#pthreadsForks=|v_#pthreadsForks_4|} OutVars{#pthreadsForks=|v_#pthreadsForks_4|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre3#1] 19754#[L741]don't care [298] L741-->L741-1: Formula: (= (+ 1 |v_#pthreadsForks_6|) |v_#pthreadsForks_5|) InVars {#pthreadsForks=|v_#pthreadsForks_6|} OutVars{#pthreadsForks=|v_#pthreadsForks_5|} AuxVars[] AssignedVars[#pthreadsForks] 19756#[L741-1]don't care [294] L741-1-->L741-2: Formula: (and (<= 0 |v_ULTIMATE.start_main_~#t1~0#1.offset_6|) (<= (+ |v_ULTIMATE.start_main_~#t1~0#1.offset_6| 4) (select |v_#length_10| |v_ULTIMATE.start_main_~#t1~0#1.base_6|)) (= (store |v_#memory_int_8| |v_ULTIMATE.start_main_~#t1~0#1.base_6| (store (select |v_#memory_int_8| |v_ULTIMATE.start_main_~#t1~0#1.base_6|) |v_ULTIMATE.start_main_~#t1~0#1.offset_6| |v_ULTIMATE.start_main_#t~pre3#1_4|)) |v_#memory_int_7|) (= (select |v_#valid_15| |v_ULTIMATE.start_main_~#t1~0#1.base_6|) 1)) InVars {#valid=|v_#valid_15|, #memory_int=|v_#memory_int_8|, #length=|v_#length_10|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_6|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_6|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_4|} OutVars{#valid=|v_#valid_15|, #memory_int=|v_#memory_int_7|, #length=|v_#length_10|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_6|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_6|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_4|} AuxVars[] AssignedVars[#memory_int] 22518#[L741-2]don't care [401] L741-2-->thr1ENTRY: Formula: (and (= v_thr1Thread1of1ForFork1_thidvar1_2 0) (= |v_ULTIMATE.start_main_#t~pre3#1_6| v_thr1Thread1of1ForFork1_thidvar0_2) (= |v_thr1Thread1of1ForFork1_#in~_.base_4| 0) (= |v_thr1Thread1of1ForFork1_#in~_.offset_4| 0)) InVars {ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_6|} OutVars{thr1Thread1of1ForFork1_#in~_.offset=|v_thr1Thread1of1ForFork1_#in~_.offset_4|, thr1Thread1of1ForFork1_~_.base=v_thr1Thread1of1ForFork1_~_.base_4, thr1Thread1of1ForFork1_#res.base=|v_thr1Thread1of1ForFork1_#res.base_4|, thr1Thread1of1ForFork1_#in~_.base=|v_thr1Thread1of1ForFork1_#in~_.base_4|, thr1Thread1of1ForFork1_~_.offset=v_thr1Thread1of1ForFork1_~_.offset_4, thr1Thread1of1ForFork1_#res.offset=|v_thr1Thread1of1ForFork1_#res.offset_4|, thr1Thread1of1ForFork1_thidvar1=v_thr1Thread1of1ForFork1_thidvar1_2, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_6|, thr1Thread1of1ForFork1_thidvar0=v_thr1Thread1of1ForFork1_thidvar0_2} AuxVars[] AssignedVars[thr1Thread1of1ForFork1_#in~_.offset, thr1Thread1of1ForFork1_~_.base, thr1Thread1of1ForFork1_#res.base, thr1Thread1of1ForFork1_#in~_.base, thr1Thread1of1ForFork1_~_.offset, thr1Thread1of1ForFork1_#res.offset, thr1Thread1of1ForFork1_thidvar1, thr1Thread1of1ForFork1_thidvar0] 21224#[L741-3, thr1ENTRY]don't care [362] thr1ENTRY-->L688loopEntry: Formula: (and (= v_thr1Thread1of1ForFork1_~_.base_1 |v_thr1Thread1of1ForFork1_#in~_.base_1|) (= |v_thr1Thread1of1ForFork1_#in~_.offset_1| v_thr1Thread1of1ForFork1_~_.offset_1)) InVars {thr1Thread1of1ForFork1_#in~_.offset=|v_thr1Thread1of1ForFork1_#in~_.offset_1|, thr1Thread1of1ForFork1_#in~_.base=|v_thr1Thread1of1ForFork1_#in~_.base_1|} OutVars{thr1Thread1of1ForFork1_#in~_.offset=|v_thr1Thread1of1ForFork1_#in~_.offset_1|, thr1Thread1of1ForFork1_#in~_.base=|v_thr1Thread1of1ForFork1_#in~_.base_1|, thr1Thread1of1ForFork1_~_.offset=v_thr1Thread1of1ForFork1_~_.offset_1, thr1Thread1of1ForFork1_~_.base=v_thr1Thread1of1ForFork1_~_.base_1} AuxVars[] AssignedVars[thr1Thread1of1ForFork1_~_.base, thr1Thread1of1ForFork1_~_.offset] 21226#[L741-3, L688loopEntry]don't care [363] L688loopEntry-->L701-3: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 22128#[L701-3, L741-3]don't care [366] L701-3-->L689: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 22568#[L741-3, L689]don't care [368] L689-->L690: Formula: (= v_~b1~0_3 1) InVars {} OutVars{~b1~0=v_~b1~0_3} AuxVars[] AssignedVars[~b1~0] 20828#[L690, L741-3]don't care [371] L690-->L691: Formula: (= v_~x~0_5 1) InVars {} OutVars{~x~0=v_~x~0_5} AuxVars[] AssignedVars[~x~0] 20830#[L691, L741-3]don't care [375] L691-->L696: Formula: (= v_~y~0_19 0) InVars {~y~0=v_~y~0_19} OutVars{~y~0=v_~y~0_19} AuxVars[] AssignedVars[] 22112#[L741-3, L696]don't care [379] L696-->L697: Formula: (= v_~y~0_20 1) InVars {} OutVars{~y~0=v_~y~0_20} AuxVars[] AssignedVars[~y~0] 22114#[L741-3, L697]don't care [384] L697-->L698: Formula: (not (= v_~x~0_6 1)) InVars {~x~0=v_~x~0_6} OutVars{~x~0=v_~x~0_6} AuxVars[] AssignedVars[] 20674#[L741-3, L698]don't care [387] L698-->L699-2: Formula: (= v_~b1~0_6 0) InVars {} OutVars{~b1~0=v_~b1~0_6} AuxVars[] AssignedVars[~b1~0] 20676#[L699-2, L741-3]don't care [2022-07-26 13:22:14,409 INFO L735 eck$LassoCheckResult]: Loop: 20676#[L699-2, L741-3]don't care [390] L699-2-->L699-2: Formula: (<= 1 v_~b2~0_6) InVars {~b2~0=v_~b2~0_6} OutVars{~b2~0=v_~b2~0_6} AuxVars[] AssignedVars[] 20676#[L699-2, L741-3]don't care [2022-07-26 13:22:14,410 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:14,410 INFO L85 PathProgramCache]: Analyzing trace with hash 480512550, now seen corresponding path program 1 times [2022-07-26 13:22:14,410 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:14,410 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [776749428] [2022-07-26 13:22:14,410 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:14,411 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:14,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-26 13:22:14,481 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-26 13:22:14,481 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-26 13:22:14,482 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [776749428] [2022-07-26 13:22:14,482 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [776749428] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-26 13:22:14,483 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-26 13:22:14,483 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-26 13:22:14,483 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [618208094] [2022-07-26 13:22:14,483 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-26 13:22:14,484 INFO L738 eck$LassoCheckResult]: stem already infeasible [2022-07-26 13:22:14,484 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:14,485 INFO L85 PathProgramCache]: Analyzing trace with hash 421, now seen corresponding path program 1 times [2022-07-26 13:22:14,485 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:14,488 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [168919727] [2022-07-26 13:22:14,488 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:14,488 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:14,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:14,492 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-26 13:22:14,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:14,495 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-26 13:22:14,511 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-26 13:22:14,512 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-26 13:22:14,513 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-26 13:22:14,513 INFO L87 Difference]: Start difference. First operand 1912 states and 5383 transitions. cyclomatic complexity: 3916 Second operand has 3 states, 3 states have (on average 10.666666666666666) internal successors, (32), 3 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-26 13:22:14,559 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-26 13:22:14,559 INFO L93 Difference]: Finished difference Result 2631 states and 7204 transitions. [2022-07-26 13:22:14,559 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2631 states and 7204 transitions. [2022-07-26 13:22:14,584 INFO L131 ngComponentsAnalysis]: Automaton has 570 accepting balls. 570 [2022-07-26 13:22:14,607 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2631 states to 2311 states and 6372 transitions. [2022-07-26 13:22:14,608 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2311 [2022-07-26 13:22:14,612 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2311 [2022-07-26 13:22:14,613 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2311 states and 6372 transitions. [2022-07-26 13:22:14,617 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-26 13:22:14,617 INFO L220 hiAutomatonCegarLoop]: Abstraction has 2311 states and 6372 transitions. [2022-07-26 13:22:14,624 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2311 states and 6372 transitions. [2022-07-26 13:22:14,713 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2311 to 1772. [2022-07-26 13:22:14,717 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1772 states, 1772 states have (on average 2.7866817155756207) internal successors, (4938), 1771 states have internal predecessors, (4938), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-26 13:22:14,726 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1772 states to 1772 states and 4938 transitions. [2022-07-26 13:22:14,726 INFO L242 hiAutomatonCegarLoop]: Abstraction has 1772 states and 4938 transitions. [2022-07-26 13:22:14,727 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-26 13:22:14,728 INFO L426 stractBuchiCegarLoop]: Abstraction has 1772 states and 4938 transitions. [2022-07-26 13:22:14,728 INFO L333 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-07-26 13:22:14,728 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1772 states and 4938 transitions. [2022-07-26 13:22:14,740 INFO L131 ngComponentsAnalysis]: Automaton has 421 accepting balls. 421 [2022-07-26 13:22:14,740 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-26 13:22:14,740 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-26 13:22:14,743 INFO L150 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-26 13:22:14,743 INFO L151 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-07-26 13:22:14,745 INFO L733 eck$LassoCheckResult]: Stem: 28193#[ULTIMATE.startENTRY]don't care [296] ULTIMATE.startENTRY-->L-1: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 28195#[L-1]don't care [276] L-1-->L-1-1: Formula: (and (= |v_#NULL.base_1| 0) (= |v_#NULL.offset_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] 28201#[L-1-1]don't care [304] L-1-1-->L-1-2: Formula: (= (select |v_#valid_8| 0) 0) InVars {#valid=|v_#valid_8|} OutVars{#valid=|v_#valid_8|} AuxVars[] AssignedVars[] 28203#[L-1-2]don't care [307] L-1-2-->L12: Formula: (< 0 |v_#StackHeapBarrier_1|) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|} AuxVars[] AssignedVars[] 27815#[L12]don't care [246] L12-->L12-1: Formula: (and (= 2 (select |v_#length_4| 1)) (= (select |v_#valid_9| 1) 1)) InVars {#length=|v_#length_4|, #valid=|v_#valid_9|} OutVars{#length=|v_#length_4|, #valid=|v_#valid_9|} AuxVars[] AssignedVars[] 27817#[L12-1]don't care [273] L12-1-->L12-2: Formula: (= (select (select |v_#memory_int_5| 1) 0) 48) InVars {#memory_int=|v_#memory_int_5|} OutVars{#memory_int=|v_#memory_int_5|} AuxVars[] AssignedVars[] 27871#[L12-2]don't care [271] L12-2-->L12-3: Formula: (= (select (select |v_#memory_int_6| 1) 1) 0) InVars {#memory_int=|v_#memory_int_6|} OutVars{#memory_int=|v_#memory_int_6|} AuxVars[] AssignedVars[] 26631#[L12-3]don't care [297] L12-3-->L12-4: Formula: (and (= (select |v_#valid_10| 2) 1) (= (select |v_#length_5| 2) 10)) InVars {#length=|v_#length_5|, #valid=|v_#valid_10|} OutVars{#length=|v_#length_5|, #valid=|v_#valid_10|} AuxVars[] AssignedVars[] 26633#[L12-4]don't care [285] L12-4-->L684: Formula: (= v_~x~0_7 0) InVars {} OutVars{~x~0=v_~x~0_7} AuxVars[] AssignedVars[~x~0] 27907#[L684]don't care [220] L684-->L685: Formula: (= v_~y~0_21 0) InVars {} OutVars{~y~0=v_~y~0_21} AuxVars[] AssignedVars[~y~0] 28601#[L685]don't care [245] L685-->L685-1: Formula: (= v_~b1~0_7 0) InVars {} OutVars{~b1~0=v_~b1~0_7} AuxVars[] AssignedVars[~b1~0] 28603#[L685-1]don't care [288] L685-1-->L686: Formula: (= v_~b2~0_7 0) InVars {} OutVars{~b2~0=v_~b2~0_7} AuxVars[] AssignedVars[~b2~0] 28627#[L686]don't care [321] L686-->L-1-3: Formula: (= v_~X~0_7 0) InVars {} OutVars{~X~0=v_~X~0_7} AuxVars[] AssignedVars[~X~0] 28509#[L-1-3]don't care [312] L-1-3-->L-1-4: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 25969#[L-1-4]don't care [284] L-1-4-->L-1-5: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 25971#[L-1-5]don't care [244] L-1-5-->L-1-6: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res#1=|v_ULTIMATE.start_main_#res#1_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res#1] 27397#[L-1-6]don't care [282] L-1-6-->L740: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_4|, ULTIMATE.start_main_#t~nondet4#1=|v_ULTIMATE.start_main_#t~nondet4#1_2|, ULTIMATE.start_main_#t~mem7#1=|v_ULTIMATE.start_main_#t~mem7#1_3|, ULTIMATE.start_main_#t~mem8#1=|v_ULTIMATE.start_main_#t~mem8#1_3|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_5|, ULTIMATE.start_main_#t~nondet6#1=|v_ULTIMATE.start_main_#t~nondet6#1_2|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_4|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_4|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_2|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_5|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre5#1, ULTIMATE.start_main_#t~nondet4#1, ULTIMATE.start_main_#t~mem7#1, ULTIMATE.start_main_#t~mem8#1, ULTIMATE.start_main_~#t2~0#1.offset, ULTIMATE.start_main_#t~nondet6#1, ULTIMATE.start_main_~#t1~0#1.base, ULTIMATE.start_main_~#t1~0#1.offset, ULTIMATE.start_main_#t~pre3#1, ULTIMATE.start_main_~#t2~0#1.base] 27399#[L740]don't care [286] L740-->L740-1: Formula: (and (= (select |v_#valid_12| |v_ULTIMATE.start_main_~#t1~0#1.base_5|) 0) (< |v_#StackHeapBarrier_2| |v_ULTIMATE.start_main_~#t1~0#1.base_5|) (= (store |v_#valid_12| |v_ULTIMATE.start_main_~#t1~0#1.base_5| 1) |v_#valid_11|) (not (= |v_ULTIMATE.start_main_~#t1~0#1.base_5| 0)) (= |v_#length_6| (store |v_#length_7| |v_ULTIMATE.start_main_~#t1~0#1.base_5| 4)) (= |v_ULTIMATE.start_main_~#t1~0#1.offset_5| 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_7|, #valid=|v_#valid_12|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_6|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_5|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_5|, #valid=|v_#valid_11|} AuxVars[] AssignedVars[#valid, #length, ULTIMATE.start_main_~#t1~0#1.base, ULTIMATE.start_main_~#t1~0#1.offset] 28371#[L740-1]don't care [293] L740-1-->L740-2: Formula: (and (= |v_#valid_13| (store |v_#valid_14| |v_ULTIMATE.start_main_~#t2~0#1.base_6| 1)) (not (= |v_ULTIMATE.start_main_~#t2~0#1.base_6| 0)) (= |v_#length_8| (store |v_#length_9| |v_ULTIMATE.start_main_~#t2~0#1.base_6| 4)) (< |v_#StackHeapBarrier_3| |v_ULTIMATE.start_main_~#t2~0#1.base_6|) (= (select |v_#valid_14| |v_ULTIMATE.start_main_~#t2~0#1.base_6|) 0) (= 0 |v_ULTIMATE.start_main_~#t2~0#1.offset_6|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_3|, #length=|v_#length_9|, #valid=|v_#valid_14|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_3|, #length=|v_#length_8|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_6|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_6|, #valid=|v_#valid_13|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2~0#1.offset, #valid, #length, ULTIMATE.start_main_~#t2~0#1.base] 28249#[L740-2]don't care [263] L740-2-->L741: Formula: (= |v_ULTIMATE.start_main_#t~pre3#1_3| |v_#pthreadsForks_4|) InVars {#pthreadsForks=|v_#pthreadsForks_4|} OutVars{#pthreadsForks=|v_#pthreadsForks_4|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre3#1] 26641#[L741]don't care [298] L741-->L741-1: Formula: (= (+ 1 |v_#pthreadsForks_6|) |v_#pthreadsForks_5|) InVars {#pthreadsForks=|v_#pthreadsForks_6|} OutVars{#pthreadsForks=|v_#pthreadsForks_5|} AuxVars[] AssignedVars[#pthreadsForks] 26643#[L741-1]don't care [294] L741-1-->L741-2: Formula: (and (<= 0 |v_ULTIMATE.start_main_~#t1~0#1.offset_6|) (<= (+ |v_ULTIMATE.start_main_~#t1~0#1.offset_6| 4) (select |v_#length_10| |v_ULTIMATE.start_main_~#t1~0#1.base_6|)) (= (store |v_#memory_int_8| |v_ULTIMATE.start_main_~#t1~0#1.base_6| (store (select |v_#memory_int_8| |v_ULTIMATE.start_main_~#t1~0#1.base_6|) |v_ULTIMATE.start_main_~#t1~0#1.offset_6| |v_ULTIMATE.start_main_#t~pre3#1_4|)) |v_#memory_int_7|) (= (select |v_#valid_15| |v_ULTIMATE.start_main_~#t1~0#1.base_6|) 1)) InVars {#valid=|v_#valid_15|, #memory_int=|v_#memory_int_8|, #length=|v_#length_10|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_6|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_6|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_4|} OutVars{#valid=|v_#valid_15|, #memory_int=|v_#memory_int_7|, #length=|v_#length_10|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_6|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_6|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_4|} AuxVars[] AssignedVars[#memory_int] 28133#[L741-2]don't care [401] L741-2-->thr1ENTRY: Formula: (and (= v_thr1Thread1of1ForFork1_thidvar1_2 0) (= |v_ULTIMATE.start_main_#t~pre3#1_6| v_thr1Thread1of1ForFork1_thidvar0_2) (= |v_thr1Thread1of1ForFork1_#in~_.base_4| 0) (= |v_thr1Thread1of1ForFork1_#in~_.offset_4| 0)) InVars {ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_6|} OutVars{thr1Thread1of1ForFork1_#in~_.offset=|v_thr1Thread1of1ForFork1_#in~_.offset_4|, thr1Thread1of1ForFork1_~_.base=v_thr1Thread1of1ForFork1_~_.base_4, thr1Thread1of1ForFork1_#res.base=|v_thr1Thread1of1ForFork1_#res.base_4|, thr1Thread1of1ForFork1_#in~_.base=|v_thr1Thread1of1ForFork1_#in~_.base_4|, thr1Thread1of1ForFork1_~_.offset=v_thr1Thread1of1ForFork1_~_.offset_4, thr1Thread1of1ForFork1_#res.offset=|v_thr1Thread1of1ForFork1_#res.offset_4|, thr1Thread1of1ForFork1_thidvar1=v_thr1Thread1of1ForFork1_thidvar1_2, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_6|, thr1Thread1of1ForFork1_thidvar0=v_thr1Thread1of1ForFork1_thidvar0_2} AuxVars[] AssignedVars[thr1Thread1of1ForFork1_#in~_.offset, thr1Thread1of1ForFork1_~_.base, thr1Thread1of1ForFork1_#res.base, thr1Thread1of1ForFork1_#in~_.base, thr1Thread1of1ForFork1_~_.offset, thr1Thread1of1ForFork1_#res.offset, thr1Thread1of1ForFork1_thidvar1, thr1Thread1of1ForFork1_thidvar0] 28135#[L741-3, thr1ENTRY]don't care [283] L741-3-->L741-4: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre3#1] 28233#[thr1ENTRY, L741-4]don't care [239] L741-4-->L742: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet4#1=|v_ULTIMATE.start_main_#t~nondet4#1_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet4#1] 26827#[L742, thr1ENTRY]don't care [274] L742-->L742-1: Formula: (= |v_ULTIMATE.start_main_#t~pre5#1_1| |v_#pthreadsForks_1|) InVars {#pthreadsForks=|v_#pthreadsForks_1|} OutVars{ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_1|, #pthreadsForks=|v_#pthreadsForks_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre5#1] 26829#[L742-1, thr1ENTRY]don't care [278] L742-1-->L742-2: Formula: (= (+ 1 |v_#pthreadsForks_3|) |v_#pthreadsForks_2|) InVars {#pthreadsForks=|v_#pthreadsForks_3|} OutVars{#pthreadsForks=|v_#pthreadsForks_2|} AuxVars[] AssignedVars[#pthreadsForks] 28467#[L742-2, thr1ENTRY]don't care [238] L742-2-->L742-3: Formula: (and (= (select |v_#valid_1| |v_ULTIMATE.start_main_~#t2~0#1.base_1|) 1) (= (store |v_#memory_int_2| |v_ULTIMATE.start_main_~#t2~0#1.base_1| (store (select |v_#memory_int_2| |v_ULTIMATE.start_main_~#t2~0#1.base_1|) |v_ULTIMATE.start_main_~#t2~0#1.offset_1| |v_ULTIMATE.start_main_#t~pre5#1_2|)) |v_#memory_int_1|) (<= (+ 4 |v_ULTIMATE.start_main_~#t2~0#1.offset_1|) (select |v_#length_1| |v_ULTIMATE.start_main_~#t2~0#1.base_1|)) (<= 0 |v_ULTIMATE.start_main_~#t2~0#1.offset_1|)) InVars {ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_2|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_2|, #length=|v_#length_1|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_1|} OutVars{ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_2|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #length=|v_#length_1|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_1|} AuxVars[] AssignedVars[#memory_int] 28171#[thr1ENTRY, L742-3]don't care [398] L742-3-->thr2ENTRY: Formula: (and (= v_thr2Thread1of1ForFork0_thidvar2_2 0) (= |v_thr2Thread1of1ForFork0_#in~_.offset_4| 0) (= |v_thr2Thread1of1ForFork0_#in~_.base_4| 0) (= v_thr2Thread1of1ForFork0_thidvar1_2 0) (= |v_ULTIMATE.start_main_#t~pre5#1_6| v_thr2Thread1of1ForFork0_thidvar0_2)) InVars {ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_6|} OutVars{ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_6|, thr2Thread1of1ForFork0_~_.offset=v_thr2Thread1of1ForFork0_~_.offset_4, thr2Thread1of1ForFork0_#in~_.offset=|v_thr2Thread1of1ForFork0_#in~_.offset_4|, thr2Thread1of1ForFork0_#res.base=|v_thr2Thread1of1ForFork0_#res.base_4|, thr2Thread1of1ForFork0_thidvar0=v_thr2Thread1of1ForFork0_thidvar0_2, thr2Thread1of1ForFork0_thidvar1=v_thr2Thread1of1ForFork0_thidvar1_2, thr2Thread1of1ForFork0_thidvar2=v_thr2Thread1of1ForFork0_thidvar2_2, thr2Thread1of1ForFork0_#res.offset=|v_thr2Thread1of1ForFork0_#res.offset_4|, thr2Thread1of1ForFork0_#in~_.base=|v_thr2Thread1of1ForFork0_#in~_.base_4|, thr2Thread1of1ForFork0_~_.base=v_thr2Thread1of1ForFork0_~_.base_4} AuxVars[] AssignedVars[thr2Thread1of1ForFork0_~_.offset, thr2Thread1of1ForFork0_#in~_.offset, thr2Thread1of1ForFork0_#res.base, thr2Thread1of1ForFork0_thidvar0, thr2Thread1of1ForFork0_thidvar1, thr2Thread1of1ForFork0_thidvar2, thr2Thread1of1ForFork0_#res.offset, thr2Thread1of1ForFork0_#in~_.base, thr2Thread1of1ForFork0_~_.base] 27539#[thr1ENTRY, L742-4, thr2ENTRY]don't care [328] thr2ENTRY-->L714loopEntry: Formula: (and (= |v_thr2Thread1of1ForFork0_#in~_.base_1| v_thr2Thread1of1ForFork0_~_.base_1) (= v_thr2Thread1of1ForFork0_~_.offset_1 |v_thr2Thread1of1ForFork0_#in~_.offset_1|)) InVars {thr2Thread1of1ForFork0_#in~_.offset=|v_thr2Thread1of1ForFork0_#in~_.offset_1|, thr2Thread1of1ForFork0_#in~_.base=|v_thr2Thread1of1ForFork0_#in~_.base_1|} OutVars{thr2Thread1of1ForFork0_~_.offset=v_thr2Thread1of1ForFork0_~_.offset_1, thr2Thread1of1ForFork0_#in~_.offset=|v_thr2Thread1of1ForFork0_#in~_.offset_1|, thr2Thread1of1ForFork0_#in~_.base=|v_thr2Thread1of1ForFork0_#in~_.base_1|, thr2Thread1of1ForFork0_~_.base=v_thr2Thread1of1ForFork0_~_.base_1} AuxVars[] AssignedVars[thr2Thread1of1ForFork0_~_.offset, thr2Thread1of1ForFork0_~_.base] 27541#[thr1ENTRY, L742-4, L714loopEntry]don't care [329] L714loopEntry-->L727-3: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 27873#[thr1ENTRY, L742-4, L727-3]don't care [332] L727-3-->L715: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 27803#[thr1ENTRY, L742-4, L715]don't care [334] L715-->L716: Formula: (= v_~b2~0_1 1) InVars {} OutVars{~b2~0=v_~b2~0_1} AuxVars[] AssignedVars[~b2~0] 27747#[thr1ENTRY, L716, L742-4]don't care [337] L716-->L717: Formula: (= 2 v_~x~0_2) InVars {} OutVars{~x~0=v_~x~0_2} AuxVars[] AssignedVars[~x~0] 27749#[thr1ENTRY, L742-4, L717]don't care [341] L717-->L722: Formula: (= v_~y~0_5 0) InVars {~y~0=v_~y~0_5} OutVars{~y~0=v_~y~0_5} AuxVars[] AssignedVars[] 28517#[thr1ENTRY, L742-4, L722]don't care [345] L722-->L723: Formula: (= 2 v_~y~0_6) InVars {} OutVars{~y~0=v_~y~0_6} AuxVars[] AssignedVars[~y~0] 28671#[thr1ENTRY, L742-4, L723]don't care [350] L723-->L724: Formula: (not (= 2 v_~x~0_3)) InVars {~x~0=v_~x~0_3} OutVars{~x~0=v_~x~0_3} AuxVars[] AssignedVars[] 28607#[thr1ENTRY, L742-4, L724]don't care [353] L724-->L725-2: Formula: (= v_~b2~0_4 0) InVars {} OutVars{~b2~0=v_~b2~0_4} AuxVars[] AssignedVars[~b2~0] 28609#[thr1ENTRY, L742-4, L725-2]don't care [2022-07-26 13:22:14,746 INFO L735 eck$LassoCheckResult]: Loop: 28609#[thr1ENTRY, L742-4, L725-2]don't care [356] L725-2-->L725-2: Formula: (<= 1 v_~b1~0_2) InVars {~b1~0=v_~b1~0_2} OutVars{~b1~0=v_~b1~0_2} AuxVars[] AssignedVars[] 28609#[thr1ENTRY, L742-4, L725-2]don't care [2022-07-26 13:22:14,746 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:14,746 INFO L85 PathProgramCache]: Analyzing trace with hash 149030380, now seen corresponding path program 1 times [2022-07-26 13:22:14,746 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:14,747 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1901596829] [2022-07-26 13:22:14,747 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:14,747 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:14,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-26 13:22:14,810 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-26 13:22:14,811 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-26 13:22:14,811 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1901596829] [2022-07-26 13:22:14,811 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1901596829] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-26 13:22:14,811 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-26 13:22:14,811 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-07-26 13:22:14,812 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1033688058] [2022-07-26 13:22:14,812 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-26 13:22:14,813 INFO L738 eck$LassoCheckResult]: stem already infeasible [2022-07-26 13:22:14,813 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:14,813 INFO L85 PathProgramCache]: Analyzing trace with hash 387, now seen corresponding path program 1 times [2022-07-26 13:22:14,816 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:14,816 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [372336758] [2022-07-26 13:22:14,817 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:14,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:14,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:14,821 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-26 13:22:14,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:14,827 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-26 13:22:14,833 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-26 13:22:14,833 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-26 13:22:14,833 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-26 13:22:14,834 INFO L87 Difference]: Start difference. First operand 1772 states and 4938 transitions. cyclomatic complexity: 3587 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-26 13:22:14,861 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-26 13:22:14,861 INFO L93 Difference]: Finished difference Result 1871 states and 4868 transitions. [2022-07-26 13:22:14,861 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1871 states and 4868 transitions. [2022-07-26 13:22:14,876 INFO L131 ngComponentsAnalysis]: Automaton has 345 accepting balls. 345 [2022-07-26 13:22:14,888 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1871 states to 1473 states and 3883 transitions. [2022-07-26 13:22:14,889 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1473 [2022-07-26 13:22:14,890 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1473 [2022-07-26 13:22:14,891 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1473 states and 3883 transitions. [2022-07-26 13:22:14,893 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-26 13:22:14,893 INFO L220 hiAutomatonCegarLoop]: Abstraction has 1473 states and 3883 transitions. [2022-07-26 13:22:14,897 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1473 states and 3883 transitions. [2022-07-26 13:22:14,920 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1473 to 1401. [2022-07-26 13:22:14,924 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1401 states, 1401 states have (on average 2.6473947180585298) internal successors, (3709), 1400 states have internal predecessors, (3709), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-26 13:22:14,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1401 states to 1401 states and 3709 transitions. [2022-07-26 13:22:14,930 INFO L242 hiAutomatonCegarLoop]: Abstraction has 1401 states and 3709 transitions. [2022-07-26 13:22:14,931 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-26 13:22:14,933 INFO L426 stractBuchiCegarLoop]: Abstraction has 1401 states and 3709 transitions. [2022-07-26 13:22:14,933 INFO L333 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-07-26 13:22:14,934 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1401 states and 3709 transitions. [2022-07-26 13:22:14,942 INFO L131 ngComponentsAnalysis]: Automaton has 313 accepting balls. 313 [2022-07-26 13:22:14,942 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-26 13:22:14,942 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-26 13:22:14,943 INFO L150 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-26 13:22:14,944 INFO L151 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-07-26 13:22:14,945 INFO L733 eck$LassoCheckResult]: Stem: 33020#[ULTIMATE.startENTRY]don't care [296] ULTIMATE.startENTRY-->L-1: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 33022#[L-1]don't care [276] L-1-->L-1-1: Formula: (and (= |v_#NULL.base_1| 0) (= |v_#NULL.offset_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] 33028#[L-1-1]don't care [304] L-1-1-->L-1-2: Formula: (= (select |v_#valid_8| 0) 0) InVars {#valid=|v_#valid_8|} OutVars{#valid=|v_#valid_8|} AuxVars[] AssignedVars[] 33030#[L-1-2]don't care [307] L-1-2-->L12: Formula: (< 0 |v_#StackHeapBarrier_1|) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|} AuxVars[] AssignedVars[] 32696#[L12]don't care [246] L12-->L12-1: Formula: (and (= 2 (select |v_#length_4| 1)) (= (select |v_#valid_9| 1) 1)) InVars {#length=|v_#length_4|, #valid=|v_#valid_9|} OutVars{#length=|v_#length_4|, #valid=|v_#valid_9|} AuxVars[] AssignedVars[] 32698#[L12-1]don't care [273] L12-1-->L12-2: Formula: (= (select (select |v_#memory_int_5| 1) 0) 48) InVars {#memory_int=|v_#memory_int_5|} OutVars{#memory_int=|v_#memory_int_5|} AuxVars[] AssignedVars[] 32746#[L12-2]don't care [271] L12-2-->L12-3: Formula: (= (select (select |v_#memory_int_6| 1) 1) 0) InVars {#memory_int=|v_#memory_int_6|} OutVars{#memory_int=|v_#memory_int_6|} AuxVars[] AssignedVars[] 31768#[L12-3]don't care [297] L12-3-->L12-4: Formula: (and (= (select |v_#valid_10| 2) 1) (= (select |v_#length_5| 2) 10)) InVars {#length=|v_#length_5|, #valid=|v_#valid_10|} OutVars{#length=|v_#length_5|, #valid=|v_#valid_10|} AuxVars[] AssignedVars[] 31770#[L12-4]don't care [285] L12-4-->L684: Formula: (= v_~x~0_7 0) InVars {} OutVars{~x~0=v_~x~0_7} AuxVars[] AssignedVars[~x~0] 32786#[L684]don't care [220] L684-->L685: Formula: (= v_~y~0_21 0) InVars {} OutVars{~y~0=v_~y~0_21} AuxVars[] AssignedVars[~y~0] 33402#[L685]don't care [245] L685-->L685-1: Formula: (= v_~b1~0_7 0) InVars {} OutVars{~b1~0=v_~b1~0_7} AuxVars[] AssignedVars[~b1~0] 33404#[L685-1]don't care [288] L685-1-->L686: Formula: (= v_~b2~0_7 0) InVars {} OutVars{~b2~0=v_~b2~0_7} AuxVars[] AssignedVars[~b2~0] 33424#[L686]don't care [321] L686-->L-1-3: Formula: (= v_~X~0_7 0) InVars {} OutVars{~X~0=v_~X~0_7} AuxVars[] AssignedVars[~X~0] 33312#[L-1-3]don't care [312] L-1-3-->L-1-4: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 31282#[L-1-4]don't care [284] L-1-4-->L-1-5: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 31284#[L-1-5]don't care [244] L-1-5-->L-1-6: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res#1=|v_ULTIMATE.start_main_#res#1_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res#1] 32380#[L-1-6]don't care [282] L-1-6-->L740: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_4|, ULTIMATE.start_main_#t~nondet4#1=|v_ULTIMATE.start_main_#t~nondet4#1_2|, ULTIMATE.start_main_#t~mem7#1=|v_ULTIMATE.start_main_#t~mem7#1_3|, ULTIMATE.start_main_#t~mem8#1=|v_ULTIMATE.start_main_#t~mem8#1_3|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_5|, ULTIMATE.start_main_#t~nondet6#1=|v_ULTIMATE.start_main_#t~nondet6#1_2|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_4|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_4|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_2|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_5|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre5#1, ULTIMATE.start_main_#t~nondet4#1, ULTIMATE.start_main_#t~mem7#1, ULTIMATE.start_main_#t~mem8#1, ULTIMATE.start_main_~#t2~0#1.offset, ULTIMATE.start_main_#t~nondet6#1, ULTIMATE.start_main_~#t1~0#1.base, ULTIMATE.start_main_~#t1~0#1.offset, ULTIMATE.start_main_#t~pre3#1, ULTIMATE.start_main_~#t2~0#1.base] 32382#[L740]don't care [286] L740-->L740-1: Formula: (and (= (select |v_#valid_12| |v_ULTIMATE.start_main_~#t1~0#1.base_5|) 0) (< |v_#StackHeapBarrier_2| |v_ULTIMATE.start_main_~#t1~0#1.base_5|) (= (store |v_#valid_12| |v_ULTIMATE.start_main_~#t1~0#1.base_5| 1) |v_#valid_11|) (not (= |v_ULTIMATE.start_main_~#t1~0#1.base_5| 0)) (= |v_#length_6| (store |v_#length_7| |v_ULTIMATE.start_main_~#t1~0#1.base_5| 4)) (= |v_ULTIMATE.start_main_~#t1~0#1.offset_5| 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_7|, #valid=|v_#valid_12|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_6|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_5|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_5|, #valid=|v_#valid_11|} AuxVars[] AssignedVars[#valid, #length, ULTIMATE.start_main_~#t1~0#1.base, ULTIMATE.start_main_~#t1~0#1.offset] 33196#[L740-1]don't care [293] L740-1-->L740-2: Formula: (and (= |v_#valid_13| (store |v_#valid_14| |v_ULTIMATE.start_main_~#t2~0#1.base_6| 1)) (not (= |v_ULTIMATE.start_main_~#t2~0#1.base_6| 0)) (= |v_#length_8| (store |v_#length_9| |v_ULTIMATE.start_main_~#t2~0#1.base_6| 4)) (< |v_#StackHeapBarrier_3| |v_ULTIMATE.start_main_~#t2~0#1.base_6|) (= (select |v_#valid_14| |v_ULTIMATE.start_main_~#t2~0#1.base_6|) 0) (= 0 |v_ULTIMATE.start_main_~#t2~0#1.offset_6|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_3|, #length=|v_#length_9|, #valid=|v_#valid_14|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_3|, #length=|v_#length_8|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_6|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_6|, #valid=|v_#valid_13|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2~0#1.offset, #valid, #length, ULTIMATE.start_main_~#t2~0#1.base] 33080#[L740-2]don't care [263] L740-2-->L741: Formula: (= |v_ULTIMATE.start_main_#t~pre3#1_3| |v_#pthreadsForks_4|) InVars {#pthreadsForks=|v_#pthreadsForks_4|} OutVars{#pthreadsForks=|v_#pthreadsForks_4|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre3#1] 31780#[L741]don't care [298] L741-->L741-1: Formula: (= (+ 1 |v_#pthreadsForks_6|) |v_#pthreadsForks_5|) InVars {#pthreadsForks=|v_#pthreadsForks_6|} OutVars{#pthreadsForks=|v_#pthreadsForks_5|} AuxVars[] AssignedVars[#pthreadsForks] 31782#[L741-1]don't care [294] L741-1-->L741-2: Formula: (and (<= 0 |v_ULTIMATE.start_main_~#t1~0#1.offset_6|) (<= (+ |v_ULTIMATE.start_main_~#t1~0#1.offset_6| 4) (select |v_#length_10| |v_ULTIMATE.start_main_~#t1~0#1.base_6|)) (= (store |v_#memory_int_8| |v_ULTIMATE.start_main_~#t1~0#1.base_6| (store (select |v_#memory_int_8| |v_ULTIMATE.start_main_~#t1~0#1.base_6|) |v_ULTIMATE.start_main_~#t1~0#1.offset_6| |v_ULTIMATE.start_main_#t~pre3#1_4|)) |v_#memory_int_7|) (= (select |v_#valid_15| |v_ULTIMATE.start_main_~#t1~0#1.base_6|) 1)) InVars {#valid=|v_#valid_15|, #memory_int=|v_#memory_int_8|, #length=|v_#length_10|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_6|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_6|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_4|} OutVars{#valid=|v_#valid_15|, #memory_int=|v_#memory_int_7|, #length=|v_#length_10|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_6|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_6|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_4|} AuxVars[] AssignedVars[#memory_int] 32976#[L741-2]don't care [401] L741-2-->thr1ENTRY: Formula: (and (= v_thr1Thread1of1ForFork1_thidvar1_2 0) (= |v_ULTIMATE.start_main_#t~pre3#1_6| v_thr1Thread1of1ForFork1_thidvar0_2) (= |v_thr1Thread1of1ForFork1_#in~_.base_4| 0) (= |v_thr1Thread1of1ForFork1_#in~_.offset_4| 0)) InVars {ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_6|} OutVars{thr1Thread1of1ForFork1_#in~_.offset=|v_thr1Thread1of1ForFork1_#in~_.offset_4|, thr1Thread1of1ForFork1_~_.base=v_thr1Thread1of1ForFork1_~_.base_4, thr1Thread1of1ForFork1_#res.base=|v_thr1Thread1of1ForFork1_#res.base_4|, thr1Thread1of1ForFork1_#in~_.base=|v_thr1Thread1of1ForFork1_#in~_.base_4|, thr1Thread1of1ForFork1_~_.offset=v_thr1Thread1of1ForFork1_~_.offset_4, thr1Thread1of1ForFork1_#res.offset=|v_thr1Thread1of1ForFork1_#res.offset_4|, thr1Thread1of1ForFork1_thidvar1=v_thr1Thread1of1ForFork1_thidvar1_2, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_6|, thr1Thread1of1ForFork1_thidvar0=v_thr1Thread1of1ForFork1_thidvar0_2} AuxVars[] AssignedVars[thr1Thread1of1ForFork1_#in~_.offset, thr1Thread1of1ForFork1_~_.base, thr1Thread1of1ForFork1_#res.base, thr1Thread1of1ForFork1_#in~_.base, thr1Thread1of1ForFork1_~_.offset, thr1Thread1of1ForFork1_#res.offset, thr1Thread1of1ForFork1_thidvar1, thr1Thread1of1ForFork1_thidvar0] 32978#[L741-3, thr1ENTRY]don't care [362] thr1ENTRY-->L688loopEntry: Formula: (and (= v_thr1Thread1of1ForFork1_~_.base_1 |v_thr1Thread1of1ForFork1_#in~_.base_1|) (= |v_thr1Thread1of1ForFork1_#in~_.offset_1| v_thr1Thread1of1ForFork1_~_.offset_1)) InVars {thr1Thread1of1ForFork1_#in~_.offset=|v_thr1Thread1of1ForFork1_#in~_.offset_1|, thr1Thread1of1ForFork1_#in~_.base=|v_thr1Thread1of1ForFork1_#in~_.base_1|} OutVars{thr1Thread1of1ForFork1_#in~_.offset=|v_thr1Thread1of1ForFork1_#in~_.offset_1|, thr1Thread1of1ForFork1_#in~_.base=|v_thr1Thread1of1ForFork1_#in~_.base_1|, thr1Thread1of1ForFork1_~_.offset=v_thr1Thread1of1ForFork1_~_.offset_1, thr1Thread1of1ForFork1_~_.base=v_thr1Thread1of1ForFork1_~_.base_1} AuxVars[] AssignedVars[thr1Thread1of1ForFork1_~_.base, thr1Thread1of1ForFork1_~_.offset] 33064#[L741-3, L688loopEntry]don't care [283] L741-3-->L741-4: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre3#1] 31022#[L741-4, L688loopEntry]don't care [363] L688loopEntry-->L701-3: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 31024#[L701-3, L741-4]don't care [366] L701-3-->L689: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 30978#[L689, L741-4]don't care [368] L689-->L690: Formula: (= v_~b1~0_3 1) InVars {} OutVars{~b1~0=v_~b1~0_3} AuxVars[] AssignedVars[~b1~0] 30980#[L690, L741-4]don't care [371] L690-->L691: Formula: (= v_~x~0_5 1) InVars {} OutVars{~x~0=v_~x~0_5} AuxVars[] AssignedVars[~x~0] 32534#[L691, L741-4]don't care [375] L691-->L696: Formula: (= v_~y~0_19 0) InVars {~y~0=v_~y~0_19} OutVars{~y~0=v_~y~0_19} AuxVars[] AssignedVars[] 33344#[L696, L741-4]don't care [379] L696-->L697: Formula: (= v_~y~0_20 1) InVars {} OutVars{~y~0=v_~y~0_20} AuxVars[] AssignedVars[~y~0] 33194#[L697, L741-4]don't care [239] L741-4-->L742: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet4#1=|v_ULTIMATE.start_main_#t~nondet4#1_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet4#1] 31290#[L742, L697]don't care [274] L742-->L742-1: Formula: (= |v_ULTIMATE.start_main_#t~pre5#1_1| |v_#pthreadsForks_1|) InVars {#pthreadsForks=|v_#pthreadsForks_1|} OutVars{ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_1|, #pthreadsForks=|v_#pthreadsForks_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre5#1] 31750#[L742-1, L697]don't care [278] L742-1-->L742-2: Formula: (= (+ 1 |v_#pthreadsForks_3|) |v_#pthreadsForks_2|) InVars {#pthreadsForks=|v_#pthreadsForks_3|} OutVars{#pthreadsForks=|v_#pthreadsForks_2|} AuxVars[] AssignedVars[#pthreadsForks] 32256#[L742-2, L697]don't care [238] L742-2-->L742-3: Formula: (and (= (select |v_#valid_1| |v_ULTIMATE.start_main_~#t2~0#1.base_1|) 1) (= (store |v_#memory_int_2| |v_ULTIMATE.start_main_~#t2~0#1.base_1| (store (select |v_#memory_int_2| |v_ULTIMATE.start_main_~#t2~0#1.base_1|) |v_ULTIMATE.start_main_~#t2~0#1.offset_1| |v_ULTIMATE.start_main_#t~pre5#1_2|)) |v_#memory_int_1|) (<= (+ 4 |v_ULTIMATE.start_main_~#t2~0#1.offset_1|) (select |v_#length_1| |v_ULTIMATE.start_main_~#t2~0#1.base_1|)) (<= 0 |v_ULTIMATE.start_main_~#t2~0#1.offset_1|)) InVars {ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_2|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_2|, #length=|v_#length_1|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_1|} OutVars{ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_2|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #length=|v_#length_1|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_1|} AuxVars[] AssignedVars[#memory_int] 32536#[L697, L742-3]don't care [398] L742-3-->thr2ENTRY: Formula: (and (= v_thr2Thread1of1ForFork0_thidvar2_2 0) (= |v_thr2Thread1of1ForFork0_#in~_.offset_4| 0) (= |v_thr2Thread1of1ForFork0_#in~_.base_4| 0) (= v_thr2Thread1of1ForFork0_thidvar1_2 0) (= |v_ULTIMATE.start_main_#t~pre5#1_6| v_thr2Thread1of1ForFork0_thidvar0_2)) InVars {ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_6|} OutVars{ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_6|, thr2Thread1of1ForFork0_~_.offset=v_thr2Thread1of1ForFork0_~_.offset_4, thr2Thread1of1ForFork0_#in~_.offset=|v_thr2Thread1of1ForFork0_#in~_.offset_4|, thr2Thread1of1ForFork0_#res.base=|v_thr2Thread1of1ForFork0_#res.base_4|, thr2Thread1of1ForFork0_thidvar0=v_thr2Thread1of1ForFork0_thidvar0_2, thr2Thread1of1ForFork0_thidvar1=v_thr2Thread1of1ForFork0_thidvar1_2, thr2Thread1of1ForFork0_thidvar2=v_thr2Thread1of1ForFork0_thidvar2_2, thr2Thread1of1ForFork0_#res.offset=|v_thr2Thread1of1ForFork0_#res.offset_4|, thr2Thread1of1ForFork0_#in~_.base=|v_thr2Thread1of1ForFork0_#in~_.base_4|, thr2Thread1of1ForFork0_~_.base=v_thr2Thread1of1ForFork0_~_.base_4} AuxVars[] AssignedVars[thr2Thread1of1ForFork0_~_.offset, thr2Thread1of1ForFork0_#in~_.offset, thr2Thread1of1ForFork0_#res.base, thr2Thread1of1ForFork0_thidvar0, thr2Thread1of1ForFork0_thidvar1, thr2Thread1of1ForFork0_thidvar2, thr2Thread1of1ForFork0_#res.offset, thr2Thread1of1ForFork0_#in~_.base, thr2Thread1of1ForFork0_~_.base] 32538#[L697, L742-4, thr2ENTRY]don't care [328] thr2ENTRY-->L714loopEntry: Formula: (and (= |v_thr2Thread1of1ForFork0_#in~_.base_1| v_thr2Thread1of1ForFork0_~_.base_1) (= v_thr2Thread1of1ForFork0_~_.offset_1 |v_thr2Thread1of1ForFork0_#in~_.offset_1|)) InVars {thr2Thread1of1ForFork0_#in~_.offset=|v_thr2Thread1of1ForFork0_#in~_.offset_1|, thr2Thread1of1ForFork0_#in~_.base=|v_thr2Thread1of1ForFork0_#in~_.base_1|} OutVars{thr2Thread1of1ForFork0_~_.offset=v_thr2Thread1of1ForFork0_~_.offset_1, thr2Thread1of1ForFork0_#in~_.offset=|v_thr2Thread1of1ForFork0_#in~_.offset_1|, thr2Thread1of1ForFork0_#in~_.base=|v_thr2Thread1of1ForFork0_#in~_.base_1|, thr2Thread1of1ForFork0_~_.base=v_thr2Thread1of1ForFork0_~_.base_1} AuxVars[] AssignedVars[thr2Thread1of1ForFork0_~_.offset, thr2Thread1of1ForFork0_~_.base] 31732#[L697, L742-4, L714loopEntry]don't care [329] L714loopEntry-->L727-3: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 31736#[L697, L742-4, L727-3]don't care [332] L727-3-->L715: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 32444#[L715, L697, L742-4]don't care [334] L715-->L716: Formula: (= v_~b2~0_1 1) InVars {} OutVars{~b2~0=v_~b2~0_1} AuxVars[] AssignedVars[~b2~0] 32236#[L716, L697, L742-4]don't care [337] L716-->L717: Formula: (= 2 v_~x~0_2) InVars {} OutVars{~x~0=v_~x~0_2} AuxVars[] AssignedVars[~x~0] 32238#[L697, L742-4, L717]don't care [384] L697-->L698: Formula: (not (= v_~x~0_6 1)) InVars {~x~0=v_~x~0_6} OutVars{~x~0=v_~x~0_6} AuxVars[] AssignedVars[] 33182#[L698, L742-4, L717]don't care [387] L698-->L699-2: Formula: (= v_~b1~0_6 0) InVars {} OutVars{~b1~0=v_~b1~0_6} AuxVars[] AssignedVars[~b1~0] 31396#[L742-4, L717, L699-2]don't care [2022-07-26 13:22:14,945 INFO L735 eck$LassoCheckResult]: Loop: 31396#[L742-4, L717, L699-2]don't care [390] L699-2-->L699-2: Formula: (<= 1 v_~b2~0_6) InVars {~b2~0=v_~b2~0_6} OutVars{~b2~0=v_~b2~0_6} AuxVars[] AssignedVars[] 31396#[L742-4, L717, L699-2]don't care [2022-07-26 13:22:14,945 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:14,945 INFO L85 PathProgramCache]: Analyzing trace with hash -1911550294, now seen corresponding path program 1 times [2022-07-26 13:22:14,945 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:14,946 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1799392168] [2022-07-26 13:22:14,946 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:14,946 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:14,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:14,981 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-26 13:22:14,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:15,011 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-26 13:22:15,011 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:15,012 INFO L85 PathProgramCache]: Analyzing trace with hash 421, now seen corresponding path program 2 times [2022-07-26 13:22:15,012 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:15,012 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1514790091] [2022-07-26 13:22:15,012 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:15,012 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:15,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:15,015 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-26 13:22:15,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:15,017 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-26 13:22:15,017 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:15,017 INFO L85 PathProgramCache]: Analyzing trace with hash 871483420, now seen corresponding path program 1 times [2022-07-26 13:22:15,018 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:15,018 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1750244751] [2022-07-26 13:22:15,018 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:15,018 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:15,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:15,049 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-26 13:22:15,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:15,070 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-26 13:22:16,078 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 26.07 01:22:16 BoogieIcfgContainer [2022-07-26 13:22:16,078 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-07-26 13:22:16,079 INFO L158 Benchmark]: Toolchain (without parser) took 4402.81ms. Allocated memory was 174.1MB in the beginning and 358.6MB in the end (delta: 184.5MB). Free memory was 115.0MB in the beginning and 280.8MB in the end (delta: -165.8MB). Peak memory consumption was 109.0MB. Max. memory is 8.0GB. [2022-07-26 13:22:16,079 INFO L158 Benchmark]: CDTParser took 0.10ms. Allocated memory is still 174.1MB. Free memory is still 132.5MB. There was no memory consumed. Max. memory is 8.0GB. [2022-07-26 13:22:16,079 INFO L158 Benchmark]: CACSL2BoogieTranslator took 466.09ms. Allocated memory was 174.1MB in the beginning and 237.0MB in the end (delta: 62.9MB). Free memory was 114.8MB in the beginning and 199.0MB in the end (delta: -84.2MB). Peak memory consumption was 9.4MB. Max. memory is 8.0GB. [2022-07-26 13:22:16,080 INFO L158 Benchmark]: Boogie Procedure Inliner took 44.38ms. Allocated memory is still 237.0MB. Free memory was 199.0MB in the beginning and 196.8MB in the end (delta: 2.2MB). Peak memory consumption was 2.1MB. Max. memory is 8.0GB. [2022-07-26 13:22:16,080 INFO L158 Benchmark]: Boogie Preprocessor took 24.13ms. Allocated memory is still 237.0MB. Free memory was 196.8MB in the beginning and 195.3MB in the end (delta: 1.4MB). Peak memory consumption was 1.0MB. Max. memory is 8.0GB. [2022-07-26 13:22:16,081 INFO L158 Benchmark]: RCFGBuilder took 355.66ms. Allocated memory is still 237.0MB. Free memory was 195.3MB in the beginning and 181.7MB in the end (delta: 13.6MB). Peak memory consumption was 13.6MB. Max. memory is 8.0GB. [2022-07-26 13:22:16,081 INFO L158 Benchmark]: BuchiAutomizer took 3505.94ms. Allocated memory was 237.0MB in the beginning and 358.6MB in the end (delta: 121.6MB). Free memory was 181.2MB in the beginning and 280.8MB in the end (delta: -99.6MB). Peak memory consumption was 112.7MB. Max. memory is 8.0GB. [2022-07-26 13:22:16,083 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.10ms. Allocated memory is still 174.1MB. Free memory is still 132.5MB. There was no memory consumed. Max. memory is 8.0GB. * CACSL2BoogieTranslator took 466.09ms. Allocated memory was 174.1MB in the beginning and 237.0MB in the end (delta: 62.9MB). Free memory was 114.8MB in the beginning and 199.0MB in the end (delta: -84.2MB). Peak memory consumption was 9.4MB. Max. memory is 8.0GB. * Boogie Procedure Inliner took 44.38ms. Allocated memory is still 237.0MB. Free memory was 199.0MB in the beginning and 196.8MB in the end (delta: 2.2MB). Peak memory consumption was 2.1MB. Max. memory is 8.0GB. * Boogie Preprocessor took 24.13ms. Allocated memory is still 237.0MB. Free memory was 196.8MB in the beginning and 195.3MB in the end (delta: 1.4MB). Peak memory consumption was 1.0MB. Max. memory is 8.0GB. * RCFGBuilder took 355.66ms. Allocated memory is still 237.0MB. Free memory was 195.3MB in the beginning and 181.7MB in the end (delta: 13.6MB). Peak memory consumption was 13.6MB. Max. memory is 8.0GB. * BuchiAutomizer took 3505.94ms. Allocated memory was 237.0MB in the beginning and 358.6MB in the end (delta: 121.6MB). Free memory was 181.2MB in the beginning and 280.8MB in the end (delta: -99.6MB). Peak memory consumption was 112.7MB. Max. memory is 8.0GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 5 terminating modules (5 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.5 modules have a trivial ranking function, the largest among these consists of 3 locations. The remainder module has 1401 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 3.3s and 6 iterations. TraceHistogramMax:1. Analysis of lassos took 1.7s. Construction of modules took 0.0s. Büchi inclusion checks took 0.9s. Highest rank in rank-based complementation 0. Minimization of det autom 5. Minimization of nondet autom 0. Automata minimization 0.5s AutomataMinimizationTime, 5 MinimizatonAttempts, 611 StatesRemovedByMinimization, 2 NontrivialMinimizations. Non-live state removal took 0.2s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 188 SdHoareTripleChecker+Valid, 0.1s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 188 mSDsluCounter, 775 SdHoareTripleChecker+Invalid, 0.1s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 267 mSDsCounter, 22 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 87 IncrementalHoareTripleChecker+Invalid, 109 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 22 mSolverCounterUnsat, 519 mSDtfsCounter, 87 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI2 SFLT0 conc0 concLT0 SILN3 SILU0 SILI0 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.1s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 699]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {\result={0:0}, \result=0, \result={0:0}, _={0:0}, _={0:0}, _={0:0}, _={0:0}, b1=0, b2=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@22eb36a3 in0,51998, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6a6f2dc1 in0,0, org.eclipse.cdt.internal.core.dom.parser.c.CASTIdExpression@61ee0da0=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTIdExpression@6200c9e4=0, t1={9797:0}, t2={3:0}, x=2, X=0, y=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 699]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L684] 0 int x, y; [L685] 0 int b1, b2; [L686] 0 int X; [L740] 0 pthread_t t1, t2; [L741] FCALL, FORK 0 pthread_create(&t1, 0, thr1, 0) [L688] COND TRUE 1 1 [L689] 1 b1 = 1 [L690] 1 x = 1 [L691] COND FALSE 1 !(y != 0) [L696] 1 y = 1 [L742] FCALL, FORK 0 pthread_create(&t2, 0, thr2, 0) [L714] COND TRUE 2 1 [L715] 2 b2 = 1 [L716] 2 x = 2 [L697] COND TRUE 1 x != 1 [L698] 1 b1 = 0 Loop: [L699] COND TRUE b2 >= 1 End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-07-26 13:22:16,144 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request...