/usr/bin/java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/BuchiAutomizerCInline.xml -s ../../../trunk/examples/settings/buchiAutomizer/concurrent-automaton-noLbe.epf -i ../../../trunk/examples/svcomp/pthread-atomic/lamport.i -------------------------------------------------------------------------------- This is Ultimate 0.2.2-dev-0d686a6 [2022-07-26 13:22:10,838 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-07-26 13:22:10,840 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-07-26 13:22:10,869 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... 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[2022-07-26 13:22:10,915 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-07-26 13:22:10,920 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-07-26 13:22:10,923 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-07-26 13:22:10,923 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/buchiAutomizer/concurrent-automaton-noLbe.epf [2022-07-26 13:22:10,959 INFO L113 SettingsManager]: Loading preferences was successful [2022-07-26 13:22:10,960 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-07-26 13:22:10,960 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-07-26 13:22:10,960 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-07-26 13:22:10,961 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-07-26 13:22:10,961 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-07-26 13:22:10,961 INFO L138 SettingsManager]: * Use SBE=true [2022-07-26 13:22:10,961 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-07-26 13:22:10,962 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-07-26 13:22:10,962 INFO L138 SettingsManager]: * Use old map elimination=false [2022-07-26 13:22:10,962 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-07-26 13:22:10,963 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-07-26 13:22:10,963 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-07-26 13:22:10,963 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-07-26 13:22:10,963 INFO L138 SettingsManager]: * sizeof long=4 [2022-07-26 13:22:10,963 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-07-26 13:22:10,963 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-07-26 13:22:10,963 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-07-26 13:22:10,963 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-07-26 13:22:10,964 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-07-26 13:22:10,964 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-07-26 13:22:10,964 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-07-26 13:22:10,964 INFO L138 SettingsManager]: * sizeof long double=12 [2022-07-26 13:22:10,964 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-07-26 13:22:10,964 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-07-26 13:22:10,964 INFO L138 SettingsManager]: * Use constant arrays=true [2022-07-26 13:22:10,965 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-07-26 13:22:10,965 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-07-26 13:22:10,965 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-07-26 13:22:10,965 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-07-26 13:22:10,965 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-07-26 13:22:10,965 INFO L138 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2022-07-26 13:22:10,966 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-07-26 13:22:10,966 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release [2022-07-26 13:22:11,146 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-07-26 13:22:11,168 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-07-26 13:22:11,172 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-07-26 13:22:11,173 INFO L271 PluginConnector]: Initializing CDTParser... [2022-07-26 13:22:11,174 INFO L275 PluginConnector]: CDTParser initialized [2022-07-26 13:22:11,175 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/pthread-atomic/lamport.i [2022-07-26 13:22:11,247 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/521ef7d3d/f51fdc0cc91a4734b0672345b127222f/FLAG882957e04 [2022-07-26 13:22:11,643 INFO L306 CDTParser]: Found 1 translation units. [2022-07-26 13:22:11,643 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/pthread-atomic/lamport.i [2022-07-26 13:22:11,669 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/521ef7d3d/f51fdc0cc91a4734b0672345b127222f/FLAG882957e04 [2022-07-26 13:22:11,680 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/521ef7d3d/f51fdc0cc91a4734b0672345b127222f [2022-07-26 13:22:11,682 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-07-26 13:22:11,684 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2022-07-26 13:22:11,685 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-07-26 13:22:11,685 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-07-26 13:22:11,695 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-07-26 13:22:11,696 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.07 01:22:11" (1/1) ... [2022-07-26 13:22:11,697 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@34be3385 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.07 01:22:11, skipping insertion in model container [2022-07-26 13:22:11,697 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.07 01:22:11" (1/1) ... [2022-07-26 13:22:11,703 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-07-26 13:22:11,739 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-07-26 13:22:11,968 WARN L611 FunctionHandler]: implicit declaration of function __builtin_bswap16 [2022-07-26 13:22:12,121 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/pthread-atomic/lamport.i[32156,32169] [2022-07-26 13:22:12,129 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/pthread-atomic/lamport.i[34083,34096] [2022-07-26 13:22:12,137 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-26 13:22:12,148 INFO L203 MainTranslator]: Completed pre-run [2022-07-26 13:22:12,171 WARN L611 FunctionHandler]: implicit declaration of function __builtin_bswap16 [2022-07-26 13:22:12,196 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/pthread-atomic/lamport.i[32156,32169] [2022-07-26 13:22:12,199 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/pthread-atomic/lamport.i[34083,34096] [2022-07-26 13:22:12,202 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-26 13:22:12,239 INFO L208 MainTranslator]: Completed translation [2022-07-26 13:22:12,239 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.07 01:22:12 WrapperNode [2022-07-26 13:22:12,239 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-07-26 13:22:12,240 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-07-26 13:22:12,240 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-07-26 13:22:12,241 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-07-26 13:22:12,247 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.07 01:22:12" (1/1) ... [2022-07-26 13:22:12,275 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.07 01:22:12" (1/1) ... [2022-07-26 13:22:12,295 INFO L137 Inliner]: procedures = 171, calls = 83, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 44 [2022-07-26 13:22:12,295 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-07-26 13:22:12,296 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-07-26 13:22:12,296 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-07-26 13:22:12,297 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-07-26 13:22:12,304 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.07 01:22:12" (1/1) ... [2022-07-26 13:22:12,304 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.07 01:22:12" (1/1) ... [2022-07-26 13:22:12,317 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.07 01:22:12" (1/1) ... [2022-07-26 13:22:12,318 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.07 01:22:12" (1/1) ... [2022-07-26 13:22:12,323 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.07 01:22:12" (1/1) ... [2022-07-26 13:22:12,328 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.07 01:22:12" (1/1) ... [2022-07-26 13:22:12,330 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.07 01:22:12" (1/1) ... [2022-07-26 13:22:12,332 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-07-26 13:22:12,333 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-07-26 13:22:12,333 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-07-26 13:22:12,333 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-07-26 13:22:12,340 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.07 01:22:12" (1/1) ... [2022-07-26 13:22:12,348 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-26 13:22:12,358 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-26 13:22:12,370 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-26 13:22:12,377 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-07-26 13:22:12,406 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-07-26 13:22:12,407 INFO L130 BoogieDeclarations]: Found specification of procedure thr2 [2022-07-26 13:22:12,407 INFO L138 BoogieDeclarations]: Found implementation of procedure thr2 [2022-07-26 13:22:12,407 INFO L130 BoogieDeclarations]: Found specification of procedure thr1 [2022-07-26 13:22:12,407 INFO L138 BoogieDeclarations]: Found implementation of procedure thr1 [2022-07-26 13:22:12,407 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-07-26 13:22:12,407 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2022-07-26 13:22:12,407 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-07-26 13:22:12,408 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-07-26 13:22:12,408 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-07-26 13:22:12,408 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-07-26 13:22:12,408 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2022-07-26 13:22:12,408 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-07-26 13:22:12,408 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-07-26 13:22:12,409 WARN L208 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2022-07-26 13:22:12,498 INFO L234 CfgBuilder]: Building ICFG [2022-07-26 13:22:12,499 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-07-26 13:22:12,742 INFO L275 CfgBuilder]: Performing block encoding [2022-07-26 13:22:12,750 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-07-26 13:22:12,750 INFO L299 CfgBuilder]: Removed 8 assume(true) statements. [2022-07-26 13:22:12,752 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.07 01:22:12 BoogieIcfgContainer [2022-07-26 13:22:12,752 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-07-26 13:22:12,753 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-07-26 13:22:12,753 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-07-26 13:22:12,757 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-07-26 13:22:12,757 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-26 13:22:12,757 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 26.07 01:22:11" (1/3) ... [2022-07-26 13:22:12,758 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@10eb32af and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.07 01:22:12, skipping insertion in model container [2022-07-26 13:22:12,758 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-26 13:22:12,758 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.07 01:22:12" (2/3) ... [2022-07-26 13:22:12,759 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@10eb32af and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.07 01:22:12, skipping insertion in model container [2022-07-26 13:22:12,759 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-26 13:22:12,759 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.07 01:22:12" (3/3) ... [2022-07-26 13:22:12,760 INFO L322 chiAutomizerObserver]: Analyzing ICFG lamport.i [2022-07-26 13:22:12,834 INFO L144 ThreadInstanceAdder]: Constructed 2 joinOtherThreadTransitions. [2022-07-26 13:22:12,860 INFO L74 FinitePrefix]: Start finitePrefix. Operand has 114 places, 133 transitions, 282 flow [2022-07-26 13:22:12,900 INFO L129 PetriNetUnfolder]: 24/129 cut-off events. [2022-07-26 13:22:12,901 INFO L130 PetriNetUnfolder]: For 2/2 co-relation queries the response was YES. [2022-07-26 13:22:12,908 INFO L84 FinitePrefix]: Finished finitePrefix Result has 138 conditions, 129 events. 24/129 cut-off events. For 2/2 co-relation queries the response was YES. Maximal size of possible extension queue 6. Compared 243 event pairs, 0 based on Foata normal form. 0/105 useless extension candidates. Maximal degree in co-relation 95. Up to 5 conditions per place. [2022-07-26 13:22:12,908 INFO L82 GeneralOperation]: Start removeDead. Operand has 114 places, 133 transitions, 282 flow [2022-07-26 13:22:12,916 INFO L88 GeneralOperation]: Finished RemoveDead, result has has 112 places, 129 transitions, 270 flow [2022-07-26 13:22:12,928 INFO L301 stractBuchiCegarLoop]: Interprodecural is true [2022-07-26 13:22:12,928 INFO L302 stractBuchiCegarLoop]: Hoare is false [2022-07-26 13:22:12,928 INFO L303 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-07-26 13:22:12,928 INFO L304 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-07-26 13:22:12,928 INFO L305 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-07-26 13:22:12,929 INFO L306 stractBuchiCegarLoop]: Difference is false [2022-07-26 13:22:12,929 INFO L307 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-07-26 13:22:12,929 INFO L311 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-07-26 13:22:12,931 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand currently 0 states, but on-demand construction may add more states [2022-07-26 13:22:13,331 INFO L131 ngComponentsAnalysis]: Automaton has 93 accepting balls. 3633 [2022-07-26 13:22:13,332 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-26 13:22:13,332 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-26 13:22:13,338 INFO L150 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-26 13:22:13,339 INFO L151 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2022-07-26 13:22:13,339 INFO L333 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-07-26 13:22:13,339 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand currently 4155 states, but on-demand construction may add more states [2022-07-26 13:22:13,419 INFO L131 ngComponentsAnalysis]: Automaton has 93 accepting balls. 3633 [2022-07-26 13:22:13,419 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-26 13:22:13,419 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-26 13:22:13,421 INFO L150 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-26 13:22:13,421 INFO L151 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2022-07-26 13:22:13,430 INFO L733 eck$LassoCheckResult]: Stem: 117#[ULTIMATE.startENTRY]don't care [341] ULTIMATE.startENTRY-->L-1: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 120#[L-1]don't care [266] L-1-->L-1-1: Formula: (and (= |v_#NULL.base_1| 0) (= |v_#NULL.offset_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] 122#[L-1-1]don't care [350] L-1-1-->L-1-2: Formula: (= 0 (select |v_#valid_13| 0)) InVars {#valid=|v_#valid_13|} OutVars{#valid=|v_#valid_13|} AuxVars[] AssignedVars[] 124#[L-1-2]don't care [352] L-1-2-->L12: Formula: (< 0 |v_#StackHeapBarrier_3|) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_3|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_3|} AuxVars[] AssignedVars[] 126#[L12]don't care [305] L12-->L12-1: Formula: (and (= (select |v_#length_9| 1) 2) (= (select |v_#valid_14| 1) 1)) InVars {#length=|v_#length_9|, #valid=|v_#valid_14|} OutVars{#length=|v_#length_9|, #valid=|v_#valid_14|} AuxVars[] AssignedVars[] 128#[L12-1]don't care [320] L12-1-->L12-2: Formula: (= (select (select |v_#memory_int_7| 1) 0) 48) InVars {#memory_int=|v_#memory_int_7|} OutVars{#memory_int=|v_#memory_int_7|} AuxVars[] AssignedVars[] 130#[L12-2]don't care [319] L12-2-->L12-3: Formula: (= (select (select |v_#memory_int_8| 1) 1) 0) InVars {#memory_int=|v_#memory_int_8|} OutVars{#memory_int=|v_#memory_int_8|} AuxVars[] AssignedVars[] 132#[L12-3]don't care [343] L12-3-->L12-4: Formula: (and (= (select |v_#length_10| 2) 10) (= (select |v_#valid_15| 2) 1)) InVars {#length=|v_#length_10|, #valid=|v_#valid_15|} OutVars{#length=|v_#length_10|, #valid=|v_#valid_15|} AuxVars[] AssignedVars[] 134#[L12-4]don't care [336] L12-4-->L700: Formula: (= v_~x~0_5 0) InVars {} OutVars{~x~0=v_~x~0_5} AuxVars[] AssignedVars[~x~0] 136#[L700]don't care [280] L700-->L701: Formula: (= v_~y~0_17 0) InVars {} OutVars{~y~0=v_~y~0_17} AuxVars[] AssignedVars[~y~0] 138#[L701]don't care [348] L701-->L701-1: Formula: (= v_~b1~0_7 0) InVars {} OutVars{~b1~0=v_~b1~0_7} AuxVars[] AssignedVars[~b1~0] 140#[L701-1]don't care [247] L701-1-->L702: Formula: (= v_~b2~0_7 0) InVars {} OutVars{~b2~0=v_~b2~0_7} AuxVars[] AssignedVars[~b2~0] 142#[L702]don't care [251] L702-->L-1-3: Formula: (= v_~X~0_7 0) InVars {} OutVars{~X~0=v_~X~0_7} AuxVars[] AssignedVars[~X~0] 144#[L-1-3]don't care [353] L-1-3-->L-1-4: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 146#[L-1-4]don't care [272] L-1-4-->L-1-5: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 148#[L-1-5]don't care [242] L-1-5-->L-1-6: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res#1=|v_ULTIMATE.start_main_#res#1_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res#1] 150#[L-1-6]don't care [335] L-1-6-->L844: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~pre6#1=|v_ULTIMATE.start_main_#t~pre6#1_1|, ULTIMATE.start_main_#t~mem8#1=|v_ULTIMATE.start_main_#t~mem8#1_1|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_1|, ULTIMATE.start_main_#t~nondet5#1=|v_ULTIMATE.start_main_#t~nondet5#1_1|, ULTIMATE.start_main_#t~nondet7#1=|v_ULTIMATE.start_main_#t~nondet7#1_1|, ULTIMATE.start_main_#t~mem9#1=|v_ULTIMATE.start_main_#t~mem9#1_1|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_1|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_1|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_1|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre6#1, ULTIMATE.start_main_#t~mem8#1, ULTIMATE.start_main_~#t2~0#1.offset, ULTIMATE.start_main_#t~nondet5#1, ULTIMATE.start_main_#t~nondet7#1, ULTIMATE.start_main_#t~mem9#1, ULTIMATE.start_main_~#t1~0#1.base, ULTIMATE.start_main_#t~pre4#1, ULTIMATE.start_main_~#t1~0#1.offset, ULTIMATE.start_main_~#t2~0#1.base] 152#[L844]don't care [293] L844-->L844-1: Formula: (and (= (store |v_#valid_2| |v_ULTIMATE.start_main_~#t1~0#1.base_2| 1) |v_#valid_1|) (= |v_ULTIMATE.start_main_~#t1~0#1.offset_2| 0) (= (select |v_#valid_2| |v_ULTIMATE.start_main_~#t1~0#1.base_2|) 0) (< |v_#StackHeapBarrier_1| |v_ULTIMATE.start_main_~#t1~0#1.base_2|) (= (store |v_#length_2| |v_ULTIMATE.start_main_~#t1~0#1.base_2| 4) |v_#length_1|) (not (= |v_ULTIMATE.start_main_~#t1~0#1.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_2|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_2|, #valid=|v_#valid_1|} AuxVars[] AssignedVars[#valid, #length, ULTIMATE.start_main_~#t1~0#1.base, ULTIMATE.start_main_~#t1~0#1.offset] 154#[L844-1]don't care [279] L844-1-->L844-2: Formula: (and (< |v_#StackHeapBarrier_2| |v_ULTIMATE.start_main_~#t2~0#1.base_2|) (not (= |v_ULTIMATE.start_main_~#t2~0#1.base_2| 0)) (= |v_#length_3| (store |v_#length_4| |v_ULTIMATE.start_main_~#t2~0#1.base_2| 4)) (= 0 |v_ULTIMATE.start_main_~#t2~0#1.offset_2|) (= (store |v_#valid_4| |v_ULTIMATE.start_main_~#t2~0#1.base_2| 1) |v_#valid_3|) (= (select |v_#valid_4| |v_ULTIMATE.start_main_~#t2~0#1.base_2|) 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_4|, #valid=|v_#valid_4|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_2|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_2|, #valid=|v_#valid_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2~0#1.offset, #valid, #length, ULTIMATE.start_main_~#t2~0#1.base] 156#[L844-2]don't care [313] L844-2-->L845: Formula: (= |v_ULTIMATE.start_main_#t~pre4#1_2| |v_#pthreadsForks_1|) InVars {#pthreadsForks=|v_#pthreadsForks_1|} OutVars{#pthreadsForks=|v_#pthreadsForks_1|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre4#1] 158#[L845]don't care [340] L845-->L845-1: Formula: (= (+ 1 |v_#pthreadsForks_3|) |v_#pthreadsForks_2|) InVars {#pthreadsForks=|v_#pthreadsForks_3|} OutVars{#pthreadsForks=|v_#pthreadsForks_2|} AuxVars[] AssignedVars[#pthreadsForks] 160#[L845-1]don't care [244] L845-1-->L845-2: Formula: (and (<= 0 |v_ULTIMATE.start_main_~#t1~0#1.offset_3|) (= (select |v_#valid_5| |v_ULTIMATE.start_main_~#t1~0#1.base_3|) 1) (= (store |v_#memory_int_2| |v_ULTIMATE.start_main_~#t1~0#1.base_3| (store (select |v_#memory_int_2| |v_ULTIMATE.start_main_~#t1~0#1.base_3|) |v_ULTIMATE.start_main_~#t1~0#1.offset_3| |v_ULTIMATE.start_main_#t~pre4#1_3|)) |v_#memory_int_1|) (<= (+ |v_ULTIMATE.start_main_~#t1~0#1.offset_3| 4) (select |v_#length_5| |v_ULTIMATE.start_main_~#t1~0#1.base_3|))) InVars {#valid=|v_#valid_5|, #memory_int=|v_#memory_int_2|, #length=|v_#length_5|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_3|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_3|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_3|} OutVars{#valid=|v_#valid_5|, #memory_int=|v_#memory_int_1|, #length=|v_#length_5|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_3|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_3|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_3|} AuxVars[] AssignedVars[#memory_int] 162#[L845-2]don't care [449] L845-2-->thr1ENTRY: Formula: (and (= v_thr1Thread1of1ForFork1_thidvar1_2 0) (= |v_ULTIMATE.start_main_#t~pre4#1_6| v_thr1Thread1of1ForFork1_thidvar0_2) (= |v_thr1Thread1of1ForFork1_#in~_.base_4| 0) (= |v_thr1Thread1of1ForFork1_#in~_.offset_4| 0)) InVars {ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_6|} OutVars{thr1Thread1of1ForFork1_#in~_.offset=|v_thr1Thread1of1ForFork1_#in~_.offset_4|, thr1Thread1of1ForFork1_~_.base=v_thr1Thread1of1ForFork1_~_.base_4, thr1Thread1of1ForFork1_~b21~0=v_thr1Thread1of1ForFork1_~b21~0_10, thr1Thread1of1ForFork1_#res.base=|v_thr1Thread1of1ForFork1_#res.base_4|, thr1Thread1of1ForFork1_~y1~0=v_thr1Thread1of1ForFork1_~y1~0_30, thr1Thread1of1ForFork1_#in~_.base=|v_thr1Thread1of1ForFork1_#in~_.base_4|, thr1Thread1of1ForFork1_~_.offset=v_thr1Thread1of1ForFork1_~_.offset_4, thr1Thread1of1ForFork1_#res.offset=|v_thr1Thread1of1ForFork1_#res.offset_4|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_6|, thr1Thread1of1ForFork1_thidvar1=v_thr1Thread1of1ForFork1_thidvar1_2, thr1Thread1of1ForFork1_thidvar0=v_thr1Thread1of1ForFork1_thidvar0_2, thr1Thread1of1ForFork1_~x1~0=v_thr1Thread1of1ForFork1_~x1~0_8} AuxVars[] AssignedVars[thr1Thread1of1ForFork1_#in~_.offset, thr1Thread1of1ForFork1_~_.base, thr1Thread1of1ForFork1_~b21~0, thr1Thread1of1ForFork1_#res.base, thr1Thread1of1ForFork1_~y1~0, thr1Thread1of1ForFork1_#in~_.base, thr1Thread1of1ForFork1_~_.offset, thr1Thread1of1ForFork1_#res.offset, thr1Thread1of1ForFork1_thidvar1, thr1Thread1of1ForFork1_thidvar0, thr1Thread1of1ForFork1_~x1~0] 164#[thr1ENTRY, L845-3]don't care [402] thr1ENTRY-->L704loopEntry: Formula: (and (= v_thr1Thread1of1ForFork1_~_.base_1 |v_thr1Thread1of1ForFork1_#in~_.base_1|) (= |v_thr1Thread1of1ForFork1_#in~_.offset_1| v_thr1Thread1of1ForFork1_~_.offset_1)) InVars {thr1Thread1of1ForFork1_#in~_.offset=|v_thr1Thread1of1ForFork1_#in~_.offset_1|, thr1Thread1of1ForFork1_#in~_.base=|v_thr1Thread1of1ForFork1_#in~_.base_1|} OutVars{thr1Thread1of1ForFork1_#in~_.offset=|v_thr1Thread1of1ForFork1_#in~_.offset_1|, thr1Thread1of1ForFork1_#in~_.base=|v_thr1Thread1of1ForFork1_#in~_.base_1|, thr1Thread1of1ForFork1_~_.offset=v_thr1Thread1of1ForFork1_~_.offset_1, thr1Thread1of1ForFork1_~_.base=v_thr1Thread1of1ForFork1_~_.base_1} AuxVars[] AssignedVars[thr1Thread1of1ForFork1_~_.base, thr1Thread1of1ForFork1_~_.offset] 166#[L704loopEntry, L845-3]don't care [403] L704loopEntry-->L753-1: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 170#[L753-1, L845-3]don't care [2022-07-26 13:22:13,434 INFO L735 eck$LassoCheckResult]: Loop: 170#[L753-1, L845-3]don't care [406] L753-1-->L705: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 178#[L845-3, L705]don't care [408] L705-->L707: Formula: (= v_~b1~0_4 1) InVars {} OutVars{~b1~0=v_~b1~0_4} AuxVars[] AssignedVars[~b1~0] 192#[L845-3, L707]don't care [411] L707-->L710: Formula: (= v_~x~0_3 1) InVars {} OutVars{~x~0=v_~x~0_3} AuxVars[] AssignedVars[~x~0] 212#[L710, L845-3]don't care [414] L710-->L713: Formula: (= v_~y~0_12 v_thr1Thread1of1ForFork1_~y1~0_1) InVars {~y~0=v_~y~0_12} OutVars{~y~0=v_~y~0_12, thr1Thread1of1ForFork1_~y1~0=v_thr1Thread1of1ForFork1_~y1~0_1} AuxVars[] AssignedVars[thr1Thread1of1ForFork1_~y1~0] 236#[L845-3, L713]don't care [416] L713-->L715: Formula: (not (= v_thr1Thread1of1ForFork1_~y1~0_3 0)) InVars {thr1Thread1of1ForFork1_~y1~0=v_thr1Thread1of1ForFork1_~y1~0_3} OutVars{thr1Thread1of1ForFork1_~y1~0=v_thr1Thread1of1ForFork1_~y1~0_3} AuxVars[] AssignedVars[] 264#[L845-3, L715]don't care [419] L715-->L717: Formula: (= v_~b1~0_5 0) InVars {} OutVars{~b1~0=v_~b1~0_5} AuxVars[] AssignedVars[~b1~0] 302#[L845-3, L717]don't care [422] L717-->L724: Formula: (= v_~y~0_13 v_thr1Thread1of1ForFork1_~y1~0_7) InVars {~y~0=v_~y~0_13} OutVars{~y~0=v_~y~0_13, thr1Thread1of1ForFork1_~y1~0=v_thr1Thread1of1ForFork1_~y1~0_7} AuxVars[] AssignedVars[thr1Thread1of1ForFork1_~y1~0] 352#[L845-3, L724]don't care [424] L724-->L753-1: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] 170#[L753-1, L845-3]don't care [2022-07-26 13:22:13,441 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:13,442 INFO L85 PathProgramCache]: Analyzing trace with hash -2049050784, now seen corresponding path program 1 times [2022-07-26 13:22:13,450 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:13,450 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1606394533] [2022-07-26 13:22:13,451 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:13,453 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:13,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:13,547 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-26 13:22:13,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:13,586 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-26 13:22:13,589 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:13,589 INFO L85 PathProgramCache]: Analyzing trace with hash 1999980075, now seen corresponding path program 1 times [2022-07-26 13:22:13,589 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:13,590 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2013781931] [2022-07-26 13:22:13,590 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:13,590 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:13,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-26 13:22:13,639 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-26 13:22:13,639 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-26 13:22:13,640 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2013781931] [2022-07-26 13:22:13,640 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2013781931] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-26 13:22:13,640 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-26 13:22:13,641 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2022-07-26 13:22:13,641 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1156117708] [2022-07-26 13:22:13,641 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-26 13:22:13,648 INFO L750 eck$LassoCheckResult]: loop already infeasible [2022-07-26 13:22:13,648 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-26 13:22:13,675 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-07-26 13:22:13,676 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-07-26 13:22:13,678 INFO L87 Difference]: Start difference. First operand currently 4155 states, but on-demand construction may add more states Second operand has 2 states, 1 states have (on average 8.0) internal successors, (8), 2 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-26 13:22:13,780 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-26 13:22:13,780 INFO L93 Difference]: Finished difference Result 4156 states and 12447 transitions. [2022-07-26 13:22:13,782 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4156 states and 12447 transitions. [2022-07-26 13:22:13,834 INFO L131 ngComponentsAnalysis]: Automaton has 93 accepting balls. 3633 [2022-07-26 13:22:13,891 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4156 states to 3866 states and 11618 transitions. [2022-07-26 13:22:13,893 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3866 [2022-07-26 13:22:13,903 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3866 [2022-07-26 13:22:13,904 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3866 states and 11618 transitions. [2022-07-26 13:22:13,928 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-26 13:22:13,929 INFO L220 hiAutomatonCegarLoop]: Abstraction has 3866 states and 11618 transitions. [2022-07-26 13:22:13,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3866 states and 11618 transitions. [2022-07-26 13:22:14,096 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3866 to 3866. [2022-07-26 13:22:14,112 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3866 states, 3866 states have (on average 3.0051733057423693) internal successors, (11618), 3865 states have internal predecessors, (11618), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-26 13:22:14,132 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3866 states to 3866 states and 11618 transitions. [2022-07-26 13:22:14,133 INFO L242 hiAutomatonCegarLoop]: Abstraction has 3866 states and 11618 transitions. [2022-07-26 13:22:14,134 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-07-26 13:22:14,140 INFO L426 stractBuchiCegarLoop]: Abstraction has 3866 states and 11618 transitions. [2022-07-26 13:22:14,140 INFO L333 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-07-26 13:22:14,140 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3866 states and 11618 transitions. [2022-07-26 13:22:14,168 INFO L131 ngComponentsAnalysis]: Automaton has 93 accepting balls. 3633 [2022-07-26 13:22:14,168 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-26 13:22:14,169 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-26 13:22:14,170 INFO L150 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-26 13:22:14,171 INFO L151 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2022-07-26 13:22:14,174 INFO L733 eck$LassoCheckResult]: Stem: 20163#[ULTIMATE.startENTRY]don't care [341] ULTIMATE.startENTRY-->L-1: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 20165#[L-1]don't care [266] L-1-->L-1-1: Formula: (and (= |v_#NULL.base_1| 0) (= |v_#NULL.offset_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] 15741#[L-1-1]don't care [350] L-1-1-->L-1-2: Formula: (= 0 (select |v_#valid_13| 0)) InVars {#valid=|v_#valid_13|} OutVars{#valid=|v_#valid_13|} AuxVars[] AssignedVars[] 15743#[L-1-2]don't care [352] L-1-2-->L12: Formula: (< 0 |v_#StackHeapBarrier_3|) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_3|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_3|} AuxVars[] AssignedVars[] 20285#[L12]don't care [305] L12-->L12-1: Formula: (and (= (select |v_#length_9| 1) 2) (= (select |v_#valid_14| 1) 1)) InVars {#length=|v_#length_9|, #valid=|v_#valid_14|} OutVars{#length=|v_#length_9|, #valid=|v_#valid_14|} AuxVars[] AssignedVars[] 18653#[L12-1]don't care [320] L12-1-->L12-2: Formula: (= (select (select |v_#memory_int_7| 1) 0) 48) InVars {#memory_int=|v_#memory_int_7|} OutVars{#memory_int=|v_#memory_int_7|} AuxVars[] AssignedVars[] 18655#[L12-2]don't care [319] L12-2-->L12-3: Formula: (= (select (select |v_#memory_int_8| 1) 1) 0) InVars {#memory_int=|v_#memory_int_8|} OutVars{#memory_int=|v_#memory_int_8|} AuxVars[] AssignedVars[] 18069#[L12-3]don't care [343] L12-3-->L12-4: Formula: (and (= (select |v_#length_10| 2) 10) (= (select |v_#valid_15| 2) 1)) InVars {#length=|v_#length_10|, #valid=|v_#valid_15|} OutVars{#length=|v_#length_10|, #valid=|v_#valid_15|} AuxVars[] AssignedVars[] 18071#[L12-4]don't care [336] L12-4-->L700: Formula: (= v_~x~0_5 0) InVars {} OutVars{~x~0=v_~x~0_5} AuxVars[] AssignedVars[~x~0] 17119#[L700]don't care [280] L700-->L701: Formula: (= v_~y~0_17 0) InVars {} OutVars{~y~0=v_~y~0_17} AuxVars[] AssignedVars[~y~0] 17121#[L701]don't care [348] L701-->L701-1: Formula: (= v_~b1~0_7 0) InVars {} OutVars{~b1~0=v_~b1~0_7} AuxVars[] AssignedVars[~b1~0] 20311#[L701-1]don't care [247] L701-1-->L702: Formula: (= v_~b2~0_7 0) InVars {} OutVars{~b2~0=v_~b2~0_7} AuxVars[] AssignedVars[~b2~0] 16485#[L702]don't care [251] L702-->L-1-3: Formula: (= v_~X~0_7 0) InVars {} OutVars{~X~0=v_~X~0_7} AuxVars[] AssignedVars[~X~0] 16487#[L-1-3]don't care [353] L-1-3-->L-1-4: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 16891#[L-1-4]don't care [272] L-1-4-->L-1-5: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 19783#[L-1-5]don't care [242] L-1-5-->L-1-6: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res#1=|v_ULTIMATE.start_main_#res#1_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res#1] 19979#[L-1-6]don't care [335] L-1-6-->L844: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~pre6#1=|v_ULTIMATE.start_main_#t~pre6#1_1|, ULTIMATE.start_main_#t~mem8#1=|v_ULTIMATE.start_main_#t~mem8#1_1|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_1|, ULTIMATE.start_main_#t~nondet5#1=|v_ULTIMATE.start_main_#t~nondet5#1_1|, ULTIMATE.start_main_#t~nondet7#1=|v_ULTIMATE.start_main_#t~nondet7#1_1|, ULTIMATE.start_main_#t~mem9#1=|v_ULTIMATE.start_main_#t~mem9#1_1|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_1|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_1|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_1|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre6#1, ULTIMATE.start_main_#t~mem8#1, ULTIMATE.start_main_~#t2~0#1.offset, ULTIMATE.start_main_#t~nondet5#1, ULTIMATE.start_main_#t~nondet7#1, ULTIMATE.start_main_#t~mem9#1, ULTIMATE.start_main_~#t1~0#1.base, ULTIMATE.start_main_#t~pre4#1, ULTIMATE.start_main_~#t1~0#1.offset, ULTIMATE.start_main_~#t2~0#1.base] 19981#[L844]don't care [293] L844-->L844-1: Formula: (and (= (store |v_#valid_2| |v_ULTIMATE.start_main_~#t1~0#1.base_2| 1) |v_#valid_1|) (= |v_ULTIMATE.start_main_~#t1~0#1.offset_2| 0) (= (select |v_#valid_2| |v_ULTIMATE.start_main_~#t1~0#1.base_2|) 0) (< |v_#StackHeapBarrier_1| |v_ULTIMATE.start_main_~#t1~0#1.base_2|) (= (store |v_#length_2| |v_ULTIMATE.start_main_~#t1~0#1.base_2| 4) |v_#length_1|) (not (= |v_ULTIMATE.start_main_~#t1~0#1.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_2|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_2|, #valid=|v_#valid_1|} AuxVars[] AssignedVars[#valid, #length, ULTIMATE.start_main_~#t1~0#1.base, ULTIMATE.start_main_~#t1~0#1.offset] 16023#[L844-1]don't care [279] L844-1-->L844-2: Formula: (and (< |v_#StackHeapBarrier_2| |v_ULTIMATE.start_main_~#t2~0#1.base_2|) (not (= |v_ULTIMATE.start_main_~#t2~0#1.base_2| 0)) (= |v_#length_3| (store |v_#length_4| |v_ULTIMATE.start_main_~#t2~0#1.base_2| 4)) (= 0 |v_ULTIMATE.start_main_~#t2~0#1.offset_2|) (= (store |v_#valid_4| |v_ULTIMATE.start_main_~#t2~0#1.base_2| 1) |v_#valid_3|) (= (select |v_#valid_4| |v_ULTIMATE.start_main_~#t2~0#1.base_2|) 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_4|, #valid=|v_#valid_4|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_2|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_2|, #valid=|v_#valid_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2~0#1.offset, #valid, #length, ULTIMATE.start_main_~#t2~0#1.base] 16025#[L844-2]don't care [313] L844-2-->L845: Formula: (= |v_ULTIMATE.start_main_#t~pre4#1_2| |v_#pthreadsForks_1|) InVars {#pthreadsForks=|v_#pthreadsForks_1|} OutVars{#pthreadsForks=|v_#pthreadsForks_1|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre4#1] 16719#[L845]don't care [340] L845-->L845-1: Formula: (= (+ 1 |v_#pthreadsForks_3|) |v_#pthreadsForks_2|) InVars {#pthreadsForks=|v_#pthreadsForks_3|} OutVars{#pthreadsForks=|v_#pthreadsForks_2|} AuxVars[] AssignedVars[#pthreadsForks] 18753#[L845-1]don't care [244] L845-1-->L845-2: Formula: (and (<= 0 |v_ULTIMATE.start_main_~#t1~0#1.offset_3|) (= (select |v_#valid_5| |v_ULTIMATE.start_main_~#t1~0#1.base_3|) 1) (= (store |v_#memory_int_2| |v_ULTIMATE.start_main_~#t1~0#1.base_3| (store (select |v_#memory_int_2| |v_ULTIMATE.start_main_~#t1~0#1.base_3|) |v_ULTIMATE.start_main_~#t1~0#1.offset_3| |v_ULTIMATE.start_main_#t~pre4#1_3|)) |v_#memory_int_1|) (<= (+ |v_ULTIMATE.start_main_~#t1~0#1.offset_3| 4) (select |v_#length_5| |v_ULTIMATE.start_main_~#t1~0#1.base_3|))) InVars {#valid=|v_#valid_5|, #memory_int=|v_#memory_int_2|, #length=|v_#length_5|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_3|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_3|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_3|} OutVars{#valid=|v_#valid_5|, #memory_int=|v_#memory_int_1|, #length=|v_#length_5|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_3|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_3|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_3|} AuxVars[] AssignedVars[#memory_int] 18755#[L845-2]don't care [449] L845-2-->thr1ENTRY: Formula: (and (= v_thr1Thread1of1ForFork1_thidvar1_2 0) (= |v_ULTIMATE.start_main_#t~pre4#1_6| v_thr1Thread1of1ForFork1_thidvar0_2) (= |v_thr1Thread1of1ForFork1_#in~_.base_4| 0) (= |v_thr1Thread1of1ForFork1_#in~_.offset_4| 0)) InVars {ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_6|} OutVars{thr1Thread1of1ForFork1_#in~_.offset=|v_thr1Thread1of1ForFork1_#in~_.offset_4|, thr1Thread1of1ForFork1_~_.base=v_thr1Thread1of1ForFork1_~_.base_4, thr1Thread1of1ForFork1_~b21~0=v_thr1Thread1of1ForFork1_~b21~0_10, thr1Thread1of1ForFork1_#res.base=|v_thr1Thread1of1ForFork1_#res.base_4|, thr1Thread1of1ForFork1_~y1~0=v_thr1Thread1of1ForFork1_~y1~0_30, thr1Thread1of1ForFork1_#in~_.base=|v_thr1Thread1of1ForFork1_#in~_.base_4|, thr1Thread1of1ForFork1_~_.offset=v_thr1Thread1of1ForFork1_~_.offset_4, thr1Thread1of1ForFork1_#res.offset=|v_thr1Thread1of1ForFork1_#res.offset_4|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_6|, thr1Thread1of1ForFork1_thidvar1=v_thr1Thread1of1ForFork1_thidvar1_2, thr1Thread1of1ForFork1_thidvar0=v_thr1Thread1of1ForFork1_thidvar0_2, thr1Thread1of1ForFork1_~x1~0=v_thr1Thread1of1ForFork1_~x1~0_8} AuxVars[] AssignedVars[thr1Thread1of1ForFork1_#in~_.offset, thr1Thread1of1ForFork1_~_.base, thr1Thread1of1ForFork1_~b21~0, thr1Thread1of1ForFork1_#res.base, thr1Thread1of1ForFork1_~y1~0, thr1Thread1of1ForFork1_#in~_.base, thr1Thread1of1ForFork1_~_.offset, thr1Thread1of1ForFork1_#res.offset, thr1Thread1of1ForFork1_thidvar1, thr1Thread1of1ForFork1_thidvar0, thr1Thread1of1ForFork1_~x1~0] 18935#[thr1ENTRY, L845-3]don't care [402] thr1ENTRY-->L704loopEntry: Formula: (and (= v_thr1Thread1of1ForFork1_~_.base_1 |v_thr1Thread1of1ForFork1_#in~_.base_1|) (= |v_thr1Thread1of1ForFork1_#in~_.offset_1| v_thr1Thread1of1ForFork1_~_.offset_1)) InVars {thr1Thread1of1ForFork1_#in~_.offset=|v_thr1Thread1of1ForFork1_#in~_.offset_1|, thr1Thread1of1ForFork1_#in~_.base=|v_thr1Thread1of1ForFork1_#in~_.base_1|} OutVars{thr1Thread1of1ForFork1_#in~_.offset=|v_thr1Thread1of1ForFork1_#in~_.offset_1|, thr1Thread1of1ForFork1_#in~_.base=|v_thr1Thread1of1ForFork1_#in~_.base_1|, thr1Thread1of1ForFork1_~_.offset=v_thr1Thread1of1ForFork1_~_.offset_1, thr1Thread1of1ForFork1_~_.base=v_thr1Thread1of1ForFork1_~_.base_1} AuxVars[] AssignedVars[thr1Thread1of1ForFork1_~_.base, thr1Thread1of1ForFork1_~_.offset] 20257#[L704loopEntry, L845-3]don't care [403] L704loopEntry-->L753-1: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 18327#[L753-1, L845-3]don't care [2022-07-26 13:22:14,176 INFO L735 eck$LassoCheckResult]: Loop: 18327#[L753-1, L845-3]don't care [406] L753-1-->L705: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 18329#[L845-3, L705]don't care [408] L705-->L707: Formula: (= v_~b1~0_4 1) InVars {} OutVars{~b1~0=v_~b1~0_4} AuxVars[] AssignedVars[~b1~0] 17321#[L845-3, L707]don't care [411] L707-->L710: Formula: (= v_~x~0_3 1) InVars {} OutVars{~x~0=v_~x~0_3} AuxVars[] AssignedVars[~x~0] 16365#[L710, L845-3]don't care [414] L710-->L713: Formula: (= v_~y~0_12 v_thr1Thread1of1ForFork1_~y1~0_1) InVars {~y~0=v_~y~0_12} OutVars{~y~0=v_~y~0_12, thr1Thread1of1ForFork1_~y1~0=v_thr1Thread1of1ForFork1_~y1~0_1} AuxVars[] AssignedVars[thr1Thread1of1ForFork1_~y1~0] 16367#[L845-3, L713]don't care [416] L713-->L715: Formula: (not (= v_thr1Thread1of1ForFork1_~y1~0_3 0)) InVars {thr1Thread1of1ForFork1_~y1~0=v_thr1Thread1of1ForFork1_~y1~0_3} OutVars{thr1Thread1of1ForFork1_~y1~0=v_thr1Thread1of1ForFork1_~y1~0_3} AuxVars[] AssignedVars[] 17445#[L845-3, L715]don't care [419] L715-->L717: Formula: (= v_~b1~0_5 0) InVars {} OutVars{~b1~0=v_~b1~0_5} AuxVars[] AssignedVars[~b1~0] 19919#[L845-3, L717]don't care [422] L717-->L724: Formula: (= v_~y~0_13 v_thr1Thread1of1ForFork1_~y1~0_7) InVars {~y~0=v_~y~0_13} OutVars{~y~0=v_~y~0_13, thr1Thread1of1ForFork1_~y1~0=v_thr1Thread1of1ForFork1_~y1~0_7} AuxVars[] AssignedVars[thr1Thread1of1ForFork1_~y1~0] 19873#[L845-3, L724]don't care [425] L724-->L753-1: Formula: (= v_thr1Thread1of1ForFork1_~y1~0_9 0) InVars {thr1Thread1of1ForFork1_~y1~0=v_thr1Thread1of1ForFork1_~y1~0_9} OutVars{thr1Thread1of1ForFork1_~y1~0=v_thr1Thread1of1ForFork1_~y1~0_9} AuxVars[] AssignedVars[] 18327#[L753-1, L845-3]don't care [2022-07-26 13:22:14,180 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:14,184 INFO L85 PathProgramCache]: Analyzing trace with hash -2049050784, now seen corresponding path program 2 times [2022-07-26 13:22:14,185 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:14,185 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1940203553] [2022-07-26 13:22:14,185 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:14,185 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:14,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:14,228 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-26 13:22:14,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:14,258 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-26 13:22:14,259 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:14,259 INFO L85 PathProgramCache]: Analyzing trace with hash 1999980076, now seen corresponding path program 1 times [2022-07-26 13:22:14,263 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:14,263 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [38610106] [2022-07-26 13:22:14,264 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:14,264 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:14,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-26 13:22:14,344 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-26 13:22:14,344 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-26 13:22:14,344 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [38610106] [2022-07-26 13:22:14,344 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [38610106] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-26 13:22:14,344 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-26 13:22:14,345 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-26 13:22:14,345 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [218140794] [2022-07-26 13:22:14,345 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-26 13:22:14,345 INFO L750 eck$LassoCheckResult]: loop already infeasible [2022-07-26 13:22:14,346 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-26 13:22:14,346 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-26 13:22:14,346 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-26 13:22:14,346 INFO L87 Difference]: Start difference. First operand 3866 states and 11618 transitions. cyclomatic complexity: 7845 Second operand has 5 states, 4 states have (on average 2.0) internal successors, (8), 5 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-26 13:22:14,681 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-26 13:22:14,681 INFO L93 Difference]: Finished difference Result 7589 states and 21892 transitions. [2022-07-26 13:22:14,681 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7589 states and 21892 transitions. [2022-07-26 13:22:14,774 INFO L131 ngComponentsAnalysis]: Automaton has 562 accepting balls. 5380 [2022-07-26 13:22:14,854 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7589 states to 7589 states and 21892 transitions. [2022-07-26 13:22:14,854 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7589 [2022-07-26 13:22:14,872 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7589 [2022-07-26 13:22:14,872 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7589 states and 21892 transitions. [2022-07-26 13:22:14,890 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-26 13:22:14,891 INFO L220 hiAutomatonCegarLoop]: Abstraction has 7589 states and 21892 transitions. [2022-07-26 13:22:14,911 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7589 states and 21892 transitions. [2022-07-26 13:22:15,047 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7589 to 4510. [2022-07-26 13:22:15,061 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4510 states, 4510 states have (on average 2.924390243902439) internal successors, (13189), 4509 states have internal predecessors, (13189), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-26 13:22:15,147 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4510 states to 4510 states and 13189 transitions. [2022-07-26 13:22:15,148 INFO L242 hiAutomatonCegarLoop]: Abstraction has 4510 states and 13189 transitions. [2022-07-26 13:22:15,149 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-07-26 13:22:15,149 INFO L426 stractBuchiCegarLoop]: Abstraction has 4510 states and 13189 transitions. [2022-07-26 13:22:15,150 INFO L333 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-07-26 13:22:15,150 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4510 states and 13189 transitions. [2022-07-26 13:22:15,178 INFO L131 ngComponentsAnalysis]: Automaton has 297 accepting balls. 3275 [2022-07-26 13:22:15,178 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-26 13:22:15,178 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-26 13:22:15,180 INFO L150 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-26 13:22:15,180 INFO L151 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2022-07-26 13:22:15,183 INFO L733 eck$LassoCheckResult]: Stem: 35678#[ULTIMATE.startENTRY]don't care [341] ULTIMATE.startENTRY-->L-1: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 35680#[L-1]don't care [266] L-1-->L-1-1: Formula: (and (= |v_#NULL.base_1| 0) (= |v_#NULL.offset_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] 31046#[L-1-1]don't care [350] L-1-1-->L-1-2: Formula: (= 0 (select |v_#valid_13| 0)) InVars {#valid=|v_#valid_13|} OutVars{#valid=|v_#valid_13|} AuxVars[] AssignedVars[] 31048#[L-1-2]don't care [352] L-1-2-->L12: Formula: (< 0 |v_#StackHeapBarrier_3|) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_3|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_3|} AuxVars[] AssignedVars[] 35842#[L12]don't care [305] L12-->L12-1: Formula: (and (= (select |v_#length_9| 1) 2) (= (select |v_#valid_14| 1) 1)) InVars {#length=|v_#length_9|, #valid=|v_#valid_14|} OutVars{#length=|v_#length_9|, #valid=|v_#valid_14|} AuxVars[] AssignedVars[] 34010#[L12-1]don't care [320] L12-1-->L12-2: Formula: (= (select (select |v_#memory_int_7| 1) 0) 48) InVars {#memory_int=|v_#memory_int_7|} OutVars{#memory_int=|v_#memory_int_7|} AuxVars[] AssignedVars[] 34012#[L12-2]don't care [319] L12-2-->L12-3: Formula: (= (select (select |v_#memory_int_8| 1) 1) 0) InVars {#memory_int=|v_#memory_int_8|} OutVars{#memory_int=|v_#memory_int_8|} AuxVars[] AssignedVars[] 33402#[L12-3]don't care [343] L12-3-->L12-4: Formula: (and (= (select |v_#length_10| 2) 10) (= (select |v_#valid_15| 2) 1)) InVars {#length=|v_#length_10|, #valid=|v_#valid_15|} OutVars{#length=|v_#length_10|, #valid=|v_#valid_15|} AuxVars[] AssignedVars[] 33404#[L12-4]don't care [336] L12-4-->L700: Formula: (= v_~x~0_5 0) InVars {} OutVars{~x~0=v_~x~0_5} AuxVars[] AssignedVars[~x~0] 32426#[L700]don't care [280] L700-->L701: Formula: (= v_~y~0_17 0) InVars {} OutVars{~y~0=v_~y~0_17} AuxVars[] AssignedVars[~y~0] 32428#[L701]don't care [348] L701-->L701-1: Formula: (= v_~b1~0_7 0) InVars {} OutVars{~b1~0=v_~b1~0_7} AuxVars[] AssignedVars[~b1~0] 35896#[L701-1]don't care [247] L701-1-->L702: Formula: (= v_~b2~0_7 0) InVars {} OutVars{~b2~0=v_~b2~0_7} AuxVars[] AssignedVars[~b2~0] 31792#[L702]don't care [251] L702-->L-1-3: Formula: (= v_~X~0_7 0) InVars {} OutVars{~X~0=v_~X~0_7} AuxVars[] AssignedVars[~X~0] 31794#[L-1-3]don't care [353] L-1-3-->L-1-4: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 32202#[L-1-4]don't care [272] L-1-4-->L-1-5: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 35244#[L-1-5]don't care [242] L-1-5-->L-1-6: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res#1=|v_ULTIMATE.start_main_#res#1_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res#1] 35462#[L-1-6]don't care [335] L-1-6-->L844: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~pre6#1=|v_ULTIMATE.start_main_#t~pre6#1_1|, ULTIMATE.start_main_#t~mem8#1=|v_ULTIMATE.start_main_#t~mem8#1_1|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_1|, ULTIMATE.start_main_#t~nondet5#1=|v_ULTIMATE.start_main_#t~nondet5#1_1|, ULTIMATE.start_main_#t~nondet7#1=|v_ULTIMATE.start_main_#t~nondet7#1_1|, ULTIMATE.start_main_#t~mem9#1=|v_ULTIMATE.start_main_#t~mem9#1_1|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_1|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_1|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_1|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre6#1, ULTIMATE.start_main_#t~mem8#1, ULTIMATE.start_main_~#t2~0#1.offset, ULTIMATE.start_main_#t~nondet5#1, ULTIMATE.start_main_#t~nondet7#1, ULTIMATE.start_main_#t~mem9#1, ULTIMATE.start_main_~#t1~0#1.base, ULTIMATE.start_main_#t~pre4#1, ULTIMATE.start_main_~#t1~0#1.offset, ULTIMATE.start_main_~#t2~0#1.base] 35464#[L844]don't care [293] L844-->L844-1: Formula: (and (= (store |v_#valid_2| |v_ULTIMATE.start_main_~#t1~0#1.base_2| 1) |v_#valid_1|) (= |v_ULTIMATE.start_main_~#t1~0#1.offset_2| 0) (= (select |v_#valid_2| |v_ULTIMATE.start_main_~#t1~0#1.base_2|) 0) (< |v_#StackHeapBarrier_1| |v_ULTIMATE.start_main_~#t1~0#1.base_2|) (= (store |v_#length_2| |v_ULTIMATE.start_main_~#t1~0#1.base_2| 4) |v_#length_1|) (not (= |v_ULTIMATE.start_main_~#t1~0#1.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_2|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_2|, #valid=|v_#valid_1|} AuxVars[] AssignedVars[#valid, #length, ULTIMATE.start_main_~#t1~0#1.base, ULTIMATE.start_main_~#t1~0#1.offset] 31328#[L844-1]don't care [279] L844-1-->L844-2: Formula: (and (< |v_#StackHeapBarrier_2| |v_ULTIMATE.start_main_~#t2~0#1.base_2|) (not (= |v_ULTIMATE.start_main_~#t2~0#1.base_2| 0)) (= |v_#length_3| (store |v_#length_4| |v_ULTIMATE.start_main_~#t2~0#1.base_2| 4)) (= 0 |v_ULTIMATE.start_main_~#t2~0#1.offset_2|) (= (store |v_#valid_4| |v_ULTIMATE.start_main_~#t2~0#1.base_2| 1) |v_#valid_3|) (= (select |v_#valid_4| |v_ULTIMATE.start_main_~#t2~0#1.base_2|) 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_4|, #valid=|v_#valid_4|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_2|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_2|, #valid=|v_#valid_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2~0#1.offset, #valid, #length, ULTIMATE.start_main_~#t2~0#1.base] 31330#[L844-2]don't care [313] L844-2-->L845: Formula: (= |v_ULTIMATE.start_main_#t~pre4#1_2| |v_#pthreadsForks_1|) InVars {#pthreadsForks=|v_#pthreadsForks_1|} OutVars{#pthreadsForks=|v_#pthreadsForks_1|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre4#1] 32024#[L845]don't care [340] L845-->L845-1: Formula: (= (+ 1 |v_#pthreadsForks_3|) |v_#pthreadsForks_2|) InVars {#pthreadsForks=|v_#pthreadsForks_3|} OutVars{#pthreadsForks=|v_#pthreadsForks_2|} AuxVars[] AssignedVars[#pthreadsForks] 34120#[L845-1]don't care [244] L845-1-->L845-2: Formula: (and (<= 0 |v_ULTIMATE.start_main_~#t1~0#1.offset_3|) (= (select |v_#valid_5| |v_ULTIMATE.start_main_~#t1~0#1.base_3|) 1) (= (store |v_#memory_int_2| |v_ULTIMATE.start_main_~#t1~0#1.base_3| (store (select |v_#memory_int_2| |v_ULTIMATE.start_main_~#t1~0#1.base_3|) |v_ULTIMATE.start_main_~#t1~0#1.offset_3| |v_ULTIMATE.start_main_#t~pre4#1_3|)) |v_#memory_int_1|) (<= (+ |v_ULTIMATE.start_main_~#t1~0#1.offset_3| 4) (select |v_#length_5| |v_ULTIMATE.start_main_~#t1~0#1.base_3|))) InVars {#valid=|v_#valid_5|, #memory_int=|v_#memory_int_2|, #length=|v_#length_5|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_3|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_3|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_3|} OutVars{#valid=|v_#valid_5|, #memory_int=|v_#memory_int_1|, #length=|v_#length_5|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_3|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_3|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_3|} AuxVars[] AssignedVars[#memory_int] 34122#[L845-2]don't care [449] L845-2-->thr1ENTRY: Formula: (and (= v_thr1Thread1of1ForFork1_thidvar1_2 0) (= |v_ULTIMATE.start_main_#t~pre4#1_6| v_thr1Thread1of1ForFork1_thidvar0_2) (= |v_thr1Thread1of1ForFork1_#in~_.base_4| 0) (= |v_thr1Thread1of1ForFork1_#in~_.offset_4| 0)) InVars {ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_6|} OutVars{thr1Thread1of1ForFork1_#in~_.offset=|v_thr1Thread1of1ForFork1_#in~_.offset_4|, thr1Thread1of1ForFork1_~_.base=v_thr1Thread1of1ForFork1_~_.base_4, thr1Thread1of1ForFork1_~b21~0=v_thr1Thread1of1ForFork1_~b21~0_10, thr1Thread1of1ForFork1_#res.base=|v_thr1Thread1of1ForFork1_#res.base_4|, thr1Thread1of1ForFork1_~y1~0=v_thr1Thread1of1ForFork1_~y1~0_30, thr1Thread1of1ForFork1_#in~_.base=|v_thr1Thread1of1ForFork1_#in~_.base_4|, thr1Thread1of1ForFork1_~_.offset=v_thr1Thread1of1ForFork1_~_.offset_4, thr1Thread1of1ForFork1_#res.offset=|v_thr1Thread1of1ForFork1_#res.offset_4|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_6|, thr1Thread1of1ForFork1_thidvar1=v_thr1Thread1of1ForFork1_thidvar1_2, thr1Thread1of1ForFork1_thidvar0=v_thr1Thread1of1ForFork1_thidvar0_2, thr1Thread1of1ForFork1_~x1~0=v_thr1Thread1of1ForFork1_~x1~0_8} AuxVars[] AssignedVars[thr1Thread1of1ForFork1_#in~_.offset, thr1Thread1of1ForFork1_~_.base, thr1Thread1of1ForFork1_~b21~0, thr1Thread1of1ForFork1_#res.base, thr1Thread1of1ForFork1_~y1~0, thr1Thread1of1ForFork1_#in~_.base, thr1Thread1of1ForFork1_~_.offset, thr1Thread1of1ForFork1_#res.offset, thr1Thread1of1ForFork1_thidvar1, thr1Thread1of1ForFork1_thidvar0, thr1Thread1of1ForFork1_~x1~0] 34312#[thr1ENTRY, L845-3]don't care [328] L845-3-->L845-4: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre4#1] 35906#[thr1ENTRY, L845-4]don't care [259] L845-4-->L846: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet5#1=|v_ULTIMATE.start_main_#t~nondet5#1_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet5#1] 34914#[thr1ENTRY, L846]don't care [243] L846-->L846-1: Formula: (= |v_ULTIMATE.start_main_#t~pre6#1_2| |v_#pthreadsForks_4|) InVars {#pthreadsForks=|v_#pthreadsForks_4|} OutVars{#pthreadsForks=|v_#pthreadsForks_4|, ULTIMATE.start_main_#t~pre6#1=|v_ULTIMATE.start_main_#t~pre6#1_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre6#1] 34916#[thr1ENTRY, L846-1]don't care [234] L846-1-->L846-2: Formula: (= (+ 1 |v_#pthreadsForks_6|) |v_#pthreadsForks_5|) InVars {#pthreadsForks=|v_#pthreadsForks_6|} OutVars{#pthreadsForks=|v_#pthreadsForks_5|} AuxVars[] AssignedVars[#pthreadsForks] 35460#[thr1ENTRY, L846-2]don't care [258] L846-2-->L846-3: Formula: (and (<= (+ 4 |v_ULTIMATE.start_main_~#t2~0#1.offset_3|) (select |v_#length_6| |v_ULTIMATE.start_main_~#t2~0#1.base_3|)) (= (store |v_#memory_int_4| |v_ULTIMATE.start_main_~#t2~0#1.base_3| (store (select |v_#memory_int_4| |v_ULTIMATE.start_main_~#t2~0#1.base_3|) |v_ULTIMATE.start_main_~#t2~0#1.offset_3| |v_ULTIMATE.start_main_#t~pre6#1_3|)) |v_#memory_int_3|) (= (select |v_#valid_6| |v_ULTIMATE.start_main_~#t2~0#1.base_3|) 1) (<= 0 |v_ULTIMATE.start_main_~#t2~0#1.offset_3|)) InVars {ULTIMATE.start_main_#t~pre6#1=|v_ULTIMATE.start_main_#t~pre6#1_3|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_3|, #valid=|v_#valid_6|, #memory_int=|v_#memory_int_4|, #length=|v_#length_6|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_3|} OutVars{ULTIMATE.start_main_#t~pre6#1=|v_ULTIMATE.start_main_#t~pre6#1_3|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_3|, #valid=|v_#valid_6|, #memory_int=|v_#memory_int_3|, #length=|v_#length_6|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_3|} AuxVars[] AssignedVars[#memory_int] 34518#[thr1ENTRY, L846-3]don't care [446] L846-3-->thr2ENTRY: Formula: (and (= v_thr2Thread1of1ForFork0_thidvar2_2 0) (= |v_ULTIMATE.start_main_#t~pre6#1_6| v_thr2Thread1of1ForFork0_thidvar0_2) (= |v_thr2Thread1of1ForFork0_#in~_.offset_4| 0) (= |v_thr2Thread1of1ForFork0_#in~_.base_4| 0) (= v_thr2Thread1of1ForFork0_thidvar1_2 0)) InVars {ULTIMATE.start_main_#t~pre6#1=|v_ULTIMATE.start_main_#t~pre6#1_6|} OutVars{thr2Thread1of1ForFork0_~y2~0=v_thr2Thread1of1ForFork0_~y2~0_30, ULTIMATE.start_main_#t~pre6#1=|v_ULTIMATE.start_main_#t~pre6#1_6|, thr2Thread1of1ForFork0_#in~_.offset=|v_thr2Thread1of1ForFork0_#in~_.offset_4|, thr2Thread1of1ForFork0_#res.base=|v_thr2Thread1of1ForFork0_#res.base_4|, thr2Thread1of1ForFork0_~x2~0=v_thr2Thread1of1ForFork0_~x2~0_8, thr2Thread1of1ForFork0_#res.offset=|v_thr2Thread1of1ForFork0_#res.offset_4|, thr2Thread1of1ForFork0_~b12~0=v_thr2Thread1of1ForFork0_~b12~0_10, thr2Thread1of1ForFork0_#in~_.base=|v_thr2Thread1of1ForFork0_#in~_.base_4|, thr2Thread1of1ForFork0_~_.base=v_thr2Thread1of1ForFork0_~_.base_4, thr2Thread1of1ForFork0_~_.offset=v_thr2Thread1of1ForFork0_~_.offset_4, thr2Thread1of1ForFork0_thidvar0=v_thr2Thread1of1ForFork0_thidvar0_2, thr2Thread1of1ForFork0_thidvar1=v_thr2Thread1of1ForFork0_thidvar1_2, thr2Thread1of1ForFork0_thidvar2=v_thr2Thread1of1ForFork0_thidvar2_2} AuxVars[] AssignedVars[thr2Thread1of1ForFork0_~y2~0, thr2Thread1of1ForFork0_~_.offset, thr2Thread1of1ForFork0_#in~_.offset, thr2Thread1of1ForFork0_#res.base, thr2Thread1of1ForFork0_thidvar0, thr2Thread1of1ForFork0_thidvar1, thr2Thread1of1ForFork0_thidvar2, thr2Thread1of1ForFork0_~x2~0, thr2Thread1of1ForFork0_#res.offset, thr2Thread1of1ForFork0_~b12~0, thr2Thread1of1ForFork0_#in~_.base, thr2Thread1of1ForFork0_~_.base] 34168#[thr2ENTRY, L846-4, thr1ENTRY]don't care [360] thr2ENTRY-->L774loopEntry: Formula: (and (= |v_thr2Thread1of1ForFork0_#in~_.base_1| v_thr2Thread1of1ForFork0_~_.base_1) (= v_thr2Thread1of1ForFork0_~_.offset_1 |v_thr2Thread1of1ForFork0_#in~_.offset_1|)) InVars {thr2Thread1of1ForFork0_#in~_.offset=|v_thr2Thread1of1ForFork0_#in~_.offset_1|, thr2Thread1of1ForFork0_#in~_.base=|v_thr2Thread1of1ForFork0_#in~_.base_1|} OutVars{thr2Thread1of1ForFork0_~_.offset=v_thr2Thread1of1ForFork0_~_.offset_1, thr2Thread1of1ForFork0_#in~_.offset=|v_thr2Thread1of1ForFork0_#in~_.offset_1|, thr2Thread1of1ForFork0_#in~_.base=|v_thr2Thread1of1ForFork0_#in~_.base_1|, thr2Thread1of1ForFork0_~_.base=v_thr2Thread1of1ForFork0_~_.base_1} AuxVars[] AssignedVars[thr2Thread1of1ForFork0_~_.offset, thr2Thread1of1ForFork0_~_.base] 34172#[L774loopEntry, thr1ENTRY, L846-4]don't care [361] L774loopEntry-->L823-1: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 35838#[L823-1, L846-4, thr1ENTRY]don't care [2022-07-26 13:22:15,184 INFO L735 eck$LassoCheckResult]: Loop: 35838#[L823-1, L846-4, thr1ENTRY]don't care [364] L823-1-->L775: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 36786#[L775, thr1ENTRY, L846-4]don't care [366] L775-->L777: Formula: (= v_~b2~0_1 1) InVars {} OutVars{~b2~0=v_~b2~0_1} AuxVars[] AssignedVars[~b2~0] 36790#[L777, L846-4, thr1ENTRY]don't care [369] L777-->L780: Formula: (= 2 v_~x~0_1) InVars {} OutVars{~x~0=v_~x~0_1} AuxVars[] AssignedVars[~x~0] 36816#[L780, thr1ENTRY, L846-4]don't care [372] L780-->L783: Formula: (= v_~y~0_2 v_thr2Thread1of1ForFork0_~y2~0_1) InVars {~y~0=v_~y~0_2} OutVars{~y~0=v_~y~0_2, thr2Thread1of1ForFork0_~y2~0=v_thr2Thread1of1ForFork0_~y2~0_1} AuxVars[] AssignedVars[thr2Thread1of1ForFork0_~y2~0] 36810#[L783, L846-4, thr1ENTRY]don't care [374] L783-->L785: Formula: (not (= v_thr2Thread1of1ForFork0_~y2~0_3 0)) InVars {thr2Thread1of1ForFork0_~y2~0=v_thr2Thread1of1ForFork0_~y2~0_3} OutVars{thr2Thread1of1ForFork0_~y2~0=v_thr2Thread1of1ForFork0_~y2~0_3} AuxVars[] AssignedVars[] 36804#[L785, thr1ENTRY, L846-4]don't care [377] L785-->L787: Formula: (= v_~b2~0_2 0) InVars {} OutVars{~b2~0=v_~b2~0_2} AuxVars[] AssignedVars[~b2~0] 36800#[L787, L846-4, thr1ENTRY]don't care [380] L787-->L794: Formula: (= v_~y~0_3 v_thr2Thread1of1ForFork0_~y2~0_7) InVars {~y~0=v_~y~0_3} OutVars{~y~0=v_~y~0_3, thr2Thread1of1ForFork0_~y2~0=v_thr2Thread1of1ForFork0_~y2~0_7} AuxVars[] AssignedVars[thr2Thread1of1ForFork0_~y2~0] 36794#[L794, thr1ENTRY, L846-4]don't care [383] L794-->L823-1: Formula: (= v_thr2Thread1of1ForFork0_~y2~0_9 0) InVars {thr2Thread1of1ForFork0_~y2~0=v_thr2Thread1of1ForFork0_~y2~0_9} OutVars{thr2Thread1of1ForFork0_~y2~0=v_thr2Thread1of1ForFork0_~y2~0_9} AuxVars[] AssignedVars[] 35838#[L823-1, L846-4, thr1ENTRY]don't care [2022-07-26 13:22:15,185 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:15,185 INFO L85 PathProgramCache]: Analyzing trace with hash -921846738, now seen corresponding path program 1 times [2022-07-26 13:22:15,185 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:15,185 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1173321271] [2022-07-26 13:22:15,185 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:15,186 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:15,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:15,227 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-26 13:22:15,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:15,259 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-26 13:22:15,260 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:15,260 INFO L85 PathProgramCache]: Analyzing trace with hash 1953435948, now seen corresponding path program 1 times [2022-07-26 13:22:15,260 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:15,261 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1337333806] [2022-07-26 13:22:15,261 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:15,261 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:15,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-26 13:22:15,299 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-26 13:22:15,299 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-26 13:22:15,299 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1337333806] [2022-07-26 13:22:15,300 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1337333806] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-26 13:22:15,300 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-26 13:22:15,300 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-26 13:22:15,301 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [785865364] [2022-07-26 13:22:15,301 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-26 13:22:15,301 INFO L750 eck$LassoCheckResult]: loop already infeasible [2022-07-26 13:22:15,301 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-26 13:22:15,302 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-07-26 13:22:15,302 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-07-26 13:22:15,302 INFO L87 Difference]: Start difference. First operand 4510 states and 13189 transitions. cyclomatic complexity: 8976 Second operand has 5 states, 4 states have (on average 2.0) internal successors, (8), 5 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-26 13:22:15,532 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-26 13:22:15,532 INFO L93 Difference]: Finished difference Result 6560 states and 18538 transitions. [2022-07-26 13:22:15,533 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6560 states and 18538 transitions. [2022-07-26 13:22:15,606 INFO L131 ngComponentsAnalysis]: Automaton has 954 accepting balls. 1980 [2022-07-26 13:22:15,667 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6560 states to 6560 states and 18538 transitions. [2022-07-26 13:22:15,667 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6560 [2022-07-26 13:22:15,677 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6560 [2022-07-26 13:22:15,677 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6560 states and 18538 transitions. [2022-07-26 13:22:15,690 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-26 13:22:15,691 INFO L220 hiAutomatonCegarLoop]: Abstraction has 6560 states and 18538 transitions. [2022-07-26 13:22:15,708 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6560 states and 18538 transitions. [2022-07-26 13:22:15,863 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6560 to 4651. [2022-07-26 13:22:15,876 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4651 states, 4651 states have (on average 2.8449795742851) internal successors, (13232), 4650 states have internal predecessors, (13232), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-26 13:22:15,893 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4651 states to 4651 states and 13232 transitions. [2022-07-26 13:22:15,893 INFO L242 hiAutomatonCegarLoop]: Abstraction has 4651 states and 13232 transitions. [2022-07-26 13:22:15,894 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-07-26 13:22:15,895 INFO L426 stractBuchiCegarLoop]: Abstraction has 4651 states and 13232 transitions. [2022-07-26 13:22:15,895 INFO L333 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-07-26 13:22:15,896 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4651 states and 13232 transitions. [2022-07-26 13:22:15,926 INFO L131 ngComponentsAnalysis]: Automaton has 714 accepting balls. 1500 [2022-07-26 13:22:15,926 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-26 13:22:15,926 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-26 13:22:15,928 INFO L150 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-26 13:22:15,928 INFO L151 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-07-26 13:22:15,931 INFO L733 eck$LassoCheckResult]: Stem: 51398#[ULTIMATE.startENTRY]don't care [341] ULTIMATE.startENTRY-->L-1: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 51400#[L-1]don't care [266] L-1-->L-1-1: Formula: (and (= |v_#NULL.base_1| 0) (= |v_#NULL.offset_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] 46570#[L-1-1]don't care [350] L-1-1-->L-1-2: Formula: (= 0 (select |v_#valid_13| 0)) InVars {#valid=|v_#valid_13|} OutVars{#valid=|v_#valid_13|} AuxVars[] AssignedVars[] 46572#[L-1-2]don't care [352] L-1-2-->L12: Formula: (< 0 |v_#StackHeapBarrier_3|) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_3|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_3|} AuxVars[] AssignedVars[] 51620#[L12]don't care [305] L12-->L12-1: Formula: (and (= (select |v_#length_9| 1) 2) (= (select |v_#valid_14| 1) 1)) InVars {#length=|v_#length_9|, #valid=|v_#valid_14|} OutVars{#length=|v_#length_9|, #valid=|v_#valid_14|} AuxVars[] AssignedVars[] 49592#[L12-1]don't care [320] L12-1-->L12-2: Formula: (= (select (select |v_#memory_int_7| 1) 0) 48) InVars {#memory_int=|v_#memory_int_7|} OutVars{#memory_int=|v_#memory_int_7|} AuxVars[] AssignedVars[] 49594#[L12-2]don't care [319] L12-2-->L12-3: Formula: (= (select (select |v_#memory_int_8| 1) 1) 0) InVars {#memory_int=|v_#memory_int_8|} OutVars{#memory_int=|v_#memory_int_8|} AuxVars[] AssignedVars[] 48946#[L12-3]don't care [343] L12-3-->L12-4: Formula: (and (= (select |v_#length_10| 2) 10) (= (select |v_#valid_15| 2) 1)) InVars {#length=|v_#length_10|, #valid=|v_#valid_15|} OutVars{#length=|v_#length_10|, #valid=|v_#valid_15|} AuxVars[] AssignedVars[] 48948#[L12-4]don't care [336] L12-4-->L700: Formula: (= v_~x~0_5 0) InVars {} OutVars{~x~0=v_~x~0_5} AuxVars[] AssignedVars[~x~0] 47930#[L700]don't care [280] L700-->L701: Formula: (= v_~y~0_17 0) InVars {} OutVars{~y~0=v_~y~0_17} AuxVars[] AssignedVars[~y~0] 47932#[L701]don't care [348] L701-->L701-1: Formula: (= v_~b1~0_7 0) InVars {} OutVars{~b1~0=v_~b1~0_7} AuxVars[] AssignedVars[~b1~0] 51710#[L701-1]don't care [247] L701-1-->L702: Formula: (= v_~b2~0_7 0) InVars {} OutVars{~b2~0=v_~b2~0_7} AuxVars[] AssignedVars[~b2~0] 47302#[L702]don't care [251] L702-->L-1-3: Formula: (= v_~X~0_7 0) InVars {} OutVars{~X~0=v_~X~0_7} AuxVars[] AssignedVars[~X~0] 47304#[L-1-3]don't care [353] L-1-3-->L-1-4: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 47704#[L-1-4]don't care [272] L-1-4-->L-1-5: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 50880#[L-1-5]don't care [242] L-1-5-->L-1-6: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res#1=|v_ULTIMATE.start_main_#res#1_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res#1] 51126#[L-1-6]don't care [335] L-1-6-->L844: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~pre6#1=|v_ULTIMATE.start_main_#t~pre6#1_1|, ULTIMATE.start_main_#t~mem8#1=|v_ULTIMATE.start_main_#t~mem8#1_1|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_1|, ULTIMATE.start_main_#t~nondet5#1=|v_ULTIMATE.start_main_#t~nondet5#1_1|, ULTIMATE.start_main_#t~nondet7#1=|v_ULTIMATE.start_main_#t~nondet7#1_1|, ULTIMATE.start_main_#t~mem9#1=|v_ULTIMATE.start_main_#t~mem9#1_1|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_1|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_1|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_1|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre6#1, ULTIMATE.start_main_#t~mem8#1, ULTIMATE.start_main_~#t2~0#1.offset, ULTIMATE.start_main_#t~nondet5#1, ULTIMATE.start_main_#t~nondet7#1, ULTIMATE.start_main_#t~mem9#1, ULTIMATE.start_main_~#t1~0#1.base, ULTIMATE.start_main_#t~pre4#1, ULTIMATE.start_main_~#t1~0#1.offset, ULTIMATE.start_main_~#t2~0#1.base] 51128#[L844]don't care [293] L844-->L844-1: Formula: (and (= (store |v_#valid_2| |v_ULTIMATE.start_main_~#t1~0#1.base_2| 1) |v_#valid_1|) (= |v_ULTIMATE.start_main_~#t1~0#1.offset_2| 0) (= (select |v_#valid_2| |v_ULTIMATE.start_main_~#t1~0#1.base_2|) 0) (< |v_#StackHeapBarrier_1| |v_ULTIMATE.start_main_~#t1~0#1.base_2|) (= (store |v_#length_2| |v_ULTIMATE.start_main_~#t1~0#1.base_2| 4) |v_#length_1|) (not (= |v_ULTIMATE.start_main_~#t1~0#1.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_2|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_2|, #valid=|v_#valid_1|} AuxVars[] AssignedVars[#valid, #length, ULTIMATE.start_main_~#t1~0#1.base, ULTIMATE.start_main_~#t1~0#1.offset] 46852#[L844-1]don't care [279] L844-1-->L844-2: Formula: (and (< |v_#StackHeapBarrier_2| |v_ULTIMATE.start_main_~#t2~0#1.base_2|) (not (= |v_ULTIMATE.start_main_~#t2~0#1.base_2| 0)) (= |v_#length_3| (store |v_#length_4| |v_ULTIMATE.start_main_~#t2~0#1.base_2| 4)) (= 0 |v_ULTIMATE.start_main_~#t2~0#1.offset_2|) (= (store |v_#valid_4| |v_ULTIMATE.start_main_~#t2~0#1.base_2| 1) |v_#valid_3|) (= (select |v_#valid_4| |v_ULTIMATE.start_main_~#t2~0#1.base_2|) 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_4|, #valid=|v_#valid_4|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_2|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_2|, #valid=|v_#valid_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2~0#1.offset, #valid, #length, ULTIMATE.start_main_~#t2~0#1.base] 46854#[L844-2]don't care [313] L844-2-->L845: Formula: (= |v_ULTIMATE.start_main_#t~pre4#1_2| |v_#pthreadsForks_1|) InVars {#pthreadsForks=|v_#pthreadsForks_1|} OutVars{#pthreadsForks=|v_#pthreadsForks_1|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre4#1] 47526#[L845]don't care [340] L845-->L845-1: Formula: (= (+ 1 |v_#pthreadsForks_3|) |v_#pthreadsForks_2|) InVars {#pthreadsForks=|v_#pthreadsForks_3|} OutVars{#pthreadsForks=|v_#pthreadsForks_2|} AuxVars[] AssignedVars[#pthreadsForks] 49706#[L845-1]don't care [244] L845-1-->L845-2: Formula: (and (<= 0 |v_ULTIMATE.start_main_~#t1~0#1.offset_3|) (= (select |v_#valid_5| |v_ULTIMATE.start_main_~#t1~0#1.base_3|) 1) (= (store |v_#memory_int_2| |v_ULTIMATE.start_main_~#t1~0#1.base_3| (store (select |v_#memory_int_2| |v_ULTIMATE.start_main_~#t1~0#1.base_3|) |v_ULTIMATE.start_main_~#t1~0#1.offset_3| |v_ULTIMATE.start_main_#t~pre4#1_3|)) |v_#memory_int_1|) (<= (+ |v_ULTIMATE.start_main_~#t1~0#1.offset_3| 4) (select |v_#length_5| |v_ULTIMATE.start_main_~#t1~0#1.base_3|))) InVars {#valid=|v_#valid_5|, #memory_int=|v_#memory_int_2|, #length=|v_#length_5|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_3|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_3|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_3|} OutVars{#valid=|v_#valid_5|, #memory_int=|v_#memory_int_1|, #length=|v_#length_5|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_3|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_3|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_3|} AuxVars[] AssignedVars[#memory_int] 49708#[L845-2]don't care [449] L845-2-->thr1ENTRY: Formula: (and (= v_thr1Thread1of1ForFork1_thidvar1_2 0) (= |v_ULTIMATE.start_main_#t~pre4#1_6| v_thr1Thread1of1ForFork1_thidvar0_2) (= |v_thr1Thread1of1ForFork1_#in~_.base_4| 0) (= |v_thr1Thread1of1ForFork1_#in~_.offset_4| 0)) InVars {ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_6|} OutVars{thr1Thread1of1ForFork1_#in~_.offset=|v_thr1Thread1of1ForFork1_#in~_.offset_4|, thr1Thread1of1ForFork1_~_.base=v_thr1Thread1of1ForFork1_~_.base_4, thr1Thread1of1ForFork1_~b21~0=v_thr1Thread1of1ForFork1_~b21~0_10, thr1Thread1of1ForFork1_#res.base=|v_thr1Thread1of1ForFork1_#res.base_4|, thr1Thread1of1ForFork1_~y1~0=v_thr1Thread1of1ForFork1_~y1~0_30, thr1Thread1of1ForFork1_#in~_.base=|v_thr1Thread1of1ForFork1_#in~_.base_4|, thr1Thread1of1ForFork1_~_.offset=v_thr1Thread1of1ForFork1_~_.offset_4, thr1Thread1of1ForFork1_#res.offset=|v_thr1Thread1of1ForFork1_#res.offset_4|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_6|, thr1Thread1of1ForFork1_thidvar1=v_thr1Thread1of1ForFork1_thidvar1_2, thr1Thread1of1ForFork1_thidvar0=v_thr1Thread1of1ForFork1_thidvar0_2, thr1Thread1of1ForFork1_~x1~0=v_thr1Thread1of1ForFork1_~x1~0_8} AuxVars[] AssignedVars[thr1Thread1of1ForFork1_#in~_.offset, thr1Thread1of1ForFork1_~_.base, thr1Thread1of1ForFork1_~b21~0, thr1Thread1of1ForFork1_#res.base, thr1Thread1of1ForFork1_~y1~0, thr1Thread1of1ForFork1_#in~_.base, thr1Thread1of1ForFork1_~_.offset, thr1Thread1of1ForFork1_#res.offset, thr1Thread1of1ForFork1_thidvar1, thr1Thread1of1ForFork1_thidvar0, thr1Thread1of1ForFork1_~x1~0] 49906#[thr1ENTRY, L845-3]don't care [402] thr1ENTRY-->L704loopEntry: Formula: (and (= v_thr1Thread1of1ForFork1_~_.base_1 |v_thr1Thread1of1ForFork1_#in~_.base_1|) (= |v_thr1Thread1of1ForFork1_#in~_.offset_1| v_thr1Thread1of1ForFork1_~_.offset_1)) InVars {thr1Thread1of1ForFork1_#in~_.offset=|v_thr1Thread1of1ForFork1_#in~_.offset_1|, thr1Thread1of1ForFork1_#in~_.base=|v_thr1Thread1of1ForFork1_#in~_.base_1|} OutVars{thr1Thread1of1ForFork1_#in~_.offset=|v_thr1Thread1of1ForFork1_#in~_.offset_1|, thr1Thread1of1ForFork1_#in~_.base=|v_thr1Thread1of1ForFork1_#in~_.base_1|, thr1Thread1of1ForFork1_~_.offset=v_thr1Thread1of1ForFork1_~_.offset_1, thr1Thread1of1ForFork1_~_.base=v_thr1Thread1of1ForFork1_~_.base_1} AuxVars[] AssignedVars[thr1Thread1of1ForFork1_~_.base, thr1Thread1of1ForFork1_~_.offset] 51560#[L704loopEntry, L845-3]don't care [403] L704loopEntry-->L753-1: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 49226#[L753-1, L845-3]don't care [406] L753-1-->L705: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 49228#[L845-3, L705]don't care [408] L705-->L707: Formula: (= v_~b1~0_4 1) InVars {} OutVars{~b1~0=v_~b1~0_4} AuxVars[] AssignedVars[~b1~0] 48144#[L845-3, L707]don't care [411] L707-->L710: Formula: (= v_~x~0_3 1) InVars {} OutVars{~x~0=v_~x~0_3} AuxVars[] AssignedVars[~x~0] 47184#[L710, L845-3]don't care [414] L710-->L713: Formula: (= v_~y~0_12 v_thr1Thread1of1ForFork1_~y1~0_1) InVars {~y~0=v_~y~0_12} OutVars{~y~0=v_~y~0_12, thr1Thread1of1ForFork1_~y1~0=v_thr1Thread1of1ForFork1_~y1~0_1} AuxVars[] AssignedVars[thr1Thread1of1ForFork1_~y1~0] 47186#[L845-3, L713]don't care [416] L713-->L715: Formula: (not (= v_thr1Thread1of1ForFork1_~y1~0_3 0)) InVars {thr1Thread1of1ForFork1_~y1~0=v_thr1Thread1of1ForFork1_~y1~0_3} OutVars{thr1Thread1of1ForFork1_~y1~0=v_thr1Thread1of1ForFork1_~y1~0_3} AuxVars[] AssignedVars[] 48260#[L845-3, L715]don't care [419] L715-->L717: Formula: (= v_~b1~0_5 0) InVars {} OutVars{~b1~0=v_~b1~0_5} AuxVars[] AssignedVars[~b1~0] 51056#[L845-3, L717]don't care [422] L717-->L724: Formula: (= v_~y~0_13 v_thr1Thread1of1ForFork1_~y1~0_7) InVars {~y~0=v_~y~0_13} OutVars{~y~0=v_~y~0_13, thr1Thread1of1ForFork1_~y1~0=v_thr1Thread1of1ForFork1_~y1~0_7} AuxVars[] AssignedVars[thr1Thread1of1ForFork1_~y1~0] 51000#[L845-3, L724]don't care [2022-07-26 13:22:15,931 INFO L735 eck$LassoCheckResult]: Loop: 51000#[L845-3, L724]don't care [426] L724-->L722: Formula: (not (= v_thr1Thread1of1ForFork1_~y1~0_11 0)) InVars {thr1Thread1of1ForFork1_~y1~0=v_thr1Thread1of1ForFork1_~y1~0_11} OutVars{thr1Thread1of1ForFork1_~y1~0=v_thr1Thread1of1ForFork1_~y1~0_11} AuxVars[] AssignedVars[] 50996#[L845-3, L722]don't care [429] L722-->L724: Formula: (= v_thr1Thread1of1ForFork1_~y1~0_13 v_~y~0_15) InVars {~y~0=v_~y~0_15} OutVars{~y~0=v_~y~0_15, thr1Thread1of1ForFork1_~y1~0=v_thr1Thread1of1ForFork1_~y1~0_13} AuxVars[] AssignedVars[thr1Thread1of1ForFork1_~y1~0] 51000#[L845-3, L724]don't care [2022-07-26 13:22:15,931 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:15,931 INFO L85 PathProgramCache]: Analyzing trace with hash -2097385762, now seen corresponding path program 1 times [2022-07-26 13:22:15,932 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:15,932 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2092744411] [2022-07-26 13:22:15,932 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:15,932 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:15,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-26 13:22:15,981 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-26 13:22:15,981 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-26 13:22:15,981 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2092744411] [2022-07-26 13:22:15,982 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2092744411] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-26 13:22:15,982 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-26 13:22:15,983 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-26 13:22:15,983 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [880760283] [2022-07-26 13:22:15,984 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-26 13:22:15,987 INFO L738 eck$LassoCheckResult]: stem already infeasible [2022-07-26 13:22:15,988 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:15,988 INFO L85 PathProgramCache]: Analyzing trace with hash 14596, now seen corresponding path program 1 times [2022-07-26 13:22:15,989 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:15,989 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1291271140] [2022-07-26 13:22:15,989 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:15,989 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:15,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:15,997 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-26 13:22:16,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:16,002 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-26 13:22:16,023 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-26 13:22:16,025 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-26 13:22:16,025 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-26 13:22:16,025 INFO L87 Difference]: Start difference. First operand 4651 states and 13232 transitions. cyclomatic complexity: 9295 Second operand has 4 states, 4 states have (on average 8.0) internal successors, (32), 4 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-26 13:22:16,180 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-26 13:22:16,180 INFO L93 Difference]: Finished difference Result 5773 states and 15950 transitions. [2022-07-26 13:22:16,180 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5773 states and 15950 transitions. [2022-07-26 13:22:16,230 INFO L131 ngComponentsAnalysis]: Automaton has 802 accepting balls. 1668 [2022-07-26 13:22:16,260 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5773 states to 5773 states and 15950 transitions. [2022-07-26 13:22:16,261 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5773 [2022-07-26 13:22:16,267 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5773 [2022-07-26 13:22:16,267 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5773 states and 15950 transitions. [2022-07-26 13:22:16,276 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-26 13:22:16,277 INFO L220 hiAutomatonCegarLoop]: Abstraction has 5773 states and 15950 transitions. [2022-07-26 13:22:16,290 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5773 states and 15950 transitions. [2022-07-26 13:22:16,447 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5773 to 4355. [2022-07-26 13:22:16,470 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4355 states, 4355 states have (on average 2.815614236509759) internal successors, (12262), 4354 states have internal predecessors, (12262), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-26 13:22:16,485 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4355 states to 4355 states and 12262 transitions. [2022-07-26 13:22:16,485 INFO L242 hiAutomatonCegarLoop]: Abstraction has 4355 states and 12262 transitions. [2022-07-26 13:22:16,486 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-07-26 13:22:16,486 INFO L426 stractBuchiCegarLoop]: Abstraction has 4355 states and 12262 transitions. [2022-07-26 13:22:16,487 INFO L333 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-07-26 13:22:16,487 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4355 states and 12262 transitions. [2022-07-26 13:22:16,509 INFO L131 ngComponentsAnalysis]: Automaton has 640 accepting balls. 1344 [2022-07-26 13:22:16,509 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-26 13:22:16,510 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-26 13:22:16,511 INFO L150 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-26 13:22:16,511 INFO L151 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-07-26 13:22:16,512 INFO L733 eck$LassoCheckResult]: Stem: 65966#[ULTIMATE.startENTRY]don't care [341] ULTIMATE.startENTRY-->L-1: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 65968#[L-1]don't care [266] L-1-->L-1-1: Formula: (and (= |v_#NULL.base_1| 0) (= |v_#NULL.offset_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] 61482#[L-1-1]don't care [350] L-1-1-->L-1-2: Formula: (= 0 (select |v_#valid_13| 0)) InVars {#valid=|v_#valid_13|} OutVars{#valid=|v_#valid_13|} AuxVars[] AssignedVars[] 61484#[L-1-2]don't care [352] L-1-2-->L12: Formula: (< 0 |v_#StackHeapBarrier_3|) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_3|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_3|} AuxVars[] AssignedVars[] 66144#[L12]don't care [305] L12-->L12-1: Formula: (and (= (select |v_#length_9| 1) 2) (= (select |v_#valid_14| 1) 1)) InVars {#length=|v_#length_9|, #valid=|v_#valid_14|} OutVars{#length=|v_#length_9|, #valid=|v_#valid_14|} AuxVars[] AssignedVars[] 64278#[L12-1]don't care [320] L12-1-->L12-2: Formula: (= (select (select |v_#memory_int_7| 1) 0) 48) InVars {#memory_int=|v_#memory_int_7|} OutVars{#memory_int=|v_#memory_int_7|} AuxVars[] AssignedVars[] 64280#[L12-2]don't care [319] L12-2-->L12-3: Formula: (= (select (select |v_#memory_int_8| 1) 1) 0) InVars {#memory_int=|v_#memory_int_8|} OutVars{#memory_int=|v_#memory_int_8|} AuxVars[] AssignedVars[] 63658#[L12-3]don't care [343] L12-3-->L12-4: Formula: (and (= (select |v_#length_10| 2) 10) (= (select |v_#valid_15| 2) 1)) InVars {#length=|v_#length_10|, #valid=|v_#valid_15|} OutVars{#length=|v_#length_10|, #valid=|v_#valid_15|} AuxVars[] AssignedVars[] 63660#[L12-4]don't care [336] L12-4-->L700: Formula: (= v_~x~0_5 0) InVars {} OutVars{~x~0=v_~x~0_5} AuxVars[] AssignedVars[~x~0] 62728#[L700]don't care [280] L700-->L701: Formula: (= v_~y~0_17 0) InVars {} OutVars{~y~0=v_~y~0_17} AuxVars[] AssignedVars[~y~0] 62730#[L701]don't care [348] L701-->L701-1: Formula: (= v_~b1~0_7 0) InVars {} OutVars{~b1~0=v_~b1~0_7} AuxVars[] AssignedVars[~b1~0] 66208#[L701-1]don't care [247] L701-1-->L702: Formula: (= v_~b2~0_7 0) InVars {} OutVars{~b2~0=v_~b2~0_7} AuxVars[] AssignedVars[~b2~0] 62132#[L702]don't care [251] L702-->L-1-3: Formula: (= v_~X~0_7 0) InVars {} OutVars{~X~0=v_~X~0_7} AuxVars[] AssignedVars[~X~0] 62134#[L-1-3]don't care [353] L-1-3-->L-1-4: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 62508#[L-1-4]don't care [272] L-1-4-->L-1-5: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 65490#[L-1-5]don't care [242] L-1-5-->L-1-6: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res#1=|v_ULTIMATE.start_main_#res#1_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res#1] 65722#[L-1-6]don't care [335] L-1-6-->L844: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~pre6#1=|v_ULTIMATE.start_main_#t~pre6#1_1|, ULTIMATE.start_main_#t~mem8#1=|v_ULTIMATE.start_main_#t~mem8#1_1|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_1|, ULTIMATE.start_main_#t~nondet5#1=|v_ULTIMATE.start_main_#t~nondet5#1_1|, ULTIMATE.start_main_#t~nondet7#1=|v_ULTIMATE.start_main_#t~nondet7#1_1|, ULTIMATE.start_main_#t~mem9#1=|v_ULTIMATE.start_main_#t~mem9#1_1|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_1|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_1|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_1|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre6#1, ULTIMATE.start_main_#t~mem8#1, ULTIMATE.start_main_~#t2~0#1.offset, ULTIMATE.start_main_#t~nondet5#1, ULTIMATE.start_main_#t~nondet7#1, ULTIMATE.start_main_#t~mem9#1, ULTIMATE.start_main_~#t1~0#1.base, ULTIMATE.start_main_#t~pre4#1, ULTIMATE.start_main_~#t1~0#1.offset, ULTIMATE.start_main_~#t2~0#1.base] 65724#[L844]don't care [293] L844-->L844-1: Formula: (and (= (store |v_#valid_2| |v_ULTIMATE.start_main_~#t1~0#1.base_2| 1) |v_#valid_1|) (= |v_ULTIMATE.start_main_~#t1~0#1.offset_2| 0) (= (select |v_#valid_2| |v_ULTIMATE.start_main_~#t1~0#1.base_2|) 0) (< |v_#StackHeapBarrier_1| |v_ULTIMATE.start_main_~#t1~0#1.base_2|) (= (store |v_#length_2| |v_ULTIMATE.start_main_~#t1~0#1.base_2| 4) |v_#length_1|) (not (= |v_ULTIMATE.start_main_~#t1~0#1.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_2|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_2|, #valid=|v_#valid_1|} AuxVars[] AssignedVars[#valid, #length, ULTIMATE.start_main_~#t1~0#1.base, ULTIMATE.start_main_~#t1~0#1.offset] 61722#[L844-1]don't care [279] L844-1-->L844-2: Formula: (and (< |v_#StackHeapBarrier_2| |v_ULTIMATE.start_main_~#t2~0#1.base_2|) (not (= |v_ULTIMATE.start_main_~#t2~0#1.base_2| 0)) (= |v_#length_3| (store |v_#length_4| |v_ULTIMATE.start_main_~#t2~0#1.base_2| 4)) (= 0 |v_ULTIMATE.start_main_~#t2~0#1.offset_2|) (= (store |v_#valid_4| |v_ULTIMATE.start_main_~#t2~0#1.base_2| 1) |v_#valid_3|) (= (select |v_#valid_4| |v_ULTIMATE.start_main_~#t2~0#1.base_2|) 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_4|, #valid=|v_#valid_4|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_2|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_2|, #valid=|v_#valid_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2~0#1.offset, #valid, #length, ULTIMATE.start_main_~#t2~0#1.base] 61724#[L844-2]don't care [313] L844-2-->L845: Formula: (= |v_ULTIMATE.start_main_#t~pre4#1_2| |v_#pthreadsForks_1|) InVars {#pthreadsForks=|v_#pthreadsForks_1|} OutVars{#pthreadsForks=|v_#pthreadsForks_1|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre4#1] 62342#[L845]don't care [340] L845-->L845-1: Formula: (= (+ 1 |v_#pthreadsForks_3|) |v_#pthreadsForks_2|) InVars {#pthreadsForks=|v_#pthreadsForks_3|} OutVars{#pthreadsForks=|v_#pthreadsForks_2|} AuxVars[] AssignedVars[#pthreadsForks] 64384#[L845-1]don't care [244] L845-1-->L845-2: Formula: (and (<= 0 |v_ULTIMATE.start_main_~#t1~0#1.offset_3|) (= (select |v_#valid_5| |v_ULTIMATE.start_main_~#t1~0#1.base_3|) 1) (= (store |v_#memory_int_2| |v_ULTIMATE.start_main_~#t1~0#1.base_3| (store (select |v_#memory_int_2| |v_ULTIMATE.start_main_~#t1~0#1.base_3|) |v_ULTIMATE.start_main_~#t1~0#1.offset_3| |v_ULTIMATE.start_main_#t~pre4#1_3|)) |v_#memory_int_1|) (<= (+ |v_ULTIMATE.start_main_~#t1~0#1.offset_3| 4) (select |v_#length_5| |v_ULTIMATE.start_main_~#t1~0#1.base_3|))) InVars {#valid=|v_#valid_5|, #memory_int=|v_#memory_int_2|, #length=|v_#length_5|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_3|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_3|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_3|} OutVars{#valid=|v_#valid_5|, #memory_int=|v_#memory_int_1|, #length=|v_#length_5|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_3|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_3|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_3|} AuxVars[] AssignedVars[#memory_int] 64386#[L845-2]don't care [449] L845-2-->thr1ENTRY: Formula: (and (= v_thr1Thread1of1ForFork1_thidvar1_2 0) (= |v_ULTIMATE.start_main_#t~pre4#1_6| v_thr1Thread1of1ForFork1_thidvar0_2) (= |v_thr1Thread1of1ForFork1_#in~_.base_4| 0) (= |v_thr1Thread1of1ForFork1_#in~_.offset_4| 0)) InVars {ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_6|} OutVars{thr1Thread1of1ForFork1_#in~_.offset=|v_thr1Thread1of1ForFork1_#in~_.offset_4|, thr1Thread1of1ForFork1_~_.base=v_thr1Thread1of1ForFork1_~_.base_4, thr1Thread1of1ForFork1_~b21~0=v_thr1Thread1of1ForFork1_~b21~0_10, thr1Thread1of1ForFork1_#res.base=|v_thr1Thread1of1ForFork1_#res.base_4|, thr1Thread1of1ForFork1_~y1~0=v_thr1Thread1of1ForFork1_~y1~0_30, thr1Thread1of1ForFork1_#in~_.base=|v_thr1Thread1of1ForFork1_#in~_.base_4|, thr1Thread1of1ForFork1_~_.offset=v_thr1Thread1of1ForFork1_~_.offset_4, thr1Thread1of1ForFork1_#res.offset=|v_thr1Thread1of1ForFork1_#res.offset_4|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_6|, thr1Thread1of1ForFork1_thidvar1=v_thr1Thread1of1ForFork1_thidvar1_2, thr1Thread1of1ForFork1_thidvar0=v_thr1Thread1of1ForFork1_thidvar0_2, thr1Thread1of1ForFork1_~x1~0=v_thr1Thread1of1ForFork1_~x1~0_8} AuxVars[] AssignedVars[thr1Thread1of1ForFork1_#in~_.offset, thr1Thread1of1ForFork1_~_.base, thr1Thread1of1ForFork1_~b21~0, thr1Thread1of1ForFork1_#res.base, thr1Thread1of1ForFork1_~y1~0, thr1Thread1of1ForFork1_#in~_.base, thr1Thread1of1ForFork1_~_.offset, thr1Thread1of1ForFork1_#res.offset, thr1Thread1of1ForFork1_thidvar1, thr1Thread1of1ForFork1_thidvar0, thr1Thread1of1ForFork1_~x1~0] 64568#[thr1ENTRY, L845-3]don't care [402] thr1ENTRY-->L704loopEntry: Formula: (and (= v_thr1Thread1of1ForFork1_~_.base_1 |v_thr1Thread1of1ForFork1_#in~_.base_1|) (= |v_thr1Thread1of1ForFork1_#in~_.offset_1| v_thr1Thread1of1ForFork1_~_.offset_1)) InVars {thr1Thread1of1ForFork1_#in~_.offset=|v_thr1Thread1of1ForFork1_#in~_.offset_1|, thr1Thread1of1ForFork1_#in~_.base=|v_thr1Thread1of1ForFork1_#in~_.base_1|} OutVars{thr1Thread1of1ForFork1_#in~_.offset=|v_thr1Thread1of1ForFork1_#in~_.offset_1|, thr1Thread1of1ForFork1_#in~_.base=|v_thr1Thread1of1ForFork1_#in~_.base_1|, thr1Thread1of1ForFork1_~_.offset=v_thr1Thread1of1ForFork1_~_.offset_1, thr1Thread1of1ForFork1_~_.base=v_thr1Thread1of1ForFork1_~_.base_1} AuxVars[] AssignedVars[thr1Thread1of1ForFork1_~_.base, thr1Thread1of1ForFork1_~_.offset] 66090#[L704loopEntry, L845-3]don't care [403] L704loopEntry-->L753-1: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 63936#[L753-1, L845-3]don't care [406] L753-1-->L705: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 63938#[L845-3, L705]don't care [408] L705-->L707: Formula: (= v_~b1~0_4 1) InVars {} OutVars{~b1~0=v_~b1~0_4} AuxVars[] AssignedVars[~b1~0] 62930#[L845-3, L707]don't care [411] L707-->L710: Formula: (= v_~x~0_3 1) InVars {} OutVars{~x~0=v_~x~0_3} AuxVars[] AssignedVars[~x~0] 62022#[L710, L845-3]don't care [414] L710-->L713: Formula: (= v_~y~0_12 v_thr1Thread1of1ForFork1_~y1~0_1) InVars {~y~0=v_~y~0_12} OutVars{~y~0=v_~y~0_12, thr1Thread1of1ForFork1_~y1~0=v_thr1Thread1of1ForFork1_~y1~0_1} AuxVars[] AssignedVars[thr1Thread1of1ForFork1_~y1~0] 62024#[L845-3, L713]don't care [417] L713-->L728: Formula: (= v_thr1Thread1of1ForFork1_~y1~0_5 0) InVars {thr1Thread1of1ForFork1_~y1~0=v_thr1Thread1of1ForFork1_~y1~0_5} OutVars{thr1Thread1of1ForFork1_~y1~0=v_thr1Thread1of1ForFork1_~y1~0_5} AuxVars[] AssignedVars[] 63040#[L845-3, L728]don't care [420] L728-->L730: Formula: (= v_~y~0_16 1) InVars {} OutVars{~y~0=v_~y~0_16} AuxVars[] AssignedVars[~y~0] 62598#[L730, L845-3]don't care [423] L730-->L733: Formula: (= v_thr1Thread1of1ForFork1_~x1~0_1 v_~x~0_4) InVars {~x~0=v_~x~0_4} OutVars{~x~0=v_~x~0_4, thr1Thread1of1ForFork1_~x1~0=v_thr1Thread1of1ForFork1_~x1~0_1} AuxVars[] AssignedVars[thr1Thread1of1ForFork1_~x1~0] 62600#[L845-3, L733]don't care [427] L733-->L735: Formula: (not (= v_thr1Thread1of1ForFork1_~x1~0_3 1)) InVars {thr1Thread1of1ForFork1_~x1~0=v_thr1Thread1of1ForFork1_~x1~0_3} OutVars{thr1Thread1of1ForFork1_~x1~0=v_thr1Thread1of1ForFork1_~x1~0_3} AuxVars[] AssignedVars[] 65324#[L845-3, L735]don't care [430] L735-->L737: Formula: (= v_~b1~0_3 0) InVars {} OutVars{~b1~0=v_~b1~0_3} AuxVars[] AssignedVars[~b1~0] 65326#[L845-3, L737]don't care [431] L737-->L744: Formula: (= v_~b2~0_5 v_thr1Thread1of1ForFork1_~b21~0_1) InVars {~b2~0=v_~b2~0_5} OutVars{~b2~0=v_~b2~0_5, thr1Thread1of1ForFork1_~b21~0=v_thr1Thread1of1ForFork1_~b21~0_1} AuxVars[] AssignedVars[thr1Thread1of1ForFork1_~b21~0] 64030#[L845-3, L744]don't care [2022-07-26 13:22:16,512 INFO L735 eck$LassoCheckResult]: Loop: 64030#[L845-3, L744]don't care [434] L744-->L742: Formula: (<= 1 v_thr1Thread1of1ForFork1_~b21~0_5) InVars {thr1Thread1of1ForFork1_~b21~0=v_thr1Thread1of1ForFork1_~b21~0_5} OutVars{thr1Thread1of1ForFork1_~b21~0=v_thr1Thread1of1ForFork1_~b21~0_5} AuxVars[] AssignedVars[] 64034#[L845-3, L742]don't care [436] L742-->L744: Formula: (= v_~b2~0_6 v_thr1Thread1of1ForFork1_~b21~0_7) InVars {~b2~0=v_~b2~0_6} OutVars{~b2~0=v_~b2~0_6, thr1Thread1of1ForFork1_~b21~0=v_thr1Thread1of1ForFork1_~b21~0_7} AuxVars[] AssignedVars[thr1Thread1of1ForFork1_~b21~0] 64030#[L845-3, L744]don't care [2022-07-26 13:22:16,513 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:16,513 INFO L85 PathProgramCache]: Analyzing trace with hash -5006963, now seen corresponding path program 1 times [2022-07-26 13:22:16,513 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:16,514 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [307971694] [2022-07-26 13:22:16,514 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:16,514 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:16,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-26 13:22:16,567 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-26 13:22:16,567 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-26 13:22:16,567 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [307971694] [2022-07-26 13:22:16,567 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [307971694] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-26 13:22:16,568 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-26 13:22:16,568 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-26 13:22:16,568 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [424182836] [2022-07-26 13:22:16,568 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-26 13:22:16,568 INFO L738 eck$LassoCheckResult]: stem already infeasible [2022-07-26 13:22:16,569 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:16,569 INFO L85 PathProgramCache]: Analyzing trace with hash 14851, now seen corresponding path program 1 times [2022-07-26 13:22:16,569 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:16,569 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [43784684] [2022-07-26 13:22:16,569 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:16,569 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:16,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:16,573 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-26 13:22:16,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:16,577 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-26 13:22:16,589 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-26 13:22:16,589 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-26 13:22:16,590 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-26 13:22:16,590 INFO L87 Difference]: Start difference. First operand 4355 states and 12262 transitions. cyclomatic complexity: 8547 Second operand has 4 states, 4 states have (on average 8.75) internal successors, (35), 4 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-26 13:22:16,657 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-26 13:22:16,657 INFO L93 Difference]: Finished difference Result 7277 states and 20080 transitions. [2022-07-26 13:22:16,657 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7277 states and 20080 transitions. [2022-07-26 13:22:16,783 INFO L131 ngComponentsAnalysis]: Automaton has 976 accepting balls. 2032 [2022-07-26 13:22:16,829 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7277 states to 6685 states and 18500 transitions. [2022-07-26 13:22:16,829 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6685 [2022-07-26 13:22:16,836 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6685 [2022-07-26 13:22:16,837 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6685 states and 18500 transitions. [2022-07-26 13:22:16,846 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-26 13:22:16,847 INFO L220 hiAutomatonCegarLoop]: Abstraction has 6685 states and 18500 transitions. [2022-07-26 13:22:16,861 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6685 states and 18500 transitions. [2022-07-26 13:22:16,939 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6685 to 4217. [2022-07-26 13:22:16,948 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4217 states, 4217 states have (on average 2.8183542802940478) internal successors, (11885), 4216 states have internal predecessors, (11885), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-26 13:22:16,963 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4217 states to 4217 states and 11885 transitions. [2022-07-26 13:22:16,963 INFO L242 hiAutomatonCegarLoop]: Abstraction has 4217 states and 11885 transitions. [2022-07-26 13:22:16,963 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-07-26 13:22:16,964 INFO L426 stractBuchiCegarLoop]: Abstraction has 4217 states and 11885 transitions. [2022-07-26 13:22:16,964 INFO L333 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-07-26 13:22:16,964 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4217 states and 11885 transitions. [2022-07-26 13:22:16,987 INFO L131 ngComponentsAnalysis]: Automaton has 644 accepting balls. 1352 [2022-07-26 13:22:16,988 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-26 13:22:16,988 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-26 13:22:16,988 INFO L150 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-26 13:22:16,988 INFO L151 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-07-26 13:22:16,989 INFO L733 eck$LassoCheckResult]: Stem: 81146#[ULTIMATE.startENTRY]don't care [341] ULTIMATE.startENTRY-->L-1: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 81148#[L-1]don't care [266] L-1-->L-1-1: Formula: (and (= |v_#NULL.base_1| 0) (= |v_#NULL.offset_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] 77106#[L-1-1]don't care [350] L-1-1-->L-1-2: Formula: (= 0 (select |v_#valid_13| 0)) InVars {#valid=|v_#valid_13|} OutVars{#valid=|v_#valid_13|} AuxVars[] AssignedVars[] 77108#[L-1-2]don't care [352] L-1-2-->L12: Formula: (< 0 |v_#StackHeapBarrier_3|) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_3|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_3|} AuxVars[] AssignedVars[] 81316#[L12]don't care [305] L12-->L12-1: Formula: (and (= (select |v_#length_9| 1) 2) (= (select |v_#valid_14| 1) 1)) InVars {#length=|v_#length_9|, #valid=|v_#valid_14|} OutVars{#length=|v_#length_9|, #valid=|v_#valid_14|} AuxVars[] AssignedVars[] 79610#[L12-1]don't care [320] L12-1-->L12-2: Formula: (= (select (select |v_#memory_int_7| 1) 0) 48) InVars {#memory_int=|v_#memory_int_7|} OutVars{#memory_int=|v_#memory_int_7|} AuxVars[] AssignedVars[] 79612#[L12-2]don't care [319] L12-2-->L12-3: Formula: (= (select (select |v_#memory_int_8| 1) 1) 0) InVars {#memory_int=|v_#memory_int_8|} OutVars{#memory_int=|v_#memory_int_8|} AuxVars[] AssignedVars[] 79050#[L12-3]don't care [343] L12-3-->L12-4: Formula: (and (= (select |v_#length_10| 2) 10) (= (select |v_#valid_15| 2) 1)) InVars {#length=|v_#length_10|, #valid=|v_#valid_15|} OutVars{#length=|v_#length_10|, #valid=|v_#valid_15|} AuxVars[] AssignedVars[] 79052#[L12-4]don't care [336] L12-4-->L700: Formula: (= v_~x~0_5 0) InVars {} OutVars{~x~0=v_~x~0_5} AuxVars[] AssignedVars[~x~0] 78204#[L700]don't care [280] L700-->L701: Formula: (= v_~y~0_17 0) InVars {} OutVars{~y~0=v_~y~0_17} AuxVars[] AssignedVars[~y~0] 78206#[L701]don't care [348] L701-->L701-1: Formula: (= v_~b1~0_7 0) InVars {} OutVars{~b1~0=v_~b1~0_7} AuxVars[] AssignedVars[~b1~0] 81380#[L701-1]don't care [247] L701-1-->L702: Formula: (= v_~b2~0_7 0) InVars {} OutVars{~b2~0=v_~b2~0_7} AuxVars[] AssignedVars[~b2~0] 77688#[L702]don't care [251] L702-->L-1-3: Formula: (= v_~X~0_7 0) InVars {} OutVars{~X~0=v_~X~0_7} AuxVars[] AssignedVars[~X~0] 77690#[L-1-3]don't care [353] L-1-3-->L-1-4: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 78010#[L-1-4]don't care [272] L-1-4-->L-1-5: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 80712#[L-1-5]don't care [242] L-1-5-->L-1-6: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res#1=|v_ULTIMATE.start_main_#res#1_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res#1] 80920#[L-1-6]don't care [335] L-1-6-->L844: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~pre6#1=|v_ULTIMATE.start_main_#t~pre6#1_1|, ULTIMATE.start_main_#t~mem8#1=|v_ULTIMATE.start_main_#t~mem8#1_1|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_1|, ULTIMATE.start_main_#t~nondet5#1=|v_ULTIMATE.start_main_#t~nondet5#1_1|, ULTIMATE.start_main_#t~nondet7#1=|v_ULTIMATE.start_main_#t~nondet7#1_1|, ULTIMATE.start_main_#t~mem9#1=|v_ULTIMATE.start_main_#t~mem9#1_1|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_1|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_1|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_1|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre6#1, ULTIMATE.start_main_#t~mem8#1, ULTIMATE.start_main_~#t2~0#1.offset, ULTIMATE.start_main_#t~nondet5#1, ULTIMATE.start_main_#t~nondet7#1, ULTIMATE.start_main_#t~mem9#1, ULTIMATE.start_main_~#t1~0#1.base, ULTIMATE.start_main_#t~pre4#1, ULTIMATE.start_main_~#t1~0#1.offset, ULTIMATE.start_main_~#t2~0#1.base] 80922#[L844]don't care [293] L844-->L844-1: Formula: (and (= (store |v_#valid_2| |v_ULTIMATE.start_main_~#t1~0#1.base_2| 1) |v_#valid_1|) (= |v_ULTIMATE.start_main_~#t1~0#1.offset_2| 0) (= (select |v_#valid_2| |v_ULTIMATE.start_main_~#t1~0#1.base_2|) 0) (< |v_#StackHeapBarrier_1| |v_ULTIMATE.start_main_~#t1~0#1.base_2|) (= (store |v_#length_2| |v_ULTIMATE.start_main_~#t1~0#1.base_2| 4) |v_#length_1|) (not (= |v_ULTIMATE.start_main_~#t1~0#1.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_2|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_2|, #valid=|v_#valid_1|} AuxVars[] AssignedVars[#valid, #length, ULTIMATE.start_main_~#t1~0#1.base, ULTIMATE.start_main_~#t1~0#1.offset] 77322#[L844-1]don't care [279] L844-1-->L844-2: Formula: (and (< |v_#StackHeapBarrier_2| |v_ULTIMATE.start_main_~#t2~0#1.base_2|) (not (= |v_ULTIMATE.start_main_~#t2~0#1.base_2| 0)) (= |v_#length_3| (store |v_#length_4| |v_ULTIMATE.start_main_~#t2~0#1.base_2| 4)) (= 0 |v_ULTIMATE.start_main_~#t2~0#1.offset_2|) (= (store |v_#valid_4| |v_ULTIMATE.start_main_~#t2~0#1.base_2| 1) |v_#valid_3|) (= (select |v_#valid_4| |v_ULTIMATE.start_main_~#t2~0#1.base_2|) 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_4|, #valid=|v_#valid_4|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_2|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_2|, #valid=|v_#valid_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2~0#1.offset, #valid, #length, ULTIMATE.start_main_~#t2~0#1.base] 77324#[L844-2]don't care [313] L844-2-->L845: Formula: (= |v_ULTIMATE.start_main_#t~pre4#1_2| |v_#pthreadsForks_1|) InVars {#pthreadsForks=|v_#pthreadsForks_1|} OutVars{#pthreadsForks=|v_#pthreadsForks_1|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre4#1] 77852#[L845]don't care [340] L845-->L845-1: Formula: (= (+ 1 |v_#pthreadsForks_3|) |v_#pthreadsForks_2|) InVars {#pthreadsForks=|v_#pthreadsForks_3|} OutVars{#pthreadsForks=|v_#pthreadsForks_2|} AuxVars[] AssignedVars[#pthreadsForks] 79700#[L845-1]don't care [244] L845-1-->L845-2: Formula: (and (<= 0 |v_ULTIMATE.start_main_~#t1~0#1.offset_3|) (= (select |v_#valid_5| |v_ULTIMATE.start_main_~#t1~0#1.base_3|) 1) (= (store |v_#memory_int_2| |v_ULTIMATE.start_main_~#t1~0#1.base_3| (store (select |v_#memory_int_2| |v_ULTIMATE.start_main_~#t1~0#1.base_3|) |v_ULTIMATE.start_main_~#t1~0#1.offset_3| |v_ULTIMATE.start_main_#t~pre4#1_3|)) |v_#memory_int_1|) (<= (+ |v_ULTIMATE.start_main_~#t1~0#1.offset_3| 4) (select |v_#length_5| |v_ULTIMATE.start_main_~#t1~0#1.base_3|))) InVars {#valid=|v_#valid_5|, #memory_int=|v_#memory_int_2|, #length=|v_#length_5|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_3|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_3|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_3|} OutVars{#valid=|v_#valid_5|, #memory_int=|v_#memory_int_1|, #length=|v_#length_5|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_3|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_3|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_3|} AuxVars[] AssignedVars[#memory_int] 79702#[L845-2]don't care [449] L845-2-->thr1ENTRY: Formula: (and (= v_thr1Thread1of1ForFork1_thidvar1_2 0) (= |v_ULTIMATE.start_main_#t~pre4#1_6| v_thr1Thread1of1ForFork1_thidvar0_2) (= |v_thr1Thread1of1ForFork1_#in~_.base_4| 0) (= |v_thr1Thread1of1ForFork1_#in~_.offset_4| 0)) InVars {ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_6|} OutVars{thr1Thread1of1ForFork1_#in~_.offset=|v_thr1Thread1of1ForFork1_#in~_.offset_4|, thr1Thread1of1ForFork1_~_.base=v_thr1Thread1of1ForFork1_~_.base_4, thr1Thread1of1ForFork1_~b21~0=v_thr1Thread1of1ForFork1_~b21~0_10, thr1Thread1of1ForFork1_#res.base=|v_thr1Thread1of1ForFork1_#res.base_4|, thr1Thread1of1ForFork1_~y1~0=v_thr1Thread1of1ForFork1_~y1~0_30, thr1Thread1of1ForFork1_#in~_.base=|v_thr1Thread1of1ForFork1_#in~_.base_4|, thr1Thread1of1ForFork1_~_.offset=v_thr1Thread1of1ForFork1_~_.offset_4, thr1Thread1of1ForFork1_#res.offset=|v_thr1Thread1of1ForFork1_#res.offset_4|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_6|, thr1Thread1of1ForFork1_thidvar1=v_thr1Thread1of1ForFork1_thidvar1_2, thr1Thread1of1ForFork1_thidvar0=v_thr1Thread1of1ForFork1_thidvar0_2, thr1Thread1of1ForFork1_~x1~0=v_thr1Thread1of1ForFork1_~x1~0_8} AuxVars[] AssignedVars[thr1Thread1of1ForFork1_#in~_.offset, thr1Thread1of1ForFork1_~_.base, thr1Thread1of1ForFork1_~b21~0, thr1Thread1of1ForFork1_#res.base, thr1Thread1of1ForFork1_~y1~0, thr1Thread1of1ForFork1_#in~_.base, thr1Thread1of1ForFork1_~_.offset, thr1Thread1of1ForFork1_#res.offset, thr1Thread1of1ForFork1_thidvar1, thr1Thread1of1ForFork1_thidvar0, thr1Thread1of1ForFork1_~x1~0] 79872#[thr1ENTRY, L845-3]don't care [328] L845-3-->L845-4: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre4#1] 81398#[thr1ENTRY, L845-4]don't care [259] L845-4-->L846: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet5#1=|v_ULTIMATE.start_main_#t~nondet5#1_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet5#1] 80438#[thr1ENTRY, L846]don't care [243] L846-->L846-1: Formula: (= |v_ULTIMATE.start_main_#t~pre6#1_2| |v_#pthreadsForks_4|) InVars {#pthreadsForks=|v_#pthreadsForks_4|} OutVars{#pthreadsForks=|v_#pthreadsForks_4|, ULTIMATE.start_main_#t~pre6#1=|v_ULTIMATE.start_main_#t~pre6#1_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre6#1] 80440#[thr1ENTRY, L846-1]don't care [234] L846-1-->L846-2: Formula: (= (+ 1 |v_#pthreadsForks_6|) |v_#pthreadsForks_5|) InVars {#pthreadsForks=|v_#pthreadsForks_6|} OutVars{#pthreadsForks=|v_#pthreadsForks_5|} AuxVars[] AssignedVars[#pthreadsForks] 80916#[thr1ENTRY, L846-2]don't care [258] L846-2-->L846-3: Formula: (and (<= (+ 4 |v_ULTIMATE.start_main_~#t2~0#1.offset_3|) (select |v_#length_6| |v_ULTIMATE.start_main_~#t2~0#1.base_3|)) (= (store |v_#memory_int_4| |v_ULTIMATE.start_main_~#t2~0#1.base_3| (store (select |v_#memory_int_4| |v_ULTIMATE.start_main_~#t2~0#1.base_3|) |v_ULTIMATE.start_main_~#t2~0#1.offset_3| |v_ULTIMATE.start_main_#t~pre6#1_3|)) |v_#memory_int_3|) (= (select |v_#valid_6| |v_ULTIMATE.start_main_~#t2~0#1.base_3|) 1) (<= 0 |v_ULTIMATE.start_main_~#t2~0#1.offset_3|)) InVars {ULTIMATE.start_main_#t~pre6#1=|v_ULTIMATE.start_main_#t~pre6#1_3|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_3|, #valid=|v_#valid_6|, #memory_int=|v_#memory_int_4|, #length=|v_#length_6|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_3|} OutVars{ULTIMATE.start_main_#t~pre6#1=|v_ULTIMATE.start_main_#t~pre6#1_3|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_3|, #valid=|v_#valid_6|, #memory_int=|v_#memory_int_3|, #length=|v_#length_6|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_3|} AuxVars[] AssignedVars[#memory_int] 80072#[thr1ENTRY, L846-3]don't care [446] L846-3-->thr2ENTRY: Formula: (and (= v_thr2Thread1of1ForFork0_thidvar2_2 0) (= |v_ULTIMATE.start_main_#t~pre6#1_6| v_thr2Thread1of1ForFork0_thidvar0_2) (= |v_thr2Thread1of1ForFork0_#in~_.offset_4| 0) (= |v_thr2Thread1of1ForFork0_#in~_.base_4| 0) (= v_thr2Thread1of1ForFork0_thidvar1_2 0)) InVars {ULTIMATE.start_main_#t~pre6#1=|v_ULTIMATE.start_main_#t~pre6#1_6|} OutVars{thr2Thread1of1ForFork0_~y2~0=v_thr2Thread1of1ForFork0_~y2~0_30, ULTIMATE.start_main_#t~pre6#1=|v_ULTIMATE.start_main_#t~pre6#1_6|, thr2Thread1of1ForFork0_#in~_.offset=|v_thr2Thread1of1ForFork0_#in~_.offset_4|, thr2Thread1of1ForFork0_#res.base=|v_thr2Thread1of1ForFork0_#res.base_4|, thr2Thread1of1ForFork0_~x2~0=v_thr2Thread1of1ForFork0_~x2~0_8, thr2Thread1of1ForFork0_#res.offset=|v_thr2Thread1of1ForFork0_#res.offset_4|, thr2Thread1of1ForFork0_~b12~0=v_thr2Thread1of1ForFork0_~b12~0_10, thr2Thread1of1ForFork0_#in~_.base=|v_thr2Thread1of1ForFork0_#in~_.base_4|, thr2Thread1of1ForFork0_~_.base=v_thr2Thread1of1ForFork0_~_.base_4, thr2Thread1of1ForFork0_~_.offset=v_thr2Thread1of1ForFork0_~_.offset_4, thr2Thread1of1ForFork0_thidvar0=v_thr2Thread1of1ForFork0_thidvar0_2, thr2Thread1of1ForFork0_thidvar1=v_thr2Thread1of1ForFork0_thidvar1_2, thr2Thread1of1ForFork0_thidvar2=v_thr2Thread1of1ForFork0_thidvar2_2} AuxVars[] AssignedVars[thr2Thread1of1ForFork0_~y2~0, thr2Thread1of1ForFork0_~_.offset, thr2Thread1of1ForFork0_#in~_.offset, thr2Thread1of1ForFork0_#res.base, thr2Thread1of1ForFork0_thidvar0, thr2Thread1of1ForFork0_thidvar1, thr2Thread1of1ForFork0_thidvar2, thr2Thread1of1ForFork0_~x2~0, thr2Thread1of1ForFork0_#res.offset, thr2Thread1of1ForFork0_~b12~0, thr2Thread1of1ForFork0_#in~_.base, thr2Thread1of1ForFork0_~_.base] 79738#[thr2ENTRY, L846-4, thr1ENTRY]don't care [360] thr2ENTRY-->L774loopEntry: Formula: (and (= |v_thr2Thread1of1ForFork0_#in~_.base_1| v_thr2Thread1of1ForFork0_~_.base_1) (= v_thr2Thread1of1ForFork0_~_.offset_1 |v_thr2Thread1of1ForFork0_#in~_.offset_1|)) InVars {thr2Thread1of1ForFork0_#in~_.offset=|v_thr2Thread1of1ForFork0_#in~_.offset_1|, thr2Thread1of1ForFork0_#in~_.base=|v_thr2Thread1of1ForFork0_#in~_.base_1|} OutVars{thr2Thread1of1ForFork0_~_.offset=v_thr2Thread1of1ForFork0_~_.offset_1, thr2Thread1of1ForFork0_#in~_.offset=|v_thr2Thread1of1ForFork0_#in~_.offset_1|, thr2Thread1of1ForFork0_#in~_.base=|v_thr2Thread1of1ForFork0_#in~_.base_1|, thr2Thread1of1ForFork0_~_.base=v_thr2Thread1of1ForFork0_~_.base_1} AuxVars[] AssignedVars[thr2Thread1of1ForFork0_~_.offset, thr2Thread1of1ForFork0_~_.base] 79742#[L774loopEntry, thr1ENTRY, L846-4]don't care [361] L774loopEntry-->L823-1: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 81296#[L823-1, L846-4, thr1ENTRY]don't care [364] L823-1-->L775: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 80586#[L775, thr1ENTRY, L846-4]don't care [366] L775-->L777: Formula: (= v_~b2~0_1 1) InVars {} OutVars{~b2~0=v_~b2~0_1} AuxVars[] AssignedVars[~b2~0] 80590#[L777, L846-4, thr1ENTRY]don't care [369] L777-->L780: Formula: (= 2 v_~x~0_1) InVars {} OutVars{~x~0=v_~x~0_1} AuxVars[] AssignedVars[~x~0] 76582#[L780, thr1ENTRY, L846-4]don't care [372] L780-->L783: Formula: (= v_~y~0_2 v_thr2Thread1of1ForFork0_~y2~0_1) InVars {~y~0=v_~y~0_2} OutVars{~y~0=v_~y~0_2, thr2Thread1of1ForFork0_~y2~0=v_thr2Thread1of1ForFork0_~y2~0_1} AuxVars[] AssignedVars[thr2Thread1of1ForFork0_~y2~0] 76586#[L783, L846-4, thr1ENTRY]don't care [374] L783-->L785: Formula: (not (= v_thr2Thread1of1ForFork0_~y2~0_3 0)) InVars {thr2Thread1of1ForFork0_~y2~0=v_thr2Thread1of1ForFork0_~y2~0_3} OutVars{thr2Thread1of1ForFork0_~y2~0=v_thr2Thread1of1ForFork0_~y2~0_3} AuxVars[] AssignedVars[] 77718#[L785, thr1ENTRY, L846-4]don't care [377] L785-->L787: Formula: (= v_~b2~0_2 0) InVars {} OutVars{~b2~0=v_~b2~0_2} AuxVars[] AssignedVars[~b2~0] 76928#[L787, L846-4, thr1ENTRY]don't care [380] L787-->L794: Formula: (= v_~y~0_3 v_thr2Thread1of1ForFork0_~y2~0_7) InVars {~y~0=v_~y~0_3} OutVars{~y~0=v_~y~0_3, thr2Thread1of1ForFork0_~y2~0=v_thr2Thread1of1ForFork0_~y2~0_7} AuxVars[] AssignedVars[thr2Thread1of1ForFork0_~y2~0] 76934#[L794, thr1ENTRY, L846-4]don't care [2022-07-26 13:22:16,989 INFO L735 eck$LassoCheckResult]: Loop: 76934#[L794, thr1ENTRY, L846-4]don't care [384] L794-->L792: Formula: (not (= v_thr2Thread1of1ForFork0_~y2~0_11 0)) InVars {thr2Thread1of1ForFork0_~y2~0=v_thr2Thread1of1ForFork0_~y2~0_11} OutVars{thr2Thread1of1ForFork0_~y2~0=v_thr2Thread1of1ForFork0_~y2~0_11} AuxVars[] AssignedVars[] 79900#[L792, L846-4, thr1ENTRY]don't care [387] L792-->L794: Formula: (= v_thr2Thread1of1ForFork0_~y2~0_13 v_~y~0_5) InVars {~y~0=v_~y~0_5} OutVars{~y~0=v_~y~0_5, thr2Thread1of1ForFork0_~y2~0=v_thr2Thread1of1ForFork0_~y2~0_13} AuxVars[] AssignedVars[thr2Thread1of1ForFork0_~y2~0] 76934#[L794, thr1ENTRY, L846-4]don't care [2022-07-26 13:22:16,990 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:16,990 INFO L85 PathProgramCache]: Analyzing trace with hash 581266918, now seen corresponding path program 1 times [2022-07-26 13:22:16,990 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:16,990 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1596580935] [2022-07-26 13:22:16,990 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:16,990 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:17,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-26 13:22:17,073 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-26 13:22:17,073 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-26 13:22:17,073 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1596580935] [2022-07-26 13:22:17,074 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1596580935] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-26 13:22:17,074 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-26 13:22:17,074 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-26 13:22:17,074 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [987463262] [2022-07-26 13:22:17,074 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-26 13:22:17,074 INFO L738 eck$LassoCheckResult]: stem already infeasible [2022-07-26 13:22:17,075 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:17,075 INFO L85 PathProgramCache]: Analyzing trace with hash 13252, now seen corresponding path program 1 times [2022-07-26 13:22:17,075 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:17,075 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1779343544] [2022-07-26 13:22:17,075 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:17,075 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:17,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:17,081 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-26 13:22:17,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:17,090 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-26 13:22:17,108 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-26 13:22:17,108 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-26 13:22:17,108 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-26 13:22:17,108 INFO L87 Difference]: Start difference. First operand 4217 states and 11885 transitions. cyclomatic complexity: 8312 Second operand has 4 states, 4 states have (on average 9.5) internal successors, (38), 4 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-26 13:22:17,214 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-26 13:22:17,215 INFO L93 Difference]: Finished difference Result 4795 states and 13166 transitions. [2022-07-26 13:22:17,215 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4795 states and 13166 transitions. [2022-07-26 13:22:17,244 INFO L131 ngComponentsAnalysis]: Automaton has 677 accepting balls. 1418 [2022-07-26 13:22:17,274 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4795 states to 4795 states and 13166 transitions. [2022-07-26 13:22:17,274 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4795 [2022-07-26 13:22:17,280 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4795 [2022-07-26 13:22:17,280 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4795 states and 13166 transitions. [2022-07-26 13:22:17,286 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-26 13:22:17,287 INFO L220 hiAutomatonCegarLoop]: Abstraction has 4795 states and 13166 transitions. [2022-07-26 13:22:17,297 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4795 states and 13166 transitions. [2022-07-26 13:22:17,370 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4795 to 3946. [2022-07-26 13:22:17,379 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3946 states, 3946 states have (on average 2.7833248859604662) internal successors, (10983), 3945 states have internal predecessors, (10983), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-26 13:22:17,393 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3946 states to 3946 states and 10983 transitions. [2022-07-26 13:22:17,393 INFO L242 hiAutomatonCegarLoop]: Abstraction has 3946 states and 10983 transitions. [2022-07-26 13:22:17,393 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-07-26 13:22:17,395 INFO L426 stractBuchiCegarLoop]: Abstraction has 3946 states and 10983 transitions. [2022-07-26 13:22:17,395 INFO L333 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-07-26 13:22:17,395 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3946 states and 10983 transitions. [2022-07-26 13:22:17,413 INFO L131 ngComponentsAnalysis]: Automaton has 581 accepting balls. 1226 [2022-07-26 13:22:17,413 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-26 13:22:17,413 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-26 13:22:17,416 INFO L150 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-26 13:22:17,416 INFO L151 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-07-26 13:22:17,420 INFO L733 eck$LassoCheckResult]: Stem: 94290#[ULTIMATE.startENTRY]don't care [341] ULTIMATE.startENTRY-->L-1: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 94292#[L-1]don't care [266] L-1-->L-1-1: Formula: (and (= |v_#NULL.base_1| 0) (= |v_#NULL.offset_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] 90244#[L-1-1]don't care [350] L-1-1-->L-1-2: Formula: (= 0 (select |v_#valid_13| 0)) InVars {#valid=|v_#valid_13|} OutVars{#valid=|v_#valid_13|} AuxVars[] AssignedVars[] 90246#[L-1-2]don't care [352] L-1-2-->L12: Formula: (< 0 |v_#StackHeapBarrier_3|) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_3|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_3|} AuxVars[] AssignedVars[] 94490#[L12]don't care [305] L12-->L12-1: Formula: (and (= (select |v_#length_9| 1) 2) (= (select |v_#valid_14| 1) 1)) InVars {#length=|v_#length_9|, #valid=|v_#valid_14|} OutVars{#length=|v_#length_9|, #valid=|v_#valid_14|} AuxVars[] AssignedVars[] 92712#[L12-1]don't care [320] L12-1-->L12-2: Formula: (= (select (select |v_#memory_int_7| 1) 0) 48) InVars {#memory_int=|v_#memory_int_7|} OutVars{#memory_int=|v_#memory_int_7|} AuxVars[] AssignedVars[] 92714#[L12-2]don't care [319] L12-2-->L12-3: Formula: (= (select (select |v_#memory_int_8| 1) 1) 0) InVars {#memory_int=|v_#memory_int_8|} OutVars{#memory_int=|v_#memory_int_8|} AuxVars[] AssignedVars[] 92190#[L12-3]don't care [343] L12-3-->L12-4: Formula: (and (= (select |v_#length_10| 2) 10) (= (select |v_#valid_15| 2) 1)) InVars {#length=|v_#length_10|, #valid=|v_#valid_15|} OutVars{#length=|v_#length_10|, #valid=|v_#valid_15|} AuxVars[] AssignedVars[] 92192#[L12-4]don't care [336] L12-4-->L700: Formula: (= v_~x~0_5 0) InVars {} OutVars{~x~0=v_~x~0_5} AuxVars[] AssignedVars[~x~0] 91358#[L700]don't care [280] L700-->L701: Formula: (= v_~y~0_17 0) InVars {} OutVars{~y~0=v_~y~0_17} AuxVars[] AssignedVars[~y~0] 91360#[L701]don't care [348] L701-->L701-1: Formula: (= v_~b1~0_7 0) InVars {} OutVars{~b1~0=v_~b1~0_7} AuxVars[] AssignedVars[~b1~0] 94602#[L701-1]don't care [247] L701-1-->L702: Formula: (= v_~b2~0_7 0) InVars {} OutVars{~b2~0=v_~b2~0_7} AuxVars[] AssignedVars[~b2~0] 90824#[L702]don't care [251] L702-->L-1-3: Formula: (= v_~X~0_7 0) InVars {} OutVars{~X~0=v_~X~0_7} AuxVars[] AssignedVars[~X~0] 90826#[L-1-3]don't care [353] L-1-3-->L-1-4: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 91148#[L-1-4]don't care [272] L-1-4-->L-1-5: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 93826#[L-1-5]don't care [242] L-1-5-->L-1-6: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res#1=|v_ULTIMATE.start_main_#res#1_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res#1] 94056#[L-1-6]don't care [335] L-1-6-->L844: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~pre6#1=|v_ULTIMATE.start_main_#t~pre6#1_1|, ULTIMATE.start_main_#t~mem8#1=|v_ULTIMATE.start_main_#t~mem8#1_1|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_1|, ULTIMATE.start_main_#t~nondet5#1=|v_ULTIMATE.start_main_#t~nondet5#1_1|, ULTIMATE.start_main_#t~nondet7#1=|v_ULTIMATE.start_main_#t~nondet7#1_1|, ULTIMATE.start_main_#t~mem9#1=|v_ULTIMATE.start_main_#t~mem9#1_1|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_1|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_1|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_1|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre6#1, ULTIMATE.start_main_#t~mem8#1, ULTIMATE.start_main_~#t2~0#1.offset, ULTIMATE.start_main_#t~nondet5#1, ULTIMATE.start_main_#t~nondet7#1, ULTIMATE.start_main_#t~mem9#1, ULTIMATE.start_main_~#t1~0#1.base, ULTIMATE.start_main_#t~pre4#1, ULTIMATE.start_main_~#t1~0#1.offset, ULTIMATE.start_main_~#t2~0#1.base] 94058#[L844]don't care [293] L844-->L844-1: Formula: (and (= (store |v_#valid_2| |v_ULTIMATE.start_main_~#t1~0#1.base_2| 1) |v_#valid_1|) (= |v_ULTIMATE.start_main_~#t1~0#1.offset_2| 0) (= (select |v_#valid_2| |v_ULTIMATE.start_main_~#t1~0#1.base_2|) 0) (< |v_#StackHeapBarrier_1| |v_ULTIMATE.start_main_~#t1~0#1.base_2|) (= (store |v_#length_2| |v_ULTIMATE.start_main_~#t1~0#1.base_2| 4) |v_#length_1|) (not (= |v_ULTIMATE.start_main_~#t1~0#1.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_2|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_2|, #valid=|v_#valid_1|} AuxVars[] AssignedVars[#valid, #length, ULTIMATE.start_main_~#t1~0#1.base, ULTIMATE.start_main_~#t1~0#1.offset] 90458#[L844-1]don't care [279] L844-1-->L844-2: Formula: (and (< |v_#StackHeapBarrier_2| |v_ULTIMATE.start_main_~#t2~0#1.base_2|) (not (= |v_ULTIMATE.start_main_~#t2~0#1.base_2| 0)) (= |v_#length_3| (store |v_#length_4| |v_ULTIMATE.start_main_~#t2~0#1.base_2| 4)) (= 0 |v_ULTIMATE.start_main_~#t2~0#1.offset_2|) (= (store |v_#valid_4| |v_ULTIMATE.start_main_~#t2~0#1.base_2| 1) |v_#valid_3|) (= (select |v_#valid_4| |v_ULTIMATE.start_main_~#t2~0#1.base_2|) 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_4|, #valid=|v_#valid_4|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_2|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_2|, #valid=|v_#valid_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2~0#1.offset, #valid, #length, ULTIMATE.start_main_~#t2~0#1.base] 90460#[L844-2]don't care [313] L844-2-->L845: Formula: (= |v_ULTIMATE.start_main_#t~pre4#1_2| |v_#pthreadsForks_1|) InVars {#pthreadsForks=|v_#pthreadsForks_1|} OutVars{#pthreadsForks=|v_#pthreadsForks_1|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre4#1] 90984#[L845]don't care [340] L845-->L845-1: Formula: (= (+ 1 |v_#pthreadsForks_3|) |v_#pthreadsForks_2|) InVars {#pthreadsForks=|v_#pthreadsForks_3|} OutVars{#pthreadsForks=|v_#pthreadsForks_2|} AuxVars[] AssignedVars[#pthreadsForks] 92802#[L845-1]don't care [244] L845-1-->L845-2: Formula: (and (<= 0 |v_ULTIMATE.start_main_~#t1~0#1.offset_3|) (= (select |v_#valid_5| |v_ULTIMATE.start_main_~#t1~0#1.base_3|) 1) (= (store |v_#memory_int_2| |v_ULTIMATE.start_main_~#t1~0#1.base_3| (store (select |v_#memory_int_2| |v_ULTIMATE.start_main_~#t1~0#1.base_3|) |v_ULTIMATE.start_main_~#t1~0#1.offset_3| |v_ULTIMATE.start_main_#t~pre4#1_3|)) |v_#memory_int_1|) (<= (+ |v_ULTIMATE.start_main_~#t1~0#1.offset_3| 4) (select |v_#length_5| |v_ULTIMATE.start_main_~#t1~0#1.base_3|))) InVars {#valid=|v_#valid_5|, #memory_int=|v_#memory_int_2|, #length=|v_#length_5|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_3|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_3|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_3|} OutVars{#valid=|v_#valid_5|, #memory_int=|v_#memory_int_1|, #length=|v_#length_5|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_3|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_3|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_3|} AuxVars[] AssignedVars[#memory_int] 92804#[L845-2]don't care [449] L845-2-->thr1ENTRY: Formula: (and (= v_thr1Thread1of1ForFork1_thidvar1_2 0) (= |v_ULTIMATE.start_main_#t~pre4#1_6| v_thr1Thread1of1ForFork1_thidvar0_2) (= |v_thr1Thread1of1ForFork1_#in~_.base_4| 0) (= |v_thr1Thread1of1ForFork1_#in~_.offset_4| 0)) InVars {ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_6|} OutVars{thr1Thread1of1ForFork1_#in~_.offset=|v_thr1Thread1of1ForFork1_#in~_.offset_4|, thr1Thread1of1ForFork1_~_.base=v_thr1Thread1of1ForFork1_~_.base_4, thr1Thread1of1ForFork1_~b21~0=v_thr1Thread1of1ForFork1_~b21~0_10, thr1Thread1of1ForFork1_#res.base=|v_thr1Thread1of1ForFork1_#res.base_4|, thr1Thread1of1ForFork1_~y1~0=v_thr1Thread1of1ForFork1_~y1~0_30, thr1Thread1of1ForFork1_#in~_.base=|v_thr1Thread1of1ForFork1_#in~_.base_4|, thr1Thread1of1ForFork1_~_.offset=v_thr1Thread1of1ForFork1_~_.offset_4, thr1Thread1of1ForFork1_#res.offset=|v_thr1Thread1of1ForFork1_#res.offset_4|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_6|, thr1Thread1of1ForFork1_thidvar1=v_thr1Thread1of1ForFork1_thidvar1_2, thr1Thread1of1ForFork1_thidvar0=v_thr1Thread1of1ForFork1_thidvar0_2, thr1Thread1of1ForFork1_~x1~0=v_thr1Thread1of1ForFork1_~x1~0_8} AuxVars[] AssignedVars[thr1Thread1of1ForFork1_#in~_.offset, thr1Thread1of1ForFork1_~_.base, thr1Thread1of1ForFork1_~b21~0, thr1Thread1of1ForFork1_#res.base, thr1Thread1of1ForFork1_~y1~0, thr1Thread1of1ForFork1_#in~_.base, thr1Thread1of1ForFork1_~_.offset, thr1Thread1of1ForFork1_#res.offset, thr1Thread1of1ForFork1_thidvar1, thr1Thread1of1ForFork1_thidvar0, thr1Thread1of1ForFork1_~x1~0] 92982#[thr1ENTRY, L845-3]don't care [328] L845-3-->L845-4: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre4#1] 94628#[thr1ENTRY, L845-4]don't care [259] L845-4-->L846: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet5#1=|v_ULTIMATE.start_main_#t~nondet5#1_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet5#1] 93546#[thr1ENTRY, L846]don't care [243] L846-->L846-1: Formula: (= |v_ULTIMATE.start_main_#t~pre6#1_2| |v_#pthreadsForks_4|) InVars {#pthreadsForks=|v_#pthreadsForks_4|} OutVars{#pthreadsForks=|v_#pthreadsForks_4|, ULTIMATE.start_main_#t~pre6#1=|v_ULTIMATE.start_main_#t~pre6#1_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre6#1] 93548#[thr1ENTRY, L846-1]don't care [234] L846-1-->L846-2: Formula: (= (+ 1 |v_#pthreadsForks_6|) |v_#pthreadsForks_5|) InVars {#pthreadsForks=|v_#pthreadsForks_6|} OutVars{#pthreadsForks=|v_#pthreadsForks_5|} AuxVars[] AssignedVars[#pthreadsForks] 94044#[thr1ENTRY, L846-2]don't care [258] L846-2-->L846-3: Formula: (and (<= (+ 4 |v_ULTIMATE.start_main_~#t2~0#1.offset_3|) (select |v_#length_6| |v_ULTIMATE.start_main_~#t2~0#1.base_3|)) (= (store |v_#memory_int_4| |v_ULTIMATE.start_main_~#t2~0#1.base_3| (store (select |v_#memory_int_4| |v_ULTIMATE.start_main_~#t2~0#1.base_3|) |v_ULTIMATE.start_main_~#t2~0#1.offset_3| |v_ULTIMATE.start_main_#t~pre6#1_3|)) |v_#memory_int_3|) (= (select |v_#valid_6| |v_ULTIMATE.start_main_~#t2~0#1.base_3|) 1) (<= 0 |v_ULTIMATE.start_main_~#t2~0#1.offset_3|)) InVars {ULTIMATE.start_main_#t~pre6#1=|v_ULTIMATE.start_main_#t~pre6#1_3|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_3|, #valid=|v_#valid_6|, #memory_int=|v_#memory_int_4|, #length=|v_#length_6|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_3|} OutVars{ULTIMATE.start_main_#t~pre6#1=|v_ULTIMATE.start_main_#t~pre6#1_3|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_3|, #valid=|v_#valid_6|, #memory_int=|v_#memory_int_3|, #length=|v_#length_6|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_3|} AuxVars[] AssignedVars[#memory_int] 93174#[thr1ENTRY, L846-3]don't care [446] L846-3-->thr2ENTRY: Formula: (and (= v_thr2Thread1of1ForFork0_thidvar2_2 0) (= |v_ULTIMATE.start_main_#t~pre6#1_6| v_thr2Thread1of1ForFork0_thidvar0_2) (= |v_thr2Thread1of1ForFork0_#in~_.offset_4| 0) (= |v_thr2Thread1of1ForFork0_#in~_.base_4| 0) (= v_thr2Thread1of1ForFork0_thidvar1_2 0)) InVars {ULTIMATE.start_main_#t~pre6#1=|v_ULTIMATE.start_main_#t~pre6#1_6|} OutVars{thr2Thread1of1ForFork0_~y2~0=v_thr2Thread1of1ForFork0_~y2~0_30, ULTIMATE.start_main_#t~pre6#1=|v_ULTIMATE.start_main_#t~pre6#1_6|, thr2Thread1of1ForFork0_#in~_.offset=|v_thr2Thread1of1ForFork0_#in~_.offset_4|, thr2Thread1of1ForFork0_#res.base=|v_thr2Thread1of1ForFork0_#res.base_4|, thr2Thread1of1ForFork0_~x2~0=v_thr2Thread1of1ForFork0_~x2~0_8, thr2Thread1of1ForFork0_#res.offset=|v_thr2Thread1of1ForFork0_#res.offset_4|, thr2Thread1of1ForFork0_~b12~0=v_thr2Thread1of1ForFork0_~b12~0_10, thr2Thread1of1ForFork0_#in~_.base=|v_thr2Thread1of1ForFork0_#in~_.base_4|, thr2Thread1of1ForFork0_~_.base=v_thr2Thread1of1ForFork0_~_.base_4, thr2Thread1of1ForFork0_~_.offset=v_thr2Thread1of1ForFork0_~_.offset_4, thr2Thread1of1ForFork0_thidvar0=v_thr2Thread1of1ForFork0_thidvar0_2, thr2Thread1of1ForFork0_thidvar1=v_thr2Thread1of1ForFork0_thidvar1_2, thr2Thread1of1ForFork0_thidvar2=v_thr2Thread1of1ForFork0_thidvar2_2} AuxVars[] AssignedVars[thr2Thread1of1ForFork0_~y2~0, thr2Thread1of1ForFork0_~_.offset, thr2Thread1of1ForFork0_#in~_.offset, thr2Thread1of1ForFork0_#res.base, thr2Thread1of1ForFork0_thidvar0, thr2Thread1of1ForFork0_thidvar1, thr2Thread1of1ForFork0_thidvar2, thr2Thread1of1ForFork0_~x2~0, thr2Thread1of1ForFork0_#res.offset, thr2Thread1of1ForFork0_~b12~0, thr2Thread1of1ForFork0_#in~_.base, thr2Thread1of1ForFork0_~_.base] 92834#[thr2ENTRY, L846-4, thr1ENTRY]don't care [360] thr2ENTRY-->L774loopEntry: Formula: (and (= |v_thr2Thread1of1ForFork0_#in~_.base_1| v_thr2Thread1of1ForFork0_~_.base_1) (= v_thr2Thread1of1ForFork0_~_.offset_1 |v_thr2Thread1of1ForFork0_#in~_.offset_1|)) InVars {thr2Thread1of1ForFork0_#in~_.offset=|v_thr2Thread1of1ForFork0_#in~_.offset_1|, thr2Thread1of1ForFork0_#in~_.base=|v_thr2Thread1of1ForFork0_#in~_.base_1|} OutVars{thr2Thread1of1ForFork0_~_.offset=v_thr2Thread1of1ForFork0_~_.offset_1, thr2Thread1of1ForFork0_#in~_.offset=|v_thr2Thread1of1ForFork0_#in~_.offset_1|, thr2Thread1of1ForFork0_#in~_.base=|v_thr2Thread1of1ForFork0_#in~_.base_1|, thr2Thread1of1ForFork0_~_.base=v_thr2Thread1of1ForFork0_~_.base_1} AuxVars[] AssignedVars[thr2Thread1of1ForFork0_~_.offset, thr2Thread1of1ForFork0_~_.base] 92838#[L774loopEntry, thr1ENTRY, L846-4]don't care [361] L774loopEntry-->L823-1: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 94468#[L823-1, L846-4, thr1ENTRY]don't care [364] L823-1-->L775: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 93684#[L775, thr1ENTRY, L846-4]don't care [366] L775-->L777: Formula: (= v_~b2~0_1 1) InVars {} OutVars{~b2~0=v_~b2~0_1} AuxVars[] AssignedVars[~b2~0] 93688#[L777, L846-4, thr1ENTRY]don't care [369] L777-->L780: Formula: (= 2 v_~x~0_1) InVars {} OutVars{~x~0=v_~x~0_1} AuxVars[] AssignedVars[~x~0] 89738#[L780, thr1ENTRY, L846-4]don't care [372] L780-->L783: Formula: (= v_~y~0_2 v_thr2Thread1of1ForFork0_~y2~0_1) InVars {~y~0=v_~y~0_2} OutVars{~y~0=v_~y~0_2, thr2Thread1of1ForFork0_~y2~0=v_thr2Thread1of1ForFork0_~y2~0_1} AuxVars[] AssignedVars[thr2Thread1of1ForFork0_~y2~0] 89742#[L783, L846-4, thr1ENTRY]don't care [375] L783-->L798: Formula: (= v_thr2Thread1of1ForFork0_~y2~0_5 0) InVars {thr2Thread1of1ForFork0_~y2~0=v_thr2Thread1of1ForFork0_~y2~0_5} OutVars{thr2Thread1of1ForFork0_~y2~0=v_thr2Thread1of1ForFork0_~y2~0_5} AuxVars[] AssignedVars[] 90850#[L798, thr1ENTRY, L846-4]don't care [378] L798-->L800: Formula: (= 2 v_~y~0_6) InVars {} OutVars{~y~0=v_~y~0_6} AuxVars[] AssignedVars[~y~0] 94284#[L846-4, thr1ENTRY, L800]don't care [381] L800-->L803: Formula: (= v_~x~0_2 v_thr2Thread1of1ForFork0_~x2~0_1) InVars {~x~0=v_~x~0_2} OutVars{thr2Thread1of1ForFork0_~x2~0=v_thr2Thread1of1ForFork0_~x2~0_1, ~x~0=v_~x~0_2} AuxVars[] AssignedVars[thr2Thread1of1ForFork0_~x2~0] 94212#[L803, thr1ENTRY, L846-4]don't care [385] L803-->L805: Formula: (not (= 2 v_thr2Thread1of1ForFork0_~x2~0_3)) InVars {thr2Thread1of1ForFork0_~x2~0=v_thr2Thread1of1ForFork0_~x2~0_3} OutVars{thr2Thread1of1ForFork0_~x2~0=v_thr2Thread1of1ForFork0_~x2~0_3} AuxVars[] AssignedVars[] 94214#[L846-4, thr1ENTRY, L805]don't care [388] L805-->L807: Formula: (= v_~b2~0_4 0) InVars {} OutVars{~b2~0=v_~b2~0_4} AuxVars[] AssignedVars[~b2~0] 90200#[L807, thr1ENTRY, L846-4]don't care [389] L807-->L814: Formula: (= v_~b1~0_1 v_thr2Thread1of1ForFork0_~b12~0_1) InVars {~b1~0=v_~b1~0_1} OutVars{~b1~0=v_~b1~0_1, thr2Thread1of1ForFork0_~b12~0=v_thr2Thread1of1ForFork0_~b12~0_1} AuxVars[] AssignedVars[thr2Thread1of1ForFork0_~b12~0] 89268#[L846-4, thr1ENTRY, L814]don't care [2022-07-26 13:22:17,420 INFO L735 eck$LassoCheckResult]: Loop: 89268#[L846-4, thr1ENTRY, L814]don't care [392] L814-->L812: Formula: (<= 1 v_thr2Thread1of1ForFork0_~b12~0_5) InVars {thr2Thread1of1ForFork0_~b12~0=v_thr2Thread1of1ForFork0_~b12~0_5} OutVars{thr2Thread1of1ForFork0_~b12~0=v_thr2Thread1of1ForFork0_~b12~0_5} AuxVars[] AssignedVars[] 89276#[L812, thr1ENTRY, L846-4]don't care [394] L812-->L814: Formula: (= v_~b1~0_2 v_thr2Thread1of1ForFork0_~b12~0_7) InVars {~b1~0=v_~b1~0_2} OutVars{~b1~0=v_~b1~0_2, thr2Thread1of1ForFork0_~b12~0=v_thr2Thread1of1ForFork0_~b12~0_7} AuxVars[] AssignedVars[thr2Thread1of1ForFork0_~b12~0] 89268#[L846-4, thr1ENTRY, L814]don't care [2022-07-26 13:22:17,420 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:17,420 INFO L85 PathProgramCache]: Analyzing trace with hash -755418469, now seen corresponding path program 1 times [2022-07-26 13:22:17,420 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:17,420 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [784532281] [2022-07-26 13:22:17,421 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:17,421 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:17,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-26 13:22:17,494 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-26 13:22:17,495 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-26 13:22:17,495 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [784532281] [2022-07-26 13:22:17,495 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [784532281] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-26 13:22:17,495 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-26 13:22:17,495 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-07-26 13:22:17,495 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1197305328] [2022-07-26 13:22:17,496 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-26 13:22:17,496 INFO L738 eck$LassoCheckResult]: stem already infeasible [2022-07-26 13:22:17,496 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:17,496 INFO L85 PathProgramCache]: Analyzing trace with hash 13507, now seen corresponding path program 1 times [2022-07-26 13:22:17,496 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:17,496 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1316725240] [2022-07-26 13:22:17,497 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:17,497 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:17,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:17,500 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-26 13:22:17,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:17,502 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-26 13:22:17,512 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-26 13:22:17,513 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-07-26 13:22:17,513 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-07-26 13:22:17,513 INFO L87 Difference]: Start difference. First operand 3946 states and 10983 transitions. cyclomatic complexity: 7618 Second operand has 4 states, 4 states have (on average 10.25) internal successors, (41), 4 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-26 13:22:17,557 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-26 13:22:17,557 INFO L93 Difference]: Finished difference Result 4006 states and 10610 transitions. [2022-07-26 13:22:17,557 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4006 states and 10610 transitions. [2022-07-26 13:22:17,585 INFO L131 ngComponentsAnalysis]: Automaton has 473 accepting balls. 978 [2022-07-26 13:22:17,608 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4006 states to 3291 states and 8787 transitions. [2022-07-26 13:22:17,608 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3291 [2022-07-26 13:22:17,612 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3291 [2022-07-26 13:22:17,612 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3291 states and 8787 transitions. [2022-07-26 13:22:17,618 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-26 13:22:17,618 INFO L220 hiAutomatonCegarLoop]: Abstraction has 3291 states and 8787 transitions. [2022-07-26 13:22:17,627 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3291 states and 8787 transitions. [2022-07-26 13:22:17,676 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3291 to 2987. [2022-07-26 13:22:17,683 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2987 states, 2987 states have (on average 2.6859725477067293) internal successors, (8023), 2986 states have internal predecessors, (8023), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-26 13:22:17,693 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2987 states to 2987 states and 8023 transitions. [2022-07-26 13:22:17,693 INFO L242 hiAutomatonCegarLoop]: Abstraction has 2987 states and 8023 transitions. [2022-07-26 13:22:17,694 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-07-26 13:22:17,695 INFO L426 stractBuchiCegarLoop]: Abstraction has 2987 states and 8023 transitions. [2022-07-26 13:22:17,695 INFO L333 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-07-26 13:22:17,696 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2987 states and 8023 transitions. [2022-07-26 13:22:17,714 INFO L131 ngComponentsAnalysis]: Automaton has 417 accepting balls. 866 [2022-07-26 13:22:17,715 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-26 13:22:17,715 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-26 13:22:17,717 INFO L150 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-26 13:22:17,717 INFO L151 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-07-26 13:22:17,718 INFO L733 eck$LassoCheckResult]: Stem: 102945#[ULTIMATE.startENTRY]don't care [341] ULTIMATE.startENTRY-->L-1: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 102947#[L-1]don't care [266] L-1-->L-1-1: Formula: (and (= |v_#NULL.base_1| 0) (= |v_#NULL.offset_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] 102977#[L-1-1]don't care [350] L-1-1-->L-1-2: Formula: (= 0 (select |v_#valid_13| 0)) InVars {#valid=|v_#valid_13|} OutVars{#valid=|v_#valid_13|} AuxVars[] AssignedVars[] 102979#[L-1-2]don't care [352] L-1-2-->L12: Formula: (< 0 |v_#StackHeapBarrier_3|) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_3|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_3|} AuxVars[] AssignedVars[] 104279#[L12]don't care [305] L12-->L12-1: Formula: (and (= (select |v_#length_9| 1) 2) (= (select |v_#valid_14| 1) 1)) InVars {#length=|v_#length_9|, #valid=|v_#valid_14|} OutVars{#length=|v_#length_9|, #valid=|v_#valid_14|} AuxVars[] AssignedVars[] 104611#[L12-1]don't care [320] L12-1-->L12-2: Formula: (= (select (select |v_#memory_int_7| 1) 0) 48) InVars {#memory_int=|v_#memory_int_7|} OutVars{#memory_int=|v_#memory_int_7|} AuxVars[] AssignedVars[] 103331#[L12-2]don't care [319] L12-2-->L12-3: Formula: (= (select (select |v_#memory_int_8| 1) 1) 0) InVars {#memory_int=|v_#memory_int_8|} OutVars{#memory_int=|v_#memory_int_8|} AuxVars[] AssignedVars[] 103333#[L12-3]don't care [343] L12-3-->L12-4: Formula: (and (= (select |v_#length_10| 2) 10) (= (select |v_#valid_15| 2) 1)) InVars {#length=|v_#length_10|, #valid=|v_#valid_15|} OutVars{#length=|v_#length_10|, #valid=|v_#valid_15|} AuxVars[] AssignedVars[] 102295#[L12-4]don't care [336] L12-4-->L700: Formula: (= v_~x~0_5 0) InVars {} OutVars{~x~0=v_~x~0_5} AuxVars[] AssignedVars[~x~0] 102297#[L700]don't care [280] L700-->L701: Formula: (= v_~y~0_17 0) InVars {} OutVars{~y~0=v_~y~0_17} AuxVars[] AssignedVars[~y~0] 103921#[L701]don't care [348] L701-->L701-1: Formula: (= v_~b1~0_7 0) InVars {} OutVars{~b1~0=v_~b1~0_7} AuxVars[] AssignedVars[~b1~0] 104675#[L701-1]don't care [247] L701-1-->L702: Formula: (= v_~b2~0_7 0) InVars {} OutVars{~b2~0=v_~b2~0_7} AuxVars[] AssignedVars[~b2~0] 103511#[L702]don't care [251] L702-->L-1-3: Formula: (= v_~X~0_7 0) InVars {} OutVars{~X~0=v_~X~0_7} AuxVars[] AssignedVars[~X~0] 103513#[L-1-3]don't care [353] L-1-3-->L-1-4: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 100131#[L-1-4]don't care [272] L-1-4-->L-1-5: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 100133#[L-1-5]don't care [242] L-1-5-->L-1-6: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res#1=|v_ULTIMATE.start_main_#res#1_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res#1] 101521#[L-1-6]don't care [335] L-1-6-->L844: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~pre6#1=|v_ULTIMATE.start_main_#t~pre6#1_1|, ULTIMATE.start_main_#t~mem8#1=|v_ULTIMATE.start_main_#t~mem8#1_1|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_1|, ULTIMATE.start_main_#t~nondet5#1=|v_ULTIMATE.start_main_#t~nondet5#1_1|, ULTIMATE.start_main_#t~nondet7#1=|v_ULTIMATE.start_main_#t~nondet7#1_1|, ULTIMATE.start_main_#t~mem9#1=|v_ULTIMATE.start_main_#t~mem9#1_1|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_1|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_1|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_1|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre6#1, ULTIMATE.start_main_#t~mem8#1, ULTIMATE.start_main_~#t2~0#1.offset, ULTIMATE.start_main_#t~nondet5#1, ULTIMATE.start_main_#t~nondet7#1, ULTIMATE.start_main_#t~mem9#1, ULTIMATE.start_main_~#t1~0#1.base, ULTIMATE.start_main_#t~pre4#1, ULTIMATE.start_main_~#t1~0#1.offset, ULTIMATE.start_main_~#t2~0#1.base] 101523#[L844]don't care [293] L844-->L844-1: Formula: (and (= (store |v_#valid_2| |v_ULTIMATE.start_main_~#t1~0#1.base_2| 1) |v_#valid_1|) (= |v_ULTIMATE.start_main_~#t1~0#1.offset_2| 0) (= (select |v_#valid_2| |v_ULTIMATE.start_main_~#t1~0#1.base_2|) 0) (< |v_#StackHeapBarrier_1| |v_ULTIMATE.start_main_~#t1~0#1.base_2|) (= (store |v_#length_2| |v_ULTIMATE.start_main_~#t1~0#1.base_2| 4) |v_#length_1|) (not (= |v_ULTIMATE.start_main_~#t1~0#1.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_2|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_2|, #valid=|v_#valid_1|} AuxVars[] AssignedVars[#valid, #length, ULTIMATE.start_main_~#t1~0#1.base, ULTIMATE.start_main_~#t1~0#1.offset] 103197#[L844-1]don't care [279] L844-1-->L844-2: Formula: (and (< |v_#StackHeapBarrier_2| |v_ULTIMATE.start_main_~#t2~0#1.base_2|) (not (= |v_ULTIMATE.start_main_~#t2~0#1.base_2| 0)) (= |v_#length_3| (store |v_#length_4| |v_ULTIMATE.start_main_~#t2~0#1.base_2| 4)) (= 0 |v_ULTIMATE.start_main_~#t2~0#1.offset_2|) (= (store |v_#valid_4| |v_ULTIMATE.start_main_~#t2~0#1.base_2| 1) |v_#valid_3|) (= (select |v_#valid_4| |v_ULTIMATE.start_main_~#t2~0#1.base_2|) 0)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_4|, #valid=|v_#valid_4|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_2|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_2|, #valid=|v_#valid_3|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2~0#1.offset, #valid, #length, ULTIMATE.start_main_~#t2~0#1.base] 103199#[L844-2]don't care [313] L844-2-->L845: Formula: (= |v_ULTIMATE.start_main_#t~pre4#1_2| |v_#pthreadsForks_1|) InVars {#pthreadsForks=|v_#pthreadsForks_1|} OutVars{#pthreadsForks=|v_#pthreadsForks_1|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre4#1] 102337#[L845]don't care [340] L845-->L845-1: Formula: (= (+ 1 |v_#pthreadsForks_3|) |v_#pthreadsForks_2|) InVars {#pthreadsForks=|v_#pthreadsForks_3|} OutVars{#pthreadsForks=|v_#pthreadsForks_2|} AuxVars[] AssignedVars[#pthreadsForks] 102339#[L845-1]don't care [244] L845-1-->L845-2: Formula: (and (<= 0 |v_ULTIMATE.start_main_~#t1~0#1.offset_3|) (= (select |v_#valid_5| |v_ULTIMATE.start_main_~#t1~0#1.base_3|) 1) (= (store |v_#memory_int_2| |v_ULTIMATE.start_main_~#t1~0#1.base_3| (store (select |v_#memory_int_2| |v_ULTIMATE.start_main_~#t1~0#1.base_3|) |v_ULTIMATE.start_main_~#t1~0#1.offset_3| |v_ULTIMATE.start_main_#t~pre4#1_3|)) |v_#memory_int_1|) (<= (+ |v_ULTIMATE.start_main_~#t1~0#1.offset_3| 4) (select |v_#length_5| |v_ULTIMATE.start_main_~#t1~0#1.base_3|))) InVars {#valid=|v_#valid_5|, #memory_int=|v_#memory_int_2|, #length=|v_#length_5|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_3|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_3|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_3|} OutVars{#valid=|v_#valid_5|, #memory_int=|v_#memory_int_1|, #length=|v_#length_5|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_3|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_3|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_3|} AuxVars[] AssignedVars[#memory_int] 104669#[L845-2]don't care [449] L845-2-->thr1ENTRY: Formula: (and (= v_thr1Thread1of1ForFork1_thidvar1_2 0) (= |v_ULTIMATE.start_main_#t~pre4#1_6| v_thr1Thread1of1ForFork1_thidvar0_2) (= |v_thr1Thread1of1ForFork1_#in~_.base_4| 0) (= |v_thr1Thread1of1ForFork1_#in~_.offset_4| 0)) InVars {ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_6|} OutVars{thr1Thread1of1ForFork1_#in~_.offset=|v_thr1Thread1of1ForFork1_#in~_.offset_4|, thr1Thread1of1ForFork1_~_.base=v_thr1Thread1of1ForFork1_~_.base_4, thr1Thread1of1ForFork1_~b21~0=v_thr1Thread1of1ForFork1_~b21~0_10, thr1Thread1of1ForFork1_#res.base=|v_thr1Thread1of1ForFork1_#res.base_4|, thr1Thread1of1ForFork1_~y1~0=v_thr1Thread1of1ForFork1_~y1~0_30, thr1Thread1of1ForFork1_#in~_.base=|v_thr1Thread1of1ForFork1_#in~_.base_4|, thr1Thread1of1ForFork1_~_.offset=v_thr1Thread1of1ForFork1_~_.offset_4, thr1Thread1of1ForFork1_#res.offset=|v_thr1Thread1of1ForFork1_#res.offset_4|, ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_6|, thr1Thread1of1ForFork1_thidvar1=v_thr1Thread1of1ForFork1_thidvar1_2, thr1Thread1of1ForFork1_thidvar0=v_thr1Thread1of1ForFork1_thidvar0_2, thr1Thread1of1ForFork1_~x1~0=v_thr1Thread1of1ForFork1_~x1~0_8} AuxVars[] AssignedVars[thr1Thread1of1ForFork1_#in~_.offset, thr1Thread1of1ForFork1_~_.base, thr1Thread1of1ForFork1_~b21~0, thr1Thread1of1ForFork1_#res.base, thr1Thread1of1ForFork1_~y1~0, thr1Thread1of1ForFork1_#in~_.base, thr1Thread1of1ForFork1_~_.offset, thr1Thread1of1ForFork1_#res.offset, thr1Thread1of1ForFork1_thidvar1, thr1Thread1of1ForFork1_thidvar0, thr1Thread1of1ForFork1_~x1~0] 104733#[thr1ENTRY, L845-3]don't care [402] thr1ENTRY-->L704loopEntry: Formula: (and (= v_thr1Thread1of1ForFork1_~_.base_1 |v_thr1Thread1of1ForFork1_#in~_.base_1|) (= |v_thr1Thread1of1ForFork1_#in~_.offset_1| v_thr1Thread1of1ForFork1_~_.offset_1)) InVars {thr1Thread1of1ForFork1_#in~_.offset=|v_thr1Thread1of1ForFork1_#in~_.offset_1|, thr1Thread1of1ForFork1_#in~_.base=|v_thr1Thread1of1ForFork1_#in~_.base_1|} OutVars{thr1Thread1of1ForFork1_#in~_.offset=|v_thr1Thread1of1ForFork1_#in~_.offset_1|, thr1Thread1of1ForFork1_#in~_.base=|v_thr1Thread1of1ForFork1_#in~_.base_1|, thr1Thread1of1ForFork1_~_.offset=v_thr1Thread1of1ForFork1_~_.offset_1, thr1Thread1of1ForFork1_~_.base=v_thr1Thread1of1ForFork1_~_.base_1} AuxVars[] AssignedVars[thr1Thread1of1ForFork1_~_.base, thr1Thread1of1ForFork1_~_.offset] 103943#[L704loopEntry, L845-3]don't care [403] L704loopEntry-->L753-1: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 103945#[L753-1, L845-3]don't care [406] L753-1-->L705: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 104497#[L845-3, L705]don't care [328] L845-3-->L845-4: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~pre4#1=|v_ULTIMATE.start_main_#t~pre4#1_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre4#1] 101769#[L845-4, L705]don't care [259] L845-4-->L846: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet5#1=|v_ULTIMATE.start_main_#t~nondet5#1_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet5#1] 101771#[L846, L705]don't care [243] L846-->L846-1: Formula: (= |v_ULTIMATE.start_main_#t~pre6#1_2| |v_#pthreadsForks_4|) InVars {#pthreadsForks=|v_#pthreadsForks_4|} OutVars{#pthreadsForks=|v_#pthreadsForks_4|, ULTIMATE.start_main_#t~pre6#1=|v_ULTIMATE.start_main_#t~pre6#1_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre6#1] 104023#[L846-1, L705]don't care [408] L705-->L707: Formula: (= v_~b1~0_4 1) InVars {} OutVars{~b1~0=v_~b1~0_4} AuxVars[] AssignedVars[~b1~0] 100953#[L707, L846-1]don't care [234] L846-1-->L846-2: Formula: (= (+ 1 |v_#pthreadsForks_6|) |v_#pthreadsForks_5|) InVars {#pthreadsForks=|v_#pthreadsForks_6|} OutVars{#pthreadsForks=|v_#pthreadsForks_5|} AuxVars[] AssignedVars[#pthreadsForks] 100955#[L846-2, L707]don't care [258] L846-2-->L846-3: Formula: (and (<= (+ 4 |v_ULTIMATE.start_main_~#t2~0#1.offset_3|) (select |v_#length_6| |v_ULTIMATE.start_main_~#t2~0#1.base_3|)) (= (store |v_#memory_int_4| |v_ULTIMATE.start_main_~#t2~0#1.base_3| (store (select |v_#memory_int_4| |v_ULTIMATE.start_main_~#t2~0#1.base_3|) |v_ULTIMATE.start_main_~#t2~0#1.offset_3| |v_ULTIMATE.start_main_#t~pre6#1_3|)) |v_#memory_int_3|) (= (select |v_#valid_6| |v_ULTIMATE.start_main_~#t2~0#1.base_3|) 1) (<= 0 |v_ULTIMATE.start_main_~#t2~0#1.offset_3|)) InVars {ULTIMATE.start_main_#t~pre6#1=|v_ULTIMATE.start_main_#t~pre6#1_3|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_3|, #valid=|v_#valid_6|, #memory_int=|v_#memory_int_4|, #length=|v_#length_6|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_3|} OutVars{ULTIMATE.start_main_#t~pre6#1=|v_ULTIMATE.start_main_#t~pre6#1_3|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_3|, #valid=|v_#valid_6|, #memory_int=|v_#memory_int_3|, #length=|v_#length_6|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_3|} AuxVars[] AssignedVars[#memory_int] 100513#[L846-3, L707]don't care [411] L707-->L710: Formula: (= v_~x~0_3 1) InVars {} OutVars{~x~0=v_~x~0_3} AuxVars[] AssignedVars[~x~0] 100515#[L710, L846-3]don't care [414] L710-->L713: Formula: (= v_~y~0_12 v_thr1Thread1of1ForFork1_~y1~0_1) InVars {~y~0=v_~y~0_12} OutVars{~y~0=v_~y~0_12, thr1Thread1of1ForFork1_~y1~0=v_thr1Thread1of1ForFork1_~y1~0_1} AuxVars[] AssignedVars[thr1Thread1of1ForFork1_~y1~0] 104387#[L846-3, L713]don't care [417] L713-->L728: Formula: (= v_thr1Thread1of1ForFork1_~y1~0_5 0) InVars {thr1Thread1of1ForFork1_~y1~0=v_thr1Thread1of1ForFork1_~y1~0_5} OutVars{thr1Thread1of1ForFork1_~y1~0=v_thr1Thread1of1ForFork1_~y1~0_5} AuxVars[] AssignedVars[] 103823#[L846-3, L728]don't care [420] L728-->L730: Formula: (= v_~y~0_16 1) InVars {} OutVars{~y~0=v_~y~0_16} AuxVars[] AssignedVars[~y~0] 104229#[L730, L846-3]don't care [446] L846-3-->thr2ENTRY: Formula: (and (= v_thr2Thread1of1ForFork0_thidvar2_2 0) (= |v_ULTIMATE.start_main_#t~pre6#1_6| v_thr2Thread1of1ForFork0_thidvar0_2) (= |v_thr2Thread1of1ForFork0_#in~_.offset_4| 0) (= |v_thr2Thread1of1ForFork0_#in~_.base_4| 0) (= v_thr2Thread1of1ForFork0_thidvar1_2 0)) InVars {ULTIMATE.start_main_#t~pre6#1=|v_ULTIMATE.start_main_#t~pre6#1_6|} OutVars{thr2Thread1of1ForFork0_~y2~0=v_thr2Thread1of1ForFork0_~y2~0_30, ULTIMATE.start_main_#t~pre6#1=|v_ULTIMATE.start_main_#t~pre6#1_6|, thr2Thread1of1ForFork0_#in~_.offset=|v_thr2Thread1of1ForFork0_#in~_.offset_4|, thr2Thread1of1ForFork0_#res.base=|v_thr2Thread1of1ForFork0_#res.base_4|, thr2Thread1of1ForFork0_~x2~0=v_thr2Thread1of1ForFork0_~x2~0_8, thr2Thread1of1ForFork0_#res.offset=|v_thr2Thread1of1ForFork0_#res.offset_4|, thr2Thread1of1ForFork0_~b12~0=v_thr2Thread1of1ForFork0_~b12~0_10, thr2Thread1of1ForFork0_#in~_.base=|v_thr2Thread1of1ForFork0_#in~_.base_4|, thr2Thread1of1ForFork0_~_.base=v_thr2Thread1of1ForFork0_~_.base_4, thr2Thread1of1ForFork0_~_.offset=v_thr2Thread1of1ForFork0_~_.offset_4, thr2Thread1of1ForFork0_thidvar0=v_thr2Thread1of1ForFork0_thidvar0_2, thr2Thread1of1ForFork0_thidvar1=v_thr2Thread1of1ForFork0_thidvar1_2, thr2Thread1of1ForFork0_thidvar2=v_thr2Thread1of1ForFork0_thidvar2_2} AuxVars[] AssignedVars[thr2Thread1of1ForFork0_~y2~0, thr2Thread1of1ForFork0_~_.offset, thr2Thread1of1ForFork0_#in~_.offset, thr2Thread1of1ForFork0_#res.base, thr2Thread1of1ForFork0_thidvar0, thr2Thread1of1ForFork0_thidvar1, thr2Thread1of1ForFork0_thidvar2, thr2Thread1of1ForFork0_~x2~0, thr2Thread1of1ForFork0_#res.offset, thr2Thread1of1ForFork0_~b12~0, thr2Thread1of1ForFork0_#in~_.base, thr2Thread1of1ForFork0_~_.base] 104207#[L730, thr2ENTRY, L846-4]don't care [360] thr2ENTRY-->L774loopEntry: Formula: (and (= |v_thr2Thread1of1ForFork0_#in~_.base_1| v_thr2Thread1of1ForFork0_~_.base_1) (= v_thr2Thread1of1ForFork0_~_.offset_1 |v_thr2Thread1of1ForFork0_#in~_.offset_1|)) InVars {thr2Thread1of1ForFork0_#in~_.offset=|v_thr2Thread1of1ForFork0_#in~_.offset_1|, thr2Thread1of1ForFork0_#in~_.base=|v_thr2Thread1of1ForFork0_#in~_.base_1|} OutVars{thr2Thread1of1ForFork0_~_.offset=v_thr2Thread1of1ForFork0_~_.offset_1, thr2Thread1of1ForFork0_#in~_.offset=|v_thr2Thread1of1ForFork0_#in~_.offset_1|, thr2Thread1of1ForFork0_#in~_.base=|v_thr2Thread1of1ForFork0_#in~_.base_1|, thr2Thread1of1ForFork0_~_.base=v_thr2Thread1of1ForFork0_~_.base_1} AuxVars[] AssignedVars[thr2Thread1of1ForFork0_~_.offset, thr2Thread1of1ForFork0_~_.base] 102973#[L730, L774loopEntry, L846-4]don't care [361] L774loopEntry-->L823-1: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 102937#[L730, L823-1, L846-4]don't care [364] L823-1-->L775: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 102263#[L730, L775, L846-4]don't care [366] L775-->L777: Formula: (= v_~b2~0_1 1) InVars {} OutVars{~b2~0=v_~b2~0_1} AuxVars[] AssignedVars[~b2~0] 102265#[L730, L777, L846-4]don't care [369] L777-->L780: Formula: (= 2 v_~x~0_1) InVars {} OutVars{~x~0=v_~x~0_1} AuxVars[] AssignedVars[~x~0] 104283#[L730, L780, L846-4]don't care [372] L780-->L783: Formula: (= v_~y~0_2 v_thr2Thread1of1ForFork0_~y2~0_1) InVars {~y~0=v_~y~0_2} OutVars{~y~0=v_~y~0_2, thr2Thread1of1ForFork0_~y2~0=v_thr2Thread1of1ForFork0_~y2~0_1} AuxVars[] AssignedVars[thr2Thread1of1ForFork0_~y2~0] 105261#[L783, L730, L846-4]don't care [374] L783-->L785: Formula: (not (= v_thr2Thread1of1ForFork0_~y2~0_3 0)) InVars {thr2Thread1of1ForFork0_~y2~0=v_thr2Thread1of1ForFork0_~y2~0_3} OutVars{thr2Thread1of1ForFork0_~y2~0=v_thr2Thread1of1ForFork0_~y2~0_3} AuxVars[] AssignedVars[] 105263#[L730, L785, L846-4]don't care [377] L785-->L787: Formula: (= v_~b2~0_2 0) InVars {} OutVars{~b2~0=v_~b2~0_2} AuxVars[] AssignedVars[~b2~0] 105513#[L730, L787, L846-4]don't care [380] L787-->L794: Formula: (= v_~y~0_3 v_thr2Thread1of1ForFork0_~y2~0_7) InVars {~y~0=v_~y~0_3} OutVars{~y~0=v_~y~0_3, thr2Thread1of1ForFork0_~y2~0=v_thr2Thread1of1ForFork0_~y2~0_7} AuxVars[] AssignedVars[thr2Thread1of1ForFork0_~y2~0] 105517#[L730, L794, L846-4]don't care [2022-07-26 13:22:17,718 INFO L735 eck$LassoCheckResult]: Loop: 105517#[L730, L794, L846-4]don't care [384] L794-->L792: Formula: (not (= v_thr2Thread1of1ForFork0_~y2~0_11 0)) InVars {thr2Thread1of1ForFork0_~y2~0=v_thr2Thread1of1ForFork0_~y2~0_11} OutVars{thr2Thread1of1ForFork0_~y2~0=v_thr2Thread1of1ForFork0_~y2~0_11} AuxVars[] AssignedVars[] 105519#[L730, L792, L846-4]don't care [387] L792-->L794: Formula: (= v_thr2Thread1of1ForFork0_~y2~0_13 v_~y~0_5) InVars {~y~0=v_~y~0_5} OutVars{~y~0=v_~y~0_5, thr2Thread1of1ForFork0_~y2~0=v_thr2Thread1of1ForFork0_~y2~0_13} AuxVars[] AssignedVars[thr2Thread1of1ForFork0_~y2~0] 105517#[L730, L794, L846-4]don't care [2022-07-26 13:22:17,718 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:17,718 INFO L85 PathProgramCache]: Analyzing trace with hash 1620938889, now seen corresponding path program 1 times [2022-07-26 13:22:17,718 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:17,719 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1711446045] [2022-07-26 13:22:17,719 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:17,722 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:17,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:17,743 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-26 13:22:17,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:17,763 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-26 13:22:17,763 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:17,764 INFO L85 PathProgramCache]: Analyzing trace with hash 13252, now seen corresponding path program 2 times [2022-07-26 13:22:17,764 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:17,764 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1180104354] [2022-07-26 13:22:17,764 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:17,765 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:17,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:17,768 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-26 13:22:17,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:17,772 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-26 13:22:17,772 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:17,772 INFO L85 PathProgramCache]: Analyzing trace with hash -1350843828, now seen corresponding path program 1 times [2022-07-26 13:22:17,773 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:17,773 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1891230589] [2022-07-26 13:22:17,773 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:17,773 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:17,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:17,790 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-26 13:22:17,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:17,807 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-26 13:22:18,798 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 26.07 01:22:18 BoogieIcfgContainer [2022-07-26 13:22:18,798 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-07-26 13:22:18,799 INFO L158 Benchmark]: Toolchain (without parser) took 7115.27ms. Allocated memory was 195.0MB in the beginning and 859.8MB in the end (delta: 664.8MB). Free memory was 145.0MB in the beginning and 662.0MB in the end (delta: -516.9MB). Peak memory consumption was 279.0MB. Max. memory is 8.0GB. [2022-07-26 13:22:18,799 INFO L158 Benchmark]: CDTParser took 0.13ms. Allocated memory is still 195.0MB. Free memory is still 163.5MB. There was no memory consumed. Max. memory is 8.0GB. [2022-07-26 13:22:18,800 INFO L158 Benchmark]: CACSL2BoogieTranslator took 554.83ms. Allocated memory is still 195.0MB. Free memory was 144.8MB in the beginning and 162.3MB in the end (delta: -17.5MB). Peak memory consumption was 12.7MB. Max. memory is 8.0GB. [2022-07-26 13:22:18,800 INFO L158 Benchmark]: Boogie Procedure Inliner took 55.36ms. Allocated memory is still 195.0MB. Free memory was 162.3MB in the beginning and 160.4MB in the end (delta: 1.9MB). Peak memory consumption was 2.1MB. Max. memory is 8.0GB. [2022-07-26 13:22:18,800 INFO L158 Benchmark]: Boogie Preprocessor took 36.12ms. Allocated memory is still 195.0MB. Free memory was 160.4MB in the beginning and 158.7MB in the end (delta: 1.7MB). Peak memory consumption was 2.1MB. Max. memory is 8.0GB. [2022-07-26 13:22:18,801 INFO L158 Benchmark]: RCFGBuilder took 419.46ms. Allocated memory is still 195.0MB. Free memory was 158.7MB in the beginning and 145.0MB in the end (delta: 13.6MB). Peak memory consumption was 13.6MB. Max. memory is 8.0GB. [2022-07-26 13:22:18,801 INFO L158 Benchmark]: BuchiAutomizer took 6045.18ms. Allocated memory was 195.0MB in the beginning and 859.8MB in the end (delta: 664.8MB). Free memory was 145.0MB in the beginning and 662.0MB in the end (delta: -516.9MB). Peak memory consumption was 278.8MB. Max. memory is 8.0GB. [2022-07-26 13:22:18,803 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.13ms. Allocated memory is still 195.0MB. Free memory is still 163.5MB. There was no memory consumed. Max. memory is 8.0GB. * CACSL2BoogieTranslator took 554.83ms. Allocated memory is still 195.0MB. Free memory was 144.8MB in the beginning and 162.3MB in the end (delta: -17.5MB). Peak memory consumption was 12.7MB. Max. memory is 8.0GB. * Boogie Procedure Inliner took 55.36ms. Allocated memory is still 195.0MB. Free memory was 162.3MB in the beginning and 160.4MB in the end (delta: 1.9MB). Peak memory consumption was 2.1MB. Max. memory is 8.0GB. * Boogie Preprocessor took 36.12ms. Allocated memory is still 195.0MB. Free memory was 160.4MB in the beginning and 158.7MB in the end (delta: 1.7MB). Peak memory consumption was 2.1MB. Max. memory is 8.0GB. * RCFGBuilder took 419.46ms. Allocated memory is still 195.0MB. Free memory was 158.7MB in the beginning and 145.0MB in the end (delta: 13.6MB). Peak memory consumption was 13.6MB. Max. memory is 8.0GB. * BuchiAutomizer took 6045.18ms. Allocated memory was 195.0MB in the beginning and 859.8MB in the end (delta: 664.8MB). Free memory was 145.0MB in the beginning and 662.0MB in the end (delta: -516.9MB). Peak memory consumption was 278.8MB. Max. memory is 8.0GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 7 terminating modules (7 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.7 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 2987 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 5.9s and 8 iterations. TraceHistogramMax:1. Analysis of lassos took 1.9s. Construction of modules took 0.4s. Büchi inclusion checks took 2.7s. Highest rank in rank-based complementation 0. Minimization of det autom 7. Minimization of nondet autom 0. Automata minimization 1.2s AutomataMinimizationTime, 7 MinimizatonAttempts, 10027 StatesRemovedByMinimization, 6 NontrivialMinimizations. Non-live state removal took 0.7s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 1159 SdHoareTripleChecker+Valid, 0.5s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 1159 mSDsluCounter, 2819 SdHoareTripleChecker+Invalid, 0.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 1730 mSDsCounter, 122 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 475 IncrementalHoareTripleChecker+Invalid, 597 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 122 mSolverCounterUnsat, 1140 mSDtfsCounter, 475 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc0 concLT0 SILN4 SILU0 SILI0 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 791]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {\result=0, \result={0:0}, \result={0:0}, _={0:0}, _={0:0}, _={0:0}, _={0:0}, b1=1, b12=0, b2=0, b21=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@49b6fd2 in25320,0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4f2a553f in0,0, org.eclipse.cdt.internal.core.dom.parser.c.CASTIdExpression@2086f53f=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTIdExpression@6abc49a9=0, t1={19782:0}, t2={19783:0}, X=0, x=2, x1=0, x2=0, y=1, y1=0, y2=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 791]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L700] 0 int x, y; [L701] 0 int b1, b2; [L702] 0 int X; [L844] 0 pthread_t t1, t2; [L845] FCALL, FORK 0 pthread_create(&t1, 0, thr1, 0) [L704] COND TRUE 1 1 [L706] 1 b1 = 1 [L709] 1 x = 1 [L712] 1 int y1 = y; [L714] COND FALSE 1 !(y1 != 0) [L729] 1 y = 1 [L846] FCALL, FORK 0 pthread_create(&t2, 0, thr2, 0) [L774] COND TRUE 2 1 [L776] 2 b2 = 1 [L779] 2 x = 2 [L782] 2 int y2 = y; [L784] COND TRUE 2 y2 != 0 [L786] 2 b2 = 0 [L789] 2 y2 = y Loop: [L791] COND TRUE y2 != 0 [L793] y2 = y End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-07-26 13:22:18,859 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request...