/usr/bin/java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/BuchiAutomizerCInline.xml -s ../../../trunk/examples/settings/buchiAutomizer/concurrent-automaton-noLbe.epf -i ../../../trunk/examples/svcomp/pthread-atomic/szymanski-b.i -------------------------------------------------------------------------------- This is Ultimate 0.2.2-dev-0d686a6 [2022-07-26 13:22:16,882 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-07-26 13:22:16,884 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-07-26 13:22:16,921 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... 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[2022-07-26 13:22:16,966 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-07-26 13:22:16,967 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-07-26 13:22:16,968 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-07-26 13:22:16,969 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/buchiAutomizer/concurrent-automaton-noLbe.epf [2022-07-26 13:22:16,995 INFO L113 SettingsManager]: Loading preferences was successful [2022-07-26 13:22:16,995 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-07-26 13:22:16,995 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-07-26 13:22:16,995 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-07-26 13:22:16,996 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-07-26 13:22:16,996 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-07-26 13:22:16,996 INFO L138 SettingsManager]: * Use SBE=true [2022-07-26 13:22:16,996 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-07-26 13:22:16,996 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-07-26 13:22:16,996 INFO L138 SettingsManager]: * Use old map elimination=false [2022-07-26 13:22:16,996 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-07-26 13:22:16,996 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-07-26 13:22:16,997 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-07-26 13:22:16,997 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-07-26 13:22:16,997 INFO L138 SettingsManager]: * sizeof long=4 [2022-07-26 13:22:16,997 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-07-26 13:22:16,997 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-07-26 13:22:16,997 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-07-26 13:22:16,997 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-07-26 13:22:16,997 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-07-26 13:22:16,997 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-07-26 13:22:16,997 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-07-26 13:22:16,997 INFO L138 SettingsManager]: * sizeof long double=12 [2022-07-26 13:22:16,997 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-07-26 13:22:16,998 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-07-26 13:22:16,998 INFO L138 SettingsManager]: * Use constant arrays=true [2022-07-26 13:22:16,998 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-07-26 13:22:16,998 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-07-26 13:22:16,998 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-07-26 13:22:17,011 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-07-26 13:22:17,011 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-07-26 13:22:17,011 INFO L138 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2022-07-26 13:22:17,012 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-07-26 13:22:17,012 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release [2022-07-26 13:22:17,171 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-07-26 13:22:17,191 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-07-26 13:22:17,193 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-07-26 13:22:17,194 INFO L271 PluginConnector]: Initializing CDTParser... [2022-07-26 13:22:17,195 INFO L275 PluginConnector]: CDTParser initialized [2022-07-26 13:22:17,196 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/pthread-atomic/szymanski-b.i [2022-07-26 13:22:17,245 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/da85bf091/9e8b0068b7b746adb3b0b3b0a1fa2593/FLAGdd643262a [2022-07-26 13:22:17,647 INFO L306 CDTParser]: Found 1 translation units. [2022-07-26 13:22:17,647 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/pthread-atomic/szymanski-b.i [2022-07-26 13:22:17,660 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/da85bf091/9e8b0068b7b746adb3b0b3b0a1fa2593/FLAGdd643262a [2022-07-26 13:22:17,974 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/da85bf091/9e8b0068b7b746adb3b0b3b0a1fa2593 [2022-07-26 13:22:17,976 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-07-26 13:22:17,977 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2022-07-26 13:22:17,979 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-07-26 13:22:17,980 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-07-26 13:22:17,982 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-07-26 13:22:17,982 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.07 01:22:17" (1/1) ... [2022-07-26 13:22:17,983 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@418ad424 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.07 01:22:17, skipping insertion in model container [2022-07-26 13:22:17,983 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.07 01:22:17" (1/1) ... [2022-07-26 13:22:17,988 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-07-26 13:22:18,023 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-07-26 13:22:18,220 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/pthread-atomic/szymanski-b.i[30088,30101] [2022-07-26 13:22:18,222 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/pthread-atomic/szymanski-b.i[30375,30388] [2022-07-26 13:22:18,226 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-26 13:22:18,230 INFO L203 MainTranslator]: Completed pre-run [2022-07-26 13:22:18,273 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/pthread-atomic/szymanski-b.i[30088,30101] [2022-07-26 13:22:18,275 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/pthread-atomic/szymanski-b.i[30375,30388] [2022-07-26 13:22:18,277 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-07-26 13:22:18,300 INFO L208 MainTranslator]: Completed translation [2022-07-26 13:22:18,301 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.07 01:22:18 WrapperNode [2022-07-26 13:22:18,301 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-07-26 13:22:18,302 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-07-26 13:22:18,302 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-07-26 13:22:18,302 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-07-26 13:22:18,307 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.07 01:22:18" (1/1) ... [2022-07-26 13:22:18,329 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.07 01:22:18" (1/1) ... [2022-07-26 13:22:18,344 INFO L137 Inliner]: procedures = 167, calls = 18, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 42 [2022-07-26 13:22:18,344 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-07-26 13:22:18,344 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-07-26 13:22:18,345 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-07-26 13:22:18,345 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-07-26 13:22:18,349 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.07 01:22:18" (1/1) ... [2022-07-26 13:22:18,349 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.07 01:22:18" (1/1) ... [2022-07-26 13:22:18,352 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.07 01:22:18" (1/1) ... [2022-07-26 13:22:18,352 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.07 01:22:18" (1/1) ... [2022-07-26 13:22:18,355 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.07 01:22:18" (1/1) ... [2022-07-26 13:22:18,366 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.07 01:22:18" (1/1) ... [2022-07-26 13:22:18,367 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.07 01:22:18" (1/1) ... [2022-07-26 13:22:18,369 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-07-26 13:22:18,369 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-07-26 13:22:18,369 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-07-26 13:22:18,369 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-07-26 13:22:18,370 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.07 01:22:18" (1/1) ... [2022-07-26 13:22:18,377 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-07-26 13:22:18,387 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-07-26 13:22:18,397 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-07-26 13:22:18,401 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-07-26 13:22:18,422 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-07-26 13:22:18,422 INFO L130 BoogieDeclarations]: Found specification of procedure thr2 [2022-07-26 13:22:18,423 INFO L138 BoogieDeclarations]: Found implementation of procedure thr2 [2022-07-26 13:22:18,423 INFO L130 BoogieDeclarations]: Found specification of procedure thr1 [2022-07-26 13:22:18,423 INFO L138 BoogieDeclarations]: Found implementation of procedure thr1 [2022-07-26 13:22:18,423 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-07-26 13:22:18,423 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-07-26 13:22:18,423 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-07-26 13:22:18,423 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-07-26 13:22:18,423 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-07-26 13:22:18,423 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-07-26 13:22:18,423 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-07-26 13:22:18,424 WARN L208 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2022-07-26 13:22:18,488 INFO L234 CfgBuilder]: Building ICFG [2022-07-26 13:22:18,489 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-07-26 13:22:18,628 INFO L275 CfgBuilder]: Performing block encoding [2022-07-26 13:22:18,633 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-07-26 13:22:18,633 INFO L299 CfgBuilder]: Removed 8 assume(true) statements. [2022-07-26 13:22:18,635 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.07 01:22:18 BoogieIcfgContainer [2022-07-26 13:22:18,635 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-07-26 13:22:18,636 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-07-26 13:22:18,636 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-07-26 13:22:18,654 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-07-26 13:22:18,654 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-26 13:22:18,654 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 26.07 01:22:17" (1/3) ... [2022-07-26 13:22:18,655 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@298b481a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.07 01:22:18, skipping insertion in model container [2022-07-26 13:22:18,655 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-26 13:22:18,655 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.07 01:22:18" (2/3) ... [2022-07-26 13:22:18,655 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@298b481a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.07 01:22:18, skipping insertion in model container [2022-07-26 13:22:18,655 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-07-26 13:22:18,655 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.07 01:22:18" (3/3) ... [2022-07-26 13:22:18,656 INFO L322 chiAutomizerObserver]: Analyzing ICFG szymanski-b.i [2022-07-26 13:22:18,711 INFO L144 ThreadInstanceAdder]: Constructed 2 joinOtherThreadTransitions. [2022-07-26 13:22:18,731 INFO L74 FinitePrefix]: Start finitePrefix. Operand has 86 places, 101 transitions, 218 flow [2022-07-26 13:22:18,778 INFO L129 PetriNetUnfolder]: 20/97 cut-off events. [2022-07-26 13:22:18,778 INFO L130 PetriNetUnfolder]: For 2/2 co-relation queries the response was YES. [2022-07-26 13:22:18,781 INFO L84 FinitePrefix]: Finished finitePrefix Result has 106 conditions, 97 events. 20/97 cut-off events. For 2/2 co-relation queries the response was YES. Maximal size of possible extension queue 4. Compared 100 event pairs, 0 based on Foata normal form. 0/77 useless extension candidates. Maximal degree in co-relation 65. Up to 3 conditions per place. [2022-07-26 13:22:18,781 INFO L82 GeneralOperation]: Start removeDead. Operand has 86 places, 101 transitions, 218 flow [2022-07-26 13:22:18,786 INFO L88 GeneralOperation]: Finished RemoveDead, result has has 84 places, 97 transitions, 206 flow [2022-07-26 13:22:18,795 INFO L301 stractBuchiCegarLoop]: Interprodecural is true [2022-07-26 13:22:18,795 INFO L302 stractBuchiCegarLoop]: Hoare is false [2022-07-26 13:22:18,795 INFO L303 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-07-26 13:22:18,797 INFO L304 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-07-26 13:22:18,797 INFO L305 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-07-26 13:22:18,797 INFO L306 stractBuchiCegarLoop]: Difference is false [2022-07-26 13:22:18,797 INFO L307 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-07-26 13:22:18,798 INFO L311 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-07-26 13:22:18,799 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand currently 0 states, but on-demand construction may add more states [2022-07-26 13:22:19,040 INFO L131 ngComponentsAnalysis]: Automaton has 548 accepting balls. 548 [2022-07-26 13:22:19,041 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-26 13:22:19,041 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-26 13:22:19,045 INFO L150 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-26 13:22:19,045 INFO L151 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-07-26 13:22:19,046 INFO L333 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-07-26 13:22:19,046 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand currently 1488 states, but on-demand construction may add more states [2022-07-26 13:22:19,087 INFO L131 ngComponentsAnalysis]: Automaton has 548 accepting balls. 548 [2022-07-26 13:22:19,088 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-26 13:22:19,088 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-26 13:22:19,089 INFO L150 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-26 13:22:19,090 INFO L151 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-07-26 13:22:19,099 INFO L733 eck$LassoCheckResult]: Stem: 89#[ULTIMATE.startENTRY]don't care [266] ULTIMATE.startENTRY-->L-1: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 92#[L-1]don't care [245] L-1-->L-1-1: Formula: (and (= |v_#NULL.base_1| 0) (= |v_#NULL.offset_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] 94#[L-1-1]don't care [272] L-1-1-->L-1-2: Formula: (= (select |v_#valid_1| 0) 0) InVars {#valid=|v_#valid_1|} OutVars{#valid=|v_#valid_1|} AuxVars[] AssignedVars[] 96#[L-1-2]don't care [274] L-1-2-->L12: Formula: (< 0 |v_#StackHeapBarrier_1|) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|} AuxVars[] AssignedVars[] 98#[L12]don't care [220] L12-->L12-1: Formula: (and (= (select |v_#valid_2| 1) 1) (= 2 (select |v_#length_1| 1))) InVars {#length=|v_#length_1|, #valid=|v_#valid_2|} OutVars{#length=|v_#length_1|, #valid=|v_#valid_2|} AuxVars[] AssignedVars[] 100#[L12-1]don't care [239] L12-1-->L12-2: Formula: (= 48 (select (select |v_#memory_int_1| 1) 0)) InVars {#memory_int=|v_#memory_int_1|} OutVars{#memory_int=|v_#memory_int_1|} AuxVars[] AssignedVars[] 102#[L12-2]don't care [237] L12-2-->L12-3: Formula: (= (select (select |v_#memory_int_2| 1) 1) 0) InVars {#memory_int=|v_#memory_int_2|} OutVars{#memory_int=|v_#memory_int_2|} AuxVars[] AssignedVars[] 104#[L12-3]don't care [268] L12-3-->L12-4: Formula: (and (= 12 (select |v_#length_2| 2)) (= (select |v_#valid_3| 2) 1)) InVars {#length=|v_#length_2|, #valid=|v_#valid_3|} OutVars{#length=|v_#length_2|, #valid=|v_#valid_3|} AuxVars[] AssignedVars[] 106#[L12-4]don't care [253] L12-4-->L684: Formula: (= v_~flag1~0_16 0) InVars {} OutVars{~flag1~0=v_~flag1~0_16} AuxVars[] AssignedVars[~flag1~0] 108#[L684]don't care [195] L684-->L685: Formula: (= v_~flag2~0_16 0) InVars {} OutVars{~flag2~0=v_~flag2~0_16} AuxVars[] AssignedVars[~flag2~0] 110#[L685]don't care [219] L685-->L-1-3: Formula: (= v_~x~0_7 0) InVars {} OutVars{~x~0=v_~x~0_7} AuxVars[] AssignedVars[~x~0] 112#[L-1-3]don't care [276] L-1-3-->L-1-4: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 114#[L-1-4]don't care [251] L-1-4-->L-1-5: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 116#[L-1-5]don't care [217] L-1-5-->L-1-6: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res#1=|v_ULTIMATE.start_main_#res#1_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res#1] 118#[L-1-6]don't care [249] L-1-6-->L719: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_1|, ULTIMATE.start_main_#t~nondet4#1=|v_ULTIMATE.start_main_#t~nondet4#1_1|, ULTIMATE.start_main_#t~mem7#1=|v_ULTIMATE.start_main_#t~mem7#1_1|, ULTIMATE.start_main_#t~mem8#1=|v_ULTIMATE.start_main_#t~mem8#1_1|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_1|, ULTIMATE.start_main_#t~nondet6#1=|v_ULTIMATE.start_main_#t~nondet6#1_1|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_1|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_1|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_1|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre5#1, ULTIMATE.start_main_#t~nondet4#1, ULTIMATE.start_main_#t~mem7#1, ULTIMATE.start_main_#t~mem8#1, ULTIMATE.start_main_~#t2~0#1.offset, ULTIMATE.start_main_#t~nondet6#1, ULTIMATE.start_main_~#t1~0#1.base, ULTIMATE.start_main_~#t1~0#1.offset, ULTIMATE.start_main_#t~pre3#1, ULTIMATE.start_main_~#t2~0#1.base] 120#[L719]don't care [194] L719-->L719-1: Formula: (and (= |v_ULTIMATE.start_main_~#t1~0#1.offset_2| 0) (= (select |v_#valid_5| |v_ULTIMATE.start_main_~#t1~0#1.base_2|) 0) (< |v_#StackHeapBarrier_2| |v_ULTIMATE.start_main_~#t1~0#1.base_2|) (= |v_#length_3| (store |v_#length_4| |v_ULTIMATE.start_main_~#t1~0#1.base_2| 4)) (not (= |v_ULTIMATE.start_main_~#t1~0#1.base_2| 0)) (= (store |v_#valid_5| |v_ULTIMATE.start_main_~#t1~0#1.base_2| 1) |v_#valid_4|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_4|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_2|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_2|, #valid=|v_#valid_4|} AuxVars[] AssignedVars[#valid, #length, ULTIMATE.start_main_~#t1~0#1.base, ULTIMATE.start_main_~#t1~0#1.offset] 122#[L719-1]don't care [262] L719-1-->L719-2: Formula: (and (= |v_#length_5| (store |v_#length_6| |v_ULTIMATE.start_main_~#t2~0#1.base_2| 4)) (= (select |v_#valid_7| |v_ULTIMATE.start_main_~#t2~0#1.base_2|) 0) (= (store |v_#valid_7| |v_ULTIMATE.start_main_~#t2~0#1.base_2| 1) |v_#valid_6|) (not (= |v_ULTIMATE.start_main_~#t2~0#1.base_2| 0)) (= 0 |v_ULTIMATE.start_main_~#t2~0#1.offset_2|) (< |v_#StackHeapBarrier_3| |v_ULTIMATE.start_main_~#t2~0#1.base_2|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_3|, #length=|v_#length_6|, #valid=|v_#valid_7|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_3|, #length=|v_#length_5|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_2|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_2|, #valid=|v_#valid_6|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2~0#1.offset, #valid, #length, ULTIMATE.start_main_~#t2~0#1.base] 124#[L719-2]don't care [231] L719-2-->L720: Formula: (= |v_ULTIMATE.start_main_#t~pre3#1_2| |v_#pthreadsForks_1|) InVars {#pthreadsForks=|v_#pthreadsForks_1|} OutVars{#pthreadsForks=|v_#pthreadsForks_1|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre3#1] 126#[L720]don't care [236] L720-->L720-1: Formula: (= (+ 1 |v_#pthreadsForks_3|) |v_#pthreadsForks_2|) InVars {#pthreadsForks=|v_#pthreadsForks_3|} OutVars{#pthreadsForks=|v_#pthreadsForks_2|} AuxVars[] AssignedVars[#pthreadsForks] 128#[L720-1]don't care [250] L720-1-->L720-2: Formula: (and (<= 0 |v_ULTIMATE.start_main_~#t1~0#1.offset_3|) (= (select |v_#valid_8| |v_ULTIMATE.start_main_~#t1~0#1.base_3|) 1) (<= (+ |v_ULTIMATE.start_main_~#t1~0#1.offset_3| 4) (select |v_#length_7| |v_ULTIMATE.start_main_~#t1~0#1.base_3|)) (= (store |v_#memory_int_4| |v_ULTIMATE.start_main_~#t1~0#1.base_3| (store (select |v_#memory_int_4| |v_ULTIMATE.start_main_~#t1~0#1.base_3|) |v_ULTIMATE.start_main_~#t1~0#1.offset_3| |v_ULTIMATE.start_main_#t~pre3#1_3|)) |v_#memory_int_3|)) InVars {#valid=|v_#valid_8|, #memory_int=|v_#memory_int_4|, #length=|v_#length_7|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_3|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_3|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_3|} OutVars{#valid=|v_#valid_8|, #memory_int=|v_#memory_int_3|, #length=|v_#length_7|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_3|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_3|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_3|} AuxVars[] AssignedVars[#memory_int] 130#[L720-2]don't care [340] L720-2-->thr1ENTRY: Formula: (and (= 0 |v_thr1Thread1of1ForFork0_#in~_.base_4|) (= |v_thr1Thread1of1ForFork0_#in~_.offset_4| 0) (= v_thr1Thread1of1ForFork0_thidvar1_2 0) (= |v_ULTIMATE.start_main_#t~pre3#1_6| v_thr1Thread1of1ForFork0_thidvar0_2)) InVars {ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_6|} OutVars{thr1Thread1of1ForFork0_~_.base=v_thr1Thread1of1ForFork0_~_.base_4, thr1Thread1of1ForFork0_#in~_.offset=|v_thr1Thread1of1ForFork0_#in~_.offset_4|, thr1Thread1of1ForFork0_#res.base=|v_thr1Thread1of1ForFork0_#res.base_4|, thr1Thread1of1ForFork0_thidvar0=v_thr1Thread1of1ForFork0_thidvar0_2, thr1Thread1of1ForFork0_thidvar1=v_thr1Thread1of1ForFork0_thidvar1_2, thr1Thread1of1ForFork0_#in~_.base=|v_thr1Thread1of1ForFork0_#in~_.base_4|, thr1Thread1of1ForFork0_#res.offset=|v_thr1Thread1of1ForFork0_#res.offset_4|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_6|, thr1Thread1of1ForFork0_~_.offset=v_thr1Thread1of1ForFork0_~_.offset_4} AuxVars[] AssignedVars[thr1Thread1of1ForFork0_~_.base, thr1Thread1of1ForFork0_#in~_.offset, thr1Thread1of1ForFork0_#res.base, thr1Thread1of1ForFork0_thidvar0, thr1Thread1of1ForFork0_thidvar1, thr1Thread1of1ForFork0_#in~_.base, thr1Thread1of1ForFork0_#res.offset, thr1Thread1of1ForFork0_~_.offset] 132#[thr1ENTRY, L720-3]don't care [311] thr1ENTRY-->L687: Formula: (and (= v_thr1Thread1of1ForFork0_~_.base_1 |v_thr1Thread1of1ForFork0_#in~_.base_1|) (= |v_thr1Thread1of1ForFork0_#in~_.offset_1| v_thr1Thread1of1ForFork0_~_.offset_1)) InVars {thr1Thread1of1ForFork0_#in~_.base=|v_thr1Thread1of1ForFork0_#in~_.base_1|, thr1Thread1of1ForFork0_#in~_.offset=|v_thr1Thread1of1ForFork0_#in~_.offset_1|} OutVars{thr1Thread1of1ForFork0_~_.base=v_thr1Thread1of1ForFork0_~_.base_1, thr1Thread1of1ForFork0_#in~_.offset=|v_thr1Thread1of1ForFork0_#in~_.offset_1|, thr1Thread1of1ForFork0_#in~_.base=|v_thr1Thread1of1ForFork0_#in~_.base_1|, thr1Thread1of1ForFork0_~_.offset=v_thr1Thread1of1ForFork0_~_.offset_1} AuxVars[] AssignedVars[thr1Thread1of1ForFork0_~_.base, thr1Thread1of1ForFork0_~_.offset] 134#[L687, L720-3]don't care [312] L687-->L688-2: Formula: (= v_~flag1~0_11 1) InVars {} OutVars{~flag1~0=v_~flag1~0_11} AuxVars[] AssignedVars[~flag1~0] 138#[L688-2, L720-3]don't care [2022-07-26 13:22:19,100 INFO L735 eck$LassoCheckResult]: Loop: 138#[L688-2, L720-3]don't care [315] L688-2-->L688-2: Formula: (<= 3 v_~flag2~0_9) InVars {~flag2~0=v_~flag2~0_9} OutVars{~flag2~0=v_~flag2~0_9} AuxVars[] AssignedVars[] 138#[L688-2, L720-3]don't care [2022-07-26 13:22:19,107 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:19,107 INFO L85 PathProgramCache]: Analyzing trace with hash 473020928, now seen corresponding path program 1 times [2022-07-26 13:22:19,113 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:19,113 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [331868049] [2022-07-26 13:22:19,113 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:19,114 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:19,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:19,206 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-26 13:22:19,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:19,237 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-26 13:22:19,239 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:19,239 INFO L85 PathProgramCache]: Analyzing trace with hash 346, now seen corresponding path program 1 times [2022-07-26 13:22:19,239 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:19,240 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1031925419] [2022-07-26 13:22:19,240 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:19,240 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:19,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:19,263 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-26 13:22:19,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:19,267 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-26 13:22:19,268 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:19,268 INFO L85 PathProgramCache]: Analyzing trace with hash 1778747195, now seen corresponding path program 1 times [2022-07-26 13:22:19,268 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:19,268 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [848177160] [2022-07-26 13:22:19,268 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:19,273 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:19,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-26 13:22:19,410 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-26 13:22:19,411 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-26 13:22:19,411 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [848177160] [2022-07-26 13:22:19,411 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [848177160] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-26 13:22:19,411 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-26 13:22:19,412 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-26 13:22:19,412 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [707715898] [2022-07-26 13:22:19,412 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-26 13:22:19,427 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-26 13:22:19,448 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-26 13:22:19,448 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-26 13:22:19,450 INFO L87 Difference]: Start difference. First operand currently 1488 states, but on-demand construction may add more states Second operand has 3 states, 2 states have (on average 12.0) internal successors, (24), 3 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-26 13:22:19,502 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-26 13:22:19,502 INFO L93 Difference]: Finished difference Result 1312 states and 3898 transitions. [2022-07-26 13:22:19,503 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1312 states and 3898 transitions. [2022-07-26 13:22:19,514 INFO L131 ngComponentsAnalysis]: Automaton has 424 accepting balls. 424 [2022-07-26 13:22:19,528 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1312 states to 1067 states and 3265 transitions. [2022-07-26 13:22:19,530 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1067 [2022-07-26 13:22:19,534 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1067 [2022-07-26 13:22:19,535 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1067 states and 3265 transitions. [2022-07-26 13:22:19,541 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-26 13:22:19,542 INFO L220 hiAutomatonCegarLoop]: Abstraction has 1067 states and 3265 transitions. [2022-07-26 13:22:19,555 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1067 states and 3265 transitions. [2022-07-26 13:22:19,608 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1067 to 1067. [2022-07-26 13:22:19,611 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1067 states, 1067 states have (on average 3.0599812558575445) internal successors, (3265), 1066 states have internal predecessors, (3265), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-26 13:22:19,615 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1067 states to 1067 states and 3265 transitions. [2022-07-26 13:22:19,616 INFO L242 hiAutomatonCegarLoop]: Abstraction has 1067 states and 3265 transitions. [2022-07-26 13:22:19,617 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-26 13:22:19,622 INFO L426 stractBuchiCegarLoop]: Abstraction has 1067 states and 3265 transitions. [2022-07-26 13:22:19,623 INFO L333 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-07-26 13:22:19,623 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1067 states and 3265 transitions. [2022-07-26 13:22:19,629 INFO L131 ngComponentsAnalysis]: Automaton has 424 accepting balls. 424 [2022-07-26 13:22:19,629 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-26 13:22:19,629 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-26 13:22:19,629 INFO L150 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-26 13:22:19,629 INFO L151 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-07-26 13:22:19,630 INFO L733 eck$LassoCheckResult]: Stem: 6252#[ULTIMATE.startENTRY]don't care [266] ULTIMATE.startENTRY-->L-1: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 6254#[L-1]don't care [245] L-1-->L-1-1: Formula: (and (= |v_#NULL.base_1| 0) (= |v_#NULL.offset_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] 6260#[L-1-1]don't care [272] L-1-1-->L-1-2: Formula: (= (select |v_#valid_1| 0) 0) InVars {#valid=|v_#valid_1|} OutVars{#valid=|v_#valid_1|} AuxVars[] AssignedVars[] 6262#[L-1-2]don't care [274] L-1-2-->L12: Formula: (< 0 |v_#StackHeapBarrier_1|) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|} AuxVars[] AssignedVars[] 5892#[L12]don't care [220] L12-->L12-1: Formula: (and (= (select |v_#valid_2| 1) 1) (= 2 (select |v_#length_1| 1))) InVars {#length=|v_#length_1|, #valid=|v_#valid_2|} OutVars{#length=|v_#length_1|, #valid=|v_#valid_2|} AuxVars[] AssignedVars[] 5894#[L12-1]don't care [239] L12-1-->L12-2: Formula: (= 48 (select (select |v_#memory_int_1| 1) 0)) InVars {#memory_int=|v_#memory_int_1|} OutVars{#memory_int=|v_#memory_int_1|} AuxVars[] AssignedVars[] 5944#[L12-2]don't care [237] L12-2-->L12-3: Formula: (= (select (select |v_#memory_int_2| 1) 1) 0) InVars {#memory_int=|v_#memory_int_2|} OutVars{#memory_int=|v_#memory_int_2|} AuxVars[] AssignedVars[] 5010#[L12-3]don't care [268] L12-3-->L12-4: Formula: (and (= 12 (select |v_#length_2| 2)) (= (select |v_#valid_3| 2) 1)) InVars {#length=|v_#length_2|, #valid=|v_#valid_3|} OutVars{#length=|v_#length_2|, #valid=|v_#valid_3|} AuxVars[] AssignedVars[] 5012#[L12-4]don't care [253] L12-4-->L684: Formula: (= v_~flag1~0_16 0) InVars {} OutVars{~flag1~0=v_~flag1~0_16} AuxVars[] AssignedVars[~flag1~0] 5974#[L684]don't care [195] L684-->L685: Formula: (= v_~flag2~0_16 0) InVars {} OutVars{~flag2~0=v_~flag2~0_16} AuxVars[] AssignedVars[~flag2~0] 6508#[L685]don't care [219] L685-->L-1-3: Formula: (= v_~x~0_7 0) InVars {} OutVars{~x~0=v_~x~0_7} AuxVars[] AssignedVars[~x~0] 6490#[L-1-3]don't care [276] L-1-3-->L-1-4: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 4654#[L-1-4]don't care [251] L-1-4-->L-1-5: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 4656#[L-1-5]don't care [217] L-1-5-->L-1-6: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res#1=|v_ULTIMATE.start_main_#res#1_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res#1] 5544#[L-1-6]don't care [249] L-1-6-->L719: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_1|, ULTIMATE.start_main_#t~nondet4#1=|v_ULTIMATE.start_main_#t~nondet4#1_1|, ULTIMATE.start_main_#t~mem7#1=|v_ULTIMATE.start_main_#t~mem7#1_1|, ULTIMATE.start_main_#t~mem8#1=|v_ULTIMATE.start_main_#t~mem8#1_1|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_1|, ULTIMATE.start_main_#t~nondet6#1=|v_ULTIMATE.start_main_#t~nondet6#1_1|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_1|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_1|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_1|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre5#1, ULTIMATE.start_main_#t~nondet4#1, ULTIMATE.start_main_#t~mem7#1, ULTIMATE.start_main_#t~mem8#1, ULTIMATE.start_main_~#t2~0#1.offset, ULTIMATE.start_main_#t~nondet6#1, ULTIMATE.start_main_~#t1~0#1.base, ULTIMATE.start_main_~#t1~0#1.offset, ULTIMATE.start_main_#t~pre3#1, ULTIMATE.start_main_~#t2~0#1.base] 5546#[L719]don't care [194] L719-->L719-1: Formula: (and (= |v_ULTIMATE.start_main_~#t1~0#1.offset_2| 0) (= (select |v_#valid_5| |v_ULTIMATE.start_main_~#t1~0#1.base_2|) 0) (< |v_#StackHeapBarrier_2| |v_ULTIMATE.start_main_~#t1~0#1.base_2|) (= |v_#length_3| (store |v_#length_4| |v_ULTIMATE.start_main_~#t1~0#1.base_2| 4)) (not (= |v_ULTIMATE.start_main_~#t1~0#1.base_2| 0)) (= (store |v_#valid_5| |v_ULTIMATE.start_main_~#t1~0#1.base_2| 1) |v_#valid_4|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_4|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_2|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_2|, #valid=|v_#valid_4|} AuxVars[] AssignedVars[#valid, #length, ULTIMATE.start_main_~#t1~0#1.base, ULTIMATE.start_main_~#t1~0#1.offset] 5792#[L719-1]don't care [262] L719-1-->L719-2: Formula: (and (= |v_#length_5| (store |v_#length_6| |v_ULTIMATE.start_main_~#t2~0#1.base_2| 4)) (= (select |v_#valid_7| |v_ULTIMATE.start_main_~#t2~0#1.base_2|) 0) (= (store |v_#valid_7| |v_ULTIMATE.start_main_~#t2~0#1.base_2| 1) |v_#valid_6|) (not (= |v_ULTIMATE.start_main_~#t2~0#1.base_2| 0)) (= 0 |v_ULTIMATE.start_main_~#t2~0#1.offset_2|) (< |v_#StackHeapBarrier_3| |v_ULTIMATE.start_main_~#t2~0#1.base_2|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_3|, #length=|v_#length_6|, #valid=|v_#valid_7|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_3|, #length=|v_#length_5|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_2|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_2|, #valid=|v_#valid_6|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2~0#1.offset, #valid, #length, ULTIMATE.start_main_~#t2~0#1.base] 5746#[L719-2]don't care [231] L719-2-->L720: Formula: (= |v_ULTIMATE.start_main_#t~pre3#1_2| |v_#pthreadsForks_1|) InVars {#pthreadsForks=|v_#pthreadsForks_1|} OutVars{#pthreadsForks=|v_#pthreadsForks_1|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre3#1] 5748#[L720]don't care [236] L720-->L720-1: Formula: (= (+ 1 |v_#pthreadsForks_3|) |v_#pthreadsForks_2|) InVars {#pthreadsForks=|v_#pthreadsForks_3|} OutVars{#pthreadsForks=|v_#pthreadsForks_2|} AuxVars[] AssignedVars[#pthreadsForks] 6442#[L720-1]don't care [250] L720-1-->L720-2: Formula: (and (<= 0 |v_ULTIMATE.start_main_~#t1~0#1.offset_3|) (= (select |v_#valid_8| |v_ULTIMATE.start_main_~#t1~0#1.base_3|) 1) (<= (+ |v_ULTIMATE.start_main_~#t1~0#1.offset_3| 4) (select |v_#length_7| |v_ULTIMATE.start_main_~#t1~0#1.base_3|)) (= (store |v_#memory_int_4| |v_ULTIMATE.start_main_~#t1~0#1.base_3| (store (select |v_#memory_int_4| |v_ULTIMATE.start_main_~#t1~0#1.base_3|) |v_ULTIMATE.start_main_~#t1~0#1.offset_3| |v_ULTIMATE.start_main_#t~pre3#1_3|)) |v_#memory_int_3|)) InVars {#valid=|v_#valid_8|, #memory_int=|v_#memory_int_4|, #length=|v_#length_7|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_3|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_3|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_3|} OutVars{#valid=|v_#valid_8|, #memory_int=|v_#memory_int_3|, #length=|v_#length_7|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_3|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_3|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_3|} AuxVars[] AssignedVars[#memory_int] 6444#[L720-2]don't care [340] L720-2-->thr1ENTRY: Formula: (and (= 0 |v_thr1Thread1of1ForFork0_#in~_.base_4|) (= |v_thr1Thread1of1ForFork0_#in~_.offset_4| 0) (= v_thr1Thread1of1ForFork0_thidvar1_2 0) (= |v_ULTIMATE.start_main_#t~pre3#1_6| v_thr1Thread1of1ForFork0_thidvar0_2)) InVars {ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_6|} OutVars{thr1Thread1of1ForFork0_~_.base=v_thr1Thread1of1ForFork0_~_.base_4, thr1Thread1of1ForFork0_#in~_.offset=|v_thr1Thread1of1ForFork0_#in~_.offset_4|, thr1Thread1of1ForFork0_#res.base=|v_thr1Thread1of1ForFork0_#res.base_4|, thr1Thread1of1ForFork0_thidvar0=v_thr1Thread1of1ForFork0_thidvar0_2, thr1Thread1of1ForFork0_thidvar1=v_thr1Thread1of1ForFork0_thidvar1_2, thr1Thread1of1ForFork0_#in~_.base=|v_thr1Thread1of1ForFork0_#in~_.base_4|, thr1Thread1of1ForFork0_#res.offset=|v_thr1Thread1of1ForFork0_#res.offset_4|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_6|, thr1Thread1of1ForFork0_~_.offset=v_thr1Thread1of1ForFork0_~_.offset_4} AuxVars[] AssignedVars[thr1Thread1of1ForFork0_~_.base, thr1Thread1of1ForFork0_#in~_.offset, thr1Thread1of1ForFork0_#res.base, thr1Thread1of1ForFork0_thidvar0, thr1Thread1of1ForFork0_thidvar1, thr1Thread1of1ForFork0_#in~_.base, thr1Thread1of1ForFork0_#res.offset, thr1Thread1of1ForFork0_~_.offset] 5978#[thr1ENTRY, L720-3]don't care [205] L720-3-->L720-4: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre3#1] 5562#[thr1ENTRY, L720-4]don't care [261] L720-4-->L721: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet4#1=|v_ULTIMATE.start_main_#t~nondet4#1_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet4#1] 5564#[thr1ENTRY, L721]don't care [218] L721-->L721-1: Formula: (= |v_ULTIMATE.start_main_#t~pre5#1_2| |v_#pthreadsForks_4|) InVars {#pthreadsForks=|v_#pthreadsForks_4|} OutVars{ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_2|, #pthreadsForks=|v_#pthreadsForks_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre5#1] 5674#[thr1ENTRY, L721-1]don't care [270] L721-1-->L721-2: Formula: (= (+ 1 |v_#pthreadsForks_6|) |v_#pthreadsForks_5|) InVars {#pthreadsForks=|v_#pthreadsForks_6|} OutVars{#pthreadsForks=|v_#pthreadsForks_5|} AuxVars[] AssignedVars[#pthreadsForks] 5676#[thr1ENTRY, L721-2]don't care [197] L721-2-->L721-3: Formula: (and (<= (+ 4 |v_ULTIMATE.start_main_~#t2~0#1.offset_3|) (select |v_#length_8| |v_ULTIMATE.start_main_~#t2~0#1.base_3|)) (= (select |v_#valid_9| |v_ULTIMATE.start_main_~#t2~0#1.base_3|) 1) (= (store |v_#memory_int_6| |v_ULTIMATE.start_main_~#t2~0#1.base_3| (store (select |v_#memory_int_6| |v_ULTIMATE.start_main_~#t2~0#1.base_3|) |v_ULTIMATE.start_main_~#t2~0#1.offset_3| |v_ULTIMATE.start_main_#t~pre5#1_3|)) |v_#memory_int_5|) (<= 0 |v_ULTIMATE.start_main_~#t2~0#1.offset_3|)) InVars {ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_3|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_3|, #valid=|v_#valid_9|, #memory_int=|v_#memory_int_6|, #length=|v_#length_8|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_3|} OutVars{ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_3|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_3|, #valid=|v_#valid_9|, #memory_int=|v_#memory_int_5|, #length=|v_#length_8|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_3|} AuxVars[] AssignedVars[#memory_int] 6292#[thr1ENTRY, L721-3]don't care [343] L721-3-->thr2ENTRY: Formula: (and (= v_thr2Thread1of1ForFork1_thidvar2_2 0) (= |v_thr2Thread1of1ForFork1_#in~_.base_4| 0) (= |v_thr2Thread1of1ForFork1_#in~_.offset_4| 0) (= v_thr2Thread1of1ForFork1_thidvar1_2 0) (= |v_ULTIMATE.start_main_#t~pre5#1_6| v_thr2Thread1of1ForFork1_thidvar0_2)) InVars {ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_6|} OutVars{ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_6|, thr2Thread1of1ForFork1_thidvar0=v_thr2Thread1of1ForFork1_thidvar0_2, thr2Thread1of1ForFork1_thidvar1=v_thr2Thread1of1ForFork1_thidvar1_2, thr2Thread1of1ForFork1_thidvar2=v_thr2Thread1of1ForFork1_thidvar2_2, thr2Thread1of1ForFork1_~_.offset=v_thr2Thread1of1ForFork1_~_.offset_4, thr2Thread1of1ForFork1_#res.base=|v_thr2Thread1of1ForFork1_#res.base_4|, thr2Thread1of1ForFork1_#in~_.offset=|v_thr2Thread1of1ForFork1_#in~_.offset_4|, thr2Thread1of1ForFork1_#res.offset=|v_thr2Thread1of1ForFork1_#res.offset_4|, thr2Thread1of1ForFork1_#in~_.base=|v_thr2Thread1of1ForFork1_#in~_.base_4|, thr2Thread1of1ForFork1_~_.base=v_thr2Thread1of1ForFork1_~_.base_4} AuxVars[] AssignedVars[thr2Thread1of1ForFork1_thidvar0, thr2Thread1of1ForFork1_thidvar1, thr2Thread1of1ForFork1_thidvar2, thr2Thread1of1ForFork1_~_.offset, thr2Thread1of1ForFork1_#res.base, thr2Thread1of1ForFork1_#in~_.offset, thr2Thread1of1ForFork1_#res.offset, thr2Thread1of1ForFork1_#in~_.base, thr2Thread1of1ForFork1_~_.base] 4670#[L721-4, thr2ENTRY, thr1ENTRY]don't care [284] thr2ENTRY-->L703: Formula: (and (= v_thr2Thread1of1ForFork1_~_.offset_1 |v_thr2Thread1of1ForFork1_#in~_.offset_1|) (= |v_thr2Thread1of1ForFork1_#in~_.base_1| v_thr2Thread1of1ForFork1_~_.base_1)) InVars {thr2Thread1of1ForFork1_#in~_.base=|v_thr2Thread1of1ForFork1_#in~_.base_1|, thr2Thread1of1ForFork1_#in~_.offset=|v_thr2Thread1of1ForFork1_#in~_.offset_1|} OutVars{thr2Thread1of1ForFork1_~_.offset=v_thr2Thread1of1ForFork1_~_.offset_1, thr2Thread1of1ForFork1_#in~_.base=|v_thr2Thread1of1ForFork1_#in~_.base_1|, thr2Thread1of1ForFork1_#in~_.offset=|v_thr2Thread1of1ForFork1_#in~_.offset_1|, thr2Thread1of1ForFork1_~_.base=v_thr2Thread1of1ForFork1_~_.base_1} AuxVars[] AssignedVars[thr2Thread1of1ForFork1_~_.offset, thr2Thread1of1ForFork1_~_.base] 4676#[L721-4, L703, thr1ENTRY]don't care [285] L703-->L704-2: Formula: (= v_~flag2~0_1 1) InVars {} OutVars{~flag2~0=v_~flag2~0_1} AuxVars[] AssignedVars[~flag2~0] 6340#[L721-4, L704-2, thr1ENTRY]don't care [2022-07-26 13:22:19,631 INFO L735 eck$LassoCheckResult]: Loop: 6340#[L721-4, L704-2, thr1ENTRY]don't care [288] L704-2-->L704-2: Formula: (<= 3 v_~flag1~0_3) InVars {~flag1~0=v_~flag1~0_3} OutVars{~flag1~0=v_~flag1~0_3} AuxVars[] AssignedVars[] 6340#[L721-4, L704-2, thr1ENTRY]don't care [2022-07-26 13:22:19,631 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:19,631 INFO L85 PathProgramCache]: Analyzing trace with hash -1331703458, now seen corresponding path program 1 times [2022-07-26 13:22:19,631 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:19,631 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1153966039] [2022-07-26 13:22:19,631 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:19,632 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:19,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:19,655 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-26 13:22:19,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:19,668 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-26 13:22:19,669 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:19,669 INFO L85 PathProgramCache]: Analyzing trace with hash 319, now seen corresponding path program 1 times [2022-07-26 13:22:19,669 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:19,669 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [589596421] [2022-07-26 13:22:19,669 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:19,670 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:19,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:19,674 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-26 13:22:19,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:19,676 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-26 13:22:19,676 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:19,677 INFO L85 PathProgramCache]: Analyzing trace with hash 1666866050, now seen corresponding path program 1 times [2022-07-26 13:22:19,677 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:19,677 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [398423384] [2022-07-26 13:22:19,677 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:19,677 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:19,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-26 13:22:19,708 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-26 13:22:19,709 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-26 13:22:19,709 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [398423384] [2022-07-26 13:22:19,709 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [398423384] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-26 13:22:19,709 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-26 13:22:19,709 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-26 13:22:19,709 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [37907524] [2022-07-26 13:22:19,709 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-26 13:22:19,714 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-26 13:22:19,714 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-26 13:22:19,714 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-26 13:22:19,715 INFO L87 Difference]: Start difference. First operand 1067 states and 3265 transitions. cyclomatic complexity: 2622 Second operand has 3 states, 2 states have (on average 15.0) internal successors, (30), 3 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-26 13:22:19,754 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-26 13:22:19,755 INFO L93 Difference]: Finished difference Result 1051 states and 3106 transitions. [2022-07-26 13:22:19,755 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1051 states and 3106 transitions. [2022-07-26 13:22:19,765 INFO L131 ngComponentsAnalysis]: Automaton has 347 accepting balls. 347 [2022-07-26 13:22:19,771 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1051 states to 883 states and 2695 transitions. [2022-07-26 13:22:19,772 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 883 [2022-07-26 13:22:19,773 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 883 [2022-07-26 13:22:19,773 INFO L73 IsDeterministic]: Start isDeterministic. Operand 883 states and 2695 transitions. [2022-07-26 13:22:19,774 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-26 13:22:19,774 INFO L220 hiAutomatonCegarLoop]: Abstraction has 883 states and 2695 transitions. [2022-07-26 13:22:19,777 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 883 states and 2695 transitions. [2022-07-26 13:22:19,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 883 to 883. [2022-07-26 13:22:19,810 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 883 states, 883 states have (on average 3.0520951302378254) internal successors, (2695), 882 states have internal predecessors, (2695), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-26 13:22:19,814 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 883 states to 883 states and 2695 transitions. [2022-07-26 13:22:19,814 INFO L242 hiAutomatonCegarLoop]: Abstraction has 883 states and 2695 transitions. [2022-07-26 13:22:19,814 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-26 13:22:19,815 INFO L426 stractBuchiCegarLoop]: Abstraction has 883 states and 2695 transitions. [2022-07-26 13:22:19,815 INFO L333 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-07-26 13:22:19,815 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 883 states and 2695 transitions. [2022-07-26 13:22:19,820 INFO L131 ngComponentsAnalysis]: Automaton has 347 accepting balls. 347 [2022-07-26 13:22:19,820 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-26 13:22:19,820 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-26 13:22:19,821 INFO L150 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-26 13:22:19,821 INFO L151 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-07-26 13:22:19,822 INFO L733 eck$LassoCheckResult]: Stem: 9143#[ULTIMATE.startENTRY]don't care [266] ULTIMATE.startENTRY-->L-1: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 9145#[L-1]don't care [245] L-1-->L-1-1: Formula: (and (= |v_#NULL.base_1| 0) (= |v_#NULL.offset_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] 9149#[L-1-1]don't care [272] L-1-1-->L-1-2: Formula: (= (select |v_#valid_1| 0) 0) InVars {#valid=|v_#valid_1|} OutVars{#valid=|v_#valid_1|} AuxVars[] AssignedVars[] 9151#[L-1-2]don't care [274] L-1-2-->L12: Formula: (< 0 |v_#StackHeapBarrier_1|) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|} AuxVars[] AssignedVars[] 8827#[L12]don't care [220] L12-->L12-1: Formula: (and (= (select |v_#valid_2| 1) 1) (= 2 (select |v_#length_1| 1))) InVars {#length=|v_#length_1|, #valid=|v_#valid_2|} OutVars{#length=|v_#length_1|, #valid=|v_#valid_2|} AuxVars[] AssignedVars[] 8829#[L12-1]don't care [239] L12-1-->L12-2: Formula: (= 48 (select (select |v_#memory_int_1| 1) 0)) InVars {#memory_int=|v_#memory_int_1|} OutVars{#memory_int=|v_#memory_int_1|} AuxVars[] AssignedVars[] 8877#[L12-2]don't care [237] L12-2-->L12-3: Formula: (= (select (select |v_#memory_int_2| 1) 1) 0) InVars {#memory_int=|v_#memory_int_2|} OutVars{#memory_int=|v_#memory_int_2|} AuxVars[] AssignedVars[] 8111#[L12-3]don't care [268] L12-3-->L12-4: Formula: (and (= 12 (select |v_#length_2| 2)) (= (select |v_#valid_3| 2) 1)) InVars {#length=|v_#length_2|, #valid=|v_#valid_3|} OutVars{#length=|v_#length_2|, #valid=|v_#valid_3|} AuxVars[] AssignedVars[] 8113#[L12-4]don't care [253] L12-4-->L684: Formula: (= v_~flag1~0_16 0) InVars {} OutVars{~flag1~0=v_~flag1~0_16} AuxVars[] AssignedVars[~flag1~0] 8903#[L684]don't care [195] L684-->L685: Formula: (= v_~flag2~0_16 0) InVars {} OutVars{~flag2~0=v_~flag2~0_16} AuxVars[] AssignedVars[~flag2~0] 9333#[L685]don't care [219] L685-->L-1-3: Formula: (= v_~x~0_7 0) InVars {} OutVars{~x~0=v_~x~0_7} AuxVars[] AssignedVars[~x~0] 9321#[L-1-3]don't care [276] L-1-3-->L-1-4: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 7815#[L-1-4]don't care [251] L-1-4-->L-1-5: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 7817#[L-1-5]don't care [217] L-1-5-->L-1-6: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res#1=|v_ULTIMATE.start_main_#res#1_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res#1] 8543#[L-1-6]don't care [249] L-1-6-->L719: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_1|, ULTIMATE.start_main_#t~nondet4#1=|v_ULTIMATE.start_main_#t~nondet4#1_1|, ULTIMATE.start_main_#t~mem7#1=|v_ULTIMATE.start_main_#t~mem7#1_1|, ULTIMATE.start_main_#t~mem8#1=|v_ULTIMATE.start_main_#t~mem8#1_1|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_1|, ULTIMATE.start_main_#t~nondet6#1=|v_ULTIMATE.start_main_#t~nondet6#1_1|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_1|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_1|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_1|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre5#1, ULTIMATE.start_main_#t~nondet4#1, ULTIMATE.start_main_#t~mem7#1, ULTIMATE.start_main_#t~mem8#1, ULTIMATE.start_main_~#t2~0#1.offset, ULTIMATE.start_main_#t~nondet6#1, ULTIMATE.start_main_~#t1~0#1.base, ULTIMATE.start_main_~#t1~0#1.offset, ULTIMATE.start_main_#t~pre3#1, ULTIMATE.start_main_~#t2~0#1.base] 8545#[L719]don't care [194] L719-->L719-1: Formula: (and (= |v_ULTIMATE.start_main_~#t1~0#1.offset_2| 0) (= (select |v_#valid_5| |v_ULTIMATE.start_main_~#t1~0#1.base_2|) 0) (< |v_#StackHeapBarrier_2| |v_ULTIMATE.start_main_~#t1~0#1.base_2|) (= |v_#length_3| (store |v_#length_4| |v_ULTIMATE.start_main_~#t1~0#1.base_2| 4)) (not (= |v_ULTIMATE.start_main_~#t1~0#1.base_2| 0)) (= (store |v_#valid_5| |v_ULTIMATE.start_main_~#t1~0#1.base_2| 1) |v_#valid_4|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_4|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_2|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_2|, #valid=|v_#valid_4|} AuxVars[] AssignedVars[#valid, #length, ULTIMATE.start_main_~#t1~0#1.base, ULTIMATE.start_main_~#t1~0#1.offset] 8745#[L719-1]don't care [262] L719-1-->L719-2: Formula: (and (= |v_#length_5| (store |v_#length_6| |v_ULTIMATE.start_main_~#t2~0#1.base_2| 4)) (= (select |v_#valid_7| |v_ULTIMATE.start_main_~#t2~0#1.base_2|) 0) (= (store |v_#valid_7| |v_ULTIMATE.start_main_~#t2~0#1.base_2| 1) |v_#valid_6|) (not (= |v_ULTIMATE.start_main_~#t2~0#1.base_2| 0)) (= 0 |v_ULTIMATE.start_main_~#t2~0#1.offset_2|) (< |v_#StackHeapBarrier_3| |v_ULTIMATE.start_main_~#t2~0#1.base_2|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_3|, #length=|v_#length_6|, #valid=|v_#valid_7|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_3|, #length=|v_#length_5|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_2|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_2|, #valid=|v_#valid_6|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2~0#1.offset, #valid, #length, ULTIMATE.start_main_~#t2~0#1.base] 8707#[L719-2]don't care [231] L719-2-->L720: Formula: (= |v_ULTIMATE.start_main_#t~pre3#1_2| |v_#pthreadsForks_1|) InVars {#pthreadsForks=|v_#pthreadsForks_1|} OutVars{#pthreadsForks=|v_#pthreadsForks_1|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre3#1] 8709#[L720]don't care [236] L720-->L720-1: Formula: (= (+ 1 |v_#pthreadsForks_3|) |v_#pthreadsForks_2|) InVars {#pthreadsForks=|v_#pthreadsForks_3|} OutVars{#pthreadsForks=|v_#pthreadsForks_2|} AuxVars[] AssignedVars[#pthreadsForks] 9293#[L720-1]don't care [250] L720-1-->L720-2: Formula: (and (<= 0 |v_ULTIMATE.start_main_~#t1~0#1.offset_3|) (= (select |v_#valid_8| |v_ULTIMATE.start_main_~#t1~0#1.base_3|) 1) (<= (+ |v_ULTIMATE.start_main_~#t1~0#1.offset_3| 4) (select |v_#length_7| |v_ULTIMATE.start_main_~#t1~0#1.base_3|)) (= (store |v_#memory_int_4| |v_ULTIMATE.start_main_~#t1~0#1.base_3| (store (select |v_#memory_int_4| |v_ULTIMATE.start_main_~#t1~0#1.base_3|) |v_ULTIMATE.start_main_~#t1~0#1.offset_3| |v_ULTIMATE.start_main_#t~pre3#1_3|)) |v_#memory_int_3|)) InVars {#valid=|v_#valid_8|, #memory_int=|v_#memory_int_4|, #length=|v_#length_7|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_3|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_3|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_3|} OutVars{#valid=|v_#valid_8|, #memory_int=|v_#memory_int_3|, #length=|v_#length_7|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_3|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_3|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_3|} AuxVars[] AssignedVars[#memory_int] 9295#[L720-2]don't care [340] L720-2-->thr1ENTRY: Formula: (and (= 0 |v_thr1Thread1of1ForFork0_#in~_.base_4|) (= |v_thr1Thread1of1ForFork0_#in~_.offset_4| 0) (= v_thr1Thread1of1ForFork0_thidvar1_2 0) (= |v_ULTIMATE.start_main_#t~pre3#1_6| v_thr1Thread1of1ForFork0_thidvar0_2)) InVars {ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_6|} OutVars{thr1Thread1of1ForFork0_~_.base=v_thr1Thread1of1ForFork0_~_.base_4, thr1Thread1of1ForFork0_#in~_.offset=|v_thr1Thread1of1ForFork0_#in~_.offset_4|, thr1Thread1of1ForFork0_#res.base=|v_thr1Thread1of1ForFork0_#res.base_4|, thr1Thread1of1ForFork0_thidvar0=v_thr1Thread1of1ForFork0_thidvar0_2, thr1Thread1of1ForFork0_thidvar1=v_thr1Thread1of1ForFork0_thidvar1_2, thr1Thread1of1ForFork0_#in~_.base=|v_thr1Thread1of1ForFork0_#in~_.base_4|, thr1Thread1of1ForFork0_#res.offset=|v_thr1Thread1of1ForFork0_#res.offset_4|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_6|, thr1Thread1of1ForFork0_~_.offset=v_thr1Thread1of1ForFork0_~_.offset_4} AuxVars[] AssignedVars[thr1Thread1of1ForFork0_~_.base, thr1Thread1of1ForFork0_#in~_.offset, thr1Thread1of1ForFork0_#res.base, thr1Thread1of1ForFork0_thidvar0, thr1Thread1of1ForFork0_thidvar1, thr1Thread1of1ForFork0_#in~_.base, thr1Thread1of1ForFork0_#res.offset, thr1Thread1of1ForFork0_~_.offset] 8909#[thr1ENTRY, L720-3]don't care [311] thr1ENTRY-->L687: Formula: (and (= v_thr1Thread1of1ForFork0_~_.base_1 |v_thr1Thread1of1ForFork0_#in~_.base_1|) (= |v_thr1Thread1of1ForFork0_#in~_.offset_1| v_thr1Thread1of1ForFork0_~_.offset_1)) InVars {thr1Thread1of1ForFork0_#in~_.base=|v_thr1Thread1of1ForFork0_#in~_.base_1|, thr1Thread1of1ForFork0_#in~_.offset=|v_thr1Thread1of1ForFork0_#in~_.offset_1|} OutVars{thr1Thread1of1ForFork0_~_.base=v_thr1Thread1of1ForFork0_~_.base_1, thr1Thread1of1ForFork0_#in~_.offset=|v_thr1Thread1of1ForFork0_#in~_.offset_1|, thr1Thread1of1ForFork0_#in~_.base=|v_thr1Thread1of1ForFork0_#in~_.base_1|, thr1Thread1of1ForFork0_~_.offset=v_thr1Thread1of1ForFork0_~_.offset_1} AuxVars[] AssignedVars[thr1Thread1of1ForFork0_~_.base, thr1Thread1of1ForFork0_~_.offset] 8911#[L687, L720-3]don't care [312] L687-->L688-2: Formula: (= v_~flag1~0_11 1) InVars {} OutVars{~flag1~0=v_~flag1~0_11} AuxVars[] AssignedVars[~flag1~0] 8669#[L688-2, L720-3]don't care [205] L720-3-->L720-4: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre3#1] 8673#[L720-4, L688-2]don't care [261] L720-4-->L721: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet4#1=|v_ULTIMATE.start_main_#t~nondet4#1_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet4#1] 8325#[L688-2, L721]don't care [218] L721-->L721-1: Formula: (= |v_ULTIMATE.start_main_#t~pre5#1_2| |v_#pthreadsForks_4|) InVars {#pthreadsForks=|v_#pthreadsForks_4|} OutVars{ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_2|, #pthreadsForks=|v_#pthreadsForks_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre5#1] 9265#[L721-1, L688-2]don't care [270] L721-1-->L721-2: Formula: (= (+ 1 |v_#pthreadsForks_6|) |v_#pthreadsForks_5|) InVars {#pthreadsForks=|v_#pthreadsForks_6|} OutVars{#pthreadsForks=|v_#pthreadsForks_5|} AuxVars[] AssignedVars[#pthreadsForks] 8025#[L721-2, L688-2]don't care [197] L721-2-->L721-3: Formula: (and (<= (+ 4 |v_ULTIMATE.start_main_~#t2~0#1.offset_3|) (select |v_#length_8| |v_ULTIMATE.start_main_~#t2~0#1.base_3|)) (= (select |v_#valid_9| |v_ULTIMATE.start_main_~#t2~0#1.base_3|) 1) (= (store |v_#memory_int_6| |v_ULTIMATE.start_main_~#t2~0#1.base_3| (store (select |v_#memory_int_6| |v_ULTIMATE.start_main_~#t2~0#1.base_3|) |v_ULTIMATE.start_main_~#t2~0#1.offset_3| |v_ULTIMATE.start_main_#t~pre5#1_3|)) |v_#memory_int_5|) (<= 0 |v_ULTIMATE.start_main_~#t2~0#1.offset_3|)) InVars {ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_3|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_3|, #valid=|v_#valid_9|, #memory_int=|v_#memory_int_6|, #length=|v_#length_8|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_3|} OutVars{ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_3|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_3|, #valid=|v_#valid_9|, #memory_int=|v_#memory_int_5|, #length=|v_#length_8|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_3|} AuxVars[] AssignedVars[#memory_int] 8105#[L688-2, L721-3]don't care [343] L721-3-->thr2ENTRY: Formula: (and (= v_thr2Thread1of1ForFork1_thidvar2_2 0) (= |v_thr2Thread1of1ForFork1_#in~_.base_4| 0) (= |v_thr2Thread1of1ForFork1_#in~_.offset_4| 0) (= v_thr2Thread1of1ForFork1_thidvar1_2 0) (= |v_ULTIMATE.start_main_#t~pre5#1_6| v_thr2Thread1of1ForFork1_thidvar0_2)) InVars {ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_6|} OutVars{ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_6|, thr2Thread1of1ForFork1_thidvar0=v_thr2Thread1of1ForFork1_thidvar0_2, thr2Thread1of1ForFork1_thidvar1=v_thr2Thread1of1ForFork1_thidvar1_2, thr2Thread1of1ForFork1_thidvar2=v_thr2Thread1of1ForFork1_thidvar2_2, thr2Thread1of1ForFork1_~_.offset=v_thr2Thread1of1ForFork1_~_.offset_4, thr2Thread1of1ForFork1_#res.base=|v_thr2Thread1of1ForFork1_#res.base_4|, thr2Thread1of1ForFork1_#in~_.offset=|v_thr2Thread1of1ForFork1_#in~_.offset_4|, thr2Thread1of1ForFork1_#res.offset=|v_thr2Thread1of1ForFork1_#res.offset_4|, thr2Thread1of1ForFork1_#in~_.base=|v_thr2Thread1of1ForFork1_#in~_.base_4|, thr2Thread1of1ForFork1_~_.base=v_thr2Thread1of1ForFork1_~_.base_4} AuxVars[] AssignedVars[thr2Thread1of1ForFork1_thidvar0, thr2Thread1of1ForFork1_thidvar1, thr2Thread1of1ForFork1_thidvar2, thr2Thread1of1ForFork1_~_.offset, thr2Thread1of1ForFork1_#res.base, thr2Thread1of1ForFork1_#in~_.offset, thr2Thread1of1ForFork1_#res.offset, thr2Thread1of1ForFork1_#in~_.base, thr2Thread1of1ForFork1_~_.base] 8107#[L688-2, L721-4, thr2ENTRY]don't care [284] thr2ENTRY-->L703: Formula: (and (= v_thr2Thread1of1ForFork1_~_.offset_1 |v_thr2Thread1of1ForFork1_#in~_.offset_1|) (= |v_thr2Thread1of1ForFork1_#in~_.base_1| v_thr2Thread1of1ForFork1_~_.base_1)) InVars {thr2Thread1of1ForFork1_#in~_.base=|v_thr2Thread1of1ForFork1_#in~_.base_1|, thr2Thread1of1ForFork1_#in~_.offset=|v_thr2Thread1of1ForFork1_#in~_.offset_1|} OutVars{thr2Thread1of1ForFork1_~_.offset=v_thr2Thread1of1ForFork1_~_.offset_1, thr2Thread1of1ForFork1_#in~_.base=|v_thr2Thread1of1ForFork1_#in~_.base_1|, thr2Thread1of1ForFork1_#in~_.offset=|v_thr2Thread1of1ForFork1_#in~_.offset_1|, thr2Thread1of1ForFork1_~_.base=v_thr2Thread1of1ForFork1_~_.base_1} AuxVars[] AssignedVars[thr2Thread1of1ForFork1_~_.offset, thr2Thread1of1ForFork1_~_.base] 8007#[L688-2, L721-4, L703]don't care [285] L703-->L704-2: Formula: (= v_~flag2~0_1 1) InVars {} OutVars{~flag2~0=v_~flag2~0_1} AuxVars[] AssignedVars[~flag2~0] 8013#[L688-2, L721-4, L704-2]don't care [2022-07-26 13:22:19,822 INFO L735 eck$LassoCheckResult]: Loop: 8013#[L688-2, L721-4, L704-2]don't care [288] L704-2-->L704-2: Formula: (<= 3 v_~flag1~0_3) InVars {~flag1~0=v_~flag1~0_3} OutVars{~flag1~0=v_~flag1~0_3} AuxVars[] AssignedVars[] 8013#[L688-2, L721-4, L704-2]don't care [2022-07-26 13:22:19,822 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:19,822 INFO L85 PathProgramCache]: Analyzing trace with hash -1256256641, now seen corresponding path program 1 times [2022-07-26 13:22:19,822 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:19,823 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1891328667] [2022-07-26 13:22:19,823 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:19,823 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:19,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:19,852 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-26 13:22:19,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:19,879 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-26 13:22:19,880 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:19,880 INFO L85 PathProgramCache]: Analyzing trace with hash 319, now seen corresponding path program 2 times [2022-07-26 13:22:19,880 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:19,880 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [240522267] [2022-07-26 13:22:19,880 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:19,880 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:19,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:19,883 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-26 13:22:19,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:19,885 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-26 13:22:19,885 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:19,885 INFO L85 PathProgramCache]: Analyzing trace with hash -289249919, now seen corresponding path program 1 times [2022-07-26 13:22:19,886 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:19,886 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1323317060] [2022-07-26 13:22:19,886 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:19,886 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:19,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-26 13:22:19,928 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-26 13:22:19,928 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-26 13:22:19,928 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1323317060] [2022-07-26 13:22:19,928 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1323317060] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-26 13:22:19,928 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-26 13:22:19,929 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-26 13:22:19,929 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1694452102] [2022-07-26 13:22:19,929 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-26 13:22:19,934 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-26 13:22:19,934 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-26 13:22:19,934 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-26 13:22:19,934 INFO L87 Difference]: Start difference. First operand 883 states and 2695 transitions. cyclomatic complexity: 2159 Second operand has 3 states, 2 states have (on average 16.0) internal successors, (32), 3 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-26 13:22:19,993 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-26 13:22:19,993 INFO L93 Difference]: Finished difference Result 963 states and 2907 transitions. [2022-07-26 13:22:19,993 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 963 states and 2907 transitions. [2022-07-26 13:22:20,000 INFO L131 ngComponentsAnalysis]: Automaton has 387 accepting balls. 387 [2022-07-26 13:22:20,007 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 963 states to 963 states and 2907 transitions. [2022-07-26 13:22:20,007 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 963 [2022-07-26 13:22:20,008 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 963 [2022-07-26 13:22:20,008 INFO L73 IsDeterministic]: Start isDeterministic. Operand 963 states and 2907 transitions. [2022-07-26 13:22:20,009 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-26 13:22:20,010 INFO L220 hiAutomatonCegarLoop]: Abstraction has 963 states and 2907 transitions. [2022-07-26 13:22:20,012 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 963 states and 2907 transitions. [2022-07-26 13:22:20,022 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 963 to 963. [2022-07-26 13:22:20,024 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 963 states, 963 states have (on average 3.0186915887850465) internal successors, (2907), 962 states have internal predecessors, (2907), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-26 13:22:20,026 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 963 states to 963 states and 2907 transitions. [2022-07-26 13:22:20,027 INFO L242 hiAutomatonCegarLoop]: Abstraction has 963 states and 2907 transitions. [2022-07-26 13:22:20,027 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-26 13:22:20,028 INFO L426 stractBuchiCegarLoop]: Abstraction has 963 states and 2907 transitions. [2022-07-26 13:22:20,028 INFO L333 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-07-26 13:22:20,029 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 963 states and 2907 transitions. [2022-07-26 13:22:20,043 INFO L131 ngComponentsAnalysis]: Automaton has 387 accepting balls. 387 [2022-07-26 13:22:20,047 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-26 13:22:20,047 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-26 13:22:20,049 INFO L150 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-26 13:22:20,049 INFO L151 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-07-26 13:22:20,053 INFO L733 eck$LassoCheckResult]: Stem: 11886#[ULTIMATE.startENTRY]don't care [266] ULTIMATE.startENTRY-->L-1: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 11888#[L-1]don't care [245] L-1-->L-1-1: Formula: (and (= |v_#NULL.base_1| 0) (= |v_#NULL.offset_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] 11896#[L-1-1]don't care [272] L-1-1-->L-1-2: Formula: (= (select |v_#valid_1| 0) 0) InVars {#valid=|v_#valid_1|} OutVars{#valid=|v_#valid_1|} AuxVars[] AssignedVars[] 11898#[L-1-2]don't care [274] L-1-2-->L12: Formula: (< 0 |v_#StackHeapBarrier_1|) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|} AuxVars[] AssignedVars[] 11562#[L12]don't care [220] L12-->L12-1: Formula: (and (= (select |v_#valid_2| 1) 1) (= 2 (select |v_#length_1| 1))) InVars {#length=|v_#length_1|, #valid=|v_#valid_2|} OutVars{#length=|v_#length_1|, #valid=|v_#valid_2|} AuxVars[] AssignedVars[] 11564#[L12-1]don't care [239] L12-1-->L12-2: Formula: (= 48 (select (select |v_#memory_int_1| 1) 0)) InVars {#memory_int=|v_#memory_int_1|} OutVars{#memory_int=|v_#memory_int_1|} AuxVars[] AssignedVars[] 11612#[L12-2]don't care [237] L12-2-->L12-3: Formula: (= (select (select |v_#memory_int_2| 1) 1) 0) InVars {#memory_int=|v_#memory_int_2|} OutVars{#memory_int=|v_#memory_int_2|} AuxVars[] AssignedVars[] 10846#[L12-3]don't care [268] L12-3-->L12-4: Formula: (and (= 12 (select |v_#length_2| 2)) (= (select |v_#valid_3| 2) 1)) InVars {#length=|v_#length_2|, #valid=|v_#valid_3|} OutVars{#length=|v_#length_2|, #valid=|v_#valid_3|} AuxVars[] AssignedVars[] 10848#[L12-4]don't care [253] L12-4-->L684: Formula: (= v_~flag1~0_16 0) InVars {} OutVars{~flag1~0=v_~flag1~0_16} AuxVars[] AssignedVars[~flag1~0] 11638#[L684]don't care [195] L684-->L685: Formula: (= v_~flag2~0_16 0) InVars {} OutVars{~flag2~0=v_~flag2~0_16} AuxVars[] AssignedVars[~flag2~0] 12110#[L685]don't care [219] L685-->L-1-3: Formula: (= v_~x~0_7 0) InVars {} OutVars{~x~0=v_~x~0_7} AuxVars[] AssignedVars[~x~0] 12096#[L-1-3]don't care [276] L-1-3-->L-1-4: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 10550#[L-1-4]don't care [251] L-1-4-->L-1-5: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 10552#[L-1-5]don't care [217] L-1-5-->L-1-6: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res#1=|v_ULTIMATE.start_main_#res#1_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res#1] 11276#[L-1-6]don't care [249] L-1-6-->L719: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_1|, ULTIMATE.start_main_#t~nondet4#1=|v_ULTIMATE.start_main_#t~nondet4#1_1|, ULTIMATE.start_main_#t~mem7#1=|v_ULTIMATE.start_main_#t~mem7#1_1|, ULTIMATE.start_main_#t~mem8#1=|v_ULTIMATE.start_main_#t~mem8#1_1|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_1|, ULTIMATE.start_main_#t~nondet6#1=|v_ULTIMATE.start_main_#t~nondet6#1_1|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_1|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_1|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_1|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre5#1, ULTIMATE.start_main_#t~nondet4#1, ULTIMATE.start_main_#t~mem7#1, ULTIMATE.start_main_#t~mem8#1, ULTIMATE.start_main_~#t2~0#1.offset, ULTIMATE.start_main_#t~nondet6#1, ULTIMATE.start_main_~#t1~0#1.base, ULTIMATE.start_main_~#t1~0#1.offset, ULTIMATE.start_main_#t~pre3#1, ULTIMATE.start_main_~#t2~0#1.base] 11278#[L719]don't care [194] L719-->L719-1: Formula: (and (= |v_ULTIMATE.start_main_~#t1~0#1.offset_2| 0) (= (select |v_#valid_5| |v_ULTIMATE.start_main_~#t1~0#1.base_2|) 0) (< |v_#StackHeapBarrier_2| |v_ULTIMATE.start_main_~#t1~0#1.base_2|) (= |v_#length_3| (store |v_#length_4| |v_ULTIMATE.start_main_~#t1~0#1.base_2| 4)) (not (= |v_ULTIMATE.start_main_~#t1~0#1.base_2| 0)) (= (store |v_#valid_5| |v_ULTIMATE.start_main_~#t1~0#1.base_2| 1) |v_#valid_4|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_4|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_2|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_2|, #valid=|v_#valid_4|} AuxVars[] AssignedVars[#valid, #length, ULTIMATE.start_main_~#t1~0#1.base, ULTIMATE.start_main_~#t1~0#1.offset] 11474#[L719-1]don't care [262] L719-1-->L719-2: Formula: (and (= |v_#length_5| (store |v_#length_6| |v_ULTIMATE.start_main_~#t2~0#1.base_2| 4)) (= (select |v_#valid_7| |v_ULTIMATE.start_main_~#t2~0#1.base_2|) 0) (= (store |v_#valid_7| |v_ULTIMATE.start_main_~#t2~0#1.base_2| 1) |v_#valid_6|) (not (= |v_ULTIMATE.start_main_~#t2~0#1.base_2| 0)) (= 0 |v_ULTIMATE.start_main_~#t2~0#1.offset_2|) (< |v_#StackHeapBarrier_3| |v_ULTIMATE.start_main_~#t2~0#1.base_2|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_3|, #length=|v_#length_6|, #valid=|v_#valid_7|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_3|, #length=|v_#length_5|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_2|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_2|, #valid=|v_#valid_6|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2~0#1.offset, #valid, #length, ULTIMATE.start_main_~#t2~0#1.base] 11436#[L719-2]don't care [231] L719-2-->L720: Formula: (= |v_ULTIMATE.start_main_#t~pre3#1_2| |v_#pthreadsForks_1|) InVars {#pthreadsForks=|v_#pthreadsForks_1|} OutVars{#pthreadsForks=|v_#pthreadsForks_1|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre3#1] 11438#[L720]don't care [236] L720-->L720-1: Formula: (= (+ 1 |v_#pthreadsForks_3|) |v_#pthreadsForks_2|) InVars {#pthreadsForks=|v_#pthreadsForks_3|} OutVars{#pthreadsForks=|v_#pthreadsForks_2|} AuxVars[] AssignedVars[#pthreadsForks] 12062#[L720-1]don't care [250] L720-1-->L720-2: Formula: (and (<= 0 |v_ULTIMATE.start_main_~#t1~0#1.offset_3|) (= (select |v_#valid_8| |v_ULTIMATE.start_main_~#t1~0#1.base_3|) 1) (<= (+ |v_ULTIMATE.start_main_~#t1~0#1.offset_3| 4) (select |v_#length_7| |v_ULTIMATE.start_main_~#t1~0#1.base_3|)) (= (store |v_#memory_int_4| |v_ULTIMATE.start_main_~#t1~0#1.base_3| (store (select |v_#memory_int_4| |v_ULTIMATE.start_main_~#t1~0#1.base_3|) |v_ULTIMATE.start_main_~#t1~0#1.offset_3| |v_ULTIMATE.start_main_#t~pre3#1_3|)) |v_#memory_int_3|)) InVars {#valid=|v_#valid_8|, #memory_int=|v_#memory_int_4|, #length=|v_#length_7|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_3|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_3|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_3|} OutVars{#valid=|v_#valid_8|, #memory_int=|v_#memory_int_3|, #length=|v_#length_7|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_3|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_3|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_3|} AuxVars[] AssignedVars[#memory_int] 12064#[L720-2]don't care [340] L720-2-->thr1ENTRY: Formula: (and (= 0 |v_thr1Thread1of1ForFork0_#in~_.base_4|) (= |v_thr1Thread1of1ForFork0_#in~_.offset_4| 0) (= v_thr1Thread1of1ForFork0_thidvar1_2 0) (= |v_ULTIMATE.start_main_#t~pre3#1_6| v_thr1Thread1of1ForFork0_thidvar0_2)) InVars {ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_6|} OutVars{thr1Thread1of1ForFork0_~_.base=v_thr1Thread1of1ForFork0_~_.base_4, thr1Thread1of1ForFork0_#in~_.offset=|v_thr1Thread1of1ForFork0_#in~_.offset_4|, thr1Thread1of1ForFork0_#res.base=|v_thr1Thread1of1ForFork0_#res.base_4|, thr1Thread1of1ForFork0_thidvar0=v_thr1Thread1of1ForFork0_thidvar0_2, thr1Thread1of1ForFork0_thidvar1=v_thr1Thread1of1ForFork0_thidvar1_2, thr1Thread1of1ForFork0_#in~_.base=|v_thr1Thread1of1ForFork0_#in~_.base_4|, thr1Thread1of1ForFork0_#res.offset=|v_thr1Thread1of1ForFork0_#res.offset_4|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_6|, thr1Thread1of1ForFork0_~_.offset=v_thr1Thread1of1ForFork0_~_.offset_4} AuxVars[] AssignedVars[thr1Thread1of1ForFork0_~_.base, thr1Thread1of1ForFork0_#in~_.offset, thr1Thread1of1ForFork0_#res.base, thr1Thread1of1ForFork0_thidvar0, thr1Thread1of1ForFork0_thidvar1, thr1Thread1of1ForFork0_#in~_.base, thr1Thread1of1ForFork0_#res.offset, thr1Thread1of1ForFork0_~_.offset] 11640#[thr1ENTRY, L720-3]don't care [311] thr1ENTRY-->L687: Formula: (and (= v_thr1Thread1of1ForFork0_~_.base_1 |v_thr1Thread1of1ForFork0_#in~_.base_1|) (= |v_thr1Thread1of1ForFork0_#in~_.offset_1| v_thr1Thread1of1ForFork0_~_.offset_1)) InVars {thr1Thread1of1ForFork0_#in~_.base=|v_thr1Thread1of1ForFork0_#in~_.base_1|, thr1Thread1of1ForFork0_#in~_.offset=|v_thr1Thread1of1ForFork0_#in~_.offset_1|} OutVars{thr1Thread1of1ForFork0_~_.base=v_thr1Thread1of1ForFork0_~_.base_1, thr1Thread1of1ForFork0_#in~_.offset=|v_thr1Thread1of1ForFork0_#in~_.offset_1|, thr1Thread1of1ForFork0_#in~_.base=|v_thr1Thread1of1ForFork0_#in~_.base_1|, thr1Thread1of1ForFork0_~_.offset=v_thr1Thread1of1ForFork0_~_.offset_1} AuxVars[] AssignedVars[thr1Thread1of1ForFork0_~_.base, thr1Thread1of1ForFork0_~_.offset] 11642#[L687, L720-3]don't care [312] L687-->L688-2: Formula: (= v_~flag1~0_11 1) InVars {} OutVars{~flag1~0=v_~flag1~0_11} AuxVars[] AssignedVars[~flag1~0] 11400#[L688-2, L720-3]don't care [205] L720-3-->L720-4: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre3#1] 11404#[L720-4, L688-2]don't care [261] L720-4-->L721: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet4#1=|v_ULTIMATE.start_main_#t~nondet4#1_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet4#1] 11058#[L688-2, L721]don't care [218] L721-->L721-1: Formula: (= |v_ULTIMATE.start_main_#t~pre5#1_2| |v_#pthreadsForks_4|) InVars {#pthreadsForks=|v_#pthreadsForks_4|} OutVars{ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_2|, #pthreadsForks=|v_#pthreadsForks_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre5#1] 12030#[L721-1, L688-2]don't care [270] L721-1-->L721-2: Formula: (= (+ 1 |v_#pthreadsForks_6|) |v_#pthreadsForks_5|) InVars {#pthreadsForks=|v_#pthreadsForks_6|} OutVars{#pthreadsForks=|v_#pthreadsForks_5|} AuxVars[] AssignedVars[#pthreadsForks] 10760#[L721-2, L688-2]don't care [197] L721-2-->L721-3: Formula: (and (<= (+ 4 |v_ULTIMATE.start_main_~#t2~0#1.offset_3|) (select |v_#length_8| |v_ULTIMATE.start_main_~#t2~0#1.base_3|)) (= (select |v_#valid_9| |v_ULTIMATE.start_main_~#t2~0#1.base_3|) 1) (= (store |v_#memory_int_6| |v_ULTIMATE.start_main_~#t2~0#1.base_3| (store (select |v_#memory_int_6| |v_ULTIMATE.start_main_~#t2~0#1.base_3|) |v_ULTIMATE.start_main_~#t2~0#1.offset_3| |v_ULTIMATE.start_main_#t~pre5#1_3|)) |v_#memory_int_5|) (<= 0 |v_ULTIMATE.start_main_~#t2~0#1.offset_3|)) InVars {ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_3|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_3|, #valid=|v_#valid_9|, #memory_int=|v_#memory_int_6|, #length=|v_#length_8|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_3|} OutVars{ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_3|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_3|, #valid=|v_#valid_9|, #memory_int=|v_#memory_int_5|, #length=|v_#length_8|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_3|} AuxVars[] AssignedVars[#memory_int] 10840#[L688-2, L721-3]don't care [343] L721-3-->thr2ENTRY: Formula: (and (= v_thr2Thread1of1ForFork1_thidvar2_2 0) (= |v_thr2Thread1of1ForFork1_#in~_.base_4| 0) (= |v_thr2Thread1of1ForFork1_#in~_.offset_4| 0) (= v_thr2Thread1of1ForFork1_thidvar1_2 0) (= |v_ULTIMATE.start_main_#t~pre5#1_6| v_thr2Thread1of1ForFork1_thidvar0_2)) InVars {ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_6|} OutVars{ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_6|, thr2Thread1of1ForFork1_thidvar0=v_thr2Thread1of1ForFork1_thidvar0_2, thr2Thread1of1ForFork1_thidvar1=v_thr2Thread1of1ForFork1_thidvar1_2, thr2Thread1of1ForFork1_thidvar2=v_thr2Thread1of1ForFork1_thidvar2_2, thr2Thread1of1ForFork1_~_.offset=v_thr2Thread1of1ForFork1_~_.offset_4, thr2Thread1of1ForFork1_#res.base=|v_thr2Thread1of1ForFork1_#res.base_4|, thr2Thread1of1ForFork1_#in~_.offset=|v_thr2Thread1of1ForFork1_#in~_.offset_4|, thr2Thread1of1ForFork1_#res.offset=|v_thr2Thread1of1ForFork1_#res.offset_4|, thr2Thread1of1ForFork1_#in~_.base=|v_thr2Thread1of1ForFork1_#in~_.base_4|, thr2Thread1of1ForFork1_~_.base=v_thr2Thread1of1ForFork1_~_.base_4} AuxVars[] AssignedVars[thr2Thread1of1ForFork1_thidvar0, thr2Thread1of1ForFork1_thidvar1, thr2Thread1of1ForFork1_thidvar2, thr2Thread1of1ForFork1_~_.offset, thr2Thread1of1ForFork1_#res.base, thr2Thread1of1ForFork1_#in~_.offset, thr2Thread1of1ForFork1_#res.offset, thr2Thread1of1ForFork1_#in~_.base, thr2Thread1of1ForFork1_~_.base] 10842#[L688-2, L721-4, thr2ENTRY]don't care [284] thr2ENTRY-->L703: Formula: (and (= v_thr2Thread1of1ForFork1_~_.offset_1 |v_thr2Thread1of1ForFork1_#in~_.offset_1|) (= |v_thr2Thread1of1ForFork1_#in~_.base_1| v_thr2Thread1of1ForFork1_~_.base_1)) InVars {thr2Thread1of1ForFork1_#in~_.base=|v_thr2Thread1of1ForFork1_#in~_.base_1|, thr2Thread1of1ForFork1_#in~_.offset=|v_thr2Thread1of1ForFork1_#in~_.offset_1|} OutVars{thr2Thread1of1ForFork1_~_.offset=v_thr2Thread1of1ForFork1_~_.offset_1, thr2Thread1of1ForFork1_#in~_.base=|v_thr2Thread1of1ForFork1_#in~_.base_1|, thr2Thread1of1ForFork1_#in~_.offset=|v_thr2Thread1of1ForFork1_#in~_.offset_1|, thr2Thread1of1ForFork1_~_.base=v_thr2Thread1of1ForFork1_~_.base_1} AuxVars[] AssignedVars[thr2Thread1of1ForFork1_~_.offset, thr2Thread1of1ForFork1_~_.base] 10742#[L688-2, L721-4, L703]don't care [285] L703-->L704-2: Formula: (= v_~flag2~0_1 1) InVars {} OutVars{~flag2~0=v_~flag2~0_1} AuxVars[] AssignedVars[~flag2~0] 10748#[L688-2, L721-4, L704-2]don't care [2022-07-26 13:22:20,053 INFO L735 eck$LassoCheckResult]: Loop: 10748#[L688-2, L721-4, L704-2]don't care [315] L688-2-->L688-2: Formula: (<= 3 v_~flag2~0_9) InVars {~flag2~0=v_~flag2~0_9} OutVars{~flag2~0=v_~flag2~0_9} AuxVars[] AssignedVars[] 10748#[L688-2, L721-4, L704-2]don't care [2022-07-26 13:22:20,053 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:20,053 INFO L85 PathProgramCache]: Analyzing trace with hash -1256256641, now seen corresponding path program 2 times [2022-07-26 13:22:20,053 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:20,054 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1487999417] [2022-07-26 13:22:20,054 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:20,054 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:20,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:20,073 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-26 13:22:20,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:20,096 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-26 13:22:20,097 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:20,097 INFO L85 PathProgramCache]: Analyzing trace with hash 346, now seen corresponding path program 2 times [2022-07-26 13:22:20,097 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:20,097 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1346071360] [2022-07-26 13:22:20,097 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:20,097 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:20,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:20,100 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-26 13:22:20,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:20,101 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-26 13:22:20,101 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:20,102 INFO L85 PathProgramCache]: Analyzing trace with hash -289249892, now seen corresponding path program 1 times [2022-07-26 13:22:20,102 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:20,102 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1610725760] [2022-07-26 13:22:20,102 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:20,102 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:20,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-07-26 13:22:20,129 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-07-26 13:22:20,129 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-07-26 13:22:20,129 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1610725760] [2022-07-26 13:22:20,129 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1610725760] provided 1 perfect and 0 imperfect interpolant sequences [2022-07-26 13:22:20,129 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-07-26 13:22:20,129 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-07-26 13:22:20,130 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1213180307] [2022-07-26 13:22:20,130 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-07-26 13:22:20,133 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-07-26 13:22:20,134 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-07-26 13:22:20,134 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-07-26 13:22:20,134 INFO L87 Difference]: Start difference. First operand 963 states and 2907 transitions. cyclomatic complexity: 2331 Second operand has 3 states, 2 states have (on average 16.0) internal successors, (32), 3 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-26 13:22:20,174 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-07-26 13:22:20,174 INFO L93 Difference]: Finished difference Result 1051 states and 3141 transitions. [2022-07-26 13:22:20,174 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1051 states and 3141 transitions. [2022-07-26 13:22:20,181 INFO L131 ngComponentsAnalysis]: Automaton has 431 accepting balls. 431 [2022-07-26 13:22:20,188 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1051 states to 1051 states and 3141 transitions. [2022-07-26 13:22:20,189 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1051 [2022-07-26 13:22:20,190 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1051 [2022-07-26 13:22:20,190 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1051 states and 3141 transitions. [2022-07-26 13:22:20,192 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-07-26 13:22:20,192 INFO L220 hiAutomatonCegarLoop]: Abstraction has 1051 states and 3141 transitions. [2022-07-26 13:22:20,194 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1051 states and 3141 transitions. [2022-07-26 13:22:20,205 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1051 to 1051. [2022-07-26 13:22:20,207 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1051 states, 1051 states have (on average 2.988582302568982) internal successors, (3141), 1050 states have internal predecessors, (3141), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-07-26 13:22:20,209 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1051 states to 1051 states and 3141 transitions. [2022-07-26 13:22:20,209 INFO L242 hiAutomatonCegarLoop]: Abstraction has 1051 states and 3141 transitions. [2022-07-26 13:22:20,210 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-07-26 13:22:20,211 INFO L426 stractBuchiCegarLoop]: Abstraction has 1051 states and 3141 transitions. [2022-07-26 13:22:20,211 INFO L333 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-07-26 13:22:20,211 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1051 states and 3141 transitions. [2022-07-26 13:22:20,215 INFO L131 ngComponentsAnalysis]: Automaton has 431 accepting balls. 431 [2022-07-26 13:22:20,216 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-07-26 13:22:20,216 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-07-26 13:22:20,217 INFO L150 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-07-26 13:22:20,217 INFO L151 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-07-26 13:22:20,218 INFO L733 eck$LassoCheckResult]: Stem: 14883#[ULTIMATE.startENTRY]don't care [266] ULTIMATE.startENTRY-->L-1: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 14885#[L-1]don't care [245] L-1-->L-1-1: Formula: (and (= |v_#NULL.base_1| 0) (= |v_#NULL.offset_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] 14891#[L-1-1]don't care [272] L-1-1-->L-1-2: Formula: (= (select |v_#valid_1| 0) 0) InVars {#valid=|v_#valid_1|} OutVars{#valid=|v_#valid_1|} AuxVars[] AssignedVars[] 14893#[L-1-2]don't care [274] L-1-2-->L12: Formula: (< 0 |v_#StackHeapBarrier_1|) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|} AuxVars[] AssignedVars[] 14555#[L12]don't care [220] L12-->L12-1: Formula: (and (= (select |v_#valid_2| 1) 1) (= 2 (select |v_#length_1| 1))) InVars {#length=|v_#length_1|, #valid=|v_#valid_2|} OutVars{#length=|v_#length_1|, #valid=|v_#valid_2|} AuxVars[] AssignedVars[] 14557#[L12-1]don't care [239] L12-1-->L12-2: Formula: (= 48 (select (select |v_#memory_int_1| 1) 0)) InVars {#memory_int=|v_#memory_int_1|} OutVars{#memory_int=|v_#memory_int_1|} AuxVars[] AssignedVars[] 14605#[L12-2]don't care [237] L12-2-->L12-3: Formula: (= (select (select |v_#memory_int_2| 1) 1) 0) InVars {#memory_int=|v_#memory_int_2|} OutVars{#memory_int=|v_#memory_int_2|} AuxVars[] AssignedVars[] 13831#[L12-3]don't care [268] L12-3-->L12-4: Formula: (and (= 12 (select |v_#length_2| 2)) (= (select |v_#valid_3| 2) 1)) InVars {#length=|v_#length_2|, #valid=|v_#valid_3|} OutVars{#length=|v_#length_2|, #valid=|v_#valid_3|} AuxVars[] AssignedVars[] 13833#[L12-4]don't care [253] L12-4-->L684: Formula: (= v_~flag1~0_16 0) InVars {} OutVars{~flag1~0=v_~flag1~0_16} AuxVars[] AssignedVars[~flag1~0] 14631#[L684]don't care [195] L684-->L685: Formula: (= v_~flag2~0_16 0) InVars {} OutVars{~flag2~0=v_~flag2~0_16} AuxVars[] AssignedVars[~flag2~0] 15125#[L685]don't care [219] L685-->L-1-3: Formula: (= v_~x~0_7 0) InVars {} OutVars{~x~0=v_~x~0_7} AuxVars[] AssignedVars[~x~0] 15111#[L-1-3]don't care [276] L-1-3-->L-1-4: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 13533#[L-1-4]don't care [251] L-1-4-->L-1-5: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] 13535#[L-1-5]don't care [217] L-1-5-->L-1-6: Formula: true InVars {} OutVars{ULTIMATE.start_main_#res#1=|v_ULTIMATE.start_main_#res#1_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#res#1] 14263#[L-1-6]don't care [249] L-1-6-->L719: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_1|, ULTIMATE.start_main_#t~nondet4#1=|v_ULTIMATE.start_main_#t~nondet4#1_1|, ULTIMATE.start_main_#t~mem7#1=|v_ULTIMATE.start_main_#t~mem7#1_1|, ULTIMATE.start_main_#t~mem8#1=|v_ULTIMATE.start_main_#t~mem8#1_1|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_1|, ULTIMATE.start_main_#t~nondet6#1=|v_ULTIMATE.start_main_#t~nondet6#1_1|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_1|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_1|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_1|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_1|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre5#1, ULTIMATE.start_main_#t~nondet4#1, ULTIMATE.start_main_#t~mem7#1, ULTIMATE.start_main_#t~mem8#1, ULTIMATE.start_main_~#t2~0#1.offset, ULTIMATE.start_main_#t~nondet6#1, ULTIMATE.start_main_~#t1~0#1.base, ULTIMATE.start_main_~#t1~0#1.offset, ULTIMATE.start_main_#t~pre3#1, ULTIMATE.start_main_~#t2~0#1.base] 14265#[L719]don't care [194] L719-->L719-1: Formula: (and (= |v_ULTIMATE.start_main_~#t1~0#1.offset_2| 0) (= (select |v_#valid_5| |v_ULTIMATE.start_main_~#t1~0#1.base_2|) 0) (< |v_#StackHeapBarrier_2| |v_ULTIMATE.start_main_~#t1~0#1.base_2|) (= |v_#length_3| (store |v_#length_4| |v_ULTIMATE.start_main_~#t1~0#1.base_2| 4)) (not (= |v_ULTIMATE.start_main_~#t1~0#1.base_2| 0)) (= (store |v_#valid_5| |v_ULTIMATE.start_main_~#t1~0#1.base_2| 1) |v_#valid_4|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_4|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_2|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_2|, #valid=|v_#valid_4|} AuxVars[] AssignedVars[#valid, #length, ULTIMATE.start_main_~#t1~0#1.base, ULTIMATE.start_main_~#t1~0#1.offset] 14465#[L719-1]don't care [262] L719-1-->L719-2: Formula: (and (= |v_#length_5| (store |v_#length_6| |v_ULTIMATE.start_main_~#t2~0#1.base_2| 4)) (= (select |v_#valid_7| |v_ULTIMATE.start_main_~#t2~0#1.base_2|) 0) (= (store |v_#valid_7| |v_ULTIMATE.start_main_~#t2~0#1.base_2| 1) |v_#valid_6|) (not (= |v_ULTIMATE.start_main_~#t2~0#1.base_2| 0)) (= 0 |v_ULTIMATE.start_main_~#t2~0#1.offset_2|) (< |v_#StackHeapBarrier_3| |v_ULTIMATE.start_main_~#t2~0#1.base_2|)) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_3|, #length=|v_#length_6|, #valid=|v_#valid_7|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_3|, #length=|v_#length_5|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_2|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_2|, #valid=|v_#valid_6|} AuxVars[] AssignedVars[ULTIMATE.start_main_~#t2~0#1.offset, #valid, #length, ULTIMATE.start_main_~#t2~0#1.base] 14429#[L719-2]don't care [231] L719-2-->L720: Formula: (= |v_ULTIMATE.start_main_#t~pre3#1_2| |v_#pthreadsForks_1|) InVars {#pthreadsForks=|v_#pthreadsForks_1|} OutVars{#pthreadsForks=|v_#pthreadsForks_1|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre3#1] 14431#[L720]don't care [236] L720-->L720-1: Formula: (= (+ 1 |v_#pthreadsForks_3|) |v_#pthreadsForks_2|) InVars {#pthreadsForks=|v_#pthreadsForks_3|} OutVars{#pthreadsForks=|v_#pthreadsForks_2|} AuxVars[] AssignedVars[#pthreadsForks] 15073#[L720-1]don't care [250] L720-1-->L720-2: Formula: (and (<= 0 |v_ULTIMATE.start_main_~#t1~0#1.offset_3|) (= (select |v_#valid_8| |v_ULTIMATE.start_main_~#t1~0#1.base_3|) 1) (<= (+ |v_ULTIMATE.start_main_~#t1~0#1.offset_3| 4) (select |v_#length_7| |v_ULTIMATE.start_main_~#t1~0#1.base_3|)) (= (store |v_#memory_int_4| |v_ULTIMATE.start_main_~#t1~0#1.base_3| (store (select |v_#memory_int_4| |v_ULTIMATE.start_main_~#t1~0#1.base_3|) |v_ULTIMATE.start_main_~#t1~0#1.offset_3| |v_ULTIMATE.start_main_#t~pre3#1_3|)) |v_#memory_int_3|)) InVars {#valid=|v_#valid_8|, #memory_int=|v_#memory_int_4|, #length=|v_#length_7|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_3|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_3|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_3|} OutVars{#valid=|v_#valid_8|, #memory_int=|v_#memory_int_3|, #length=|v_#length_7|, ULTIMATE.start_main_~#t1~0#1.base=|v_ULTIMATE.start_main_~#t1~0#1.base_3|, ULTIMATE.start_main_~#t1~0#1.offset=|v_ULTIMATE.start_main_~#t1~0#1.offset_3|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_3|} AuxVars[] AssignedVars[#memory_int] 15075#[L720-2]don't care [340] L720-2-->thr1ENTRY: Formula: (and (= 0 |v_thr1Thread1of1ForFork0_#in~_.base_4|) (= |v_thr1Thread1of1ForFork0_#in~_.offset_4| 0) (= v_thr1Thread1of1ForFork0_thidvar1_2 0) (= |v_ULTIMATE.start_main_#t~pre3#1_6| v_thr1Thread1of1ForFork0_thidvar0_2)) InVars {ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_6|} OutVars{thr1Thread1of1ForFork0_~_.base=v_thr1Thread1of1ForFork0_~_.base_4, thr1Thread1of1ForFork0_#in~_.offset=|v_thr1Thread1of1ForFork0_#in~_.offset_4|, thr1Thread1of1ForFork0_#res.base=|v_thr1Thread1of1ForFork0_#res.base_4|, thr1Thread1of1ForFork0_thidvar0=v_thr1Thread1of1ForFork0_thidvar0_2, thr1Thread1of1ForFork0_thidvar1=v_thr1Thread1of1ForFork0_thidvar1_2, thr1Thread1of1ForFork0_#in~_.base=|v_thr1Thread1of1ForFork0_#in~_.base_4|, thr1Thread1of1ForFork0_#res.offset=|v_thr1Thread1of1ForFork0_#res.offset_4|, ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_6|, thr1Thread1of1ForFork0_~_.offset=v_thr1Thread1of1ForFork0_~_.offset_4} AuxVars[] AssignedVars[thr1Thread1of1ForFork0_~_.base, thr1Thread1of1ForFork0_#in~_.offset, thr1Thread1of1ForFork0_#res.base, thr1Thread1of1ForFork0_thidvar0, thr1Thread1of1ForFork0_thidvar1, thr1Thread1of1ForFork0_#in~_.base, thr1Thread1of1ForFork0_#res.offset, thr1Thread1of1ForFork0_~_.offset] 14635#[thr1ENTRY, L720-3]don't care [311] thr1ENTRY-->L687: Formula: (and (= v_thr1Thread1of1ForFork0_~_.base_1 |v_thr1Thread1of1ForFork0_#in~_.base_1|) (= |v_thr1Thread1of1ForFork0_#in~_.offset_1| v_thr1Thread1of1ForFork0_~_.offset_1)) InVars {thr1Thread1of1ForFork0_#in~_.base=|v_thr1Thread1of1ForFork0_#in~_.base_1|, thr1Thread1of1ForFork0_#in~_.offset=|v_thr1Thread1of1ForFork0_#in~_.offset_1|} OutVars{thr1Thread1of1ForFork0_~_.base=v_thr1Thread1of1ForFork0_~_.base_1, thr1Thread1of1ForFork0_#in~_.offset=|v_thr1Thread1of1ForFork0_#in~_.offset_1|, thr1Thread1of1ForFork0_#in~_.base=|v_thr1Thread1of1ForFork0_#in~_.base_1|, thr1Thread1of1ForFork0_~_.offset=v_thr1Thread1of1ForFork0_~_.offset_1} AuxVars[] AssignedVars[thr1Thread1of1ForFork0_~_.base, thr1Thread1of1ForFork0_~_.offset] 14637#[L687, L720-3]don't care [312] L687-->L688-2: Formula: (= v_~flag1~0_11 1) InVars {} OutVars{~flag1~0=v_~flag1~0_11} AuxVars[] AssignedVars[~flag1~0] 14389#[L688-2, L720-3]don't care [314] L688-2-->L688-3: Formula: (not (<= 3 v_~flag2~0_8)) InVars {~flag2~0=v_~flag2~0_8} OutVars{~flag2~0=v_~flag2~0_8} AuxVars[] AssignedVars[] 14391#[L688-3, L720-3]don't care [316] L688-3-->L690: Formula: (= v_~flag1~0_13 3) InVars {} OutVars{~flag1~0=v_~flag1~0_13} AuxVars[] AssignedVars[~flag1~0] 15129#[L690, L720-3]don't care [205] L720-3-->L720-4: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~pre3#1=|v_ULTIMATE.start_main_#t~pre3#1_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre3#1] 15085#[L720-4, L690]don't care [261] L720-4-->L721: Formula: true InVars {} OutVars{ULTIMATE.start_main_#t~nondet4#1=|v_ULTIMATE.start_main_#t~nondet4#1_2|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~nondet4#1] 14249#[L690, L721]don't care [218] L721-->L721-1: Formula: (= |v_ULTIMATE.start_main_#t~pre5#1_2| |v_#pthreadsForks_4|) InVars {#pthreadsForks=|v_#pthreadsForks_4|} OutVars{ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_2|, #pthreadsForks=|v_#pthreadsForks_4|} AuxVars[] AssignedVars[ULTIMATE.start_main_#t~pre5#1] 14251#[L721-1, L690]don't care [270] L721-1-->L721-2: Formula: (= (+ 1 |v_#pthreadsForks_6|) |v_#pthreadsForks_5|) InVars {#pthreadsForks=|v_#pthreadsForks_6|} OutVars{#pthreadsForks=|v_#pthreadsForks_5|} AuxVars[] AssignedVars[#pthreadsForks] 14327#[L721-2, L690]don't care [197] L721-2-->L721-3: Formula: (and (<= (+ 4 |v_ULTIMATE.start_main_~#t2~0#1.offset_3|) (select |v_#length_8| |v_ULTIMATE.start_main_~#t2~0#1.base_3|)) (= (select |v_#valid_9| |v_ULTIMATE.start_main_~#t2~0#1.base_3|) 1) (= (store |v_#memory_int_6| |v_ULTIMATE.start_main_~#t2~0#1.base_3| (store (select |v_#memory_int_6| |v_ULTIMATE.start_main_~#t2~0#1.base_3|) |v_ULTIMATE.start_main_~#t2~0#1.offset_3| |v_ULTIMATE.start_main_#t~pre5#1_3|)) |v_#memory_int_5|) (<= 0 |v_ULTIMATE.start_main_~#t2~0#1.offset_3|)) InVars {ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_3|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_3|, #valid=|v_#valid_9|, #memory_int=|v_#memory_int_6|, #length=|v_#length_8|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_3|} OutVars{ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_3|, ULTIMATE.start_main_~#t2~0#1.offset=|v_ULTIMATE.start_main_~#t2~0#1.offset_3|, #valid=|v_#valid_9|, #memory_int=|v_#memory_int_5|, #length=|v_#length_8|, ULTIMATE.start_main_~#t2~0#1.base=|v_ULTIMATE.start_main_~#t2~0#1.base_3|} AuxVars[] AssignedVars[#memory_int] 13997#[L690, L721-3]don't care [343] L721-3-->thr2ENTRY: Formula: (and (= v_thr2Thread1of1ForFork1_thidvar2_2 0) (= |v_thr2Thread1of1ForFork1_#in~_.base_4| 0) (= |v_thr2Thread1of1ForFork1_#in~_.offset_4| 0) (= v_thr2Thread1of1ForFork1_thidvar1_2 0) (= |v_ULTIMATE.start_main_#t~pre5#1_6| v_thr2Thread1of1ForFork1_thidvar0_2)) InVars {ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_6|} OutVars{ULTIMATE.start_main_#t~pre5#1=|v_ULTIMATE.start_main_#t~pre5#1_6|, thr2Thread1of1ForFork1_thidvar0=v_thr2Thread1of1ForFork1_thidvar0_2, thr2Thread1of1ForFork1_thidvar1=v_thr2Thread1of1ForFork1_thidvar1_2, thr2Thread1of1ForFork1_thidvar2=v_thr2Thread1of1ForFork1_thidvar2_2, thr2Thread1of1ForFork1_~_.offset=v_thr2Thread1of1ForFork1_~_.offset_4, thr2Thread1of1ForFork1_#res.base=|v_thr2Thread1of1ForFork1_#res.base_4|, thr2Thread1of1ForFork1_#in~_.offset=|v_thr2Thread1of1ForFork1_#in~_.offset_4|, thr2Thread1of1ForFork1_#res.offset=|v_thr2Thread1of1ForFork1_#res.offset_4|, thr2Thread1of1ForFork1_#in~_.base=|v_thr2Thread1of1ForFork1_#in~_.base_4|, thr2Thread1of1ForFork1_~_.base=v_thr2Thread1of1ForFork1_~_.base_4} AuxVars[] AssignedVars[thr2Thread1of1ForFork1_thidvar0, thr2Thread1of1ForFork1_thidvar1, thr2Thread1of1ForFork1_thidvar2, thr2Thread1of1ForFork1_~_.offset, thr2Thread1of1ForFork1_#res.base, thr2Thread1of1ForFork1_#in~_.offset, thr2Thread1of1ForFork1_#res.offset, thr2Thread1of1ForFork1_#in~_.base, thr2Thread1of1ForFork1_~_.base] 14575#[L690, L721-4, thr2ENTRY]don't care [284] thr2ENTRY-->L703: Formula: (and (= v_thr2Thread1of1ForFork1_~_.offset_1 |v_thr2Thread1of1ForFork1_#in~_.offset_1|) (= |v_thr2Thread1of1ForFork1_#in~_.base_1| v_thr2Thread1of1ForFork1_~_.base_1)) InVars {thr2Thread1of1ForFork1_#in~_.base=|v_thr2Thread1of1ForFork1_#in~_.base_1|, thr2Thread1of1ForFork1_#in~_.offset=|v_thr2Thread1of1ForFork1_#in~_.offset_1|} OutVars{thr2Thread1of1ForFork1_~_.offset=v_thr2Thread1of1ForFork1_~_.offset_1, thr2Thread1of1ForFork1_#in~_.base=|v_thr2Thread1of1ForFork1_#in~_.base_1|, thr2Thread1of1ForFork1_#in~_.offset=|v_thr2Thread1of1ForFork1_#in~_.offset_1|, thr2Thread1of1ForFork1_~_.base=v_thr2Thread1of1ForFork1_~_.base_1} AuxVars[] AssignedVars[thr2Thread1of1ForFork1_~_.offset, thr2Thread1of1ForFork1_~_.base] 13931#[L690, L721-4, L703]don't care [285] L703-->L704-2: Formula: (= v_~flag2~0_1 1) InVars {} OutVars{~flag2~0=v_~flag2~0_1} AuxVars[] AssignedVars[~flag2~0] 14855#[L690, L721-4, L704-2]don't care [2022-07-26 13:22:20,218 INFO L735 eck$LassoCheckResult]: Loop: 14855#[L690, L721-4, L704-2]don't care [288] L704-2-->L704-2: Formula: (<= 3 v_~flag1~0_3) InVars {~flag1~0=v_~flag1~0_3} OutVars{~flag1~0=v_~flag1~0_3} AuxVars[] AssignedVars[] 14855#[L690, L721-4, L704-2]don't care [2022-07-26 13:22:20,219 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:20,219 INFO L85 PathProgramCache]: Analyzing trace with hash -995733311, now seen corresponding path program 1 times [2022-07-26 13:22:20,219 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:20,219 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1404112868] [2022-07-26 13:22:20,220 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:20,220 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:20,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:20,232 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-26 13:22:20,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:20,240 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-26 13:22:20,240 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:20,240 INFO L85 PathProgramCache]: Analyzing trace with hash 319, now seen corresponding path program 3 times [2022-07-26 13:22:20,240 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:20,241 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [782604894] [2022-07-26 13:22:20,241 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:20,241 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:20,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:20,243 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-26 13:22:20,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:20,244 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-26 13:22:20,245 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-07-26 13:22:20,245 INFO L85 PathProgramCache]: Analyzing trace with hash -802961281, now seen corresponding path program 1 times [2022-07-26 13:22:20,245 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-07-26 13:22:20,245 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1086590502] [2022-07-26 13:22:20,245 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-07-26 13:22:20,245 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-07-26 13:22:20,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:20,253 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-07-26 13:22:20,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-07-26 13:22:20,262 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-07-26 13:22:20,930 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 26.07 01:22:20 BoogieIcfgContainer [2022-07-26 13:22:20,930 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-07-26 13:22:20,931 INFO L158 Benchmark]: Toolchain (without parser) took 2953.21ms. Allocated memory was 191.9MB in the beginning and 235.9MB in the end (delta: 44.0MB). Free memory was 162.8MB in the beginning and 205.0MB in the end (delta: -42.2MB). Peak memory consumption was 138.1MB. Max. memory is 8.0GB. [2022-07-26 13:22:20,931 INFO L158 Benchmark]: CDTParser took 0.11ms. Allocated memory is still 191.9MB. Free memory is still 151.3MB. There was no memory consumed. Max. memory is 8.0GB. [2022-07-26 13:22:20,931 INFO L158 Benchmark]: CACSL2BoogieTranslator took 321.76ms. Allocated memory is still 191.9MB. Free memory was 162.6MB in the beginning and 156.3MB in the end (delta: 6.3MB). Peak memory consumption was 9.5MB. Max. memory is 8.0GB. [2022-07-26 13:22:20,932 INFO L158 Benchmark]: Boogie Procedure Inliner took 41.92ms. Allocated memory is still 191.9MB. Free memory was 156.3MB in the beginning and 154.3MB in the end (delta: 2.0MB). Peak memory consumption was 2.1MB. Max. memory is 8.0GB. [2022-07-26 13:22:20,932 INFO L158 Benchmark]: Boogie Preprocessor took 24.19ms. Allocated memory is still 191.9MB. Free memory was 154.3MB in the beginning and 153.0MB in the end (delta: 1.3MB). Peak memory consumption was 1.0MB. Max. memory is 8.0GB. [2022-07-26 13:22:20,932 INFO L158 Benchmark]: RCFGBuilder took 265.77ms. Allocated memory is still 191.9MB. Free memory was 152.8MB in the beginning and 139.9MB in the end (delta: 12.9MB). Peak memory consumption was 13.6MB. Max. memory is 8.0GB. [2022-07-26 13:22:20,933 INFO L158 Benchmark]: BuchiAutomizer took 2294.66ms. Allocated memory was 191.9MB in the beginning and 235.9MB in the end (delta: 44.0MB). Free memory was 139.9MB in the beginning and 205.0MB in the end (delta: -65.1MB). Peak memory consumption was 116.0MB. Max. memory is 8.0GB. [2022-07-26 13:22:20,934 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.11ms. Allocated memory is still 191.9MB. Free memory is still 151.3MB. There was no memory consumed. Max. memory is 8.0GB. * CACSL2BoogieTranslator took 321.76ms. Allocated memory is still 191.9MB. Free memory was 162.6MB in the beginning and 156.3MB in the end (delta: 6.3MB). Peak memory consumption was 9.5MB. Max. memory is 8.0GB. * Boogie Procedure Inliner took 41.92ms. Allocated memory is still 191.9MB. Free memory was 156.3MB in the beginning and 154.3MB in the end (delta: 2.0MB). Peak memory consumption was 2.1MB. Max. memory is 8.0GB. * Boogie Preprocessor took 24.19ms. Allocated memory is still 191.9MB. Free memory was 154.3MB in the beginning and 153.0MB in the end (delta: 1.3MB). Peak memory consumption was 1.0MB. Max. memory is 8.0GB. * RCFGBuilder took 265.77ms. Allocated memory is still 191.9MB. Free memory was 152.8MB in the beginning and 139.9MB in the end (delta: 12.9MB). Peak memory consumption was 13.6MB. Max. memory is 8.0GB. * BuchiAutomizer took 2294.66ms. Allocated memory was 191.9MB in the beginning and 235.9MB in the end (delta: 44.0MB). Free memory was 139.9MB in the beginning and 205.0MB in the end (delta: -65.1MB). Peak memory consumption was 116.0MB. Max. memory is 8.0GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 4 terminating modules (4 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.4 modules have a trivial ranking function, the largest among these consists of 3 locations. The remainder module has 1051 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 2.1s and 5 iterations. TraceHistogramMax:1. Analysis of lassos took 1.2s. Construction of modules took 0.0s. Büchi inclusion checks took 0.3s. Highest rank in rank-based complementation 0. Minimization of det autom 4. Minimization of nondet autom 0. Automata minimization 0.1s AutomataMinimizationTime, 4 MinimizatonAttempts, 0 StatesRemovedByMinimization, 0 NontrivialMinimizations. Non-live state removal took 0.0s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 115 SdHoareTripleChecker+Valid, 0.1s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 115 mSDsluCounter, 525 SdHoareTripleChecker+Invalid, 0.1s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 194 mSDsCounter, 20 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 103 IncrementalHoareTripleChecker+Invalid, 123 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 20 mSolverCounterUnsat, 339 mSDtfsCounter, 103 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI0 SFLT0 conc4 concLT0 SILN0 SILU0 SILI0 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 704]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {\result={0:0}, \result=0, \result={0:0}, _={0:0}, _={0:0}, _={0:0}, _={0:0}, flag1=3, flag2=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@79eb4145 in0,2246, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@e895ffd in0,0, org.eclipse.cdt.internal.core.dom.parser.c.CASTIdExpression@5706374f=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTIdExpression@683714a0=0, t1={3:0}, t2={22217:0}, x=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 704]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L684] 0 int flag1 = 0, flag2 = 0; [L685] 0 int x; [L719] 0 pthread_t t1, t2; [L720] FCALL, FORK 0 pthread_create(&t1, 0, thr1, 0) [L687] 1 flag1 = 1 [L688] COND FALSE 1 !(flag2 >= 3) [L689] 1 flag1 = 3 [L721] FCALL, FORK 0 pthread_create(&t2, 0, thr2, 0) [L703] 2 flag2 = 1 Loop: [L704] COND TRUE flag1 >= 3 End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-07-26 13:22:21,030 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request...