/usr/bin/java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data -s ../../../trunk/examples/settings/gemcutter/NewStatesSleep-VarAbsGlobalSyntactic.epf -tc ../../../trunk/examples/toolchains/AutomizerBpl.xml -i ../../../trunk/examples/boogie-benchmarks-from-svcomp-memsafety-concurrent/race-4_1-thread_local_vars.line1357.bpl -------------------------------------------------------------------------------- This is Ultimate 0.2.2-wip.dk.por-optimizations-5c708e3-m [2022-10-04 01:03:11,252 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-10-04 01:03:11,253 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-10-04 01:03:11,278 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-10-04 01:03:11,278 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-10-04 01:03:11,281 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-10-04 01:03:11,284 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-10-04 01:03:11,289 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-10-04 01:03:11,291 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-10-04 01:03:11,296 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-10-04 01:03:11,297 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-10-04 01:03:11,298 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-10-04 01:03:11,298 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-10-04 01:03:11,300 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-10-04 01:03:11,302 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-10-04 01:03:11,303 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-10-04 01:03:11,304 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-10-04 01:03:11,304 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-10-04 01:03:11,308 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-10-04 01:03:11,313 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-10-04 01:03:11,314 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-10-04 01:03:11,315 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-10-04 01:03:11,317 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-10-04 01:03:11,318 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-10-04 01:03:11,324 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-10-04 01:03:11,324 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-10-04 01:03:11,324 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-10-04 01:03:11,326 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-10-04 01:03:11,326 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-10-04 01:03:11,327 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-10-04 01:03:11,327 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-10-04 01:03:11,328 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-10-04 01:03:11,329 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-10-04 01:03:11,330 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-10-04 01:03:11,331 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-10-04 01:03:11,331 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-10-04 01:03:11,331 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-10-04 01:03:11,331 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-10-04 01:03:11,332 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-10-04 01:03:11,332 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-10-04 01:03:11,333 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-10-04 01:03:11,333 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/gemcutter/NewStatesSleep-VarAbsGlobalSyntactic.epf [2022-10-04 01:03:11,367 INFO L113 SettingsManager]: Loading preferences was successful [2022-10-04 01:03:11,368 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-10-04 01:03:11,368 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-10-04 01:03:11,368 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-10-04 01:03:11,369 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-10-04 01:03:11,369 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-10-04 01:03:11,369 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-10-04 01:03:11,369 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-10-04 01:03:11,369 INFO L138 SettingsManager]: * Use SBE=true [2022-10-04 01:03:11,370 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-10-04 01:03:11,370 INFO L138 SettingsManager]: * sizeof long=4 [2022-10-04 01:03:11,370 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-10-04 01:03:11,370 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-10-04 01:03:11,370 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-10-04 01:03:11,370 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-10-04 01:03:11,370 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-10-04 01:03:11,370 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-10-04 01:03:11,371 INFO L138 SettingsManager]: * sizeof long double=12 [2022-10-04 01:03:11,371 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-10-04 01:03:11,371 INFO L138 SettingsManager]: * Use constant arrays=true [2022-10-04 01:03:11,373 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-10-04 01:03:11,373 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-10-04 01:03:11,373 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-10-04 01:03:11,374 INFO L138 SettingsManager]: * To the following directory=./dump/ [2022-10-04 01:03:11,374 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-10-04 01:03:11,375 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-10-04 01:03:11,375 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-10-04 01:03:11,375 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-10-04 01:03:11,375 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-10-04 01:03:11,376 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-10-04 01:03:11,376 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-10-04 01:03:11,376 INFO L138 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2022-10-04 01:03:11,376 INFO L138 SettingsManager]: * Abstraction used for commutativity in POR=VARIABLES_GLOBAL [2022-10-04 01:03:11,376 INFO L138 SettingsManager]: * Automaton type used in concurrency analysis=PARTIAL_ORDER_FA [2022-10-04 01:03:11,376 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-10-04 01:03:11,376 INFO L138 SettingsManager]: * CEGAR restart behaviour=ONE_CEGAR_PER_ERROR_LOCATION [2022-10-04 01:03:11,377 INFO L138 SettingsManager]: * Partial Order Reduction in concurrent analysis=SLEEP_NEW_STATES [2022-10-04 01:03:11,377 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2022-10-04 01:03:11,377 INFO L138 SettingsManager]: * Independence relation used for POR in concurrent analysis=SYNTACTIC WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release [2022-10-04 01:03:11,576 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-10-04 01:03:11,594 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-10-04 01:03:11,596 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-10-04 01:03:11,597 INFO L271 PluginConnector]: Initializing Boogie PL CUP Parser... [2022-10-04 01:03:11,598 INFO L275 PluginConnector]: Boogie PL CUP Parser initialized [2022-10-04 01:03:11,599 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/boogie-benchmarks-from-svcomp-memsafety-concurrent/race-4_1-thread_local_vars.line1357.bpl [2022-10-04 01:03:11,600 INFO L110 BoogieParser]: Parsing: '/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/boogie-benchmarks-from-svcomp-memsafety-concurrent/race-4_1-thread_local_vars.line1357.bpl' [2022-10-04 01:03:11,662 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-10-04 01:03:11,663 INFO L131 ToolchainWalker]: Walking toolchain with 3 elements. [2022-10-04 01:03:11,664 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-10-04 01:03:11,665 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-10-04 01:03:11,665 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-10-04 01:03:11,678 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "race-4_1-thread_local_vars.line1357.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.10 01:03:11" (1/1) ... [2022-10-04 01:03:11,679 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "race-4_1-thread_local_vars.line1357.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.10 01:03:11" (1/1) ... [2022-10-04 01:03:11,716 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "race-4_1-thread_local_vars.line1357.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.10 01:03:11" (1/1) ... [2022-10-04 01:03:11,717 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "race-4_1-thread_local_vars.line1357.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.10 01:03:11" (1/1) ... [2022-10-04 01:03:11,742 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "race-4_1-thread_local_vars.line1357.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.10 01:03:11" (1/1) ... [2022-10-04 01:03:11,749 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "race-4_1-thread_local_vars.line1357.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.10 01:03:11" (1/1) ... [2022-10-04 01:03:11,755 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "race-4_1-thread_local_vars.line1357.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.10 01:03:11" (1/1) ... [2022-10-04 01:03:11,762 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-10-04 01:03:11,768 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-10-04 01:03:11,768 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-10-04 01:03:11,768 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-10-04 01:03:11,775 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "race-4_1-thread_local_vars.line1357.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.10 01:03:11" (1/1) ... [2022-10-04 01:03:11,781 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-10-04 01:03:11,789 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-10-04 01:03:11,804 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-10-04 01:03:11,805 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-10-04 01:03:11,830 INFO L130 BoogieDeclarations]: Found specification of procedure thread_usb [2022-10-04 01:03:11,830 INFO L138 BoogieDeclarations]: Found implementation of procedure thread_usb [2022-10-04 01:03:11,830 INFO L130 BoogieDeclarations]: Found specification of procedure thread_ath9k [2022-10-04 01:03:11,830 INFO L138 BoogieDeclarations]: Found implementation of procedure thread_ath9k [2022-10-04 01:03:11,831 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-10-04 01:03:11,831 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-10-04 01:03:11,832 WARN L208 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement [2022-10-04 01:03:12,130 INFO L234 CfgBuilder]: Building ICFG [2022-10-04 01:03:12,132 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-10-04 01:03:12,483 INFO L275 CfgBuilder]: Performing block encoding [2022-10-04 01:03:12,498 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-10-04 01:03:12,498 INFO L299 CfgBuilder]: Removed 2 assume(true) statements. [2022-10-04 01:03:12,500 INFO L202 PluginConnector]: Adding new model race-4_1-thread_local_vars.line1357.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 04.10 01:03:12 BoogieIcfgContainer [2022-10-04 01:03:12,501 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-10-04 01:03:12,502 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-10-04 01:03:12,502 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-10-04 01:03:12,513 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-10-04 01:03:12,513 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "race-4_1-thread_local_vars.line1357.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.10 01:03:11" (1/2) ... [2022-10-04 01:03:12,514 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@80719db and model type race-4_1-thread_local_vars.line1357.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 04.10 01:03:12, skipping insertion in model container [2022-10-04 01:03:12,514 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "race-4_1-thread_local_vars.line1357.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 04.10 01:03:12" (2/2) ... [2022-10-04 01:03:12,516 INFO L112 eAbstractionObserver]: Analyzing ICFG race-4_1-thread_local_vars.line1357.bpl [2022-10-04 01:03:12,522 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2022-10-04 01:03:12,528 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-10-04 01:03:12,528 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-10-04 01:03:12,529 INFO L515 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2022-10-04 01:03:12,636 INFO L144 ThreadInstanceAdder]: Constructed 5 joinOtherThreadTransitions. [2022-10-04 01:03:12,689 INFO L100 denceProviderFactory]: Independence Relation #1: [IndependenceType=SYNTACTIC, AbstractionType=VARIABLES_GLOBAL, UseConditional=, UseSemiCommutativity=, Solver=, SolverTimeout=] [2022-10-04 01:03:12,691 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 [2022-10-04 01:03:12,695 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-10-04 01:03:12,698 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 (exit command is (exit), workingDir is null) [2022-10-04 01:03:12,717 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 (2)] Waiting until timeout for monitored process [2022-10-04 01:03:12,733 INFO L158 artialOrderCegarLoop]: Running PartialOrderCegarLoop with 1 independence relations. [2022-10-04 01:03:12,739 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == ULTIMATE.startErr0ASSERT_VIOLATIONASSERT ======== [2022-10-04 01:03:12,744 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=PARTIAL_ORDER_FA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@46f9d599, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2022-10-04 01:03:12,744 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-10-04 01:03:12,863 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT] === [2022-10-04 01:03:12,867 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-04 01:03:12,868 INFO L85 PathProgramCache]: Analyzing trace with hash 1327467712, now seen corresponding path program 1 times [2022-10-04 01:03:12,873 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-04 01:03:12,874 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [903545676] [2022-10-04 01:03:12,874 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-04 01:03:12,874 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-04 01:03:13,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-04 01:03:13,268 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-04 01:03:13,268 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-04 01:03:13,269 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [903545676] [2022-10-04 01:03:13,269 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [903545676] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-04 01:03:13,269 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-04 01:03:13,270 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-04 01:03:13,272 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1521507512] [2022-10-04 01:03:13,273 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-04 01:03:13,277 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 2 states [2022-10-04 01:03:13,277 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-04 01:03:13,294 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-10-04 01:03:13,295 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-10-04 01:03:13,295 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-10-04 01:03:13,298 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2022-10-04 01:03:13,298 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 2 states, 2 states have (on average 63.5) internal successors, (127), 2 states have internal predecessors, (127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-04 01:03:13,298 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2022-10-04 01:03:13,324 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-10-04 01:03:13,325 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-10-04 01:03:13,325 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT] === [2022-10-04 01:03:13,326 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-04 01:03:13,326 INFO L85 PathProgramCache]: Analyzing trace with hash -1689526522, now seen corresponding path program 1 times [2022-10-04 01:03:13,326 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-04 01:03:13,326 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [855728477] [2022-10-04 01:03:13,327 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-04 01:03:13,327 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-04 01:03:13,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-04 01:03:14,081 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-04 01:03:14,082 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-04 01:03:14,082 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [855728477] [2022-10-04 01:03:14,082 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [855728477] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-04 01:03:14,083 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-04 01:03:14,083 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2022-10-04 01:03:14,083 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [105025895] [2022-10-04 01:03:14,083 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-04 01:03:14,086 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2022-10-04 01:03:14,086 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-04 01:03:14,087 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2022-10-04 01:03:14,087 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2022-10-04 01:03:14,088 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-10-04 01:03:14,088 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2022-10-04 01:03:14,089 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 8 states have (on average 15.625) internal successors, (125), 9 states have internal predecessors, (125), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-04 01:03:14,090 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2022-10-04 01:03:14,090 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2022-10-04 01:03:14,431 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-10-04 01:03:14,432 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-10-04 01:03:14,432 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-10-04 01:03:14,432 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT] === [2022-10-04 01:03:14,433 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-04 01:03:14,433 INFO L85 PathProgramCache]: Analyzing trace with hash -1712257136, now seen corresponding path program 1 times [2022-10-04 01:03:14,433 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-04 01:03:14,434 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1540626792] [2022-10-04 01:03:14,434 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-04 01:03:14,435 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-04 01:03:14,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-04 01:03:14,590 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-04 01:03:14,591 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-04 01:03:14,591 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1540626792] [2022-10-04 01:03:14,592 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1540626792] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-04 01:03:14,592 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-04 01:03:14,593 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-04 01:03:14,593 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2022217712] [2022-10-04 01:03:14,593 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-04 01:03:14,595 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-10-04 01:03:14,595 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-04 01:03:14,596 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-10-04 01:03:14,596 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-10-04 01:03:14,596 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-10-04 01:03:14,597 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2022-10-04 01:03:14,597 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 42.4) internal successors, (212), 5 states have internal predecessors, (212), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-04 01:03:14,597 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2022-10-04 01:03:14,597 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 10 states. [2022-10-04 01:03:14,598 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2022-10-04 01:03:14,686 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-10-04 01:03:14,687 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-10-04 01:03:14,688 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-10-04 01:03:14,688 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2022-10-04 01:03:14,689 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT] === [2022-10-04 01:03:14,689 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-04 01:03:14,689 INFO L85 PathProgramCache]: Analyzing trace with hash -1132695671, now seen corresponding path program 1 times [2022-10-04 01:03:14,689 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-04 01:03:14,690 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1539286194] [2022-10-04 01:03:14,690 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-04 01:03:14,690 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-04 01:03:14,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-04 01:03:14,855 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2022-10-04 01:03:14,855 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-04 01:03:14,855 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1539286194] [2022-10-04 01:03:14,856 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1539286194] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-04 01:03:14,856 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-04 01:03:14,856 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-04 01:03:14,857 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1043894493] [2022-10-04 01:03:14,859 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-04 01:03:14,861 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-10-04 01:03:14,861 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-04 01:03:14,861 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-10-04 01:03:14,862 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-10-04 01:03:14,862 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-10-04 01:03:14,862 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2022-10-04 01:03:14,863 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 43.4) internal successors, (217), 5 states have internal predecessors, (217), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-04 01:03:14,863 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2022-10-04 01:03:14,863 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 10 states. [2022-10-04 01:03:14,863 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 6 states. [2022-10-04 01:03:14,864 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2022-10-04 01:03:14,931 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-10-04 01:03:14,933 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-10-04 01:03:14,938 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-10-04 01:03:14,938 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-10-04 01:03:14,938 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3 [2022-10-04 01:03:14,939 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT] === [2022-10-04 01:03:14,939 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-04 01:03:14,939 INFO L85 PathProgramCache]: Analyzing trace with hash -875005728, now seen corresponding path program 1 times [2022-10-04 01:03:14,940 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-04 01:03:14,940 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [942594738] [2022-10-04 01:03:14,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-04 01:03:14,941 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-04 01:03:14,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-04 01:03:15,053 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 37 proven. 0 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2022-10-04 01:03:15,053 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-04 01:03:15,054 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [942594738] [2022-10-04 01:03:15,054 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [942594738] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-04 01:03:15,054 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-04 01:03:15,054 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-04 01:03:15,054 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2095891247] [2022-10-04 01:03:15,054 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-04 01:03:15,055 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-10-04 01:03:15,055 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-04 01:03:15,056 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-04 01:03:15,056 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-04 01:03:15,056 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-10-04 01:03:15,056 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2022-10-04 01:03:15,057 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 83.0) internal successors, (249), 3 states have internal predecessors, (249), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-04 01:03:15,057 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2022-10-04 01:03:15,057 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 10 states. [2022-10-04 01:03:15,057 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 6 states. [2022-10-04 01:03:15,057 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 7 states. [2022-10-04 01:03:15,058 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2022-10-04 01:03:15,081 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-10-04 01:03:15,082 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-10-04 01:03:15,082 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-10-04 01:03:15,082 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-10-04 01:03:15,082 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-04 01:03:15,082 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4 [2022-10-04 01:03:15,083 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT] === [2022-10-04 01:03:15,083 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-04 01:03:15,083 INFO L85 PathProgramCache]: Analyzing trace with hash -140061847, now seen corresponding path program 1 times [2022-10-04 01:03:15,083 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-04 01:03:15,083 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [364308699] [2022-10-04 01:03:15,083 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-04 01:03:15,084 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-04 01:03:15,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-04 01:03:15,148 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-04 01:03:15,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-04 01:03:15,267 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-04 01:03:15,267 INFO L359 BasicCegarLoop]: Counterexample is feasible [2022-10-04 01:03:15,268 INFO L805 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr0ASSERT_VIOLATIONASSERT (0 of 1 remaining) [2022-10-04 01:03:15,271 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5 [2022-10-04 01:03:15,279 INFO L444 BasicCegarLoop]: Path program histogram: [1, 1, 1, 1, 1, 1] [2022-10-04 01:03:15,281 INFO L307 ceAbstractionStarter]: Result for error location ULTIMATE.startErr0ASSERT_VIOLATIONASSERT was UNSAFE (1/4) [2022-10-04 01:03:15,291 INFO L228 ceAbstractionStarter]: Analysis of concurrent program completed with 1 thread instances [2022-10-04 01:03:15,291 INFO L178 ceAbstractionStarter]: Computing trace abstraction results [2022-10-04 01:03:15,444 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,445 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,445 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,445 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,446 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,446 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,446 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,446 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,446 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,447 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,447 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,447 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,447 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,447 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,447 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,448 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,448 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,448 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,448 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,448 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,449 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,449 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,449 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,449 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,449 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,450 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,450 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,450 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,450 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,450 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,450 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,450 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,450 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,451 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,451 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,451 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,451 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,451 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,451 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,451 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,452 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,452 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,452 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,452 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,452 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,452 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,453 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,453 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,453 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,453 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,453 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,453 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,454 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,454 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,454 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,454 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,454 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,454 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,454 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,455 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,455 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,455 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,455 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,455 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,455 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,456 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,456 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,456 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,456 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,456 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,456 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,457 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,457 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,457 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,457 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,457 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,457 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,458 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,458 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,458 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,458 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,458 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,458 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,459 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,459 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,459 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,459 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,459 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,459 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,460 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,460 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,460 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,460 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,460 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,460 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,461 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,461 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,461 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,461 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,461 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,461 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,462 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,462 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,462 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,462 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,462 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,462 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,463 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,463 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,463 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,463 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,463 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,463 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,464 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,464 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,464 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,464 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,464 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,464 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,465 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,465 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,465 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,465 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,465 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,466 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,466 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,466 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,466 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,466 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,466 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,467 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,467 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,467 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,467 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,467 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,468 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,468 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,468 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,468 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,468 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,469 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,469 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,469 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,469 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,469 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,470 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,470 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,470 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,470 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,470 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,471 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,471 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,471 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,471 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,471 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,472 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,472 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,472 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,472 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,472 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,472 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,473 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,473 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,473 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,473 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,473 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,473 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,474 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,474 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,474 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,474 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,474 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,474 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,475 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,475 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,475 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,475 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,475 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,475 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,476 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,476 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,476 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,476 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,476 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,476 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,477 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,477 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,477 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,477 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,477 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,477 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,478 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,478 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,478 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,478 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,478 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,478 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,479 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,479 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,479 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,479 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,479 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,480 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,480 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,480 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,480 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,480 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,481 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,481 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,481 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,481 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,481 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,482 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,482 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,482 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,482 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,482 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,483 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,483 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,483 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,483 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,483 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,484 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,484 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,484 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,484 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,484 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,485 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,485 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,485 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,485 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,485 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,485 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,486 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,486 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,486 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,486 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,486 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,486 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,487 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,487 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,487 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,487 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,488 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled [2022-10-04 01:03:15,540 INFO L202 PluginConnector]: Adding new model race-4_1-thread_local_vars.line1357.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 04.10 01:03:15 BasicIcfg [2022-10-04 01:03:15,541 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2022-10-04 01:03:15,541 INFO L158 Benchmark]: Toolchain (without parser) took 3878.05ms. Allocated memory was 179.3MB in the beginning and 373.3MB in the end (delta: 194.0MB). Free memory was 131.0MB in the beginning and 295.9MB in the end (delta: -164.9MB). Peak memory consumption was 150.1MB. Max. memory is 8.0GB. [2022-10-04 01:03:15,543 INFO L158 Benchmark]: Boogie PL CUP Parser took 0.12ms. Allocated memory is still 179.3MB. Free memory is still 135.2MB. There was no memory consumed. Max. memory is 8.0GB. [2022-10-04 01:03:15,543 INFO L158 Benchmark]: Boogie Preprocessor took 97.58ms. Allocated memory is still 179.3MB. Free memory was 131.0MB in the beginning and 127.5MB in the end (delta: 3.6MB). Peak memory consumption was 3.1MB. Max. memory is 8.0GB. [2022-10-04 01:03:15,543 INFO L158 Benchmark]: RCFGBuilder took 732.60ms. Allocated memory is still 179.3MB. Free memory was 127.3MB in the beginning and 130.7MB in the end (delta: -3.3MB). Peak memory consumption was 15.4MB. Max. memory is 8.0GB. [2022-10-04 01:03:15,544 INFO L158 Benchmark]: TraceAbstraction took 3038.32ms. Allocated memory was 179.3MB in the beginning and 373.3MB in the end (delta: 194.0MB). Free memory was 129.8MB in the beginning and 295.9MB in the end (delta: -166.1MB). Peak memory consumption was 148.3MB. Max. memory is 8.0GB. [2022-10-04 01:03:15,545 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * Boogie PL CUP Parser took 0.12ms. Allocated memory is still 179.3MB. Free memory is still 135.2MB. There was no memory consumed. Max. memory is 8.0GB. * Boogie Preprocessor took 97.58ms. Allocated memory is still 179.3MB. Free memory was 131.0MB in the beginning and 127.5MB in the end (delta: 3.6MB). Peak memory consumption was 3.1MB. Max. memory is 8.0GB. * RCFGBuilder took 732.60ms. Allocated memory is still 179.3MB. Free memory was 127.3MB in the beginning and 130.7MB in the end (delta: -3.3MB). Peak memory consumption was 15.4MB. Max. memory is 8.0GB. * TraceAbstraction took 3038.32ms. Allocated memory was 179.3MB in the beginning and 373.3MB in the end (delta: 194.0MB). Free memory was 129.8MB in the beginning and 295.9MB in the end (delta: -166.1MB). Peak memory consumption was 148.3MB. Max. memory is 8.0GB. * Results from de.uni_freiburg.informatik.ultimate.boogie.preprocessor: - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Independence relation #1 benchmarks IndependenceRelationWithAbstraction.Independence Queries: [ total: 30, positive: 28, positive conditional: 28, positive unconditional: 0, negative: 2, negative conditional: 2, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , IndependenceRelationWithAbstraction.Statistics on underlying relation: ThreadSeparatingIndependenceRelation.Independence Queries: [ total: 2491, positive: 2364, positive conditional: 2364, positive unconditional: 0, negative: 127, negative conditional: 127, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ThreadSeparatingIndependenceRelation.Statistics on underlying relation: CachedIndependenceRelation.Independence Queries: [ total: 2372, positive: 2364, positive conditional: 0, positive unconditional: 2364, negative: 8, negative conditional: 0, negative unconditional: 8, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , CachedIndependenceRelation.Statistics on underlying relation: SyntacticIndependenceRelation.Independence Queries: [ total: 539, positive: 537, positive conditional: 0, positive unconditional: 537, negative: 2, negative conditional: 0, negative unconditional: 2, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , Cache Queries: [ total: 2372, positive: 1827, positive conditional: 0, positive unconditional: 1827, negative: 6, negative conditional: 0, negative unconditional: 6, unknown: 539, unknown conditional: 0, unknown unconditional: 539] , Statistics on independence cache: Total cache size (in pairs): 28, Positive cache size: 28, Positive conditional cache size: 0, Positive unconditional cache size: 28, Negative cache size: 0, Negative conditional cache size: 0, Negative unconditional cache size: 0, Independence queries for same thread: 2, Statistics for Abstraction: - StatisticsResult: Independence relation #2 benchmarks IndependenceRelationWithAbstraction.Independence Queries: [ total: 28, positive: 26, positive conditional: 26, positive unconditional: 0, negative: 2, negative conditional: 2, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , IndependenceRelationWithAbstraction.Statistics on underlying relation: ThreadSeparatingIndependenceRelation.Independence Queries: [ total: 2491, positive: 2364, positive conditional: 2364, positive unconditional: 0, negative: 127, negative conditional: 127, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ThreadSeparatingIndependenceRelation.Statistics on underlying relation: CachedIndependenceRelation.Independence Queries: [ total: 2372, positive: 2364, positive conditional: 0, positive unconditional: 2364, negative: 8, negative conditional: 0, negative unconditional: 8, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , CachedIndependenceRelation.Statistics on underlying relation: SyntacticIndependenceRelation.Independence Queries: [ total: 539, positive: 537, positive conditional: 0, positive unconditional: 537, negative: 2, negative conditional: 0, negative unconditional: 2, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , Cache Queries: [ total: 2372, positive: 1827, positive conditional: 0, positive unconditional: 1827, negative: 6, negative conditional: 0, negative unconditional: 6, unknown: 539, unknown conditional: 0, unknown unconditional: 539] , Statistics on independence cache: Total cache size (in pairs): 28, Positive cache size: 28, Positive conditional cache size: 0, Positive unconditional cache size: 28, Negative cache size: 0, Negative conditional cache size: 0, Negative unconditional cache size: 0, Independence queries for same thread: 4, Statistics for Abstraction: - StatisticsResult: Independence relation #3 benchmarks IndependenceRelationWithAbstraction.Independence Queries: [ total: 488, positive: 462, positive conditional: 462, positive unconditional: 0, negative: 26, negative conditional: 26, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , IndependenceRelationWithAbstraction.Statistics on underlying relation: ThreadSeparatingIndependenceRelation.Independence Queries: [ total: 2491, positive: 2364, positive conditional: 2364, positive unconditional: 0, negative: 127, negative conditional: 127, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ThreadSeparatingIndependenceRelation.Statistics on underlying relation: CachedIndependenceRelation.Independence Queries: [ total: 2372, positive: 2364, positive conditional: 0, positive unconditional: 2364, negative: 8, negative conditional: 0, negative unconditional: 8, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , CachedIndependenceRelation.Statistics on underlying relation: SyntacticIndependenceRelation.Independence Queries: [ total: 539, positive: 537, positive conditional: 0, positive unconditional: 537, negative: 2, negative conditional: 0, negative unconditional: 2, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , Cache Queries: [ total: 2372, positive: 1827, positive conditional: 0, positive unconditional: 1827, negative: 6, negative conditional: 0, negative unconditional: 6, unknown: 539, unknown conditional: 0, unknown unconditional: 539] , Statistics on independence cache: Total cache size (in pairs): 369, Positive cache size: 367, Positive conditional cache size: 0, Positive unconditional cache size: 367, Negative cache size: 2, Negative conditional cache size: 0, Negative unconditional cache size: 2, Independence queries for same thread: 28, Statistics for Abstraction: - StatisticsResult: Independence relation #4 benchmarks IndependenceRelationWithAbstraction.Independence Queries: [ total: 626, positive: 596, positive conditional: 596, positive unconditional: 0, negative: 30, negative conditional: 30, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , IndependenceRelationWithAbstraction.Statistics on underlying relation: ThreadSeparatingIndependenceRelation.Independence Queries: [ total: 2491, positive: 2364, positive conditional: 2364, positive unconditional: 0, negative: 127, negative conditional: 127, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ThreadSeparatingIndependenceRelation.Statistics on underlying relation: CachedIndependenceRelation.Independence Queries: [ total: 2372, positive: 2364, positive conditional: 0, positive unconditional: 2364, negative: 8, negative conditional: 0, negative unconditional: 8, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , CachedIndependenceRelation.Statistics on underlying relation: SyntacticIndependenceRelation.Independence Queries: [ total: 539, positive: 537, positive conditional: 0, positive unconditional: 537, negative: 2, negative conditional: 0, negative unconditional: 2, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , Cache Queries: [ total: 2372, positive: 1827, positive conditional: 0, positive unconditional: 1827, negative: 6, negative conditional: 0, negative unconditional: 6, unknown: 539, unknown conditional: 0, unknown unconditional: 539] , Statistics on independence cache: Total cache size (in pairs): 486, Positive cache size: 484, Positive conditional cache size: 0, Positive unconditional cache size: 484, Negative cache size: 2, Negative conditional cache size: 0, Negative unconditional cache size: 2, Independence queries for same thread: 56, Statistics for Abstraction: - StatisticsResult: Independence relation #5 benchmarks IndependenceRelationWithAbstraction.Independence Queries: [ total: 766, positive: 728, positive conditional: 728, positive unconditional: 0, negative: 38, negative conditional: 38, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , IndependenceRelationWithAbstraction.Statistics on underlying relation: ThreadSeparatingIndependenceRelation.Independence Queries: [ total: 2491, positive: 2364, positive conditional: 2364, positive unconditional: 0, negative: 127, negative conditional: 127, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ThreadSeparatingIndependenceRelation.Statistics on underlying relation: CachedIndependenceRelation.Independence Queries: [ total: 2372, positive: 2364, positive conditional: 0, positive unconditional: 2364, negative: 8, negative conditional: 0, negative unconditional: 8, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , CachedIndependenceRelation.Statistics on underlying relation: SyntacticIndependenceRelation.Independence Queries: [ total: 539, positive: 537, positive conditional: 0, positive unconditional: 537, negative: 2, negative conditional: 0, negative unconditional: 2, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , Cache Queries: [ total: 2372, positive: 1827, positive conditional: 0, positive unconditional: 1827, negative: 6, negative conditional: 0, negative unconditional: 6, unknown: 539, unknown conditional: 0, unknown unconditional: 539] , Statistics on independence cache: Total cache size (in pairs): 522, Positive cache size: 520, Positive conditional cache size: 0, Positive unconditional cache size: 520, Negative cache size: 2, Negative conditional cache size: 0, Negative unconditional cache size: 2, Independence queries for same thread: 92, Statistics for Abstraction: - StatisticsResult: Independence relation #6 benchmarks IndependenceRelationWithAbstraction.Independence Queries: [ total: 553, positive: 524, positive conditional: 524, positive unconditional: 0, negative: 29, negative conditional: 29, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , IndependenceRelationWithAbstraction.Statistics on underlying relation: ThreadSeparatingIndependenceRelation.Independence Queries: [ total: 2491, positive: 2364, positive conditional: 2364, positive unconditional: 0, negative: 127, negative conditional: 127, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ThreadSeparatingIndependenceRelation.Statistics on underlying relation: CachedIndependenceRelation.Independence Queries: [ total: 2372, positive: 2364, positive conditional: 0, positive unconditional: 2364, negative: 8, negative conditional: 0, negative unconditional: 8, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , CachedIndependenceRelation.Statistics on underlying relation: SyntacticIndependenceRelation.Independence Queries: [ total: 539, positive: 537, positive conditional: 0, positive unconditional: 537, negative: 2, negative conditional: 0, negative unconditional: 2, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , Cache Queries: [ total: 2372, positive: 1827, positive conditional: 0, positive unconditional: 1827, negative: 6, negative conditional: 0, negative unconditional: 6, unknown: 539, unknown conditional: 0, unknown unconditional: 539] , Statistics on independence cache: Total cache size (in pairs): 539, Positive cache size: 537, Positive conditional cache size: 0, Positive unconditional cache size: 537, Negative cache size: 2, Negative conditional cache size: 0, Negative unconditional cache size: 2, Independence queries for same thread: 119, Statistics for Abstraction: - CounterExampleResult [Line: 1357]: assertion can be violated assertion can be violated We found a FailurePath: [L1199] 0 assume { :begin_inline_ULTIMATE.init } true; [L1200] 0 #NULL := { base: 0, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0] [L1201] 0 assume 0 == #valid[0]; VAL [#NULL!base=0, #NULL!offset=0] [L1202] 0 assume 0 < #StackHeapBarrier; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5] [L1203] 0 assume { :begin_inline_#Ultimate.allocInit } true; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5] [L1204] 0 #Ultimate.allocInit_~size#1, #Ultimate.allocInit_ptrBase#1 := 2, 1; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=1, #Ultimate.allocInit_~size#1=2] [L1205] 0 assume 1 == #valid[#Ultimate.allocInit_ptrBase#1]; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=1, #Ultimate.allocInit_~size#1=2] [L1206] 0 assume #length[#Ultimate.allocInit_ptrBase#1] == #Ultimate.allocInit_~size#1; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=1, #Ultimate.allocInit_~size#1=2] [L1207] 0 assume { :end_inline_#Ultimate.allocInit } true; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=1, #Ultimate.allocInit_~size#1=2] [L1208] 0 assume { :begin_inline_write~init~int } true; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=1, #Ultimate.allocInit_~size#1=2] [L1209] 0 write~init~int_#value#1, write~init~int_#ptr#1, write~init~int_#sizeOfWrittenType#1 := 48, { base: 1, offset: 0 }, 1; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=1, #Ultimate.allocInit_~size#1=2, write~init~int_#ptr#1!base=1, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=1, write~init~int_#value#1=48] [L1210] 0 assume #memory_int[write~init~int_#ptr#1] == write~init~int_#value#1; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=1, #Ultimate.allocInit_~size#1=2, write~init~int_#ptr#1!base=1, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=1, write~init~int_#value#1=48] [L1211] 0 assume { :end_inline_write~init~int } true; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=1, #Ultimate.allocInit_~size#1=2, write~init~int_#ptr#1!base=1, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=1, write~init~int_#value#1=48] [L1212] 0 assume { :begin_inline_write~init~int } true; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=1, #Ultimate.allocInit_~size#1=2, write~init~int_#ptr#1!base=1, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=1, write~init~int_#value#1=48] [L1213] 0 write~init~int_#value#1, write~init~int_#ptr#1, write~init~int_#sizeOfWrittenType#1 := 0, { base: 1, offset: 1 }, 1; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=1, #Ultimate.allocInit_~size#1=2, write~init~int_#ptr#1!base=1, write~init~int_#ptr#1!offset=1, write~init~int_#sizeOfWrittenType#1=1, write~init~int_#value#1=0] [L1214] 0 assume #memory_int[write~init~int_#ptr#1] == write~init~int_#value#1; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=1, #Ultimate.allocInit_~size#1=2, write~init~int_#ptr#1!base=1, write~init~int_#ptr#1!offset=1, write~init~int_#sizeOfWrittenType#1=1, write~init~int_#value#1=0] [L1215] 0 assume { :end_inline_write~init~int } true; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=1, #Ultimate.allocInit_~size#1=2, write~init~int_#ptr#1!base=1, write~init~int_#ptr#1!offset=1, write~init~int_#sizeOfWrittenType#1=1, write~init~int_#value#1=0] [L1216] 0 assume { :begin_inline_#Ultimate.allocInit } true; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=1, #Ultimate.allocInit_~size#1=2, write~init~int_#ptr#1!base=1, write~init~int_#ptr#1!offset=1, write~init~int_#sizeOfWrittenType#1=1, write~init~int_#value#1=0] [L1217] 0 #Ultimate.allocInit_~size#1, #Ultimate.allocInit_ptrBase#1 := 29, 2; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=2, #Ultimate.allocInit_~size#1=29, write~init~int_#ptr#1!base=1, write~init~int_#ptr#1!offset=1, write~init~int_#sizeOfWrittenType#1=1, write~init~int_#value#1=0] [L1218] 0 assume 1 == #valid[#Ultimate.allocInit_ptrBase#1]; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=2, #Ultimate.allocInit_~size#1=29, write~init~int_#ptr#1!base=1, write~init~int_#ptr#1!offset=1, write~init~int_#sizeOfWrittenType#1=1, write~init~int_#value#1=0] [L1219] 0 assume #length[#Ultimate.allocInit_ptrBase#1] == #Ultimate.allocInit_~size#1; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=2, #Ultimate.allocInit_~size#1=29, write~init~int_#ptr#1!base=1, write~init~int_#ptr#1!offset=1, write~init~int_#sizeOfWrittenType#1=1, write~init~int_#value#1=0] [L1220] 0 assume { :end_inline_#Ultimate.allocInit } true; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=2, #Ultimate.allocInit_~size#1=29, write~init~int_#ptr#1!base=1, write~init~int_#ptr#1!offset=1, write~init~int_#sizeOfWrittenType#1=1, write~init~int_#value#1=0] [L1221] 0 ~#t1~0 := { base: 3, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=2, #Ultimate.allocInit_~size#1=29, write~init~int_#ptr#1!base=1, write~init~int_#ptr#1!offset=1, write~init~int_#sizeOfWrittenType#1=1, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0] [L1222] 0 assume { :begin_inline_#Ultimate.allocInit } true; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=2, #Ultimate.allocInit_~size#1=29, write~init~int_#ptr#1!base=1, write~init~int_#ptr#1!offset=1, write~init~int_#sizeOfWrittenType#1=1, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0] [L1223] 0 #Ultimate.allocInit_~size#1, #Ultimate.allocInit_ptrBase#1 := 4, 3; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=3, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=1, write~init~int_#ptr#1!offset=1, write~init~int_#sizeOfWrittenType#1=1, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0] [L1224] 0 assume 1 == #valid[#Ultimate.allocInit_ptrBase#1]; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=3, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=1, write~init~int_#ptr#1!offset=1, write~init~int_#sizeOfWrittenType#1=1, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0] [L1225] 0 assume #length[#Ultimate.allocInit_ptrBase#1] == #Ultimate.allocInit_~size#1; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=3, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=1, write~init~int_#ptr#1!offset=1, write~init~int_#sizeOfWrittenType#1=1, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0] [L1226] 0 assume { :end_inline_#Ultimate.allocInit } true; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=3, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=1, write~init~int_#ptr#1!offset=1, write~init~int_#sizeOfWrittenType#1=1, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0] [L1227] 0 assume { :begin_inline_write~init~int } true; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=3, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=1, write~init~int_#ptr#1!offset=1, write~init~int_#sizeOfWrittenType#1=1, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0] [L1228] 0 write~init~int_#value#1, write~init~int_#ptr#1, write~init~int_#sizeOfWrittenType#1 := 0, ~#t1~0, 4; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=3, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=3, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0] [L1229] 0 assume #memory_int[write~init~int_#ptr#1] == write~init~int_#value#1; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=3, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=3, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0] [L1230] 0 assume { :end_inline_write~init~int } true; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=3, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=3, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0] [L1231] 0 ~#t2~0 := { base: 4, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=3, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=3, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0] [L1232] 0 assume { :begin_inline_#Ultimate.allocInit } true; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=3, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=3, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0] [L1233] 0 #Ultimate.allocInit_~size#1, #Ultimate.allocInit_ptrBase#1 := 4, 4; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=4, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=3, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0] [L1234] 0 assume 1 == #valid[#Ultimate.allocInit_ptrBase#1]; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=4, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=3, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0] [L1235] 0 assume #length[#Ultimate.allocInit_ptrBase#1] == #Ultimate.allocInit_~size#1; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=4, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=3, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0] [L1236] 0 assume { :end_inline_#Ultimate.allocInit } true; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=4, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=3, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0] [L1237] 0 assume { :begin_inline_write~init~int } true; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=4, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=3, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0] [L1238] 0 write~init~int_#value#1, write~init~int_#ptr#1, write~init~int_#sizeOfWrittenType#1 := 0, ~#t2~0, 4; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=4, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=4, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0] [L1239] 0 assume #memory_int[write~init~int_#ptr#1] == write~init~int_#value#1; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=4, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=4, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0] [L1240] 0 assume { :end_inline_write~init~int } true; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=4, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=4, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0] [L1241] 0 ~#mutex~0 := { base: 5, offset: 0 }; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=4, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=4, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0] [L1242] 0 assume { :begin_inline_#Ultimate.allocInit } true; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=4, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=4, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0] [L1243] 0 #Ultimate.allocInit_~size#1, #Ultimate.allocInit_ptrBase#1 := 24, 5; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=4, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0] [L1244] 0 assume 1 == #valid[#Ultimate.allocInit_ptrBase#1]; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=4, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0] [L1245] 0 assume #length[#Ultimate.allocInit_ptrBase#1] == #Ultimate.allocInit_~size#1; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=4, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0] [L1246] 0 assume { :end_inline_#Ultimate.allocInit } true; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=4, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0] [L1247] 0 assume { :begin_inline_write~init~int } true; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=4, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0] [L1248] 0 write~init~int_#value#1, write~init~int_#ptr#1, write~init~int_#sizeOfWrittenType#1 := 0, { base: ~#mutex~0!base, offset: ~#mutex~0!offset }, 4; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0] [L1249] 0 assume #memory_int[write~init~int_#ptr#1] == write~init~int_#value#1; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0] [L1250] 0 assume { :end_inline_write~init~int } true; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0] [L1251] 0 assume { :begin_inline_write~init~int } true; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0] [L1252] 0 write~init~int_#value#1, write~init~int_#ptr#1, write~init~int_#sizeOfWrittenType#1 := 0, { base: ~#mutex~0!base, offset: 4 + ~#mutex~0!offset }, 4; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=4, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0] [L1253] 0 assume #memory_int[write~init~int_#ptr#1] == write~init~int_#value#1; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=4, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0] [L1254] 0 assume { :end_inline_write~init~int } true; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=4, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0] [L1255] 0 assume { :begin_inline_write~init~int } true; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=4, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0] [L1256] 0 write~init~int_#value#1, write~init~int_#ptr#1, write~init~int_#sizeOfWrittenType#1 := 0, { base: ~#mutex~0!base, offset: 8 + ~#mutex~0!offset }, 4; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=8, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0] [L1257] 0 assume #memory_int[write~init~int_#ptr#1] == write~init~int_#value#1; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=8, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0] [L1258] 0 assume { :end_inline_write~init~int } true; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=8, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0] [L1259] 0 assume { :begin_inline_write~init~int } true; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=8, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0] [L1260] 0 write~init~int_#value#1, write~init~int_#ptr#1, write~init~int_#sizeOfWrittenType#1 := 0, { base: ~#mutex~0!base, offset: 12 + ~#mutex~0!offset }, 4; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=12, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0] [L1261] 0 assume #memory_int[write~init~int_#ptr#1] == write~init~int_#value#1; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=12, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0] [L1262] 0 assume { :end_inline_write~init~int } true; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=12, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0] [L1263] 0 assume { :begin_inline_write~init~int } true; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=12, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0] [L1264] 0 write~init~int_#value#1, write~init~int_#ptr#1, write~init~int_#sizeOfWrittenType#1 := 0, { base: ~#mutex~0!base, offset: 16 + ~#mutex~0!offset }, 4; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0] [L1265] 0 assume #memory_int[write~init~int_#ptr#1] == write~init~int_#value#1; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0] [L1266] 0 assume { :end_inline_write~init~int } true; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0] [L1267] 0 ~pdev~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~pdev~0=0] [L1268] 0 ~ldv_usb_state~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=0] [L1270] 0 assume { :end_inline_ULTIMATE.init } true; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=0] [L1271] 0 assume { :begin_inline_main } true; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=0] [L1272] 0 havoc main_#res#1; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=0] [L1273] 0 havoc main_#t~ret48#1; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=0] [L1274] 0 assume { :begin_inline_module_init } true; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=0] [L1275] 0 havoc module_init_#res#1; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=0] [L1276] 0 havoc module_init_#t~nondet43#1, module_init_#t~pre44#1, module_init_#t~nondet45#1; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=0] [L1277] 0 #pthreadsMutex[~#mutex~0] := 0; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=0] [L1278] 0 ~pdev~0 := 1; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1279] 0 assume { :begin_inline_ldv_assert } true; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1280] 0 ldv_assert_#in~expression#1 := (if 1 == ~pdev~0 then 1 else 0); VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1281] 0 havoc ldv_assert_~expression#1; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1282] 0 ldv_assert_~expression#1 := ldv_assert_#in~expression#1; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1283] COND FALSE 0 !(0 == ldv_assert_~expression#1) VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1290] 0 assume { :end_inline_ldv_assert } true; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1291] 0 assume -2147483648 <= module_init_#t~nondet43#1 && module_init_#t~nondet43#1 <= 2147483647; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~nondet43#1=1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1292] COND TRUE 0 0 != module_init_#t~nondet43#1 VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~nondet43#1=1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1293] 0 havoc module_init_#t~nondet43#1; VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1294] 0 module_init_#t~pre44#1 := #pthreadsForks; VAL [#NULL!base=0, #NULL!offset=0, #pthreadsForks=-1, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1295] 0 #pthreadsForks := 1 + #pthreadsForks; VAL [#NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1296] 0 write~int_old_#memory_$Pointer$#1, write~int_old_#memory_int#1 := #memory_$Pointer$, #memory_int; VAL [#NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1297] 0 assume { :begin_inline_write~int } true; VAL [#NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1298] 0 write~int_#value#1, write~int_#ptr#1, write~int_#sizeOfWrittenType#1 := module_init_#t~pre44#1, ~#t1~0, 4; VAL [#NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1301] 0 assume 1 == #valid[write~int_#ptr#1!base]; VAL [#NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1302] 0 assume write~int_#sizeOfWrittenType#1 + write~int_#ptr#1!offset <= #length[write~int_#ptr#1!base] && 0 <= write~int_#ptr#1!offset; VAL [#NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1303] 0 havoc #memory_int, #memory_$Pointer$; VAL [#NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1304] 0 assume #memory_int == write~int_old_#memory_int#1[write~int_#ptr#1 := write~int_#value#1] && #memory_$Pointer$ == write~int_old_#memory_$Pointer$#1[write~int_#ptr#1 := #memory_$Pointer$[write~int_#ptr#1]]; VAL [#NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1305] 0 assume { :end_inline_write~int } true; VAL [#NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1306] FORK 0 fork module_init_#t~pre44#1, 0, 0 thread_usb({ base: 0, offset: 0 }); VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1307] 0 havoc module_init_#t~pre44#1; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1308] 0 havoc module_init_#t~nondet45#1; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1309] 0 module_init_#res#1 := 0; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1330] 0 main_#t~ret48#1 := module_init_#res#1; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, main_#t~ret48#1=0, module_init_#res#1=0, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1331] 0 assume { :end_inline_module_init } true; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, main_#t~ret48#1=0, module_init_#res#1=0, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1332] 0 assume -2147483648 <= main_#t~ret48#1 && main_#t~ret48#1 <= 2147483647; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, main_#t~ret48#1=0, module_init_#res#1=0, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1333] COND FALSE 0 !(0 != main_#t~ret48#1) VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, main_#t~ret48#1=0, module_init_#res#1=0, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1337] 0 havoc main_#t~ret48#1; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1339] 0 assume { :begin_inline_module_exit } true; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1340] 0 havoc module_exit_#t~mem46#1, module_exit_#t~nondet47#1, module_exit_~#status~1#1; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1341] 0 #Ultimate.allocOnStack_old_#length#1, #Ultimate.allocOnStack_old_#valid#1 := #length, #valid; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1342] 0 assume { :begin_inline_#Ultimate.allocOnStack } true; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1343] 0 #Ultimate.allocOnStack_~size#1 := 4; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_~size#1=4, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1344] 0 havoc #Ultimate.allocOnStack_#res#1; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_~size#1=4, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1345] 0 havoc #valid, #length; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_~size#1=4, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1346] 0 assume 0 == #Ultimate.allocOnStack_old_#valid#1[#Ultimate.allocOnStack_#res#1!base]; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_~size#1=4, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1347] 0 assume #valid == #Ultimate.allocOnStack_old_#valid#1[#Ultimate.allocOnStack_#res#1!base := 1]; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_~size#1=4, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1348] 0 assume 0 == #Ultimate.allocOnStack_#res#1!offset; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1349] 0 assume 0 != #Ultimate.allocOnStack_#res#1!base; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1350] 0 assume #StackHeapBarrier < #Ultimate.allocOnStack_#res#1!base; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1351] 0 assume #length == #Ultimate.allocOnStack_old_#length#1[#Ultimate.allocOnStack_#res#1!base := #Ultimate.allocOnStack_~size#1]; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1352] 0 module_exit_~#status~1#1 := #Ultimate.allocOnStack_#res#1; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1353] 0 assume { :end_inline_#Ultimate.allocOnStack } true; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1354] 0 assume { :begin_inline_read~int } true; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1355] 0 read~int_#ptr#1, read~int_#sizeOfReadType#1 := ~#t1~0, 4; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L922] 1 ~arg#1 := #in~arg#1; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L923] 1 ~ldv_usb_state~0 := 0; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L924] 1 havoc ~probe_ret~0#1; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L928] COND FALSE 1 !(false) VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L931] 1 assume -2147483648 <= #t~nondet40#1 && #t~nondet40#1 <= 2147483647; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L932] 1 #t~switch41#1 := 0 == #t~nondet40#1; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L933] COND TRUE 1 #t~switch41#1 VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L934] COND TRUE 1 0 == ~ldv_usb_state~0 VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L935] 1 assume { :begin_inline_ath_ahb_probe } true; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L936] 1 havoc ath_ahb_probe_#res#1; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L937] 1 havoc ath_ahb_probe_#t~ret39#1, ath_ahb_probe_~error~0#1; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L938] 1 havoc ath_ahb_probe_~error~0#1; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L939] 1 assume { :begin_inline_ieee80211_register_hw } true; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L940] 1 havoc ieee80211_register_hw_#res#1; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L941] 1 havoc ieee80211_register_hw_#t~nondet34#1, ieee80211_register_hw_#t~pre35#1, ieee80211_register_hw_#t~nondet36#1; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L942] 1 assume -2147483648 <= ieee80211_register_hw_#t~nondet34#1 && ieee80211_register_hw_#t~nondet34#1 <= 2147483647; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~nondet34#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L943] COND TRUE 1 0 != ieee80211_register_hw_#t~nondet34#1 VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~nondet34#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L944] 1 havoc ieee80211_register_hw_#t~nondet34#1; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L945] 1 ieee80211_register_hw_#t~pre35#1 := #pthreadsForks; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L946] 1 #pthreadsForks := 1 + #pthreadsForks; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L947] 1 write~int_old_#memory_$Pointer$#1, write~int_old_#memory_int#1 := #memory_$Pointer$, #memory_int; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L948] 1 assume { :begin_inline_write~int } true; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L949] 1 write~int_#value#1, write~int_#ptr#1, write~int_#sizeOfWrittenType#1 := ieee80211_register_hw_#t~pre35#1, ~#t2~0, 4; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L952] 1 assume 1 == #valid[write~int_#ptr#1!base]; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L953] 1 assume write~int_#sizeOfWrittenType#1 + write~int_#ptr#1!offset <= #length[write~int_#ptr#1!base] && 0 <= write~int_#ptr#1!offset; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L954] 1 havoc #memory_int, #memory_$Pointer$; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L955] 1 assume #memory_int == write~int_old_#memory_int#1[write~int_#ptr#1 := write~int_#value#1] && #memory_$Pointer$ == write~int_old_#memory_$Pointer$#1[write~int_#ptr#1 := #memory_$Pointer$[write~int_#ptr#1]]; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L956] 1 assume { :end_inline_write~int } true; VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L957] FORK 1 fork ieee80211_register_hw_#t~pre35#1, 0 thread_ath9k({ base: 0, offset: 0 }); VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1114] 2 ~arg#1 := #in~arg#1; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1118] COND FALSE 2 !(false) VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1121] 2 assume -2147483648 <= #t~nondet32#1 && #t~nondet32#1 <= 2147483647; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1122] 2 #t~switch33#1 := 1 == #t~nondet32#1; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1123] COND TRUE 2 #t~switch33#1 VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1124] 2 assume { :begin_inline_ath9k_flush } true; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1125] 2 havoc ath9k_flush_#t~nondet31#1; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1126] 2 #PthreadsMutexLock_old_#pthreadsMutex#1 := #pthreadsMutex; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1127] 2 assume { :begin_inline_#PthreadsMutexLock } true; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1128] 2 #PthreadsMutexLock_#inputPtr#1 := ~#mutex~0; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1129] 2 havoc #PthreadsMutexLock_#res#1; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1130] 2 havoc #pthreadsMutex; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1131] 2 assume 0 == #PthreadsMutexLock_old_#pthreadsMutex#1[#PthreadsMutexLock_#inputPtr#1]; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1132] 2 assume #pthreadsMutex == #PthreadsMutexLock_old_#pthreadsMutex#1[#PthreadsMutexLock_#inputPtr#1 := 1]; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1133] 2 assume 0 == #PthreadsMutexLock_#res#1; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1134] 2 ath9k_flush_#t~nondet31#1 := #PthreadsMutexLock_#res#1; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath9k_flush_#t~nondet31#1=0, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1135] 2 assume { :end_inline_#PthreadsMutexLock } true; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath9k_flush_#t~nondet31#1=0, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1136] 2 havoc ath9k_flush_#t~nondet31#1; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1] [L1137] 2 ~pdev~0 := 6; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L1138] 2 assume { :begin_inline_ldv_assert } true; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L1139] 2 ldv_assert_#in~expression#1 := (if 6 == ~pdev~0 then 1 else 0); VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L1140] 2 havoc ldv_assert_~expression#1; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L1141] 2 ldv_assert_~expression#1 := ldv_assert_#in~expression#1; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L1142] COND FALSE 2 !(0 == ldv_assert_~expression#1) VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L1149] 2 assume { :end_inline_ldv_assert } true; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L1150] 2 #pthreadsMutex[~#mutex~0] := 0; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L1152] 2 assume { :end_inline_ath9k_flush } true; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L1160] 2 havoc #t~nondet32#1; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L1161] 2 havoc #t~switch33#1; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L1118] COND FALSE 2 !(false) VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L1121] 2 assume -2147483648 <= #t~nondet32#1 && #t~nondet32#1 <= 2147483647; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L1122] 2 #t~switch33#1 := 1 == #t~nondet32#1; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L1123] COND TRUE 2 #t~switch33#1 VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L1124] 2 assume { :begin_inline_ath9k_flush } true; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L1125] 2 havoc ath9k_flush_#t~nondet31#1; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L1126] 2 #PthreadsMutexLock_old_#pthreadsMutex#1 := #pthreadsMutex; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L1127] 2 assume { :begin_inline_#PthreadsMutexLock } true; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L1128] 2 #PthreadsMutexLock_#inputPtr#1 := ~#mutex~0; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L1129] 2 havoc #PthreadsMutexLock_#res#1; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L1130] 2 havoc #pthreadsMutex; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L1131] 2 assume 0 == #PthreadsMutexLock_old_#pthreadsMutex#1[#PthreadsMutexLock_#inputPtr#1]; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L1132] 2 assume #pthreadsMutex == #PthreadsMutexLock_old_#pthreadsMutex#1[#PthreadsMutexLock_#inputPtr#1 := 1]; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L1133] 2 assume 0 == #PthreadsMutexLock_#res#1; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L1134] 2 ath9k_flush_#t~nondet31#1 := #PthreadsMutexLock_#res#1; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath9k_flush_#t~nondet31#1=0, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L1135] 2 assume { :end_inline_#PthreadsMutexLock } true; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath9k_flush_#t~nondet31#1=0, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L1136] 2 havoc ath9k_flush_#t~nondet31#1; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L1137] 2 ~pdev~0 := 6; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L1138] 2 assume { :begin_inline_ldv_assert } true; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L1139] 2 ldv_assert_#in~expression#1 := (if 6 == ~pdev~0 then 1 else 0); VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#t~pre35#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L958] 1 havoc ieee80211_register_hw_#t~pre35#1; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L959] 1 havoc ieee80211_register_hw_#t~nondet36#1; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L960] 1 ieee80211_register_hw_#res#1 := 0; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L968] 1 ath_ahb_probe_#t~ret39#1 := ieee80211_register_hw_#res#1; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#t~ret39#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L969] 1 assume { :end_inline_ieee80211_register_hw } true; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#t~ret39#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L970] 1 assume -2147483648 <= ath_ahb_probe_#t~ret39#1 && ath_ahb_probe_#t~ret39#1 <= 2147483647; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#t~ret39#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L971] 1 ath_ahb_probe_~error~0#1 := ath_ahb_probe_#t~ret39#1; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#t~ret39#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L972] 1 havoc ath_ahb_probe_#t~ret39#1; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L973] COND FALSE 1 !(0 != ath_ahb_probe_~error~0#1) VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L976] 1 ath_ahb_probe_#res#1 := 0; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L982] 1 #t~ret42#1 := ath_ahb_probe_#res#1; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~ret42#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L983] 1 assume { :end_inline_ath_ahb_probe } true; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~ret42#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L984] 1 assume -2147483648 <= #t~ret42#1 && #t~ret42#1 <= 2147483647; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~ret42#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6] [L985] 1 ~probe_ret~0#1 := #t~ret42#1; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~ret42#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6, ~probe_ret~0#1=0] [L986] 1 havoc #t~ret42#1; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6, ~probe_ret~0#1=0] [L987] COND FALSE 1 !(0 != ~probe_ret~0#1) VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=6, ~probe_ret~0#1=0] [L990] 1 ~ldv_usb_state~0 := 1; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=0, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=6, ~probe_ret~0#1=0] [L1080] 1 havoc #t~nondet40#1; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=6, ~probe_ret~0#1=0] [L1081] 1 havoc #t~switch41#1; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~switch33#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=6, ~probe_ret~0#1=0] [L928] COND FALSE 1 !(false) VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~switch33#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=6, ~probe_ret~0#1=0] [L931] 1 assume -2147483648 <= #t~nondet40#1 && #t~nondet40#1 <= 2147483647; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=1, #t~switch33#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=6, ~probe_ret~0#1=0] [L932] 1 #t~switch41#1 := 0 == #t~nondet40#1; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=1, #t~switch33#1=true, #t~switch41#1=false, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=6, ~probe_ret~0#1=0] [L933] COND FALSE 1 !(#t~switch41#1) VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=1, #t~switch33#1=true, #t~switch41#1=false, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=6, ~probe_ret~0#1=0] [L994] 1 #t~switch41#1 := #t~switch41#1 || 1 == #t~nondet40#1; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=1, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=6, ~probe_ret~0#1=0] [L995] COND TRUE 1 #t~switch41#1 VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=1, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=6, ~probe_ret~0#1=0] [L996] COND TRUE 1 1 == ~ldv_usb_state~0 VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=1, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=6, ~probe_ret~0#1=0] [L997] 1 assume { :begin_inline_ath_ahb_disconnect } true; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=1, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=6, ~probe_ret~0#1=0] [L998] 1 assume { :begin_inline_ieee80211_deregister_hw } true; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=1, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=6, ~probe_ret~0#1=0] [L999] 1 havoc ieee80211_deregister_hw_#t~mem37#1, ieee80211_deregister_hw_#t~nondet38#1, ieee80211_deregister_hw_~#status~0#1; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=1, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=6, ~probe_ret~0#1=0] [L1000] 1 #Ultimate.allocOnStack_old_#length#1, #Ultimate.allocOnStack_old_#valid#1 := #length, #valid; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=1, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=6, ~probe_ret~0#1=0] [L1001] 1 assume { :begin_inline_#Ultimate.allocOnStack } true; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=1, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=6, ~probe_ret~0#1=0] [L1002] 1 #Ultimate.allocOnStack_~size#1 := 4; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=1, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=6, ~probe_ret~0#1=0] [L1003] 1 havoc #Ultimate.allocOnStack_#res#1; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=1, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=6, ~probe_ret~0#1=0] [L1004] 1 havoc #valid, #length; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=1, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=6, ~probe_ret~0#1=0] [L1357] 0 assert read~int_#sizeOfReadType#1 + read~int_#ptr#1!offset <= #length[read~int_#ptr#1!base] && 0 <= read~int_#ptr#1!offset; VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=1, #PthreadsMutexLock_#inputPtr#1!base=5, #PthreadsMutexLock_#inputPtr#1!offset=0, #PthreadsMutexLock_#res#1=0, #StackHeapBarrier=5, #t~nondet32#1=1, #t~nondet40#1=1, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_exit_~#status~1#1!base=6, module_exit_~#status~1#1!offset=0, module_init_#res#1=0, read~int_#ptr#1!base=3, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=6, ~probe_ret~0#1=0] - StatisticsResult: Ultimate Automizer benchmark data for error location: ULTIMATE.startErr0ASSERT_VIOLATIONASSERT with 1 thread instances CFG has 5 procedures, 500 locations, 4 error locations. Started 1 CEGAR loops. OverallTime: 2.6s, OverallIterations: 6, TraceHistogramMax: 0, PathProgramHistogramMax: 1, EmptinessCheckTime: 0.7s, AutomataDifference: 0.0s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: , PredicateUnifierStatistics: No data available, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=0occurred in iteration=0, InterpolantAutomatonStates: 28, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: No data available, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 1.1s InterpolantComputationTime, 1207 NumberOfCodeBlocks, 1207 NumberOfCodeBlocksAsserted, 6 NumberOfCheckSat, 965 ConstructedInterpolants, 0 QuantifiedInterpolants, 1910 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 5 InterpolantComputations, 5 PerfectInterpolantSequences, 85/85 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! [2022-10-04 01:03:15,595 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 (2)] Forceful destruction successful, exit code 0 [2022-10-04 01:03:15,811 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Forceful destruction successful, exit code 0 Received shutdown request...