/usr/bin/java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data -s ../../../trunk/examples/settings/gemcutter/NewStatesSleep-VarAbsGlobalSyntactic.epf -tc ../../../trunk/examples/toolchains/AutomizerBpl.xml -i ../../../trunk/examples/boogie-benchmarks-from-svcomp-memsafety-concurrent/race-4_2-thread_local_vars.line1041.bpl
--------------------------------------------------------------------------------
This is Ultimate 0.2.2-wip.dk.por-optimizations-5c708e3-m
[2022-10-04 01:03:37,465 INFO L177 SettingsManager]: Resetting all preferences to default values...
[2022-10-04 01:03:37,467 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values
[2022-10-04 01:03:37,487 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring...
[2022-10-04 01:03:37,487 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values
[2022-10-04 01:03:37,488 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values
[2022-10-04 01:03:37,489 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values
[2022-10-04 01:03:37,490 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values
[2022-10-04 01:03:37,491 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values
[2022-10-04 01:03:37,492 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values
[2022-10-04 01:03:37,492 INFO L181 SettingsManager]: Resetting Sifa preferences to default values
[2022-10-04 01:03:37,493 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring...
[2022-10-04 01:03:37,493 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values
[2022-10-04 01:03:37,494 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values
[2022-10-04 01:03:37,494 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values
[2022-10-04 01:03:37,495 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values
[2022-10-04 01:03:37,496 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values
[2022-10-04 01:03:37,496 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values
[2022-10-04 01:03:37,497 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values
[2022-10-04 01:03:37,499 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values
[2022-10-04 01:03:37,509 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values
[2022-10-04 01:03:37,513 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values
[2022-10-04 01:03:37,514 INFO L181 SettingsManager]: Resetting Referee preferences to default values
[2022-10-04 01:03:37,514 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values
[2022-10-04 01:03:37,517 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring...
[2022-10-04 01:03:37,517 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring...
[2022-10-04 01:03:37,517 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values
[2022-10-04 01:03:37,517 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values
[2022-10-04 01:03:37,518 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values
[2022-10-04 01:03:37,518 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring...
[2022-10-04 01:03:37,518 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values
[2022-10-04 01:03:37,519 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values
[2022-10-04 01:03:37,519 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values
[2022-10-04 01:03:37,520 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values
[2022-10-04 01:03:37,520 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring...
[2022-10-04 01:03:37,520 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values
[2022-10-04 01:03:37,521 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring...
[2022-10-04 01:03:37,521 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring...
[2022-10-04 01:03:37,521 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values
[2022-10-04 01:03:37,522 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values
[2022-10-04 01:03:37,522 INFO L188 SettingsManager]: Finished resetting all preferences to default values...
[2022-10-04 01:03:37,526 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/gemcutter/NewStatesSleep-VarAbsGlobalSyntactic.epf
[2022-10-04 01:03:37,541 INFO L113 SettingsManager]: Loading preferences was successful
[2022-10-04 01:03:37,541 INFO L115 SettingsManager]: Preferences different from defaults after loading the file:
[2022-10-04 01:03:37,541 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults:
[2022-10-04 01:03:37,541 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR;
[2022-10-04 01:03:37,541 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults:
[2022-10-04 01:03:37,542 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS
[2022-10-04 01:03:37,542 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults:
[2022-10-04 01:03:37,542 INFO L138 SettingsManager]: * Create parallel compositions if possible=false
[2022-10-04 01:03:37,542 INFO L138 SettingsManager]: * Use SBE=true
[2022-10-04 01:03:37,542 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults:
[2022-10-04 01:03:37,542 INFO L138 SettingsManager]: * sizeof long=4
[2022-10-04 01:03:37,542 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true
[2022-10-04 01:03:37,542 INFO L138 SettingsManager]: * sizeof POINTER=4
[2022-10-04 01:03:37,543 INFO L138 SettingsManager]: * Check division by zero=IGNORE
[2022-10-04 01:03:37,543 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE
[2022-10-04 01:03:37,543 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE
[2022-10-04 01:03:37,543 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE
[2022-10-04 01:03:37,543 INFO L138 SettingsManager]: * sizeof long double=12
[2022-10-04 01:03:37,543 INFO L138 SettingsManager]: * Check if freed pointer was valid=false
[2022-10-04 01:03:37,543 INFO L138 SettingsManager]: * Use constant arrays=true
[2022-10-04 01:03:37,543 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE
[2022-10-04 01:03:37,543 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults:
[2022-10-04 01:03:37,543 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements
[2022-10-04 01:03:37,544 INFO L138 SettingsManager]: * To the following directory=./dump/
[2022-10-04 01:03:37,544 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode
[2022-10-04 01:03:37,544 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000
[2022-10-04 01:03:37,544 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults:
[2022-10-04 01:03:37,544 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP
[2022-10-04 01:03:37,544 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles
[2022-10-04 01:03:37,544 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL
[2022-10-04 01:03:37,544 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in
[2022-10-04 01:03:37,544 INFO L138 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false
[2022-10-04 01:03:37,544 INFO L138 SettingsManager]: * Abstraction used for commutativity in POR=VARIABLES_GLOBAL
[2022-10-04 01:03:37,544 INFO L138 SettingsManager]: * Automaton type used in concurrency analysis=PARTIAL_ORDER_FA
[2022-10-04 01:03:37,545 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true
[2022-10-04 01:03:37,545 INFO L138 SettingsManager]: * CEGAR restart behaviour=ONE_CEGAR_PER_ERROR_LOCATION
[2022-10-04 01:03:37,545 INFO L138 SettingsManager]: * Partial Order Reduction in concurrent analysis=SLEEP_NEW_STATES
[2022-10-04 01:03:37,545 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode
[2022-10-04 01:03:37,545 INFO L138 SettingsManager]: * Independence relation used for POR in concurrent analysis=SYNTACTIC
WARNING: An illegal reflective access operation has occurred
WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int)
WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1
WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations
WARNING: All illegal access operations will be denied in a future release
[2022-10-04 01:03:37,742 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp
[2022-10-04 01:03:37,762 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized
[2022-10-04 01:03:37,764 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected.
[2022-10-04 01:03:37,765 INFO L271 PluginConnector]: Initializing Boogie PL CUP Parser...
[2022-10-04 01:03:37,766 INFO L275 PluginConnector]: Boogie PL CUP Parser initialized
[2022-10-04 01:03:37,767 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/boogie-benchmarks-from-svcomp-memsafety-concurrent/race-4_2-thread_local_vars.line1041.bpl
[2022-10-04 01:03:37,767 INFO L110 BoogieParser]: Parsing: '/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/boogie-benchmarks-from-svcomp-memsafety-concurrent/race-4_2-thread_local_vars.line1041.bpl'
[2022-10-04 01:03:37,821 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] #######################
[2022-10-04 01:03:37,822 INFO L131 ToolchainWalker]: Walking toolchain with 3 elements.
[2022-10-04 01:03:37,823 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor----------------------------
[2022-10-04 01:03:37,823 INFO L271 PluginConnector]: Initializing Boogie Preprocessor...
[2022-10-04 01:03:37,824 INFO L275 PluginConnector]: Boogie Preprocessor initialized
[2022-10-04 01:03:37,834 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "race-4_2-thread_local_vars.line1041.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.10 01:03:37" (1/1) ...
[2022-10-04 01:03:37,835 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "race-4_2-thread_local_vars.line1041.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.10 01:03:37" (1/1) ...
[2022-10-04 01:03:37,866 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "race-4_2-thread_local_vars.line1041.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.10 01:03:37" (1/1) ...
[2022-10-04 01:03:37,866 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "race-4_2-thread_local_vars.line1041.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.10 01:03:37" (1/1) ...
[2022-10-04 01:03:37,887 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "race-4_2-thread_local_vars.line1041.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.10 01:03:37" (1/1) ...
[2022-10-04 01:03:37,891 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "race-4_2-thread_local_vars.line1041.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.10 01:03:37" (1/1) ...
[2022-10-04 01:03:37,894 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "race-4_2-thread_local_vars.line1041.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.10 01:03:37" (1/1) ...
[2022-10-04 01:03:37,925 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor----------------------------
[2022-10-04 01:03:37,947 INFO L113 PluginConnector]: ------------------------RCFGBuilder----------------------------
[2022-10-04 01:03:37,947 INFO L271 PluginConnector]: Initializing RCFGBuilder...
[2022-10-04 01:03:37,948 INFO L275 PluginConnector]: RCFGBuilder initialized
[2022-10-04 01:03:37,953 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "race-4_2-thread_local_vars.line1041.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.10 01:03:37" (1/1) ...
[2022-10-04 01:03:37,962 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000
[2022-10-04 01:03:37,968 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3
[2022-10-04 01:03:37,992 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null)
[2022-10-04 01:03:38,040 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process
[2022-10-04 01:03:38,062 INFO L130 BoogieDeclarations]: Found specification of procedure thread_usb
[2022-10-04 01:03:38,062 INFO L138 BoogieDeclarations]: Found implementation of procedure thread_usb
[2022-10-04 01:03:38,062 INFO L130 BoogieDeclarations]: Found specification of procedure thread_ath9k
[2022-10-04 01:03:38,062 INFO L138 BoogieDeclarations]: Found implementation of procedure thread_ath9k
[2022-10-04 01:03:38,062 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start
[2022-10-04 01:03:38,062 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start
[2022-10-04 01:03:38,063 WARN L208 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to SingleStatement
[2022-10-04 01:03:38,341 INFO L234 CfgBuilder]: Building ICFG
[2022-10-04 01:03:38,342 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation
[2022-10-04 01:03:38,613 INFO L275 CfgBuilder]: Performing block encoding
[2022-10-04 01:03:38,623 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start)
[2022-10-04 01:03:38,623 INFO L299 CfgBuilder]: Removed 2 assume(true) statements.
[2022-10-04 01:03:38,625 INFO L202 PluginConnector]: Adding new model race-4_2-thread_local_vars.line1041.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 04.10 01:03:38 BoogieIcfgContainer
[2022-10-04 01:03:38,626 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder----------------------------
[2022-10-04 01:03:38,628 INFO L113 PluginConnector]: ------------------------TraceAbstraction----------------------------
[2022-10-04 01:03:38,628 INFO L271 PluginConnector]: Initializing TraceAbstraction...
[2022-10-04 01:03:38,636 INFO L275 PluginConnector]: TraceAbstraction initialized
[2022-10-04 01:03:38,637 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "race-4_2-thread_local_vars.line1041.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.10 01:03:37" (1/2) ...
[2022-10-04 01:03:38,637 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@14ad0cf3 and model type race-4_2-thread_local_vars.line1041.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 04.10 01:03:38, skipping insertion in model container
[2022-10-04 01:03:38,637 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "race-4_2-thread_local_vars.line1041.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 04.10 01:03:38" (2/2) ...
[2022-10-04 01:03:38,638 INFO L112 eAbstractionObserver]: Analyzing ICFG race-4_2-thread_local_vars.line1041.bpl
[2022-10-04 01:03:38,645 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program
[2022-10-04 01:03:38,651 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION
[2022-10-04 01:03:38,651 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations.
[2022-10-04 01:03:38,651 INFO L515 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances.
[2022-10-04 01:03:38,734 INFO L144 ThreadInstanceAdder]: Constructed 5 joinOtherThreadTransitions.
[2022-10-04 01:03:38,785 INFO L100 denceProviderFactory]: Independence Relation #1: [IndependenceType=SYNTACTIC, AbstractionType=VARIABLES_GLOBAL, UseConditional=<UNSUPPORTED>, UseSemiCommutativity=<UNSUPPORTED>, Solver=<NOT_USED>, SolverTimeout=<NOT_USED>]
[2022-10-04 01:03:38,786 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000
[2022-10-04 01:03:38,787 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3
[2022-10-04 01:03:38,788 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 (exit command is (exit), workingDir is null)
[2022-10-04 01:03:38,790 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 (2)] Waiting until timeout for monitored process
[2022-10-04 01:03:38,813 INFO L158 artialOrderCegarLoop]: Running PartialOrderCegarLoop with 1 independence relations.
[2022-10-04 01:03:38,818 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES ========
[2022-10-04 01:03:38,822 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=PARTIAL_ORDER_FA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@3e1200b1, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms]
[2022-10-04 01:03:38,823 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations.
[2022-10-04 01:03:38,878 INFO L805 garLoopResultBuilder]: Registering result SAFE for location ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (0 of 1 remaining)
[2022-10-04 01:03:38,881 INFO L444 BasicCegarLoop]: Path program histogram: []
[2022-10-04 01:03:38,900 INFO L307 ceAbstractionStarter]: Result for error location ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES was SAFE (1/5)
[2022-10-04 01:03:38,910 INFO L100 denceProviderFactory]: Independence Relation #1: [IndependenceType=SYNTACTIC, AbstractionType=VARIABLES_GLOBAL, UseConditional=<UNSUPPORTED>, UseSemiCommutativity=<UNSUPPORTED>, Solver=<NOT_USED>, SolverTimeout=<NOT_USED>]
[2022-10-04 01:03:38,910 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000
[2022-10-04 01:03:38,910 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3
[2022-10-04 01:03:38,912 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 (exit command is (exit), workingDir is null)
[2022-10-04 01:03:38,913 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 (3)] Waiting until timeout for monitored process
[2022-10-04 01:03:38,917 INFO L158 artialOrderCegarLoop]: Running PartialOrderCegarLoop with 1 independence relations.
[2022-10-04 01:03:38,918 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == thread_usbErr0ASSERT_VIOLATIONASSERT ========
[2022-10-04 01:03:38,918 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=PARTIAL_ORDER_FA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@3e1200b1, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms]
[2022-10-04 01:03:38,919 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations.
[2022-10-04 01:03:44,102 INFO L805 garLoopResultBuilder]: Registering result SAFE for location thread_usbErr0ASSERT_VIOLATIONASSERT (0 of 1 remaining)
[2022-10-04 01:03:44,104 INFO L444 BasicCegarLoop]: Path program histogram: []
[2022-10-04 01:03:44,107 INFO L307 ceAbstractionStarter]: Result for error location thread_usbErr0ASSERT_VIOLATIONASSERT was SAFE (2/5)
[2022-10-04 01:03:44,126 INFO L100 denceProviderFactory]: Independence Relation #1: [IndependenceType=SYNTACTIC, AbstractionType=VARIABLES_GLOBAL, UseConditional=<UNSUPPORTED>, UseSemiCommutativity=<UNSUPPORTED>, Solver=<NOT_USED>, SolverTimeout=<NOT_USED>]
[2022-10-04 01:03:44,126 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000
[2022-10-04 01:03:44,126 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3
[2022-10-04 01:03:44,157 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 (exit command is (exit), workingDir is null)
[2022-10-04 01:03:44,158 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 (4)] Waiting until timeout for monitored process
[2022-10-04 01:03:44,161 INFO L158 artialOrderCegarLoop]: Running PartialOrderCegarLoop with 1 independence relations.
[2022-10-04 01:03:44,161 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == thread_usbErr2INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES ========
[2022-10-04 01:03:44,162 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=PARTIAL_ORDER_FA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@3e1200b1, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms]
[2022-10-04 01:03:44,162 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations.
[2022-10-04 01:03:48,706 INFO L805 garLoopResultBuilder]: Registering result SAFE for location thread_usbErr2INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (0 of 1 remaining)
[2022-10-04 01:03:48,707 INFO L444 BasicCegarLoop]: Path program histogram: []
[2022-10-04 01:03:48,707 INFO L307 ceAbstractionStarter]: Result for error location thread_usbErr2INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES was SAFE (3/5)
[2022-10-04 01:03:48,723 INFO L100 denceProviderFactory]: Independence Relation #1: [IndependenceType=SYNTACTIC, AbstractionType=VARIABLES_GLOBAL, UseConditional=<UNSUPPORTED>, UseSemiCommutativity=<UNSUPPORTED>, Solver=<NOT_USED>, SolverTimeout=<NOT_USED>]
[2022-10-04 01:03:48,723 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000
[2022-10-04 01:03:48,723 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3
[2022-10-04 01:03:48,736 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 (exit command is (exit), workingDir is null)
[2022-10-04 01:03:48,739 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 (5)] Waiting until timeout for monitored process
[2022-10-04 01:03:48,750 INFO L158 artialOrderCegarLoop]: Running PartialOrderCegarLoop with 1 independence relations.
[2022-10-04 01:03:48,751 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == thread_usbErr0ASSERT_VIOLATIONASSERT ========
[2022-10-04 01:03:48,751 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=PARTIAL_ORDER_FA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@3e1200b1, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms]
[2022-10-04 01:03:48,751 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations.
[2022-10-04 01:03:50,234 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting thread_usbErr0ASSERT_VIOLATIONASSERT === [thread_usbErr0ASSERT_VIOLATIONASSERT] ===
[2022-10-04 01:03:50,237 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2022-10-04 01:03:50,237 INFO L85 PathProgramCache]: Analyzing trace with hash -117167137, now seen corresponding path program 1 times
[2022-10-04 01:03:50,243 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2022-10-04 01:03:50,243 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [815576035]
[2022-10-04 01:03:50,243 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2022-10-04 01:03:50,244 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2022-10-04 01:03:50,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2022-10-04 01:03:50,698 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked.
[2022-10-04 01:03:50,699 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2022-10-04 01:03:50,699 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [815576035]
[2022-10-04 01:03:50,699 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [815576035] provided 1 perfect and 0 imperfect interpolant sequences
[2022-10-04 01:03:50,699 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2022-10-04 01:03:50,699 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2022-10-04 01:03:50,700 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [199381809]
[2022-10-04 01:03:50,701 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2022-10-04 01:03:50,705 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 2 states
[2022-10-04 01:03:50,705 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2022-10-04 01:03:50,718 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants.
[2022-10-04 01:03:50,719 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2
[2022-10-04 01:03:50,720 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states.
[2022-10-04 01:03:50,721 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states
[2022-10-04 01:03:50,721 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 2 states, 2 states have (on average 103.5) internal successors, (207), 2 states have internal predecessors, (207), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2022-10-04 01:03:50,721 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states.
[2022-10-04 01:03:51,965 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states.
[2022-10-04 01:03:51,965 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0
[2022-10-04 01:03:51,966 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting thread_usbErr0ASSERT_VIOLATIONASSERT === [thread_usbErr0ASSERT_VIOLATIONASSERT] ===
[2022-10-04 01:03:51,966 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2022-10-04 01:03:51,966 INFO L85 PathProgramCache]: Analyzing trace with hash 1987355310, now seen corresponding path program 1 times
[2022-10-04 01:03:51,966 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2022-10-04 01:03:51,966 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1312356198]
[2022-10-04 01:03:51,966 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2022-10-04 01:03:51,967 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2022-10-04 01:03:52,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2022-10-04 01:03:52,228 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2022-10-04 01:03:52,228 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2022-10-04 01:03:52,228 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1312356198]
[2022-10-04 01:03:52,228 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1312356198] provided 1 perfect and 0 imperfect interpolant sequences
[2022-10-04 01:03:52,229 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2022-10-04 01:03:52,229 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5
[2022-10-04 01:03:52,230 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1967748043]
[2022-10-04 01:03:52,230 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2022-10-04 01:03:52,231 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states
[2022-10-04 01:03:52,232 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2022-10-04 01:03:52,233 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants.
[2022-10-04 01:03:52,233 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20
[2022-10-04 01:03:52,233 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states.
[2022-10-04 01:03:52,235 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states
[2022-10-04 01:03:52,236 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 42.2) internal successors, (211), 5 states have internal predecessors, (211), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2022-10-04 01:03:52,236 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states.
[2022-10-04 01:03:52,236 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states.
[2022-10-04 01:03:53,426 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states.
[2022-10-04 01:03:53,426 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states.
[2022-10-04 01:03:53,426 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1
[2022-10-04 01:03:53,427 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting thread_usbErr0ASSERT_VIOLATIONASSERT === [thread_usbErr0ASSERT_VIOLATIONASSERT] ===
[2022-10-04 01:03:53,427 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2022-10-04 01:03:53,427 INFO L85 PathProgramCache]: Analyzing trace with hash 2029772892, now seen corresponding path program 1 times
[2022-10-04 01:03:53,427 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2022-10-04 01:03:53,427 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1193936033]
[2022-10-04 01:03:53,427 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2022-10-04 01:03:53,427 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2022-10-04 01:03:53,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2022-10-04 01:03:53,511 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 44 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2022-10-04 01:03:53,511 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2022-10-04 01:03:53,511 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1193936033]
[2022-10-04 01:03:53,511 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1193936033] provided 1 perfect and 0 imperfect interpolant sequences
[2022-10-04 01:03:53,511 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2022-10-04 01:03:53,512 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2022-10-04 01:03:53,512 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [745777683]
[2022-10-04 01:03:53,512 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2022-10-04 01:03:53,512 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 3 states
[2022-10-04 01:03:53,512 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2022-10-04 01:03:53,513 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2022-10-04 01:03:53,513 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2022-10-04 01:03:53,513 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states.
[2022-10-04 01:03:53,513 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states
[2022-10-04 01:03:53,513 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 83.33333333333333) internal successors, (250), 3 states have internal predecessors, (250), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2022-10-04 01:03:53,514 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states.
[2022-10-04 01:03:53,514 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 7 states.
[2022-10-04 01:03:53,514 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states.
[2022-10-04 01:03:53,763 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states.
[2022-10-04 01:03:53,763 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states.
[2022-10-04 01:03:53,763 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2022-10-04 01:03:53,763 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2
[2022-10-04 01:03:53,764 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting thread_usbErr0ASSERT_VIOLATIONASSERT === [thread_usbErr0ASSERT_VIOLATIONASSERT] ===
[2022-10-04 01:03:53,764 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2022-10-04 01:03:53,764 INFO L85 PathProgramCache]: Analyzing trace with hash -996948338, now seen corresponding path program 1 times
[2022-10-04 01:03:53,764 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2022-10-04 01:03:53,764 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [312854468]
[2022-10-04 01:03:53,764 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2022-10-04 01:03:53,764 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2022-10-04 01:03:53,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2022-10-04 01:03:53,834 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked.
[2022-10-04 01:03:53,834 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2022-10-04 01:03:53,835 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [312854468]
[2022-10-04 01:03:53,835 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [312854468] provided 1 perfect and 0 imperfect interpolant sequences
[2022-10-04 01:03:53,835 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2022-10-04 01:03:53,835 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4
[2022-10-04 01:03:53,835 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [777544577]
[2022-10-04 01:03:53,835 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2022-10-04 01:03:53,835 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states
[2022-10-04 01:03:53,835 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2022-10-04 01:03:53,836 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2022-10-04 01:03:53,836 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2022-10-04 01:03:53,836 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states.
[2022-10-04 01:03:53,836 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states
[2022-10-04 01:03:53,836 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 52.0) internal successors, (208), 4 states have internal predecessors, (208), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2022-10-04 01:03:53,836 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states.
[2022-10-04 01:03:53,837 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 7 states.
[2022-10-04 01:03:53,837 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 3 states.
[2022-10-04 01:03:53,837 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states.
[2022-10-04 01:03:54,127 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states.
[2022-10-04 01:03:54,127 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states.
[2022-10-04 01:03:54,127 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2022-10-04 01:03:54,127 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states.
[2022-10-04 01:03:54,127 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3
[2022-10-04 01:03:54,128 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting thread_usbErr0ASSERT_VIOLATIONASSERT === [thread_usbErr0ASSERT_VIOLATIONASSERT] ===
[2022-10-04 01:03:54,128 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2022-10-04 01:03:54,128 INFO L85 PathProgramCache]: Analyzing trace with hash 1644636600, now seen corresponding path program 1 times
[2022-10-04 01:03:54,128 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2022-10-04 01:03:54,128 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1122884897]
[2022-10-04 01:03:54,128 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2022-10-04 01:03:54,128 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2022-10-04 01:03:54,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2022-10-04 01:03:54,444 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked.
[2022-10-04 01:03:54,444 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2022-10-04 01:03:54,444 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1122884897]
[2022-10-04 01:03:54,444 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1122884897] provided 1 perfect and 0 imperfect interpolant sequences
[2022-10-04 01:03:54,444 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2022-10-04 01:03:54,444 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10
[2022-10-04 01:03:54,444 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2120436083]
[2022-10-04 01:03:54,445 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2022-10-04 01:03:54,445 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 11 states
[2022-10-04 01:03:54,445 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2022-10-04 01:03:54,446 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants.
[2022-10-04 01:03:54,446 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=87, Unknown=0, NotChecked=0, Total=110
[2022-10-04 01:03:54,446 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states.
[2022-10-04 01:03:54,446 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states
[2022-10-04 01:03:54,447 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 11 states, 10 states have (on average 22.7) internal successors, (227), 11 states have internal predecessors, (227), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2022-10-04 01:03:54,447 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states.
[2022-10-04 01:03:54,447 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 7 states.
[2022-10-04 01:03:54,447 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 3 states.
[2022-10-04 01:03:54,447 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 4 states.
[2022-10-04 01:03:54,447 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states.
[2022-10-04 01:03:55,956 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states.
[2022-10-04 01:03:55,956 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states.
[2022-10-04 01:03:55,957 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2022-10-04 01:03:55,957 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states.
[2022-10-04 01:03:55,957 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states.
[2022-10-04 01:03:55,957 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4
[2022-10-04 01:03:55,957 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting thread_usbErr0ASSERT_VIOLATIONASSERT === [thread_usbErr0ASSERT_VIOLATIONASSERT] ===
[2022-10-04 01:03:55,957 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2022-10-04 01:03:55,958 INFO L85 PathProgramCache]: Analyzing trace with hash 2049447409, now seen corresponding path program 1 times
[2022-10-04 01:03:55,958 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2022-10-04 01:03:55,958 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1086606805]
[2022-10-04 01:03:55,964 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2022-10-04 01:03:55,964 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2022-10-04 01:03:56,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2022-10-04 01:03:56,067 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2022-10-04 01:03:56,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2022-10-04 01:03:56,257 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2022-10-04 01:03:56,257 INFO L359 BasicCegarLoop]: Counterexample is feasible
[2022-10-04 01:03:56,257 INFO L805 garLoopResultBuilder]: Registering result UNSAFE for location thread_usbErr0ASSERT_VIOLATIONASSERT (0 of 1 remaining)
[2022-10-04 01:03:56,257 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5
[2022-10-04 01:03:56,265 INFO L444 BasicCegarLoop]: Path program histogram: [1, 1, 1, 1, 1, 1]
[2022-10-04 01:03:56,265 INFO L307 ceAbstractionStarter]: Result for error location thread_usbErr0ASSERT_VIOLATIONASSERT was UNSAFE (4/5)
[2022-10-04 01:03:56,268 INFO L228 ceAbstractionStarter]: Analysis of concurrent program completed with 1 thread instances
[2022-10-04 01:03:56,268 INFO L178 ceAbstractionStarter]: Computing trace abstraction results
[2022-10-04 01:03:56,459 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,460 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,460 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,460 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,460 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,460 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,460 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,460 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,461 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,461 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,461 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,461 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,461 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,461 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,461 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,465 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,465 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,465 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,465 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,465 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,465 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,466 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,466 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,466 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,466 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,466 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,466 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,467 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,467 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,467 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,467 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,468 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,468 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,468 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,468 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,468 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,484 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,487 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,487 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,487 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,488 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,489 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,489 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,489 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,489 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,489 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,489 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,489 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,489 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,489 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,489 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,490 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,490 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,490 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,490 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,490 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,490 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,490 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,490 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,490 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,490 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,490 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,491 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,491 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,491 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,491 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,491 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,491 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,491 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,491 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,492 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,492 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,492 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,492 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,492 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,492 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,492 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,492 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,492 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,492 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,493 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,493 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,493 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,493 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,493 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,493 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,493 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,493 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,493 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,493 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,493 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,494 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,494 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,494 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,494 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,494 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,494 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,494 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,494 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,494 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,494 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,494 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,494 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,494 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,494 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,495 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,495 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,495 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,495 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,495 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,495 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,495 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,495 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,495 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,495 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,495 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,495 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,495 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,496 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,496 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,496 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,496 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,496 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,496 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,496 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,496 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,496 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,496 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,497 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,497 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,497 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,497 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,497 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,497 WARN L418 cessorBacktranslator]: Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
[2022-10-04 01:03:56,557 INFO L202 PluginConnector]: Adding new model race-4_2-thread_local_vars.line1041.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 04.10 01:03:56 BasicIcfg
[2022-10-04 01:03:56,557 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction----------------------------
[2022-10-04 01:03:56,558 INFO L158 Benchmark]: Toolchain (without parser) took 18735.33ms. Allocated memory was 186.6MB in the beginning and 6.7GB in the end (delta: 6.5GB). Free memory was 142.2MB in the beginning and 6.1GB in the end (delta: -5.9GB). Peak memory consumption was 549.5MB. Max. memory is 8.0GB.
[2022-10-04 01:03:56,558 INFO L158 Benchmark]: Boogie PL CUP Parser took 0.14ms. Allocated memory is still 186.6MB. Free memory is still 146.4MB. There was no memory consumed. Max. memory is 8.0GB.
[2022-10-04 01:03:56,558 INFO L158 Benchmark]: Boogie Preprocessor took 102.81ms. Allocated memory is still 186.6MB. Free memory was 142.1MB in the beginning and 138.6MB in the end (delta: 3.5MB). Peak memory consumption was 3.1MB. Max. memory is 8.0GB.
[2022-10-04 01:03:56,558 INFO L158 Benchmark]: RCFGBuilder took 678.46ms. Allocated memory is still 186.6MB. Free memory was 138.5MB in the beginning and 138.0MB in the end (delta: 579.5kB). Peak memory consumption was 12.2MB. Max. memory is 8.0GB.
[2022-10-04 01:03:56,558 INFO L158 Benchmark]: TraceAbstraction took 17929.44ms. Allocated memory was 186.6MB in the beginning and 6.7GB in the end (delta: 6.5GB). Free memory was 137.3MB in the beginning and 6.1GB in the end (delta: -5.9GB). Peak memory consumption was 544.7MB. Max. memory is 8.0GB.
[2022-10-04 01:03:56,566 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] #######################
--- Results ---
* Results from de.uni_freiburg.informatik.ultimate.core:
- StatisticsResult: Toolchain Benchmarks
Benchmark results are:
* Boogie PL CUP Parser took 0.14ms. Allocated memory is still 186.6MB. Free memory is still 146.4MB. There was no memory consumed. Max. memory is 8.0GB.
* Boogie Preprocessor took 102.81ms. Allocated memory is still 186.6MB. Free memory was 142.1MB in the beginning and 138.6MB in the end (delta: 3.5MB). Peak memory consumption was 3.1MB. Max. memory is 8.0GB.
* RCFGBuilder took 678.46ms. Allocated memory is still 186.6MB. Free memory was 138.5MB in the beginning and 138.0MB in the end (delta: 579.5kB). Peak memory consumption was 12.2MB. Max. memory is 8.0GB.
* TraceAbstraction took 17929.44ms. Allocated memory was 186.6MB in the beginning and 6.7GB in the end (delta: 6.5GB). Free memory was 137.3MB in the beginning and 6.1GB in the end (delta: -5.9GB). Peak memory consumption was 544.7MB. Max. memory is 8.0GB.
* Results from de.uni_freiburg.informatik.ultimate.boogie.preprocessor:
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
- GenericResult: Unfinished Backtranslation
Unfinished Backtranslation: Nested struct field access of VarList #Ultimate.allocOnStack_#res#1 : $Pointer$ not handled
* Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction:
- StatisticsResult: Independence relation #1 benchmarks
IndependenceRelationWithAbstraction.Independence Queries: [ total: 1, positive: 0, positive conditional: 0, positive unconditional: 0, negative: 1, negative conditional: 1, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , IndependenceRelationWithAbstraction.Statistics on underlying relation: ThreadSeparatingIndependenceRelation.Independence Queries: [ total: 1, positive: 0, positive conditional: 0, positive unconditional: 0, negative: 1, negative conditional: 1, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ThreadSeparatingIndependenceRelation.Statistics on underlying relation: CachedIndependenceRelation.Independence Queries: [ total: 0, positive: 0, positive conditional: 0, positive unconditional: 0, negative: 0, negative conditional: 0, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , CachedIndependenceRelation.Statistics on underlying relation: SyntacticIndependenceRelation.Independence Queries: [ total: 0, positive: 0, positive conditional: 0, positive unconditional: 0, negative: 0, negative conditional: 0, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , Cache Queries: [ total: 0, positive: 0, positive conditional: 0, positive unconditional: 0, negative: 0, negative conditional: 0, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , Statistics on independence cache: Total cache size (in pairs): 0, Positive cache size: 0, Positive conditional cache size: 0, Positive unconditional cache size: 0, Negative cache size: 0, Negative conditional cache size: 0, Negative unconditional cache size: 0, Independence queries for same thread: 1, Statistics for Abstraction:
- StatisticsResult: Independence relation #1 benchmarks
IndependenceRelationWithAbstraction.Independence Queries: [ total: 357358, positive: 336928, positive conditional: 336928, positive unconditional: 0, negative: 20430, negative conditional: 20430, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , IndependenceRelationWithAbstraction.Statistics on underlying relation: ThreadSeparatingIndependenceRelation.Independence Queries: [ total: 357358, positive: 336928, positive conditional: 336928, positive unconditional: 0, negative: 20430, negative conditional: 20430, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ThreadSeparatingIndependenceRelation.Statistics on underlying relation: CachedIndependenceRelation.Independence Queries: [ total: 337380, positive: 336928, positive conditional: 0, positive unconditional: 336928, negative: 452, negative conditional: 0, negative unconditional: 452, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , CachedIndependenceRelation.Statistics on underlying relation: SyntacticIndependenceRelation.Independence Queries: [ total: 12556, positive: 12538, positive conditional: 0, positive unconditional: 12538, negative: 18, negative conditional: 0, negative unconditional: 18, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , Cache Queries: [ total: 337380, positive: 324390, positive conditional: 0, positive unconditional: 324390, negative: 434, negative conditional: 0, negative unconditional: 434, unknown: 12556, unknown conditional: 0, unknown unconditional: 12556] , Statistics on independence cache: Total cache size (in pairs): 12556, Positive cache size: 12538, Positive conditional cache size: 0, Positive unconditional cache size: 12538, Negative cache size: 18, Negative conditional cache size: 0, Negative unconditional cache size: 18, Independence queries for same thread: 19978, Statistics for Abstraction:
- StatisticsResult: Independence relation #1 benchmarks
IndependenceRelationWithAbstraction.Independence Queries: [ total: 357358, positive: 336928, positive conditional: 336928, positive unconditional: 0, negative: 20430, negative conditional: 20430, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , IndependenceRelationWithAbstraction.Statistics on underlying relation: ThreadSeparatingIndependenceRelation.Independence Queries: [ total: 357358, positive: 336928, positive conditional: 336928, positive unconditional: 0, negative: 20430, negative conditional: 20430, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ThreadSeparatingIndependenceRelation.Statistics on underlying relation: CachedIndependenceRelation.Independence Queries: [ total: 337380, positive: 336928, positive conditional: 0, positive unconditional: 336928, negative: 452, negative conditional: 0, negative unconditional: 452, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , CachedIndependenceRelation.Statistics on underlying relation: SyntacticIndependenceRelation.Independence Queries: [ total: 12556, positive: 12538, positive conditional: 0, positive unconditional: 12538, negative: 18, negative conditional: 0, negative unconditional: 18, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , Cache Queries: [ total: 337380, positive: 324390, positive conditional: 0, positive unconditional: 324390, negative: 434, negative conditional: 0, negative unconditional: 434, unknown: 12556, unknown conditional: 0, unknown unconditional: 12556] , Statistics on independence cache: Total cache size (in pairs): 12556, Positive cache size: 12538, Positive conditional cache size: 0, Positive unconditional cache size: 12538, Negative cache size: 18, Negative conditional cache size: 0, Negative unconditional cache size: 18, Independence queries for same thread: 19978, Statistics for Abstraction:
- StatisticsResult: Independence relation #1 benchmarks
IndependenceRelationWithAbstraction.Independence Queries: [ total: 124195, positive: 115504, positive conditional: 115504, positive unconditional: 0, negative: 8691, negative conditional: 8691, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , IndependenceRelationWithAbstraction.Statistics on underlying relation: ThreadSeparatingIndependenceRelation.Independence Queries: [ total: 588841, positive: 546682, positive conditional: 546682, positive unconditional: 0, negative: 42159, negative conditional: 42159, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ThreadSeparatingIndependenceRelation.Statistics on underlying relation: CachedIndependenceRelation.Independence Queries: [ total: 546709, positive: 546682, positive conditional: 0, positive unconditional: 546682, negative: 27, negative conditional: 0, negative unconditional: 27, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , CachedIndependenceRelation.Statistics on underlying relation: SyntacticIndependenceRelation.Independence Queries: [ total: 11121, positive: 11114, positive conditional: 0, positive unconditional: 11114, negative: 7, negative conditional: 0, negative unconditional: 7, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , Cache Queries: [ total: 546709, positive: 535568, positive conditional: 0, positive unconditional: 535568, negative: 20, negative conditional: 0, negative unconditional: 20, unknown: 11121, unknown conditional: 0, unknown unconditional: 11121] , Statistics on independence cache: Total cache size (in pairs): 5704, Positive cache size: 5701, Positive conditional cache size: 0, Positive unconditional cache size: 5701, Negative cache size: 3, Negative conditional cache size: 0, Negative unconditional cache size: 3, Independence queries for same thread: 8688, Statistics for Abstraction:
- StatisticsResult: Independence relation #2 benchmarks
IndependenceRelationWithAbstraction.Independence Queries: [ total: 121299, positive: 112611, positive conditional: 112611, positive unconditional: 0, negative: 8688, negative conditional: 8688, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , IndependenceRelationWithAbstraction.Statistics on underlying relation: ThreadSeparatingIndependenceRelation.Independence Queries: [ total: 588841, positive: 546682, positive conditional: 546682, positive unconditional: 0, negative: 42159, negative conditional: 42159, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ThreadSeparatingIndependenceRelation.Statistics on underlying relation: CachedIndependenceRelation.Independence Queries: [ total: 546709, positive: 546682, positive conditional: 0, positive unconditional: 546682, negative: 27, negative conditional: 0, negative unconditional: 27, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , CachedIndependenceRelation.Statistics on underlying relation: SyntacticIndependenceRelation.Independence Queries: [ total: 11121, positive: 11114, positive conditional: 0, positive unconditional: 11114, negative: 7, negative conditional: 0, negative unconditional: 7, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , Cache Queries: [ total: 546709, positive: 535568, positive conditional: 0, positive unconditional: 535568, negative: 20, negative conditional: 0, negative unconditional: 20, unknown: 11121, unknown conditional: 0, unknown unconditional: 11121] , Statistics on independence cache: Total cache size (in pairs): 5778, Positive cache size: 5775, Positive conditional cache size: 0, Positive unconditional cache size: 5775, Negative cache size: 3, Negative conditional cache size: 0, Negative unconditional cache size: 3, Independence queries for same thread: 17373, Statistics for Abstraction:
- StatisticsResult: Independence relation #3 benchmarks
IndependenceRelationWithAbstraction.Independence Queries: [ total: 143694, positive: 133207, positive conditional: 133207, positive unconditional: 0, negative: 10487, negative conditional: 10487, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , IndependenceRelationWithAbstraction.Statistics on underlying relation: ThreadSeparatingIndependenceRelation.Independence Queries: [ total: 588841, positive: 546682, positive conditional: 546682, positive unconditional: 0, negative: 42159, negative conditional: 42159, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ThreadSeparatingIndependenceRelation.Statistics on underlying relation: CachedIndependenceRelation.Independence Queries: [ total: 546709, positive: 546682, positive conditional: 0, positive unconditional: 546682, negative: 27, negative conditional: 0, negative unconditional: 27, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , CachedIndependenceRelation.Statistics on underlying relation: SyntacticIndependenceRelation.Independence Queries: [ total: 11121, positive: 11114, positive conditional: 0, positive unconditional: 11114, negative: 7, negative conditional: 0, negative unconditional: 7, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , Cache Queries: [ total: 546709, positive: 535568, positive conditional: 0, positive unconditional: 535568, negative: 20, negative conditional: 0, negative unconditional: 20, unknown: 11121, unknown conditional: 0, unknown unconditional: 11121] , Statistics on independence cache: Total cache size (in pairs): 6024, Positive cache size: 6021, Positive conditional cache size: 0, Positive unconditional cache size: 6021, Negative cache size: 3, Negative conditional cache size: 0, Negative unconditional cache size: 3, Independence queries for same thread: 27857, Statistics for Abstraction:
- StatisticsResult: Independence relation #4 benchmarks
IndependenceRelationWithAbstraction.Independence Queries: [ total: 44693, positive: 41505, positive conditional: 41505, positive unconditional: 0, negative: 3188, negative conditional: 3188, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , IndependenceRelationWithAbstraction.Statistics on underlying relation: ThreadSeparatingIndependenceRelation.Independence Queries: [ total: 588841, positive: 546682, positive conditional: 546682, positive unconditional: 0, negative: 42159, negative conditional: 42159, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ThreadSeparatingIndependenceRelation.Statistics on underlying relation: CachedIndependenceRelation.Independence Queries: [ total: 546709, positive: 546682, positive conditional: 0, positive unconditional: 546682, negative: 27, negative conditional: 0, negative unconditional: 27, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , CachedIndependenceRelation.Statistics on underlying relation: SyntacticIndependenceRelation.Independence Queries: [ total: 11121, positive: 11114, positive conditional: 0, positive unconditional: 11114, negative: 7, negative conditional: 0, negative unconditional: 7, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , Cache Queries: [ total: 546709, positive: 535568, positive conditional: 0, positive unconditional: 535568, negative: 20, negative conditional: 0, negative unconditional: 20, unknown: 11121, unknown conditional: 0, unknown unconditional: 11121] , Statistics on independence cache: Total cache size (in pairs): 6183, Positive cache size: 6180, Positive conditional cache size: 0, Positive unconditional cache size: 6180, Negative cache size: 3, Negative conditional cache size: 0, Negative unconditional cache size: 3, Independence queries for same thread: 31045, Statistics for Abstraction:
- StatisticsResult: Independence relation #5 benchmarks
IndependenceRelationWithAbstraction.Independence Queries: [ total: 38363, positive: 35643, positive conditional: 35643, positive unconditional: 0, negative: 2720, negative conditional: 2720, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , IndependenceRelationWithAbstraction.Statistics on underlying relation: ThreadSeparatingIndependenceRelation.Independence Queries: [ total: 588841, positive: 546682, positive conditional: 546682, positive unconditional: 0, negative: 42159, negative conditional: 42159, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ThreadSeparatingIndependenceRelation.Statistics on underlying relation: CachedIndependenceRelation.Independence Queries: [ total: 546709, positive: 546682, positive conditional: 0, positive unconditional: 546682, negative: 27, negative conditional: 0, negative unconditional: 27, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , CachedIndependenceRelation.Statistics on underlying relation: SyntacticIndependenceRelation.Independence Queries: [ total: 11121, positive: 11114, positive conditional: 0, positive unconditional: 11114, negative: 7, negative conditional: 0, negative unconditional: 7, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , Cache Queries: [ total: 546709, positive: 535568, positive conditional: 0, positive unconditional: 535568, negative: 20, negative conditional: 0, negative unconditional: 20, unknown: 11121, unknown conditional: 0, unknown unconditional: 11121] , Statistics on independence cache: Total cache size (in pairs): 6501, Positive cache size: 6498, Positive conditional cache size: 0, Positive unconditional cache size: 6498, Negative cache size: 3, Negative conditional cache size: 0, Negative unconditional cache size: 3, Independence queries for same thread: 33765, Statistics for Abstraction:
- StatisticsResult: Independence relation #6 benchmarks
IndependenceRelationWithAbstraction.Independence Queries: [ total: 116597, positive: 108212, positive conditional: 108212, positive unconditional: 0, negative: 8385, negative conditional: 8385, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , IndependenceRelationWithAbstraction.Statistics on underlying relation: ThreadSeparatingIndependenceRelation.Independence Queries: [ total: 588841, positive: 546682, positive conditional: 546682, positive unconditional: 0, negative: 42159, negative conditional: 42159, negative unconditional: 0, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ThreadSeparatingIndependenceRelation.Statistics on underlying relation: CachedIndependenceRelation.Independence Queries: [ total: 546709, positive: 546682, positive conditional: 0, positive unconditional: 546682, negative: 27, negative conditional: 0, negative unconditional: 27, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , CachedIndependenceRelation.Statistics on underlying relation: SyntacticIndependenceRelation.Independence Queries: [ total: 11121, positive: 11114, positive conditional: 0, positive unconditional: 11114, negative: 7, negative conditional: 0, negative unconditional: 7, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , Cache Queries: [ total: 546709, positive: 535568, positive conditional: 0, positive unconditional: 535568, negative: 20, negative conditional: 0, negative unconditional: 20, unknown: 11121, unknown conditional: 0, unknown unconditional: 11121] , Statistics on independence cache: Total cache size (in pairs): 11121, Positive cache size: 11114, Positive conditional cache size: 0, Positive unconditional cache size: 11114, Negative cache size: 7, Negative conditional cache size: 0, Negative unconditional cache size: 7, Independence queries for same thread: 42132, Statistics for Abstraction:
- CounterExampleResult [Line: 1041]: assertion can be violated
assertion can be violated
We found a FailurePath:
[L1212] 0 assume { :begin_inline_ULTIMATE.init } true;
[L1213] 0 #NULL := { base: 0, offset: 0 };
VAL [#NULL!base=0, #NULL!offset=0]
[L1214] 0 assume 0 == #valid[0];
VAL [#NULL!base=0, #NULL!offset=0]
[L1215] 0 assume 0 < #StackHeapBarrier;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5]
[L1216] 0 assume { :begin_inline_#Ultimate.allocInit } true;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5]
[L1217] 0 #Ultimate.allocInit_~size#1, #Ultimate.allocInit_ptrBase#1 := 2, 1;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=1, #Ultimate.allocInit_~size#1=2]
[L1218] 0 assume 1 == #valid[#Ultimate.allocInit_ptrBase#1];
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=1, #Ultimate.allocInit_~size#1=2]
[L1219] 0 assume #length[#Ultimate.allocInit_ptrBase#1] == #Ultimate.allocInit_~size#1;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=1, #Ultimate.allocInit_~size#1=2]
[L1220] 0 assume { :end_inline_#Ultimate.allocInit } true;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=1, #Ultimate.allocInit_~size#1=2]
[L1221] 0 assume { :begin_inline_write~init~int } true;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=1, #Ultimate.allocInit_~size#1=2]
[L1222] 0 write~init~int_#value#1, write~init~int_#ptr#1, write~init~int_#sizeOfWrittenType#1 := 48, { base: 1, offset: 0 }, 1;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=1, #Ultimate.allocInit_~size#1=2, write~init~int_#ptr#1!base=1, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=1, write~init~int_#value#1=48]
[L1223] 0 assume #memory_int[write~init~int_#ptr#1] == write~init~int_#value#1;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=1, #Ultimate.allocInit_~size#1=2, write~init~int_#ptr#1!base=1, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=1, write~init~int_#value#1=48]
[L1224] 0 assume { :end_inline_write~init~int } true;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=1, #Ultimate.allocInit_~size#1=2, write~init~int_#ptr#1!base=1, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=1, write~init~int_#value#1=48]
[L1225] 0 assume { :begin_inline_write~init~int } true;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=1, #Ultimate.allocInit_~size#1=2, write~init~int_#ptr#1!base=1, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=1, write~init~int_#value#1=48]
[L1226] 0 write~init~int_#value#1, write~init~int_#ptr#1, write~init~int_#sizeOfWrittenType#1 := 0, { base: 1, offset: 1 }, 1;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=1, #Ultimate.allocInit_~size#1=2, write~init~int_#ptr#1!base=1, write~init~int_#ptr#1!offset=1, write~init~int_#sizeOfWrittenType#1=1, write~init~int_#value#1=0]
[L1227] 0 assume #memory_int[write~init~int_#ptr#1] == write~init~int_#value#1;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=1, #Ultimate.allocInit_~size#1=2, write~init~int_#ptr#1!base=1, write~init~int_#ptr#1!offset=1, write~init~int_#sizeOfWrittenType#1=1, write~init~int_#value#1=0]
[L1228] 0 assume { :end_inline_write~init~int } true;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=1, #Ultimate.allocInit_~size#1=2, write~init~int_#ptr#1!base=1, write~init~int_#ptr#1!offset=1, write~init~int_#sizeOfWrittenType#1=1, write~init~int_#value#1=0]
[L1229] 0 assume { :begin_inline_#Ultimate.allocInit } true;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=1, #Ultimate.allocInit_~size#1=2, write~init~int_#ptr#1!base=1, write~init~int_#ptr#1!offset=1, write~init~int_#sizeOfWrittenType#1=1, write~init~int_#value#1=0]
[L1230] 0 #Ultimate.allocInit_~size#1, #Ultimate.allocInit_ptrBase#1 := 29, 2;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=2, #Ultimate.allocInit_~size#1=29, write~init~int_#ptr#1!base=1, write~init~int_#ptr#1!offset=1, write~init~int_#sizeOfWrittenType#1=1, write~init~int_#value#1=0]
[L1231] 0 assume 1 == #valid[#Ultimate.allocInit_ptrBase#1];
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=2, #Ultimate.allocInit_~size#1=29, write~init~int_#ptr#1!base=1, write~init~int_#ptr#1!offset=1, write~init~int_#sizeOfWrittenType#1=1, write~init~int_#value#1=0]
[L1232] 0 assume #length[#Ultimate.allocInit_ptrBase#1] == #Ultimate.allocInit_~size#1;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=2, #Ultimate.allocInit_~size#1=29, write~init~int_#ptr#1!base=1, write~init~int_#ptr#1!offset=1, write~init~int_#sizeOfWrittenType#1=1, write~init~int_#value#1=0]
[L1233] 0 assume { :end_inline_#Ultimate.allocInit } true;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=2, #Ultimate.allocInit_~size#1=29, write~init~int_#ptr#1!base=1, write~init~int_#ptr#1!offset=1, write~init~int_#sizeOfWrittenType#1=1, write~init~int_#value#1=0]
[L1234] 0 ~#t1~0 := { base: 3, offset: 0 };
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=2, #Ultimate.allocInit_~size#1=29, write~init~int_#ptr#1!base=1, write~init~int_#ptr#1!offset=1, write~init~int_#sizeOfWrittenType#1=1, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0]
[L1235] 0 assume { :begin_inline_#Ultimate.allocInit } true;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=2, #Ultimate.allocInit_~size#1=29, write~init~int_#ptr#1!base=1, write~init~int_#ptr#1!offset=1, write~init~int_#sizeOfWrittenType#1=1, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0]
[L1236] 0 #Ultimate.allocInit_~size#1, #Ultimate.allocInit_ptrBase#1 := 4, 3;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=3, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=1, write~init~int_#ptr#1!offset=1, write~init~int_#sizeOfWrittenType#1=1, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0]
[L1237] 0 assume 1 == #valid[#Ultimate.allocInit_ptrBase#1];
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=3, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=1, write~init~int_#ptr#1!offset=1, write~init~int_#sizeOfWrittenType#1=1, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0]
[L1238] 0 assume #length[#Ultimate.allocInit_ptrBase#1] == #Ultimate.allocInit_~size#1;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=3, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=1, write~init~int_#ptr#1!offset=1, write~init~int_#sizeOfWrittenType#1=1, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0]
[L1239] 0 assume { :end_inline_#Ultimate.allocInit } true;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=3, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=1, write~init~int_#ptr#1!offset=1, write~init~int_#sizeOfWrittenType#1=1, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0]
[L1240] 0 assume { :begin_inline_write~init~int } true;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=3, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=1, write~init~int_#ptr#1!offset=1, write~init~int_#sizeOfWrittenType#1=1, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0]
[L1241] 0 write~init~int_#value#1, write~init~int_#ptr#1, write~init~int_#sizeOfWrittenType#1 := 0, ~#t1~0, 4;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=3, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=3, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0]
[L1242] 0 assume #memory_int[write~init~int_#ptr#1] == write~init~int_#value#1;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=3, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=3, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0]
[L1243] 0 assume { :end_inline_write~init~int } true;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=3, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=3, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0]
[L1244] 0 ~#t2~0 := { base: 4, offset: 0 };
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=3, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=3, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0]
[L1245] 0 assume { :begin_inline_#Ultimate.allocInit } true;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=3, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=3, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0]
[L1246] 0 #Ultimate.allocInit_~size#1, #Ultimate.allocInit_ptrBase#1 := 4, 4;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=4, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=3, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0]
[L1247] 0 assume 1 == #valid[#Ultimate.allocInit_ptrBase#1];
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=4, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=3, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0]
[L1248] 0 assume #length[#Ultimate.allocInit_ptrBase#1] == #Ultimate.allocInit_~size#1;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=4, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=3, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0]
[L1249] 0 assume { :end_inline_#Ultimate.allocInit } true;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=4, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=3, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0]
[L1250] 0 assume { :begin_inline_write~init~int } true;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=4, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=3, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0]
[L1251] 0 write~init~int_#value#1, write~init~int_#ptr#1, write~init~int_#sizeOfWrittenType#1 := 0, ~#t2~0, 4;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=4, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=4, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0]
[L1252] 0 assume #memory_int[write~init~int_#ptr#1] == write~init~int_#value#1;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=4, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=4, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0]
[L1253] 0 assume { :end_inline_write~init~int } true;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=4, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=4, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0]
[L1254] 0 ~#mutex~0 := { base: 5, offset: 0 };
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=4, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=4, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0]
[L1255] 0 assume { :begin_inline_#Ultimate.allocInit } true;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=4, #Ultimate.allocInit_~size#1=4, write~init~int_#ptr#1!base=4, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0]
[L1256] 0 #Ultimate.allocInit_~size#1, #Ultimate.allocInit_ptrBase#1 := 24, 5;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=4, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0]
[L1257] 0 assume 1 == #valid[#Ultimate.allocInit_ptrBase#1];
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=4, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0]
[L1258] 0 assume #length[#Ultimate.allocInit_ptrBase#1] == #Ultimate.allocInit_~size#1;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=4, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0]
[L1259] 0 assume { :end_inline_#Ultimate.allocInit } true;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=4, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0]
[L1260] 0 assume { :begin_inline_write~init~int } true;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=4, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0]
[L1261] 0 write~init~int_#value#1, write~init~int_#ptr#1, write~init~int_#sizeOfWrittenType#1 := 0, { base: ~#mutex~0!base, offset: ~#mutex~0!offset }, 4;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0]
[L1262] 0 assume #memory_int[write~init~int_#ptr#1] == write~init~int_#value#1;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0]
[L1263] 0 assume { :end_inline_write~init~int } true;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0]
[L1264] 0 assume { :begin_inline_write~init~int } true;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=0, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0]
[L1265] 0 write~init~int_#value#1, write~init~int_#ptr#1, write~init~int_#sizeOfWrittenType#1 := 0, { base: ~#mutex~0!base, offset: 4 + ~#mutex~0!offset }, 4;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=4, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0]
[L1266] 0 assume #memory_int[write~init~int_#ptr#1] == write~init~int_#value#1;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=4, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0]
[L1267] 0 assume { :end_inline_write~init~int } true;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=4, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0]
[L1268] 0 assume { :begin_inline_write~init~int } true;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=4, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0]
[L1269] 0 write~init~int_#value#1, write~init~int_#ptr#1, write~init~int_#sizeOfWrittenType#1 := 0, { base: ~#mutex~0!base, offset: 8 + ~#mutex~0!offset }, 4;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=8, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0]
[L1270] 0 assume #memory_int[write~init~int_#ptr#1] == write~init~int_#value#1;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=8, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0]
[L1271] 0 assume { :end_inline_write~init~int } true;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=8, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0]
[L1272] 0 assume { :begin_inline_write~init~int } true;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=8, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0]
[L1273] 0 write~init~int_#value#1, write~init~int_#ptr#1, write~init~int_#sizeOfWrittenType#1 := 0, { base: ~#mutex~0!base, offset: 12 + ~#mutex~0!offset }, 4;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=12, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0]
[L1274] 0 assume #memory_int[write~init~int_#ptr#1] == write~init~int_#value#1;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=12, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0]
[L1275] 0 assume { :end_inline_write~init~int } true;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=12, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0]
[L1276] 0 assume { :begin_inline_write~init~int } true;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=12, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0]
[L1277] 0 write~init~int_#value#1, write~init~int_#ptr#1, write~init~int_#sizeOfWrittenType#1 := 0, { base: ~#mutex~0!base, offset: 16 + ~#mutex~0!offset }, 4;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0]
[L1278] 0 assume #memory_int[write~init~int_#ptr#1] == write~init~int_#value#1;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0]
[L1279] 0 assume { :end_inline_write~init~int } true;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0]
[L1280] 0 ~pdev~0 := 0;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~pdev~0=0]
[L1281] 0 ~ldv_usb_state~0 := 0;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=0]
[L1283] 0 assume { :end_inline_ULTIMATE.init } true;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=0]
[L1284] 0 assume { :begin_inline_main } true;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=0]
[L1285] 0 havoc main_#res#1;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=0]
[L1286] 0 havoc main_#t~ret48#1;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=0]
[L1287] 0 assume { :begin_inline_module_init } true;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=0]
[L1288] 0 havoc module_init_#res#1;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=0]
[L1289] 0 havoc module_init_#t~nondet43#1, module_init_#t~pre44#1, module_init_#t~nondet45#1;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=0]
[L1290] 0 #pthreadsMutex[~#mutex~0] := 0;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=0]
[L1291] 0 ~pdev~0 := 1;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L1292] 0 assume { :begin_inline_ldv_assert } true;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L1293] 0 ldv_assert_#in~expression#1 := (if 1 == ~pdev~0 then 1 else 0);
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L1294] 0 havoc ldv_assert_~expression#1;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L1295] 0 ldv_assert_~expression#1 := ldv_assert_#in~expression#1;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L1296] COND FALSE 0 !(0 == ldv_assert_~expression#1)
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L1303] 0 assume { :end_inline_ldv_assert } true;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L1304] 0 assume -2147483648 <= module_init_#t~nondet43#1 && module_init_#t~nondet43#1 <= 2147483647;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~nondet43#1=1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L1305] COND TRUE 0 0 != module_init_#t~nondet43#1
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~nondet43#1=1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L1306] 0 havoc module_init_#t~nondet43#1;
VAL [#NULL!base=0, #NULL!offset=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L1307] 0 module_init_#t~pre44#1 := #pthreadsForks;
VAL [#NULL!base=0, #NULL!offset=0, #pthreadsForks=-2, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L1308] 0 #pthreadsForks := 1 + #pthreadsForks;
VAL [#NULL!base=0, #NULL!offset=0, #pthreadsForks=-1, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L1309] 0 write~int_old_#memory_$Pointer$#1, write~int_old_#memory_int#1 := #memory_$Pointer$, #memory_int;
VAL [#NULL!base=0, #NULL!offset=0, #pthreadsForks=-1, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L1310] 0 assume { :begin_inline_write~int } true;
VAL [#NULL!base=0, #NULL!offset=0, #pthreadsForks=-1, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L1311] 0 write~int_#value#1, write~int_#ptr#1, write~int_#sizeOfWrittenType#1 := module_init_#t~pre44#1, ~#t1~0, 4;
VAL [#NULL!base=0, #NULL!offset=0, #pthreadsForks=-1, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L1314] 0 assume 1 == #valid[write~int_#ptr#1!base];
VAL [#NULL!base=0, #NULL!offset=0, #pthreadsForks=-1, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L1315] 0 assume write~int_#sizeOfWrittenType#1 + write~int_#ptr#1!offset <= #length[write~int_#ptr#1!base] && 0 <= write~int_#ptr#1!offset;
VAL [#NULL!base=0, #NULL!offset=0, #pthreadsForks=-1, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L1316] 0 havoc #memory_$Pointer$, #memory_int;
VAL [#NULL!base=0, #NULL!offset=0, #pthreadsForks=-1, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L1317] 0 assume #memory_$Pointer$ == write~int_old_#memory_$Pointer$#1[write~int_#ptr#1 := #memory_$Pointer$[write~int_#ptr#1]] && #memory_int == write~int_old_#memory_int#1[write~int_#ptr#1 := write~int_#value#1];
VAL [#NULL!base=0, #NULL!offset=0, #pthreadsForks=-1, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L1318] 0 assume { :end_inline_write~int } true;
VAL [#NULL!base=0, #NULL!offset=0, #pthreadsForks=-1, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L1319] FORK 0 fork module_init_#t~pre44#1, 0, 0 thread_usb({ base: 0, offset: 0 });
VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=-1, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L922] 1 ~arg#1 := #in~arg#1;
VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=-1, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L923] 1 ~ldv_usb_state~0 := 0;
VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=-1, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L924] 1 havoc ~probe_ret~0#1;
VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=-1, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L928] COND FALSE 1 !(false)
VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=-1, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L931] 1 assume -2147483648 <= #t~nondet40#1 && #t~nondet40#1 <= 2147483647;
VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=-1, #StackHeapBarrier=5, #t~nondet40#1=0, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L932] 1 #t~switch41#1 := 0 == #t~nondet40#1;
VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=-1, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L933] COND TRUE 1 #t~switch41#1
VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=-1, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L934] COND TRUE 1 0 == ~ldv_usb_state~0
VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=-1, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L935] 1 assume { :begin_inline_ath_ahb_probe } true;
VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=-1, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L936] 1 havoc ath_ahb_probe_#res#1;
VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=-1, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L937] 1 havoc ath_ahb_probe_#t~ret39#1, ath_ahb_probe_~error~0#1;
VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=-1, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L938] 1 havoc ath_ahb_probe_~error~0#1;
VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=-1, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L939] 1 assume { :begin_inline_ieee80211_register_hw } true;
VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=-1, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L940] 1 havoc ieee80211_register_hw_#res#1;
VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=-1, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L941] 1 havoc ieee80211_register_hw_#t~nondet34#1, ieee80211_register_hw_#t~pre35#1, ieee80211_register_hw_#t~nondet36#1;
VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=-1, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L942] 1 assume -2147483648 <= ieee80211_register_hw_#t~nondet34#1 && ieee80211_register_hw_#t~nondet34#1 <= 2147483647;
VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=-1, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ieee80211_register_hw_#t~nondet34#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L943] COND TRUE 1 0 != ieee80211_register_hw_#t~nondet34#1
VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=-1, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ieee80211_register_hw_#t~nondet34#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L944] 1 havoc ieee80211_register_hw_#t~nondet34#1;
VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=-1, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L945] 1 ieee80211_register_hw_#t~pre35#1 := #pthreadsForks;
VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=-1, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ieee80211_register_hw_#t~pre35#1=-1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L946] 1 #pthreadsForks := 1 + #pthreadsForks;
VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ieee80211_register_hw_#t~pre35#1=-1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L947] 1 write~int_old_#memory_$Pointer$#1, write~int_old_#memory_int#1 := #memory_$Pointer$, #memory_int;
VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ieee80211_register_hw_#t~pre35#1=-1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L948] 1 assume { :begin_inline_write~int } true;
VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ieee80211_register_hw_#t~pre35#1=-1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L949] 1 write~int_#value#1, write~int_#ptr#1, write~int_#sizeOfWrittenType#1 := ieee80211_register_hw_#t~pre35#1, ~#t2~0, 4;
VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ieee80211_register_hw_#t~pre35#1=-1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L952] 1 assume 1 == #valid[write~int_#ptr#1!base];
VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ieee80211_register_hw_#t~pre35#1=-1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L953] 1 assume write~int_#sizeOfWrittenType#1 + write~int_#ptr#1!offset <= #length[write~int_#ptr#1!base] && 0 <= write~int_#ptr#1!offset;
VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ieee80211_register_hw_#t~pre35#1=-1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L954] 1 havoc #memory_$Pointer$, #memory_int;
VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ieee80211_register_hw_#t~pre35#1=-1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L955] 1 assume #memory_$Pointer$ == write~int_old_#memory_$Pointer$#1[write~int_#ptr#1 := #memory_$Pointer$[write~int_#ptr#1]] && #memory_int == write~int_old_#memory_int#1[write~int_#ptr#1 := write~int_#value#1];
VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ieee80211_register_hw_#t~pre35#1=-1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L956] 1 assume { :end_inline_write~int } true;
VAL [#in~arg#1!base=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ieee80211_register_hw_#t~pre35#1=-1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L957] FORK 1 fork ieee80211_register_hw_#t~pre35#1, 0 thread_ath9k({ base: 0, offset: 0 });
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ieee80211_register_hw_#t~pre35#1=-1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L958] 1 havoc ieee80211_register_hw_#t~pre35#1;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L959] 1 havoc ieee80211_register_hw_#t~nondet36#1;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L960] 1 ieee80211_register_hw_#res#1 := 0;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L968] 1 ath_ahb_probe_#t~ret39#1 := ieee80211_register_hw_#res#1;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ath_ahb_probe_#t~ret39#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L969] 1 assume { :end_inline_ieee80211_register_hw } true;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ath_ahb_probe_#t~ret39#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L970] 1 assume -2147483648 <= ath_ahb_probe_#t~ret39#1 && ath_ahb_probe_#t~ret39#1 <= 2147483647;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ath_ahb_probe_#t~ret39#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L971] 1 ath_ahb_probe_~error~0#1 := ath_ahb_probe_#t~ret39#1;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ath_ahb_probe_#t~ret39#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L972] 1 havoc ath_ahb_probe_#t~ret39#1;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L973] COND FALSE 1 !(0 != ath_ahb_probe_~error~0#1)
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L976] 1 ath_ahb_probe_#res#1 := 0;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L982] 1 #t~ret42#1 := ath_ahb_probe_#res#1;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~ret42#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L983] 1 assume { :end_inline_ath_ahb_probe } true;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~ret42#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L984] 1 assume -2147483648 <= #t~ret42#1 && #t~ret42#1 <= 2147483647;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~ret42#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1]
[L985] 1 ~probe_ret~0#1 := #t~ret42#1;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~ret42#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1, ~probe_ret~0#1=0]
[L986] 1 havoc #t~ret42#1;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1, ~probe_ret~0#1=0]
[L987] COND FALSE 1 !(0 != ~probe_ret~0#1)
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=0, ~pdev~0=1, ~probe_ret~0#1=0]
[L990] 1 ~ldv_usb_state~0 := 1;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=1, ~probe_ret~0#1=0]
[L991] 1 ~pdev~0 := 7;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L992] 1 assume { :begin_inline_ldv_assert } true;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L993] 1 ldv_assert_#in~expression#1 := (if 7 == ~pdev~0 then 1 else 0);
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L994] 1 havoc ldv_assert_~expression#1;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L995] 1 ldv_assert_~expression#1 := ldv_assert_#in~expression#1;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L996] COND FALSE 1 !(0 == ldv_assert_~expression#1)
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1003] 1 assume { :end_inline_ldv_assert } true;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=0, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1093] 1 havoc #t~nondet40#1;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1094] 1 havoc #t~switch41#1;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L928] COND FALSE 1 !(false)
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L931] 1 assume -2147483648 <= #t~nondet40#1 && #t~nondet40#1 <= 2147483647;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L932] 1 #t~switch41#1 := 0 == #t~nondet40#1;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=false, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L933] COND FALSE 1 !(#t~switch41#1)
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=false, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1007] 1 #t~switch41#1 := #t~switch41#1 || 1 == #t~nondet40#1;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1008] COND TRUE 1 #t~switch41#1
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1009] COND TRUE 1 1 == ~ldv_usb_state~0
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1010] 1 assume { :begin_inline_ath_ahb_disconnect } true;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1011] 1 assume { :begin_inline_ieee80211_deregister_hw } true;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1012] 1 havoc ieee80211_deregister_hw_#t~mem37#1, ieee80211_deregister_hw_#t~nondet38#1, ieee80211_deregister_hw_~#status~0#1;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1013] 1 #Ultimate.allocOnStack_old_#length#1, #Ultimate.allocOnStack_old_#valid#1 := #length, #valid;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1014] 1 assume { :begin_inline_#Ultimate.allocOnStack } true;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1015] 1 #Ultimate.allocOnStack_~size#1 := 4;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1016] 1 havoc #Ultimate.allocOnStack_#res#1;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1017] 1 havoc #valid, #length;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1018] 1 assume 0 == #Ultimate.allocOnStack_old_#valid#1[#Ultimate.allocOnStack_#res#1!base];
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1019] 1 assume #valid == #Ultimate.allocOnStack_old_#valid#1[#Ultimate.allocOnStack_#res#1!base := 1];
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1020] 1 assume 0 == #Ultimate.allocOnStack_#res#1!offset;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1021] 1 assume 0 != #Ultimate.allocOnStack_#res#1!base;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1022] 1 assume #StackHeapBarrier < #Ultimate.allocOnStack_#res#1!base;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1023] 1 assume #length == #Ultimate.allocOnStack_old_#length#1[#Ultimate.allocOnStack_#res#1!base := #Ultimate.allocOnStack_~size#1];
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1024] 1 ieee80211_deregister_hw_~#status~0#1 := #Ultimate.allocOnStack_#res#1;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1025] 1 assume { :end_inline_#Ultimate.allocOnStack } true;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1026] 1 assume { :begin_inline_read~int } true;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1027] 1 read~int_#ptr#1, read~int_#sizeOfReadType#1 := ~#t2~0, 4;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1030] 1 assume 1 == #valid[read~int_#ptr#1!base];
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1031] 1 assume read~int_#sizeOfReadType#1 + read~int_#ptr#1!offset <= #length[read~int_#ptr#1!base] && 0 <= read~int_#ptr#1!offset;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1032] 1 havoc read~int_#value#1;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1033] 1 assume read~int_#value#1 == #memory_int[read~int_#ptr#1];
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, read~int_#value#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1034] 1 ieee80211_deregister_hw_#t~mem37#1 := read~int_#value#1;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_#t~mem37#1=-1, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, read~int_#value#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1035] 1 assume { :end_inline_read~int } true;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_#t~mem37#1=-1, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#t~pre44#1=-2, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, read~int_#value#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1320] 0 havoc module_init_#t~pre44#1;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_#t~mem37#1=-1, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, read~int_#value#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1321] 0 havoc module_init_#t~nondet45#1;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_#t~mem37#1=-1, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, read~int_#value#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1322] 0 module_init_#res#1 := 0;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_#t~mem37#1=-1, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, read~int_#value#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1343] 0 main_#t~ret48#1 := module_init_#res#1;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_#t~mem37#1=-1, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, main_#t~ret48#1=0, module_init_#res#1=0, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, read~int_#value#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1344] 0 assume { :end_inline_module_init } true;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_#t~mem37#1=-1, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, main_#t~ret48#1=0, module_init_#res#1=0, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, read~int_#value#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1345] 0 assume -2147483648 <= main_#t~ret48#1 && main_#t~ret48#1 <= 2147483647;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_#t~mem37#1=-1, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, main_#t~ret48#1=0, module_init_#res#1=0, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, read~int_#value#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1346] COND FALSE 0 !(0 != main_#t~ret48#1)
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_#t~mem37#1=-1, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, main_#t~ret48#1=0, module_init_#res#1=0, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, read~int_#value#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1350] 0 havoc main_#t~ret48#1;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_#t~mem37#1=-1, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, read~int_#value#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1352] 0 assume { :begin_inline_module_exit } true;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_#t~mem37#1=-1, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, read~int_#value#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1353] 0 havoc module_exit_#t~mem46#1, module_exit_#t~nondet47#1, module_exit_~#status~1#1;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_#t~mem37#1=-1, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, read~int_#value#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1354] 0 #Ultimate.allocOnStack_old_#length#1, #Ultimate.allocOnStack_old_#valid#1 := #length, #valid;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_#t~mem37#1=-1, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, read~int_#value#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1355] 0 assume { :begin_inline_#Ultimate.allocOnStack } true;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_#t~mem37#1=-1, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, read~int_#value#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1356] 0 #Ultimate.allocOnStack_~size#1 := 4;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_#t~mem37#1=-1, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, read~int_#value#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1357] 0 havoc #Ultimate.allocOnStack_#res#1;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_#t~mem37#1=-1, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, read~int_#value#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1358] 0 havoc #valid, #length;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_#t~mem37#1=-1, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, read~int_#value#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1359] 0 assume 0 == #Ultimate.allocOnStack_old_#valid#1[#Ultimate.allocOnStack_#res#1!base];
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_#t~mem37#1=-1, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, read~int_#value#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1360] 0 assume #valid == #Ultimate.allocOnStack_old_#valid#1[#Ultimate.allocOnStack_#res#1!base := 1];
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_#t~mem37#1=-1, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, read~int_#value#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1361] 0 assume 0 == #Ultimate.allocOnStack_#res#1!offset;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_#t~mem37#1=-1, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, read~int_#value#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1362] 0 assume 0 != #Ultimate.allocOnStack_#res#1!base;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_#t~mem37#1=-1, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, read~int_#value#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1363] 0 assume #StackHeapBarrier < #Ultimate.allocOnStack_#res#1!base;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_#t~mem37#1=-1, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, read~int_#value#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1127] 2 ~arg#1 := #in~arg#1;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_#t~mem37#1=-1, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, read~int_#value#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1131] COND FALSE 2 !(false)
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_#t~mem37#1=-1, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, read~int_#value#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1134] 2 assume -2147483648 <= #t~nondet32#1 && #t~nondet32#1 <= 2147483647;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet32#1=2, #t~nondet40#1=1, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_#t~mem37#1=-1, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, read~int_#value#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1135] 2 #t~switch33#1 := 1 == #t~nondet32#1;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet32#1=2, #t~nondet40#1=1, #t~switch33#1=false, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_#t~mem37#1=-1, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, read~int_#value#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1136] COND FALSE 2 !(#t~switch33#1)
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet32#1=2, #t~nondet40#1=1, #t~switch33#1=false, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_#t~mem37#1=-1, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, read~int_#value#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1168] 2 #t~switch33#1 := #t~switch33#1 || 2 == #t~nondet32#1;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet32#1=2, #t~nondet40#1=1, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_#t~mem37#1=-1, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, read~int_#value#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1169] COND TRUE 2 #t~switch33#1
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #StackHeapBarrier=5, #t~nondet32#1=2, #t~nondet40#1=1, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_#t~mem37#1=-1, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, read~int_#value#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1177] 2 #res#1 := { base: 0, offset: 0 };
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #res#1!base=0, #res#1!offset=0, #StackHeapBarrier=5, #t~nondet32#1=2, #t~nondet40#1=1, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_#t~mem37#1=-1, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, read~int_#value#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1036] JOIN 2 join (if ieee80211_deregister_hw_#t~mem37#1 % 4294967296 % 4294967296 <= 2147483647 then ieee80211_deregister_hw_#t~mem37#1 % 4294967296 % 4294967296 else ieee80211_deregister_hw_#t~mem37#1 % 4294967296 % 4294967296 - 4294967296), 0 assign ieee80211_deregister_hw_#t~nondet38#1;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #res#1!base=0, #res#1!offset=0, #StackHeapBarrier=5, #t~nondet32#1=2, #t~nondet40#1=1, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_#t~mem37#1=-1, ieee80211_deregister_hw_#t~nondet38#1!base=0, ieee80211_deregister_hw_#t~nondet38#1!offset=0, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, read~int_#value#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1037] 1 write~$Pointer$_old_#memory_$Pointer$#1, write~$Pointer$_old_#memory_int#1 := #memory_$Pointer$, #memory_int;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #res#1!base=0, #res#1!offset=0, #StackHeapBarrier=5, #t~nondet32#1=2, #t~nondet40#1=1, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_#t~mem37#1=-1, ieee80211_deregister_hw_#t~nondet38#1!base=0, ieee80211_deregister_hw_#t~nondet38#1!offset=0, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, read~int_#value#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1038] 1 assume { :begin_inline_write~$Pointer$ } true;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #res#1!base=0, #res#1!offset=0, #StackHeapBarrier=5, #t~nondet32#1=2, #t~nondet40#1=1, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_#t~mem37#1=-1, ieee80211_deregister_hw_#t~nondet38#1!base=0, ieee80211_deregister_hw_#t~nondet38#1!offset=0, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, read~int_#value#1=-1, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1039] 1 write~$Pointer$_#value#1, write~$Pointer$_#ptr#1, write~$Pointer$_#sizeOfWrittenType#1 := ieee80211_deregister_hw_#t~nondet38#1, ieee80211_deregister_hw_~#status~0#1, 4;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #res#1!base=0, #res#1!offset=0, #StackHeapBarrier=5, #t~nondet32#1=2, #t~nondet40#1=1, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_#t~mem37#1=-1, ieee80211_deregister_hw_#t~nondet38#1!base=0, ieee80211_deregister_hw_#t~nondet38#1!offset=0, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, read~int_#value#1=-1, write~$Pointer$_#ptr#1.base=10, write~$Pointer$_#ptr#1.offset=0, write~$Pointer$_#sizeOfWrittenType#1=4, write~$Pointer$_#value#1!base=0, write~$Pointer$_#value#1!offset=0, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=4, write~int_#ptr#1!base=3, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
[L1041] 1 assert write~$Pointer$_#sizeOfWrittenType#1 + write~$Pointer$_#ptr#1!offset <= #length[write~$Pointer$_#ptr#1!base] && 0 <= write~$Pointer$_#ptr#1!offset;
VAL [#in~arg#1!base=0, #in~arg#1!base=0, #in~arg#1!offset=0, #in~arg#1!offset=0, #NULL!base=0, #NULL!offset=0, #pthreadsForks=0, #res#1!base=0, #res#1!offset=0, #StackHeapBarrier=5, #t~nondet32#1=2, #t~nondet40#1=1, #t~switch33#1=true, #t~switch41#1=true, #Ultimate.allocInit_ptrBase#1=5, #Ultimate.allocInit_~size#1=24, #Ultimate.allocOnStack_#res#1.base=10, #Ultimate.allocOnStack_#res#1.base=6, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_#res#1.offset=0, #Ultimate.allocOnStack_~size#1=4, #Ultimate.allocOnStack_~size#1=4, ath_ahb_probe_#res#1=0, ath_ahb_probe_~error~0#1=0, ieee80211_deregister_hw_#t~mem37#1=-1, ieee80211_deregister_hw_#t~nondet38#1!base=0, ieee80211_deregister_hw_#t~nondet38#1!offset=0, ieee80211_deregister_hw_~#status~0#1!base=10, ieee80211_deregister_hw_~#status~0#1!offset=0, ieee80211_register_hw_#res#1=0, ldv_assert_#in~expression#1=1, ldv_assert_#in~expression#1=1, ldv_assert_~expression#1=1, ldv_assert_~expression#1=1, module_init_#res#1=0, read~int_#ptr#1!base=4, read~int_#ptr#1!offset=0, read~int_#sizeOfReadType#1=4, read~int_#value#1=-1, write~$Pointer$_#ptr#1.base=10, write~$Pointer$_#ptr#1.offset=0, write~$Pointer$_#sizeOfWrittenType#1=4, write~$Pointer$_#value#1!base=0, write~$Pointer$_#value#1!offset=0, write~init~int_#ptr#1!base=5, write~init~int_#ptr#1!offset=16, write~init~int_#sizeOfWrittenType#1=4, write~init~int_#value#1=0, write~int_#ptr#1!base=3, write~int_#ptr#1!base=4, write~int_#ptr#1!offset=0, write~int_#ptr#1!offset=0, write~int_#sizeOfWrittenType#1=4, write~int_#sizeOfWrittenType#1=4, write~int_#value#1=-1, write~int_#value#1=-2, ~#mutex~0!base=5, ~#mutex~0!offset=0, ~#t1~0!base=3, ~#t1~0!offset=0, ~#t2~0!base=4, ~#t2~0!offset=0, ~arg#1!base=0, ~arg#1!base=0, ~arg#1!offset=0, ~arg#1!offset=0, ~ldv_usb_state~0=1, ~pdev~0=7, ~probe_ret~0#1=0]
- StatisticsResult: Ultimate Automizer benchmark data for thread instance sufficiency: ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES with 1 thread instances
CFG has 5 procedures, 520 locations, 5 error locations. Started 1 CEGAR loops. OverallTime: 0.1s, OverallIterations: 0, TraceHistogramMax: 0, PathProgramHistogramMax: 0, EmptinessCheckTime: 0.1s, AutomataDifference: 0.0s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: , PredicateUnifierStatistics: No data available, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=0occurred in iteration=0, InterpolantAutomatonStates: 0, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: No data available, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: No data available, ReuseStatistics: No data available
- StatisticsResult: Ultimate Automizer benchmark data for error location: thread_usbErr0ASSERT_VIOLATIONASSERT with 1 thread instances
CFG has 5 procedures, 520 locations, 5 error locations. Started 1 CEGAR loops. OverallTime: 5.2s, OverallIterations: 0, TraceHistogramMax: 0, PathProgramHistogramMax: 0, EmptinessCheckTime: 5.2s, AutomataDifference: 0.0s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: , PredicateUnifierStatistics: No data available, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=0occurred in iteration=0, InterpolantAutomatonStates: 0, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: No data available, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: No data available, ReuseStatistics: No data available
- StatisticsResult: Ultimate Automizer benchmark data for error location: thread_usbErr0ASSERT_VIOLATIONASSERT with 2 thread instances
CFG has 5 procedures, 520 locations, 5 error locations. Started 1 CEGAR loops. OverallTime: 7.5s, OverallIterations: 6, TraceHistogramMax: 0, PathProgramHistogramMax: 1, EmptinessCheckTime: 6.0s, AutomataDifference: 0.0s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: , PredicateUnifierStatistics: No data available, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=0occurred in iteration=0, InterpolantAutomatonStates: 31, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: No data available, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.1s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 0.7s InterpolantComputationTime, 1331 NumberOfCodeBlocks, 1331 NumberOfCodeBlocksAsserted, 6 NumberOfCheckSat, 1107 ConstructedInterpolants, 0 QuantifiedInterpolants, 1794 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 5 InterpolantComputations, 5 PerfectInterpolantSequences, 60/60 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available
- StatisticsResult: Ultimate Automizer benchmark data for thread instance sufficiency: thread_usbErr2INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES with 1 thread instances
CFG has 5 procedures, 520 locations, 5 error locations. Started 1 CEGAR loops. OverallTime: 4.6s, OverallIterations: 0, TraceHistogramMax: 0, PathProgramHistogramMax: 0, EmptinessCheckTime: 4.5s, AutomataDifference: 0.0s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: , PredicateUnifierStatistics: No data available, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=0occurred in iteration=0, InterpolantAutomatonStates: 0, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: No data available, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: No data available, ReuseStatistics: No data available
RESULT: Ultimate proved your program to be incorrect!
[2022-10-04 01:03:56,595 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 (5)] Ended with exit code 0
[2022-10-04 01:03:56,832 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 (4)] Forceful destruction successful, exit code 0
[2022-10-04 01:03:57,032 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 (3)] Forceful destruction successful, exit code 0
[2022-10-04 01:03:57,209 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 (2)] Forceful destruction successful, exit code 0
[2022-10-04 01:03:57,410 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Forceful destruction successful, exit code 0
Received shutdown request...