/root/.sdkman/candidates/java/current/bin/java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data -s ../benchexec/../../../trunk/examples/settings/gemcutter/NewStatesSleep.epf --traceabstraction.dfs.order.used.in.por LOOP_LOCKSTEP --traceabstraction.additional.conditional.commutativity.checking DFS --traceabstraction.criterion.for.conditional.commutativity.checking DEFAULT --traceabstraction.use.limited.checks.recommended.for.dfs true --traceabstraction.limit.for.limited.checks 50 -tc ../benchexec/../../../trunk/examples/toolchains/AutomizerBplInline.xml -i ../../../trunk/examples/concurrent/bpl/weaver-benchmarks/generated/popl20/min-max-inc-dec.wvr.bpl -------------------------------------------------------------------------------- This is Ultimate 0.2.4-wip.dk.conditional-comm-17da818-m [2024-05-04 07:35:49,304 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-05-04 07:35:49,369 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/../benchexec/../../../trunk/examples/settings/gemcutter/NewStatesSleep.epf [2024-05-04 07:35:49,374 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-05-04 07:35:49,374 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-05-04 07:35:49,398 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-05-04 07:35:49,398 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-05-04 07:35:49,398 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-05-04 07:35:49,399 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2024-05-04 07:35:49,402 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2024-05-04 07:35:49,402 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-05-04 07:35:49,402 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-05-04 07:35:49,402 INFO L153 SettingsManager]: * Use SBE=true [2024-05-04 07:35:49,403 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-05-04 07:35:49,404 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2024-05-04 07:35:49,404 INFO L153 SettingsManager]: * sizeof long=4 [2024-05-04 07:35:49,404 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-05-04 07:35:49,404 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-05-04 07:35:49,404 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-05-04 07:35:49,404 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2024-05-04 07:35:49,404 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2024-05-04 07:35:49,405 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2024-05-04 07:35:49,405 INFO L153 SettingsManager]: * sizeof long double=12 [2024-05-04 07:35:49,406 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-05-04 07:35:49,406 INFO L153 SettingsManager]: * Use constant arrays=true [2024-05-04 07:35:49,406 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-05-04 07:35:49,406 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-05-04 07:35:49,406 INFO L153 SettingsManager]: * To the following directory=./dump/ [2024-05-04 07:35:49,406 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-05-04 07:35:49,406 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2024-05-04 07:35:49,407 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-05-04 07:35:49,408 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2024-05-04 07:35:49,408 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2024-05-04 07:35:49,408 INFO L153 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2024-05-04 07:35:49,408 INFO L153 SettingsManager]: * Partial Order Reduction in concurrent analysis=SLEEP_NEW_STATES [2024-05-04 07:35:49,408 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2024-05-04 07:35:49,408 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-05-04 07:35:49,408 INFO L153 SettingsManager]: * Automaton type used in concurrency analysis=PARTIAL_ORDER_FA [2024-05-04 07:35:49,408 INFO L153 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2024-05-04 07:35:49,409 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: DFS Order used in POR -> LOOP_LOCKSTEP Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Additional conditional commutativity checking -> DFS Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Criterion for conditional commutativity checking -> DEFAULT Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: use limited checks (recommended for DFS) -> true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Limit for limited checks -> 50 [2024-05-04 07:35:49,614 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-05-04 07:35:49,636 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-05-04 07:35:49,638 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-05-04 07:35:49,639 INFO L270 PluginConnector]: Initializing Boogie PL CUP Parser... [2024-05-04 07:35:49,640 INFO L274 PluginConnector]: Boogie PL CUP Parser initialized [2024-05-04 07:35:49,641 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/../../../trunk/examples/concurrent/bpl/weaver-benchmarks/generated/popl20/min-max-inc-dec.wvr.bpl [2024-05-04 07:35:49,641 INFO L110 BoogieParser]: Parsing: '/storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/../../../trunk/examples/concurrent/bpl/weaver-benchmarks/generated/popl20/min-max-inc-dec.wvr.bpl' [2024-05-04 07:35:49,697 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-05-04 07:35:49,699 INFO L133 ToolchainWalker]: Walking toolchain with 4 elements. [2024-05-04 07:35:49,707 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-05-04 07:35:49,707 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-05-04 07:35:49,708 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-05-04 07:35:49,718 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "min-max-inc-dec.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.05 07:35:49" (1/1) ... [2024-05-04 07:35:49,725 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "min-max-inc-dec.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.05 07:35:49" (1/1) ... [2024-05-04 07:35:49,731 INFO L138 Inliner]: procedures = 6, calls = 5, calls flagged for inlining = 0, calls inlined = 0, statements flattened = 0 [2024-05-04 07:35:49,732 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-05-04 07:35:49,734 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-05-04 07:35:49,734 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-05-04 07:35:49,734 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-05-04 07:35:49,740 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "min-max-inc-dec.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.05 07:35:49" (1/1) ... [2024-05-04 07:35:49,741 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "min-max-inc-dec.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.05 07:35:49" (1/1) ... [2024-05-04 07:35:49,741 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "min-max-inc-dec.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.05 07:35:49" (1/1) ... [2024-05-04 07:35:49,748 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "min-max-inc-dec.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.05 07:35:49" (1/1) ... [2024-05-04 07:35:49,758 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "min-max-inc-dec.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.05 07:35:49" (1/1) ... [2024-05-04 07:35:49,760 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "min-max-inc-dec.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.05 07:35:49" (1/1) ... [2024-05-04 07:35:49,761 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "min-max-inc-dec.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.05 07:35:49" (1/1) ... [2024-05-04 07:35:49,761 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "min-max-inc-dec.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.05 07:35:49" (1/1) ... [2024-05-04 07:35:49,762 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-05-04 07:35:49,763 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-05-04 07:35:49,763 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-05-04 07:35:49,763 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-05-04 07:35:49,764 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "min-max-inc-dec.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.05 07:35:49" (1/1) ... [2024-05-04 07:35:49,771 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2024-05-04 07:35:49,779 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-04 07:35:49,797 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2024-05-04 07:35:49,805 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2024-05-04 07:35:49,836 INFO L124 BoogieDeclarations]: Specification and implementation of procedure thread1 given in one single declaration [2024-05-04 07:35:49,836 INFO L130 BoogieDeclarations]: Found specification of procedure thread1 [2024-05-04 07:35:49,836 INFO L138 BoogieDeclarations]: Found implementation of procedure thread1 [2024-05-04 07:35:49,837 INFO L124 BoogieDeclarations]: Specification and implementation of procedure thread2 given in one single declaration [2024-05-04 07:35:49,837 INFO L130 BoogieDeclarations]: Found specification of procedure thread2 [2024-05-04 07:35:49,837 INFO L138 BoogieDeclarations]: Found implementation of procedure thread2 [2024-05-04 07:35:49,837 INFO L124 BoogieDeclarations]: Specification and implementation of procedure ULTIMATE.start given in one single declaration [2024-05-04 07:35:49,837 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-05-04 07:35:49,837 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-05-04 07:35:49,837 INFO L124 BoogieDeclarations]: Specification and implementation of procedure thread3 given in one single declaration [2024-05-04 07:35:49,837 INFO L130 BoogieDeclarations]: Found specification of procedure thread3 [2024-05-04 07:35:49,837 INFO L138 BoogieDeclarations]: Found implementation of procedure thread3 [2024-05-04 07:35:49,837 INFO L124 BoogieDeclarations]: Specification and implementation of procedure thread4 given in one single declaration [2024-05-04 07:35:49,837 INFO L130 BoogieDeclarations]: Found specification of procedure thread4 [2024-05-04 07:35:49,837 INFO L138 BoogieDeclarations]: Found implementation of procedure thread4 [2024-05-04 07:35:49,838 INFO L124 BoogieDeclarations]: Specification and implementation of procedure thread5 given in one single declaration [2024-05-04 07:35:49,838 INFO L130 BoogieDeclarations]: Found specification of procedure thread5 [2024-05-04 07:35:49,838 INFO L138 BoogieDeclarations]: Found implementation of procedure thread5 [2024-05-04 07:35:49,838 WARN L213 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to OneNontrivialStatement [2024-05-04 07:35:49,878 INFO L241 CfgBuilder]: Building ICFG [2024-05-04 07:35:49,880 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2024-05-04 07:35:50,023 INFO L282 CfgBuilder]: Performing block encoding [2024-05-04 07:35:50,037 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-05-04 07:35:50,038 INFO L309 CfgBuilder]: Removed 0 assume(true) statements. [2024-05-04 07:35:50,039 INFO L201 PluginConnector]: Adding new model min-max-inc-dec.wvr.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 04.05 07:35:50 BoogieIcfgContainer [2024-05-04 07:35:50,039 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-05-04 07:35:50,044 INFO L112 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2024-05-04 07:35:50,044 INFO L270 PluginConnector]: Initializing TraceAbstraction... [2024-05-04 07:35:50,047 INFO L274 PluginConnector]: TraceAbstraction initialized [2024-05-04 07:35:50,048 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "min-max-inc-dec.wvr.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.05 07:35:49" (1/2) ... [2024-05-04 07:35:50,048 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@43dc354d and model type min-max-inc-dec.wvr.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 04.05 07:35:50, skipping insertion in model container [2024-05-04 07:35:50,049 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "min-max-inc-dec.wvr.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 04.05 07:35:50" (2/2) ... [2024-05-04 07:35:50,051 INFO L112 eAbstractionObserver]: Analyzing ICFG min-max-inc-dec.wvr.bpl [2024-05-04 07:35:50,058 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2024-05-04 07:35:50,065 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2024-05-04 07:35:50,065 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2024-05-04 07:35:50,066 INFO L514 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2024-05-04 07:35:50,139 INFO L144 ThreadInstanceAdder]: Constructed 5 joinOtherThreadTransitions. [2024-05-04 07:35:50,173 INFO L100 denceProviderFactory]: Independence Relation #1: [IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=true, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2024-05-04 07:35:50,174 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 [2024-05-04 07:35:50,174 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-04 07:35:50,177 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 (exit command is (exit), workingDir is null) [2024-05-04 07:35:50,201 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 (2)] Waiting until timeout for monitored process [2024-05-04 07:35:50,221 INFO L188 artialOrderCegarLoop]: Running PartialOrderCegarLoop with 1 independence relations. [2024-05-04 07:35:50,240 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-04 07:35:50,242 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2024-05-04 07:35:50,252 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=PARTIAL_ORDER_FA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopHeads, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@510c1c89, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms], mConComChecker=DFS, mConComCheckerCriterion=DEFAULT, mConComCheckerLimitedChecksCriterion=true, mConComCheckerCriterionLimit=50, mConComCheckerRandomProb=100, mConComCheckerRandomSeed=123, mConComCheckerConditionCriterion=false [2024-05-04 07:35:50,252 INFO L358 AbstractCegarLoop]: Starting to check reachability of 6 error locations. [2024-05-04 07:35:50,306 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 3 more)] === [2024-05-04 07:35:50,307 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-04 07:35:50,307 INFO L85 PathProgramCache]: Analyzing trace with hash -563538088, now seen corresponding path program 1 times [2024-05-04 07:35:50,314 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-04 07:35:50,314 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [641971044] [2024-05-04 07:35:50,314 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:35:50,314 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:35:50,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:35:50,558 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-05-04 07:35:50,559 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-04 07:35:50,559 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [641971044] [2024-05-04 07:35:50,559 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [641971044] provided 1 perfect and 0 imperfect interpolant sequences [2024-05-04 07:35:50,560 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-05-04 07:35:50,560 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-05-04 07:35:50,561 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [912153991] [2024-05-04 07:35:50,561 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-05-04 07:35:50,564 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-05-04 07:35:50,564 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-04 07:35:50,581 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-05-04 07:35:50,582 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-05-04 07:35:50,582 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-04 07:35:50,583 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-04 07:35:50,584 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 5.4) internal successors, (27), 5 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-04 07:35:50,584 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-04 07:35:51,093 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:35:51,093 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:35:51,173 INFO L85 PathProgramCache]: Analyzing trace with hash -439467170, now seen corresponding path program 1 times [2024-05-04 07:35:51,174 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:35:51,174 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:35:51,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:35:51,252 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-04 07:35:51,252 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:35:51,253 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:35:51,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:35:51,306 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-04 07:35:51,307 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-05-04 07:35:51,307 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-05-04 07:35:51,616 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:35:51,617 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 60 treesize of output 52 [2024-05-04 07:35:51,699 INFO L85 PathProgramCache]: Analyzing trace with hash -1091384554, now seen corresponding path program 1 times [2024-05-04 07:35:51,700 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:35:51,700 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:35:51,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:35:51,782 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:35:51,782 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:35:51,782 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:35:51,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:35:51,840 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:35:51,962 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:35:51,962 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 44 treesize of output 38 [2024-05-04 07:35:52,022 INFO L85 PathProgramCache]: Analyzing trace with hash -832419688, now seen corresponding path program 1 times [2024-05-04 07:35:52,022 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:35:52,022 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:35:52,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:35:52,070 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-05-04 07:35:52,070 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:35:52,070 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:35:52,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:35:52,104 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-05-04 07:35:52,256 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:35:52,257 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 60 treesize of output 52 [2024-05-04 07:35:52,315 INFO L85 PathProgramCache]: Analyzing trace with hash -35115144, now seen corresponding path program 1 times [2024-05-04 07:35:52,315 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:35:52,316 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:35:52,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:35:52,348 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-05-04 07:35:52,349 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:35:52,349 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:35:52,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:35:52,382 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-05-04 07:35:52,493 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:35:52,493 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:35:52,556 INFO L85 PathProgramCache]: Analyzing trace with hash -1966514822, now seen corresponding path program 1 times [2024-05-04 07:35:52,557 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:35:52,557 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:35:52,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:35:52,582 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-05-04 07:35:52,583 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:35:52,583 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:35:52,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:35:52,601 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-05-04 07:35:52,731 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:35:52,731 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 24 [2024-05-04 07:35:52,783 INFO L85 PathProgramCache]: Analyzing trace with hash 1752217120, now seen corresponding path program 1 times [2024-05-04 07:35:52,783 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:35:52,784 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:35:52,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:35:52,816 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:35:52,816 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:35:52,816 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:35:52,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:35:52,846 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:35:52,975 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:35:52,975 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 24 [2024-05-04 07:35:53,014 INFO L85 PathProgramCache]: Analyzing trace with hash -1061862638, now seen corresponding path program 2 times [2024-05-04 07:35:53,015 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:35:53,015 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:35:53,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:35:53,042 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:35:53,042 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:35:53,043 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:35:53,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:35:53,063 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:35:53,176 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:35:53,176 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:35:53,260 INFO L85 PathProgramCache]: Analyzing trace with hash 1441551746, now seen corresponding path program 1 times [2024-05-04 07:35:53,260 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:35:53,261 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:35:53,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:35:53,282 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:35:53,283 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:35:53,285 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:35:53,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:35:53,309 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:35:53,408 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:35:53,408 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 24 [2024-05-04 07:35:55,473 INFO L85 PathProgramCache]: Analyzing trace with hash -34254092, now seen corresponding path program 2 times [2024-05-04 07:35:55,473 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:35:55,473 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:35:55,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:35:55,501 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:35:55,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:35:55,502 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:35:55,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:35:55,538 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:35:55,648 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:35:55,648 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 44 treesize of output 38 [2024-05-04 07:35:55,713 INFO L85 PathProgramCache]: Analyzing trace with hash -1061831886, now seen corresponding path program 1 times [2024-05-04 07:35:55,713 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:35:55,713 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:35:55,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:35:55,744 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:35:55,744 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:35:55,744 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:35:55,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:35:55,766 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:35:55,876 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:35:55,877 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 60 treesize of output 52 [2024-05-04 07:35:55,940 INFO L85 PathProgramCache]: Analyzing trace with hash 1781777556, now seen corresponding path program 2 times [2024-05-04 07:35:55,941 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:35:55,941 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:35:55,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:35:55,963 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-04 07:35:55,964 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:35:55,964 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:35:55,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:35:55,998 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-04 07:35:56,101 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:35:56,102 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:35:56,160 INFO L85 PathProgramCache]: Analyzing trace with hash -351868020, now seen corresponding path program 3 times [2024-05-04 07:35:56,160 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:35:56,160 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:35:56,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:35:56,188 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:35:56,189 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:35:56,189 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:35:56,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:35:56,211 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:35:56,314 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:35:56,315 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 60 treesize of output 52 [2024-05-04 07:35:56,395 INFO L85 PathProgramCache]: Analyzing trace with hash 1976993381, now seen corresponding path program 4 times [2024-05-04 07:35:56,396 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:35:56,396 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:35:56,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:35:56,421 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:35:56,422 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:35:56,422 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:35:56,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:35:56,450 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:35:56,577 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:35:56,577 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:35:58,632 INFO L85 PathProgramCache]: Analyzing trace with hash -565539929, now seen corresponding path program 5 times [2024-05-04 07:35:58,632 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:35:58,632 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:35:58,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:35:58,654 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:35:58,654 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:35:58,654 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:35:58,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:35:58,674 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:35:58,781 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:35:58,781 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 24 [2024-05-04 07:36:00,823 INFO L85 PathProgramCache]: Analyzing trace with hash -565539929, now seen corresponding path program 6 times [2024-05-04 07:36:00,823 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:00,824 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:00,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:00,843 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:00,843 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:00,843 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:00,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:00,861 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:00,962 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:00,962 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 44 treesize of output 38 [2024-05-04 07:36:01,012 INFO L85 PathProgramCache]: Analyzing trace with hash 1162319158, now seen corresponding path program 7 times [2024-05-04 07:36:01,012 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:01,012 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:01,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:01,032 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-04 07:36:01,033 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:01,033 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:01,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:01,054 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-04 07:36:01,157 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:01,157 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 44 treesize of output 38 [2024-05-04 07:36:01,227 INFO L85 PathProgramCache]: Analyzing trace with hash -351862736, now seen corresponding path program 8 times [2024-05-04 07:36:01,227 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:01,228 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:01,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:01,278 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:01,279 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:01,279 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:01,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:01,296 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:01,394 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:01,394 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 24 [2024-05-04 07:36:01,432 INFO L85 PathProgramCache]: Analyzing trace with hash -599470503, now seen corresponding path program 9 times [2024-05-04 07:36:01,432 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:01,432 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:01,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:01,448 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-04 07:36:01,448 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:01,448 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:01,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:01,463 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-04 07:36:01,553 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:01,553 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 44 treesize of output 38 [2024-05-04 07:36:01,596 INFO L85 PathProgramCache]: Analyzing trace with hash -1403716298, now seen corresponding path program 10 times [2024-05-04 07:36:01,596 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:01,597 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:01,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:01,614 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-04 07:36:01,614 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:01,614 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:01,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:01,631 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-04 07:36:01,724 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:01,725 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:01,769 INFO L85 PathProgramCache]: Analyzing trace with hash -362710508, now seen corresponding path program 11 times [2024-05-04 07:36:01,769 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:01,769 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:01,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:01,786 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:01,786 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:01,786 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:01,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:01,805 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:01,899 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:01,899 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 44 treesize of output 38 [2024-05-04 07:36:01,951 INFO L85 PathProgramCache]: Analyzing trace with hash -1403727842, now seen corresponding path program 12 times [2024-05-04 07:36:01,952 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:01,952 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:01,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:01,967 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-04 07:36:01,968 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:01,968 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:01,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:02,017 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-04 07:36:02,118 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:02,119 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 44 treesize of output 38 [2024-05-04 07:36:02,170 INFO L85 PathProgramCache]: Analyzing trace with hash 23990200, now seen corresponding path program 1 times [2024-05-04 07:36:02,170 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:02,174 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:02,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:02,188 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:36:02,188 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:02,188 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:02,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:02,203 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:36:02,302 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:02,302 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 60 treesize of output 52 [2024-05-04 07:36:02,360 INFO L85 PathProgramCache]: Analyzing trace with hash -1966453318, now seen corresponding path program 1 times [2024-05-04 07:36:02,360 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:02,360 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:02,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:02,375 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-05-04 07:36:02,375 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:02,375 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:02,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:02,385 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-05-04 07:36:02,486 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:02,487 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 60 treesize of output 52 [2024-05-04 07:36:02,536 INFO L85 PathProgramCache]: Analyzing trace with hash -830419306, now seen corresponding path program 1 times [2024-05-04 07:36:02,537 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:02,537 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:02,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:02,550 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-05-04 07:36:02,550 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:02,550 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:02,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:02,563 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-05-04 07:36:02,664 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:02,664 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 60 treesize of output 52 [2024-05-04 07:36:02,713 INFO L85 PathProgramCache]: Analyzing trace with hash -2003096552, now seen corresponding path program 1 times [2024-05-04 07:36:02,713 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:02,714 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:02,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:02,726 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-05-04 07:36:02,727 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:02,727 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:02,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:02,738 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-05-04 07:36:02,859 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:02,859 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 44 treesize of output 38 [2024-05-04 07:36:02,920 INFO L85 PathProgramCache]: Analyzing trace with hash -114468286, now seen corresponding path program 1 times [2024-05-04 07:36:02,920 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:02,920 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:02,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:02,935 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:36:02,935 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:02,935 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:02,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:02,948 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:36:03,040 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:03,041 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 24 [2024-05-04 07:36:03,081 INFO L85 PathProgramCache]: Analyzing trace with hash 53512116, now seen corresponding path program 2 times [2024-05-04 07:36:03,081 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:03,081 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:03,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:03,094 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-05-04 07:36:03,095 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:03,095 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:03,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:03,111 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-05-04 07:36:03,205 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:03,207 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 24 [2024-05-04 07:36:03,247 INFO L85 PathProgramCache]: Analyzing trace with hash 1658430752, now seen corresponding path program 1 times [2024-05-04 07:36:03,247 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:03,247 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:03,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:03,261 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-05-04 07:36:03,261 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:03,261 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:03,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:03,274 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-05-04 07:36:03,371 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:03,371 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 24 [2024-05-04 07:36:03,413 INFO L85 PathProgramCache]: Analyzing trace with hash -829558254, now seen corresponding path program 2 times [2024-05-04 07:36:03,414 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:03,414 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:03,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:03,433 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-05-04 07:36:03,433 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:03,433 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:03,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:03,455 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-05-04 07:36:03,552 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:03,552 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 60 treesize of output 52 [2024-05-04 07:36:03,634 INFO L85 PathProgramCache]: Analyzing trace with hash 611292, now seen corresponding path program 1 times [2024-05-04 07:36:03,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:03,634 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:03,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:03,653 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:03,653 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:03,653 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:03,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:03,669 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:03,758 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:03,758 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 60 treesize of output 52 [2024-05-04 07:36:03,801 INFO L85 PathProgramCache]: Analyzing trace with hash -84915490, now seen corresponding path program 2 times [2024-05-04 07:36:03,801 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:03,801 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:03,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:03,817 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:03,818 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:03,818 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:03,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:03,833 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:03,920 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:03,923 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:03,961 INFO L85 PathProgramCache]: Analyzing trace with hash 53542868, now seen corresponding path program 3 times [2024-05-04 07:36:03,962 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:03,962 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:03,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:03,979 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:36:03,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:03,979 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:03,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:03,993 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:36:04,072 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:04,072 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 60 treesize of output 52 [2024-05-04 07:36:04,112 INFO L85 PathProgramCache]: Analyzing trace with hash -84907850, now seen corresponding path program 4 times [2024-05-04 07:36:04,112 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:04,112 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:04,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:04,131 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:04,131 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:04,132 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:04,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:04,148 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:04,227 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:04,227 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 44 treesize of output 38 [2024-05-04 07:36:04,275 INFO L85 PathProgramCache]: Analyzing trace with hash -961499474, now seen corresponding path program 5 times [2024-05-04 07:36:04,276 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:04,276 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:04,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:04,291 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:04,291 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:04,292 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:04,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:04,306 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:04,402 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:04,403 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 44 treesize of output 38 [2024-05-04 07:36:06,447 INFO L85 PathProgramCache]: Analyzing trace with hash 258287491, now seen corresponding path program 6 times [2024-05-04 07:36:06,447 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:06,447 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:06,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:06,493 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:06,494 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:06,494 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:06,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:06,509 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:06,607 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:06,608 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 44 treesize of output 38 [2024-05-04 07:36:06,659 INFO L85 PathProgramCache]: Analyzing trace with hash 246078533, now seen corresponding path program 7 times [2024-05-04 07:36:06,660 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:06,660 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:06,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:06,674 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:06,674 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:06,674 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:06,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:06,688 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:06,781 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:06,782 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:06,847 INFO L85 PathProgramCache]: Analyzing trace with hash 246078533, now seen corresponding path program 8 times [2024-05-04 07:36:06,847 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:06,847 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:06,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:06,862 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:06,862 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:06,862 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:06,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:06,877 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:06,974 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:06,975 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 24 [2024-05-04 07:36:09,018 INFO L85 PathProgramCache]: Analyzing trace with hash 1662824055, now seen corresponding path program 9 times [2024-05-04 07:36:09,018 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:09,019 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:09,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:09,042 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:09,042 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:09,042 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:09,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:09,058 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:09,158 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:09,158 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:09,194 INFO L85 PathProgramCache]: Analyzing trace with hash 7938264, now seen corresponding path program 10 times [2024-05-04 07:36:09,195 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:09,195 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:09,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:09,209 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:09,209 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:09,209 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:09,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:09,226 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:09,309 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:09,309 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:09,349 INFO L85 PathProgramCache]: Analyzing trace with hash -972341962, now seen corresponding path program 11 times [2024-05-04 07:36:09,349 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:09,351 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:09,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:09,400 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:09,401 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:09,401 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:09,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:09,414 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:09,493 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:09,493 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 24 [2024-05-04 07:36:09,523 INFO L85 PathProgramCache]: Analyzing trace with hash 7926720, now seen corresponding path program 12 times [2024-05-04 07:36:09,523 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:09,523 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:09,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:09,537 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:09,537 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:09,538 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:09,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:09,551 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:09,652 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:09,652 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:11,674 INFO L85 PathProgramCache]: Analyzing trace with hash 133906032, now seen corresponding path program 1 times [2024-05-04 07:36:11,675 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:11,675 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:11,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:11,729 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:11,729 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:11,729 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:11,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:11,743 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:11,834 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:11,834 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:11,861 INFO L85 PathProgramCache]: Analyzing trace with hash 1765500510, now seen corresponding path program 2 times [2024-05-04 07:36:11,861 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:11,861 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:11,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:11,879 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:11,880 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:11,880 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:11,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:11,893 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:11,986 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:11,987 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:12,014 INFO L85 PathProgramCache]: Analyzing trace with hash -1104742204, now seen corresponding path program 1 times [2024-05-04 07:36:12,014 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:12,014 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:12,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:12,036 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:12,036 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:12,036 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:12,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:12,049 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:12,141 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:12,141 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:12,173 INFO L85 PathProgramCache]: Analyzing trace with hash 1442424242, now seen corresponding path program 2 times [2024-05-04 07:36:12,173 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:12,174 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:12,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:12,187 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:12,187 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:12,187 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:12,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:12,200 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:12,328 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:12,328 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:12,357 INFO L85 PathProgramCache]: Analyzing trace with hash 1765629524, now seen corresponding path program 1 times [2024-05-04 07:36:12,357 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:12,357 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:12,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:12,370 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:12,370 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:12,370 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:12,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:12,383 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:12,461 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:12,461 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:12,486 INFO L85 PathProgramCache]: Analyzing trace with hash 462171970, now seen corresponding path program 2 times [2024-05-04 07:36:12,487 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:12,487 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:12,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:12,500 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:12,500 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:12,500 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:12,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:12,512 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:12,593 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:12,593 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:12,621 INFO L85 PathProgramCache]: Analyzing trace with hash 1442454994, now seen corresponding path program 1 times [2024-05-04 07:36:12,621 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:12,621 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:12,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:12,636 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-04 07:36:12,636 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:12,636 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:12,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:12,652 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-04 07:36:12,743 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:12,743 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 60 treesize of output 52 [2024-05-04 07:36:12,778 INFO L85 PathProgramCache]: Analyzing trace with hash 1835576456, now seen corresponding path program 2 times [2024-05-04 07:36:12,779 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:12,779 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:12,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:12,793 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:12,793 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:12,793 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:12,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:12,815 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:12,900 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:12,901 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:12,933 INFO L85 PathProgramCache]: Analyzing trace with hash 1068295393, now seen corresponding path program 3 times [2024-05-04 07:36:12,933 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:12,933 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:12,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:12,947 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:12,947 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:12,948 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:12,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:12,961 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:13,050 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:13,051 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 44 treesize of output 38 [2024-05-04 07:36:13,089 INFO L85 PathProgramCache]: Analyzing trace with hash 1029043471, now seen corresponding path program 4 times [2024-05-04 07:36:13,090 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:13,090 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:13,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:13,104 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:13,104 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:13,104 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:13,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:13,162 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:13,257 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:13,257 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:15,300 INFO L85 PathProgramCache]: Analyzing trace with hash 1029043471, now seen corresponding path program 5 times [2024-05-04 07:36:15,301 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:15,301 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:15,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:15,325 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:15,325 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:15,325 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:15,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:15,343 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:15,431 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:15,432 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:15,462 INFO L85 PathProgramCache]: Analyzing trace with hash -1235012236, now seen corresponding path program 6 times [2024-05-04 07:36:15,462 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:15,462 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:15,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:15,483 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-04 07:36:15,483 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:15,483 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:15,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:15,498 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-04 07:36:15,595 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:15,595 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:15,627 INFO L85 PathProgramCache]: Analyzing trace with hash 1835584322, now seen corresponding path program 7 times [2024-05-04 07:36:15,628 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:15,628 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:15,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:15,641 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:15,641 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:15,642 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:15,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:15,656 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:15,759 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:15,759 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 60 treesize of output 52 [2024-05-04 07:36:15,794 INFO L85 PathProgramCache]: Analyzing trace with hash 1766431953, now seen corresponding path program 8 times [2024-05-04 07:36:15,794 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:15,794 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:15,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:15,808 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-04 07:36:15,808 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:15,808 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:15,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:15,828 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-04 07:36:15,940 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:15,940 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 60 treesize of output 52 [2024-05-04 07:36:15,998 INFO L85 PathProgramCache]: Analyzing trace with hash -1074943942, now seen corresponding path program 9 times [2024-05-04 07:36:15,998 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:15,998 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:16,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:16,013 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-04 07:36:16,013 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:16,013 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:16,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:16,027 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-04 07:36:16,132 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:16,132 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 60 treesize of output 52 [2024-05-04 07:36:16,177 INFO L85 PathProgramCache]: Analyzing trace with hash 1442455228, now seen corresponding path program 10 times [2024-05-04 07:36:16,177 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:16,177 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:16,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:16,194 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-04 07:36:16,194 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:16,194 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:16,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:16,207 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-04 07:36:16,307 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:16,308 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 60 treesize of output 52 [2024-05-04 07:36:16,394 INFO L85 PathProgramCache]: Analyzing trace with hash -802867016, now seen corresponding path program 1 times [2024-05-04 07:36:16,394 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:16,394 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:16,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:16,404 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:36:16,405 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:16,405 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:16,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:16,414 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:36:16,518 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:16,518 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:16,559 INFO L85 PathProgramCache]: Analyzing trace with hash 1538914140, now seen corresponding path program 2 times [2024-05-04 07:36:16,559 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:16,559 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:16,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:16,574 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:16,574 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:16,574 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:16,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:16,588 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:16,698 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:16,698 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:16,733 INFO L85 PathProgramCache]: Analyzing trace with hash -866061426, now seen corresponding path program 1 times [2024-05-04 07:36:16,733 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:16,733 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:16,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:16,748 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:16,748 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:16,748 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:16,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:16,764 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:16,861 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:16,861 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:17,444 INFO L85 PathProgramCache]: Analyzing trace with hash -148387076, now seen corresponding path program 2 times [2024-05-04 07:36:17,444 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:17,444 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:17,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:17,457 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:36:17,457 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:17,458 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:17,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:17,470 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:36:17,583 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:17,583 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:17,617 INFO L85 PathProgramCache]: Analyzing trace with hash -305715226, now seen corresponding path program 1 times [2024-05-04 07:36:17,618 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:17,618 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:17,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:17,630 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:36:17,630 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:17,630 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:17,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:17,643 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:36:17,722 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:17,722 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:17,757 INFO L85 PathProgramCache]: Analyzing trace with hash 549401940, now seen corresponding path program 2 times [2024-05-04 07:36:17,757 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:17,758 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:17,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:17,783 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:36:17,783 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:17,785 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:17,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:17,802 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:36:17,893 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:17,894 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:17,924 INFO L85 PathProgramCache]: Analyzing trace with hash -148258062, now seen corresponding path program 1 times [2024-05-04 07:36:17,924 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:17,924 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:17,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:17,937 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:36:17,938 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:17,938 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:17,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:17,950 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:36:18,082 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:18,082 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:18,107 INFO L85 PathProgramCache]: Analyzing trace with hash 1541743456, now seen corresponding path program 2 times [2024-05-04 07:36:18,107 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:18,107 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:18,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:18,136 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:36:18,136 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:18,136 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:18,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:18,150 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:36:18,243 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:18,244 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:18,273 INFO L85 PathProgramCache]: Analyzing trace with hash 549432692, now seen corresponding path program 1 times [2024-05-04 07:36:18,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:18,273 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:18,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:18,286 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:18,286 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:18,286 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:18,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:18,298 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:18,389 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:18,389 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 60 treesize of output 52 [2024-05-04 07:36:18,422 INFO L85 PathProgramCache]: Analyzing trace with hash 901356330, now seen corresponding path program 2 times [2024-05-04 07:36:18,422 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:18,422 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:18,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:18,436 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:18,436 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:18,436 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:18,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:18,449 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:18,554 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:18,554 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:18,589 INFO L85 PathProgramCache]: Analyzing trace with hash -2122724737, now seen corresponding path program 3 times [2024-05-04 07:36:18,590 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:18,590 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:18,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:18,604 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:18,605 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:18,605 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:18,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:18,618 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:18,719 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:18,720 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 60 treesize of output 52 [2024-05-04 07:36:18,761 INFO L85 PathProgramCache]: Analyzing trace with hash 29076013, now seen corresponding path program 4 times [2024-05-04 07:36:18,762 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:18,762 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:18,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:18,775 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:18,775 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:18,776 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:18,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:18,788 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:18,891 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:18,891 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:18,926 INFO L85 PathProgramCache]: Analyzing trace with hash 29076013, now seen corresponding path program 5 times [2024-05-04 07:36:18,926 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:18,926 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:18,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:18,939 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:18,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:18,940 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:18,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:18,953 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:19,050 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:19,051 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:19,088 INFO L85 PathProgramCache]: Analyzing trace with hash -1372388458, now seen corresponding path program 6 times [2024-05-04 07:36:19,089 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:19,089 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:19,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:19,107 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-04 07:36:19,108 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:19,108 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:19,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:19,123 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-04 07:36:19,266 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:19,267 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:19,297 INFO L85 PathProgramCache]: Analyzing trace with hash 901364196, now seen corresponding path program 7 times [2024-05-04 07:36:19,297 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:19,298 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:19,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:19,311 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:19,311 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:19,311 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:19,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:19,325 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:19,410 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:19,410 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 60 treesize of output 52 [2024-05-04 07:36:19,460 INFO L85 PathProgramCache]: Analyzing trace with hash -147455633, now seen corresponding path program 8 times [2024-05-04 07:36:19,460 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:19,460 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:19,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:19,480 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:19,480 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:19,480 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:19,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:19,493 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:19,595 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:19,595 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 60 treesize of output 52 [2024-05-04 07:36:19,626 INFO L85 PathProgramCache]: Analyzing trace with hash -275916964, now seen corresponding path program 9 times [2024-05-04 07:36:19,626 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:19,626 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:19,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:19,656 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:19,656 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:19,656 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:19,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:19,668 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:19,768 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:19,768 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 60 treesize of output 52 [2024-05-04 07:36:19,809 INFO L85 PathProgramCache]: Analyzing trace with hash 549432926, now seen corresponding path program 10 times [2024-05-04 07:36:19,809 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:19,810 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:19,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:19,822 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:19,823 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:19,823 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:19,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:19,852 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:19,933 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:19,933 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 60 treesize of output 52 [2024-05-04 07:36:19,966 INFO L85 PathProgramCache]: Analyzing trace with hash -1965561510, now seen corresponding path program 1 times [2024-05-04 07:36:19,966 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:19,966 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:19,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:19,982 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:36:19,982 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:19,983 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:19,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:19,991 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:36:20,079 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:20,079 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:20,106 INFO L85 PathProgramCache]: Analyzing trace with hash 881002366, now seen corresponding path program 2 times [2024-05-04 07:36:20,106 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:20,107 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:20,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:20,124 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:20,124 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:20,124 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:20,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:20,138 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:20,227 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:20,227 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:20,260 INFO L85 PathProgramCache]: Analyzing trace with hash -1794914828, now seen corresponding path program 1 times [2024-05-04 07:36:20,260 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:20,260 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:20,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:20,306 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-04 07:36:20,307 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:20,307 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:20,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:20,362 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-04 07:36:20,457 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:20,457 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:20,479 INFO L85 PathProgramCache]: Analyzing trace with hash 784723546, now seen corresponding path program 2 times [2024-05-04 07:36:20,479 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:20,479 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:20,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:20,493 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:20,493 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:20,494 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:20,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:20,508 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:20,612 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:20,612 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:20,651 INFO L85 PathProgramCache]: Analyzing trace with hash -1444057016, now seen corresponding path program 1 times [2024-05-04 07:36:20,651 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:20,651 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:20,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:20,666 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:20,666 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:20,666 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:20,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:20,681 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:20,780 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:20,780 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:20,800 INFO L85 PathProgramCache]: Analyzing trace with hash -251781714, now seen corresponding path program 2 times [2024-05-04 07:36:20,801 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:20,801 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:20,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:20,827 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:20,827 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:20,827 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:20,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:20,851 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:20,931 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:20,931 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:20,959 INFO L85 PathProgramCache]: Analyzing trace with hash 784852440, now seen corresponding path program 1 times [2024-05-04 07:36:20,960 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:20,960 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:20,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:20,974 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:20,974 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:20,974 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:20,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:20,987 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:21,073 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:21,073 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:21,094 INFO L85 PathProgramCache]: Analyzing trace with hash 1377351486, now seen corresponding path program 2 times [2024-05-04 07:36:21,094 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:21,094 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:21,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:21,106 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:21,107 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:21,107 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:21,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:21,124 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:21,205 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:21,205 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:21,230 INFO L85 PathProgramCache]: Analyzing trace with hash -1414504350, now seen corresponding path program 1 times [2024-05-04 07:36:21,231 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:21,231 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:21,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:21,250 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-04 07:36:21,250 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:21,250 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:21,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:21,271 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-04 07:36:21,359 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:21,359 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:21,389 INFO L85 PathProgramCache]: Analyzing trace with hash -2129011578, now seen corresponding path program 2 times [2024-05-04 07:36:21,390 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:21,390 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:21,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:21,404 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-04 07:36:21,405 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:21,405 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:21,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:21,418 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-04 07:36:21,502 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:21,503 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 44 treesize of output 38 [2024-05-04 07:36:21,561 INFO L85 PathProgramCache]: Analyzing trace with hash 1885347772, now seen corresponding path program 3 times [2024-05-04 07:36:21,561 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:21,561 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:21,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:21,576 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-04 07:36:21,577 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:21,577 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:21,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:21,592 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-04 07:36:21,716 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:21,717 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:21,749 INFO L85 PathProgramCache]: Analyzing trace with hash -1683761107, now seen corresponding path program 4 times [2024-05-04 07:36:21,749 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:21,750 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:21,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:21,767 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-04 07:36:21,767 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:21,767 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:21,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:21,782 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-04 07:36:21,875 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:21,875 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 44 treesize of output 38 [2024-05-04 07:36:21,906 INFO L85 PathProgramCache]: Analyzing trace with hash -1601750317, now seen corresponding path program 5 times [2024-05-04 07:36:21,906 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:21,906 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:21,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:21,924 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-04 07:36:21,924 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:21,925 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:21,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:21,940 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-04 07:36:22,028 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:22,028 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:22,047 INFO L85 PathProgramCache]: Analyzing trace with hash -1601750317, now seen corresponding path program 6 times [2024-05-04 07:36:22,047 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:22,047 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:22,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:22,080 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-04 07:36:22,080 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:22,080 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:22,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:22,094 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-04 07:36:22,173 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:22,173 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:24,192 INFO L85 PathProgramCache]: Analyzing trace with hash -649536984, now seen corresponding path program 7 times [2024-05-04 07:36:24,192 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:24,192 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:24,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:24,208 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-04 07:36:24,209 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:24,209 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:24,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:24,224 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-04 07:36:24,306 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:24,307 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:24,334 INFO L85 PathProgramCache]: Analyzing trace with hash 1885355518, now seen corresponding path program 8 times [2024-05-04 07:36:24,334 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:24,334 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:24,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:24,348 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-04 07:36:24,348 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:24,348 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:24,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:24,362 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-04 07:36:24,452 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:24,452 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 24 [2024-05-04 07:36:24,473 INFO L85 PathProgramCache]: Analyzing trace with hash -1574849379, now seen corresponding path program 9 times [2024-05-04 07:36:24,473 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:24,473 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:24,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:24,488 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-04 07:36:24,488 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:24,488 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:24,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:24,501 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-04 07:36:24,595 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:24,596 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:24,629 INFO L85 PathProgramCache]: Analyzing trace with hash -1575690392, now seen corresponding path program 10 times [2024-05-04 07:36:24,629 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:24,629 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:24,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:24,644 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-04 07:36:24,645 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:24,645 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:24,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:24,660 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-04 07:36:24,737 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:24,738 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 24 [2024-05-04 07:36:24,905 INFO L85 PathProgramCache]: Analyzing trace with hash 1890533380, now seen corresponding path program 11 times [2024-05-04 07:36:24,906 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:24,906 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:24,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:24,921 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-04 07:36:24,921 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:24,921 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:24,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:25,002 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-04 07:36:25,104 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:25,104 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 24 [2024-05-04 07:36:25,132 INFO L85 PathProgramCache]: Analyzing trace with hash -1575684618, now seen corresponding path program 12 times [2024-05-04 07:36:25,132 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:25,133 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:25,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:25,147 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-04 07:36:25,147 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:25,147 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:25,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:25,161 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-04 07:36:25,259 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:25,260 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:25,284 INFO L85 PathProgramCache]: Analyzing trace with hash 1618870162, now seen corresponding path program 1 times [2024-05-04 07:36:25,284 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:25,284 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:25,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:25,298 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-04 07:36:25,298 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:25,298 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:25,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:25,310 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-04 07:36:25,409 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:25,409 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:25,443 INFO L85 PathProgramCache]: Analyzing trace with hash -266471560, now seen corresponding path program 2 times [2024-05-04 07:36:25,443 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:25,443 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:25,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:25,456 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:25,457 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:25,457 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:25,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:25,471 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:25,571 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:25,572 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:25,599 INFO L85 PathProgramCache]: Analyzing trace with hash 328633066, now seen corresponding path program 1 times [2024-05-04 07:36:25,599 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:25,599 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:25,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:25,611 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:25,611 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:25,611 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:25,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:25,623 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:25,709 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:25,709 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:25,753 INFO L85 PathProgramCache]: Analyzing trace with hash 1376876752, now seen corresponding path program 2 times [2024-05-04 07:36:25,754 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:25,754 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:25,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:25,766 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:25,766 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:25,766 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:25,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:25,778 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:25,869 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:25,869 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:25,899 INFO L85 PathProgramCache]: Analyzing trace with hash -266342666, now seen corresponding path program 1 times [2024-05-04 07:36:25,900 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:25,900 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:25,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:25,913 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:25,913 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:25,913 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:25,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:25,926 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:26,018 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:26,018 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:26,040 INFO L85 PathProgramCache]: Analyzing trace with hash 1568436188, now seen corresponding path program 2 times [2024-05-04 07:36:26,040 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:26,040 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:26,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:26,060 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:26,060 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:26,060 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:26,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:26,072 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:26,172 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:26,173 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:26,197 INFO L85 PathProgramCache]: Analyzing trace with hash -2026451634, now seen corresponding path program 1 times [2024-05-04 07:36:26,197 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:26,197 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:26,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:26,211 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-04 07:36:26,212 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:26,212 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:26,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:26,225 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-04 07:36:26,386 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:26,386 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:26,415 INFO L85 PathProgramCache]: Analyzing trace with hash 619119668, now seen corresponding path program 2 times [2024-05-04 07:36:26,415 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:26,415 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:26,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:26,429 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-04 07:36:26,429 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:26,429 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:26,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:26,442 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-04 07:36:26,525 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:26,526 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 24 [2024-05-04 07:36:26,547 INFO L85 PathProgramCache]: Analyzing trace with hash 358185732, now seen corresponding path program 3 times [2024-05-04 07:36:26,547 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:26,548 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:26,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:26,560 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-04 07:36:26,560 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:26,560 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:26,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:26,573 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-04 07:36:26,669 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:26,669 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:26,698 INFO L85 PathProgramCache]: Analyzing trace with hash 619108008, now seen corresponding path program 4 times [2024-05-04 07:36:26,698 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:26,698 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:26,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:26,711 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:26,711 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:26,711 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:26,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:26,724 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:26,809 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:26,810 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 44 treesize of output 38 [2024-05-04 07:36:26,842 INFO L85 PathProgramCache]: Analyzing trace with hash 318716126, now seen corresponding path program 5 times [2024-05-04 07:36:26,842 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:26,842 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:26,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:26,868 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-04 07:36:26,868 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:26,868 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:26,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:26,882 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-04 07:36:26,968 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:26,968 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:26,995 INFO L85 PathProgramCache]: Analyzing trace with hash 1290265419, now seen corresponding path program 6 times [2024-05-04 07:36:26,995 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:26,995 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:26,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:27,009 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-04 07:36:27,009 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:27,009 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:27,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:27,023 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-04 07:36:27,120 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:27,120 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 24 [2024-05-04 07:36:27,152 INFO L85 PathProgramCache]: Analyzing trace with hash 1257207153, now seen corresponding path program 7 times [2024-05-04 07:36:27,153 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:27,153 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:27,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:27,166 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-04 07:36:27,167 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:27,167 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:27,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:27,184 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-04 07:36:27,274 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:27,275 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:27,299 INFO L85 PathProgramCache]: Analyzing trace with hash 1257207153, now seen corresponding path program 8 times [2024-05-04 07:36:27,299 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:27,299 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:27,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:27,320 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-04 07:36:27,320 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:27,320 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:27,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:27,333 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-04 07:36:27,409 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:27,410 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:27,440 INFO L85 PathProgramCache]: Analyzing trace with hash 2012479163, now seen corresponding path program 9 times [2024-05-04 07:36:27,440 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:27,440 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:27,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:27,453 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:27,453 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:27,453 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:27,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:27,466 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:27,597 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:27,597 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:27,621 INFO L85 PathProgramCache]: Analyzing trace with hash -2037655286, now seen corresponding path program 10 times [2024-05-04 07:36:27,622 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:27,622 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:27,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:27,637 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:27,637 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:27,637 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:27,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:27,663 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:27,754 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:27,755 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 44 treesize of output 38 [2024-05-04 07:36:27,855 INFO L85 PathProgramCache]: Analyzing trace with hash 323901734, now seen corresponding path program 11 times [2024-05-04 07:36:27,855 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:27,855 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:27,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:27,871 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-04 07:36:27,871 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:27,871 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:27,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:27,887 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-04 07:36:27,977 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:27,978 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 44 treesize of output 38 [2024-05-04 07:36:28,021 INFO L85 PathProgramCache]: Analyzing trace with hash -2037649512, now seen corresponding path program 12 times [2024-05-04 07:36:28,021 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:28,021 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:28,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:28,036 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:28,036 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:28,037 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:28,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:28,050 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:28,149 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:28,149 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:28,180 INFO L85 PathProgramCache]: Analyzing trace with hash -329752206, now seen corresponding path program 1 times [2024-05-04 07:36:28,180 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:28,180 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:28,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:28,231 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:28,231 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:28,231 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:28,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:28,250 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:28,339 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:28,339 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:28,369 INFO L85 PathProgramCache]: Analyzing trace with hash 1572381610, now seen corresponding path program 2 times [2024-05-04 07:36:28,369 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:28,369 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:28,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:28,420 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-04 07:36:28,421 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:28,421 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:28,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:28,436 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-04 07:36:28,530 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:28,530 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:30,573 INFO L85 PathProgramCache]: Analyzing trace with hash 1499189767, now seen corresponding path program 3 times [2024-05-04 07:36:30,573 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:30,573 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:30,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:30,838 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 10 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-05-04 07:36:30,838 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:30,838 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:30,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:30,924 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 10 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-05-04 07:36:31,028 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:31,028 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:31,065 INFO L85 PathProgramCache]: Analyzing trace with hash -1057656683, now seen corresponding path program 4 times [2024-05-04 07:36:31,066 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:31,066 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:31,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:31,089 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-04 07:36:31,089 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:31,089 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:31,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:31,107 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-04 07:36:31,212 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:31,212 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:31,292 INFO L85 PathProgramCache]: Analyzing trace with hash -1057656683, now seen corresponding path program 5 times [2024-05-04 07:36:31,292 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:31,292 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:31,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:31,310 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-04 07:36:31,310 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:31,310 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:31,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:31,326 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-04 07:36:31,429 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:31,429 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:31,463 INFO L85 PathProgramCache]: Analyzing trace with hash -764512236, now seen corresponding path program 6 times [2024-05-04 07:36:31,463 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:31,463 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:31,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:31,479 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:31,480 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:31,480 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:31,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:31,496 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:31,589 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:31,590 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:31,624 INFO L85 PathProgramCache]: Analyzing trace with hash 1572387074, now seen corresponding path program 7 times [2024-05-04 07:36:31,624 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:31,624 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:31,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:31,640 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-04 07:36:31,640 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:31,641 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:31,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:31,656 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-04 07:36:31,753 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:31,754 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:31,779 INFO L85 PathProgramCache]: Analyzing trace with hash -1632383685, now seen corresponding path program 8 times [2024-05-04 07:36:31,780 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:31,780 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:31,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:31,794 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-04 07:36:31,794 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:31,794 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:31,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:31,809 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-04 07:36:31,905 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:31,905 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:31,930 INFO L85 PathProgramCache]: Analyzing trace with hash 935477016, now seen corresponding path program 9 times [2024-05-04 07:36:31,931 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:31,931 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:31,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:32,145 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 6 proven. 6 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:36:32,145 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:32,145 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:32,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:32,201 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 6 proven. 6 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:36:32,278 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:32,278 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:32,298 INFO L85 PathProgramCache]: Analyzing trace with hash -329752450, now seen corresponding path program 10 times [2024-05-04 07:36:32,298 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:32,298 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:32,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:32,456 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 6 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:32,456 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:32,456 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:32,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:32,506 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 6 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:32,598 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:32,598 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:32,623 INFO L85 PathProgramCache]: Analyzing trace with hash 1700856378, now seen corresponding path program 11 times [2024-05-04 07:36:32,623 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:32,623 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:32,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:32,702 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 1 proven. 8 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:36:32,702 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:32,702 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:32,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:32,727 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 1 proven. 8 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:36:32,827 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:32,827 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:32,861 INFO L85 PathProgramCache]: Analyzing trace with hash -1859556964, now seen corresponding path program 12 times [2024-05-04 07:36:32,861 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:32,862 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:32,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:32,883 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 5 proven. 4 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:32,884 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:32,884 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:32,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:32,945 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 5 proven. 4 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:33,047 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:33,048 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:33,081 INFO L85 PathProgramCache]: Analyzing trace with hash 1826652934, now seen corresponding path program 1 times [2024-05-04 07:36:33,081 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:33,081 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:33,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:33,096 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 5 proven. 4 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:33,097 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:33,097 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:33,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:33,112 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 5 proven. 4 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:33,194 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:33,195 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:33,226 INFO L85 PathProgramCache]: Analyzing trace with hash 862837566, now seen corresponding path program 2 times [2024-05-04 07:36:33,227 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:33,230 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:33,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:33,254 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:33,255 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:33,255 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:33,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:33,272 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:33,370 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:33,371 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:33,403 INFO L85 PathProgramCache]: Analyzing trace with hash 978160883, now seen corresponding path program 3 times [2024-05-04 07:36:33,403 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:33,403 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:33,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:33,426 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:33,426 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:33,426 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:33,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:33,447 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:33,535 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:33,535 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:33,563 INFO L85 PathProgramCache]: Analyzing trace with hash 582022785, now seen corresponding path program 4 times [2024-05-04 07:36:33,563 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:33,563 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:33,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:33,579 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:33,580 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:33,580 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:33,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:33,595 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:33,682 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:33,683 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:33,707 INFO L85 PathProgramCache]: Analyzing trace with hash 582022785, now seen corresponding path program 5 times [2024-05-04 07:36:33,707 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:33,707 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:33,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:33,723 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:33,723 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:33,723 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:33,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:33,748 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:33,849 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:33,850 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:33,884 INFO L85 PathProgramCache]: Analyzing trace with hash 263461544, now seen corresponding path program 6 times [2024-05-04 07:36:33,884 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:33,884 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:33,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:33,901 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 5 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-04 07:36:33,901 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:33,902 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:33,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:33,918 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 5 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-04 07:36:34,024 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:34,024 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:34,054 INFO L85 PathProgramCache]: Analyzing trace with hash 862843030, now seen corresponding path program 7 times [2024-05-04 07:36:34,054 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:34,054 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:34,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:34,071 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 5 proven. 4 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:34,071 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:34,071 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:34,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:34,086 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 5 proven. 4 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:34,180 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:34,181 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:34,216 INFO L85 PathProgramCache]: Analyzing trace with hash 791666215, now seen corresponding path program 8 times [2024-05-04 07:36:34,216 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:34,216 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:34,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:34,231 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-04 07:36:34,231 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:34,231 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:34,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:34,246 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-04 07:36:34,403 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:34,404 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:34,426 INFO L85 PathProgramCache]: Analyzing trace with hash -1228387412, now seen corresponding path program 9 times [2024-05-04 07:36:34,426 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:34,426 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:34,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:34,459 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 5 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:36:34,459 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:34,459 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:34,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:34,491 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 5 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:36:34,571 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:34,571 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:34,590 INFO L85 PathProgramCache]: Analyzing trace with hash 1826652690, now seen corresponding path program 10 times [2024-05-04 07:36:34,590 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:34,591 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:34,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:34,617 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:34,617 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:34,617 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:34,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:34,647 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:34,727 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:34,727 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:34,746 INFO L85 PathProgramCache]: Analyzing trace with hash -222229042, now seen corresponding path program 11 times [2024-05-04 07:36:34,746 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:34,746 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:34,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:34,768 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 1 proven. 8 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:36:34,768 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:34,768 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:34,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:34,790 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 1 proven. 8 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:36:34,869 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:34,869 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:34,896 INFO L85 PathProgramCache]: Analyzing trace with hash 1186258992, now seen corresponding path program 12 times [2024-05-04 07:36:34,897 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:34,897 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:34,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:34,910 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 5 proven. 4 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:34,910 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:34,910 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:34,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:34,924 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 5 proven. 4 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:35,007 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:35,007 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:37,044 INFO L85 PathProgramCache]: Analyzing trace with hash -1735684010, now seen corresponding path program 1 times [2024-05-04 07:36:37,044 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:37,044 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:37,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:37,061 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 5 proven. 4 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:37,062 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:37,062 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:37,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:37,077 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 5 proven. 4 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:37,175 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:37,176 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:37,201 INFO L85 PathProgramCache]: Analyzing trace with hash 1295106190, now seen corresponding path program 2 times [2024-05-04 07:36:37,201 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:37,201 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:37,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:37,217 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:37,217 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:37,217 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:37,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:37,233 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:37,336 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:37,336 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:37,370 INFO L85 PathProgramCache]: Analyzing trace with hash 1493586339, now seen corresponding path program 3 times [2024-05-04 07:36:37,371 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:37,371 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:37,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:37,496 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 7 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-05-04 07:36:37,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:37,496 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:37,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:37,560 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 7 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-05-04 07:36:37,726 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:37,726 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:37,758 INFO L85 PathProgramCache]: Analyzing trace with hash -650959055, now seen corresponding path program 4 times [2024-05-04 07:36:37,758 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:37,759 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:37,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:37,777 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:37,777 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:37,777 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:37,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:37,795 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:37,894 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:37,894 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:37,918 INFO L85 PathProgramCache]: Analyzing trace with hash -650959055, now seen corresponding path program 5 times [2024-05-04 07:36:37,918 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:37,918 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:37,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:37,936 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:37,936 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:37,936 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:37,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:37,954 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-04 07:36:38,051 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:38,051 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:38,086 INFO L85 PathProgramCache]: Analyzing trace with hash -938218504, now seen corresponding path program 6 times [2024-05-04 07:36:38,087 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:38,087 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:38,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:38,105 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 5 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-04 07:36:38,105 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:38,106 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:38,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:38,124 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 5 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-04 07:36:38,215 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:38,215 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:38,243 INFO L85 PathProgramCache]: Analyzing trace with hash 1295111654, now seen corresponding path program 7 times [2024-05-04 07:36:38,243 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:38,243 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:38,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:38,258 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 5 proven. 4 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:38,258 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:38,258 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:38,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:38,275 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 5 proven. 4 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:38,356 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:38,356 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:38,378 INFO L85 PathProgramCache]: Analyzing trace with hash 2028370647, now seen corresponding path program 8 times [2024-05-04 07:36:38,378 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:38,378 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:38,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:38,392 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-04 07:36:38,392 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:38,392 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:38,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:38,407 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-04 07:36:38,494 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:38,494 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:38,515 INFO L85 PathProgramCache]: Analyzing trace with hash -1545255684, now seen corresponding path program 9 times [2024-05-04 07:36:38,515 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:38,515 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:38,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:38,548 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 5 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:36:38,548 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:38,548 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:38,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:38,583 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 5 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:36:38,677 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:38,677 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:38,702 INFO L85 PathProgramCache]: Analyzing trace with hash -1735684254, now seen corresponding path program 10 times [2024-05-04 07:36:38,702 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:38,702 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:38,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:38,726 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:38,726 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:38,726 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:38,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:38,749 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:38,847 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:38,847 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:38,868 INFO L85 PathProgramCache]: Analyzing trace with hash 1378304798, now seen corresponding path program 11 times [2024-05-04 07:36:38,868 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:38,868 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:38,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:38,888 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 1 proven. 8 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:36:38,888 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:38,889 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:38,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:38,908 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 1 proven. 8 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:36:38,991 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:38,991 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:39,019 INFO L85 PathProgramCache]: Analyzing trace with hash 1700987264, now seen corresponding path program 12 times [2024-05-04 07:36:39,019 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:39,019 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:39,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:39,035 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 5 proven. 4 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:39,035 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:39,035 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:39,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:39,047 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 5 proven. 4 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:39,134 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:39,134 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 44 treesize of output 38 [2024-05-04 07:36:39,164 INFO L85 PathProgramCache]: Analyzing trace with hash -222194384, now seen corresponding path program 1 times [2024-05-04 07:36:39,164 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:39,164 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:39,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:39,171 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-04 07:36:39,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:39,377 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:39,377 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:39,411 INFO L85 PathProgramCache]: Analyzing trace with hash 1219565330, now seen corresponding path program 2 times [2024-05-04 07:36:39,411 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:39,411 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:39,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:39,429 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-04 07:36:39,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:39,531 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:39,531 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:39,559 INFO L85 PathProgramCache]: Analyzing trace with hash -523786442, now seen corresponding path program 3 times [2024-05-04 07:36:39,559 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:39,560 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:39,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:39,674 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 11 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:36:39,675 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:39,675 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:39,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:39,698 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 11 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:36:39,791 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:39,791 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:41,817 INFO L85 PathProgramCache]: Analyzing trace with hash 1506240360, now seen corresponding path program 4 times [2024-05-04 07:36:41,817 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:41,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:41,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:41,824 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-04 07:36:41,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:41,929 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:41,929 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:41,957 INFO L85 PathProgramCache]: Analyzing trace with hash 93010444, now seen corresponding path program 5 times [2024-05-04 07:36:41,957 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:41,958 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:41,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:42,067 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 13 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:42,067 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:42,067 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:42,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:42,097 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 1 proven. 13 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:42,186 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:42,186 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:42,220 INFO L85 PathProgramCache]: Analyzing trace with hash -811272978, now seen corresponding path program 6 times [2024-05-04 07:36:42,220 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:42,220 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:42,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:42,278 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 2 proven. 14 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:42,278 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:42,278 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:42,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:42,307 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 2 proven. 14 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-04 07:36:42,410 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:42,410 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 24 [2024-05-04 07:36:42,438 INFO L85 PathProgramCache]: Analyzing trace with hash -852199313, now seen corresponding path program 7 times [2024-05-04 07:36:42,438 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:42,438 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:42,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:42,447 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-04 07:36:42,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:42,560 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:42,561 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:42,597 INFO L85 PathProgramCache]: Analyzing trace with hash -852199313, now seen corresponding path program 8 times [2024-05-04 07:36:42,597 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:42,597 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:42,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:42,608 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-04 07:36:42,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:42,722 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:42,722 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:42,755 INFO L85 PathProgramCache]: Analyzing trace with hash 1375217297, now seen corresponding path program 9 times [2024-05-04 07:36:42,755 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:42,755 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:42,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:42,764 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-04 07:36:42,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:42,872 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:42,872 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:42,903 INFO L85 PathProgramCache]: Analyzing trace with hash 1375217297, now seen corresponding path program 10 times [2024-05-04 07:36:42,903 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:42,903 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:42,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:42,914 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-04 07:36:42,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:43,021 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:43,021 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 60 treesize of output 52 [2024-05-04 07:36:43,058 INFO L85 PathProgramCache]: Analyzing trace with hash -317936646, now seen corresponding path program 11 times [2024-05-04 07:36:43,058 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:43,058 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:43,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:43,068 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-04 07:36:43,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:43,173 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:43,173 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 44 treesize of output 38 [2024-05-04 07:36:43,206 INFO L85 PathProgramCache]: Analyzing trace with hash -1266101326, now seen corresponding path program 1 times [2024-05-04 07:36:43,206 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:43,206 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:43,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:43,235 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-04 07:36:43,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:43,389 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:43,390 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 44 treesize of output 38 [2024-05-04 07:36:43,440 INFO L85 PathProgramCache]: Analyzing trace with hash -1266101325, now seen corresponding path program 12 times [2024-05-04 07:36:43,440 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:43,440 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:43,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:43,452 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-04 07:36:43,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:43,562 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:43,562 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 24 [2024-05-04 07:36:45,593 INFO L85 PathProgramCache]: Analyzing trace with hash -1266101325, now seen corresponding path program 13 times [2024-05-04 07:36:45,593 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:45,593 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:45,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:45,668 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 7 proven. 7 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-04 07:36:45,668 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:45,668 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:45,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:45,703 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 7 proven. 7 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-04 07:36:45,792 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:45,793 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:45,827 INFO L85 PathProgramCache]: Analyzing trace with hash -594435306, now seen corresponding path program 14 times [2024-05-04 07:36:45,827 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:45,827 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:45,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:45,891 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 6 proven. 10 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-04 07:36:45,892 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:45,892 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:45,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:45,932 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 6 proven. 10 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-04 07:36:46,028 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:46,028 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:46,054 INFO L85 PathProgramCache]: Analyzing trace with hash -594435306, now seen corresponding path program 15 times [2024-05-04 07:36:46,054 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:46,055 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:46,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:46,064 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-04 07:36:46,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:46,177 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:46,178 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:46,209 INFO L85 PathProgramCache]: Analyzing trace with hash -206124214, now seen corresponding path program 16 times [2024-05-04 07:36:46,210 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:46,210 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:46,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:46,261 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 7 proven. 11 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-04 07:36:46,261 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:46,261 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:46,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:46,314 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 7 proven. 11 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-04 07:36:46,388 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:46,388 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:46,411 INFO L85 PathProgramCache]: Analyzing trace with hash -465018440, now seen corresponding path program 17 times [2024-05-04 07:36:46,412 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:46,412 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:46,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:46,437 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-04 07:36:46,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:46,537 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:46,538 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 44 treesize of output 38 [2024-05-04 07:36:46,602 INFO L85 PathProgramCache]: Analyzing trace with hash 812923008, now seen corresponding path program 18 times [2024-05-04 07:36:46,602 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:46,602 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:46,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:46,614 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-04 07:36:46,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:46,715 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:46,715 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:48,756 INFO L85 PathProgramCache]: Analyzing trace with hash -465033948, now seen corresponding path program 19 times [2024-05-04 07:36:48,756 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:48,756 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:48,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:48,855 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 6 proven. 10 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-04 07:36:48,855 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:48,855 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:48,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:48,900 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 6 proven. 10 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-04 07:36:49,000 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:49,000 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 60 treesize of output 52 [2024-05-04 07:36:49,044 INFO L85 PathProgramCache]: Analyzing trace with hash -1948337446, now seen corresponding path program 20 times [2024-05-04 07:36:49,045 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:49,045 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:49,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:49,059 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-04 07:36:49,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:49,175 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:49,176 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:49,216 INFO L85 PathProgramCache]: Analyzing trace with hash 1738265725, now seen corresponding path program 21 times [2024-05-04 07:36:49,216 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:49,216 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:49,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:49,231 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-04 07:36:49,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:49,351 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:49,351 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:49,383 INFO L85 PathProgramCache]: Analyzing trace with hash -1531150401, now seen corresponding path program 22 times [2024-05-04 07:36:49,383 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:49,383 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:49,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:49,539 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-04 07:36:49,540 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:49,540 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:49,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:49,596 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-04 07:36:49,700 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:49,701 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 60 treesize of output 52 [2024-05-04 07:36:49,739 INFO L85 PathProgramCache]: Analyzing trace with hash -1939576798, now seen corresponding path program 23 times [2024-05-04 07:36:49,739 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:49,739 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:49,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:49,787 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 1 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-04 07:36:49,787 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:49,787 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:49,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:49,835 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 1 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-04 07:36:49,924 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:49,924 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 60 treesize of output 52 [2024-05-04 07:36:49,964 INFO L85 PathProgramCache]: Analyzing trace with hash -221012452, now seen corresponding path program 24 times [2024-05-04 07:36:49,964 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:49,964 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:49,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:49,978 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-04 07:36:50,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:50,099 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:50,099 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 24 [2024-05-04 07:36:50,134 INFO L85 PathProgramCache]: Analyzing trace with hash -317936644, now seen corresponding path program 25 times [2024-05-04 07:36:50,134 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:50,134 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:50,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:50,165 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 7 proven. 7 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-04 07:36:50,165 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:50,165 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:50,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:50,196 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 7 proven. 7 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-04 07:36:50,335 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:50,336 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:50,354 INFO L85 PathProgramCache]: Analyzing trace with hash -317936644, now seen corresponding path program 26 times [2024-05-04 07:36:50,355 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:50,355 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:50,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:50,454 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 2 proven. 10 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-04 07:36:50,454 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:50,454 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:50,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:50,490 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 2 proven. 10 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-04 07:36:50,585 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:50,586 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 60 treesize of output 52 [2024-05-04 07:36:50,618 INFO L85 PathProgramCache]: Analyzing trace with hash -1266101261, now seen corresponding path program 27 times [2024-05-04 07:36:50,618 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:50,618 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:50,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:50,628 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-04 07:36:50,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:50,724 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:50,724 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 24 [2024-05-04 07:36:52,755 INFO L85 PathProgramCache]: Analyzing trace with hash 133879190, now seen corresponding path program 28 times [2024-05-04 07:36:52,755 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:52,755 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:52,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:52,800 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 9 proven. 7 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-04 07:36:52,801 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:52,801 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:52,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:52,845 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 9 proven. 7 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-04 07:36:52,930 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:52,930 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 24 [2024-05-04 07:36:52,952 INFO L85 PathProgramCache]: Analyzing trace with hash 1211311136, now seen corresponding path program 29 times [2024-05-04 07:36:52,953 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:52,953 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:52,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:52,962 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-04 07:36:52,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:53,074 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:53,075 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 44 treesize of output 38 [2024-05-04 07:36:53,113 INFO L85 PathProgramCache]: Analyzing trace with hash 1211314928, now seen corresponding path program 30 times [2024-05-04 07:36:53,113 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:53,113 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:53,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:53,154 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 8 proven. 7 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-04 07:36:53,154 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:53,154 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:53,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:53,193 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 8 proven. 7 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-04 07:36:53,292 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:53,293 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:53,317 INFO L85 PathProgramCache]: Analyzing trace with hash -1103942791, now seen corresponding path program 31 times [2024-05-04 07:36:53,317 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:53,317 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:53,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:53,328 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-04 07:36:53,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:53,435 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:53,436 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:53,469 INFO L85 PathProgramCache]: Analyzing trace with hash 1563095327, now seen corresponding path program 32 times [2024-05-04 07:36:53,469 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:53,469 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:53,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:53,509 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 8 proven. 7 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-04 07:36:53,509 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:53,509 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:53,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:53,555 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 8 proven. 7 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-04 07:36:53,697 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:53,697 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:53,726 INFO L85 PathProgramCache]: Analyzing trace with hash 1563095327, now seen corresponding path program 33 times [2024-05-04 07:36:53,726 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:53,726 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:53,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:53,802 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 3 proven. 10 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-04 07:36:53,802 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:53,802 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:53,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:53,854 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 3 proven. 10 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-04 07:36:53,962 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:53,962 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:53,986 INFO L85 PathProgramCache]: Analyzing trace with hash 1211495654, now seen corresponding path program 34 times [2024-05-04 07:36:53,986 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:53,987 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:53,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:53,998 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-04 07:36:54,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:54,111 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:54,111 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:54,138 INFO L85 PathProgramCache]: Analyzing trace with hash -365219380, now seen corresponding path program 35 times [2024-05-04 07:36:54,138 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:54,139 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:54,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:54,190 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 3 proven. 10 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-04 07:36:54,190 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:54,191 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:54,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:54,233 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 3 proven. 10 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-04 07:36:54,334 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:54,334 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 24 [2024-05-04 07:36:54,553 INFO L85 PathProgramCache]: Analyzing trace with hash -594792804, now seen corresponding path program 36 times [2024-05-04 07:36:54,553 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:54,553 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:54,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:54,562 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-04 07:36:54,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:54,664 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:54,664 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 24 [2024-05-04 07:36:54,993 INFO L85 PathProgramCache]: Analyzing trace with hash 1562739747, now seen corresponding path program 37 times [2024-05-04 07:36:54,993 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:54,993 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:54,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:55,155 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-04 07:36:55,155 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:55,155 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:55,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:55,192 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-04 07:36:55,280 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:55,281 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 60 treesize of output 52 [2024-05-04 07:36:55,318 INFO L85 PathProgramCache]: Analyzing trace with hash -648374814, now seen corresponding path program 38 times [2024-05-04 07:36:55,318 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:55,318 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:55,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:55,325 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-04 07:36:55,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:55,421 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:55,422 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:55,515 INFO L85 PathProgramCache]: Analyzing trace with hash 1375217361, now seen corresponding path program 39 times [2024-05-04 07:36:55,516 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:55,516 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:55,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:55,523 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-04 07:36:55,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:55,624 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:55,624 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:55,646 INFO L85 PathProgramCache]: Analyzing trace with hash -811272930, now seen corresponding path program 40 times [2024-05-04 07:36:55,646 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:55,646 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:55,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:55,669 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-04 07:36:55,670 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:55,670 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:55,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:55,693 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-04 07:36:55,803 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:55,803 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 24 [2024-05-04 07:36:55,825 INFO L85 PathProgramCache]: Analyzing trace with hash -811272930, now seen corresponding path program 41 times [2024-05-04 07:36:55,825 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:55,826 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:55,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:55,851 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:55,864 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:55,864 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:55,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:55,888 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-04 07:36:56,001 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:56,002 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 24 [2024-05-04 07:36:58,046 INFO L85 PathProgramCache]: Analyzing trace with hash -2063285494, now seen corresponding path program 42 times [2024-05-04 07:36:58,046 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:58,047 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:58,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:58,136 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 13 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-04 07:36:58,136 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:58,136 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:58,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:58,168 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 13 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-04 07:36:58,262 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:58,263 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 60 treesize of output 52 [2024-05-04 07:36:58,298 INFO L85 PathProgramCache]: Analyzing trace with hash 462659239, now seen corresponding path program 43 times [2024-05-04 07:36:58,298 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:58,298 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:58,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:58,305 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-04 07:36:58,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:58,406 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:58,407 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 60 treesize of output 52 [2024-05-04 07:36:58,444 INFO L85 PathProgramCache]: Analyzing trace with hash 764726377, now seen corresponding path program 44 times [2024-05-04 07:36:58,444 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:58,444 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:58,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:58,478 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-04 07:36:58,478 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:58,478 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:58,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:58,508 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-04 07:36:58,609 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:58,609 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 24 [2024-05-04 07:36:58,649 INFO L85 PathProgramCache]: Analyzing trace with hash 764726377, now seen corresponding path program 45 times [2024-05-04 07:36:58,649 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:58,649 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:58,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:58,679 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 13 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-04 07:36:58,679 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:58,680 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:58,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:58,709 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 13 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-04 07:36:58,795 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:58,795 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 35 [2024-05-04 07:36:58,822 INFO L85 PathProgramCache]: Analyzing trace with hash 2056321822, now seen corresponding path program 46 times [2024-05-04 07:36:58,822 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:58,822 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:58,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:58,828 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-04 07:36:58,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:58,919 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:58,920 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 60 treesize of output 52 [2024-05-04 07:36:58,953 INFO L85 PathProgramCache]: Analyzing trace with hash 440318336, now seen corresponding path program 47 times [2024-05-04 07:36:58,954 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:58,954 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:58,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:58,960 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-04 07:36:58,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:59,051 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:59,052 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 44 treesize of output 38 [2024-05-04 07:36:59,107 INFO L85 PathProgramCache]: Analyzing trace with hash 764966637, now seen corresponding path program 48 times [2024-05-04 07:36:59,107 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:59,107 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:59,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:59,141 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 5 proven. 7 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-04 07:36:59,141 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:59,141 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:59,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:36:59,172 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 5 proven. 7 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-04 07:36:59,255 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:59,255 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 21 [2024-05-04 07:36:59,275 INFO L85 PathProgramCache]: Analyzing trace with hash -2055837918, now seen corresponding path program 49 times [2024-05-04 07:36:59,275 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:59,275 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:59,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:59,282 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-04 07:36:59,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:59,381 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:36:59,382 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 28 treesize of output 24 [2024-05-04 07:36:59,421 INFO L85 PathProgramCache]: Analyzing trace with hash -505600949, now seen corresponding path program 50 times [2024-05-04 07:36:59,421 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:36:59,421 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:36:59,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:36:59,427 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-04 07:36:59,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:37:00,157 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 7 treesize of output 5 [2024-05-04 07:37:00,221 INFO L85 PathProgramCache]: Analyzing trace with hash 1164759676, now seen corresponding path program 1 times [2024-05-04 07:37:00,221 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:37:00,221 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:37:00,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:37:00,232 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-05-04 07:37:00,232 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:37:00,233 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:37:00,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:37:00,243 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-05-04 07:37:00,243 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-05-04 07:37:00,245 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=341, Invalid=4771, Unknown=0, NotChecked=0, Total=5112 [2024-05-04 07:37:00,914 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-05-04 07:37:00,917 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable306,SelfDestructingSolverStorable307,SelfDestructingSolverStorable308,SelfDestructingSolverStorable309,SelfDestructingSolverStorable302,SelfDestructingSolverStorable303,SelfDestructingSolverStorable304,SelfDestructingSolverStorable305,SelfDestructingSolverStorable300,SelfDestructingSolverStorable301,SelfDestructingSolverStorable90,SelfDestructingSolverStorable91,SelfDestructingSolverStorable92,SelfDestructingSolverStorable93,SelfDestructingSolverStorable330,SelfDestructingSolverStorable94,SelfDestructingSolverStorable95,SelfDestructingSolverStorable96,SelfDestructingSolverStorable97,SelfDestructingSolverStorable207,SelfDestructingSolverStorable328,SelfDestructingSolverStorable208,SelfDestructingSolverStorable329,SelfDestructingSolverStorable209,SelfDestructingSolverStorable98,SelfDestructingSolverStorable203,SelfDestructingSolverStorable324,SelfDestructingSolverStorable99,SelfDestructingSolverStorable204,SelfDestructingSolverStorable325,SelfDestructingSolverStorable205,SelfDestructingSolverStorable326,SelfDestructingSolverStorable206,SelfDestructingSolverStorable327,SelfDestructingSolverStorable320,SelfDestructingSolverStorable200,SelfDestructingSolverStorable321,SelfDestructingSolverStorable201,SelfDestructingSolverStorable322,SelfDestructingSolverStorable202,SelfDestructingSolverStorable323,SelfDestructingSolverStorable317,SelfDestructingSolverStorable318,SelfDestructingSolverStorable319,SelfDestructingSolverStorable313,SelfDestructingSolverStorable314,SelfDestructingSolverStorable315,SelfDestructingSolverStorable316,SelfDestructingSolverStorable310,SelfDestructingSolverStorable311,SelfDestructingSolverStorable312,SelfDestructingSolverStorable195,SelfDestructingSolverStorable196,SelfDestructingSolverStorable197,SelfDestructingSolverStorable198,SelfDestructingSolverStorable191,SelfDestructingSolverStorable192,SelfDestructingSolverStorable193,SelfDestructingSolverStorable194,SelfDestructingSolverStorable190,SelfDestructingSolverStorable188,SelfDestructingSolverStorable189,SelfDestructingSolverStorable184,SelfDestructingSolverStorable185,SelfDestructingSolverStorable186,SelfDestructingSolverStorable187,SelfDestructingSolverStorable180,SelfDestructingSolverStorable181,SelfDestructingSolverStorable182,SelfDestructingSolverStorable183,SelfDestructingSolverStorable177,SelfDestructingSolverStorable298,SelfDestructingSolverStorable178,SelfDestructingSolverStorable299,SelfDestructingSolverStorable179,SelfDestructingSolverStorable199,SelfDestructingSolverStorable151,SelfDestructingSolverStorable272,SelfDestructingSolverStorable152,SelfDestructingSolverStorable273,SelfDestructingSolverStorable153,SelfDestructingSolverStorable274,SelfDestructingSolverStorable154,SelfDestructingSolverStorable275,SelfDestructingSolverStorable30,SelfDestructingSolverStorable270,SelfDestructingSolverStorable31,SelfDestructingSolverStorable150,SelfDestructingSolverStorable271,SelfDestructingSolverStorable4,SelfDestructingSolverStorable3,SelfDestructingSolverStorable2,SelfDestructingSolverStorable1,SelfDestructingSolverStorable8,SelfDestructingSolverStorable7,SelfDestructingSolverStorable6,SelfDestructingSolverStorable5,SelfDestructingSolverStorable32,SelfDestructingSolverStorable148,SelfDestructingSolverStorable269,SelfDestructingSolverStorable33,SelfDestructingSolverStorable149,SelfDestructingSolverStorable34,SelfDestructingSolverStorable9,SelfDestructingSolverStorable35,SelfDestructingSolverStorable36,SelfDestructingSolverStorable144,SelfDestructingSolverStorable265,SelfDestructingSolverStorable37,SelfDestructingSolverStorable145,SelfDestructingSolverStorable266,SelfDestructingSolverStorable38,SelfDestructingSolverStorable146,SelfDestructingSolverStorable267,SelfDestructingSolverStorable39,SelfDestructingSolverStorable147,SelfDestructingSolverStorable268,SelfDestructingSolverStorable140,SelfDestructingSolverStorable261,SelfDestructingSolverStorable141,SelfDestructingSolverStorable262,SelfDestructingSolverStorable142,SelfDestructingSolverStorable263,SelfDestructingSolverStorable143,SelfDestructingSolverStorable264,SelfDestructingSolverStorable40,SelfDestructingSolverStorable41,SelfDestructingSolverStorable42,SelfDestructingSolverStorable260,SelfDestructingSolverStorable0,SelfDestructingSolverStorable43,SelfDestructingSolverStorable137,SelfDestructingSolverStorable258,SelfDestructingSolverStorable44,SelfDestructingSolverStorable138,SelfDestructingSolverStorable259,SelfDestructingSolverStorable45,SelfDestructingSolverStorable139,SelfDestructingSolverStorable46,SelfDestructingSolverStorable47,SelfDestructingSolverStorable133,SelfDestructingSolverStorable254,SelfDestructingSolverStorable48,SelfDestructingSolverStorable134,SelfDestructingSolverStorable255,SelfDestructingSolverStorable49,SelfDestructingSolverStorable135,SelfDestructingSolverStorable256,SelfDestructingSolverStorable136,SelfDestructingSolverStorable257,SelfDestructingSolverStorable173,SelfDestructingSolverStorable294,SelfDestructingSolverStorable174,SelfDestructingSolverStorable295,SelfDestructingSolverStorable175,SelfDestructingSolverStorable296,SelfDestructingSolverStorable176,SelfDestructingSolverStorable297,SelfDestructingSolverStorable290,SelfDestructingSolverStorable170,SelfDestructingSolverStorable291,SelfDestructingSolverStorable171,SelfDestructingSolverStorable292,SelfDestructingSolverStorable172,SelfDestructingSolverStorable293,SelfDestructingSolverStorable18,SelfDestructingSolverStorable19,SelfDestructingSolverStorable10,SelfDestructingSolverStorable11,SelfDestructingSolverStorable12,SelfDestructingSolverStorable13,SelfDestructingSolverStorable14,SelfDestructingSolverStorable166,SelfDestructingSolverStorable287,SelfDestructingSolverStorable15,SelfDestructingSolverStorable167,SelfDestructingSolverStorable288,SelfDestructingSolverStorable16,SelfDestructingSolverStorable168,SelfDestructingSolverStorable289,SelfDestructingSolverStorable17,SelfDestructingSolverStorable169,SelfDestructingSolverStorable162,SelfDestructingSolverStorable283,SelfDestructingSolverStorable163,SelfDestructingSolverStorable284,SelfDestructingSolverStorable164,SelfDestructingSolverStorable285,SelfDestructingSolverStorable165,SelfDestructingSolverStorable286,SelfDestructingSolverStorable280,SelfDestructingSolverStorable160,SelfDestructingSolverStorable281,SelfDestructingSolverStorable20,SelfDestructingSolverStorable161,SelfDestructingSolverStorable282,SelfDestructingSolverStorable29,SelfDestructingSolverStorable21,SelfDestructingSolverStorable159,SelfDestructingSolverStorable22,SelfDestructingSolverStorable23,SelfDestructingSolverStorable24,SelfDestructingSolverStorable25,SelfDestructingSolverStorable155,SelfDestructingSolverStorable276,SelfDestructingSolverStorable26,SelfDestructingSolverStorable156,SelfDestructingSolverStorable277,SelfDestructingSolverStorable27,SelfDestructingSolverStorable157,SelfDestructingSolverStorable278,SelfDestructingSolverStorable28,SelfDestructingSolverStorable158,SelfDestructingSolverStorable279,SelfDestructingSolverStorable350,SelfDestructingSolverStorable70,SelfDestructingSolverStorable230,SelfDestructingSolverStorable351,SelfDestructingSolverStorable71,SelfDestructingSolverStorable110,SelfDestructingSolverStorable231,SelfDestructingSolverStorable352,SelfDestructingSolverStorable72,SelfDestructingSolverStorable73,SelfDestructingSolverStorable74,SelfDestructingSolverStorable75,SelfDestructingSolverStorable108,SelfDestructingSolverStorable229,SelfDestructingSolverStorable109,SelfDestructingSolverStorable76,SelfDestructingSolverStorable104,SelfDestructingSolverStorable225,SelfDestructingSolverStorable346,SelfDestructingSolverStorable77,SelfDestructingSolverStorable105,SelfDestructingSolverStorable226,SelfDestructingSolverStorable347,SelfDestructingSolverStorable78,SelfDestructingSolverStorable106,SelfDestructingSolverStorable227,SelfDestructingSolverStorable348,SelfDestructingSolverStorable79,SelfDestructingSolverStorable107,SelfDestructingSolverStorable228,SelfDestructingSolverStorable349,SelfDestructingSolverStorable100,SelfDestructingSolverStorable221,SelfDestructingSolverStorable342,SelfDestructingSolverStorable101,SelfDestructingSolverStorable222,SelfDestructingSolverStorable343,SelfDestructingSolverStorable102,SelfDestructingSolverStorable223,SelfDestructingSolverStorable344,SelfDestructingSolverStorable103,SelfDestructingSolverStorable224,SelfDestructingSolverStorable345,SelfDestructingSolverStorable80,SelfDestructingSolverStorable81,SelfDestructingSolverStorable340,SelfDestructingSolverStorable82,SelfDestructingSolverStorable220,SelfDestructingSolverStorable341,SelfDestructingSolverStorable83,SelfDestructingSolverStorable84,SelfDestructingSolverStorable85,SelfDestructingSolverStorable86,SelfDestructingSolverStorable218,SelfDestructingSolverStorable339,SelfDestructingSolverStorable219,SelfDestructingSolverStorable87,SelfDestructingSolverStorable214,SelfDestructingSolverStorable335,SelfDestructingSolverStorable88,SelfDestructingSolverStorable215,SelfDestructingSolverStorable336,SelfDestructingSolverStorable89,SelfDestructingSolverStorable216,SelfDestructingSolverStorable337,SelfDestructingSolverStorable217,SelfDestructingSolverStorable338,SelfDestructingSolverStorable210,SelfDestructingSolverStorable331,SelfDestructingSolverStorable211,SelfDestructingSolverStorable332,SelfDestructingSolverStorable212,SelfDestructingSolverStorable333,SelfDestructingSolverStorable213,SelfDestructingSolverStorable334,SelfDestructingSolverStorable250,SelfDestructingSolverStorable371,SelfDestructingSolverStorable130,SelfDestructingSolverStorable251,SelfDestructingSolverStorable372,SelfDestructingSolverStorable131,SelfDestructingSolverStorable252,SelfDestructingSolverStorable373,SelfDestructingSolverStorable132,SelfDestructingSolverStorable253,SelfDestructingSolverStorable374,SelfDestructingSolverStorable50,SelfDestructingSolverStorable51,SelfDestructingSolverStorable52,SelfDestructingSolverStorable53,SelfDestructingSolverStorable370,SelfDestructingSolverStorable54,SelfDestructingSolverStorable126,SelfDestructingSolverStorable247,SelfDestructingSolverStorable368,SelfDestructingSolverStorable55,SelfDestructingSolverStorable127,SelfDestructingSolverStorable248,SelfDestructingSolverStorable369,SelfDestructingSolverStorable56,SelfDestructingSolverStorable128,SelfDestructingSolverStorable249,SelfDestructingSolverStorable57,SelfDestructingSolverStorable129,SelfDestructingSolverStorable58,SelfDestructingSolverStorable122,SelfDestructingSolverStorable243,SelfDestructingSolverStorable364,SelfDestructingSolverStorable59,SelfDestructingSolverStorable123,SelfDestructingSolverStorable244,SelfDestructingSolverStorable365,SelfDestructingSolverStorable124,SelfDestructingSolverStorable245,SelfDestructingSolverStorable366,SelfDestructingSolverStorable125,SelfDestructingSolverStorable246,SelfDestructingSolverStorable367,SelfDestructingSolverStorable360,SelfDestructingSolverStorable240,SelfDestructingSolverStorable361,SelfDestructingSolverStorable120,SelfDestructingSolverStorable241,SelfDestructingSolverStorable362,SelfDestructingSolverStorable60,SelfDestructingSolverStorable121,SelfDestructingSolverStorable242,SelfDestructingSolverStorable363,SelfDestructingSolverStorable61,SelfDestructingSolverStorable62,SelfDestructingSolverStorable63,SelfDestructingSolverStorable64,SelfDestructingSolverStorable119,SelfDestructingSolverStorable65,SelfDestructingSolverStorable115,SelfDestructingSolverStorable236,SelfDestructingSolverStorable357,SelfDestructingSolverStorable66,SelfDestructingSolverStorable116,SelfDestructingSolverStorable237,SelfDestructingSolverStorable358,SelfDestructingSolverStorable67,SelfDestructingSolverStorable117,SelfDestructingSolverStorable238,SelfDestructingSolverStorable359,SelfDestructingSolverStorable68,SelfDestructingSolverStorable118,SelfDestructingSolverStorable239,SelfDestructingSolverStorable69,SelfDestructingSolverStorable111,SelfDestructingSolverStorable232,SelfDestructingSolverStorable353,SelfDestructingSolverStorable112,SelfDestructingSolverStorable233,SelfDestructingSolverStorable354,SelfDestructingSolverStorable113,SelfDestructingSolverStorable234,SelfDestructingSolverStorable355,SelfDestructingSolverStorable114,SelfDestructingSolverStorable235,SelfDestructingSolverStorable356 [2024-05-04 07:37:00,920 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 3 more)] === [2024-05-04 07:37:00,920 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-04 07:37:00,920 INFO L85 PathProgramCache]: Analyzing trace with hash 2277392, now seen corresponding path program 1 times [2024-05-04 07:37:00,920 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-04 07:37:00,920 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2114340663] [2024-05-04 07:37:00,920 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:37:00,920 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:37:00,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:37:00,941 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-05-04 07:37:00,941 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-04 07:37:00,941 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2114340663] [2024-05-04 07:37:00,941 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2114340663] provided 1 perfect and 0 imperfect interpolant sequences [2024-05-04 07:37:00,941 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-05-04 07:37:00,941 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-05-04 07:37:00,941 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1366412199] [2024-05-04 07:37:00,941 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-05-04 07:37:00,942 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-05-04 07:37:00,942 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-04 07:37:00,943 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-05-04 07:37:00,943 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-05-04 07:37:00,943 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-04 07:37:00,943 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-04 07:37:00,943 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 6.2) internal successors, (31), 4 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-04 07:37:00,943 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 9 states. [2024-05-04 07:37:00,943 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-04 07:37:01,707 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-05-04 07:37:01,707 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:01,707 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable375 [2024-05-04 07:37:01,707 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 3 more)] === [2024-05-04 07:37:01,708 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-04 07:37:01,708 INFO L85 PathProgramCache]: Analyzing trace with hash 1695061486, now seen corresponding path program 1 times [2024-05-04 07:37:01,708 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-04 07:37:01,708 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [169602502] [2024-05-04 07:37:01,708 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:37:01,708 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:37:01,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:37:01,726 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-05-04 07:37:01,726 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-04 07:37:01,726 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [169602502] [2024-05-04 07:37:01,726 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [169602502] provided 1 perfect and 0 imperfect interpolant sequences [2024-05-04 07:37:01,726 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-05-04 07:37:01,726 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-05-04 07:37:01,726 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [162309152] [2024-05-04 07:37:01,726 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-05-04 07:37:01,727 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-05-04 07:37:01,727 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-04 07:37:01,727 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-05-04 07:37:01,727 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-05-04 07:37:01,727 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-04 07:37:01,727 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-04 07:37:01,727 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 6.6) internal successors, (33), 4 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-04 07:37:01,727 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 9 states. [2024-05-04 07:37:01,727 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:01,727 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-04 07:37:02,511 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-05-04 07:37:02,511 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:02,511 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:02,511 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable376 [2024-05-04 07:37:02,511 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 3 more)] === [2024-05-04 07:37:02,512 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-04 07:37:02,512 INFO L85 PathProgramCache]: Analyzing trace with hash -1239302896, now seen corresponding path program 1 times [2024-05-04 07:37:02,512 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-04 07:37:02,512 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [965547615] [2024-05-04 07:37:02,512 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:37:02,512 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:37:02,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:37:02,598 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-05-04 07:37:02,598 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-04 07:37:02,598 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [965547615] [2024-05-04 07:37:02,598 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [965547615] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-04 07:37:02,599 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1307562475] [2024-05-04 07:37:02,599 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:37:02,599 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-04 07:37:02,599 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-04 07:37:02,634 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-04 07:37:02,637 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2024-05-04 07:37:02,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:37:02,738 INFO L262 TraceCheckSpWp]: Trace formula consists of 113 conjuncts, 12 conjunts are in the unsatisfiable core [2024-05-04 07:37:02,741 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-04 07:37:02,851 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2024-05-04 07:37:02,874 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-05-04 07:37:02,874 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-04 07:37:03,042 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-05-04 07:37:03,042 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1307562475] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-04 07:37:03,042 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-04 07:37:03,042 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7] total 15 [2024-05-04 07:37:03,042 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1672497326] [2024-05-04 07:37:03,042 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-04 07:37:03,043 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 15 states [2024-05-04 07:37:03,043 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-04 07:37:03,043 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2024-05-04 07:37:03,043 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=71, Invalid=139, Unknown=0, NotChecked=0, Total=210 [2024-05-04 07:37:03,043 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-04 07:37:03,043 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-04 07:37:03,044 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 15 states, 15 states have (on average 4.4) internal successors, (66), 15 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-04 07:37:03,044 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 9 states. [2024-05-04 07:37:03,044 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:03,044 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:03,044 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-04 07:37:05,908 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-05-04 07:37:05,908 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:05,908 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:05,908 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2024-05-04 07:37:05,913 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Ended with exit code 0 [2024-05-04 07:37:06,109 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable377 [2024-05-04 07:37:06,109 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 3 more)] === [2024-05-04 07:37:06,109 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-04 07:37:06,110 INFO L85 PathProgramCache]: Analyzing trace with hash 2021480220, now seen corresponding path program 2 times [2024-05-04 07:37:06,110 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-04 07:37:06,110 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [240472810] [2024-05-04 07:37:06,110 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:37:06,110 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:37:06,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:37:06,124 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-05-04 07:37:06,124 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-04 07:37:06,125 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [240472810] [2024-05-04 07:37:06,125 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [240472810] provided 1 perfect and 0 imperfect interpolant sequences [2024-05-04 07:37:06,125 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-05-04 07:37:06,125 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-05-04 07:37:06,125 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1548103278] [2024-05-04 07:37:06,125 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-05-04 07:37:06,125 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-05-04 07:37:06,125 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-04 07:37:06,125 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-05-04 07:37:06,126 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-05-04 07:37:06,126 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-04 07:37:06,126 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-04 07:37:06,126 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 6.75) internal successors, (27), 3 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-04 07:37:06,126 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 9 states. [2024-05-04 07:37:06,126 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:06,126 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:06,126 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 18 states. [2024-05-04 07:37:06,126 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-04 07:37:12,561 INFO L349 Elim1Store]: treesize reduction 20, result has 59.2 percent of original size [2024-05-04 07:37:12,562 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 64 treesize of output 74 [2024-05-04 07:37:12,678 INFO L85 PathProgramCache]: Analyzing trace with hash 837201194, now seen corresponding path program 1 times [2024-05-04 07:37:12,678 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:37:12,678 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:37:12,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:37:12,681 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-04 07:37:12,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-04 07:37:12,784 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:37:12,784 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 18 treesize of output 18 [2024-05-04 07:37:12,819 INFO L85 PathProgramCache]: Analyzing trace with hash -322436714, now seen corresponding path program 1 times [2024-05-04 07:37:12,819 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:37:12,819 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:37:12,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:37:12,951 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:37:12,951 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:37:12,951 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:37:12,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:37:12,968 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:37:13,055 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:37:13,055 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 18 treesize of output 18 [2024-05-04 07:37:13,064 INFO L85 PathProgramCache]: Analyzing trace with hash 1599434354, now seen corresponding path program 1 times [2024-05-04 07:37:13,064 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:37:13,064 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:37:13,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:37:13,125 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:37:13,126 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:37:13,127 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:37:13,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:37:13,151 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:37:13,205 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:37:13,205 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 18 treesize of output 18 [2024-05-04 07:37:13,232 INFO L85 PathProgramCache]: Analyzing trace with hash 2129804630, now seen corresponding path program 1 times [2024-05-04 07:37:13,232 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:37:13,232 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:37:13,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:37:13,277 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:37:13,278 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:37:13,278 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:37:13,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:37:13,292 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:37:13,362 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:37:13,363 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 18 treesize of output 18 [2024-05-04 07:37:13,376 INFO L85 PathProgramCache]: Analyzing trace with hash 2129804661, now seen corresponding path program 2 times [2024-05-04 07:37:13,376 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:37:13,376 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:37:13,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:37:13,389 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:37:13,389 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:37:13,389 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:37:13,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:37:13,402 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:37:13,460 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:37:13,460 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 18 treesize of output 18 [2024-05-04 07:37:13,472 INFO L85 PathProgramCache]: Analyzing trace with hash -624033292, now seen corresponding path program 3 times [2024-05-04 07:37:13,473 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:37:13,474 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:37:13,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:37:13,489 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:37:13,489 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:37:13,489 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:37:13,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:37:13,504 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:37:13,571 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:37:13,572 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 18 treesize of output 18 [2024-05-04 07:37:13,579 INFO L85 PathProgramCache]: Analyzing trace with hash -624033224, now seen corresponding path program 4 times [2024-05-04 07:37:13,579 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:37:13,580 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:37:13,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:37:13,593 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:37:13,593 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:37:13,593 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:37:13,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:37:13,606 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:37:13,685 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:37:13,685 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 18 treesize of output 18 [2024-05-04 07:37:13,718 INFO L85 PathProgramCache]: Analyzing trace with hash -1257327196, now seen corresponding path program 1 times [2024-05-04 07:37:13,718 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:37:13,718 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:37:13,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:37:13,735 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:37:13,735 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:37:13,735 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:37:13,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:37:13,748 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:37:13,814 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:37:13,814 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 18 treesize of output 18 [2024-05-04 07:37:13,837 INFO L85 PathProgramCache]: Analyzing trace with hash 2112318336, now seen corresponding path program 1 times [2024-05-04 07:37:13,837 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:37:13,837 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:37:13,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:37:13,852 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:37:13,852 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:37:13,852 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:37:13,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:37:13,867 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:37:13,918 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:37:13,918 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 18 treesize of output 18 [2024-05-04 07:37:13,949 INFO L85 PathProgramCache]: Analyzing trace with hash -624597368, now seen corresponding path program 1 times [2024-05-04 07:37:13,950 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:37:13,950 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:37:13,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:37:13,964 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:37:13,964 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:37:13,964 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:37:13,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:37:13,979 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:37:14,046 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-04 07:37:14,047 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 18 treesize of output 18 [2024-05-04 07:37:14,059 INFO L85 PathProgramCache]: Analyzing trace with hash -624597337, now seen corresponding path program 2 times [2024-05-04 07:37:14,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:37:14,059 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:37:14,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:37:14,084 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-05-04 07:37:14,084 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:37:14,084 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:37:14,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:37:14,097 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-05-04 07:37:16,091 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-05-04 07:37:16,091 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:16,091 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:16,092 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2024-05-04 07:37:16,092 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:16,092 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable382,SelfDestructingSolverStorable393,SelfDestructingSolverStorable383,SelfDestructingSolverStorable394,SelfDestructingSolverStorable384,SelfDestructingSolverStorable395,SelfDestructingSolverStorable385,SelfDestructingSolverStorable396,SelfDestructingSolverStorable390,SelfDestructingSolverStorable380,SelfDestructingSolverStorable391,SelfDestructingSolverStorable381,SelfDestructingSolverStorable392,SelfDestructingSolverStorable379,SelfDestructingSolverStorable386,SelfDestructingSolverStorable397,SelfDestructingSolverStorable387,SelfDestructingSolverStorable398,SelfDestructingSolverStorable388,SelfDestructingSolverStorable399,SelfDestructingSolverStorable378,SelfDestructingSolverStorable389 [2024-05-04 07:37:16,092 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 3 more)] === [2024-05-04 07:37:16,092 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-04 07:37:16,092 INFO L85 PathProgramCache]: Analyzing trace with hash 1740352160, now seen corresponding path program 1 times [2024-05-04 07:37:16,092 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-04 07:37:16,092 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1033086747] [2024-05-04 07:37:16,092 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:37:16,092 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:37:16,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:37:16,104 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-05-04 07:37:16,104 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-04 07:37:16,104 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1033086747] [2024-05-04 07:37:16,104 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1033086747] provided 1 perfect and 0 imperfect interpolant sequences [2024-05-04 07:37:16,104 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-05-04 07:37:16,104 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-05-04 07:37:16,104 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1775055479] [2024-05-04 07:37:16,105 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-05-04 07:37:16,105 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-05-04 07:37:16,105 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-04 07:37:16,105 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-05-04 07:37:16,105 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-05-04 07:37:16,105 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-04 07:37:16,105 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-04 07:37:16,105 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 7.25) internal successors, (29), 3 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-04 07:37:16,105 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 9 states. [2024-05-04 07:37:16,105 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:16,105 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:16,105 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 24 states. [2024-05-04 07:37:16,106 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:16,106 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-04 07:37:20,180 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-05-04 07:37:20,181 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:20,181 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:20,181 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2024-05-04 07:37:20,181 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:20,181 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:20,181 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable400 [2024-05-04 07:37:20,181 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 3 more)] === [2024-05-04 07:37:20,181 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-04 07:37:20,181 INFO L85 PathProgramCache]: Analyzing trace with hash -818888160, now seen corresponding path program 1 times [2024-05-04 07:37:20,181 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-04 07:37:20,181 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2043404536] [2024-05-04 07:37:20,181 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:37:20,181 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:37:20,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:37:20,194 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-05-04 07:37:20,194 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-04 07:37:20,194 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2043404536] [2024-05-04 07:37:20,194 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2043404536] provided 1 perfect and 0 imperfect interpolant sequences [2024-05-04 07:37:20,194 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-05-04 07:37:20,194 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-05-04 07:37:20,194 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [142241530] [2024-05-04 07:37:20,194 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-05-04 07:37:20,195 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-05-04 07:37:20,195 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-04 07:37:20,195 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-05-04 07:37:20,195 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-05-04 07:37:20,195 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-04 07:37:20,195 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-04 07:37:20,195 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 7.25) internal successors, (29), 3 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-04 07:37:20,195 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 9 states. [2024-05-04 07:37:20,195 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:20,195 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:20,195 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 24 states. [2024-05-04 07:37:20,195 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:20,195 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:20,195 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-04 07:37:24,476 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-05-04 07:37:24,476 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:24,476 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:24,476 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2024-05-04 07:37:24,476 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:24,476 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:24,476 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:24,476 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable401 [2024-05-04 07:37:24,476 INFO L420 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 3 more)] === [2024-05-04 07:37:24,477 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-04 07:37:24,477 INFO L85 PathProgramCache]: Analyzing trace with hash -408697990, now seen corresponding path program 2 times [2024-05-04 07:37:24,477 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-04 07:37:24,477 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [621029952] [2024-05-04 07:37:24,477 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:37:24,477 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:37:24,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:37:24,579 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:37:24,579 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-04 07:37:24,579 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [621029952] [2024-05-04 07:37:24,579 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [621029952] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-04 07:37:24,579 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [20309376] [2024-05-04 07:37:24,579 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-05-04 07:37:24,579 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-04 07:37:24,579 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-04 07:37:24,580 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-04 07:37:24,627 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2024-05-04 07:37:24,690 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-05-04 07:37:24,690 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-05-04 07:37:24,691 INFO L262 TraceCheckSpWp]: Trace formula consists of 113 conjuncts, 16 conjunts are in the unsatisfiable core [2024-05-04 07:37:24,693 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-04 07:37:24,773 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 11 [2024-05-04 07:37:24,781 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2024-05-04 07:37:24,787 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2024-05-04 07:37:24,821 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:37:24,822 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-04 07:37:25,062 INFO L349 Elim1Store]: treesize reduction 48, result has 2.0 percent of original size [2024-05-04 07:37:25,062 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 137 treesize of output 1 [2024-05-04 07:37:25,062 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:37:25,062 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [20309376] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-04 07:37:25,062 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-04 07:37:25,062 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8] total 15 [2024-05-04 07:37:25,063 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [780603749] [2024-05-04 07:37:25,063 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-04 07:37:25,063 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 15 states [2024-05-04 07:37:25,063 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-04 07:37:25,063 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2024-05-04 07:37:25,063 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=149, Unknown=0, NotChecked=0, Total=210 [2024-05-04 07:37:25,063 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-04 07:37:25,064 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-04 07:37:25,064 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 15 states, 15 states have (on average 4.466666666666667) internal successors, (67), 15 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-04 07:37:25,064 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 9 states. [2024-05-04 07:37:25,064 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:25,064 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:25,064 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 24 states. [2024-05-04 07:37:25,064 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:25,064 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:25,064 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:25,064 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-04 07:37:43,707 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-05-04 07:37:43,707 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:43,707 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:43,707 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2024-05-04 07:37:43,707 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:43,707 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:43,707 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:43,707 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2024-05-04 07:37:43,717 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2024-05-04 07:37:43,911 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable402,4 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-04 07:37:43,915 INFO L420 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 3 more)] === [2024-05-04 07:37:43,915 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-04 07:37:43,915 INFO L85 PathProgramCache]: Analyzing trace with hash -278730592, now seen corresponding path program 3 times [2024-05-04 07:37:43,915 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-04 07:37:43,915 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [464770180] [2024-05-04 07:37:43,915 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:37:43,915 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:37:43,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:37:43,956 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 11 proven. 7 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-04 07:37:43,957 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-04 07:37:43,957 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [464770180] [2024-05-04 07:37:43,957 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [464770180] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-04 07:37:43,957 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [582476613] [2024-05-04 07:37:43,957 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-05-04 07:37:43,957 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-04 07:37:43,957 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-04 07:37:43,958 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-04 07:37:43,958 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2024-05-04 07:37:44,058 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2024-05-04 07:37:44,059 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-05-04 07:37:44,059 INFO L262 TraceCheckSpWp]: Trace formula consists of 119 conjuncts, 6 conjunts are in the unsatisfiable core [2024-05-04 07:37:44,060 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-04 07:37:44,110 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 3 proven. 10 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-04 07:37:44,110 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-04 07:37:44,161 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 3 proven. 10 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-04 07:37:44,161 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [582476613] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-04 07:37:44,161 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-04 07:37:44,161 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 5, 5] total 11 [2024-05-04 07:37:44,161 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1439519813] [2024-05-04 07:37:44,161 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-04 07:37:44,161 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 12 states [2024-05-04 07:37:44,161 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-04 07:37:44,166 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2024-05-04 07:37:44,166 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=103, Unknown=0, NotChecked=0, Total=132 [2024-05-04 07:37:44,166 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-04 07:37:44,166 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-04 07:37:44,167 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 12 states, 12 states have (on average 6.0) internal successors, (72), 11 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-04 07:37:44,167 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 9 states. [2024-05-04 07:37:44,167 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:44,167 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:44,167 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 24 states. [2024-05-04 07:37:44,167 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:44,167 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:44,167 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:37:44,167 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 29 states. [2024-05-04 07:37:44,167 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-04 07:38:45,710 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-05-04 07:38:45,711 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:38:45,711 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:38:45,711 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2024-05-04 07:38:45,711 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:38:45,711 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:38:45,711 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:38:45,711 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2024-05-04 07:38:45,711 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2024-05-04 07:38:45,719 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2024-05-04 07:38:45,914 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable403,5 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-04 07:38:45,914 INFO L420 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONASSERT === [ULTIMATE.startErr0ASSERT_VIOLATIONASSERT, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 3 more)] === [2024-05-04 07:38:45,914 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-04 07:38:45,915 INFO L85 PathProgramCache]: Analyzing trace with hash 577846284, now seen corresponding path program 4 times [2024-05-04 07:38:45,915 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-04 07:38:45,915 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2032147818] [2024-05-04 07:38:45,915 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-04 07:38:46,080 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-04 07:38:46,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-04 07:38:46,173 INFO L134 CoverageAnalysis]: Checked inductivity of 37 backedges. 4 proven. 20 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-04 07:38:46,173 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-04 07:38:46,173 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2032147818] [2024-05-04 07:38:46,173 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2032147818] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-04 07:38:46,173 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1902005187] [2024-05-04 07:38:46,173 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-05-04 07:38:46,173 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-04 07:38:46,173 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-04 07:38:46,174 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-04 07:38:46,175 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2024-05-04 07:38:46,277 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-05-04 07:38:46,277 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-05-04 07:38:46,278 INFO L262 TraceCheckSpWp]: Trace formula consists of 151 conjuncts, 5 conjunts are in the unsatisfiable core [2024-05-04 07:38:46,278 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-04 07:38:46,329 INFO L134 CoverageAnalysis]: Checked inductivity of 37 backedges. 17 proven. 2 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2024-05-04 07:38:46,330 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-04 07:38:46,378 INFO L134 CoverageAnalysis]: Checked inductivity of 37 backedges. 17 proven. 2 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2024-05-04 07:38:46,379 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1902005187] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-04 07:38:46,379 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-04 07:38:46,379 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 4, 4] total 9 [2024-05-04 07:38:46,379 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [446099429] [2024-05-04 07:38:46,379 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-04 07:38:46,380 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2024-05-04 07:38:46,380 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-04 07:38:46,380 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2024-05-04 07:38:46,380 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2024-05-04 07:38:46,380 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-04 07:38:46,381 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-04 07:38:46,381 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 7.5) internal successors, (75), 9 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-04 07:38:46,381 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 9 states. [2024-05-04 07:38:46,381 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:38:46,381 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:38:46,381 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 24 states. [2024-05-04 07:38:46,381 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:38:46,381 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:38:46,381 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 5 states. [2024-05-04 07:38:46,381 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 29 states. [2024-05-04 07:38:46,381 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 38 states. [2024-05-04 07:38:46,381 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states.