/root/.sdkman/candidates/java/current/bin/java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data -s ../benchexec/../../../trunk/examples/settings/gemcutter/NewStatesSleep.epf --traceabstraction.dfs.order.used.in.por LOOP_LOCKSTEP --traceabstraction.additional.conditional.commutativity.checking DFS --traceabstraction.criterion.for.conditional.commutativity.checking DEFAULT --traceabstraction.use.limited.checks.recommended.for.dfs true --traceabstraction.limit.for.limited.checks 50 -tc ../benchexec/../../../trunk/examples/toolchains/AutomizerCInline.xml -i ../../../trunk/examples/svcomp/weaver/popl20-bad-ring-nondet.wvr.c -------------------------------------------------------------------------------- This is Ultimate 0.2.4-wip.dk.conditional-comm-17da818-m [2024-05-06 17:46:36,751 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-05-06 17:46:36,814 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/../benchexec/../../../trunk/examples/settings/gemcutter/NewStatesSleep.epf [2024-05-06 17:46:36,818 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-05-06 17:46:36,818 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-05-06 17:46:36,842 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-05-06 17:46:36,843 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-05-06 17:46:36,843 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-05-06 17:46:36,843 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2024-05-06 17:46:36,843 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2024-05-06 17:46:36,844 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-05-06 17:46:36,844 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-05-06 17:46:36,844 INFO L153 SettingsManager]: * Use SBE=true [2024-05-06 17:46:36,845 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-05-06 17:46:36,845 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2024-05-06 17:46:36,845 INFO L153 SettingsManager]: * sizeof long=4 [2024-05-06 17:46:36,845 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-05-06 17:46:36,845 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-05-06 17:46:36,846 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-05-06 17:46:36,846 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2024-05-06 17:46:36,846 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2024-05-06 17:46:36,846 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2024-05-06 17:46:36,847 INFO L153 SettingsManager]: * sizeof long double=12 [2024-05-06 17:46:36,847 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-05-06 17:46:36,847 INFO L153 SettingsManager]: * Use constant arrays=true [2024-05-06 17:46:36,847 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-05-06 17:46:36,847 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-05-06 17:46:36,847 INFO L153 SettingsManager]: * To the following directory=./dump/ [2024-05-06 17:46:36,848 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-05-06 17:46:36,848 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2024-05-06 17:46:36,848 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-05-06 17:46:36,848 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2024-05-06 17:46:36,848 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2024-05-06 17:46:36,849 INFO L153 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2024-05-06 17:46:36,849 INFO L153 SettingsManager]: * Partial Order Reduction in concurrent analysis=SLEEP_NEW_STATES [2024-05-06 17:46:36,849 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2024-05-06 17:46:36,849 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-05-06 17:46:36,849 INFO L153 SettingsManager]: * Automaton type used in concurrency analysis=PARTIAL_ORDER_FA [2024-05-06 17:46:36,850 INFO L153 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2024-05-06 17:46:36,850 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: DFS Order used in POR -> LOOP_LOCKSTEP Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Additional conditional commutativity checking -> DFS Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Criterion for conditional commutativity checking -> DEFAULT Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: use limited checks (recommended for DFS) -> true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Limit for limited checks -> 50 [2024-05-06 17:46:37,031 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-05-06 17:46:37,047 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-05-06 17:46:37,049 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-05-06 17:46:37,050 INFO L270 PluginConnector]: Initializing CDTParser... [2024-05-06 17:46:37,050 INFO L274 PluginConnector]: CDTParser initialized [2024-05-06 17:46:37,051 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/../../../trunk/examples/svcomp/weaver/popl20-bad-ring-nondet.wvr.c [2024-05-06 17:46:38,016 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-05-06 17:46:38,213 INFO L384 CDTParser]: Found 1 translation units. [2024-05-06 17:46:38,213 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/weaver/popl20-bad-ring-nondet.wvr.c [2024-05-06 17:46:38,221 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/data/b37bf0b8e/b6c4da56ef124df69c034cf465db2a07/FLAGab34dc3b9 [2024-05-06 17:46:38,240 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/data/b37bf0b8e/b6c4da56ef124df69c034cf465db2a07 [2024-05-06 17:46:38,243 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-05-06 17:46:38,245 INFO L133 ToolchainWalker]: Walking toolchain with 5 elements. [2024-05-06 17:46:38,246 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-05-06 17:46:38,246 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-05-06 17:46:38,250 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-05-06 17:46:38,251 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.05 05:46:38" (1/1) ... [2024-05-06 17:46:38,251 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@57801204 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 05:46:38, skipping insertion in model container [2024-05-06 17:46:38,251 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.05 05:46:38" (1/1) ... [2024-05-06 17:46:38,282 INFO L177 MainTranslator]: Built tables and reachable declarations [2024-05-06 17:46:38,444 WARN L240 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/weaver/popl20-bad-ring-nondet.wvr.c[4085,4098] [2024-05-06 17:46:38,454 INFO L209 PostProcessor]: Analyzing one entry point: main [2024-05-06 17:46:38,466 INFO L202 MainTranslator]: Completed pre-run [2024-05-06 17:46:38,508 WARN L240 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/weaver/popl20-bad-ring-nondet.wvr.c[4085,4098] [2024-05-06 17:46:38,510 INFO L209 PostProcessor]: Analyzing one entry point: main [2024-05-06 17:46:38,519 WARN L675 CHandler]: The function __VERIFIER_atomic_begin is called, but not defined or handled by StandardFunctionHandler. [2024-05-06 17:46:38,520 WARN L675 CHandler]: The function __VERIFIER_atomic_end is called, but not defined or handled by StandardFunctionHandler. [2024-05-06 17:46:38,525 INFO L206 MainTranslator]: Completed translation [2024-05-06 17:46:38,526 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 05:46:38 WrapperNode [2024-05-06 17:46:38,526 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-05-06 17:46:38,528 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-05-06 17:46:38,528 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-05-06 17:46:38,528 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-05-06 17:46:38,533 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 05:46:38" (1/1) ... [2024-05-06 17:46:38,552 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 05:46:38" (1/1) ... [2024-05-06 17:46:38,587 INFO L138 Inliner]: procedures = 25, calls = 63, calls flagged for inlining = 16, calls inlined = 20, statements flattened = 330 [2024-05-06 17:46:38,588 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-05-06 17:46:38,588 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-05-06 17:46:38,588 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-05-06 17:46:38,588 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-05-06 17:46:38,596 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 05:46:38" (1/1) ... [2024-05-06 17:46:38,596 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 05:46:38" (1/1) ... [2024-05-06 17:46:38,608 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 05:46:38" (1/1) ... [2024-05-06 17:46:38,608 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 05:46:38" (1/1) ... [2024-05-06 17:46:38,614 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 05:46:38" (1/1) ... [2024-05-06 17:46:38,618 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 05:46:38" (1/1) ... [2024-05-06 17:46:38,619 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 05:46:38" (1/1) ... [2024-05-06 17:46:38,634 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 05:46:38" (1/1) ... [2024-05-06 17:46:38,636 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-05-06 17:46:38,637 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-05-06 17:46:38,637 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-05-06 17:46:38,637 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-05-06 17:46:38,638 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 05:46:38" (1/1) ... [2024-05-06 17:46:38,644 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2024-05-06 17:46:38,652 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 17:46:38,666 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2024-05-06 17:46:38,683 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2024-05-06 17:46:38,706 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-05-06 17:46:38,706 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2024-05-06 17:46:38,706 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2024-05-06 17:46:38,706 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2024-05-06 17:46:38,706 INFO L130 BoogieDeclarations]: Found specification of procedure thread1 [2024-05-06 17:46:38,707 INFO L138 BoogieDeclarations]: Found implementation of procedure thread1 [2024-05-06 17:46:38,707 INFO L130 BoogieDeclarations]: Found specification of procedure thread2 [2024-05-06 17:46:38,707 INFO L138 BoogieDeclarations]: Found implementation of procedure thread2 [2024-05-06 17:46:38,707 INFO L130 BoogieDeclarations]: Found specification of procedure thread3 [2024-05-06 17:46:38,707 INFO L138 BoogieDeclarations]: Found implementation of procedure thread3 [2024-05-06 17:46:38,707 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2024-05-06 17:46:38,708 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2024-05-06 17:46:38,708 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2024-05-06 17:46:38,709 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2024-05-06 17:46:38,709 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-05-06 17:46:38,709 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-05-06 17:46:38,709 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2024-05-06 17:46:38,710 WARN L213 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to OneNontrivialStatement [2024-05-06 17:46:38,820 INFO L241 CfgBuilder]: Building ICFG [2024-05-06 17:46:38,822 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2024-05-06 17:46:39,180 INFO L282 CfgBuilder]: Performing block encoding [2024-05-06 17:46:39,292 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-05-06 17:46:39,292 INFO L309 CfgBuilder]: Removed 6 assume(true) statements. [2024-05-06 17:46:39,294 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.05 05:46:39 BoogieIcfgContainer [2024-05-06 17:46:39,294 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-05-06 17:46:39,296 INFO L112 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2024-05-06 17:46:39,296 INFO L270 PluginConnector]: Initializing TraceAbstraction... [2024-05-06 17:46:39,298 INFO L274 PluginConnector]: TraceAbstraction initialized [2024-05-06 17:46:39,298 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 06.05 05:46:38" (1/3) ... [2024-05-06 17:46:39,299 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5dd3ced7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.05 05:46:39, skipping insertion in model container [2024-05-06 17:46:39,299 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 05:46:38" (2/3) ... [2024-05-06 17:46:39,299 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5dd3ced7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.05 05:46:39, skipping insertion in model container [2024-05-06 17:46:39,299 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.05 05:46:39" (3/3) ... [2024-05-06 17:46:39,302 INFO L112 eAbstractionObserver]: Analyzing ICFG popl20-bad-ring-nondet.wvr.c [2024-05-06 17:46:39,308 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2024-05-06 17:46:39,314 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2024-05-06 17:46:39,315 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2024-05-06 17:46:39,315 INFO L514 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2024-05-06 17:46:39,398 INFO L144 ThreadInstanceAdder]: Constructed 3 joinOtherThreadTransitions. [2024-05-06 17:46:39,441 INFO L100 denceProviderFactory]: Independence Relation #1: [IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=true, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2024-05-06 17:46:39,441 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 [2024-05-06 17:46:39,442 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 17:46:39,444 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 (exit command is (exit), workingDir is null) [2024-05-06 17:46:39,445 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 (2)] Waiting until timeout for monitored process [2024-05-06 17:46:39,468 INFO L188 artialOrderCegarLoop]: Running PartialOrderCegarLoop with 1 independence relations. [2024-05-06 17:46:39,477 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 17:46:39,478 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2024-05-06 17:46:39,483 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=PARTIAL_ORDER_FA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopHeads, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@687b2c7b, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms], mConComChecker=DFS, mConComCheckerCriterion=DEFAULT, mConComCheckerLimitedChecksCriterion=true, mConComCheckerCriterionLimit=50, mConComCheckerRandomProb=100, mConComCheckerRandomSeed=123, mConComCheckerConditionCriterion=false [2024-05-06 17:46:39,483 INFO L358 AbstractCegarLoop]: Starting to check reachability of 4 error locations. [2024-05-06 17:46:39,570 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 1 more)] === [2024-05-06 17:46:39,571 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 17:46:39,572 INFO L85 PathProgramCache]: Analyzing trace with hash 1052777447, now seen corresponding path program 1 times [2024-05-06 17:46:39,578 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 17:46:39,578 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1149725155] [2024-05-06 17:46:39,579 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:46:39,579 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:46:39,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:46:39,919 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-06 17:46:39,920 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 17:46:39,920 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1149725155] [2024-05-06 17:46:39,921 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1149725155] provided 1 perfect and 0 imperfect interpolant sequences [2024-05-06 17:46:39,921 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-05-06 17:46:39,921 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-05-06 17:46:39,922 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1672575155] [2024-05-06 17:46:39,922 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-05-06 17:46:39,928 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 2 states [2024-05-06 17:46:39,928 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 17:46:39,949 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-05-06 17:46:39,950 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-05-06 17:46:39,950 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 17:46:39,952 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 17:46:39,953 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 2 states, 2 states have (on average 113.5) internal successors, (227), 2 states have internal predecessors, (227), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 17:46:39,953 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 17:46:40,111 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 17:46:40,111 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2024-05-06 17:46:40,111 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 1 more)] === [2024-05-06 17:46:40,112 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 17:46:40,112 INFO L85 PathProgramCache]: Analyzing trace with hash 1356684668, now seen corresponding path program 1 times [2024-05-06 17:46:40,112 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 17:46:40,112 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [529513656] [2024-05-06 17:46:40,112 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:46:40,112 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:46:40,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:46:40,479 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-05-06 17:46:40,479 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 17:46:40,479 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [529513656] [2024-05-06 17:46:40,479 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [529513656] provided 1 perfect and 0 imperfect interpolant sequences [2024-05-06 17:46:40,479 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-05-06 17:46:40,480 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-05-06 17:46:40,480 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1227330016] [2024-05-06 17:46:40,480 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-05-06 17:46:40,481 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-05-06 17:46:40,481 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 17:46:40,482 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-05-06 17:46:40,482 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2024-05-06 17:46:40,482 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 17:46:40,482 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 17:46:40,482 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 36.333333333333336) internal successors, (218), 6 states have internal predecessors, (218), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 17:46:40,483 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 17:46:40,483 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 17:46:40,668 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 17:46:40,669 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-05-06 17:46:40,669 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2024-05-06 17:46:40,669 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 1 more)] === [2024-05-06 17:46:40,670 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 17:46:40,670 INFO L85 PathProgramCache]: Analyzing trace with hash 779113091, now seen corresponding path program 1 times [2024-05-06 17:46:40,670 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 17:46:40,671 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [463570144] [2024-05-06 17:46:40,671 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:46:40,671 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:46:40,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:46:40,988 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-06 17:46:40,988 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 17:46:40,988 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [463570144] [2024-05-06 17:46:40,988 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [463570144] provided 1 perfect and 0 imperfect interpolant sequences [2024-05-06 17:46:40,988 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-05-06 17:46:40,989 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-05-06 17:46:40,989 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1700617870] [2024-05-06 17:46:40,989 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-05-06 17:46:40,989 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-05-06 17:46:40,989 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 17:46:40,990 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-05-06 17:46:40,990 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2024-05-06 17:46:40,990 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 17:46:40,990 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 17:46:40,990 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 37.666666666666664) internal successors, (226), 6 states have internal predecessors, (226), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 17:46:40,991 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 17:46:40,991 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 7 states. [2024-05-06 17:46:40,991 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 17:46:41,106 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 17:46:41,106 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-05-06 17:46:41,106 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-05-06 17:46:41,106 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2024-05-06 17:46:41,107 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 1 more)] === [2024-05-06 17:46:41,107 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 17:46:41,107 INFO L85 PathProgramCache]: Analyzing trace with hash 1427258088, now seen corresponding path program 1 times [2024-05-06 17:46:41,107 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 17:46:41,109 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1849378916] [2024-05-06 17:46:41,110 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:46:41,110 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:46:41,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:46:41,408 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:46:41,409 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 17:46:41,409 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1849378916] [2024-05-06 17:46:41,409 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1849378916] provided 1 perfect and 0 imperfect interpolant sequences [2024-05-06 17:46:41,409 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-05-06 17:46:41,409 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-05-06 17:46:41,410 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1899484096] [2024-05-06 17:46:41,410 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-05-06 17:46:41,411 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-05-06 17:46:41,411 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 17:46:41,411 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-05-06 17:46:41,412 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2024-05-06 17:46:41,412 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 17:46:41,415 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 17:46:41,415 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 39.0) internal successors, (234), 6 states have internal predecessors, (234), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 17:46:41,415 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 17:46:41,416 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 7 states. [2024-05-06 17:46:41,416 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 7 states. [2024-05-06 17:46:41,416 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 17:46:41,525 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 17:46:41,526 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-05-06 17:46:41,526 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-05-06 17:46:41,526 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-05-06 17:46:41,526 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3 [2024-05-06 17:46:41,526 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 1 more)] === [2024-05-06 17:46:41,526 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 17:46:41,526 INFO L85 PathProgramCache]: Analyzing trace with hash 580442716, now seen corresponding path program 1 times [2024-05-06 17:46:41,527 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 17:46:41,527 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1783003016] [2024-05-06 17:46:41,527 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:46:41,527 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:46:41,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:46:41,941 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:46:41,941 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 17:46:41,941 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1783003016] [2024-05-06 17:46:41,941 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1783003016] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 17:46:41,941 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1820109742] [2024-05-06 17:46:41,941 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:46:41,942 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 17:46:41,942 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 17:46:41,990 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 17:46:42,004 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2024-05-06 17:46:42,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:46:42,131 INFO L262 TraceCheckSpWp]: Trace formula consists of 526 conjuncts, 7 conjunts are in the unsatisfiable core [2024-05-06 17:46:42,137 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 17:46:42,241 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 17:46:42,241 INFO L323 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-05-06 17:46:42,241 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1820109742] provided 1 perfect and 0 imperfect interpolant sequences [2024-05-06 17:46:42,241 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-05-06 17:46:42,242 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [11] total 14 [2024-05-06 17:46:42,242 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1226785393] [2024-05-06 17:46:42,242 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-05-06 17:46:42,242 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-05-06 17:46:42,242 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 17:46:42,243 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-05-06 17:46:42,244 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=153, Unknown=0, NotChecked=0, Total=182 [2024-05-06 17:46:42,244 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 17:46:42,244 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 17:46:42,244 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 48.4) internal successors, (242), 5 states have internal predecessors, (242), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 17:46:42,244 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 17:46:42,244 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 7 states. [2024-05-06 17:46:42,244 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 7 states. [2024-05-06 17:46:42,244 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 7 states. [2024-05-06 17:46:42,244 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 17:46:42,344 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 17:46:42,344 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-05-06 17:46:42,344 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-05-06 17:46:42,344 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-05-06 17:46:42,344 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-05-06 17:46:42,352 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2024-05-06 17:46:42,550 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4,3 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 17:46:42,550 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 1 more)] === [2024-05-06 17:46:42,551 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 17:46:42,551 INFO L85 PathProgramCache]: Analyzing trace with hash 656252945, now seen corresponding path program 1 times [2024-05-06 17:46:42,551 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 17:46:42,551 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [960600923] [2024-05-06 17:46:42,551 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:46:42,551 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:46:42,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:46:42,628 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 17:46:42,628 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 17:46:42,629 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [960600923] [2024-05-06 17:46:42,631 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [960600923] provided 1 perfect and 0 imperfect interpolant sequences [2024-05-06 17:46:42,631 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-05-06 17:46:42,631 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-05-06 17:46:42,631 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [379309716] [2024-05-06 17:46:42,632 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-05-06 17:46:42,633 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-05-06 17:46:42,633 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 17:46:42,633 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-05-06 17:46:42,633 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-05-06 17:46:42,633 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 17:46:42,633 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 17:46:42,634 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 85.33333333333333) internal successors, (256), 3 states have internal predecessors, (256), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 17:46:42,634 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 17:46:42,634 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 7 states. [2024-05-06 17:46:42,634 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 7 states. [2024-05-06 17:46:42,634 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 7 states. [2024-05-06 17:46:42,634 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 5 states. [2024-05-06 17:46:42,634 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 17:46:42,686 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 17:46:42,686 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-05-06 17:46:42,686 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-05-06 17:46:42,686 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-05-06 17:46:42,686 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-05-06 17:46:42,686 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-05-06 17:46:42,687 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5 [2024-05-06 17:46:42,687 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 1 more)] === [2024-05-06 17:46:42,687 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 17:46:42,688 INFO L85 PathProgramCache]: Analyzing trace with hash 2040960026, now seen corresponding path program 2 times [2024-05-06 17:46:42,688 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 17:46:42,688 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1705380615] [2024-05-06 17:46:42,688 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:46:42,688 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:46:42,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:46:42,807 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 28 proven. 1 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 17:46:42,807 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 17:46:42,807 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1705380615] [2024-05-06 17:46:42,807 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1705380615] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 17:46:42,807 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [327812018] [2024-05-06 17:46:42,807 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-05-06 17:46:42,808 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 17:46:42,808 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 17:46:42,809 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 17:46:42,834 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2024-05-06 17:46:42,966 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-05-06 17:46:42,966 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-05-06 17:46:42,968 INFO L262 TraceCheckSpWp]: Trace formula consists of 571 conjuncts, 13 conjunts are in the unsatisfiable core [2024-05-06 17:46:42,975 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 17:46:43,381 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 3 proven. 26 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 17:46:43,381 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-06 17:46:43,409 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 17:46:43,998 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 24 proven. 5 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 17:46:43,998 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [327812018] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-06 17:46:43,998 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-06 17:46:43,998 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 12, 12] total 25 [2024-05-06 17:46:43,998 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1083569043] [2024-05-06 17:46:43,998 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-06 17:46:43,999 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 25 states [2024-05-06 17:46:43,999 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 17:46:44,000 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2024-05-06 17:46:44,000 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=122, Invalid=478, Unknown=0, NotChecked=0, Total=600 [2024-05-06 17:46:44,000 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 17:46:44,001 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 17:46:44,001 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 25 states, 25 states have (on average 26.6) internal successors, (665), 25 states have internal predecessors, (665), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 17:46:44,001 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 17:46:44,001 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 7 states. [2024-05-06 17:46:44,001 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 7 states. [2024-05-06 17:46:44,001 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 7 states. [2024-05-06 17:46:44,001 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 5 states. [2024-05-06 17:46:44,001 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 3 states. [2024-05-06 17:46:44,001 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 17:46:44,670 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 17:46:44,670 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 29 [2024-05-06 17:46:44,735 INFO L85 PathProgramCache]: Analyzing trace with hash 2051231569, now seen corresponding path program 1 times [2024-05-06 17:46:44,736 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:46:44,736 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:46:44,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:46:44,905 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 16 proven. 0 refuted. 0 times theorem prover too weak. 31 trivial. 0 not checked. [2024-05-06 17:46:44,905 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:46:44,906 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:46:44,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:46:45,025 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 16 proven. 0 refuted. 0 times theorem prover too weak. 31 trivial. 0 not checked. [2024-05-06 17:46:45,026 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-05-06 17:46:45,026 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-05-06 17:46:45,258 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 17:46:45,328 INFO L85 PathProgramCache]: Analyzing trace with hash 999439360, now seen corresponding path program 1 times [2024-05-06 17:46:45,329 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:46:45,329 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:46:45,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:46:46,609 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:46:46,609 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:46:46,610 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:46:46,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:46:47,665 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:46:47,800 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 17:46:47,800 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 29 [2024-05-06 17:46:47,882 INFO L85 PathProgramCache]: Analyzing trace with hash 335918517, now seen corresponding path program 1 times [2024-05-06 17:46:47,882 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:46:47,882 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:46:47,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:46:48,084 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2024-05-06 17:46:48,085 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:46:48,085 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:46:48,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:46:48,243 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2024-05-06 17:46:48,244 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-05-06 17:46:48,244 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=94, Invalid=1166, Unknown=0, NotChecked=0, Total=1260 [2024-05-06 17:46:48,481 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 17:46:49,168 INFO L85 PathProgramCache]: Analyzing trace with hash 999439360, now seen corresponding path program 2 times [2024-05-06 17:46:49,168 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:46:49,168 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:46:49,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:46:50,640 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:46:50,641 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:46:50,641 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:46:50,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:46:51,709 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:46:51,897 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 17:46:51,897 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 29 [2024-05-06 17:46:52,196 INFO L85 PathProgramCache]: Analyzing trace with hash 1489945393, now seen corresponding path program 1 times [2024-05-06 17:46:52,197 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:46:52,197 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:46:52,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:46:53,622 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 28 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 17:46:53,622 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:46:53,622 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:46:53,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:46:55,123 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 28 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 17:46:55,280 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 17:46:55,533 INFO L85 PathProgramCache]: Analyzing trace with hash -1484308428, now seen corresponding path program 1 times [2024-05-06 17:46:55,534 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:46:55,534 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:46:55,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:46:56,471 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:46:56,471 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:46:56,471 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:46:56,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:46:57,320 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:46:57,467 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 17:46:57,468 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 29 [2024-05-06 17:46:57,812 INFO L85 PathProgramCache]: Analyzing trace with hash 455947133, now seen corresponding path program 1 times [2024-05-06 17:46:57,813 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:46:57,813 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:46:57,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:46:58,758 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 28 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 17:46:58,759 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:46:58,759 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:46:58,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:46:59,843 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 28 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 17:47:00,034 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 17:47:00,383 INFO L85 PathProgramCache]: Analyzing trace with hash -468728958, now seen corresponding path program 1 times [2024-05-06 17:47:00,384 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:00,384 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:00,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:01,279 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:47:01,279 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:01,279 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:01,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:02,208 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:47:02,384 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 17:47:02,385 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 29 [2024-05-06 17:47:02,664 INFO L85 PathProgramCache]: Analyzing trace with hash -882573585, now seen corresponding path program 1 times [2024-05-06 17:47:02,664 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:02,664 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:02,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:03,612 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 28 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 17:47:03,613 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:03,613 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:03,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:04,689 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 28 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 17:47:04,922 INFO L85 PathProgramCache]: Analyzing trace with hash 1938627129, now seen corresponding path program 1 times [2024-05-06 17:47:04,922 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:04,922 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:04,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:05,066 INFO L134 CoverageAnalysis]: Checked inductivity of 89 backedges. 37 proven. 1 refuted. 0 times theorem prover too weak. 51 trivial. 0 not checked. [2024-05-06 17:47:05,066 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:05,066 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:05,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:05,165 INFO L134 CoverageAnalysis]: Checked inductivity of 89 backedges. 37 proven. 1 refuted. 0 times theorem prover too weak. 51 trivial. 0 not checked. [2024-05-06 17:47:05,269 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 17:47:07,341 INFO L85 PathProgramCache]: Analyzing trace with hash -783504716, now seen corresponding path program 1 times [2024-05-06 17:47:07,341 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:07,342 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:07,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:07,542 INFO L134 CoverageAnalysis]: Checked inductivity of 89 backedges. 37 proven. 1 refuted. 0 times theorem prover too weak. 51 trivial. 0 not checked. [2024-05-06 17:47:07,542 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:07,542 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:07,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:07,650 INFO L134 CoverageAnalysis]: Checked inductivity of 89 backedges. 37 proven. 1 refuted. 0 times theorem prover too weak. 51 trivial. 0 not checked. [2024-05-06 17:47:07,791 INFO L85 PathProgramCache]: Analyzing trace with hash 1822405154, now seen corresponding path program 2 times [2024-05-06 17:47:07,791 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:07,791 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:07,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:08,443 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 33 proven. 1 refuted. 0 times theorem prover too weak. 46 trivial. 0 not checked. [2024-05-06 17:47:08,444 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:08,444 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:08,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:08,653 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 33 proven. 1 refuted. 0 times theorem prover too weak. 46 trivial. 0 not checked. [2024-05-06 17:47:08,757 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 17:47:09,541 INFO L85 PathProgramCache]: Analyzing trace with hash 1785464138, now seen corresponding path program 2 times [2024-05-06 17:47:09,542 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:09,542 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:09,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:09,779 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 22 proven. 1 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 17:47:09,779 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:09,779 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:09,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:10,027 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 26 proven. 1 refuted. 0 times theorem prover too weak. 31 trivial. 0 not checked. [2024-05-06 17:47:10,311 INFO L85 PathProgramCache]: Analyzing trace with hash -2025649588, now seen corresponding path program 3 times [2024-05-06 17:47:10,311 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:10,311 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:10,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:10,988 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 1 proven. 46 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 17:47:10,989 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:10,989 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:11,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:11,199 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 1 proven. 46 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 17:47:11,308 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 17:47:13,397 INFO L85 PathProgramCache]: Analyzing trace with hash -1835442751, now seen corresponding path program 3 times [2024-05-06 17:47:13,398 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:13,398 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:13,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:13,536 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 17 proven. 1 refuted. 0 times theorem prover too weak. 33 trivial. 0 not checked. [2024-05-06 17:47:13,536 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:13,536 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:13,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:13,629 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 17 proven. 1 refuted. 0 times theorem prover too weak. 33 trivial. 0 not checked. [2024-05-06 17:47:13,849 INFO L85 PathProgramCache]: Analyzing trace with hash -842653905, now seen corresponding path program 4 times [2024-05-06 17:47:13,849 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:13,849 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:13,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:14,006 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 15 proven. 1 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2024-05-06 17:47:14,006 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:14,006 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:14,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:14,173 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 15 proven. 1 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2024-05-06 17:47:14,256 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 17:47:15,245 INFO L85 PathProgramCache]: Analyzing trace with hash -438833513, now seen corresponding path program 4 times [2024-05-06 17:47:15,245 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:15,245 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:15,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:15,400 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 4 proven. 1 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2024-05-06 17:47:15,400 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:15,401 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:15,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:15,602 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 4 proven. 1 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2024-05-06 17:47:15,777 INFO L85 PathProgramCache]: Analyzing trace with hash -1824134881, now seen corresponding path program 5 times [2024-05-06 17:47:15,777 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:15,778 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:15,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:15,910 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2024-05-06 17:47:15,910 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:15,910 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:15,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:15,994 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2024-05-06 17:47:16,079 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 17:47:18,171 INFO L85 PathProgramCache]: Analyzing trace with hash 1419880974, now seen corresponding path program 5 times [2024-05-06 17:47:18,172 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:18,172 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:18,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:18,256 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2024-05-06 17:47:18,257 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:18,257 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:18,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:18,340 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2024-05-06 17:47:18,576 INFO L85 PathProgramCache]: Analyzing trace with hash 1518511484, now seen corresponding path program 6 times [2024-05-06 17:47:18,576 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:18,577 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:18,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:21,934 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-06 17:47:21,934 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:21,935 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:21,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:24,675 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-06 17:47:24,772 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 17:47:26,865 INFO L85 PathProgramCache]: Analyzing trace with hash 1001160996, now seen corresponding path program 6 times [2024-05-06 17:47:26,865 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:26,865 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:26,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:29,601 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-06 17:47:29,601 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:29,601 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:29,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:32,115 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-06 17:47:32,292 INFO L85 PathProgramCache]: Analyzing trace with hash -2127920047, now seen corresponding path program 1 times [2024-05-06 17:47:32,292 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:32,292 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:32,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:32,743 INFO L134 CoverageAnalysis]: Checked inductivity of 84 backedges. 16 proven. 64 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 17:47:32,743 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:32,743 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:32,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:32,955 INFO L134 CoverageAnalysis]: Checked inductivity of 84 backedges. 16 proven. 64 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 17:47:33,046 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 17:47:35,113 INFO L85 PathProgramCache]: Analyzing trace with hash 852093340, now seen corresponding path program 1 times [2024-05-06 17:47:35,114 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:35,114 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:35,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:35,225 INFO L134 CoverageAnalysis]: Checked inductivity of 84 backedges. 35 proven. 1 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2024-05-06 17:47:35,226 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:35,226 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:35,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:35,322 INFO L134 CoverageAnalysis]: Checked inductivity of 84 backedges. 35 proven. 1 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2024-05-06 17:47:35,484 INFO L85 PathProgramCache]: Analyzing trace with hash 973586698, now seen corresponding path program 2 times [2024-05-06 17:47:35,485 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:35,485 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:35,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:35,664 INFO L134 CoverageAnalysis]: Checked inductivity of 76 backedges. 16 proven. 56 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 17:47:35,664 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:35,664 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:35,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:35,896 INFO L134 CoverageAnalysis]: Checked inductivity of 76 backedges. 16 proven. 56 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 17:47:35,995 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 17:47:38,062 INFO L85 PathProgramCache]: Analyzing trace with hash -1914300878, now seen corresponding path program 2 times [2024-05-06 17:47:38,063 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:38,063 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:38,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:38,274 INFO L134 CoverageAnalysis]: Checked inductivity of 54 backedges. 21 proven. 3 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2024-05-06 17:47:38,275 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:38,275 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:38,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:38,450 INFO L134 CoverageAnalysis]: Checked inductivity of 54 backedges. 23 proven. 1 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2024-05-06 17:47:38,596 INFO L85 PathProgramCache]: Analyzing trace with hash 1500990052, now seen corresponding path program 3 times [2024-05-06 17:47:38,597 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:38,597 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:38,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:38,686 INFO L134 CoverageAnalysis]: Checked inductivity of 48 backedges. 15 proven. 1 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2024-05-06 17:47:38,686 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:38,686 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:38,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:38,840 INFO L134 CoverageAnalysis]: Checked inductivity of 48 backedges. 15 proven. 1 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2024-05-06 17:47:38,937 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 17:47:41,033 INFO L85 PathProgramCache]: Analyzing trace with hash 1091045033, now seen corresponding path program 3 times [2024-05-06 17:47:41,033 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:41,033 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:41,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:41,122 INFO L134 CoverageAnalysis]: Checked inductivity of 48 backedges. 15 proven. 1 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2024-05-06 17:47:41,122 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:41,122 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:41,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:41,216 INFO L134 CoverageAnalysis]: Checked inductivity of 48 backedges. 15 proven. 1 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2024-05-06 17:47:41,395 INFO L85 PathProgramCache]: Analyzing trace with hash 1010014231, now seen corresponding path program 4 times [2024-05-06 17:47:41,396 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:41,396 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:41,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:41,550 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 14 proven. 1 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 17:47:41,550 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:41,550 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:41,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:41,732 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 12 proven. 3 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 17:47:41,836 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 17:47:42,305 INFO L85 PathProgramCache]: Analyzing trace with hash 70510975, now seen corresponding path program 4 times [2024-05-06 17:47:42,305 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:42,305 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:42,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:42,528 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 17:47:42,529 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:42,529 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:42,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:42,870 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 17:47:43,133 INFO L85 PathProgramCache]: Analyzing trace with hash 1564114743, now seen corresponding path program 5 times [2024-05-06 17:47:43,134 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:43,134 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:43,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:43,218 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2024-05-06 17:47:43,218 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:43,218 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:43,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:43,297 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2024-05-06 17:47:43,391 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 17:47:43,810 INFO L85 PathProgramCache]: Analyzing trace with hash 443038966, now seen corresponding path program 5 times [2024-05-06 17:47:43,810 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:43,810 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:43,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:43,900 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2024-05-06 17:47:43,900 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:43,900 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:43,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:43,979 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2024-05-06 17:47:44,136 INFO L85 PathProgramCache]: Analyzing trace with hash -782497692, now seen corresponding path program 6 times [2024-05-06 17:47:44,136 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:44,136 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:44,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:46,785 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-06 17:47:46,785 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:46,785 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:46,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:49,478 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-06 17:47:49,587 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 17:47:50,028 INFO L85 PathProgramCache]: Analyzing trace with hash 309388812, now seen corresponding path program 6 times [2024-05-06 17:47:50,028 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:50,028 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:50,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:52,411 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-06 17:47:52,411 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:52,411 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:52,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:55,183 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-06 17:47:55,342 INFO L85 PathProgramCache]: Analyzing trace with hash 949401659, now seen corresponding path program 1 times [2024-05-06 17:47:55,342 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:55,342 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:55,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:55,626 INFO L134 CoverageAnalysis]: Checked inductivity of 84 backedges. 16 proven. 64 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 17:47:55,626 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:55,626 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:55,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:55,865 INFO L134 CoverageAnalysis]: Checked inductivity of 84 backedges. 16 proven. 64 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 17:47:55,975 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 17:47:56,437 INFO L85 PathProgramCache]: Analyzing trace with hash 1266103666, now seen corresponding path program 1 times [2024-05-06 17:47:56,437 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:56,437 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:56,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:56,531 INFO L134 CoverageAnalysis]: Checked inductivity of 84 backedges. 35 proven. 1 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2024-05-06 17:47:56,532 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:56,532 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:56,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:56,623 INFO L134 CoverageAnalysis]: Checked inductivity of 84 backedges. 35 proven. 1 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2024-05-06 17:47:56,754 INFO L85 PathProgramCache]: Analyzing trace with hash -855410464, now seen corresponding path program 2 times [2024-05-06 17:47:56,754 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:56,754 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:56,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:56,925 INFO L134 CoverageAnalysis]: Checked inductivity of 76 backedges. 16 proven. 56 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 17:47:56,926 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:56,926 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:56,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:57,165 INFO L134 CoverageAnalysis]: Checked inductivity of 76 backedges. 16 proven. 56 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 17:47:57,274 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 17:47:59,337 INFO L85 PathProgramCache]: Analyzing trace with hash -292060792, now seen corresponding path program 2 times [2024-05-06 17:47:59,338 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:59,338 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:59,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:59,509 INFO L134 CoverageAnalysis]: Checked inductivity of 54 backedges. 19 proven. 1 refuted. 0 times theorem prover too weak. 34 trivial. 0 not checked. [2024-05-06 17:47:59,509 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:59,509 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:59,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:47:59,673 INFO L134 CoverageAnalysis]: Checked inductivity of 54 backedges. 19 proven. 1 refuted. 0 times theorem prover too weak. 34 trivial. 0 not checked. [2024-05-06 17:47:59,838 INFO L85 PathProgramCache]: Analyzing trace with hash -391019314, now seen corresponding path program 3 times [2024-05-06 17:47:59,838 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:47:59,838 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:47:59,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:00,004 INFO L134 CoverageAnalysis]: Checked inductivity of 48 backedges. 1 proven. 44 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-06 17:48:00,004 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:00,004 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:00,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:00,169 INFO L134 CoverageAnalysis]: Checked inductivity of 48 backedges. 1 proven. 44 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-06 17:48:00,258 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 17:48:00,710 INFO L85 PathProgramCache]: Analyzing trace with hash -904152065, now seen corresponding path program 3 times [2024-05-06 17:48:00,711 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:00,711 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:00,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:00,797 INFO L134 CoverageAnalysis]: Checked inductivity of 48 backedges. 15 proven. 1 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2024-05-06 17:48:00,797 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:00,797 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:00,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:00,950 INFO L134 CoverageAnalysis]: Checked inductivity of 48 backedges. 15 proven. 1 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2024-05-06 17:48:01,131 INFO L85 PathProgramCache]: Analyzing trace with hash 815315309, now seen corresponding path program 4 times [2024-05-06 17:48:01,131 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:01,132 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:01,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:01,300 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 12 proven. 3 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 17:48:01,300 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:01,301 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:01,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:01,455 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 14 proven. 1 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 17:48:01,544 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 17:48:03,636 INFO L85 PathProgramCache]: Analyzing trace with hash -37970347, now seen corresponding path program 4 times [2024-05-06 17:48:03,636 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:03,637 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:03,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:03,790 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 3 proven. 1 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 17:48:03,790 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:03,790 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:03,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:03,937 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 3 proven. 1 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 17:48:04,123 INFO L85 PathProgramCache]: Analyzing trace with hash -1372626911, now seen corresponding path program 5 times [2024-05-06 17:48:04,123 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:04,123 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:04,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:06,831 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-06 17:48:06,831 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:06,831 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:06,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:08,929 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-06 17:48:09,022 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 17:48:11,126 INFO L85 PathProgramCache]: Analyzing trace with hash 456244172, now seen corresponding path program 5 times [2024-05-06 17:48:11,126 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:11,126 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:11,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:11,205 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2024-05-06 17:48:11,205 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:11,205 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:11,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:11,282 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2024-05-06 17:48:11,467 INFO L85 PathProgramCache]: Analyzing trace with hash 2033840954, now seen corresponding path program 6 times [2024-05-06 17:48:11,467 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:11,467 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:11,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:14,249 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-06 17:48:14,249 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:14,249 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:14,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:17,105 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-06 17:48:17,213 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 17:48:19,312 INFO L85 PathProgramCache]: Analyzing trace with hash 9978978, now seen corresponding path program 6 times [2024-05-06 17:48:19,312 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:19,312 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:19,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:22,116 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-06 17:48:22,117 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:22,117 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:22,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:24,738 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-06 17:48:24,862 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 17:48:24,937 INFO L85 PathProgramCache]: Analyzing trace with hash -1044256843, now seen corresponding path program 1 times [2024-05-06 17:48:24,938 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:24,938 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:24,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:25,177 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2024-05-06 17:48:25,178 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:25,178 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:25,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:25,301 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2024-05-06 17:48:25,421 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 17:48:25,421 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 29 [2024-05-06 17:48:25,508 INFO L85 PathProgramCache]: Analyzing trace with hash -1274003286, now seen corresponding path program 1 times [2024-05-06 17:48:25,508 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:25,508 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:25,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:25,635 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2024-05-06 17:48:25,635 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:25,636 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:25,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:25,818 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2024-05-06 17:48:25,955 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 17:48:25,955 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 29 [2024-05-06 17:48:26,056 INFO L85 PathProgramCache]: Analyzing trace with hash 1853654428, now seen corresponding path program 1 times [2024-05-06 17:48:26,056 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:26,057 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:26,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:26,179 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2024-05-06 17:48:26,180 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:26,180 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:26,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:26,299 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2024-05-06 17:48:26,412 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 17:48:26,481 INFO L85 PathProgramCache]: Analyzing trace with hash 1636354527, now seen corresponding path program 1 times [2024-05-06 17:48:26,482 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:26,482 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:26,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:26,600 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2024-05-06 17:48:26,600 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:26,600 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:26,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:26,719 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2024-05-06 17:48:26,833 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 17:48:26,834 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 29 [2024-05-06 17:48:26,913 INFO L85 PathProgramCache]: Analyzing trace with hash -1289547436, now seen corresponding path program 1 times [2024-05-06 17:48:26,914 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:26,914 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:26,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:27,038 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2024-05-06 17:48:27,038 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:27,038 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:27,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:27,224 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2024-05-06 17:48:27,352 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 17:48:27,352 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 29 [2024-05-06 17:48:27,431 INFO L85 PathProgramCache]: Analyzing trace with hash -86509646, now seen corresponding path program 1 times [2024-05-06 17:48:27,431 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:27,431 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:27,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:27,553 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2024-05-06 17:48:27,553 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:27,554 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:27,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:27,674 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2024-05-06 17:48:27,788 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 17:48:27,865 INFO L85 PathProgramCache]: Analyzing trace with hash 1848694903, now seen corresponding path program 1 times [2024-05-06 17:48:27,866 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:27,866 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:27,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:27,982 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2024-05-06 17:48:27,982 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:27,982 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:27,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:28,099 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2024-05-06 17:48:28,215 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 17:48:28,216 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 29 [2024-05-06 17:48:28,294 INFO L85 PathProgramCache]: Analyzing trace with hash -740182548, now seen corresponding path program 1 times [2024-05-06 17:48:28,295 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:28,295 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:28,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:28,421 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2024-05-06 17:48:28,421 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:28,421 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:28,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:28,656 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2024-05-06 17:48:28,783 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 17:48:28,783 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 29 [2024-05-06 17:48:28,872 INFO L85 PathProgramCache]: Analyzing trace with hash -68788198, now seen corresponding path program 1 times [2024-05-06 17:48:28,872 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:28,872 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:28,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:28,995 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2024-05-06 17:48:28,995 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:28,995 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:29,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:29,117 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2024-05-06 17:48:29,242 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 17:48:29,312 INFO L85 PathProgramCache]: Analyzing trace with hash 1652181398, now seen corresponding path program 1 times [2024-05-06 17:48:29,312 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:29,312 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:29,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:29,426 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 27 refuted. 0 times theorem prover too weak. 34 trivial. 0 not checked. [2024-05-06 17:48:29,427 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:29,427 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:29,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:29,544 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 27 refuted. 0 times theorem prover too weak. 34 trivial. 0 not checked. [2024-05-06 17:48:29,719 INFO L85 PathProgramCache]: Analyzing trace with hash 1276886786, now seen corresponding path program 2 times [2024-05-06 17:48:29,719 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:29,719 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:29,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:29,998 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 8 proven. 64 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2024-05-06 17:48:29,998 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:29,998 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:30,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:30,224 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 8 proven. 64 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2024-05-06 17:48:30,316 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 17:48:30,714 INFO L85 PathProgramCache]: Analyzing trace with hash -790174389, now seen corresponding path program 1 times [2024-05-06 17:48:30,715 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:30,715 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:30,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:30,861 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 1 proven. 27 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2024-05-06 17:48:30,862 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:30,862 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:30,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:31,009 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 1 proven. 27 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2024-05-06 17:48:31,144 INFO L85 PathProgramCache]: Analyzing trace with hash 26737337, now seen corresponding path program 3 times [2024-05-06 17:48:31,144 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:31,144 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:31,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:31,457 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 35 proven. 48 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 17:48:31,457 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:31,457 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:31,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:31,724 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 35 proven. 48 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 17:48:31,827 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 17:48:33,891 INFO L85 PathProgramCache]: Analyzing trace with hash 483577505, now seen corresponding path program 2 times [2024-05-06 17:48:33,891 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:33,891 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:33,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:34,078 INFO L134 CoverageAnalysis]: Checked inductivity of 76 backedges. 21 proven. 48 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 17:48:34,078 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:34,079 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:34,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:34,269 INFO L134 CoverageAnalysis]: Checked inductivity of 76 backedges. 21 proven. 48 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 17:48:34,427 INFO L85 PathProgramCache]: Analyzing trace with hash -148406443, now seen corresponding path program 4 times [2024-05-06 17:48:34,427 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:34,427 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:34,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:34,628 INFO L134 CoverageAnalysis]: Checked inductivity of 70 backedges. 9 proven. 55 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 17:48:34,628 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:34,628 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:34,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:34,906 INFO L134 CoverageAnalysis]: Checked inductivity of 70 backedges. 9 proven. 55 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 17:48:34,993 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 17:48:35,531 INFO L85 PathProgramCache]: Analyzing trace with hash -1654071272, now seen corresponding path program 3 times [2024-05-06 17:48:35,532 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:35,532 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:35,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:35,671 INFO L134 CoverageAnalysis]: Checked inductivity of 70 backedges. 1 proven. 27 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2024-05-06 17:48:35,671 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:35,672 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:35,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:35,809 INFO L134 CoverageAnalysis]: Checked inductivity of 70 backedges. 1 proven. 27 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2024-05-06 17:48:36,037 INFO L85 PathProgramCache]: Analyzing trace with hash -621072506, now seen corresponding path program 5 times [2024-05-06 17:48:36,038 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:36,038 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:36,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:36,216 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 3 proven. 56 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 17:48:36,217 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:36,217 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:36,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:36,395 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 3 proven. 56 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 17:48:36,570 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 17:48:38,663 INFO L85 PathProgramCache]: Analyzing trace with hash -1063374930, now seen corresponding path program 4 times [2024-05-06 17:48:38,663 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:38,663 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:38,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:38,828 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 1 proven. 27 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 17:48:38,829 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:38,829 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:38,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:38,987 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 1 proven. 27 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 17:48:39,163 INFO L85 PathProgramCache]: Analyzing trace with hash -1770013080, now seen corresponding path program 6 times [2024-05-06 17:48:39,163 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:39,164 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:39,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:39,249 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2024-05-06 17:48:39,249 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:39,249 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:39,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:39,347 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2024-05-06 17:48:39,348 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-05-06 17:48:39,362 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1346, Invalid=65994, Unknown=0, NotChecked=0, Total=67340 [2024-05-06 17:48:39,630 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 17:48:39,990 INFO L85 PathProgramCache]: Analyzing trace with hash 999439360, now seen corresponding path program 3 times [2024-05-06 17:48:39,990 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:39,990 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:40,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:41,218 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:48:41,219 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:41,219 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:41,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:42,343 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:48:42,482 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 17:48:42,964 INFO L85 PathProgramCache]: Analyzing trace with hash -1491615409, now seen corresponding path program 4 times [2024-05-06 17:48:42,964 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:42,964 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:43,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:44,357 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 2 proven. 32 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:48:44,357 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:44,357 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:44,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:44,748 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 2 proven. 32 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:48:44,895 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 17:48:44,895 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 29 [2024-05-06 17:48:45,732 INFO L85 PathProgramCache]: Analyzing trace with hash 2056951362, now seen corresponding path program 2 times [2024-05-06 17:48:45,732 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:45,732 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:45,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:46,153 INFO L134 CoverageAnalysis]: Checked inductivity of 53 backedges. 18 proven. 31 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 17:48:46,154 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:46,154 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:46,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:46,570 INFO L134 CoverageAnalysis]: Checked inductivity of 53 backedges. 18 proven. 31 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 17:48:46,712 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 17:48:46,712 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 29 [2024-05-06 17:48:47,623 INFO L85 PathProgramCache]: Analyzing trace with hash 1489945393, now seen corresponding path program 3 times [2024-05-06 17:48:47,623 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:47,624 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:47,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:49,170 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 28 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 17:48:49,170 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:49,170 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:49,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:51,086 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 28 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 17:48:51,249 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 17:48:51,786 INFO L85 PathProgramCache]: Analyzing trace with hash -1484308428, now seen corresponding path program 2 times [2024-05-06 17:48:51,787 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:51,787 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:51,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:52,337 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:48:52,337 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:52,337 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:52,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:53,495 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:48:53,621 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 17:48:54,011 INFO L85 PathProgramCache]: Analyzing trace with hash 1769353627, now seen corresponding path program 3 times [2024-05-06 17:48:54,011 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:54,011 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:54,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:54,475 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 2 proven. 32 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:48:54,475 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:54,475 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:54,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:55,709 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 2 proven. 32 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:48:55,856 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 17:48:55,856 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 29 [2024-05-06 17:48:56,575 INFO L85 PathProgramCache]: Analyzing trace with hash 386531702, now seen corresponding path program 2 times [2024-05-06 17:48:56,576 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:56,576 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:56,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:57,074 INFO L134 CoverageAnalysis]: Checked inductivity of 53 backedges. 18 proven. 31 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 17:48:57,074 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:57,074 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:57,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:57,491 INFO L134 CoverageAnalysis]: Checked inductivity of 53 backedges. 18 proven. 31 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 17:48:57,628 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 17:48:57,629 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 29 [2024-05-06 17:48:58,277 INFO L85 PathProgramCache]: Analyzing trace with hash 455947133, now seen corresponding path program 3 times [2024-05-06 17:48:58,277 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:58,278 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:58,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:59,016 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 28 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 17:48:59,017 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:48:59,017 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:48:59,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:48:59,557 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 28 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 17:48:59,803 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 17:49:00,316 INFO L85 PathProgramCache]: Analyzing trace with hash -468728958, now seen corresponding path program 2 times [2024-05-06 17:49:00,316 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:00,316 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:00,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:00,979 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:49:00,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:00,979 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:01,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:02,442 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:49:02,567 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 17:49:02,940 INFO L85 PathProgramCache]: Analyzing trace with hash 430832909, now seen corresponding path program 3 times [2024-05-06 17:49:02,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:02,940 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:02,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:03,331 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 2 proven. 32 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:49:03,332 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:03,332 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:03,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:03,723 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 2 proven. 32 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:49:03,950 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 17:49:03,950 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 29 [2024-05-06 17:49:04,272 INFO L85 PathProgramCache]: Analyzing trace with hash 735567684, now seen corresponding path program 2 times [2024-05-06 17:49:04,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:04,273 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:04,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:05,186 INFO L134 CoverageAnalysis]: Checked inductivity of 53 backedges. 18 proven. 31 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 17:49:05,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:05,187 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:05,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:05,603 INFO L134 CoverageAnalysis]: Checked inductivity of 53 backedges. 18 proven. 31 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 17:49:05,759 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 17:49:05,759 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 29 [2024-05-06 17:49:06,146 INFO L85 PathProgramCache]: Analyzing trace with hash -882573585, now seen corresponding path program 3 times [2024-05-06 17:49:06,146 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:06,147 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:06,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:07,647 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 28 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 17:49:07,648 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:07,648 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:07,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:09,047 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 28 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 17:49:09,439 INFO L85 PathProgramCache]: Analyzing trace with hash 1822405154, now seen corresponding path program 7 times [2024-05-06 17:49:09,439 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:09,439 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:09,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:09,615 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 16 proven. 59 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 17:49:09,615 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:09,615 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:09,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:09,792 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 16 proven. 59 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 17:49:09,897 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 17:49:10,619 INFO L85 PathProgramCache]: Analyzing trace with hash 1785464138, now seen corresponding path program 7 times [2024-05-06 17:49:10,619 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:10,619 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:10,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:10,805 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 26 proven. 1 refuted. 0 times theorem prover too weak. 31 trivial. 0 not checked. [2024-05-06 17:49:10,805 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:10,805 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:10,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:10,985 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 26 proven. 1 refuted. 0 times theorem prover too weak. 31 trivial. 0 not checked. [2024-05-06 17:49:11,309 INFO L85 PathProgramCache]: Analyzing trace with hash -842653905, now seen corresponding path program 8 times [2024-05-06 17:49:11,310 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:11,310 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:11,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:11,546 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 15 proven. 1 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2024-05-06 17:49:11,547 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:11,547 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:11,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:11,704 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 15 proven. 1 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2024-05-06 17:49:11,801 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 17:49:13,885 INFO L85 PathProgramCache]: Analyzing trace with hash -438833513, now seen corresponding path program 8 times [2024-05-06 17:49:13,885 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:13,886 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:13,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:14,040 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 4 proven. 1 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2024-05-06 17:49:14,040 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:14,040 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:14,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:14,196 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 4 proven. 1 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2024-05-06 17:49:14,504 INFO L85 PathProgramCache]: Analyzing trace with hash 1518511484, now seen corresponding path program 9 times [2024-05-06 17:49:14,504 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:14,504 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:14,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:18,211 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-06 17:49:18,211 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:18,212 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:18,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:22,063 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-06 17:49:22,166 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 17:49:24,267 INFO L85 PathProgramCache]: Analyzing trace with hash 1001160996, now seen corresponding path program 9 times [2024-05-06 17:49:24,268 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:24,268 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:24,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:28,084 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-06 17:49:28,084 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:28,085 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:28,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:29,337 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-06 17:49:29,632 INFO L85 PathProgramCache]: Analyzing trace with hash 973586698, now seen corresponding path program 7 times [2024-05-06 17:49:29,633 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:29,633 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:29,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:29,874 INFO L134 CoverageAnalysis]: Checked inductivity of 76 backedges. 16 proven. 56 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 17:49:29,875 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:29,875 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:29,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:30,046 INFO L134 CoverageAnalysis]: Checked inductivity of 76 backedges. 16 proven. 56 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 17:49:30,157 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 17:49:32,222 INFO L85 PathProgramCache]: Analyzing trace with hash -1914300878, now seen corresponding path program 7 times [2024-05-06 17:49:32,223 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:32,223 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:32,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:32,383 INFO L134 CoverageAnalysis]: Checked inductivity of 54 backedges. 19 proven. 1 refuted. 0 times theorem prover too weak. 34 trivial. 0 not checked. [2024-05-06 17:49:32,383 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:32,384 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:32,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:32,552 INFO L134 CoverageAnalysis]: Checked inductivity of 54 backedges. 23 proven. 1 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2024-05-06 17:49:32,860 INFO L85 PathProgramCache]: Analyzing trace with hash 1010014231, now seen corresponding path program 8 times [2024-05-06 17:49:32,860 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:32,860 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:32,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:33,022 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 12 proven. 3 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 17:49:33,022 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:33,023 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:33,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:33,203 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 12 proven. 3 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 17:49:33,302 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 17:49:35,388 INFO L85 PathProgramCache]: Analyzing trace with hash 70510975, now seen corresponding path program 8 times [2024-05-06 17:49:35,389 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:35,389 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:35,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:35,640 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 17:49:35,641 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:35,641 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:35,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:35,812 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 17:49:36,124 INFO L85 PathProgramCache]: Analyzing trace with hash -782497692, now seen corresponding path program 9 times [2024-05-06 17:49:36,125 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:36,125 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:36,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:39,133 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-06 17:49:39,133 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:39,134 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:39,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:41,465 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-06 17:49:41,577 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 17:49:43,155 INFO L85 PathProgramCache]: Analyzing trace with hash 309388812, now seen corresponding path program 9 times [2024-05-06 17:49:43,155 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:43,155 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:43,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:46,066 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-06 17:49:46,066 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:46,066 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:46,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:48,731 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-06 17:49:49,133 INFO L85 PathProgramCache]: Analyzing trace with hash -855410464, now seen corresponding path program 7 times [2024-05-06 17:49:49,133 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:49,133 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:49,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:49,304 INFO L134 CoverageAnalysis]: Checked inductivity of 76 backedges. 16 proven. 56 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 17:49:49,304 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:49,305 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:49,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:49,549 INFO L134 CoverageAnalysis]: Checked inductivity of 76 backedges. 16 proven. 56 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 17:49:49,660 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 17:49:50,023 INFO L85 PathProgramCache]: Analyzing trace with hash -292060792, now seen corresponding path program 7 times [2024-05-06 17:49:50,023 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:50,023 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:50,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:50,195 INFO L134 CoverageAnalysis]: Checked inductivity of 54 backedges. 23 proven. 1 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2024-05-06 17:49:50,196 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:50,196 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:50,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:50,365 INFO L134 CoverageAnalysis]: Checked inductivity of 54 backedges. 19 proven. 1 refuted. 0 times theorem prover too weak. 34 trivial. 0 not checked. [2024-05-06 17:49:50,697 INFO L85 PathProgramCache]: Analyzing trace with hash 815315309, now seen corresponding path program 8 times [2024-05-06 17:49:50,698 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:50,698 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:50,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:50,855 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 14 proven. 1 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 17:49:50,855 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:50,856 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:50,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:51,017 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 14 proven. 1 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 17:49:51,115 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 17:49:53,196 INFO L85 PathProgramCache]: Analyzing trace with hash -37970347, now seen corresponding path program 8 times [2024-05-06 17:49:53,196 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:53,196 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:53,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:53,348 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 3 proven. 1 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 17:49:53,348 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:53,348 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:53,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:53,592 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 17:49:53,972 INFO L85 PathProgramCache]: Analyzing trace with hash 2033840954, now seen corresponding path program 9 times [2024-05-06 17:49:53,972 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:53,973 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:54,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:49:57,348 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-06 17:49:57,348 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:49:57,348 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:49:57,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:01,054 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-06 17:50:01,162 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 17:50:03,250 INFO L85 PathProgramCache]: Analyzing trace with hash 9978978, now seen corresponding path program 9 times [2024-05-06 17:50:03,250 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:03,250 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:03,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:07,068 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-06 17:50:07,069 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:07,069 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:07,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:09,720 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-05-06 17:50:09,844 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 17:50:09,938 INFO L85 PathProgramCache]: Analyzing trace with hash -1044256843, now seen corresponding path program 2 times [2024-05-06 17:50:09,938 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:09,938 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:09,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:10,054 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2024-05-06 17:50:10,055 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:10,055 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:10,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:10,171 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2024-05-06 17:50:10,291 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 17:50:10,390 INFO L85 PathProgramCache]: Analyzing trace with hash -1127906374, now seen corresponding path program 3 times [2024-05-06 17:50:10,390 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:10,391 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:10,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:10,513 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2024-05-06 17:50:10,513 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:10,513 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:10,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:10,634 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2024-05-06 17:50:10,760 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 17:50:10,760 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 29 [2024-05-06 17:50:10,858 INFO L85 PathProgramCache]: Analyzing trace with hash 601616367, now seen corresponding path program 2 times [2024-05-06 17:50:10,858 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:10,859 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:10,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:10,993 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 55 trivial. 0 not checked. [2024-05-06 17:50:10,994 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:10,994 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:11,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:11,124 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 55 trivial. 0 not checked. [2024-05-06 17:50:11,269 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 17:50:11,269 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 29 [2024-05-06 17:50:11,447 INFO L85 PathProgramCache]: Analyzing trace with hash 1082874295, now seen corresponding path program 2 times [2024-05-06 17:50:11,447 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:11,448 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:11,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:11,575 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 55 trivial. 0 not checked. [2024-05-06 17:50:11,575 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:11,575 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:11,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:11,703 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 55 trivial. 0 not checked. [2024-05-06 17:50:11,828 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 17:50:11,828 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 29 [2024-05-06 17:50:11,923 INFO L85 PathProgramCache]: Analyzing trace with hash -1274003286, now seen corresponding path program 3 times [2024-05-06 17:50:11,923 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:11,924 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:11,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:12,047 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2024-05-06 17:50:12,047 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:12,047 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:12,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:12,171 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2024-05-06 17:50:12,304 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 17:50:12,305 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 29 [2024-05-06 17:50:12,423 INFO L85 PathProgramCache]: Analyzing trace with hash 1853654428, now seen corresponding path program 3 times [2024-05-06 17:50:12,423 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:12,423 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:12,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:12,546 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2024-05-06 17:50:12,546 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:12,546 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:12,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:12,667 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2024-05-06 17:50:12,793 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 17:50:12,898 INFO L85 PathProgramCache]: Analyzing trace with hash 1636354527, now seen corresponding path program 2 times [2024-05-06 17:50:12,899 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:12,899 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:12,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:13,019 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2024-05-06 17:50:13,019 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:13,020 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:13,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:13,236 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2024-05-06 17:50:13,352 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 17:50:13,444 INFO L85 PathProgramCache]: Analyzing trace with hash 1226896848, now seen corresponding path program 3 times [2024-05-06 17:50:13,444 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:13,445 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:13,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:13,581 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2024-05-06 17:50:13,581 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:13,581 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:13,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:13,709 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2024-05-06 17:50:13,833 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 17:50:13,833 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 29 [2024-05-06 17:50:13,943 INFO L85 PathProgramCache]: Analyzing trace with hash -484244603, now seen corresponding path program 2 times [2024-05-06 17:50:13,943 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:13,944 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:13,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:14,078 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 55 trivial. 0 not checked. [2024-05-06 17:50:14,078 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:14,079 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:14,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:14,212 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 55 trivial. 0 not checked. [2024-05-06 17:50:14,356 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 17:50:14,356 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 29 [2024-05-06 17:50:14,474 INFO L85 PathProgramCache]: Analyzing trace with hash 216562529, now seen corresponding path program 2 times [2024-05-06 17:50:14,474 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:14,475 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:14,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:14,603 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 55 trivial. 0 not checked. [2024-05-06 17:50:14,604 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:14,604 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:14,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:14,731 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 55 trivial. 0 not checked. [2024-05-06 17:50:14,861 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 17:50:14,861 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 29 [2024-05-06 17:50:14,947 INFO L85 PathProgramCache]: Analyzing trace with hash -1289547436, now seen corresponding path program 3 times [2024-05-06 17:50:14,948 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:14,948 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:14,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:15,162 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2024-05-06 17:50:15,162 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:15,162 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:15,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:15,287 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2024-05-06 17:50:15,430 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 17:50:15,430 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 29 [2024-05-06 17:50:15,557 INFO L85 PathProgramCache]: Analyzing trace with hash -86509646, now seen corresponding path program 3 times [2024-05-06 17:50:15,557 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:15,557 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:15,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:15,686 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2024-05-06 17:50:15,686 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:15,686 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:15,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:15,809 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2024-05-06 17:50:15,941 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 17:50:16,035 INFO L85 PathProgramCache]: Analyzing trace with hash 1848694903, now seen corresponding path program 2 times [2024-05-06 17:50:16,035 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:16,035 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:16,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:16,157 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2024-05-06 17:50:16,158 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:16,158 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:16,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:16,278 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2024-05-06 17:50:16,398 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 17:50:16,499 INFO L85 PathProgramCache]: Analyzing trace with hash 1244618296, now seen corresponding path program 3 times [2024-05-06 17:50:16,499 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:16,499 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:16,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:16,620 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2024-05-06 17:50:16,620 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:16,620 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:16,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:16,741 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2024-05-06 17:50:16,892 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 17:50:16,892 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 29 [2024-05-06 17:50:16,976 INFO L85 PathProgramCache]: Analyzing trace with hash -1744923155, now seen corresponding path program 2 times [2024-05-06 17:50:16,976 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:16,976 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:16,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:17,201 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 55 trivial. 0 not checked. [2024-05-06 17:50:17,202 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:17,202 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:17,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:17,329 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 55 trivial. 0 not checked. [2024-05-06 17:50:17,482 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 17:50:17,482 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 29 [2024-05-06 17:50:17,597 INFO L85 PathProgramCache]: Analyzing trace with hash -1902314503, now seen corresponding path program 2 times [2024-05-06 17:50:17,597 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:17,598 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:17,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:17,727 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 55 trivial. 0 not checked. [2024-05-06 17:50:17,727 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:17,727 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:17,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:17,853 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 55 trivial. 0 not checked. [2024-05-06 17:50:17,976 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 17:50:17,976 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 29 [2024-05-06 17:50:18,080 INFO L85 PathProgramCache]: Analyzing trace with hash -740182548, now seen corresponding path program 3 times [2024-05-06 17:50:18,081 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:18,081 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:18,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:18,208 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2024-05-06 17:50:18,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:18,208 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:18,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:18,332 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2024-05-06 17:50:18,468 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 17:50:18,468 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 29 [2024-05-06 17:50:18,596 INFO L85 PathProgramCache]: Analyzing trace with hash -68788198, now seen corresponding path program 3 times [2024-05-06 17:50:18,596 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:18,596 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:18,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:18,720 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2024-05-06 17:50:18,720 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:18,720 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:18,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:18,944 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2024-05-06 17:50:19,076 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 17:50:19,161 INFO L85 PathProgramCache]: Analyzing trace with hash 1652181398, now seen corresponding path program 7 times [2024-05-06 17:50:19,161 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:19,161 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:19,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:19,280 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 27 refuted. 0 times theorem prover too weak. 34 trivial. 0 not checked. [2024-05-06 17:50:19,280 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:19,280 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:19,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:19,399 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 27 refuted. 0 times theorem prover too weak. 34 trivial. 0 not checked. [2024-05-06 17:50:19,727 INFO L85 PathProgramCache]: Analyzing trace with hash 26737337, now seen corresponding path program 8 times [2024-05-06 17:50:19,727 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:19,727 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:19,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:19,933 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 24 proven. 59 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 17:50:19,933 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:19,933 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:19,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:20,135 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 24 proven. 59 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 17:50:20,249 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 17:50:20,327 INFO L85 PathProgramCache]: Analyzing trace with hash 483577505, now seen corresponding path program 5 times [2024-05-06 17:50:20,327 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:20,327 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:20,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:20,516 INFO L134 CoverageAnalysis]: Checked inductivity of 76 backedges. 21 proven. 48 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 17:50:20,516 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:20,516 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:20,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:20,805 INFO L134 CoverageAnalysis]: Checked inductivity of 76 backedges. 21 proven. 48 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 17:50:21,127 INFO L85 PathProgramCache]: Analyzing trace with hash -621072506, now seen corresponding path program 9 times [2024-05-06 17:50:21,127 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:21,128 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:21,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:21,318 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 3 proven. 56 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 17:50:21,318 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:21,318 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:21,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:21,498 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 3 proven. 56 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 17:50:21,594 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 17:50:22,037 INFO L85 PathProgramCache]: Analyzing trace with hash -1063374930, now seen corresponding path program 6 times [2024-05-06 17:50:22,037 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:22,037 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:22,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:22,167 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 1 proven. 27 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 17:50:22,167 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:22,167 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:22,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:22,313 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 1 proven. 27 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 17:50:22,646 INFO L85 PathProgramCache]: Analyzing trace with hash -1947538029, now seen corresponding path program 10 times [2024-05-06 17:50:22,647 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:22,647 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:22,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:22,864 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 27 refuted. 0 times theorem prover too weak. 34 trivial. 0 not checked. [2024-05-06 17:50:22,865 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:22,865 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:22,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:22,989 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 27 refuted. 0 times theorem prover too weak. 34 trivial. 0 not checked. [2024-05-06 17:50:23,301 INFO L85 PathProgramCache]: Analyzing trace with hash 505173284, now seen corresponding path program 11 times [2024-05-06 17:50:23,301 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:23,301 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:23,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:23,507 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 24 proven. 59 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 17:50:23,507 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:23,507 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:23,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:23,709 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 24 proven. 59 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 17:50:23,819 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 17:50:25,888 INFO L85 PathProgramCache]: Analyzing trace with hash 1342579404, now seen corresponding path program 7 times [2024-05-06 17:50:25,888 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:25,888 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:25,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:26,080 INFO L134 CoverageAnalysis]: Checked inductivity of 76 backedges. 21 proven. 48 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 17:50:26,080 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:26,081 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:26,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:26,280 INFO L134 CoverageAnalysis]: Checked inductivity of 76 backedges. 21 proven. 48 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 17:50:26,650 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 17:50:27,169 INFO L85 PathProgramCache]: Analyzing trace with hash -1667250023, now seen corresponding path program 8 times [2024-05-06 17:50:27,169 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:27,169 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:27,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:27,299 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 1 proven. 27 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 17:50:27,299 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:50:27,299 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:50:27,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:50:27,432 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 1 proven. 27 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 17:51:00,849 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 27 [2024-05-06 17:51:01,439 INFO L85 PathProgramCache]: Analyzing trace with hash -1500405191, now seen corresponding path program 1 times [2024-05-06 17:51:01,439 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:51:01,440 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:51:01,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 17:51:01,464 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 17:51:01,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 17:51:01,679 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 60 treesize of output 44 [2024-05-06 17:51:04,341 INFO L85 PathProgramCache]: Analyzing trace with hash 732080276, now seen corresponding path program 1 times [2024-05-06 17:51:04,341 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:51:04,342 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:51:04,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:51:04,716 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 17:51:04,716 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:51:04,719 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:51:04,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:51:04,769 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 17:51:04,769 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-05-06 17:51:04,779 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2832, Invalid=154380, Unknown=0, NotChecked=0, Total=157212 [2024-05-06 17:51:21,055 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 27 [2024-05-06 17:51:21,480 INFO L85 PathProgramCache]: Analyzing trace with hash 1219667850, now seen corresponding path program 1 times [2024-05-06 17:51:21,482 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:51:21,482 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:51:21,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 17:51:21,506 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 17:51:21,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 17:51:22,653 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 27 [2024-05-06 17:51:23,042 INFO L85 PathProgramCache]: Analyzing trace with hash -1864864847, now seen corresponding path program 1 times [2024-05-06 17:51:23,043 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:51:23,043 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:51:23,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 17:51:23,062 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 17:51:23,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 17:51:23,181 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 60 treesize of output 44 [2024-05-06 17:51:25,466 INFO L85 PathProgramCache]: Analyzing trace with hash -1976234468, now seen corresponding path program 1 times [2024-05-06 17:51:25,466 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:51:25,466 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:51:25,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 17:51:25,486 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 17:51:25,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 17:51:25,620 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 27 [2024-05-06 17:51:25,901 INFO L85 PathProgramCache]: Analyzing trace with hash -202470274, now seen corresponding path program 1 times [2024-05-06 17:51:25,901 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:51:25,902 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:51:25,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:51:28,594 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:51:28,595 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:51:28,595 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:51:28,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:51:30,029 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:51:30,125 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 27 [2024-05-06 17:51:30,988 INFO L85 PathProgramCache]: Analyzing trace with hash -255599379, now seen corresponding path program 2 times [2024-05-06 17:51:30,989 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:51:30,989 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:51:31,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:51:32,163 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 30 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:51:32,163 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:51:32,164 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:51:32,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:51:32,681 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 30 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:51:32,798 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 30 [2024-05-06 17:51:33,096 INFO L85 PathProgramCache]: Analyzing trace with hash -110873796, now seen corresponding path program 1 times [2024-05-06 17:51:33,097 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:51:33,097 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:51:33,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:51:33,641 INFO L134 CoverageAnalysis]: Checked inductivity of 54 backedges. 19 proven. 30 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 17:51:33,641 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:51:33,641 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:51:33,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:51:34,062 INFO L134 CoverageAnalysis]: Checked inductivity of 54 backedges. 19 proven. 30 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 17:51:34,160 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 52 treesize of output 36 [2024-05-06 17:51:34,436 INFO L85 PathProgramCache]: Analyzing trace with hash 470403467, now seen corresponding path program 1 times [2024-05-06 17:51:34,436 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:51:34,436 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:51:34,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:51:35,026 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:51:35,027 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:51:35,027 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:51:35,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:51:35,930 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:51:36,027 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 30 [2024-05-06 17:51:36,534 INFO L85 PathProgramCache]: Analyzing trace with hash 1978472267, now seen corresponding path program 2 times [2024-05-06 17:51:36,534 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:51:36,534 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:51:36,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:51:37,467 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 27 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 17:51:37,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:51:37,468 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:51:37,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:51:39,537 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 27 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 17:51:39,627 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 52 treesize of output 36 [2024-05-06 17:51:39,738 INFO L85 PathProgramCache]: Analyzing trace with hash 768346906, now seen corresponding path program 2 times [2024-05-06 17:51:39,739 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:51:39,739 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:51:39,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:51:41,822 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:51:41,822 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:51:41,822 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:51:41,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:51:44,018 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:51:44,123 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 27 [2024-05-06 17:51:45,133 INFO L85 PathProgramCache]: Analyzing trace with hash 1037010178, now seen corresponding path program 1 times [2024-05-06 17:51:45,133 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:51:45,133 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:51:45,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:51:46,348 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:51:46,349 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:51:46,349 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:51:46,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:51:55,195 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 0 proven. 29 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-05-06 17:51:55,297 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 27 [2024-05-06 17:51:56,280 INFO L85 PathProgramCache]: Analyzing trace with hash 76667625, now seen corresponding path program 2 times [2024-05-06 17:51:56,280 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:51:56,280 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:51:56,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:51:56,678 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 30 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:51:56,678 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:51:56,678 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:51:56,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:51:58,006 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 30 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:51:58,104 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 30 [2024-05-06 17:51:58,616 INFO L85 PathProgramCache]: Analyzing trace with hash -1051996480, now seen corresponding path program 1 times [2024-05-06 17:51:58,617 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:51:58,617 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:51:58,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:51:59,132 INFO L134 CoverageAnalysis]: Checked inductivity of 54 backedges. 19 proven. 30 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 17:51:59,132 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:51:59,132 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:51:59,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:51:59,553 INFO L134 CoverageAnalysis]: Checked inductivity of 54 backedges. 19 proven. 30 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 17:51:59,647 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 52 treesize of output 36 [2024-05-06 17:51:59,770 INFO L85 PathProgramCache]: Analyzing trace with hash -838381809, now seen corresponding path program 1 times [2024-05-06 17:51:59,770 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:51:59,770 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:51:59,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:52:00,547 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:52:00,547 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:52:00,547 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:52:00,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:52:02,326 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:52:02,408 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 30 [2024-05-06 17:52:02,898 INFO L85 PathProgramCache]: Analyzing trace with hash -1984228025, now seen corresponding path program 2 times [2024-05-06 17:52:02,898 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:52:02,899 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:52:02,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:52:04,763 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 27 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 17:52:04,763 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:52:04,763 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:52:04,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:52:06,236 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 27 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 17:52:06,328 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 52 treesize of output 36 [2024-05-06 17:52:06,449 INFO L85 PathProgramCache]: Analyzing trace with hash -667951338, now seen corresponding path program 2 times [2024-05-06 17:52:06,449 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:52:06,449 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:52:06,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:52:07,923 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:52:07,924 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:52:07,924 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:52:07,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:52:09,643 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:52:09,743 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 27 [2024-05-06 17:52:12,217 INFO L85 PathProgramCache]: Analyzing trace with hash -147995204, now seen corresponding path program 1 times [2024-05-06 17:52:12,217 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:52:12,217 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:52:12,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:52:13,757 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:52:13,758 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:52:13,758 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:52:13,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:52:15,809 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:52:15,900 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 27 [2024-05-06 17:52:16,904 INFO L85 PathProgramCache]: Analyzing trace with hash -2122311569, now seen corresponding path program 2 times [2024-05-06 17:52:16,905 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:52:16,905 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:52:16,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:52:17,294 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 30 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:52:17,294 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:52:17,294 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:52:17,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:52:18,969 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 3 proven. 31 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:52:19,076 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 30 [2024-05-06 17:52:19,532 INFO L85 PathProgramCache]: Analyzing trace with hash 1245723386, now seen corresponding path program 1 times [2024-05-06 17:52:19,533 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:52:19,533 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:52:19,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:52:19,955 INFO L134 CoverageAnalysis]: Checked inductivity of 54 backedges. 19 proven. 30 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 17:52:19,955 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:52:19,955 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:52:19,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:52:20,361 INFO L134 CoverageAnalysis]: Checked inductivity of 54 backedges. 19 proven. 30 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 17:52:20,450 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 52 treesize of output 36 [2024-05-06 17:52:20,573 INFO L85 PathProgramCache]: Analyzing trace with hash -2030265271, now seen corresponding path program 1 times [2024-05-06 17:52:20,573 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:52:20,573 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:52:20,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:52:22,444 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:52:22,444 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:52:22,444 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:52:22,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:52:23,113 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:52:23,203 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 30 [2024-05-06 17:52:23,698 INFO L85 PathProgramCache]: Analyzing trace with hash 111760077, now seen corresponding path program 2 times [2024-05-06 17:52:23,698 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:52:23,699 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:52:23,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:52:24,430 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 27 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 17:52:24,430 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:52:24,430 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:52:24,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:52:25,196 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 27 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 17:52:25,285 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 52 treesize of output 36 [2024-05-06 17:52:25,410 INFO L85 PathProgramCache]: Analyzing trace with hash 809737116, now seen corresponding path program 2 times [2024-05-06 17:52:25,410 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:52:25,410 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:52:25,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:52:26,907 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:52:26,907 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:52:26,907 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:52:26,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:52:28,826 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:52:29,248 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 27 [2024-05-06 17:52:30,297 INFO L85 PathProgramCache]: Analyzing trace with hash 1915281452, now seen corresponding path program 1 times [2024-05-06 17:52:30,297 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:52:30,297 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:52:30,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 17:52:30,318 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 17:52:30,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 17:52:30,460 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 60 treesize of output 44 [2024-05-06 17:52:32,868 INFO L85 PathProgramCache]: Analyzing trace with hash -755816191, now seen corresponding path program 2 times [2024-05-06 17:52:32,868 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:52:32,868 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:52:32,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:52:33,122 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 34 trivial. 0 not checked. [2024-05-06 17:52:33,122 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:52:33,122 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:52:33,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:52:33,180 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 34 trivial. 0 not checked. [2024-05-06 17:52:33,181 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-05-06 17:52:33,193 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4238, Invalid=243268, Unknown=0, NotChecked=0, Total=247506 [2024-05-06 17:52:51,062 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 27 [2024-05-06 17:52:52,183 INFO L85 PathProgramCache]: Analyzing trace with hash 1219667850, now seen corresponding path program 2 times [2024-05-06 17:52:52,183 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:52:52,184 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:52:52,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 17:52:52,204 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 17:52:52,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 17:52:53,352 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 27 [2024-05-06 17:52:53,566 INFO L85 PathProgramCache]: Analyzing trace with hash -1864864847, now seen corresponding path program 2 times [2024-05-06 17:52:53,566 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:52:53,566 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:52:53,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 17:52:53,587 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 17:52:53,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 17:52:53,714 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 60 treesize of output 44 [2024-05-06 17:52:56,035 INFO L85 PathProgramCache]: Analyzing trace with hash -1976234468, now seen corresponding path program 2 times [2024-05-06 17:52:56,035 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:52:56,035 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:52:56,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 17:52:56,055 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 17:52:56,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 17:52:56,368 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 27 [2024-05-06 17:52:56,863 INFO L85 PathProgramCache]: Analyzing trace with hash -202470274, now seen corresponding path program 3 times [2024-05-06 17:52:56,864 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:52:56,864 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:52:56,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:52:58,793 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:52:58,793 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:52:58,793 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:52:58,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:53:00,420 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:53:00,523 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 27 [2024-05-06 17:53:01,148 INFO L85 PathProgramCache]: Analyzing trace with hash -255599379, now seen corresponding path program 4 times [2024-05-06 17:53:01,149 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:53:01,149 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:53:01,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:53:01,570 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 30 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:53:01,570 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 17:53:01,570 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 17:53:01,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 17:53:01,969 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 4 proven. 30 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 17:53:02,204 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 27