/root/.sdkman/candidates/java/current/bin/java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data -s ../benchexec/../../../trunk/examples/settings/gemcutter/NewStatesSleep.epf --traceabstraction.dfs.order.used.in.por LOOP_LOCKSTEP --traceabstraction.additional.conditional.commutativity.checking DFS --traceabstraction.criterion.for.conditional.commutativity.checking DEFAULT --traceabstraction.use.limited.checks.recommended.for.dfs true --traceabstraction.limit.for.limited.checks 50 -tc ../benchexec/../../../trunk/examples/toolchains/AutomizerCInline.xml -i ../../../trunk/examples/svcomp/weaver/popl20-more-buffer-mult.wvr.c -------------------------------------------------------------------------------- This is Ultimate 0.2.4-wip.dk.conditional-comm-17da818-m [2024-05-06 18:01:46,371 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-05-06 18:01:46,441 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/../benchexec/../../../trunk/examples/settings/gemcutter/NewStatesSleep.epf [2024-05-06 18:01:46,445 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-05-06 18:01:46,445 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-05-06 18:01:46,474 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-05-06 18:01:46,475 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-05-06 18:01:46,475 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-05-06 18:01:46,476 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2024-05-06 18:01:46,480 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2024-05-06 18:01:46,480 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-05-06 18:01:46,480 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-05-06 18:01:46,481 INFO L153 SettingsManager]: * Use SBE=true [2024-05-06 18:01:46,482 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-05-06 18:01:46,483 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2024-05-06 18:01:46,483 INFO L153 SettingsManager]: * sizeof long=4 [2024-05-06 18:01:46,483 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-05-06 18:01:46,483 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-05-06 18:01:46,483 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-05-06 18:01:46,483 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2024-05-06 18:01:46,484 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2024-05-06 18:01:46,484 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2024-05-06 18:01:46,484 INFO L153 SettingsManager]: * sizeof long double=12 [2024-05-06 18:01:46,484 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-05-06 18:01:46,485 INFO L153 SettingsManager]: * Use constant arrays=true [2024-05-06 18:01:46,485 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-05-06 18:01:46,485 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-05-06 18:01:46,485 INFO L153 SettingsManager]: * To the following directory=./dump/ [2024-05-06 18:01:46,485 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-05-06 18:01:46,485 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2024-05-06 18:01:46,487 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-05-06 18:01:46,487 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2024-05-06 18:01:46,487 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2024-05-06 18:01:46,487 INFO L153 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2024-05-06 18:01:46,487 INFO L153 SettingsManager]: * Partial Order Reduction in concurrent analysis=SLEEP_NEW_STATES [2024-05-06 18:01:46,487 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2024-05-06 18:01:46,488 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-05-06 18:01:46,488 INFO L153 SettingsManager]: * Automaton type used in concurrency analysis=PARTIAL_ORDER_FA [2024-05-06 18:01:46,488 INFO L153 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2024-05-06 18:01:46,488 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: DFS Order used in POR -> LOOP_LOCKSTEP Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Additional conditional commutativity checking -> DFS Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Criterion for conditional commutativity checking -> DEFAULT Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: use limited checks (recommended for DFS) -> true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Limit for limited checks -> 50 [2024-05-06 18:01:46,689 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-05-06 18:01:46,707 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-05-06 18:01:46,709 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-05-06 18:01:46,710 INFO L270 PluginConnector]: Initializing CDTParser... [2024-05-06 18:01:46,710 INFO L274 PluginConnector]: CDTParser initialized [2024-05-06 18:01:46,711 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/../../../trunk/examples/svcomp/weaver/popl20-more-buffer-mult.wvr.c [2024-05-06 18:01:47,873 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-05-06 18:01:48,056 INFO L384 CDTParser]: Found 1 translation units. [2024-05-06 18:01:48,056 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/weaver/popl20-more-buffer-mult.wvr.c [2024-05-06 18:01:48,064 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/data/7db6f6e64/0a223cba9b384c59b3f0626db209fc9f/FLAGf24cda0ba [2024-05-06 18:01:48,076 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/data/7db6f6e64/0a223cba9b384c59b3f0626db209fc9f [2024-05-06 18:01:48,079 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-05-06 18:01:48,080 INFO L133 ToolchainWalker]: Walking toolchain with 5 elements. [2024-05-06 18:01:48,081 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-05-06 18:01:48,081 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-05-06 18:01:48,085 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-05-06 18:01:48,086 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.05 06:01:48" (1/1) ... [2024-05-06 18:01:48,087 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2b431fcc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:01:48, skipping insertion in model container [2024-05-06 18:01:48,087 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.05 06:01:48" (1/1) ... [2024-05-06 18:01:48,116 INFO L177 MainTranslator]: Built tables and reachable declarations [2024-05-06 18:01:48,330 WARN L240 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/weaver/popl20-more-buffer-mult.wvr.c[4218,4231] [2024-05-06 18:01:48,348 INFO L209 PostProcessor]: Analyzing one entry point: main [2024-05-06 18:01:48,360 INFO L202 MainTranslator]: Completed pre-run [2024-05-06 18:01:48,408 WARN L240 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/weaver/popl20-more-buffer-mult.wvr.c[4218,4231] [2024-05-06 18:01:48,412 INFO L209 PostProcessor]: Analyzing one entry point: main [2024-05-06 18:01:48,418 WARN L675 CHandler]: The function __VERIFIER_atomic_begin is called, but not defined or handled by StandardFunctionHandler. [2024-05-06 18:01:48,419 WARN L675 CHandler]: The function __VERIFIER_atomic_end is called, but not defined or handled by StandardFunctionHandler. [2024-05-06 18:01:48,460 INFO L206 MainTranslator]: Completed translation [2024-05-06 18:01:48,461 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:01:48 WrapperNode [2024-05-06 18:01:48,461 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-05-06 18:01:48,462 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-05-06 18:01:48,462 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-05-06 18:01:48,462 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-05-06 18:01:48,468 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:01:48" (1/1) ... [2024-05-06 18:01:48,487 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:01:48" (1/1) ... [2024-05-06 18:01:48,527 INFO L138 Inliner]: procedures = 27, calls = 80, calls flagged for inlining = 18, calls inlined = 22, statements flattened = 316 [2024-05-06 18:01:48,527 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-05-06 18:01:48,528 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-05-06 18:01:48,528 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-05-06 18:01:48,528 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-05-06 18:01:48,536 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:01:48" (1/1) ... [2024-05-06 18:01:48,537 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:01:48" (1/1) ... [2024-05-06 18:01:48,544 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:01:48" (1/1) ... [2024-05-06 18:01:48,544 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:01:48" (1/1) ... [2024-05-06 18:01:48,557 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:01:48" (1/1) ... [2024-05-06 18:01:48,560 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:01:48" (1/1) ... [2024-05-06 18:01:48,562 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:01:48" (1/1) ... [2024-05-06 18:01:48,564 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:01:48" (1/1) ... [2024-05-06 18:01:48,566 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-05-06 18:01:48,567 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-05-06 18:01:48,567 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-05-06 18:01:48,567 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-05-06 18:01:48,567 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:01:48" (1/1) ... [2024-05-06 18:01:48,572 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2024-05-06 18:01:48,582 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:01:48,610 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2024-05-06 18:01:48,627 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2024-05-06 18:01:48,650 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-05-06 18:01:48,650 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2024-05-06 18:01:48,650 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2024-05-06 18:01:48,650 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2024-05-06 18:01:48,650 INFO L130 BoogieDeclarations]: Found specification of procedure thread1 [2024-05-06 18:01:48,650 INFO L138 BoogieDeclarations]: Found implementation of procedure thread1 [2024-05-06 18:01:48,650 INFO L130 BoogieDeclarations]: Found specification of procedure thread2 [2024-05-06 18:01:48,650 INFO L138 BoogieDeclarations]: Found implementation of procedure thread2 [2024-05-06 18:01:48,650 INFO L130 BoogieDeclarations]: Found specification of procedure thread3 [2024-05-06 18:01:48,650 INFO L138 BoogieDeclarations]: Found implementation of procedure thread3 [2024-05-06 18:01:48,650 INFO L130 BoogieDeclarations]: Found specification of procedure thread4 [2024-05-06 18:01:48,651 INFO L138 BoogieDeclarations]: Found implementation of procedure thread4 [2024-05-06 18:01:48,651 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2024-05-06 18:01:48,651 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2024-05-06 18:01:48,651 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2024-05-06 18:01:48,651 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2024-05-06 18:01:48,651 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-05-06 18:01:48,651 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-05-06 18:01:48,651 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2024-05-06 18:01:48,652 WARN L213 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to OneNontrivialStatement [2024-05-06 18:01:48,765 INFO L241 CfgBuilder]: Building ICFG [2024-05-06 18:01:48,767 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2024-05-06 18:01:49,097 INFO L282 CfgBuilder]: Performing block encoding [2024-05-06 18:01:49,246 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-05-06 18:01:49,246 INFO L309 CfgBuilder]: Removed 6 assume(true) statements. [2024-05-06 18:01:49,248 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.05 06:01:49 BoogieIcfgContainer [2024-05-06 18:01:49,248 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-05-06 18:01:49,252 INFO L112 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2024-05-06 18:01:49,252 INFO L270 PluginConnector]: Initializing TraceAbstraction... [2024-05-06 18:01:49,255 INFO L274 PluginConnector]: TraceAbstraction initialized [2024-05-06 18:01:49,255 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 06.05 06:01:48" (1/3) ... [2024-05-06 18:01:49,256 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@520f7020 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.05 06:01:49, skipping insertion in model container [2024-05-06 18:01:49,256 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:01:48" (2/3) ... [2024-05-06 18:01:49,256 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@520f7020 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.05 06:01:49, skipping insertion in model container [2024-05-06 18:01:49,256 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.05 06:01:49" (3/3) ... [2024-05-06 18:01:49,257 INFO L112 eAbstractionObserver]: Analyzing ICFG popl20-more-buffer-mult.wvr.c [2024-05-06 18:01:49,265 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2024-05-06 18:01:49,273 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2024-05-06 18:01:49,274 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2024-05-06 18:01:49,274 INFO L514 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2024-05-06 18:01:49,332 INFO L144 ThreadInstanceAdder]: Constructed 4 joinOtherThreadTransitions. [2024-05-06 18:01:49,377 INFO L100 denceProviderFactory]: Independence Relation #1: [IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=true, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2024-05-06 18:01:49,378 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 [2024-05-06 18:01:49,378 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:01:49,381 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 (exit command is (exit), workingDir is null) [2024-05-06 18:01:49,397 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 (2)] Waiting until timeout for monitored process [2024-05-06 18:01:49,437 INFO L188 artialOrderCegarLoop]: Running PartialOrderCegarLoop with 1 independence relations. [2024-05-06 18:01:49,452 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:01:49,453 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2024-05-06 18:01:49,460 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=PARTIAL_ORDER_FA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopHeads, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@627c0bc2, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms], mConComChecker=DFS, mConComCheckerCriterion=DEFAULT, mConComCheckerLimitedChecksCriterion=true, mConComCheckerCriterionLimit=50, mConComCheckerRandomProb=100, mConComCheckerRandomSeed=123, mConComCheckerConditionCriterion=false [2024-05-06 18:01:49,460 INFO L358 AbstractCegarLoop]: Starting to check reachability of 5 error locations. [2024-05-06 18:01:49,948 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:01:50,015 INFO L85 PathProgramCache]: Analyzing trace with hash -1264897234, now seen corresponding path program 1 times [2024-05-06 18:01:50,020 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:01:50,020 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:01:50,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:01:50,494 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:01:50,494 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:01:50,494 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:01:50,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:01:50,607 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:01:50,639 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-05-06 18:01:50,641 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-05-06 18:01:50,921 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:01:50,976 INFO L85 PathProgramCache]: Analyzing trace with hash 750604411, now seen corresponding path program 1 times [2024-05-06 18:01:50,977 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:01:50,977 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:01:51,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:01:51,560 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-06 18:01:51,560 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:01:51,560 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:01:51,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:01:51,794 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-06 18:01:51,795 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-05-06 18:01:51,795 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2024-05-06 18:01:52,161 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:01:52,209 INFO L85 PathProgramCache]: Analyzing trace with hash -476508331, now seen corresponding path program 1 times [2024-05-06 18:01:52,209 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:01:52,209 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:01:52,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:01:52,405 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-06 18:01:52,406 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:01:52,406 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:01:52,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:01:52,603 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-06 18:01:52,604 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-05-06 18:01:52,604 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=143, Unknown=0, NotChecked=0, Total=182 [2024-05-06 18:01:52,852 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:01:52,911 INFO L85 PathProgramCache]: Analyzing trace with hash -1585306233, now seen corresponding path program 1 times [2024-05-06 18:01:52,912 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:01:52,912 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:01:52,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:01:53,186 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:01:53,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:01:53,186 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:01:53,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:01:53,408 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:01:53,490 INFO L85 PathProgramCache]: Analyzing trace with hash -1899852116, now seen corresponding path program 2 times [2024-05-06 18:01:53,491 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:01:53,491 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:01:53,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:01:53,734 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:01:53,734 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:01:53,735 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:01:53,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:01:53,977 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:01:54,127 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:01:54,177 INFO L85 PathProgramCache]: Analyzing trace with hash 352895570, now seen corresponding path program 1 times [2024-05-06 18:01:54,177 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:01:54,177 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:01:54,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:01:54,379 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:01:54,379 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:01:54,380 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:01:54,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:01:54,606 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:01:54,691 INFO L85 PathProgramCache]: Analyzing trace with hash -1945138376, now seen corresponding path program 2 times [2024-05-06 18:01:54,691 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:01:54,691 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:01:54,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:01:54,877 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:01:54,878 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:01:54,879 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:01:54,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:01:55,121 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:01:55,230 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:01:55,270 INFO L85 PathProgramCache]: Analyzing trace with hash 709174153, now seen corresponding path program 3 times [2024-05-06 18:01:55,270 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:01:55,270 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:01:55,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:01:55,553 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:01:55,554 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:01:55,554 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:01:55,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:01:55,844 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:01:55,923 INFO L85 PathProgramCache]: Analyzing trace with hash 509563105, now seen corresponding path program 4 times [2024-05-06 18:01:55,923 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:01:55,923 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:01:55,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:01:56,190 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:01:56,190 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:01:56,190 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:01:56,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:01:56,442 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:01:56,724 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:01:56,725 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:01:57,383 INFO L85 PathProgramCache]: Analyzing trace with hash -891221064, now seen corresponding path program 5 times [2024-05-06 18:01:57,383 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:01:57,383 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:01:57,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:01:57,699 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:01:57,699 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:01:57,700 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:01:57,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:01:57,927 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:01:58,166 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:01:58,166 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:02:03,561 INFO L85 PathProgramCache]: Analyzing trace with hash 1277604235, now seen corresponding path program 6 times [2024-05-06 18:02:03,561 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:03,561 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:03,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:03,849 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:02:03,850 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:03,850 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:03,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:04,199 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:02:04,289 INFO L85 PathProgramCache]: Analyzing trace with hash -2080372961, now seen corresponding path program 7 times [2024-05-06 18:02:04,289 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:04,289 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:04,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:04,597 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:02:04,598 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:04,598 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:04,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:04,953 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:02:05,103 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:02:05,105 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:02:05,290 INFO L85 PathProgramCache]: Analyzing trace with hash 1173252875, now seen corresponding path program 8 times [2024-05-06 18:02:05,290 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:05,291 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:05,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:05,631 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:02:05,632 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:05,632 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:05,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:05,906 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:02:06,035 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:02:06,079 INFO L85 PathProgramCache]: Analyzing trace with hash 2011101617, now seen corresponding path program 9 times [2024-05-06 18:02:06,079 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:06,079 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:06,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:06,415 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:02:06,416 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:06,416 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:06,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:06,689 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:02:06,834 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:02:06,886 INFO L85 PathProgramCache]: Analyzing trace with hash -2121681854, now seen corresponding path program 10 times [2024-05-06 18:02:06,886 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:06,887 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:06,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:07,150 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:02:07,150 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:07,151 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:07,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:07,507 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:02:07,577 INFO L85 PathProgramCache]: Analyzing trace with hash -1347627192, now seen corresponding path program 11 times [2024-05-06 18:02:07,578 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:07,578 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:07,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:07,850 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:02:07,850 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:07,851 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:07,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:08,112 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:02:08,269 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:02:08,270 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:02:08,553 INFO L85 PathProgramCache]: Analyzing trace with hash -2008104048, now seen corresponding path program 12 times [2024-05-06 18:02:08,554 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:08,554 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:08,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:08,787 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:02:08,787 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:08,787 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:08,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:09,032 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:02:09,319 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:02:09,319 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:02:10,191 INFO L85 PathProgramCache]: Analyzing trace with hash 967718707, now seen corresponding path program 13 times [2024-05-06 18:02:10,192 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:10,192 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:10,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:10,458 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:02:10,459 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:10,459 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:10,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:10,694 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:02:10,827 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:02:10,881 INFO L85 PathProgramCache]: Analyzing trace with hash -2030198306, now seen corresponding path program 14 times [2024-05-06 18:02:10,881 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:10,881 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:10,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:11,122 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:02:11,122 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:11,122 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:11,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:11,307 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:02:11,369 INFO L85 PathProgramCache]: Analyzing trace with hash 1488362796, now seen corresponding path program 15 times [2024-05-06 18:02:11,370 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:11,370 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:11,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:11,614 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:02:11,615 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:11,615 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:11,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:11,787 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:02:12,112 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:02:12,112 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:02:14,787 INFO L85 PathProgramCache]: Analyzing trace with hash 92564967, now seen corresponding path program 16 times [2024-05-06 18:02:14,787 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:14,787 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:14,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:15,049 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:02:15,050 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:15,050 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:15,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:15,428 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:02:15,524 INFO L85 PathProgramCache]: Analyzing trace with hash -1425452459, now seen corresponding path program 17 times [2024-05-06 18:02:15,524 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:15,525 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:15,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:15,876 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:02:15,876 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:15,876 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:15,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:16,111 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:02:16,180 INFO L85 PathProgramCache]: Analyzing trace with hash -1239352401, now seen corresponding path program 18 times [2024-05-06 18:02:16,180 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:16,180 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:16,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:16,426 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:02:16,426 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:16,429 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:16,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:16,666 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:02:16,735 INFO L85 PathProgramCache]: Analyzing trace with hash 234782103, now seen corresponding path program 19 times [2024-05-06 18:02:16,735 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:16,735 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:16,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:17,063 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:02:17,063 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:17,064 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:17,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:17,311 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:02:17,449 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:02:17,450 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:02:17,611 INFO L85 PathProgramCache]: Analyzing trace with hash -65490316, now seen corresponding path program 20 times [2024-05-06 18:02:17,612 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:17,612 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:17,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:17,820 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:02:17,820 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:17,821 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:17,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:18,027 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:02:18,295 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:02:18,295 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:02:19,062 INFO L85 PathProgramCache]: Analyzing trace with hash -2030198954, now seen corresponding path program 21 times [2024-05-06 18:02:19,062 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:19,062 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:19,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:19,315 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:02:19,315 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:19,315 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:19,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:19,573 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:02:19,638 INFO L85 PathProgramCache]: Analyzing trace with hash 1488342726, now seen corresponding path program 22 times [2024-05-06 18:02:19,638 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:19,638 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:19,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:19,837 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:02:19,838 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:19,838 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:19,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:20,045 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:02:20,114 INFO L85 PathProgramCache]: Analyzing trace with hash -1106014882, now seen corresponding path program 23 times [2024-05-06 18:02:20,115 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:20,115 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:20,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:20,329 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:02:20,329 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:20,329 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:20,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:20,531 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:02:20,665 INFO L85 PathProgramCache]: Analyzing trace with hash 73277896, now seen corresponding path program 24 times [2024-05-06 18:02:20,666 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:20,666 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:20,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:20,871 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:02:20,871 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:20,872 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:20,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:21,083 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:02:21,238 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:02:21,239 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:02:21,407 INFO L85 PathProgramCache]: Analyzing trace with hash 2020603108, now seen corresponding path program 1 times [2024-05-06 18:02:21,408 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:21,408 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:21,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:21,617 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:02:21,618 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:21,618 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:21,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:21,829 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:02:21,941 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:02:21,986 INFO L85 PathProgramCache]: Analyzing trace with hash -1785812232, now seen corresponding path program 2 times [2024-05-06 18:02:21,986 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:21,986 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:22,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:22,200 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:02:22,200 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:22,200 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:22,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:22,495 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:02:22,614 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:02:22,667 INFO L85 PathProgramCache]: Analyzing trace with hash 2053496923, now seen corresponding path program 3 times [2024-05-06 18:02:22,667 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:22,668 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:22,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:22,874 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:02:22,874 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:22,874 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:22,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:23,074 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:02:23,139 INFO L85 PathProgramCache]: Analyzing trace with hash -766103985, now seen corresponding path program 4 times [2024-05-06 18:02:23,139 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:23,139 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:23,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:23,343 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:02:23,343 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:23,343 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:23,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:23,553 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:02:23,684 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:02:23,684 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:02:23,869 INFO L85 PathProgramCache]: Analyzing trace with hash -1180684201, now seen corresponding path program 5 times [2024-05-06 18:02:23,870 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:23,870 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:23,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:24,074 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:02:24,074 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:24,074 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:24,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:24,349 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:02:24,417 INFO L85 PathProgramCache]: Analyzing trace with hash -63797974, now seen corresponding path program 6 times [2024-05-06 18:02:24,418 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:24,418 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:24,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:24,617 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:02:24,617 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:24,618 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:24,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:24,815 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:02:24,882 INFO L85 PathProgramCache]: Analyzing trace with hash 221129471, now seen corresponding path program 1 times [2024-05-06 18:02:24,882 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:24,882 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:24,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:25,085 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:02:25,086 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:25,086 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:25,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:25,297 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:02:25,437 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:02:25,438 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:02:25,599 INFO L85 PathProgramCache]: Analyzing trace with hash 1108608747, now seen corresponding path program 2 times [2024-05-06 18:02:25,600 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:25,600 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:25,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:25,802 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:02:25,803 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:25,803 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:25,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:26,095 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:02:26,205 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:02:26,254 INFO L85 PathProgramCache]: Analyzing trace with hash 7133649, now seen corresponding path program 3 times [2024-05-06 18:02:26,254 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:26,255 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:26,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:26,459 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:02:26,459 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:26,459 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:26,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:26,671 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:02:26,792 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:02:26,827 INFO L85 PathProgramCache]: Analyzing trace with hash -1205549022, now seen corresponding path program 4 times [2024-05-06 18:02:26,827 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:26,827 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:26,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:27,026 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:02:27,026 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:27,026 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:27,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:27,224 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:02:27,286 INFO L85 PathProgramCache]: Analyzing trace with hash 1282686824, now seen corresponding path program 5 times [2024-05-06 18:02:27,287 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:27,287 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:27,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:27,491 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:02:27,491 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:27,491 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:27,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:27,800 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:02:27,929 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:02:27,930 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:02:28,082 INFO L85 PathProgramCache]: Analyzing trace with hash -1978551376, now seen corresponding path program 6 times [2024-05-06 18:02:28,082 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:28,082 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:28,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:28,332 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:02:28,332 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:28,332 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:28,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:28,528 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:02:28,605 INFO L85 PathProgramCache]: Analyzing trace with hash -1600833574, now seen corresponding path program 1 times [2024-05-06 18:02:28,605 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:28,605 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:28,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:28,819 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:02:28,819 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:28,819 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:28,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:29,029 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:02:29,166 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:02:29,167 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:02:29,331 INFO L85 PathProgramCache]: Analyzing trace with hash 637439622, now seen corresponding path program 2 times [2024-05-06 18:02:29,332 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:29,332 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:29,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:29,535 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:02:29,535 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:29,535 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:29,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:29,736 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:02:29,940 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:02:29,987 INFO L85 PathProgramCache]: Analyzing trace with hash -1714207338, now seen corresponding path program 3 times [2024-05-06 18:02:29,988 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:29,988 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:30,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:30,200 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:02:30,200 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:30,200 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:30,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:30,411 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:02:30,532 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:02:30,573 INFO L85 PathProgramCache]: Analyzing trace with hash -2001569155, now seen corresponding path program 4 times [2024-05-06 18:02:30,573 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:30,573 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:30,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:30,770 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:02:30,770 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:30,771 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:30,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:30,971 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:02:31,036 INFO L85 PathProgramCache]: Analyzing trace with hash -1919100819, now seen corresponding path program 5 times [2024-05-06 18:02:31,037 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:31,037 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:31,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:31,244 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:02:31,244 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:31,244 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:31,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:31,398 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:02:31,514 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:02:31,515 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:02:31,657 INFO L85 PathProgramCache]: Analyzing trace with hash -64566795, now seen corresponding path program 6 times [2024-05-06 18:02:31,657 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:31,657 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:31,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:31,916 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:02:31,916 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:31,917 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:31,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:32,066 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:02:32,153 INFO L85 PathProgramCache]: Analyzing trace with hash -154603358, now seen corresponding path program 25 times [2024-05-06 18:02:32,153 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:32,153 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:32,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:32,322 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:02:32,322 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:32,322 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:32,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:32,488 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:02:32,605 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:02:32,605 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:02:32,748 INFO L85 PathProgramCache]: Analyzing trace with hash 98163022, now seen corresponding path program 26 times [2024-05-06 18:02:32,748 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:32,748 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:32,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:32,903 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:02:32,904 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:32,904 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:32,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:33,054 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:02:33,150 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:02:33,185 INFO L85 PathProgramCache]: Analyzing trace with hash -1251912754, now seen corresponding path program 27 times [2024-05-06 18:02:33,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:33,186 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:33,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:33,341 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:02:33,342 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:33,342 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:33,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:33,585 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:02:33,683 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:02:33,716 INFO L85 PathProgramCache]: Analyzing trace with hash -84814011, now seen corresponding path program 28 times [2024-05-06 18:02:33,716 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:33,716 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:33,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:33,867 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:02:33,867 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:33,867 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:33,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:34,017 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:02:34,071 INFO L85 PathProgramCache]: Analyzing trace with hash 1665733797, now seen corresponding path program 29 times [2024-05-06 18:02:34,072 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:34,072 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:34,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:34,225 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:02:34,225 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:34,225 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:34,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:34,375 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:02:34,502 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:02:34,503 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:02:34,649 INFO L85 PathProgramCache]: Analyzing trace with hash 967095341, now seen corresponding path program 30 times [2024-05-06 18:02:34,649 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:34,649 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:34,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:34,795 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:02:34,795 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:34,795 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:34,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:34,943 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:02:35,291 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:02:35,292 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:02:52,723 WARN L293 SmtUtils]: Spent 14.60s on a formula simplification. DAG size of input: 33 DAG size of output: 28 (called from [L 210] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.abduction.Abducer.solveAbductionProblem) [2024-05-06 18:02:54,731 WARN L854 $PredicateComparison]: unable to prove that (and (forall ((v_~q2~0.base_In_10 Int) (v_~q2~0.offset_In_10 Int)) (= (select (select |c_#memory_int| v_~q2~0.base_In_10) (+ (* c_~q2_front~0 4) v_~q2~0.offset_In_10)) 0)) (forall ((v_~q1~0.offset_In_30 Int) (v_~q1_front~0_In_49 Int) (v_~q1~0.base_In_30 Int)) (let ((.cse0 (select (select |c_#memory_int| v_~q1~0.base_In_30) (+ (* v_~q1_front~0_In_49 4) v_~q1~0.offset_In_30)))) (or (< 4294967295 .cse0) (= .cse0 0) (< (+ .cse0 4294967295) 0) (< v_~q1_front~0_In_49 0))))) is different from false [2024-05-06 18:02:54,734 INFO L85 PathProgramCache]: Analyzing trace with hash 1029788170, now seen corresponding path program 31 times [2024-05-06 18:02:54,734 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:54,734 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:54,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:54,919 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:02:54,919 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:54,919 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:54,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:55,071 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:02:55,201 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:02:55,202 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:02:55,342 INFO L85 PathProgramCache]: Analyzing trace with hash -531160901, now seen corresponding path program 32 times [2024-05-06 18:02:55,342 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:55,342 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:55,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:55,480 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:02:55,480 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:02:55,480 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:02:55,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:02:55,616 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:02:55,844 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:02:55,844 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:03:02,927 INFO L85 PathProgramCache]: Analyzing trace with hash 655509330, now seen corresponding path program 33 times [2024-05-06 18:03:02,927 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:02,927 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:02,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:03,073 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:03:03,073 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:03,073 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:03,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:03,348 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:03:03,434 INFO L85 PathProgramCache]: Analyzing trace with hash -1415698614, now seen corresponding path program 34 times [2024-05-06 18:03:03,434 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:03,434 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:03,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:03,581 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:03:03,581 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:03,581 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:03,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:03,728 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:03:03,954 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:03:03,954 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:03:06,731 INFO L85 PathProgramCache]: Analyzing trace with hash 713882118, now seen corresponding path program 35 times [2024-05-06 18:03:06,732 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:06,732 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:06,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:06,870 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:03:06,870 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:06,871 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:06,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:07,001 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:03:07,101 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:03:07,101 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:03:07,258 INFO L85 PathProgramCache]: Analyzing trace with hash 655510046, now seen corresponding path program 36 times [2024-05-06 18:03:07,258 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:07,258 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:07,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:07,390 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:03:07,390 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:07,390 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:07,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:07,524 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:03:07,652 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:03:07,693 INFO L85 PathProgramCache]: Analyzing trace with hash -1154024194, now seen corresponding path program 37 times [2024-05-06 18:03:07,693 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:07,693 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:07,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:07,915 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:03:07,915 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:07,915 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:07,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:08,052 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:03:08,266 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:03:08,267 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:03:13,414 INFO L85 PathProgramCache]: Analyzing trace with hash 1916269675, now seen corresponding path program 1 times [2024-05-06 18:03:13,414 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:13,414 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:13,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:13,631 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:03:13,632 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:13,632 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:13,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:13,843 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:03:14,089 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:03:14,089 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:03:14,659 INFO L85 PathProgramCache]: Analyzing trace with hash 54284200, now seen corresponding path program 2 times [2024-05-06 18:03:14,660 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:14,660 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:14,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:14,832 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:03:14,833 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:14,833 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:14,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:15,177 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:03:15,413 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:03:15,413 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:03:15,922 INFO L85 PathProgramCache]: Analyzing trace with hash -908016158, now seen corresponding path program 1 times [2024-05-06 18:03:15,922 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:15,922 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:15,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:16,067 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:03:16,067 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:16,067 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:16,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:16,211 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:03:16,428 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:03:16,429 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:03:25,064 WARN L293 SmtUtils]: Spent 6.08s on a formula simplification. DAG size of input: 33 DAG size of output: 28 (called from [L 210] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.abduction.Abducer.solveAbductionProblem) [2024-05-06 18:03:27,071 WARN L854 $PredicateComparison]: unable to prove that (and (forall ((v_~q1~0.base_In_39 Int) (v_~q1_front~0_In_59 Int) (v_~q1~0.offset_In_39 Int)) (let ((.cse0 (select (select |c_#memory_int| v_~q1~0.base_In_39) (+ (* v_~q1_front~0_In_59 4) v_~q1~0.offset_In_39)))) (or (= .cse0 0) (< (+ 4294967295 .cse0) 0) (< 4294967295 .cse0) (< v_~q1_front~0_In_59 0)))) (forall ((v_~q2~0.base_In_16 Int) (v_~q2~0.offset_In_16 Int)) (= (select (select |c_#memory_int| v_~q2~0.base_In_16) (+ (* c_~q2_front~0 4) v_~q2~0.offset_In_16)) 0))) is different from false [2024-05-06 18:03:27,074 INFO L85 PathProgramCache]: Analyzing trace with hash 1276261393, now seen corresponding path program 2 times [2024-05-06 18:03:27,074 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:27,074 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:27,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:27,252 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:03:27,254 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:27,256 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:27,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:27,418 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:03:27,639 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:03:27,640 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:03:30,480 INFO L85 PathProgramCache]: Analyzing trace with hash -1414764145, now seen corresponding path program 1 times [2024-05-06 18:03:30,481 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:30,481 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:30,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:30,617 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:03:30,618 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:30,618 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:30,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:30,750 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:03:30,967 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:03:30,967 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:03:33,695 INFO L85 PathProgramCache]: Analyzing trace with hash 391078660, now seen corresponding path program 2 times [2024-05-06 18:03:33,695 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:33,695 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:33,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:33,850 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:03:33,851 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:33,851 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:33,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:34,003 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:03:34,268 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:03:34,269 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:03:36,916 INFO L85 PathProgramCache]: Analyzing trace with hash -1154016253, now seen corresponding path program 1 times [2024-05-06 18:03:36,916 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:36,916 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:36,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:37,192 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:03:37,193 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:37,193 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:37,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:37,331 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:03:37,546 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:03:37,547 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:03:38,270 INFO L85 PathProgramCache]: Analyzing trace with hash -1527500016, now seen corresponding path program 2 times [2024-05-06 18:03:38,270 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:38,271 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:38,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:38,428 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:03:38,429 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:38,429 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:38,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:38,586 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:03:38,824 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:03:38,825 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:03:39,444 INFO L85 PathProgramCache]: Analyzing trace with hash 655510322, now seen corresponding path program 1 times [2024-05-06 18:03:39,445 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:39,445 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:39,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:39,584 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:03:39,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:39,585 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:39,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:39,723 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:03:40,030 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:03:40,030 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:03:40,675 INFO L85 PathProgramCache]: Analyzing trace with hash -1262901055, now seen corresponding path program 2 times [2024-05-06 18:03:40,675 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:40,676 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:40,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:40,823 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:03:40,823 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:40,823 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:40,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:40,984 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:03:41,186 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:03:41,186 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:03:43,755 INFO L85 PathProgramCache]: Analyzing trace with hash 713882149, now seen corresponding path program 1 times [2024-05-06 18:03:43,755 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:43,755 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:43,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:43,888 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:03:43,888 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:43,888 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:43,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:44,020 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:03:44,236 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:03:44,237 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:03:44,823 INFO L85 PathProgramCache]: Analyzing trace with hash -954655954, now seen corresponding path program 2 times [2024-05-06 18:03:44,823 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:44,823 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:44,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:45,078 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:03:45,078 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:45,078 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:45,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:45,238 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:03:45,461 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:03:45,461 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:03:46,538 INFO L85 PathProgramCache]: Analyzing trace with hash -531160875, now seen corresponding path program 38 times [2024-05-06 18:03:46,538 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:46,538 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:46,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:46,702 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:03:46,702 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:46,702 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:46,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:46,837 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:03:47,021 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:03:47,021 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:03:47,544 INFO L85 PathProgramCache]: Analyzing trace with hash -841516418, now seen corresponding path program 39 times [2024-05-06 18:03:47,544 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:47,545 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:47,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:47,689 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:03:47,689 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:47,689 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:47,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:47,923 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:03:48,036 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:03:48,036 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:03:48,937 INFO L85 PathProgramCache]: Analyzing trace with hash -1670724113, now seen corresponding path program 40 times [2024-05-06 18:03:48,937 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:48,937 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:48,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:49,059 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:03:49,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:49,059 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:49,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:49,177 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:03:49,268 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:03:49,310 INFO L85 PathProgramCache]: Analyzing trace with hash -252839091, now seen corresponding path program 41 times [2024-05-06 18:03:49,310 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:49,310 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:49,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:49,434 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:03:49,434 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:49,435 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:49,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:49,558 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:03:49,752 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:03:49,753 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:03:50,223 INFO L85 PathProgramCache]: Analyzing trace with hash 1044133257, now seen corresponding path program 42 times [2024-05-06 18:03:50,224 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:50,224 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:50,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:50,364 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:03:50,364 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:50,364 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:50,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:50,502 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:03:50,583 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:03:50,583 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:03:51,172 INFO L85 PathProgramCache]: Analyzing trace with hash 1044133257, now seen corresponding path program 43 times [2024-05-06 18:03:51,172 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:51,172 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:51,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:51,402 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:03:51,402 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:51,402 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:51,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:51,537 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:03:51,629 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:03:51,667 INFO L85 PathProgramCache]: Analyzing trace with hash -1991606541, now seen corresponding path program 44 times [2024-05-06 18:03:51,667 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:51,667 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:51,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:51,802 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:03:51,802 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:51,802 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:51,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:51,935 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:03:52,024 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:03:52,058 INFO L85 PathProgramCache]: Analyzing trace with hash -1610259759, now seen corresponding path program 45 times [2024-05-06 18:03:52,058 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:52,058 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:52,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:52,200 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:03:52,200 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:52,200 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:52,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:52,342 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:03:52,422 INFO L85 PathProgramCache]: Analyzing trace with hash -862134108, now seen corresponding path program 46 times [2024-05-06 18:03:52,422 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:52,422 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:52,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:52,549 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:03:52,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:52,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:52,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:52,670 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:03:52,725 INFO L85 PathProgramCache]: Analyzing trace with hash 707997994, now seen corresponding path program 47 times [2024-05-06 18:03:52,725 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:52,725 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:52,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:52,949 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:03:52,949 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:52,949 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:52,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:53,198 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:03:53,435 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:03:53,435 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:03:54,022 INFO L85 PathProgramCache]: Analyzing trace with hash 707997983, now seen corresponding path program 48 times [2024-05-06 18:03:54,022 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:54,022 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:54,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:54,167 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:03:54,168 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:54,168 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:54,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:54,310 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:03:54,363 INFO L85 PathProgramCache]: Analyzing trace with hash 1781256423, now seen corresponding path program 49 times [2024-05-06 18:03:54,363 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:54,363 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:54,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:54,524 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:03:54,524 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:54,524 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:54,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:54,677 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:03:54,733 INFO L85 PathProgramCache]: Analyzing trace with hash 1090019266, now seen corresponding path program 50 times [2024-05-06 18:03:54,733 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:54,733 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:54,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:54,891 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:03:54,891 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:54,892 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:54,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:55,150 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:03:55,272 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:03:55,272 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:03:55,431 INFO L85 PathProgramCache]: Analyzing trace with hash -1197732050, now seen corresponding path program 51 times [2024-05-06 18:03:55,431 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:55,432 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:55,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:55,631 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:03:55,631 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:55,631 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:55,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:55,801 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:03:55,905 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:03:55,942 INFO L85 PathProgramCache]: Analyzing trace with hash 1525012982, now seen corresponding path program 52 times [2024-05-06 18:03:55,942 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:55,942 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:55,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:56,123 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:03:56,123 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:56,124 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:56,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:56,302 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:03:56,415 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:03:56,463 INFO L85 PathProgramCache]: Analyzing trace with hash 713836615, now seen corresponding path program 53 times [2024-05-06 18:03:56,463 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:56,464 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:56,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:56,634 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:03:56,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:56,634 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:56,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:56,804 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:03:56,856 INFO L85 PathProgramCache]: Analyzing trace with hash 654099436, now seen corresponding path program 54 times [2024-05-06 18:03:56,856 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:56,857 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:56,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:57,126 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:03:57,127 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:57,127 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:57,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:57,303 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:03:57,417 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:03:57,417 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:03:57,528 INFO L85 PathProgramCache]: Analyzing trace with hash 854310933, now seen corresponding path program 55 times [2024-05-06 18:03:57,529 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:57,529 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:57,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:57,687 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:03:57,688 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:57,688 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:57,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:57,848 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:03:58,075 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:03:58,075 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:03:58,708 INFO L85 PathProgramCache]: Analyzing trace with hash -30107780, now seen corresponding path program 56 times [2024-05-06 18:03:58,708 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:58,708 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:58,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:58,848 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:03:58,849 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:58,849 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:58,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:58,995 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:03:59,048 INFO L85 PathProgramCache]: Analyzing trace with hash -933340312, now seen corresponding path program 57 times [2024-05-06 18:03:59,048 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:59,048 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:59,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:59,319 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:03:59,319 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:59,319 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:59,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:59,466 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:03:59,522 INFO L85 PathProgramCache]: Analyzing trace with hash 1131222260, now seen corresponding path program 58 times [2024-05-06 18:03:59,523 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:59,523 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:59,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:59,677 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:03:59,678 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:03:59,678 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:03:59,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:03:59,831 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:04:00,071 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:04:00,071 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:04:00,673 INFO L85 PathProgramCache]: Analyzing trace with hash 1930088257, now seen corresponding path program 59 times [2024-05-06 18:04:00,673 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:00,673 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:00,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:00,821 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:04:00,822 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:00,822 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:00,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:00,976 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:04:01,142 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:04:01,142 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:04:02,071 INFO L85 PathProgramCache]: Analyzing trace with hash 1211565268, now seen corresponding path program 60 times [2024-05-06 18:04:02,071 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:02,072 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:02,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:02,230 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:04:02,230 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:02,230 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:02,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:02,471 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:04:02,674 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:04:02,675 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:04:07,904 INFO L85 PathProgramCache]: Analyzing trace with hash 1211565268, now seen corresponding path program 61 times [2024-05-06 18:04:07,909 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:07,909 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:07,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:08,087 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:04:08,088 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:08,088 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:08,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:08,250 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:04:08,348 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:04:08,391 INFO L85 PathProgramCache]: Analyzing trace with hash -1096181488, now seen corresponding path program 62 times [2024-05-06 18:04:08,392 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:08,392 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:08,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:08,545 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:04:08,545 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:08,545 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:08,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:08,700 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:04:08,796 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:04:08,831 INFO L85 PathProgramCache]: Analyzing trace with hash 378113100, now seen corresponding path program 63 times [2024-05-06 18:04:08,831 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:08,831 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:08,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:09,110 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:04:09,111 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:09,111 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:09,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:09,273 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:04:09,392 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:04:09,439 INFO L85 PathProgramCache]: Analyzing trace with hash -1163394926, now seen corresponding path program 64 times [2024-05-06 18:04:09,439 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:09,439 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:09,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:09,638 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:04:09,638 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:09,638 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:09,662 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:09,814 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:04:10,053 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:04:10,054 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:04:15,100 INFO L85 PathProgramCache]: Analyzing trace with hash 378129969, now seen corresponding path program 1 times [2024-05-06 18:04:15,100 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:15,100 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:15,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:15,278 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:04:15,278 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:15,279 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:15,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:15,564 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:04:15,756 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:04:15,756 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:04:16,352 INFO L85 PathProgramCache]: Analyzing trace with hash -608430942, now seen corresponding path program 2 times [2024-05-06 18:04:16,352 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:16,352 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:16,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:16,531 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:04:16,532 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:16,532 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:16,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:16,708 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:04:16,971 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:04:16,972 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:04:17,674 INFO L85 PathProgramCache]: Analyzing trace with hash -1096180933, now seen corresponding path program 1 times [2024-05-06 18:04:17,674 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:17,674 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:17,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:17,825 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:04:17,825 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:17,825 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:17,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:17,976 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:04:18,286 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:04:18,286 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:04:27,412 WARN L293 SmtUtils]: Spent 6.65s on a formula simplification. DAG size of input: 34 DAG size of output: 14 (called from [L 210] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.abduction.Abducer.solveAbductionProblem) [2024-05-06 18:04:27,438 INFO L85 PathProgramCache]: Analyzing trace with hash 1089557208, now seen corresponding path program 2 times [2024-05-06 18:04:27,438 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:27,438 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:27,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:27,608 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:04:27,608 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:27,609 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:27,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:27,778 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:04:27,994 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:04:27,994 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:04:28,802 INFO L85 PathProgramCache]: Analyzing trace with hash 1211565299, now seen corresponding path program 1 times [2024-05-06 18:04:28,803 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:28,803 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:28,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:28,956 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:04:28,956 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:28,956 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:28,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:29,111 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:04:29,301 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:04:29,301 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:04:29,962 INFO L85 PathProgramCache]: Analyzing trace with hash -634169312, now seen corresponding path program 2 times [2024-05-06 18:04:29,962 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:29,962 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:29,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:30,151 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:04:30,152 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:30,152 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:30,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:30,335 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:04:30,530 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:04:30,531 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:04:33,656 INFO L85 PathProgramCache]: Analyzing trace with hash -1762032578, now seen corresponding path program 65 times [2024-05-06 18:04:33,657 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:33,657 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:33,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:33,817 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:04:33,817 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:33,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:33,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:33,992 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:04:34,191 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:04:34,191 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:04:34,939 INFO L85 PathProgramCache]: Analyzing trace with hash 106159413, now seen corresponding path program 66 times [2024-05-06 18:04:34,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:34,940 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:35,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:35,207 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:04:35,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:35,208 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:35,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:35,386 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:04:35,513 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:04:35,558 INFO L85 PathProgramCache]: Analyzing trace with hash -611029139, now seen corresponding path program 67 times [2024-05-06 18:04:35,558 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:35,558 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:35,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:35,733 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:04:35,733 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:35,733 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:35,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:35,917 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:04:36,001 INFO L85 PathProgramCache]: Analyzing trace with hash -1762033274, now seen corresponding path program 68 times [2024-05-06 18:04:36,001 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:36,001 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:36,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:36,172 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:04:36,172 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:36,172 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:36,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:36,340 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:04:36,455 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:04:36,456 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:04:36,785 INFO L85 PathProgramCache]: Analyzing trace with hash -296805329, now seen corresponding path program 69 times [2024-05-06 18:04:36,785 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:36,785 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:36,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:36,940 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:04:36,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:36,940 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:36,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:37,188 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:04:37,386 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:04:37,386 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:04:40,128 INFO L85 PathProgramCache]: Analyzing trace with hash -611029756, now seen corresponding path program 70 times [2024-05-06 18:04:40,128 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:40,129 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:40,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:40,288 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:04:40,289 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:40,289 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:40,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:40,451 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:04:40,507 INFO L85 PathProgramCache]: Analyzing trace with hash -1762052384, now seen corresponding path program 71 times [2024-05-06 18:04:40,507 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:40,507 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:40,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:40,680 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:04:40,681 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:40,681 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:40,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:40,839 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:04:40,893 INFO L85 PathProgramCache]: Analyzing trace with hash 1210951804, now seen corresponding path program 72 times [2024-05-06 18:04:40,893 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:40,894 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:40,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:41,063 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:04:41,063 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:41,063 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:41,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:41,397 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:04:41,455 INFO L85 PathProgramCache]: Analyzing trace with hash -1115198878, now seen corresponding path program 73 times [2024-05-06 18:04:41,455 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:41,455 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:41,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:41,609 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:04:41,609 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:41,609 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:41,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:41,808 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:04:41,930 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:04:41,974 INFO L85 PathProgramCache]: Analyzing trace with hash -1322550119, now seen corresponding path program 74 times [2024-05-06 18:04:41,974 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:41,975 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:41,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:42,145 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:04:42,145 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:42,145 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:42,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:42,308 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:04:42,416 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:04:42,459 INFO L85 PathProgramCache]: Analyzing trace with hash -1322519336, now seen corresponding path program 1 times [2024-05-06 18:04:42,459 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:42,459 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:42,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:42,629 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:04:42,629 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:42,629 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:42,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:42,790 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:04:42,847 INFO L85 PathProgramCache]: Analyzing trace with hash 1951574395, now seen corresponding path program 2 times [2024-05-06 18:04:42,847 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:42,848 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:42,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:43,108 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:04:43,108 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:43,108 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:43,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:43,276 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:04:43,418 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:04:43,418 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:04:43,545 INFO L85 PathProgramCache]: Analyzing trace with hash -1693347865, now seen corresponding path program 3 times [2024-05-06 18:04:43,545 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:43,546 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:43,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:43,723 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:04:43,723 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:43,723 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:43,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:43,891 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:04:43,989 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:04:44,022 INFO L85 PathProgramCache]: Analyzing trace with hash -954175395, now seen corresponding path program 4 times [2024-05-06 18:04:44,022 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:44,023 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:44,048 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:44,210 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:04:44,210 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:44,210 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:44,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:44,384 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:04:44,502 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:04:44,502 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:04:44,627 INFO L85 PathProgramCache]: Analyzing trace with hash -716725764, now seen corresponding path program 5 times [2024-05-06 18:04:44,627 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:44,627 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:44,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:44,896 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:04:44,897 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:44,897 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:44,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:45,060 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:04:45,117 INFO L85 PathProgramCache]: Analyzing trace with hash -1618620754, now seen corresponding path program 6 times [2024-05-06 18:04:45,118 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:45,118 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:45,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:45,295 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:04:45,295 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:45,295 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:45,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:45,467 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:04:45,568 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:04:45,601 INFO L85 PathProgramCache]: Analyzing trace with hash 1481358697, now seen corresponding path program 1 times [2024-05-06 18:04:45,601 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:45,601 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:45,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:45,760 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:04:45,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:45,760 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:45,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:45,916 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:04:45,971 INFO L85 PathProgramCache]: Analyzing trace with hash -1322519798, now seen corresponding path program 2 times [2024-05-06 18:04:45,971 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:45,971 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:45,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:46,132 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:04:46,133 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:46,133 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:46,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:46,290 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:04:46,504 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:04:46,504 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:04:46,651 INFO L85 PathProgramCache]: Analyzing trace with hash 1154210422, now seen corresponding path program 3 times [2024-05-06 18:04:46,651 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:46,652 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:46,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:46,837 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:04:46,837 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:46,838 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:46,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:47,044 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:04:47,153 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:04:47,195 INFO L85 PathProgramCache]: Analyzing trace with hash 1420785582, now seen corresponding path program 4 times [2024-05-06 18:04:47,196 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:47,196 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:47,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:47,368 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:04:47,368 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:47,369 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:47,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:47,562 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:04:47,674 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:04:47,675 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:04:48,353 INFO L85 PathProgramCache]: Analyzing trace with hash 1037629901, now seen corresponding path program 5 times [2024-05-06 18:04:48,354 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:48,354 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:48,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:48,538 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:04:48,538 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:48,538 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:48,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:48,719 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:04:48,775 INFO L85 PathProgramCache]: Analyzing trace with hash -1451432257, now seen corresponding path program 6 times [2024-05-06 18:04:48,775 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:48,776 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:48,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:49,048 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:04:49,048 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:49,048 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:49,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:49,231 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:04:49,329 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:04:49,361 INFO L85 PathProgramCache]: Analyzing trace with hash 2125995706, now seen corresponding path program 1 times [2024-05-06 18:04:49,362 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:49,362 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:49,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:49,534 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:04:49,534 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:49,534 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:49,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:49,706 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:04:49,761 INFO L85 PathProgramCache]: Analyzing trace with hash 1481358297, now seen corresponding path program 2 times [2024-05-06 18:04:49,761 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:49,761 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:49,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:49,939 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:04:49,939 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:49,939 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:49,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:50,115 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:04:50,230 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:04:50,231 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:04:50,341 INFO L85 PathProgramCache]: Analyzing trace with hash -1225169851, now seen corresponding path program 3 times [2024-05-06 18:04:50,341 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:50,341 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:50,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:50,528 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:04:50,528 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:50,528 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:50,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:50,809 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:04:50,916 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:04:50,960 INFO L85 PathProgramCache]: Analyzing trace with hash 674441151, now seen corresponding path program 4 times [2024-05-06 18:04:50,960 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:50,960 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:50,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:51,142 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:04:51,143 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:51,143 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:51,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:51,330 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:04:51,446 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:04:51,446 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:04:51,563 INFO L85 PathProgramCache]: Analyzing trace with hash -594453922, now seen corresponding path program 5 times [2024-05-06 18:04:51,564 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:51,564 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:51,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:51,748 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:04:51,748 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:51,749 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:51,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:51,928 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:04:51,983 INFO L85 PathProgramCache]: Analyzing trace with hash 356923280, now seen corresponding path program 6 times [2024-05-06 18:04:51,983 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:51,983 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:52,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:52,159 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:04:52,159 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:52,159 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:52,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:52,429 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:04:52,541 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:04:52,587 INFO L85 PathProgramCache]: Analyzing trace with hash -1316892852, now seen corresponding path program 75 times [2024-05-06 18:04:52,588 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:52,588 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:52,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:52,752 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:04:52,752 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:52,752 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:52,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:52,918 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:04:52,978 INFO L85 PathProgramCache]: Analyzing trace with hash 2125995399, now seen corresponding path program 76 times [2024-05-06 18:04:52,978 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:52,979 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:53,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:53,158 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:04:53,158 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:53,159 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:53,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:53,333 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:04:53,449 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:04:53,449 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:04:53,576 INFO L85 PathProgramCache]: Analyzing trace with hash 1710766067, now seen corresponding path program 77 times [2024-05-06 18:04:53,576 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:53,576 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:53,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:53,761 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:04:53,761 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:53,761 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:53,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:53,948 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:04:54,045 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:04:54,083 INFO L85 PathProgramCache]: Analyzing trace with hash 1494141393, now seen corresponding path program 78 times [2024-05-06 18:04:54,084 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:54,084 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:54,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:54,355 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:04:54,355 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:54,355 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:54,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:54,544 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:04:54,656 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:04:54,656 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:04:54,804 INFO L85 PathProgramCache]: Analyzing trace with hash -2002463376, now seen corresponding path program 79 times [2024-05-06 18:04:54,804 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:54,804 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:54,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:54,980 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:04:54,980 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:54,981 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:55,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:55,158 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:04:55,213 INFO L85 PathProgramCache]: Analyzing trace with hash 1942048546, now seen corresponding path program 80 times [2024-05-06 18:04:55,213 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:55,213 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:55,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:55,392 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:04:55,392 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:55,392 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:55,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:55,567 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:04:55,681 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:04:55,682 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:04:55,800 INFO L85 PathProgramCache]: Analyzing trace with hash -933158779, now seen corresponding path program 81 times [2024-05-06 18:04:55,800 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:55,800 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:55,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:55,952 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:04:55,952 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:04:55,953 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:04:55,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:04:56,199 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:04:56,413 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:04:56,414 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:05:05,735 INFO L85 PathProgramCache]: Analyzing trace with hash 1136849780, now seen corresponding path program 82 times [2024-05-06 18:05:05,735 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:05,736 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:05,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:05,893 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:05:05,893 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:05,894 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:05,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:06,043 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:05:06,204 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:05:06,205 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:05:06,334 INFO L85 PathProgramCache]: Analyzing trace with hash 882605672, now seen corresponding path program 83 times [2024-05-06 18:05:06,334 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:06,334 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:06,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:06,485 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:05:06,485 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:06,486 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:06,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:06,636 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:05:06,738 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:05:06,775 INFO L85 PathProgramCache]: Analyzing trace with hash 1590972924, now seen corresponding path program 84 times [2024-05-06 18:05:06,775 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:06,776 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:06,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:07,031 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:05:07,031 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:07,031 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:07,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:07,180 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:05:07,319 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:05:07,320 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:05:07,452 INFO L85 PathProgramCache]: Analyzing trace with hash -1062802847, now seen corresponding path program 85 times [2024-05-06 18:05:07,452 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:07,452 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:07,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:07,656 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:07,656 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:07,656 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:07,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:07,790 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:08,018 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:05:08,018 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:05:08,488 INFO L85 PathProgramCache]: Analyzing trace with hash -435644763, now seen corresponding path program 86 times [2024-05-06 18:05:08,488 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:08,488 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:08,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:08,630 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:08,631 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:08,631 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:08,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:08,772 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:08,831 INFO L85 PathProgramCache]: Analyzing trace with hash 762393194, now seen corresponding path program 87 times [2024-05-06 18:05:08,832 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:08,832 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:08,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:09,057 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:09,057 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:09,057 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:09,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:09,226 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:09,336 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:05:09,371 INFO L85 PathProgramCache]: Analyzing trace with hash -722280231, now seen corresponding path program 88 times [2024-05-06 18:05:09,372 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:09,372 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:09,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:09,509 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:09,510 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:09,510 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:09,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:09,656 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:09,709 INFO L85 PathProgramCache]: Analyzing trace with hash -915849830, now seen corresponding path program 89 times [2024-05-06 18:05:09,709 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:09,709 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:09,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:09,856 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:09,857 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:09,857 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:09,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:10,000 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:10,075 INFO L85 PathProgramCache]: Analyzing trace with hash 1845809455, now seen corresponding path program 90 times [2024-05-06 18:05:10,075 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:10,075 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:10,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:10,222 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:10,223 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:10,223 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:10,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:10,371 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:10,431 INFO L85 PathProgramCache]: Analyzing trace with hash 44039282, now seen corresponding path program 91 times [2024-05-06 18:05:10,432 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:10,432 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:10,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:10,585 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:10,585 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:10,585 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:10,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:10,831 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:10,894 INFO L85 PathProgramCache]: Analyzing trace with hash -1286503827, now seen corresponding path program 92 times [2024-05-06 18:05:10,895 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:10,895 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:10,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:11,082 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:05:11,083 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:11,083 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:11,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:11,262 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:05:11,393 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:05:11,393 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:05:11,543 INFO L85 PathProgramCache]: Analyzing trace with hash -1033739815, now seen corresponding path program 93 times [2024-05-06 18:05:11,543 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:11,543 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:11,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:11,701 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:11,702 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:11,702 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:11,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:11,857 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:11,949 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:05:11,995 INFO L85 PathProgramCache]: Analyzing trace with hash -1981162333, now seen corresponding path program 94 times [2024-05-06 18:05:11,996 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:11,996 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:12,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:12,162 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:12,162 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:12,162 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:12,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:12,328 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:12,427 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:05:12,468 INFO L85 PathProgramCache]: Analyzing trace with hash -1064761712, now seen corresponding path program 95 times [2024-05-06 18:05:12,469 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:12,469 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:12,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:12,721 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:12,721 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:12,721 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:12,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:12,879 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:12,935 INFO L85 PathProgramCache]: Analyzing trace with hash 1352126138, now seen corresponding path program 96 times [2024-05-06 18:05:12,935 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:12,935 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:12,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:13,102 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:05:13,102 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:13,102 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:13,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:13,268 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:05:13,375 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:05:13,376 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:05:13,491 INFO L85 PathProgramCache]: Analyzing trace with hash -2112557182, now seen corresponding path program 97 times [2024-05-06 18:05:13,491 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:13,491 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:13,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:13,642 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:13,642 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:13,643 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:13,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:13,792 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:13,991 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:05:13,991 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:05:18,986 INFO L85 PathProgramCache]: Analyzing trace with hash -627918939, now seen corresponding path program 98 times [2024-05-06 18:05:18,986 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:18,986 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:19,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:19,134 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:19,134 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:19,136 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:19,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:19,280 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:19,337 INFO L85 PathProgramCache]: Analyzing trace with hash -2134651411, now seen corresponding path program 99 times [2024-05-06 18:05:19,337 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:19,337 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:19,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:19,523 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:19,523 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:19,523 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:19,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:19,711 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:19,827 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:05:19,874 INFO L85 PathProgramCache]: Analyzing trace with hash 1594389326, now seen corresponding path program 100 times [2024-05-06 18:05:19,874 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:19,874 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:19,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:20,039 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:20,039 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:20,040 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:20,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:20,203 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:20,264 INFO L85 PathProgramCache]: Analyzing trace with hash -2113537604, now seen corresponding path program 101 times [2024-05-06 18:05:20,264 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:20,264 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:20,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:20,535 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:05:20,535 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:20,535 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:20,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:20,707 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:05:20,767 INFO L85 PathProgramCache]: Analyzing trace with hash -1095155431, now seen corresponding path program 102 times [2024-05-06 18:05:20,767 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:20,768 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:20,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:20,938 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:05:20,938 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:20,938 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:20,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:21,110 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:05:21,171 INFO L85 PathProgramCache]: Analyzing trace with hash 409921247, now seen corresponding path program 103 times [2024-05-06 18:05:21,171 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:21,171 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:21,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:21,347 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:05:21,347 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:21,347 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:21,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:21,522 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:05:21,660 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:05:21,660 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:05:21,811 INFO L85 PathProgramCache]: Analyzing trace with hash -1671681717, now seen corresponding path program 104 times [2024-05-06 18:05:21,811 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:21,811 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:21,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:21,996 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:05:21,996 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:21,996 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:22,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:22,294 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:05:22,425 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:05:22,467 INFO L85 PathProgramCache]: Analyzing trace with hash -282524807, now seen corresponding path program 105 times [2024-05-06 18:05:22,467 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:22,467 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:22,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:22,665 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:05:22,665 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:22,665 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:22,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:22,855 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:05:22,979 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:05:23,026 INFO L85 PathProgramCache]: Analyzing trace with hash 2027308452, now seen corresponding path program 106 times [2024-05-06 18:05:23,026 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:23,026 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:23,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:23,203 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:05:23,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:23,204 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:23,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:23,387 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:05:23,449 INFO L85 PathProgramCache]: Analyzing trace with hash -1577946577, now seen corresponding path program 107 times [2024-05-06 18:05:23,449 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:23,449 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:23,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:23,634 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:05:23,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:23,634 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:23,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:23,819 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:05:23,960 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:05:23,961 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:05:24,086 INFO L85 PathProgramCache]: Analyzing trace with hash 619586328, now seen corresponding path program 108 times [2024-05-06 18:05:24,086 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:24,086 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:24,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:24,368 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:05:24,368 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:24,368 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:24,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:24,547 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:05:24,603 INFO L85 PathProgramCache]: Analyzing trace with hash 667620121, now seen corresponding path program 109 times [2024-05-06 18:05:24,603 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:24,604 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:24,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:24,781 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:05:24,781 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:24,781 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:24,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:24,960 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:05:25,074 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:05:25,074 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:05:25,189 INFO L85 PathProgramCache]: Analyzing trace with hash 487844996, now seen corresponding path program 110 times [2024-05-06 18:05:25,189 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:25,190 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:25,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:25,356 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:25,356 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:25,356 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:25,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:25,527 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:25,624 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:05:25,657 INFO L85 PathProgramCache]: Analyzing trace with hash -2056673440, now seen corresponding path program 111 times [2024-05-06 18:05:25,657 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:25,657 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:25,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:25,923 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:25,923 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:25,923 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:25,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:26,107 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:26,227 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:05:26,281 INFO L85 PathProgramCache]: Analyzing trace with hash -1192787171, now seen corresponding path program 112 times [2024-05-06 18:05:26,281 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:26,281 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:26,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:26,446 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:26,446 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:26,446 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:26,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:26,610 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:26,654 INFO L85 PathProgramCache]: Analyzing trace with hash 1678304214, now seen corresponding path program 113 times [2024-05-06 18:05:26,654 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:26,654 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:26,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:26,817 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:05:26,817 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:26,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:26,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:26,983 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:05:27,085 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:05:27,085 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:05:27,234 INFO L85 PathProgramCache]: Analyzing trace with hash -177024385, now seen corresponding path program 114 times [2024-05-06 18:05:27,234 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:27,235 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:27,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:27,402 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:27,403 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:27,403 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:27,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:27,665 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:27,807 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:05:27,808 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:05:27,948 INFO L85 PathProgramCache]: Analyzing trace with hash -1919376593, now seen corresponding path program 3 times [2024-05-06 18:05:27,948 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:27,948 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:27,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:28,125 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:28,126 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:28,126 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:28,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:28,301 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:28,421 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:05:28,464 INFO L85 PathProgramCache]: Analyzing trace with hash 628868629, now seen corresponding path program 4 times [2024-05-06 18:05:28,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:28,464 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:28,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:28,640 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:28,640 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:28,640 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:28,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:28,820 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:28,956 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:05:29,011 INFO L85 PathProgramCache]: Analyzing trace with hash 1240459400, now seen corresponding path program 5 times [2024-05-06 18:05:29,011 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:29,011 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:29,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:29,185 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:29,185 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:29,185 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:29,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:29,352 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:29,411 INFO L85 PathProgramCache]: Analyzing trace with hash -200463413, now seen corresponding path program 6 times [2024-05-06 18:05:29,411 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:29,411 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:29,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:29,675 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:05:29,675 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:29,675 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:29,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:29,851 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:05:29,991 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:05:29,992 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:05:30,123 INFO L85 PathProgramCache]: Analyzing trace with hash 40014772, now seen corresponding path program 7 times [2024-05-06 18:05:30,124 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:30,124 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:30,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:30,292 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:30,292 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:30,292 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:30,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:30,458 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:30,514 INFO L85 PathProgramCache]: Analyzing trace with hash 1671548518, now seen corresponding path program 8 times [2024-05-06 18:05:30,514 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:30,514 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:30,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:30,682 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:30,682 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:30,682 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:30,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:30,850 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:30,904 INFO L85 PathProgramCache]: Analyzing trace with hash -1812261771, now seen corresponding path program 3 times [2024-05-06 18:05:30,904 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:30,904 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:30,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:31,084 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:05:31,085 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:31,085 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:31,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:31,353 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:05:31,465 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:05:31,466 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:05:31,586 INFO L85 PathProgramCache]: Analyzing trace with hash -1798531872, now seen corresponding path program 4 times [2024-05-06 18:05:31,586 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:31,586 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:31,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:31,770 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:31,771 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:31,771 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:31,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:31,948 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:32,070 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:05:32,118 INFO L85 PathProgramCache]: Analyzing trace with hash 80087684, now seen corresponding path program 5 times [2024-05-06 18:05:32,118 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:32,118 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:32,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:32,292 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:32,292 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:32,292 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:32,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:32,468 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:32,583 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:05:32,637 INFO L85 PathProgramCache]: Analyzing trace with hash 69636729, now seen corresponding path program 6 times [2024-05-06 18:05:32,637 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:32,637 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:32,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:32,809 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:32,809 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:32,809 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:32,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:33,077 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:33,135 INFO L85 PathProgramCache]: Analyzing trace with hash -2136227846, now seen corresponding path program 7 times [2024-05-06 18:05:33,135 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:33,135 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:33,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:33,312 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:05:33,312 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:33,312 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:33,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:33,488 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:05:33,623 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:05:33,623 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:05:33,768 INFO L85 PathProgramCache]: Analyzing trace with hash 279340963, now seen corresponding path program 8 times [2024-05-06 18:05:33,768 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:33,768 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:33,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:33,936 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:33,937 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:33,937 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:33,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:34,108 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:34,174 INFO L85 PathProgramCache]: Analyzing trace with hash -1000925976, now seen corresponding path program 3 times [2024-05-06 18:05:34,174 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:34,174 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:34,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:34,358 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:05:34,358 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:34,359 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:34,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:34,551 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:05:34,703 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:05:34,704 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:05:34,860 INFO L85 PathProgramCache]: Analyzing trace with hash -184281581, now seen corresponding path program 4 times [2024-05-06 18:05:34,861 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:34,861 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:34,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:35,123 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:35,123 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:35,124 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:35,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:35,301 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:35,398 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:05:35,439 INFO L85 PathProgramCache]: Analyzing trace with hash -1417760847, now seen corresponding path program 5 times [2024-05-06 18:05:35,439 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:35,439 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:35,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:35,618 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:35,618 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:35,619 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:35,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:35,797 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:35,899 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:05:35,936 INFO L85 PathProgramCache]: Analyzing trace with hash 312657004, now seen corresponding path program 6 times [2024-05-06 18:05:35,936 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:35,936 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:35,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:36,101 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:36,101 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:36,101 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:36,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:36,275 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:36,328 INFO L85 PathProgramCache]: Analyzing trace with hash 1102433383, now seen corresponding path program 7 times [2024-05-06 18:05:36,328 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:36,329 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:36,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:36,508 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:05:36,508 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:36,508 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:36,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:36,787 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:05:36,904 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:05:36,904 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:05:37,037 INFO L85 PathProgramCache]: Analyzing trace with hash 1672653648, now seen corresponding path program 8 times [2024-05-06 18:05:37,037 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:37,037 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:37,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:37,209 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:37,210 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:37,211 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:37,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:37,381 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:37,438 INFO L85 PathProgramCache]: Analyzing trace with hash -298293034, now seen corresponding path program 3 times [2024-05-06 18:05:37,438 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:37,438 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:37,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:37,625 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:05:37,626 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:37,626 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:37,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:37,809 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:05:37,923 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:05:37,923 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:05:38,051 INFO L85 PathProgramCache]: Analyzing trace with hash -1318744703, now seen corresponding path program 4 times [2024-05-06 18:05:38,051 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:38,051 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:38,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:38,224 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:38,224 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:38,225 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:38,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:38,398 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:38,590 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:05:38,627 INFO L85 PathProgramCache]: Analyzing trace with hash 2068588035, now seen corresponding path program 5 times [2024-05-06 18:05:38,627 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:38,627 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:38,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:38,803 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:38,803 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:38,803 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:38,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:38,975 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:39,073 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:05:39,107 INFO L85 PathProgramCache]: Analyzing trace with hash 1647787866, now seen corresponding path program 6 times [2024-05-06 18:05:39,107 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:39,107 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:39,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:39,267 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:39,268 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:39,268 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:39,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:39,442 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:39,498 INFO L85 PathProgramCache]: Analyzing trace with hash -458182855, now seen corresponding path program 7 times [2024-05-06 18:05:39,498 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:39,498 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:39,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:39,676 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:05:39,677 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:39,677 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:39,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:39,852 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:05:39,968 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:05:39,969 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:05:40,092 INFO L85 PathProgramCache]: Analyzing trace with hash -2025055582, now seen corresponding path program 8 times [2024-05-06 18:05:40,092 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:40,092 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:40,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:40,368 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:40,369 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:40,369 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:40,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:40,571 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:40,633 INFO L85 PathProgramCache]: Analyzing trace with hash 56691787, now seen corresponding path program 3 times [2024-05-06 18:05:40,633 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:40,634 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:40,662 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:40,817 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:05:40,817 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:40,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:40,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:41,005 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:05:41,124 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:05:41,124 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:05:41,269 INFO L85 PathProgramCache]: Analyzing trace with hash -1881503178, now seen corresponding path program 4 times [2024-05-06 18:05:41,270 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:41,270 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:41,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:41,444 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:41,444 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:41,444 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:41,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:41,621 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:41,718 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:05:41,753 INFO L85 PathProgramCache]: Analyzing trace with hash 1802944494, now seen corresponding path program 5 times [2024-05-06 18:05:41,754 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:41,754 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:41,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:41,926 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:41,926 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:41,926 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:41,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:42,096 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:42,307 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:05:42,339 INFO L85 PathProgramCache]: Analyzing trace with hash -2017598129, now seen corresponding path program 6 times [2024-05-06 18:05:42,339 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:42,339 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:42,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:42,500 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:42,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:42,501 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:42,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:42,670 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:42,725 INFO L85 PathProgramCache]: Analyzing trace with hash 1878968292, now seen corresponding path program 7 times [2024-05-06 18:05:42,725 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:42,725 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:42,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:42,898 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:05:42,898 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:42,898 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:42,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:43,074 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:05:43,194 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:05:43,194 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:05:43,918 INFO L85 PathProgramCache]: Analyzing trace with hash -1173462515, now seen corresponding path program 8 times [2024-05-06 18:05:43,918 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:43,918 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:43,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:44,078 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:44,078 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:44,079 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:44,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:44,243 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:44,304 INFO L85 PathProgramCache]: Analyzing trace with hash 471106616, now seen corresponding path program 3 times [2024-05-06 18:05:44,304 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:44,304 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:44,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:44,478 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:05:44,478 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:44,478 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:44,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:44,763 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:05:44,887 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:05:44,887 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:05:45,001 INFO L85 PathProgramCache]: Analyzing trace with hash -2064311965, now seen corresponding path program 4 times [2024-05-06 18:05:45,001 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:45,001 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:45,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:45,175 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:45,175 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:45,175 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:45,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:45,348 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:45,446 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:05:45,479 INFO L85 PathProgramCache]: Analyzing trace with hash 430839393, now seen corresponding path program 5 times [2024-05-06 18:05:45,479 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:45,480 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:45,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:45,650 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:45,650 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:45,650 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:45,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:45,812 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:45,909 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:05:45,941 INFO L85 PathProgramCache]: Analyzing trace with hash -1164158020, now seen corresponding path program 6 times [2024-05-06 18:05:45,941 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:45,941 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:45,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:46,099 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:46,100 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:46,100 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:46,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:46,281 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:46,335 INFO L85 PathProgramCache]: Analyzing trace with hash -1729159401, now seen corresponding path program 7 times [2024-05-06 18:05:46,335 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:46,335 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:46,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:46,500 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:05:46,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:46,501 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:46,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:46,780 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:05:46,907 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:05:46,907 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:05:47,044 INFO L85 PathProgramCache]: Analyzing trace with hash -176100864, now seen corresponding path program 8 times [2024-05-06 18:05:47,045 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:47,045 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:47,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:47,204 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:47,205 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:47,205 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:47,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:47,368 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:47,437 INFO L85 PathProgramCache]: Analyzing trace with hash -2028394578, now seen corresponding path program 115 times [2024-05-06 18:05:47,438 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:47,438 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:47,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:47,615 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:05:47,616 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:47,616 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:47,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:47,789 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:05:47,930 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:05:47,930 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:05:48,083 INFO L85 PathProgramCache]: Analyzing trace with hash 1285038681, now seen corresponding path program 116 times [2024-05-06 18:05:48,083 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:48,083 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:48,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:48,251 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:48,251 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:48,251 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:48,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:48,414 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:48,498 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:05:48,537 INFO L85 PathProgramCache]: Analyzing trace with hash 1181494315, now seen corresponding path program 117 times [2024-05-06 18:05:48,537 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:48,537 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:48,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:48,838 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:48,838 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:48,839 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:48,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:49,060 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:05:49,185 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:05:49,222 INFO L85 PathProgramCache]: Analyzing trace with hash -164025806, now seen corresponding path program 118 times [2024-05-06 18:05:49,222 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:49,222 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:49,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:49,392 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:49,392 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:49,393 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:49,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:49,563 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:49,621 INFO L85 PathProgramCache]: Analyzing trace with hash -789831839, now seen corresponding path program 119 times [2024-05-06 18:05:49,621 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:49,621 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:49,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:49,800 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:05:49,800 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:49,800 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:49,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:49,974 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:05:50,104 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:05:50,105 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:05:50,299 INFO L85 PathProgramCache]: Analyzing trace with hash 410350794, now seen corresponding path program 120 times [2024-05-06 18:05:50,299 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:50,299 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:50,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:50,465 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:50,465 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:50,465 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:50,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:50,631 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:50,722 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:05:50,759 INFO L85 PathProgramCache]: Analyzing trace with hash -2134651440, now seen corresponding path program 121 times [2024-05-06 18:05:50,759 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:50,759 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:50,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:51,023 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:51,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:51,024 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:51,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:51,187 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:51,254 INFO L85 PathProgramCache]: Analyzing trace with hash -1749684358, now seen corresponding path program 122 times [2024-05-06 18:05:51,254 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:51,254 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:51,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:51,426 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:05:51,426 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:51,426 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:51,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:51,588 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:05:51,807 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:05:51,807 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:05:52,378 INFO L85 PathProgramCache]: Analyzing trace with hash -2114427723, now seen corresponding path program 123 times [2024-05-06 18:05:52,378 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:52,378 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:52,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:52,549 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:05:52,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:52,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:52,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:52,718 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:05:52,776 INFO L85 PathProgramCache]: Analyzing trace with hash -1122749113, now seen corresponding path program 124 times [2024-05-06 18:05:52,776 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:52,776 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:52,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:52,948 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:05:52,948 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:52,948 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:52,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:53,128 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:05:53,188 INFO L85 PathProgramCache]: Analyzing trace with hash -445483267, now seen corresponding path program 125 times [2024-05-06 18:05:53,189 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:53,189 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:53,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:53,467 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:05:53,467 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:53,467 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:53,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:53,639 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:05:53,698 INFO L85 PathProgramCache]: Analyzing trace with hash -445483267, now seen corresponding path program 126 times [2024-05-06 18:05:53,698 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:53,698 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:53,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:53,878 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:05:53,878 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:53,878 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:53,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:54,056 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:05:54,117 INFO L85 PathProgramCache]: Analyzing trace with hash -925078519, now seen corresponding path program 127 times [2024-05-06 18:05:54,117 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:54,118 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:54,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:54,290 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:05:54,291 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:54,291 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:54,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:54,466 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:05:54,585 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:05:54,585 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:05:54,715 INFO L85 PathProgramCache]: Analyzing trace with hash 2009350210, now seen corresponding path program 128 times [2024-05-06 18:05:54,715 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:54,715 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:54,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:54,868 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:54,868 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:54,869 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:54,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:55,018 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:55,220 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:05:55,220 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:06:04,294 WARN L293 SmtUtils]: Spent 6.13s on a formula simplification. DAG size of input: 34 DAG size of output: 14 (called from [L 210] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.abduction.Abducer.solveAbductionProblem) [2024-05-06 18:06:04,326 INFO L85 PathProgramCache]: Analyzing trace with hash -2134652088, now seen corresponding path program 129 times [2024-05-06 18:06:04,326 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:04,326 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:04,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:04,493 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:06:04,493 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:04,494 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:04,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:04,661 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:06:04,723 INFO L85 PathProgramCache]: Analyzing trace with hash -1749704428, now seen corresponding path program 130 times [2024-05-06 18:06:04,723 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:04,723 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:04,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:04,892 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:06:04,893 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:04,893 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:04,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:05,061 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:06:05,122 INFO L85 PathProgramCache]: Analyzing trace with hash 1593738448, now seen corresponding path program 131 times [2024-05-06 18:06:05,123 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:05,123 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:05,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:05,292 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:06:05,293 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:05,293 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:05,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:05,455 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:06:05,514 INFO L85 PathProgramCache]: Analyzing trace with hash 1593738448, now seen corresponding path program 132 times [2024-05-06 18:06:05,514 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:05,514 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:05,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:05,686 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:06:05,687 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:05,687 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:05,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:05,861 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:06:05,924 INFO L85 PathProgramCache]: Analyzing trace with hash -2133714794, now seen corresponding path program 133 times [2024-05-06 18:06:05,924 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:05,924 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:05,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:06,246 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:06:06,246 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:06,246 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:06,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:06,531 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:06:06,652 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:06:06,653 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:06:06,780 INFO L85 PathProgramCache]: Analyzing trace with hash -1971660842, now seen corresponding path program 7 times [2024-05-06 18:06:06,781 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:06,781 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:06,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:07,005 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:06:07,005 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:07,005 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:07,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:07,190 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:06:07,288 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:06:07,326 INFO L85 PathProgramCache]: Analyzing trace with hash -991943098, now seen corresponding path program 8 times [2024-05-06 18:06:07,327 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:07,327 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:07,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:07,524 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:06:07,524 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:07,524 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:07,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:07,692 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:06:07,813 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:06:07,868 INFO L85 PathProgramCache]: Analyzing trace with hash 458282957, now seen corresponding path program 9 times [2024-05-06 18:06:07,868 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:07,869 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:07,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:08,028 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:06:08,028 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:08,028 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:08,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:08,184 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:06:08,243 INFO L85 PathProgramCache]: Analyzing trace with hash 1321870621, now seen corresponding path program 10 times [2024-05-06 18:06:08,243 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:08,243 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:08,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:08,406 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:06:08,406 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:08,406 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:08,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:08,705 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:06:08,808 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:06:08,809 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:06:08,937 INFO L85 PathProgramCache]: Analyzing trace with hash -123764059, now seen corresponding path program 11 times [2024-05-06 18:06:08,937 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:08,937 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:08,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:09,097 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:06:09,098 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:09,098 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:09,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:09,255 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:06:09,312 INFO L85 PathProgramCache]: Analyzing trace with hash 2011042552, now seen corresponding path program 12 times [2024-05-06 18:06:09,312 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:09,312 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:09,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:09,469 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:06:09,469 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:09,469 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:09,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:09,624 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:06:09,680 INFO L85 PathProgramCache]: Analyzing trace with hash 1014998605, now seen corresponding path program 7 times [2024-05-06 18:06:09,680 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:09,680 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:09,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:09,852 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:06:09,852 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:09,852 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:09,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:10,018 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:06:10,122 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:06:10,123 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:06:10,243 INFO L85 PathProgramCache]: Analyzing trace with hash -1098383943, now seen corresponding path program 8 times [2024-05-06 18:06:10,244 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:10,244 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:10,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:10,405 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:06:10,405 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:10,405 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:10,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:10,561 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:06:10,651 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:06:10,688 INFO L85 PathProgramCache]: Analyzing trace with hash 309836995, now seen corresponding path program 9 times [2024-05-06 18:06:10,688 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:10,688 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:10,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:10,849 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:06:10,850 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:10,850 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:10,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:11,148 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:06:11,270 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:06:11,327 INFO L85 PathProgramCache]: Analyzing trace with hash -148628880, now seen corresponding path program 10 times [2024-05-06 18:06:11,328 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:11,328 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:11,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:11,493 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:06:11,493 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:11,493 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:11,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:11,650 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:06:11,713 INFO L85 PathProgramCache]: Analyzing trace with hash -312527142, now seen corresponding path program 11 times [2024-05-06 18:06:11,713 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:11,713 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:11,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:11,878 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:06:11,878 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:11,878 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:11,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:12,047 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:06:12,171 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:06:12,172 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:06:12,293 INFO L85 PathProgramCache]: Analyzing trace with hash -2083004510, now seen corresponding path program 12 times [2024-05-06 18:06:12,294 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:12,294 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:12,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:12,462 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:06:12,462 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:12,463 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:12,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:12,620 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:06:12,679 INFO L85 PathProgramCache]: Analyzing trace with hash -1298130228, now seen corresponding path program 7 times [2024-05-06 18:06:12,679 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:12,680 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:12,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:12,852 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:06:12,852 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:12,852 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:12,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:13,032 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:06:13,133 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:06:13,133 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:06:13,254 INFO L85 PathProgramCache]: Analyzing trace with hash -957774344, now seen corresponding path program 8 times [2024-05-06 18:06:13,254 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:13,254 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:13,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:13,547 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:06:13,547 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:13,547 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:13,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:13,711 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:06:13,821 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:06:13,875 INFO L85 PathProgramCache]: Analyzing trace with hash 373767268, now seen corresponding path program 9 times [2024-05-06 18:06:13,876 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:13,876 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:13,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:14,042 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:06:14,042 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:14,042 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:14,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:14,201 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:06:14,304 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:06:14,337 INFO L85 PathProgramCache]: Analyzing trace with hash -2106022289, now seen corresponding path program 10 times [2024-05-06 18:06:14,337 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:14,337 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:14,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:14,500 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:06:14,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:14,501 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:14,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:14,662 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:06:14,717 INFO L85 PathProgramCache]: Analyzing trace with hash -862180677, now seen corresponding path program 11 times [2024-05-06 18:06:14,717 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:14,717 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:14,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:14,885 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:06:14,886 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:14,886 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:14,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:15,049 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:06:15,151 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:06:15,151 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:06:15,281 INFO L85 PathProgramCache]: Analyzing trace with hash 2010273731, now seen corresponding path program 12 times [2024-05-06 18:06:15,281 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:15,281 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:15,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:15,437 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:06:15,438 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:15,438 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:15,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:15,593 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:06:15,652 INFO L85 PathProgramCache]: Analyzing trace with hash 1933371248, now seen corresponding path program 134 times [2024-05-06 18:06:15,652 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:15,652 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:15,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:16,016 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:06:16,016 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:16,016 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:16,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:16,181 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:06:16,300 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:06:16,300 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:06:16,936 INFO L85 PathProgramCache]: Analyzing trace with hash 1155083164, now seen corresponding path program 135 times [2024-05-06 18:06:16,936 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:16,937 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:16,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:17,087 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:06:17,087 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:17,087 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:17,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:17,234 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:06:17,340 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:06:17,377 INFO L85 PathProgramCache]: Analyzing trace with hash 1447840576, now seen corresponding path program 136 times [2024-05-06 18:06:17,377 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:17,378 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:17,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:17,530 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:06:17,530 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:17,530 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:17,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:17,681 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:06:17,793 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:06:17,842 INFO L85 PathProgramCache]: Analyzing trace with hash 1990026515, now seen corresponding path program 137 times [2024-05-06 18:06:17,842 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:17,842 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:17,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:17,991 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:06:17,992 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:17,992 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:18,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:18,138 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:06:18,199 INFO L85 PathProgramCache]: Analyzing trace with hash 1561280663, now seen corresponding path program 138 times [2024-05-06 18:06:18,200 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:18,200 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:18,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:18,363 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:06:18,363 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:18,363 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:18,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:18,656 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:06:18,786 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:06:18,786 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:06:18,931 INFO L85 PathProgramCache]: Analyzing trace with hash -628542305, now seen corresponding path program 139 times [2024-05-06 18:06:18,932 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:18,932 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:18,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:19,089 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:06:19,089 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:19,089 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:19,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:19,244 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:06:19,484 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:06:19,484 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:06:24,783 INFO L85 PathProgramCache]: Analyzing trace with hash 1845809460, now seen corresponding path program 140 times [2024-05-06 18:06:24,783 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:24,784 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:24,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:24,934 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:06:24,934 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:24,934 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:24,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:25,100 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:06:25,157 INFO L85 PathProgramCache]: Analyzing trace with hash 1385519280, now seen corresponding path program 141 times [2024-05-06 18:06:25,157 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:25,157 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:25,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:25,325 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:06:25,325 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:25,325 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:25,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:25,496 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:06:25,552 INFO L85 PathProgramCache]: Analyzing trace with hash 1425580, now seen corresponding path program 142 times [2024-05-06 18:06:25,552 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:25,552 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:25,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:25,711 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:06:25,712 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:25,712 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:25,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:26,024 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:06:26,084 INFO L85 PathProgramCache]: Analyzing trace with hash 1425580, now seen corresponding path program 143 times [2024-05-06 18:06:26,085 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:26,085 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:26,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:26,241 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:06:26,242 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:26,242 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:26,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:26,406 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:06:26,661 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:06:26,661 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:06:31,695 INFO L85 PathProgramCache]: Analyzing trace with hash -479074167, now seen corresponding path program 144 times [2024-05-06 18:06:31,695 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:31,695 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:31,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:31,860 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:06:31,860 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:31,860 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:31,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:32,026 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:06:32,081 INFO L85 PathProgramCache]: Analyzing trace with hash -828746047, now seen corresponding path program 145 times [2024-05-06 18:06:32,081 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:32,081 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:32,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:32,232 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:06:32,232 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:32,233 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:32,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:32,381 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:06:32,502 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:06:32,503 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:06:32,655 INFO L85 PathProgramCache]: Analyzing trace with hash -1855964644, now seen corresponding path program 146 times [2024-05-06 18:06:32,655 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:32,655 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:32,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:32,914 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:06:32,914 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:32,914 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:32,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:33,071 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:06:33,268 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:06:33,268 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:06:54,504 WARN L293 SmtUtils]: Spent 16.05s on a formula simplification. DAG size of input: 33 DAG size of output: 14 (called from [L 210] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.abduction.Abducer.solveAbductionProblem) [2024-05-06 18:06:54,537 INFO L85 PathProgramCache]: Analyzing trace with hash -1855964644, now seen corresponding path program 147 times [2024-05-06 18:06:54,537 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:54,537 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:54,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:54,693 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:06:54,693 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:54,693 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:54,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:54,842 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:06:54,951 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:06:54,997 INFO L85 PathProgramCache]: Analyzing trace with hash -1700328248, now seen corresponding path program 148 times [2024-05-06 18:06:54,998 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:54,998 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:55,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:55,161 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:06:55,161 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:55,161 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:55,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:55,323 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:06:55,437 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:06:55,496 INFO L85 PathProgramCache]: Analyzing trace with hash -1170567276, now seen corresponding path program 149 times [2024-05-06 18:06:55,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:55,496 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:55,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:55,656 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:06:55,656 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:55,656 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:55,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:55,945 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:06:56,008 INFO L85 PathProgramCache]: Analyzing trace with hash -1170567276, now seen corresponding path program 150 times [2024-05-06 18:06:56,008 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:56,009 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:56,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:56,179 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:06:56,180 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:56,180 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:56,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:56,352 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:06:56,471 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:06:56,528 INFO L85 PathProgramCache]: Analyzing trace with hash -1927846326, now seen corresponding path program 151 times [2024-05-06 18:06:56,528 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:56,528 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:56,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:56,691 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:06:56,691 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:56,692 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:56,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:56,851 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:06:56,912 INFO L85 PathProgramCache]: Analyzing trace with hash -166352257, now seen corresponding path program 152 times [2024-05-06 18:06:56,912 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:56,913 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:56,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:57,081 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:06:57,081 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:57,081 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:57,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:57,253 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:06:57,386 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:06:57,387 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:06:57,513 INFO L85 PathProgramCache]: Analyzing trace with hash -950701438, now seen corresponding path program 153 times [2024-05-06 18:06:57,514 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:57,514 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:57,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:57,676 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:06:57,676 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:57,676 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:57,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:57,840 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:06:58,057 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:06:58,058 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:07:01,467 INFO L85 PathProgramCache]: Analyzing trace with hash -1331351467, now seen corresponding path program 154 times [2024-05-06 18:07:01,467 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:01,468 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:01,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:01,643 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:07:01,644 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:01,644 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:01,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:01,824 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:07:01,963 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:07:01,964 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:07:02,118 INFO L85 PathProgramCache]: Analyzing trace with hash 1677778343, now seen corresponding path program 155 times [2024-05-06 18:07:02,119 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:02,119 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:02,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:02,298 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:07:02,299 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:02,299 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:02,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:02,475 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:07:02,616 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:07:02,616 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:07:02,759 INFO L85 PathProgramCache]: Analyzing trace with hash 471521943, now seen corresponding path program 156 times [2024-05-06 18:07:02,759 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:02,759 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:02,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:02,941 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:07:02,941 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:02,941 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:02,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:03,124 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:07:03,250 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:07:03,313 INFO L85 PathProgramCache]: Analyzing trace with hash 1732279213, now seen corresponding path program 157 times [2024-05-06 18:07:03,314 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:03,314 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:03,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:03,616 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:07:03,616 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:03,616 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:03,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:03,802 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:07:03,928 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:07:03,928 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:07:04,054 INFO L85 PathProgramCache]: Analyzing trace with hash 1369784018, now seen corresponding path program 158 times [2024-05-06 18:07:04,054 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:04,055 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:04,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:04,250 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:07:04,250 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:04,250 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:04,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:04,454 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:07:04,606 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:07:04,671 INFO L85 PathProgramCache]: Analyzing trace with hash -486367542, now seen corresponding path program 159 times [2024-05-06 18:07:04,671 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:04,671 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:04,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:04,878 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:07:04,879 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:04,879 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:04,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:05,078 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:07:05,210 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:07:05,256 INFO L85 PathProgramCache]: Analyzing trace with hash 1362566457, now seen corresponding path program 160 times [2024-05-06 18:07:05,256 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:05,256 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:05,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:05,461 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 2 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:07:05,461 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:05,461 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:05,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:05,674 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 2 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:07:05,739 INFO L85 PathProgramCache]: Analyzing trace with hash -710111942, now seen corresponding path program 161 times [2024-05-06 18:07:05,739 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:05,739 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:05,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:06,122 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:07:06,122 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:06,122 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:06,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:06,351 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:07:06,478 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:07:06,479 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:07:08,610 INFO L85 PathProgramCache]: Analyzing trace with hash 2064883069, now seen corresponding path program 162 times [2024-05-06 18:07:08,610 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:08,611 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:08,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:08,825 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:07:08,826 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:08,826 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:08,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:09,056 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:07:09,151 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:07:09,188 INFO L85 PathProgramCache]: Analyzing trace with hash -413133441, now seen corresponding path program 163 times [2024-05-06 18:07:09,189 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:09,189 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:09,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:09,414 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:07:09,414 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:09,415 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:09,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:09,664 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:07:09,773 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:07:09,805 INFO L85 PathProgramCache]: Analyzing trace with hash -413133453, now seen corresponding path program 164 times [2024-05-06 18:07:09,806 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:09,806 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:09,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:10,257 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:07:10,257 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:10,257 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:10,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:10,489 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:07:10,546 INFO L85 PathProgramCache]: Analyzing trace with hash 77765696, now seen corresponding path program 165 times [2024-05-06 18:07:10,546 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:10,546 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:10,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:10,761 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:07:10,762 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:10,762 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:10,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:10,980 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:07:11,198 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:07:11,198 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:07:27,886 WARN L293 SmtUtils]: Spent 14.11s on a formula simplification. DAG size of input: 33 DAG size of output: 28 (called from [L 210] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.abduction.Abducer.solveAbductionProblem) [2024-05-06 18:07:29,896 WARN L854 $PredicateComparison]: unable to prove that (and (forall ((v_~q2~0.base_In_128 Int) (v_~q2~0.offset_In_128 Int)) (= (select (select |c_#memory_int| v_~q2~0.base_In_128) (+ (* c_~q2_front~0 4) v_~q2~0.offset_In_128)) 0)) (forall ((v_~q1~0.offset_In_105 Int) (v_~q1~0.base_In_105 Int) (v_~q1_front~0_In_150 Int)) (let ((.cse0 (select (select |c_#memory_int| v_~q1~0.base_In_105) (+ v_~q1~0.offset_In_105 (* v_~q1_front~0_In_150 4))))) (or (< 4294967295 .cse0) (< (+ 4294967295 .cse0) 0) (< v_~q1_front~0_In_150 0) (= 0 .cse0))))) is different from false [2024-05-06 18:07:29,899 INFO L85 PathProgramCache]: Analyzing trace with hash 2131944473, now seen corresponding path program 166 times [2024-05-06 18:07:29,899 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:29,899 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:29,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:30,176 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:07:30,177 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:30,177 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:30,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:30,403 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:07:30,532 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:07:30,533 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:07:30,771 INFO L85 PathProgramCache]: Analyzing trace with hash 1665770091, now seen corresponding path program 167 times [2024-05-06 18:07:30,771 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:30,771 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:30,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:31,103 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:07:31,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:31,103 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:31,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:31,328 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:07:31,450 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:07:31,503 INFO L85 PathProgramCache]: Analyzing trace with hash 99266129, now seen corresponding path program 168 times [2024-05-06 18:07:31,503 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:31,503 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:31,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:31,732 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:07:31,732 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:31,732 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:31,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:31,963 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:07:32,083 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:07:32,084 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:07:32,224 INFO L85 PathProgramCache]: Analyzing trace with hash 905506220, now seen corresponding path program 169 times [2024-05-06 18:07:32,224 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:32,224 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:32,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:32,448 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:07:32,448 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:32,448 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:32,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:32,677 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:07:32,876 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:07:32,876 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:07:38,382 INFO L85 PathProgramCache]: Analyzing trace with hash 905506220, now seen corresponding path program 170 times [2024-05-06 18:07:38,383 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:38,383 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:38,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:38,615 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:07:38,615 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:38,615 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:38,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:38,849 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:07:38,956 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:07:38,996 INFO L85 PathProgramCache]: Analyzing trace with hash -1994077384, now seen corresponding path program 171 times [2024-05-06 18:07:38,996 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:38,997 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:39,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:39,222 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:07:39,223 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:39,223 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:39,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:39,452 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:07:39,559 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:07:39,560 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:07:40,440 INFO L85 PathProgramCache]: Analyzing trace with hash -1994077384, now seen corresponding path program 172 times [2024-05-06 18:07:40,440 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:40,441 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:40,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:40,673 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:07:40,673 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:40,673 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:40,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:41,025 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:07:41,129 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:07:41,173 INFO L85 PathProgramCache]: Analyzing trace with hash -1686855900, now seen corresponding path program 173 times [2024-05-06 18:07:41,173 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:41,173 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:41,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:41,410 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:07:41,410 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:41,410 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:41,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:41,641 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:07:41,756 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:07:41,804 INFO L85 PathProgramCache]: Analyzing trace with hash -1686855900, now seen corresponding path program 174 times [2024-05-06 18:07:41,804 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:41,804 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:41,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:42,063 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:07:42,063 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:42,063 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:42,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:42,328 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:07:42,430 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:07:42,473 INFO L85 PathProgramCache]: Analyzing trace with hash -752924486, now seen corresponding path program 175 times [2024-05-06 18:07:42,473 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:42,473 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:42,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:42,711 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:07:42,712 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:42,712 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:42,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:43,067 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:07:43,193 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:07:43,194 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:07:43,376 INFO L85 PathProgramCache]: Analyzing trace with hash 589129403, now seen corresponding path program 176 times [2024-05-06 18:07:43,376 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:43,376 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:43,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:43,648 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:07:43,648 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:43,648 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:43,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:43,897 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:07:44,011 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:07:44,060 INFO L85 PathProgramCache]: Analyzing trace with hash 1083143169, now seen corresponding path program 177 times [2024-05-06 18:07:44,060 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:44,060 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:44,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:44,306 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:07:44,306 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:44,306 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:44,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:44,555 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:07:44,676 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:07:44,719 INFO L85 PathProgramCache]: Analyzing trace with hash -1130112014, now seen corresponding path program 178 times [2024-05-06 18:07:44,719 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:44,719 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:44,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:44,968 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:07:44,968 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:44,968 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:45,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:45,327 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:07:45,388 INFO L85 PathProgramCache]: Analyzing trace with hash -673733224, now seen corresponding path program 179 times [2024-05-06 18:07:45,388 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:45,388 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:45,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:45,632 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:07:45,633 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:45,633 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:45,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:45,879 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:07:45,999 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:07:45,999 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:07:46,151 INFO L85 PathProgramCache]: Analyzing trace with hash -1837570592, now seen corresponding path program 180 times [2024-05-06 18:07:46,151 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:46,152 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:46,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:46,413 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:07:46,413 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:46,413 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:46,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:46,674 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:07:46,735 INFO L85 PathProgramCache]: Analyzing trace with hash -2053306125, now seen corresponding path program 181 times [2024-05-06 18:07:46,735 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:46,736 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:46,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:47,108 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:07:47,109 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:47,109 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:47,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:47,363 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:07:47,562 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:07:47,563 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:07:50,200 INFO L85 PathProgramCache]: Analyzing trace with hash -1686839031, now seen corresponding path program 3 times [2024-05-06 18:07:50,201 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:50,201 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:50,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:50,506 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:07:50,506 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:50,506 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:50,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:50,735 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:07:50,847 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:07:50,847 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:07:50,995 INFO L85 PathProgramCache]: Analyzing trace with hash -752401541, now seen corresponding path program 4 times [2024-05-06 18:07:50,995 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:50,995 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:51,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:51,228 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:07:51,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:51,228 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:51,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:51,588 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:07:51,709 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:07:51,773 INFO L85 PathProgramCache]: Analyzing trace with hash -1849610431, now seen corresponding path program 5 times [2024-05-06 18:07:51,773 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:51,773 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:51,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:52,010 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:07:52,010 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:52,010 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:52,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:52,246 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:07:52,476 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:07:52,477 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:08:01,044 WARN L293 SmtUtils]: Spent 6.03s on a formula simplification. DAG size of input: 34 DAG size of output: 14 (called from [L 210] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.abduction.Abducer.solveAbductionProblem) [2024-05-06 18:08:01,090 INFO L85 PathProgramCache]: Analyzing trace with hash 1326051795, now seen corresponding path program 1 times [2024-05-06 18:08:01,090 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:01,090 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:01,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:01,350 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:08:01,350 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:01,350 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:01,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:01,745 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:08:01,755 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 2 more)] === [2024-05-06 18:08:01,756 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:08:01,756 INFO L85 PathProgramCache]: Analyzing trace with hash -249473579, now seen corresponding path program 1 times [2024-05-06 18:08:01,759 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:08:01,760 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1610713239] [2024-05-06 18:08:01,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:01,760 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:01,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:02,115 INFO L134 CoverageAnalysis]: Checked inductivity of 459 backedges. 109 proven. 146 refuted. 0 times theorem prover too weak. 204 trivial. 0 not checked. [2024-05-06 18:08:02,116 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:08:02,116 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1610713239] [2024-05-06 18:08:02,116 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1610713239] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:08:02,116 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [628335879] [2024-05-06 18:08:02,116 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:02,117 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:08:02,117 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:08:02,169 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:08:02,170 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2024-05-06 18:08:02,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:02,960 INFO L262 TraceCheckSpWp]: Trace formula consists of 844 conjuncts, 9 conjunts are in the unsatisfiable core [2024-05-06 18:08:02,972 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 18:08:03,165 INFO L134 CoverageAnalysis]: Checked inductivity of 459 backedges. 98 proven. 1 refuted. 0 times theorem prover too weak. 360 trivial. 0 not checked. [2024-05-06 18:08:03,165 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-06 18:08:03,406 INFO L134 CoverageAnalysis]: Checked inductivity of 459 backedges. 96 proven. 3 refuted. 0 times theorem prover too weak. 360 trivial. 0 not checked. [2024-05-06 18:08:03,406 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [628335879] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-06 18:08:03,406 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-06 18:08:03,406 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9] total 19 [2024-05-06 18:08:03,408 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [240393110] [2024-05-06 18:08:03,408 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-06 18:08:03,412 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 19 states [2024-05-06 18:08:03,412 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:08:03,414 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2024-05-06 18:08:03,414 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=77, Invalid=265, Unknown=0, NotChecked=0, Total=342 [2024-05-06 18:08:03,415 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:08:03,415 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:08:03,416 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 19 states, 19 states have (on average 15.842105263157896) internal successors, (301), 19 states have internal predecessors, (301), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:08:03,416 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:08:03,816 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:08:03,869 INFO L85 PathProgramCache]: Analyzing trace with hash 97054817, now seen corresponding path program 3 times [2024-05-06 18:08:03,869 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:03,869 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:03,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:08:03,993 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:08:04,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:08:04,217 INFO L85 PathProgramCache]: Analyzing trace with hash -1286267118, now seen corresponding path program 4 times [2024-05-06 18:08:04,217 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:04,217 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:04,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:04,389 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:08:04,390 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:04,390 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:04,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:04,527 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:08:04,646 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:08:04,696 INFO L85 PathProgramCache]: Analyzing trace with hash -1725239752, now seen corresponding path program 182 times [2024-05-06 18:08:04,696 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:04,697 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:04,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:04,837 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:08:04,837 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:04,837 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:04,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:04,976 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:08:05,042 INFO L85 PathProgramCache]: Analyzing trace with hash -1942823918, now seen corresponding path program 183 times [2024-05-06 18:08:05,043 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:05,043 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:05,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:05,594 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 3 proven. 13 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 18:08:05,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:05,595 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:05,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:05,874 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 3 proven. 13 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 18:08:05,991 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:08:06,048 INFO L85 PathProgramCache]: Analyzing trace with hash 1276141679, now seen corresponding path program 184 times [2024-05-06 18:08:06,049 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:06,049 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:06,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:06,358 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 2 proven. 11 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:08:06,358 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:06,358 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:06,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:06,551 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 2 proven. 11 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:08:06,614 INFO L85 PathProgramCache]: Analyzing trace with hash 905687227, now seen corresponding path program 185 times [2024-05-06 18:08:06,614 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:06,614 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:06,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:06,773 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2024-05-06 18:08:06,774 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:06,774 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:06,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:06,928 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2024-05-06 18:08:07,185 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:08:07,185 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:08:10,629 INFO L85 PathProgramCache]: Analyzing trace with hash 824967838, now seen corresponding path program 186 times [2024-05-06 18:08:10,629 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:10,630 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:10,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:10,831 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:08:10,831 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:10,831 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:10,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:11,220 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:08:11,296 INFO L85 PathProgramCache]: Analyzing trace with hash -862359559, now seen corresponding path program 187 times [2024-05-06 18:08:11,296 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:11,296 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:11,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:11,478 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 18:08:11,478 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:11,478 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:11,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:11,653 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 18:08:11,783 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:08:11,784 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:08:11,949 INFO L85 PathProgramCache]: Analyzing trace with hash 866140773, now seen corresponding path program 188 times [2024-05-06 18:08:11,950 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:11,950 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:11,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:12,135 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 18:08:12,135 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:12,136 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:12,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:12,302 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 18:08:12,422 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:08:12,472 INFO L85 PathProgramCache]: Analyzing trace with hash 1080561047, now seen corresponding path program 189 times [2024-05-06 18:08:12,473 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:12,473 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:12,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:12,644 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 18:08:12,645 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:12,645 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:12,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:12,817 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 18:08:12,945 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:08:12,989 INFO L85 PathProgramCache]: Analyzing trace with hash -459433444, now seen corresponding path program 190 times [2024-05-06 18:08:12,989 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:12,989 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:13,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:13,156 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:08:13,156 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:13,156 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:13,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:13,523 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:08:13,647 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:08:13,647 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:08:13,791 INFO L85 PathProgramCache]: Analyzing trace with hash -291915146, now seen corresponding path program 191 times [2024-05-06 18:08:13,791 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:13,792 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:13,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:13,950 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:08:13,950 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:13,951 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:13,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:14,109 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:08:14,224 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:08:14,269 INFO L85 PathProgramCache]: Analyzing trace with hash -314009404, now seen corresponding path program 192 times [2024-05-06 18:08:14,269 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:14,269 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:14,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:14,426 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:08:14,427 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:14,427 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:14,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:14,584 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:08:14,710 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:08:14,710 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:08:14,848 INFO L85 PathProgramCache]: Analyzing trace with hash 1790985934, now seen corresponding path program 193 times [2024-05-06 18:08:14,848 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:14,848 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:14,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:15,000 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:08:15,000 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:15,000 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:15,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:15,157 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:08:15,502 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:08:15,502 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:08:15,641 INFO L85 PathProgramCache]: Analyzing trace with hash 1090062538, now seen corresponding path program 13 times [2024-05-06 18:08:15,642 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:15,642 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:15,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:15,804 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 18:08:15,804 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:15,804 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:15,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:15,966 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 18:08:16,061 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:08:16,095 INFO L85 PathProgramCache]: Analyzing trace with hash -567798830, now seen corresponding path program 14 times [2024-05-06 18:08:16,095 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:16,095 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:16,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:16,260 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 18:08:16,260 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:16,260 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:16,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:16,426 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 18:08:16,572 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:08:16,618 INFO L85 PathProgramCache]: Analyzing trace with hash 2043590081, now seen corresponding path program 15 times [2024-05-06 18:08:16,618 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:16,618 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:16,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:16,790 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:08:16,791 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:16,791 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:16,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:16,946 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:08:17,055 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:08:17,056 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:08:17,182 INFO L85 PathProgramCache]: Analyzing trace with hash 481564209, now seen corresponding path program 16 times [2024-05-06 18:08:17,182 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:17,182 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:17,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:17,342 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:08:17,342 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:17,342 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:17,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:17,592 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:08:17,687 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:08:17,688 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:08:17,821 INFO L85 PathProgramCache]: Analyzing trace with hash 801496645, now seen corresponding path program 13 times [2024-05-06 18:08:17,821 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:17,821 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:17,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:17,987 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 18:08:17,987 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:17,988 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:18,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:18,153 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 18:08:18,258 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:08:18,294 INFO L85 PathProgramCache]: Analyzing trace with hash -923406921, now seen corresponding path program 14 times [2024-05-06 18:08:18,294 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:18,294 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:18,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:18,462 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 18:08:18,463 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:18,463 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:18,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:18,634 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 18:08:18,766 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:08:18,820 INFO L85 PathProgramCache]: Analyzing trace with hash 456699388, now seen corresponding path program 15 times [2024-05-06 18:08:18,820 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:18,820 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:18,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:18,985 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:08:18,985 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:18,985 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:19,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:19,150 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:08:19,278 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:08:19,279 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:08:19,434 INFO L85 PathProgramCache]: Analyzing trace with hash -262362474, now seen corresponding path program 16 times [2024-05-06 18:08:19,434 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:19,434 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:19,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:19,697 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:08:19,697 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:19,697 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:19,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:19,848 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:08:19,959 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:08:19,959 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:08:20,104 INFO L85 PathProgramCache]: Analyzing trace with hash 627532780, now seen corresponding path program 13 times [2024-05-06 18:08:20,104 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:20,104 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:20,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:20,273 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 18:08:20,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:20,273 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:20,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:20,453 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 18:08:20,548 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:08:20,584 INFO L85 PathProgramCache]: Analyzing trace with hash -2021319440, now seen corresponding path program 14 times [2024-05-06 18:08:20,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:20,584 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:20,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:20,747 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 18:08:20,747 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:20,747 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:20,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:20,909 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 18:08:21,023 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:08:21,062 INFO L85 PathProgramCache]: Analyzing trace with hash -285380253, now seen corresponding path program 15 times [2024-05-06 18:08:21,062 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:21,062 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:21,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:21,228 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:08:21,229 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:21,229 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:21,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:21,485 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:08:21,609 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:08:21,609 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:08:21,772 INFO L85 PathProgramCache]: Analyzing trace with hash 1791909455, now seen corresponding path program 16 times [2024-05-06 18:08:21,773 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:21,773 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:21,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:21,927 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:08:21,927 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:21,927 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:21,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:22,085 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:08:22,210 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:08:22,211 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:08:22,345 INFO L85 PathProgramCache]: Analyzing trace with hash 1760411432, now seen corresponding path program 194 times [2024-05-06 18:08:22,345 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:22,345 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:22,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:22,500 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 18:08:22,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:22,501 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:22,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:22,659 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 18:08:22,768 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:08:22,817 INFO L85 PathProgramCache]: Analyzing trace with hash -1261819596, now seen corresponding path program 195 times [2024-05-06 18:08:22,817 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:22,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:22,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:22,977 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 18:08:22,977 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:22,977 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:23,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:23,139 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 18:08:23,255 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:08:23,298 INFO L85 PathProgramCache]: Analyzing trace with hash 1771662239, now seen corresponding path program 196 times [2024-05-06 18:08:23,298 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:23,298 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:23,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:23,545 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:08:23,546 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:23,546 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:23,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:23,697 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:08:23,815 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:08:23,816 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:08:23,958 INFO L85 PathProgramCache]: Analyzing trace with hash 334245011, now seen corresponding path program 197 times [2024-05-06 18:08:23,958 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:23,958 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:23,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:24,115 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:08:24,115 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:24,115 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:24,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:24,274 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:08:24,413 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:08:24,413 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:08:24,569 INFO L85 PathProgramCache]: Analyzing trace with hash -1621250283, now seen corresponding path program 198 times [2024-05-06 18:08:24,569 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:24,569 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:24,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:24,742 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 2 proven. 11 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:08:24,742 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:24,742 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:24,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:24,922 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 2 proven. 11 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:08:25,043 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:08:25,043 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:08:25,186 INFO L85 PathProgramCache]: Analyzing trace with hash 1051634168, now seen corresponding path program 199 times [2024-05-06 18:08:25,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:25,186 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:25,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:25,364 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 2 proven. 11 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:08:25,364 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:25,364 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:25,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:25,640 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 2 proven. 11 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:08:25,753 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 18:08:25,813 INFO L85 PathProgramCache]: Analyzing trace with hash -1759078300, now seen corresponding path program 200 times [2024-05-06 18:08:25,813 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:25,813 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:25,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:26,001 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 2 proven. 11 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:08:26,001 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:26,001 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:26,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:26,189 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 2 proven. 11 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:08:26,340 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:08:26,340 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:08:26,486 INFO L85 PathProgramCache]: Analyzing trace with hash 1230784725, now seen corresponding path program 201 times [2024-05-06 18:08:26,487 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:26,487 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:26,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:26,657 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 4 proven. 13 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-06 18:08:26,657 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:26,657 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:26,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:26,871 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 4 proven. 13 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-06 18:08:26,994 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:08:26,994 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:08:27,132 INFO L85 PathProgramCache]: Analyzing trace with hash 1061541231, now seen corresponding path program 202 times [2024-05-06 18:08:27,133 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:27,133 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:27,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:27,304 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 4 proven. 13 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:08:27,304 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:27,304 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:27,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:27,569 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 4 proven. 13 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:08:27,634 INFO L85 PathProgramCache]: Analyzing trace with hash -1025522038, now seen corresponding path program 203 times [2024-05-06 18:08:27,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:27,634 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:27,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:27,798 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 13 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 18:08:27,798 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:27,798 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:27,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:27,964 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 13 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 18:08:28,037 INFO L85 PathProgramCache]: Analyzing trace with hash -1730493052, now seen corresponding path program 204 times [2024-05-06 18:08:28,037 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:28,037 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:28,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:28,207 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2024-05-06 18:08:28,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:28,208 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:28,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:28,378 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2024-05-06 18:08:28,521 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:08:28,522 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:08:28,662 INFO L85 PathProgramCache]: Analyzing trace with hash 836623636, now seen corresponding path program 205 times [2024-05-06 18:08:28,662 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:28,662 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:28,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:28,878 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:08:28,879 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:28,879 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:28,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:29,212 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:08:29,338 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 18:08:29,383 INFO L85 PathProgramCache]: Analyzing trace with hash 165529808, now seen corresponding path program 206 times [2024-05-06 18:08:29,384 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:29,384 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:29,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:29,615 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:08:29,615 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:29,615 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:29,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:29,827 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:08:29,965 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:08:29,966 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:08:31,075 INFO L85 PathProgramCache]: Analyzing trace with hash 1284582383, now seen corresponding path program 207 times [2024-05-06 18:08:31,075 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:31,075 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:31,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:31,274 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:08:31,274 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:31,274 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:31,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:31,481 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:08:31,629 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:08:31,629 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:08:31,828 INFO L85 PathProgramCache]: Analyzing trace with hash -1865388626, now seen corresponding path program 208 times [2024-05-06 18:08:31,828 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:31,828 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:31,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:32,131 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:08:32,131 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:32,131 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:32,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:32,324 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:08:32,477 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:08:32,477 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:08:32,627 INFO L85 PathProgramCache]: Analyzing trace with hash -306712171, now seen corresponding path program 209 times [2024-05-06 18:08:32,627 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:32,627 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:32,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:32,808 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:08:32,808 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:32,808 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:32,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:32,995 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:08:33,132 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:08:33,132 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:08:33,280 INFO L85 PathProgramCache]: Analyzing trace with hash 1149371585, now seen corresponding path program 7 times [2024-05-06 18:08:33,280 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:33,280 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:33,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:33,459 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2024-05-06 18:08:33,459 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:33,460 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:33,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:33,639 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2024-05-06 18:08:33,778 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:08:33,778 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:08:33,913 INFO L85 PathProgramCache]: Analyzing trace with hash 2115300194, now seen corresponding path program 8 times [2024-05-06 18:08:33,913 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:33,913 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:33,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:34,175 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2024-05-06 18:08:34,175 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:34,175 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:34,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:34,351 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2024-05-06 18:08:34,490 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:08:34,490 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:08:34,627 INFO L85 PathProgramCache]: Analyzing trace with hash -278109604, now seen corresponding path program 7 times [2024-05-06 18:08:34,627 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:34,627 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:34,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:34,809 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2024-05-06 18:08:34,809 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:34,809 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:34,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:34,996 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2024-05-06 18:08:35,133 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:08:35,133 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:08:35,260 INFO L85 PathProgramCache]: Analyzing trace with hash -1087771737, now seen corresponding path program 8 times [2024-05-06 18:08:35,260 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:35,260 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:35,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:35,476 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2024-05-06 18:08:35,477 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:35,477 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:35,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:35,660 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2024-05-06 18:08:35,876 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:08:35,876 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:08:36,018 INFO L85 PathProgramCache]: Analyzing trace with hash 668288927, now seen corresponding path program 7 times [2024-05-06 18:08:36,018 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:36,018 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:36,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:36,216 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2024-05-06 18:08:36,216 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:36,216 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:36,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:36,412 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2024-05-06 18:08:36,538 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:08:36,539 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:08:36,817 INFO L85 PathProgramCache]: Analyzing trace with hash 583910724, now seen corresponding path program 8 times [2024-05-06 18:08:36,817 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:36,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:36,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:36,996 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2024-05-06 18:08:36,996 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:36,996 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:37,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:37,195 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2024-05-06 18:08:37,316 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:08:37,316 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:08:37,447 INFO L85 PathProgramCache]: Analyzing trace with hash 247824729, now seen corresponding path program 210 times [2024-05-06 18:08:37,447 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:37,447 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:37,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:37,645 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2024-05-06 18:08:37,645 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:37,646 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:37,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:37,910 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2024-05-06 18:08:38,027 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:08:38,027 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 18:08:38,143 INFO L85 PathProgramCache]: Analyzing trace with hash 1499231690, now seen corresponding path program 211 times [2024-05-06 18:08:38,143 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:38,143 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:38,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:38,314 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2024-05-06 18:08:38,314 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:38,314 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:38,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:38,485 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2024-05-06 18:08:38,600 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:08:38,601 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:08:38,728 INFO L85 PathProgramCache]: Analyzing trace with hash 184273587, now seen corresponding path program 212 times [2024-05-06 18:08:38,729 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:38,729 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:38,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:38,925 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 1 proven. 12 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:08:38,926 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:38,926 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:38,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:39,113 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 1 proven. 12 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:08:39,217 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 18:08:39,218 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 18:08:39,336 INFO L85 PathProgramCache]: Analyzing trace with hash -2122464024, now seen corresponding path program 213 times [2024-05-06 18:08:39,336 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:39,336 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:39,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:39,614 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 1 proven. 12 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:08:39,614 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:39,614 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:39,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:39,799 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 1 proven. 12 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:08:39,894 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:08:39,927 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Ended with exit code 0 [2024-05-06 18:08:40,105 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable670,SelfDestructingSolverStorable671,SelfDestructingSolverStorable669,SelfDestructingSolverStorable665,SelfDestructingSolverStorable666,SelfDestructingSolverStorable667,SelfDestructingSolverStorable668,SelfDestructingSolverStorable661,SelfDestructingSolverStorable662,SelfDestructingSolverStorable663,SelfDestructingSolverStorable664,SelfDestructingSolverStorable660,SelfDestructingSolverStorable658,SelfDestructingSolverStorable659,SelfDestructingSolverStorable654,SelfDestructingSolverStorable655,SelfDestructingSolverStorable656,SelfDestructingSolverStorable657,SelfDestructingSolverStorable650,SelfDestructingSolverStorable651,SelfDestructingSolverStorable652,SelfDestructingSolverStorable653,SelfDestructingSolverStorable690,SelfDestructingSolverStorable691,SelfDestructingSolverStorable692,SelfDestructingSolverStorable693,SelfDestructingSolverStorable607,SelfDestructingSolverStorable608,SelfDestructingSolverStorable609,SelfDestructingSolverStorable603,SelfDestructingSolverStorable604,SelfDestructingSolverStorable605,SelfDestructingSolverStorable606,SelfDestructingSolverStorable687,SelfDestructingSolverStorable600,SelfDestructingSolverStorable688,SelfDestructingSolverStorable601,SelfDestructingSolverStorable689,SelfDestructingSolverStorable602,SelfDestructingSolverStorable683,SelfDestructingSolverStorable684,SelfDestructingSolverStorable685,SelfDestructingSolverStorable686,3 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable680,SelfDestructingSolverStorable681,SelfDestructingSolverStorable682,SelfDestructingSolverStorable676,SelfDestructingSolverStorable677,SelfDestructingSolverStorable678,SelfDestructingSolverStorable679,SelfDestructingSolverStorable672,SelfDestructingSolverStorable673,SelfDestructingSolverStorable674,SelfDestructingSolverStorable675,SelfDestructingSolverStorable629,SelfDestructingSolverStorable625,SelfDestructingSolverStorable626,SelfDestructingSolverStorable627,SelfDestructingSolverStorable628,SelfDestructingSolverStorable621,SelfDestructingSolverStorable622,SelfDestructingSolverStorable623,SelfDestructingSolverStorable624,SelfDestructingSolverStorable620,SelfDestructingSolverStorable618,SelfDestructingSolverStorable619,SelfDestructingSolverStorable614,SelfDestructingSolverStorable615,SelfDestructingSolverStorable616,SelfDestructingSolverStorable617,SelfDestructingSolverStorable610,SelfDestructingSolverStorable698,SelfDestructingSolverStorable611,SelfDestructingSolverStorable699,SelfDestructingSolverStorable612,SelfDestructingSolverStorable613,SelfDestructingSolverStorable694,SelfDestructingSolverStorable695,SelfDestructingSolverStorable696,SelfDestructingSolverStorable697,SelfDestructingSolverStorable647,SelfDestructingSolverStorable648,SelfDestructingSolverStorable649,SelfDestructingSolverStorable643,SelfDestructingSolverStorable644,SelfDestructingSolverStorable645,SelfDestructingSolverStorable646,SelfDestructingSolverStorable640,SelfDestructingSolverStorable641,SelfDestructingSolverStorable642,SelfDestructingSolverStorable636,SelfDestructingSolverStorable637,SelfDestructingSolverStorable638,SelfDestructingSolverStorable639,SelfDestructingSolverStorable599,SelfDestructingSolverStorable632,SelfDestructingSolverStorable633,SelfDestructingSolverStorable634,SelfDestructingSolverStorable635,SelfDestructingSolverStorable596,SelfDestructingSolverStorable597,SelfDestructingSolverStorable630,SelfDestructingSolverStorable598,SelfDestructingSolverStorable631 [2024-05-06 18:08:40,106 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 2 more)] === [2024-05-06 18:08:40,106 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:08:40,106 INFO L85 PathProgramCache]: Analyzing trace with hash 498420411, now seen corresponding path program 2 times [2024-05-06 18:08:40,106 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:08:40,106 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1244232611] [2024-05-06 18:08:40,106 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:40,106 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:40,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:40,410 INFO L134 CoverageAnalysis]: Checked inductivity of 468 backedges. 109 proven. 7 refuted. 0 times theorem prover too weak. 352 trivial. 0 not checked. [2024-05-06 18:08:40,410 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:08:40,410 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1244232611] [2024-05-06 18:08:40,412 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1244232611] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:08:40,413 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1703768755] [2024-05-06 18:08:40,413 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-05-06 18:08:40,413 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:08:40,413 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:08:40,414 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:08:40,415 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2024-05-06 18:08:41,383 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-05-06 18:08:41,383 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-05-06 18:08:41,387 INFO L262 TraceCheckSpWp]: Trace formula consists of 858 conjuncts, 14 conjunts are in the unsatisfiable core [2024-05-06 18:08:41,392 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 18:08:41,743 INFO L134 CoverageAnalysis]: Checked inductivity of 468 backedges. 133 proven. 12 refuted. 0 times theorem prover too weak. 323 trivial. 0 not checked. [2024-05-06 18:08:41,743 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-06 18:08:42,256 INFO L134 CoverageAnalysis]: Checked inductivity of 468 backedges. 30 proven. 115 refuted. 0 times theorem prover too weak. 323 trivial. 0 not checked. [2024-05-06 18:08:42,257 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1703768755] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-06 18:08:42,257 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-06 18:08:42,257 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 13, 13] total 30 [2024-05-06 18:08:42,257 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [443344338] [2024-05-06 18:08:42,257 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-06 18:08:42,258 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 30 states [2024-05-06 18:08:42,258 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:08:42,259 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2024-05-06 18:08:42,259 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=128, Invalid=742, Unknown=0, NotChecked=0, Total=870 [2024-05-06 18:08:42,259 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:08:42,259 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:08:42,260 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 30 states, 30 states have (on average 14.533333333333333) internal successors, (436), 30 states have internal predecessors, (436), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:08:42,260 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:08:42,260 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:08:43,874 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:08:43,875 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2024-05-06 18:08:43,899 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2024-05-06 18:08:44,097 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable700 [2024-05-06 18:08:44,097 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 2 more)] === [2024-05-06 18:08:44,098 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:08:44,098 INFO L85 PathProgramCache]: Analyzing trace with hash -1683120427, now seen corresponding path program 3 times [2024-05-06 18:08:44,098 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:08:44,098 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1902866853] [2024-05-06 18:08:44,098 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:44,098 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:44,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:44,912 INFO L134 CoverageAnalysis]: Checked inductivity of 807 backedges. 394 proven. 88 refuted. 0 times theorem prover too weak. 325 trivial. 0 not checked. [2024-05-06 18:08:44,912 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:08:44,912 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1902866853] [2024-05-06 18:08:44,912 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1902866853] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:08:44,912 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1360601337] [2024-05-06 18:08:44,912 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-05-06 18:08:44,913 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:08:44,913 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:08:44,920 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:08:44,955 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2024-05-06 18:08:46,083 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2024-05-06 18:08:46,083 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-05-06 18:08:46,086 INFO L262 TraceCheckSpWp]: Trace formula consists of 619 conjuncts, 17 conjunts are in the unsatisfiable core [2024-05-06 18:08:46,090 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 18:08:46,706 INFO L134 CoverageAnalysis]: Checked inductivity of 807 backedges. 319 proven. 45 refuted. 0 times theorem prover too weak. 443 trivial. 0 not checked. [2024-05-06 18:08:46,707 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-06 18:08:47,304 INFO L134 CoverageAnalysis]: Checked inductivity of 807 backedges. 41 proven. 323 refuted. 0 times theorem prover too weak. 443 trivial. 0 not checked. [2024-05-06 18:08:47,304 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1360601337] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-06 18:08:47,305 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-06 18:08:47,305 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 16, 16] total 39 [2024-05-06 18:08:47,305 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [54544234] [2024-05-06 18:08:47,305 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-06 18:08:47,306 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 39 states [2024-05-06 18:08:47,306 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:08:47,306 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2024-05-06 18:08:47,307 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=245, Invalid=1237, Unknown=0, NotChecked=0, Total=1482 [2024-05-06 18:08:47,307 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:08:47,307 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:08:47,307 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 39 states, 39 states have (on average 10.384615384615385) internal successors, (405), 39 states have internal predecessors, (405), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:08:47,307 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:08:47,307 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 32 states. [2024-05-06 18:08:47,307 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:08:48,387 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:08:48,387 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2024-05-06 18:08:48,387 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2024-05-06 18:08:48,397 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2024-05-06 18:08:48,597 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable701,5 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:08:48,598 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 2 more)] === [2024-05-06 18:08:48,598 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:08:48,598 INFO L85 PathProgramCache]: Analyzing trace with hash -1132862929, now seen corresponding path program 4 times [2024-05-06 18:08:48,598 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:08:48,598 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [459278799] [2024-05-06 18:08:48,598 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:48,598 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:48,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:49,251 INFO L134 CoverageAnalysis]: Checked inductivity of 832 backedges. 394 proven. 123 refuted. 0 times theorem prover too weak. 315 trivial. 0 not checked. [2024-05-06 18:08:49,252 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:08:49,252 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [459278799] [2024-05-06 18:08:49,252 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [459278799] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:08:49,252 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1417681115] [2024-05-06 18:08:49,252 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-05-06 18:08:49,252 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:08:49,252 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:08:49,253 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:08:49,277 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2024-05-06 18:08:50,229 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-05-06 18:08:50,229 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-05-06 18:08:50,232 INFO L262 TraceCheckSpWp]: Trace formula consists of 590 conjuncts, 12 conjunts are in the unsatisfiable core [2024-05-06 18:08:50,235 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 18:08:50,567 INFO L134 CoverageAnalysis]: Checked inductivity of 832 backedges. 245 proven. 10 refuted. 0 times theorem prover too weak. 577 trivial. 0 not checked. [2024-05-06 18:08:50,567 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-06 18:08:50,901 INFO L134 CoverageAnalysis]: Checked inductivity of 832 backedges. 223 proven. 32 refuted. 0 times theorem prover too weak. 577 trivial. 0 not checked. [2024-05-06 18:08:50,901 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1417681115] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-06 18:08:50,901 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-06 18:08:50,901 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 12, 12] total 37 [2024-05-06 18:08:50,901 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [940224901] [2024-05-06 18:08:50,901 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-06 18:08:50,902 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 37 states [2024-05-06 18:08:50,902 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:08:50,904 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2024-05-06 18:08:50,904 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=148, Invalid=1184, Unknown=0, NotChecked=0, Total=1332 [2024-05-06 18:08:50,904 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:08:50,904 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:08:50,905 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 37 states, 37 states have (on average 13.108108108108109) internal successors, (485), 37 states have internal predecessors, (485), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:08:50,905 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:08:50,905 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 32 states. [2024-05-06 18:08:50,905 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 24 states. [2024-05-06 18:08:50,905 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:08:52,335 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:08:52,335 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2024-05-06 18:08:52,335 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2024-05-06 18:08:52,335 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2024-05-06 18:08:52,344 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Forceful destruction successful, exit code 0 [2024-05-06 18:08:52,544 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable702 [2024-05-06 18:08:52,544 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 2 more)] === [2024-05-06 18:08:52,544 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:08:52,544 INFO L85 PathProgramCache]: Analyzing trace with hash 349123131, now seen corresponding path program 5 times [2024-05-06 18:08:52,545 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:08:52,545 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1851751324] [2024-05-06 18:08:52,545 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:52,545 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:52,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:53,151 INFO L134 CoverageAnalysis]: Checked inductivity of 882 backedges. 375 proven. 161 refuted. 0 times theorem prover too weak. 346 trivial. 0 not checked. [2024-05-06 18:08:53,151 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:08:53,151 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1851751324] [2024-05-06 18:08:53,152 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1851751324] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:08:53,152 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1693035230] [2024-05-06 18:08:53,152 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-05-06 18:08:53,152 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:08:53,152 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:08:53,169 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:08:53,172 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2024-05-06 18:08:54,396 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2024-05-06 18:08:54,396 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-05-06 18:08:54,402 INFO L262 TraceCheckSpWp]: Trace formula consists of 1043 conjuncts, 21 conjunts are in the unsatisfiable core [2024-05-06 18:08:54,408 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 18:08:54,743 INFO L134 CoverageAnalysis]: Checked inductivity of 882 backedges. 442 proven. 98 refuted. 0 times theorem prover too weak. 342 trivial. 0 not checked. [2024-05-06 18:08:54,743 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-06 18:08:55,690 INFO L134 CoverageAnalysis]: Checked inductivity of 882 backedges. 142 proven. 600 refuted. 0 times theorem prover too weak. 140 trivial. 0 not checked. [2024-05-06 18:08:55,691 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1693035230] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-06 18:08:55,691 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-06 18:08:55,691 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 8, 22] total 41 [2024-05-06 18:08:55,691 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [928382803] [2024-05-06 18:08:55,691 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-06 18:08:55,694 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 41 states [2024-05-06 18:08:55,694 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:08:55,696 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2024-05-06 18:08:55,696 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=323, Invalid=1317, Unknown=0, NotChecked=0, Total=1640 [2024-05-06 18:08:55,697 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:08:55,697 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:08:55,697 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 41 states, 41 states have (on average 16.951219512195124) internal successors, (695), 41 states have internal predecessors, (695), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:08:55,697 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:08:55,697 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 32 states. [2024-05-06 18:08:55,697 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 24 states. [2024-05-06 18:08:55,697 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 44 states. [2024-05-06 18:08:55,697 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:08:56,204 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:08:56,204 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2024-05-06 18:08:56,204 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2024-05-06 18:08:56,204 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2024-05-06 18:08:56,204 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2024-05-06 18:08:56,214 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Forceful destruction successful, exit code 0 [2024-05-06 18:08:56,413 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable703,7 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:08:56,416 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 2 more)] === [2024-05-06 18:08:56,416 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:08:56,416 INFO L85 PathProgramCache]: Analyzing trace with hash -1894682751, now seen corresponding path program 6 times [2024-05-06 18:08:56,417 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:08:56,417 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1967899327] [2024-05-06 18:08:56,417 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:56,417 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:56,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:56,914 INFO L134 CoverageAnalysis]: Checked inductivity of 359 backedges. 58 proven. 186 refuted. 0 times theorem prover too weak. 115 trivial. 0 not checked. [2024-05-06 18:08:56,914 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:08:56,914 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1967899327] [2024-05-06 18:08:56,914 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1967899327] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:08:56,914 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [497496293] [2024-05-06 18:08:56,914 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-05-06 18:08:56,915 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:08:56,915 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:08:56,916 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:08:56,916 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2024-05-06 18:08:58,010 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 6 check-sat command(s) [2024-05-06 18:08:58,010 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-05-06 18:08:58,015 INFO L262 TraceCheckSpWp]: Trace formula consists of 802 conjuncts, 19 conjunts are in the unsatisfiable core [2024-05-06 18:08:58,019 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 18:08:58,540 INFO L134 CoverageAnalysis]: Checked inductivity of 359 backedges. 211 proven. 52 refuted. 0 times theorem prover too weak. 96 trivial. 0 not checked. [2024-05-06 18:08:58,540 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-06 18:08:59,241 INFO L134 CoverageAnalysis]: Checked inductivity of 359 backedges. 93 proven. 172 refuted. 0 times theorem prover too weak. 94 trivial. 0 not checked. [2024-05-06 18:08:59,241 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [497496293] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-06 18:08:59,241 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-06 18:08:59,241 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 19] total 48 [2024-05-06 18:08:59,241 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1197293069] [2024-05-06 18:08:59,241 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-06 18:08:59,242 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 48 states [2024-05-06 18:08:59,242 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:08:59,243 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2024-05-06 18:08:59,243 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=373, Invalid=1883, Unknown=0, NotChecked=0, Total=2256 [2024-05-06 18:08:59,243 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:08:59,243 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:08:59,244 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 48 states, 48 states have (on average 11.1875) internal successors, (537), 48 states have internal predecessors, (537), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:08:59,244 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:08:59,244 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 32 states. [2024-05-06 18:08:59,244 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 24 states. [2024-05-06 18:08:59,244 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 44 states. [2024-05-06 18:08:59,244 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 23 states. [2024-05-06 18:08:59,244 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:08:59,987 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:08:59,988 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2024-05-06 18:08:59,988 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2024-05-06 18:08:59,988 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2024-05-06 18:08:59,988 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2024-05-06 18:08:59,988 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2024-05-06 18:08:59,998 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Forceful destruction successful, exit code 0 [2024-05-06 18:09:00,197 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable704 [2024-05-06 18:09:00,198 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 2 more)] === [2024-05-06 18:09:00,198 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:09:00,198 INFO L85 PathProgramCache]: Analyzing trace with hash 2073321373, now seen corresponding path program 7 times [2024-05-06 18:09:00,198 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:09:00,198 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1766036320] [2024-05-06 18:09:00,198 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:00,198 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:00,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:00,895 INFO L134 CoverageAnalysis]: Checked inductivity of 433 backedges. 162 proven. 185 refuted. 0 times theorem prover too weak. 86 trivial. 0 not checked. [2024-05-06 18:09:00,896 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:09:00,896 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1766036320] [2024-05-06 18:09:00,896 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1766036320] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:09:00,896 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1745748018] [2024-05-06 18:09:00,896 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-05-06 18:09:00,896 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:09:00,896 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:09:00,897 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:09:00,899 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2024-05-06 18:09:01,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:01,876 INFO L262 TraceCheckSpWp]: Trace formula consists of 830 conjuncts, 24 conjunts are in the unsatisfiable core [2024-05-06 18:09:01,880 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 18:09:02,762 INFO L134 CoverageAnalysis]: Checked inductivity of 433 backedges. 221 proven. 126 refuted. 0 times theorem prover too weak. 86 trivial. 0 not checked. [2024-05-06 18:09:02,762 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-06 18:09:03,580 INFO L134 CoverageAnalysis]: Checked inductivity of 433 backedges. 144 proven. 203 refuted. 0 times theorem prover too weak. 86 trivial. 0 not checked. [2024-05-06 18:09:03,581 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1745748018] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-06 18:09:03,581 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-06 18:09:03,581 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 24, 24] total 69 [2024-05-06 18:09:03,581 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2072277741] [2024-05-06 18:09:03,581 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-06 18:09:03,582 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 69 states [2024-05-06 18:09:03,582 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:09:03,583 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2024-05-06 18:09:03,584 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=537, Invalid=4155, Unknown=0, NotChecked=0, Total=4692 [2024-05-06 18:09:03,584 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:09:03,584 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:09:03,584 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 69 states, 69 states have (on average 9.927536231884059) internal successors, (685), 69 states have internal predecessors, (685), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:09:03,584 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:09:03,584 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 32 states. [2024-05-06 18:09:03,584 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 24 states. [2024-05-06 18:09:03,584 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 44 states. [2024-05-06 18:09:03,585 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 23 states. [2024-05-06 18:09:03,585 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 28 states. [2024-05-06 18:09:03,585 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:09:05,366 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:09:05,366 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2024-05-06 18:09:05,366 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2024-05-06 18:09:05,367 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2024-05-06 18:09:05,367 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2024-05-06 18:09:05,367 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2024-05-06 18:09:05,367 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2024-05-06 18:09:05,395 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Forceful destruction successful, exit code 0 [2024-05-06 18:09:05,576 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable705,9 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:09:05,576 INFO L420 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 2 more)] === [2024-05-06 18:09:05,576 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:09:05,576 INFO L85 PathProgramCache]: Analyzing trace with hash 3306155, now seen corresponding path program 8 times [2024-05-06 18:09:05,577 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:09:05,577 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [315037418] [2024-05-06 18:09:05,577 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:05,577 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:05,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:06,394 INFO L134 CoverageAnalysis]: Checked inductivity of 482 backedges. 68 proven. 104 refuted. 0 times theorem prover too weak. 310 trivial. 0 not checked. [2024-05-06 18:09:06,394 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:09:06,394 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [315037418] [2024-05-06 18:09:06,394 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [315037418] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:09:06,394 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [118103673] [2024-05-06 18:09:06,395 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-05-06 18:09:06,395 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:09:06,395 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:09:06,396 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:09:06,396 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2024-05-06 18:09:07,391 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-05-06 18:09:07,391 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-05-06 18:09:07,396 INFO L262 TraceCheckSpWp]: Trace formula consists of 844 conjuncts, 21 conjunts are in the unsatisfiable core [2024-05-06 18:09:07,400 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 18:09:07,845 INFO L134 CoverageAnalysis]: Checked inductivity of 482 backedges. 109 proven. 33 refuted. 0 times theorem prover too weak. 340 trivial. 0 not checked. [2024-05-06 18:09:07,846 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-06 18:09:08,440 INFO L134 CoverageAnalysis]: Checked inductivity of 482 backedges. 99 proven. 45 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2024-05-06 18:09:08,440 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [118103673] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-06 18:09:08,440 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-06 18:09:08,440 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 8, 9] total 23 [2024-05-06 18:09:08,440 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [425104257] [2024-05-06 18:09:08,440 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-06 18:09:08,441 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 23 states [2024-05-06 18:09:08,441 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:09:08,442 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2024-05-06 18:09:08,442 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=75, Invalid=431, Unknown=0, NotChecked=0, Total=506 [2024-05-06 18:09:08,442 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:09:08,442 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:09:08,442 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 23 states, 23 states have (on average 20.17391304347826) internal successors, (464), 23 states have internal predecessors, (464), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:09:08,442 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:09:08,442 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 32 states. [2024-05-06 18:09:08,442 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 24 states. [2024-05-06 18:09:08,442 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 44 states. [2024-05-06 18:09:08,442 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 23 states. [2024-05-06 18:09:08,442 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 28 states. [2024-05-06 18:09:08,442 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 34 states. [2024-05-06 18:09:08,442 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:09:12,777 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:09:12,777 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2024-05-06 18:09:12,777 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2024-05-06 18:09:12,777 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2024-05-06 18:09:12,777 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2024-05-06 18:09:12,777 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2024-05-06 18:09:12,777 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2024-05-06 18:09:12,777 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 73 states. [2024-05-06 18:09:12,789 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Forceful destruction successful, exit code 0 [2024-05-06 18:09:12,987 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable706,10 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:09:12,987 INFO L420 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 2 more)] === [2024-05-06 18:09:12,988 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:09:12,988 INFO L85 PathProgramCache]: Analyzing trace with hash 1429828019, now seen corresponding path program 9 times [2024-05-06 18:09:12,988 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:09:12,988 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [663722124] [2024-05-06 18:09:12,988 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:12,988 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:13,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:13,829 INFO L134 CoverageAnalysis]: Checked inductivity of 1220 backedges. 422 proven. 430 refuted. 0 times theorem prover too weak. 368 trivial. 0 not checked. [2024-05-06 18:09:13,829 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:09:13,829 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [663722124] [2024-05-06 18:09:13,829 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [663722124] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:09:13,829 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [726526624] [2024-05-06 18:09:13,829 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-05-06 18:09:13,829 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:09:13,829 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:09:13,830 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:09:13,831 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2024-05-06 18:09:14,974 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2024-05-06 18:09:14,974 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-05-06 18:09:14,978 INFO L262 TraceCheckSpWp]: Trace formula consists of 695 conjuncts, 14 conjunts are in the unsatisfiable core [2024-05-06 18:09:14,982 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 18:09:15,299 INFO L134 CoverageAnalysis]: Checked inductivity of 1220 backedges. 269 proven. 67 refuted. 0 times theorem prover too weak. 884 trivial. 0 not checked. [2024-05-06 18:09:15,299 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-06 18:09:15,441 INFO L134 CoverageAnalysis]: Checked inductivity of 1220 backedges. 126 proven. 1 refuted. 0 times theorem prover too weak. 1093 trivial. 0 not checked. [2024-05-06 18:09:15,442 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [726526624] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-06 18:09:15,442 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-06 18:09:15,442 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 8, 6] total 31 [2024-05-06 18:09:15,442 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1855761275] [2024-05-06 18:09:15,442 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-06 18:09:15,442 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 31 states [2024-05-06 18:09:15,443 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:09:15,443 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2024-05-06 18:09:15,443 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=100, Invalid=830, Unknown=0, NotChecked=0, Total=930 [2024-05-06 18:09:15,443 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:09:15,444 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:09:15,444 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 31 states, 31 states have (on average 15.225806451612904) internal successors, (472), 31 states have internal predecessors, (472), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:09:15,444 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:09:15,444 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 32 states. [2024-05-06 18:09:15,444 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 24 states. [2024-05-06 18:09:15,444 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 44 states. [2024-05-06 18:09:15,444 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 26 states. [2024-05-06 18:09:15,444 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 28 states. [2024-05-06 18:09:15,444 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 34 states. [2024-05-06 18:09:15,444 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 73 states. [2024-05-06 18:09:15,444 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:09:19,663 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:09:19,664 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2024-05-06 18:09:19,664 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2024-05-06 18:09:19,664 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2024-05-06 18:09:19,664 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2024-05-06 18:09:19,664 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2024-05-06 18:09:19,664 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2024-05-06 18:09:19,664 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 73 states. [2024-05-06 18:09:19,664 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2024-05-06 18:09:19,690 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Forceful destruction successful, exit code 0 [2024-05-06 18:09:19,877 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable707 [2024-05-06 18:09:19,877 INFO L420 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 2 more)] === [2024-05-06 18:09:19,877 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:09:19,877 INFO L85 PathProgramCache]: Analyzing trace with hash -530507404, now seen corresponding path program 10 times [2024-05-06 18:09:19,877 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:09:19,877 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [117244189] [2024-05-06 18:09:19,877 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:19,878 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:19,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:21,136 INFO L134 CoverageAnalysis]: Checked inductivity of 1208 backedges. 155 proven. 691 refuted. 0 times theorem prover too weak. 362 trivial. 0 not checked. [2024-05-06 18:09:21,137 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:09:21,137 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [117244189] [2024-05-06 18:09:21,137 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [117244189] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:09:21,137 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [866292471] [2024-05-06 18:09:21,137 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-05-06 18:09:21,137 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:09:21,137 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:09:21,138 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:09:21,142 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2024-05-06 18:09:22,110 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-05-06 18:09:22,110 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-05-06 18:09:22,113 INFO L262 TraceCheckSpWp]: Trace formula consists of 716 conjuncts, 24 conjunts are in the unsatisfiable core [2024-05-06 18:09:22,118 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 18:09:23,066 INFO L134 CoverageAnalysis]: Checked inductivity of 1208 backedges. 636 proven. 126 refuted. 0 times theorem prover too weak. 446 trivial. 0 not checked. [2024-05-06 18:09:23,066 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-06 18:09:24,027 INFO L134 CoverageAnalysis]: Checked inductivity of 1208 backedges. 569 proven. 193 refuted. 0 times theorem prover too weak. 446 trivial. 0 not checked. [2024-05-06 18:09:24,027 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [866292471] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-06 18:09:24,027 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-06 18:09:24,027 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 24, 24] total 70 [2024-05-06 18:09:24,028 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1158071550] [2024-05-06 18:09:24,028 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-06 18:09:24,028 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 70 states [2024-05-06 18:09:24,028 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:09:24,029 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2024-05-06 18:09:24,030 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=505, Invalid=4325, Unknown=0, NotChecked=0, Total=4830 [2024-05-06 18:09:24,031 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:09:24,031 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:09:24,031 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 70 states, 70 states have (on average 10.142857142857142) internal successors, (710), 70 states have internal predecessors, (710), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:09:24,031 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:09:24,031 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 32 states. [2024-05-06 18:09:24,031 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 24 states. [2024-05-06 18:09:24,031 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 44 states. [2024-05-06 18:09:24,031 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 26 states. [2024-05-06 18:09:24,031 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 28 states. [2024-05-06 18:09:24,031 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 34 states. [2024-05-06 18:09:24,031 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 73 states. [2024-05-06 18:09:24,031 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 47 states. [2024-05-06 18:09:24,031 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:09:28,388 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:09:28,388 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2024-05-06 18:09:28,388 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2024-05-06 18:09:28,388 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2024-05-06 18:09:28,388 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2024-05-06 18:09:28,388 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2024-05-06 18:09:28,389 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2024-05-06 18:09:28,389 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 73 states. [2024-05-06 18:09:28,389 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2024-05-06 18:09:28,389 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 75 states. [2024-05-06 18:09:28,400 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Forceful destruction successful, exit code 0 [2024-05-06 18:09:28,598 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable708,12 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:09:28,598 INFO L420 AbstractCegarLoop]: === Iteration 11 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 2 more)] === [2024-05-06 18:09:28,599 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:09:28,599 INFO L85 PathProgramCache]: Analyzing trace with hash 1029870568, now seen corresponding path program 11 times [2024-05-06 18:09:28,599 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:09:28,599 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [168442012] [2024-05-06 18:09:28,599 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:28,599 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:28,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:29,708 INFO L134 CoverageAnalysis]: Checked inductivity of 1314 backedges. 446 proven. 536 refuted. 0 times theorem prover too weak. 332 trivial. 0 not checked. [2024-05-06 18:09:29,709 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:09:29,709 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [168442012] [2024-05-06 18:09:29,709 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [168442012] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:09:29,709 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [693756462] [2024-05-06 18:09:29,709 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-05-06 18:09:29,709 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:09:29,709 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:09:29,724 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:09:29,733 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2024-05-06 18:09:31,041 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2024-05-06 18:09:31,042 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-05-06 18:09:31,047 INFO L262 TraceCheckSpWp]: Trace formula consists of 755 conjuncts, 21 conjunts are in the unsatisfiable core [2024-05-06 18:09:31,057 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 18:09:31,417 INFO L134 CoverageAnalysis]: Checked inductivity of 1314 backedges. 303 proven. 303 refuted. 0 times theorem prover too weak. 708 trivial. 0 not checked. [2024-05-06 18:09:31,417 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-06 18:09:31,510 INFO L134 CoverageAnalysis]: Checked inductivity of 1314 backedges. 109 proven. 1 refuted. 0 times theorem prover too weak. 1204 trivial. 0 not checked. [2024-05-06 18:09:31,510 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [693756462] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-06 18:09:31,510 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-06 18:09:31,510 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 12, 5] total 40 [2024-05-06 18:09:31,510 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [159045032] [2024-05-06 18:09:31,510 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-06 18:09:31,511 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 40 states [2024-05-06 18:09:31,511 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:09:31,512 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2024-05-06 18:09:31,512 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=163, Invalid=1397, Unknown=0, NotChecked=0, Total=1560 [2024-05-06 18:09:31,512 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:09:31,512 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:09:31,512 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 40 states, 40 states have (on average 13.75) internal successors, (550), 40 states have internal predecessors, (550), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:09:31,512 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:09:31,513 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 32 states. [2024-05-06 18:09:31,513 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 24 states. [2024-05-06 18:09:31,513 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 44 states. [2024-05-06 18:09:31,513 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 26 states. [2024-05-06 18:09:31,513 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 28 states. [2024-05-06 18:09:31,513 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 34 states. [2024-05-06 18:09:31,513 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 73 states. [2024-05-06 18:09:31,513 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 47 states. [2024-05-06 18:09:31,513 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 75 states. [2024-05-06 18:09:31,513 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:10:15,588 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:10:15,589 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2024-05-06 18:10:15,589 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2024-05-06 18:10:15,589 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2024-05-06 18:10:15,589 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2024-05-06 18:10:15,589 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2024-05-06 18:10:15,589 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2024-05-06 18:10:15,589 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 381 states. [2024-05-06 18:10:15,589 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2024-05-06 18:10:15,589 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 75 states. [2024-05-06 18:10:15,589 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2024-05-06 18:10:15,600 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Ended with exit code 0 [2024-05-06 18:10:15,799 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable709,13 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:10:15,800 INFO L420 AbstractCegarLoop]: === Iteration 12 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 2 more)] === [2024-05-06 18:10:15,800 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:10:15,800 INFO L85 PathProgramCache]: Analyzing trace with hash -995076853, now seen corresponding path program 12 times [2024-05-06 18:10:15,800 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:10:15,800 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1902621849] [2024-05-06 18:10:15,801 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:15,801 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:16,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:20,889 INFO L134 CoverageAnalysis]: Checked inductivity of 28812 backedges. 6523 proven. 489 refuted. 0 times theorem prover too weak. 21800 trivial. 0 not checked. [2024-05-06 18:10:20,889 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:10:20,889 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1902621849] [2024-05-06 18:10:20,889 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1902621849] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:10:20,889 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1183713897] [2024-05-06 18:10:20,890 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-05-06 18:10:20,890 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:10:20,890 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:10:20,891 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:10:20,894 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2024-05-06 18:10:22,294 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2024-05-06 18:10:22,294 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-05-06 18:10:22,300 INFO L262 TraceCheckSpWp]: Trace formula consists of 755 conjuncts, 16 conjunts are in the unsatisfiable core [2024-05-06 18:10:22,322 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 18:10:22,642 INFO L134 CoverageAnalysis]: Checked inductivity of 28812 backedges. 1059 proven. 94 refuted. 0 times theorem prover too weak. 27659 trivial. 0 not checked. [2024-05-06 18:10:22,643 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-06 18:10:22,855 INFO L134 CoverageAnalysis]: Checked inductivity of 28812 backedges. 723 proven. 4 refuted. 0 times theorem prover too weak. 28085 trivial. 0 not checked. [2024-05-06 18:10:22,855 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1183713897] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-06 18:10:22,855 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-06 18:10:22,856 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 9, 8] total 42 [2024-05-06 18:10:22,856 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1953205962] [2024-05-06 18:10:22,856 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-06 18:10:22,857 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 42 states [2024-05-06 18:10:22,857 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:10:22,858 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2024-05-06 18:10:22,858 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=186, Invalid=1536, Unknown=0, NotChecked=0, Total=1722 [2024-05-06 18:10:22,858 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:10:22,858 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:10:22,859 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 42 states, 42 states have (on average 13.095238095238095) internal successors, (550), 42 states have internal predecessors, (550), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:10:22,859 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:10:22,859 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 32 states. [2024-05-06 18:10:22,859 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 24 states. [2024-05-06 18:10:22,859 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 44 states. [2024-05-06 18:10:22,859 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 26 states. [2024-05-06 18:10:22,859 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 28 states. [2024-05-06 18:10:22,859 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 34 states. [2024-05-06 18:10:22,859 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 381 states. [2024-05-06 18:10:22,859 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 49 states. [2024-05-06 18:10:22,859 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 75 states. [2024-05-06 18:10:22,859 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 96 states. [2024-05-06 18:10:22,859 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states.