/root/.sdkman/candidates/java/current/bin/java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data -s ../benchexec/../../../trunk/examples/settings/gemcutter/NewStatesSleep.epf --traceabstraction.dfs.order.used.in.por LOOP_LOCKSTEP --traceabstraction.additional.conditional.commutativity.checking DFS --traceabstraction.criterion.for.conditional.commutativity.checking DEFAULT --traceabstraction.use.limited.checks.recommended.for.dfs true --traceabstraction.limit.for.limited.checks 50 -tc ../benchexec/../../../trunk/examples/toolchains/AutomizerCInline.xml -i ../../../trunk/examples/svcomp/weaver/popl20-more-buffer-series.wvr.c -------------------------------------------------------------------------------- This is Ultimate 0.2.4-wip.dk.conditional-comm-17da818-m [2024-05-06 18:05:44,766 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-05-06 18:05:44,832 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/../benchexec/../../../trunk/examples/settings/gemcutter/NewStatesSleep.epf [2024-05-06 18:05:44,837 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-05-06 18:05:44,837 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-05-06 18:05:44,859 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-05-06 18:05:44,859 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-05-06 18:05:44,860 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-05-06 18:05:44,860 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2024-05-06 18:05:44,863 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2024-05-06 18:05:44,864 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-05-06 18:05:44,864 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-05-06 18:05:44,864 INFO L153 SettingsManager]: * Use SBE=true [2024-05-06 18:05:44,865 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-05-06 18:05:44,865 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2024-05-06 18:05:44,865 INFO L153 SettingsManager]: * sizeof long=4 [2024-05-06 18:05:44,866 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-05-06 18:05:44,866 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-05-06 18:05:44,866 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-05-06 18:05:44,866 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2024-05-06 18:05:44,866 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2024-05-06 18:05:44,866 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2024-05-06 18:05:44,867 INFO L153 SettingsManager]: * sizeof long double=12 [2024-05-06 18:05:44,868 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-05-06 18:05:44,868 INFO L153 SettingsManager]: * Use constant arrays=true [2024-05-06 18:05:44,868 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-05-06 18:05:44,868 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-05-06 18:05:44,868 INFO L153 SettingsManager]: * To the following directory=./dump/ [2024-05-06 18:05:44,868 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-05-06 18:05:44,868 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2024-05-06 18:05:44,869 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-05-06 18:05:44,870 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2024-05-06 18:05:44,870 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2024-05-06 18:05:44,870 INFO L153 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2024-05-06 18:05:44,870 INFO L153 SettingsManager]: * Partial Order Reduction in concurrent analysis=SLEEP_NEW_STATES [2024-05-06 18:05:44,870 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2024-05-06 18:05:44,870 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-05-06 18:05:44,870 INFO L153 SettingsManager]: * Automaton type used in concurrency analysis=PARTIAL_ORDER_FA [2024-05-06 18:05:44,870 INFO L153 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2024-05-06 18:05:44,870 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: DFS Order used in POR -> LOOP_LOCKSTEP Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Additional conditional commutativity checking -> DFS Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Criterion for conditional commutativity checking -> DEFAULT Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: use limited checks (recommended for DFS) -> true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Limit for limited checks -> 50 [2024-05-06 18:05:45,039 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-05-06 18:05:45,054 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-05-06 18:05:45,056 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-05-06 18:05:45,056 INFO L270 PluginConnector]: Initializing CDTParser... [2024-05-06 18:05:45,057 INFO L274 PluginConnector]: CDTParser initialized [2024-05-06 18:05:45,057 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/../../../trunk/examples/svcomp/weaver/popl20-more-buffer-series.wvr.c [2024-05-06 18:05:46,139 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-05-06 18:05:46,286 INFO L384 CDTParser]: Found 1 translation units. [2024-05-06 18:05:46,287 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/weaver/popl20-more-buffer-series.wvr.c [2024-05-06 18:05:46,295 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/data/734dc27e7/1670e6585ea545d5a4e8951b19353d90/FLAG591286742 [2024-05-06 18:05:46,313 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/data/734dc27e7/1670e6585ea545d5a4e8951b19353d90 [2024-05-06 18:05:46,316 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-05-06 18:05:46,317 INFO L133 ToolchainWalker]: Walking toolchain with 5 elements. [2024-05-06 18:05:46,320 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-05-06 18:05:46,320 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-05-06 18:05:46,324 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-05-06 18:05:46,325 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.05 06:05:46" (1/1) ... [2024-05-06 18:05:46,326 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@425db0b9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:05:46, skipping insertion in model container [2024-05-06 18:05:46,326 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.05 06:05:46" (1/1) ... [2024-05-06 18:05:46,349 INFO L177 MainTranslator]: Built tables and reachable declarations [2024-05-06 18:05:46,486 WARN L240 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/weaver/popl20-more-buffer-series.wvr.c[4351,4364] [2024-05-06 18:05:46,494 INFO L209 PostProcessor]: Analyzing one entry point: main [2024-05-06 18:05:46,502 INFO L202 MainTranslator]: Completed pre-run [2024-05-06 18:05:46,530 WARN L240 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/weaver/popl20-more-buffer-series.wvr.c[4351,4364] [2024-05-06 18:05:46,533 INFO L209 PostProcessor]: Analyzing one entry point: main [2024-05-06 18:05:46,539 WARN L675 CHandler]: The function __VERIFIER_atomic_begin is called, but not defined or handled by StandardFunctionHandler. [2024-05-06 18:05:46,539 WARN L675 CHandler]: The function __VERIFIER_atomic_end is called, but not defined or handled by StandardFunctionHandler. [2024-05-06 18:05:46,545 INFO L206 MainTranslator]: Completed translation [2024-05-06 18:05:46,545 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:05:46 WrapperNode [2024-05-06 18:05:46,545 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-05-06 18:05:46,546 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-05-06 18:05:46,546 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-05-06 18:05:46,546 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-05-06 18:05:46,551 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:05:46" (1/1) ... [2024-05-06 18:05:46,558 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:05:46" (1/1) ... [2024-05-06 18:05:46,585 INFO L138 Inliner]: procedures = 27, calls = 87, calls flagged for inlining = 22, calls inlined = 28, statements flattened = 360 [2024-05-06 18:05:46,586 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-05-06 18:05:46,586 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-05-06 18:05:46,586 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-05-06 18:05:46,586 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-05-06 18:05:46,593 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:05:46" (1/1) ... [2024-05-06 18:05:46,593 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:05:46" (1/1) ... [2024-05-06 18:05:46,597 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:05:46" (1/1) ... [2024-05-06 18:05:46,597 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:05:46" (1/1) ... [2024-05-06 18:05:46,605 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:05:46" (1/1) ... [2024-05-06 18:05:46,609 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:05:46" (1/1) ... [2024-05-06 18:05:46,610 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:05:46" (1/1) ... [2024-05-06 18:05:46,612 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:05:46" (1/1) ... [2024-05-06 18:05:46,616 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-05-06 18:05:46,629 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-05-06 18:05:46,629 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-05-06 18:05:46,629 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-05-06 18:05:46,630 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:05:46" (1/1) ... [2024-05-06 18:05:46,634 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2024-05-06 18:05:46,646 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:05:46,681 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2024-05-06 18:05:46,701 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2024-05-06 18:05:46,735 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-05-06 18:05:46,735 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2024-05-06 18:05:46,735 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2024-05-06 18:05:46,735 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2024-05-06 18:05:46,735 INFO L130 BoogieDeclarations]: Found specification of procedure thread1 [2024-05-06 18:05:46,736 INFO L138 BoogieDeclarations]: Found implementation of procedure thread1 [2024-05-06 18:05:46,736 INFO L130 BoogieDeclarations]: Found specification of procedure thread2 [2024-05-06 18:05:46,736 INFO L138 BoogieDeclarations]: Found implementation of procedure thread2 [2024-05-06 18:05:46,736 INFO L130 BoogieDeclarations]: Found specification of procedure thread3 [2024-05-06 18:05:46,736 INFO L138 BoogieDeclarations]: Found implementation of procedure thread3 [2024-05-06 18:05:46,736 INFO L130 BoogieDeclarations]: Found specification of procedure thread4 [2024-05-06 18:05:46,736 INFO L138 BoogieDeclarations]: Found implementation of procedure thread4 [2024-05-06 18:05:46,736 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2024-05-06 18:05:46,736 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2024-05-06 18:05:46,736 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2024-05-06 18:05:46,736 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2024-05-06 18:05:46,737 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-05-06 18:05:46,737 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-05-06 18:05:46,737 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2024-05-06 18:05:46,738 WARN L213 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to OneNontrivialStatement [2024-05-06 18:05:46,836 INFO L241 CfgBuilder]: Building ICFG [2024-05-06 18:05:46,838 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2024-05-06 18:05:47,223 INFO L282 CfgBuilder]: Performing block encoding [2024-05-06 18:05:47,373 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-05-06 18:05:47,374 INFO L309 CfgBuilder]: Removed 7 assume(true) statements. [2024-05-06 18:05:47,375 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.05 06:05:47 BoogieIcfgContainer [2024-05-06 18:05:47,375 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-05-06 18:05:47,377 INFO L112 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2024-05-06 18:05:47,377 INFO L270 PluginConnector]: Initializing TraceAbstraction... [2024-05-06 18:05:47,380 INFO L274 PluginConnector]: TraceAbstraction initialized [2024-05-06 18:05:47,380 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 06.05 06:05:46" (1/3) ... [2024-05-06 18:05:47,381 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6391f515 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.05 06:05:47, skipping insertion in model container [2024-05-06 18:05:47,382 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:05:46" (2/3) ... [2024-05-06 18:05:47,382 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6391f515 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.05 06:05:47, skipping insertion in model container [2024-05-06 18:05:47,382 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.05 06:05:47" (3/3) ... [2024-05-06 18:05:47,383 INFO L112 eAbstractionObserver]: Analyzing ICFG popl20-more-buffer-series.wvr.c [2024-05-06 18:05:47,390 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2024-05-06 18:05:47,397 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2024-05-06 18:05:47,397 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2024-05-06 18:05:47,397 INFO L514 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2024-05-06 18:05:47,476 INFO L144 ThreadInstanceAdder]: Constructed 4 joinOtherThreadTransitions. [2024-05-06 18:05:47,522 INFO L100 denceProviderFactory]: Independence Relation #1: [IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=true, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2024-05-06 18:05:47,522 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 [2024-05-06 18:05:47,523 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:05:47,525 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 (exit command is (exit), workingDir is null) [2024-05-06 18:05:47,576 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 (2)] Waiting until timeout for monitored process [2024-05-06 18:05:47,585 INFO L188 artialOrderCegarLoop]: Running PartialOrderCegarLoop with 1 independence relations. [2024-05-06 18:05:47,594 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:05:47,595 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2024-05-06 18:05:47,601 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=PARTIAL_ORDER_FA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopHeads, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@1da96dc7, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms], mConComChecker=DFS, mConComCheckerCriterion=DEFAULT, mConComCheckerLimitedChecksCriterion=true, mConComCheckerCriterionLimit=50, mConComCheckerRandomProb=100, mConComCheckerRandomSeed=123, mConComCheckerConditionCriterion=false [2024-05-06 18:05:47,601 INFO L358 AbstractCegarLoop]: Starting to check reachability of 5 error locations. [2024-05-06 18:05:48,184 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:05:48,185 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:05:48,275 INFO L85 PathProgramCache]: Analyzing trace with hash 1885608612, now seen corresponding path program 1 times [2024-05-06 18:05:48,279 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:48,279 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:48,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:48,660 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:05:48,661 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:48,661 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:48,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:48,794 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:05:48,815 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-05-06 18:05:48,816 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-05-06 18:05:49,053 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:05:49,053 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:05:49,119 INFO L85 PathProgramCache]: Analyzing trace with hash -1787987805, now seen corresponding path program 1 times [2024-05-06 18:05:49,119 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:49,119 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:49,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:49,502 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-06 18:05:49,503 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:49,503 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:49,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:49,747 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-06 18:05:49,748 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-05-06 18:05:49,748 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2024-05-06 18:05:50,076 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:05:50,078 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:05:50,144 INFO L85 PathProgramCache]: Analyzing trace with hash 1156997360, now seen corresponding path program 1 times [2024-05-06 18:05:50,144 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:50,144 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:50,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:50,351 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-06 18:05:50,351 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:50,351 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:50,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:50,532 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-06 18:05:50,534 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-05-06 18:05:50,534 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=143, Unknown=0, NotChecked=0, Total=182 [2024-05-06 18:05:50,790 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:05:50,790 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:05:50,853 INFO L85 PathProgramCache]: Analyzing trace with hash 1909244576, now seen corresponding path program 1 times [2024-05-06 18:05:50,853 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:50,854 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:50,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:51,122 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:51,123 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:51,123 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:51,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:51,312 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:51,387 INFO L85 PathProgramCache]: Analyzing trace with hash -942959273, now seen corresponding path program 2 times [2024-05-06 18:05:51,387 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:51,387 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:51,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:51,593 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:51,593 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:51,593 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:51,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:51,829 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:51,972 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:05:51,973 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:05:52,042 INFO L85 PathProgramCache]: Analyzing trace with hash 2142091837, now seen corresponding path program 1 times [2024-05-06 18:05:52,042 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:52,042 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:52,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:52,259 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:52,259 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:52,260 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:52,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:52,502 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:52,581 INFO L85 PathProgramCache]: Analyzing trace with hash 1980338513, now seen corresponding path program 2 times [2024-05-06 18:05:52,582 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:52,582 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:52,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:52,778 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:52,778 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:52,779 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:52,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:52,993 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:05:53,119 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:05:53,120 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:05:53,180 INFO L85 PathProgramCache]: Analyzing trace with hash -1418320652, now seen corresponding path program 3 times [2024-05-06 18:05:53,180 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:53,181 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:53,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:53,459 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:05:53,459 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:53,459 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:53,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:53,702 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:05:53,780 INFO L85 PathProgramCache]: Analyzing trace with hash -1018266246, now seen corresponding path program 4 times [2024-05-06 18:05:53,780 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:53,780 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:53,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:54,064 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:05:54,065 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:54,065 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:54,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:54,320 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:05:54,572 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:05:54,572 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:05:55,188 INFO L85 PathProgramCache]: Analyzing trace with hash 1493763107, now seen corresponding path program 5 times [2024-05-06 18:05:55,188 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:55,188 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:55,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:55,443 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:05:55,444 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:55,444 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:55,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:55,706 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:05:55,949 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:05:55,949 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:05:56,437 INFO L85 PathProgramCache]: Analyzing trace with hash 1448669860, now seen corresponding path program 6 times [2024-05-06 18:05:56,437 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:56,437 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:56,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:56,702 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:05:56,702 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:56,702 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:56,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:56,913 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:05:56,976 INFO L85 PathProgramCache]: Analyzing trace with hash -1476546248, now seen corresponding path program 7 times [2024-05-06 18:05:56,976 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:56,976 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:57,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:57,286 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:05:57,286 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:57,286 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:57,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:57,599 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:05:57,736 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:05:57,737 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:05:57,792 INFO L85 PathProgramCache]: Analyzing trace with hash 1199295900, now seen corresponding path program 8 times [2024-05-06 18:05:57,793 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:57,793 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:57,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:58,034 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:05:58,034 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:58,037 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:58,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:58,288 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:05:58,421 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:05:58,422 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:05:58,485 INFO L85 PathProgramCache]: Analyzing trace with hash -1201616421, now seen corresponding path program 9 times [2024-05-06 18:05:58,485 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:58,485 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:58,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:58,692 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:05:58,692 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:58,692 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:58,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:58,895 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:05:58,956 INFO L85 PathProgramCache]: Analyzing trace with hash 1404597619, now seen corresponding path program 10 times [2024-05-06 18:05:58,956 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:58,956 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:58,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:59,235 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:05:59,236 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:05:59,236 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:05:59,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:05:59,443 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:05:59,687 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:05:59,688 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:06:00,263 INFO L85 PathProgramCache]: Analyzing trace with hash 1975785950, now seen corresponding path program 11 times [2024-05-06 18:06:00,263 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:00,264 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:00,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:00,582 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:00,582 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:00,582 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:00,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:00,808 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:00,923 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:06:00,923 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:06:00,973 INFO L85 PathProgramCache]: Analyzing trace with hash 354785865, now seen corresponding path program 12 times [2024-05-06 18:06:00,973 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:00,973 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:01,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:01,176 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:01,176 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:01,177 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:01,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:01,423 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:01,485 INFO L85 PathProgramCache]: Analyzing trace with hash -1886539067, now seen corresponding path program 13 times [2024-05-06 18:06:01,486 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:01,486 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:01,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:01,713 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:01,713 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:01,713 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:01,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:01,941 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:02,197 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:06:02,197 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:06:02,804 INFO L85 PathProgramCache]: Analyzing trace with hash -487811648, now seen corresponding path program 14 times [2024-05-06 18:06:02,804 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:02,804 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:02,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:02,994 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:02,995 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:02,995 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:03,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:03,247 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:03,303 INFO L85 PathProgramCache]: Analyzing trace with hash 2057709120, now seen corresponding path program 15 times [2024-05-06 18:06:03,304 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:03,304 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:03,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:03,489 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:03,490 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:03,490 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:03,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:03,686 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:03,744 INFO L85 PathProgramCache]: Analyzing trace with hash -635525688, now seen corresponding path program 16 times [2024-05-06 18:06:03,744 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:03,744 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:03,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:03,932 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:03,932 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:03,933 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:03,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:04,131 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:04,190 INFO L85 PathProgramCache]: Analyzing trace with hash 1773541186, now seen corresponding path program 17 times [2024-05-06 18:06:04,190 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:04,190 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:04,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:04,427 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:04,428 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:04,428 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:04,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:04,628 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:04,856 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:06:04,858 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:06:05,496 INFO L85 PathProgramCache]: Analyzing trace with hash 354785217, now seen corresponding path program 18 times [2024-05-06 18:06:05,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:05,496 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:05,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:05,666 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:05,672 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:05,672 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:05,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:05,856 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:05,912 INFO L85 PathProgramCache]: Analyzing trace with hash -1886559137, now seen corresponding path program 19 times [2024-05-06 18:06:05,912 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:05,913 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:05,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:06,218 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:06,218 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:06,218 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:06,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:06,389 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:06,454 INFO L85 PathProgramCache]: Analyzing trace with hash 1646209929, now seen corresponding path program 20 times [2024-05-06 18:06:06,455 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:06,455 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:06,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:06,640 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:06,640 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:06,640 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:06,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:06,810 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:06,881 INFO L85 PathProgramCache]: Analyzing trace with hash -507098719, now seen corresponding path program 21 times [2024-05-06 18:06:06,881 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:06,881 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:06,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:07,053 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:07,053 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:07,053 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:07,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:07,363 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:07,497 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:06:07,498 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:06:07,551 INFO L85 PathProgramCache]: Analyzing trace with hash -1181985519, now seen corresponding path program 1 times [2024-05-06 18:06:07,552 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:07,552 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:07,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:07,778 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:06:07,779 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:07,779 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:07,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:07,997 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:06:08,120 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:06:08,120 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:06:08,175 INFO L85 PathProgramCache]: Analyzing trace with hash 510754438, now seen corresponding path program 2 times [2024-05-06 18:06:08,175 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:08,176 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:08,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:08,347 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:08,347 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:08,347 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:08,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:08,510 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:08,603 INFO L85 PathProgramCache]: Analyzing trace with hash -1346480600, now seen corresponding path program 3 times [2024-05-06 18:06:08,604 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:08,604 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:08,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:08,850 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:08,850 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:08,851 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:08,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:09,131 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:09,204 INFO L85 PathProgramCache]: Analyzing trace with hash 1121515651, now seen corresponding path program 4 times [2024-05-06 18:06:09,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:09,204 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:09,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:09,376 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:09,376 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:09,376 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:09,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:09,548 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:09,606 INFO L85 PathProgramCache]: Analyzing trace with hash 824956184, now seen corresponding path program 1 times [2024-05-06 18:06:09,607 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:09,607 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:09,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:09,787 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:06:09,788 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:09,788 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:09,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:09,967 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:06:10,083 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:06:10,083 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:06:10,128 INFO L85 PathProgramCache]: Analyzing trace with hash -804672068, now seen corresponding path program 2 times [2024-05-06 18:06:10,129 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:10,129 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:10,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:10,314 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:06:10,315 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:10,315 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:10,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:10,565 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:06:10,676 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:06:10,676 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:06:10,729 INFO L85 PathProgramCache]: Analyzing trace with hash -285483589, now seen corresponding path program 3 times [2024-05-06 18:06:10,730 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:10,730 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:10,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:10,895 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:10,895 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:10,895 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:10,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:11,064 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:11,117 INFO L85 PathProgramCache]: Analyzing trace with hash -260055661, now seen corresponding path program 4 times [2024-05-06 18:06:11,117 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:11,117 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:11,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:11,284 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:11,284 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:11,284 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:11,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:11,449 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:11,508 INFO L85 PathProgramCache]: Analyzing trace with hash 1882328005, now seen corresponding path program 1 times [2024-05-06 18:06:11,509 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:11,509 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:11,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:11,681 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:06:11,681 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:11,681 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:11,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:11,859 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:06:11,966 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:06:11,966 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:06:12,021 INFO L85 PathProgramCache]: Analyzing trace with hash 2000383343, now seen corresponding path program 2 times [2024-05-06 18:06:12,022 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:12,022 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:12,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:12,271 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:06:12,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:12,272 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:12,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:12,439 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:06:12,553 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:06:12,553 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:06:12,603 INFO L85 PathProgramCache]: Analyzing trace with hash 383415016, now seen corresponding path program 3 times [2024-05-06 18:06:12,603 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:12,603 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:12,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:12,770 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:12,770 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:12,771 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:12,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:12,934 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:13,014 INFO L85 PathProgramCache]: Analyzing trace with hash -999035386, now seen corresponding path program 4 times [2024-05-06 18:06:13,014 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:13,014 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:13,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:13,277 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:13,277 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:13,277 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:13,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:13,440 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:13,499 INFO L85 PathProgramCache]: Analyzing trace with hash -734979973, now seen corresponding path program 22 times [2024-05-06 18:06:13,499 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:13,499 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:13,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:13,669 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:06:13,670 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:13,670 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:13,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:14,060 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:06:14,185 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:06:14,186 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:06:14,236 INFO L85 PathProgramCache]: Analyzing trace with hash 1500312057, now seen corresponding path program 23 times [2024-05-06 18:06:14,236 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:14,236 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:14,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:14,475 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:06:14,475 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:14,475 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:14,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:14,678 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:06:14,817 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:06:14,818 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:06:14,873 INFO L85 PathProgramCache]: Analyzing trace with hash 1100499614, now seen corresponding path program 24 times [2024-05-06 18:06:14,873 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:14,873 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:14,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:15,046 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:15,046 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:15,046 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:15,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:15,223 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:15,288 INFO L85 PathProgramCache]: Analyzing trace with hash -244249328, now seen corresponding path program 25 times [2024-05-06 18:06:15,289 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:15,289 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:15,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:15,459 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:15,460 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:15,460 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:15,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:15,634 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:16,020 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:06:16,021 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:06:18,591 INFO L85 PathProgramCache]: Analyzing trace with hash -1118816267, now seen corresponding path program 26 times [2024-05-06 18:06:18,591 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:18,591 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:18,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:18,785 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:06:18,785 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:18,785 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:18,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:18,957 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:06:19,203 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:06:19,204 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:06:19,819 INFO L85 PathProgramCache]: Analyzing trace with hash -872320021, now seen corresponding path program 27 times [2024-05-06 18:06:19,819 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:19,819 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:19,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:19,977 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:06:19,977 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:19,978 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:19,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:20,134 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:06:20,188 INFO L85 PathProgramCache]: Analyzing trace with hash -780884445, now seen corresponding path program 28 times [2024-05-06 18:06:20,188 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:20,188 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:20,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:20,349 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:06:20,349 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:20,351 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:20,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:20,510 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:06:20,745 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:06:20,746 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:06:21,360 INFO L85 PathProgramCache]: Analyzing trace with hash -1413612687, now seen corresponding path program 29 times [2024-05-06 18:06:21,360 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:21,360 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:21,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:21,513 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:06:21,514 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:21,514 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:21,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:21,671 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:06:21,774 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:06:21,774 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:06:21,835 INFO L85 PathProgramCache]: Analyzing trace with hash -1272093655, now seen corresponding path program 30 times [2024-05-06 18:06:21,835 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:21,835 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:21,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:21,999 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:06:21,999 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:21,999 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:22,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:22,160 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:06:22,353 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:06:22,353 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:06:22,825 INFO L85 PathProgramCache]: Analyzing trace with hash 2087200140, now seen corresponding path program 1 times [2024-05-06 18:06:22,825 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:22,826 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:22,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:23,097 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:06:23,098 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:23,098 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:23,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:23,319 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:06:23,562 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:06:23,562 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:06:24,522 INFO L85 PathProgramCache]: Analyzing trace with hash -2014346677, now seen corresponding path program 2 times [2024-05-06 18:06:24,523 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:24,523 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:24,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:24,711 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:24,712 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:24,712 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:24,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:24,894 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:25,089 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:06:25,089 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:06:25,747 INFO L85 PathProgramCache]: Analyzing trace with hash 1591349721, now seen corresponding path program 1 times [2024-05-06 18:06:25,747 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:25,748 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:25,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:25,915 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:06:25,915 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:25,915 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:25,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:26,086 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:06:26,326 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:06:26,326 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:06:26,926 INFO L85 PathProgramCache]: Analyzing trace with hash 50207902, now seen corresponding path program 2 times [2024-05-06 18:06:26,927 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:26,927 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:26,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:27,112 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:27,112 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:27,112 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:27,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:27,427 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:27,672 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:06:27,672 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:06:28,211 INFO L85 PathProgramCache]: Analyzing trace with hash -779949976, now seen corresponding path program 1 times [2024-05-06 18:06:28,212 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:28,212 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:28,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:28,364 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:06:28,364 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:28,365 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:28,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:28,512 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:06:28,743 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:06:28,743 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:06:33,493 INFO L85 PathProgramCache]: Analyzing trace with hash -420727057, now seen corresponding path program 2 times [2024-05-06 18:06:33,494 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:33,494 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:33,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:33,666 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:33,666 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:33,666 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:33,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:33,841 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:34,038 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:06:34,050 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:06:34,735 INFO L85 PathProgramCache]: Analyzing trace with hash -1272085714, now seen corresponding path program 1 times [2024-05-06 18:06:34,735 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:34,735 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:34,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:35,008 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:06:35,008 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:35,009 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:35,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:35,153 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:06:35,366 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:06:35,366 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:06:43,878 WARN L854 $PredicateComparison]: unable to prove that (and (forall ((v_~q2~0.base_In_20 Int) (v_~q2~0.offset_In_20 Int) (v_~q2_front~0_In_21 Int)) (let ((.cse0 (select (select |c_#memory_int| v_~q2~0.base_In_20) (+ (* v_~q2_front~0_In_21 4) v_~q2~0.offset_In_20)))) (or (= 0 .cse0) (< (+ 4294967295 .cse0) 0) (< v_~q2_front~0_In_21 0) (< 4294967295 .cse0)))) (forall ((v_~q1~0.offset_In_30 Int) (v_~q1~0.base_In_30 Int)) (= 0 (select (select |c_#memory_int| v_~q1~0.base_In_30) (+ (* c_~q1_front~0 4) v_~q1~0.offset_In_30))))) is different from false [2024-05-06 18:06:43,881 INFO L85 PathProgramCache]: Analyzing trace with hash -2107876631, now seen corresponding path program 2 times [2024-05-06 18:06:43,881 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:43,881 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:43,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:44,055 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:44,055 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:44,056 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:44,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:44,228 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:44,457 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:06:44,457 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:06:44,918 INFO L85 PathProgramCache]: Analyzing trace with hash -872319029, now seen corresponding path program 1 times [2024-05-06 18:06:44,918 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:44,918 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:44,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:45,073 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:06:45,073 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:45,073 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:45,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:45,229 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:06:45,427 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:06:45,427 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:06:45,959 INFO L85 PathProgramCache]: Analyzing trace with hash 1489323756, now seen corresponding path program 2 times [2024-05-06 18:06:45,960 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:45,960 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:45,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:46,251 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:46,252 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:46,252 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:46,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:46,412 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:46,612 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:06:46,612 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:06:47,207 INFO L85 PathProgramCache]: Analyzing trace with hash -1413612656, now seen corresponding path program 1 times [2024-05-06 18:06:47,207 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:47,207 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:47,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:47,365 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:06:47,366 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:47,366 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:47,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:47,521 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:06:47,716 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:06:47,716 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:06:56,182 WARN L854 $PredicateComparison]: unable to prove that (and (forall ((v_~q2~0.base_In_24 Int) (v_~q2~0.offset_In_24 Int) (v_~q2_front~0_In_25 Int)) (let ((.cse0 (select (select |c_#memory_int| v_~q2~0.base_In_24) (+ v_~q2~0.offset_In_24 (* v_~q2_front~0_In_25 4))))) (or (< v_~q2_front~0_In_25 0) (< 4294967295 .cse0) (< (+ .cse0 4294967295) 0) (= .cse0 0)))) (forall ((v_~q1~0.offset_In_34 Int) (v_~q1~0.base_In_34 Int)) (= (select (select |c_#memory_int| v_~q1~0.base_In_34) (+ (* c_~q1_front~0 4) v_~q1~0.offset_In_34)) 0))) is different from false [2024-05-06 18:06:56,185 INFO L85 PathProgramCache]: Analyzing trace with hash -34590521, now seen corresponding path program 2 times [2024-05-06 18:06:56,185 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:56,185 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:56,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:56,354 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:56,355 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:56,355 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:56,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:56,527 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:06:56,758 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:06:56,758 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:06:59,476 INFO L85 PathProgramCache]: Analyzing trace with hash -1708168402, now seen corresponding path program 31 times [2024-05-06 18:06:59,476 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:59,476 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:59,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:59,753 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:06:59,753 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:06:59,753 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:06:59,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:06:59,897 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:07:00,133 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:07:00,133 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:07:05,129 INFO L85 PathProgramCache]: Analyzing trace with hash 1543467753, now seen corresponding path program 32 times [2024-05-06 18:07:05,129 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:05,129 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:05,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:05,329 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:07:05,329 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:05,330 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:05,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:05,500 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:07:05,625 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:07:05,625 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:07:05,673 INFO L85 PathProgramCache]: Analyzing trace with hash 1828470502, now seen corresponding path program 33 times [2024-05-06 18:07:05,674 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:05,674 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:05,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:05,819 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:07:05,819 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:05,819 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:05,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:05,970 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:07:06,190 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:07:06,190 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:07:09,518 INFO L85 PathProgramCache]: Analyzing trace with hash -1104471180, now seen corresponding path program 34 times [2024-05-06 18:07:09,518 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:09,519 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:09,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:09,788 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:07:09,788 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:09,788 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:09,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:09,937 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:07:10,053 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:07:10,053 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:07:10,113 INFO L85 PathProgramCache]: Analyzing trace with hash 121132812, now seen corresponding path program 35 times [2024-05-06 18:07:10,113 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:10,115 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:10,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:10,262 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:07:10,264 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:10,266 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:10,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:10,416 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:07:10,530 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:07:10,531 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:07:10,584 INFO L85 PathProgramCache]: Analyzing trace with hash -539849092, now seen corresponding path program 36 times [2024-05-06 18:07:10,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:10,584 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:10,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:10,744 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:07:10,744 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:10,745 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:10,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:10,894 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:07:10,980 INFO L85 PathProgramCache]: Analyzing trace with hash 102387599, now seen corresponding path program 37 times [2024-05-06 18:07:10,980 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:10,981 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:11,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:11,122 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:07:11,122 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:11,122 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:11,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:11,262 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:07:11,355 INFO L85 PathProgramCache]: Analyzing trace with hash 1893311619, now seen corresponding path program 38 times [2024-05-06 18:07:11,355 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:11,356 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:11,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:11,600 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:07:11,600 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:11,601 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:11,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:11,766 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:07:11,998 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:07:11,999 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:07:17,556 INFO L85 PathProgramCache]: Analyzing trace with hash 1893311608, now seen corresponding path program 39 times [2024-05-06 18:07:17,557 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:17,557 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:17,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:17,734 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:07:17,734 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:17,734 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:17,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:17,897 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:07:17,951 INFO L85 PathProgramCache]: Analyzing trace with hash -1593645440, now seen corresponding path program 40 times [2024-05-06 18:07:17,951 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:17,951 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:17,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:18,118 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:07:18,119 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:18,119 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:18,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:18,286 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:07:18,339 INFO L85 PathProgramCache]: Analyzing trace with hash 278213549, now seen corresponding path program 41 times [2024-05-06 18:07:18,339 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:18,340 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:18,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:18,511 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:07:18,511 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:18,511 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:18,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:18,682 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:07:18,859 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:07:18,860 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:07:18,965 INFO L85 PathProgramCache]: Analyzing trace with hash 1064655385, now seen corresponding path program 42 times [2024-05-06 18:07:18,965 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:18,966 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:18,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:19,285 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:07:19,285 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:19,286 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:19,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:19,463 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:07:19,608 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:07:19,608 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:07:19,673 INFO L85 PathProgramCache]: Analyzing trace with hash -1355420401, now seen corresponding path program 43 times [2024-05-06 18:07:19,673 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:19,673 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:19,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:19,856 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:07:19,857 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:19,857 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:19,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:20,039 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:07:20,190 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:07:20,190 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:07:20,254 INFO L85 PathProgramCache]: Analyzing trace with hash 1216748914, now seen corresponding path program 44 times [2024-05-06 18:07:20,254 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:20,254 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:20,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:20,431 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:07:20,432 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:20,432 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:20,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:20,608 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:07:20,663 INFO L85 PathProgramCache]: Analyzing trace with hash -935488315, now seen corresponding path program 45 times [2024-05-06 18:07:20,663 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:20,663 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:20,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:20,847 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:07:20,848 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:20,848 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:20,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:21,035 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:07:21,214 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:07:21,214 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:07:21,287 INFO L85 PathProgramCache]: Analyzing trace with hash 1840365230, now seen corresponding path program 46 times [2024-05-06 18:07:21,287 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:21,288 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:21,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:21,592 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:07:21,593 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:21,593 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:21,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:21,775 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:07:22,008 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:07:22,009 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:07:22,719 INFO L85 PathProgramCache]: Analyzing trace with hash -1825704857, now seen corresponding path program 47 times [2024-05-06 18:07:22,719 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:22,719 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:22,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:22,877 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:07:22,877 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:22,878 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:22,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:23,036 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:07:23,086 INFO L85 PathProgramCache]: Analyzing trace with hash -762274687, now seen corresponding path program 48 times [2024-05-06 18:07:23,087 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:23,087 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:23,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:23,246 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:07:23,246 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:23,247 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:23,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:23,407 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:07:23,458 INFO L85 PathProgramCache]: Analyzing trace with hash 2139289503, now seen corresponding path program 49 times [2024-05-06 18:07:23,458 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:23,458 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:23,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:23,625 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:07:23,626 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:23,626 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:23,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:23,792 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:07:23,982 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:07:23,983 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:07:24,788 INFO L85 PathProgramCache]: Analyzing trace with hash -1444813606, now seen corresponding path program 50 times [2024-05-06 18:07:24,788 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:24,788 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:24,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:24,999 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:07:24,999 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:24,999 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:25,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:25,187 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:07:25,429 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:07:25,429 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:07:35,065 WARN L293 SmtUtils]: Spent 6.42s on a formula simplification. DAG size of input: 34 DAG size of output: 14 (called from [L 210] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.abduction.Abducer.solveAbductionProblem) [2024-05-06 18:07:35,091 INFO L85 PathProgramCache]: Analyzing trace with hash 1815391981, now seen corresponding path program 51 times [2024-05-06 18:07:35,091 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:35,091 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:35,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:35,258 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:07:35,258 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:35,259 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:35,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:35,426 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:07:35,601 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:07:35,601 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:07:35,678 INFO L85 PathProgramCache]: Analyzing trace with hash 1815391981, now seen corresponding path program 52 times [2024-05-06 18:07:35,678 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:35,679 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:35,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:35,846 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:07:35,847 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:35,847 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:35,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:36,012 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:07:36,157 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:07:36,157 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:07:36,222 INFO L85 PathProgramCache]: Analyzing trace with hash 442577595, now seen corresponding path program 53 times [2024-05-06 18:07:36,222 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:36,222 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:36,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:36,530 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:07:36,531 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:36,531 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:36,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:36,701 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:07:36,847 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:07:36,847 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:07:36,913 INFO L85 PathProgramCache]: Analyzing trace with hash 835004581, now seen corresponding path program 54 times [2024-05-06 18:07:36,913 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:36,913 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:36,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:37,086 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:07:37,086 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:37,086 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:37,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:37,261 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:07:37,409 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:07:37,410 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:07:37,469 INFO L85 PathProgramCache]: Analyzing trace with hash 115339261, now seen corresponding path program 55 times [2024-05-06 18:07:37,469 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:37,469 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:37,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:37,646 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:07:37,646 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:37,646 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:37,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:37,826 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:07:38,057 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:07:38,058 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:07:42,106 INFO L85 PathProgramCache]: Analyzing trace with hash 835021450, now seen corresponding path program 1 times [2024-05-06 18:07:42,107 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:42,107 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:42,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:42,279 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:07:42,279 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:42,279 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:42,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:42,578 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:07:42,776 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:07:42,776 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:07:49,161 WARN L293 SmtUtils]: Spent 6.01s on a formula simplification. DAG size of input: 33 DAG size of output: 14 (called from [L 210] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.abduction.Abducer.solveAbductionProblem) [2024-05-06 18:07:49,196 INFO L85 PathProgramCache]: Analyzing trace with hash 1847393037, now seen corresponding path program 2 times [2024-05-06 18:07:49,196 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:49,196 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:49,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:49,389 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:07:49,389 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:49,389 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:49,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:49,578 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:07:49,821 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:07:49,821 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:07:56,923 INFO L85 PathProgramCache]: Analyzing trace with hash 442578150, now seen corresponding path program 1 times [2024-05-06 18:07:56,923 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:56,923 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:56,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:57,107 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:07:57,107 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:57,108 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:57,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:57,284 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:07:57,494 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:07:57,495 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:07:58,140 INFO L85 PathProgramCache]: Analyzing trace with hash -1047979983, now seen corresponding path program 2 times [2024-05-06 18:07:58,140 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:58,140 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:58,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:58,338 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:07:58,338 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:07:58,338 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:07:58,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:07:58,527 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:07:58,764 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:07:58,765 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:08:03,768 INFO L85 PathProgramCache]: Analyzing trace with hash 1815392012, now seen corresponding path program 1 times [2024-05-06 18:08:03,768 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:03,769 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:03,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:03,954 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:08:03,954 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:03,954 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:03,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:04,140 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:08:04,359 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:08:04,360 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:08:09,665 INFO L85 PathProgramCache]: Analyzing trace with hash 266709195, now seen corresponding path program 2 times [2024-05-06 18:08:09,666 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:09,666 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:09,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:09,983 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:08:09,983 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:09,983 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:10,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:10,168 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:08:10,407 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:08:10,407 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:08:11,153 INFO L85 PathProgramCache]: Analyzing trace with hash 1721129001, now seen corresponding path program 56 times [2024-05-06 18:08:11,154 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:11,154 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:11,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:11,330 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:08:11,330 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:11,330 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:11,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:11,517 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:08:11,726 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:08:11,726 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:08:16,657 INFO L85 PathProgramCache]: Analyzing trace with hash 1520693326, now seen corresponding path program 57 times [2024-05-06 18:08:16,658 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:16,658 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:16,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:16,863 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:08:16,864 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:16,864 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:16,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:17,065 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:08:17,367 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:08:17,367 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:08:17,429 INFO L85 PathProgramCache]: Analyzing trace with hash -1191405754, now seen corresponding path program 58 times [2024-05-06 18:08:17,429 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:17,429 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:17,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:17,614 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:08:17,615 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:17,615 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:17,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:17,788 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:08:17,845 INFO L85 PathProgramCache]: Analyzing trace with hash 1721128305, now seen corresponding path program 59 times [2024-05-06 18:08:17,845 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:17,846 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:17,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:18,023 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:08:18,023 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:18,023 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:18,048 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:18,195 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:08:18,368 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:08:18,368 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:08:18,444 INFO L85 PathProgramCache]: Analyzing trace with hash -1839547814, now seen corresponding path program 60 times [2024-05-06 18:08:18,444 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:18,444 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:18,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:18,609 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:08:18,609 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:18,609 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:18,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:18,786 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:08:19,010 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:08:19,010 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:08:19,548 INFO L85 PathProgramCache]: Analyzing trace with hash -1191406371, now seen corresponding path program 61 times [2024-05-06 18:08:19,548 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:19,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:19,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:19,737 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:08:19,738 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:19,739 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:19,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:20,065 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:08:20,123 INFO L85 PathProgramCache]: Analyzing trace with hash 1721109195, now seen corresponding path program 62 times [2024-05-06 18:08:20,123 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:20,124 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:20,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:20,308 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:08:20,308 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:20,308 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:20,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:20,485 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:08:20,540 INFO L85 PathProgramCache]: Analyzing trace with hash 1814778517, now seen corresponding path program 63 times [2024-05-06 18:08:20,540 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:20,541 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:20,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:20,714 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:08:20,714 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:20,715 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:20,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:20,890 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:08:20,946 INFO L85 PathProgramCache]: Analyzing trace with hash 423560205, now seen corresponding path program 64 times [2024-05-06 18:08:20,947 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:20,947 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:20,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:21,131 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:08:21,131 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:21,132 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:21,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:21,316 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:08:21,466 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:08:21,467 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:08:21,529 INFO L85 PathProgramCache]: Analyzing trace with hash 939837316, now seen corresponding path program 65 times [2024-05-06 18:08:21,529 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:21,529 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:21,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:21,733 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:08:21,734 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:21,734 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:21,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:21,928 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:08:22,076 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:08:22,076 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:08:22,257 INFO L85 PathProgramCache]: Analyzing trace with hash 939868099, now seen corresponding path program 1 times [2024-05-06 18:08:22,257 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:22,257 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:22,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:22,448 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:08:22,448 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:22,448 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:22,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:22,652 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:08:22,708 INFO L85 PathProgramCache]: Analyzing trace with hash -928858988, now seen corresponding path program 2 times [2024-05-06 18:08:22,708 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:22,709 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:22,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:22,900 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:08:22,900 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:22,900 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:22,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:23,091 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:08:23,274 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:08:23,274 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:08:23,352 INFO L85 PathProgramCache]: Analyzing trace with hash -1086649344, now seen corresponding path program 3 times [2024-05-06 18:08:23,352 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:23,352 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:23,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:23,567 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:08:23,567 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:23,567 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:23,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:23,772 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:08:23,926 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:08:23,926 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:08:23,988 INFO L85 PathProgramCache]: Analyzing trace with hash 673609736, now seen corresponding path program 4 times [2024-05-06 18:08:23,988 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:23,988 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:24,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:24,198 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:08:24,199 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:24,199 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:24,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:24,531 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:08:24,716 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:08:24,716 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:08:24,791 INFO L85 PathProgramCache]: Analyzing trace with hash 1393077799, now seen corresponding path program 5 times [2024-05-06 18:08:24,791 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:24,791 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:24,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:24,989 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:08:24,990 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:24,990 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:25,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:25,201 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:08:25,269 INFO L85 PathProgramCache]: Analyzing trace with hash 837203225, now seen corresponding path program 6 times [2024-05-06 18:08:25,269 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:25,270 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:25,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:25,477 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:08:25,477 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:25,478 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:25,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:25,678 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:08:25,811 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:08:25,811 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:08:25,895 INFO L85 PathProgramCache]: Analyzing trace with hash -108229054, now seen corresponding path program 1 times [2024-05-06 18:08:25,895 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:25,895 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:25,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:26,097 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:08:26,098 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:26,098 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:26,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:26,292 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:08:26,346 INFO L85 PathProgramCache]: Analyzing trace with hash 939867637, now seen corresponding path program 2 times [2024-05-06 18:08:26,347 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:26,347 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:26,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:26,544 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:08:26,544 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:26,545 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:26,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:26,858 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:08:27,042 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:08:27,042 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:08:27,147 INFO L85 PathProgramCache]: Analyzing trace with hash 1450876001, now seen corresponding path program 3 times [2024-05-06 18:08:27,147 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:27,148 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:27,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:27,338 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:08:27,338 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:27,339 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:27,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:27,534 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:08:27,681 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:08:27,681 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:08:27,751 INFO L85 PathProgramCache]: Analyzing trace with hash 2027484103, now seen corresponding path program 4 times [2024-05-06 18:08:27,752 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:27,752 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:27,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:27,953 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:08:27,953 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:27,953 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:27,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:28,154 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:08:28,347 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:08:28,347 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:08:28,417 INFO L85 PathProgramCache]: Analyzing trace with hash -141237914, now seen corresponding path program 5 times [2024-05-06 18:08:28,417 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:28,417 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:28,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:28,609 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:08:28,609 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:28,609 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:28,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:28,815 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:08:28,869 INFO L85 PathProgramCache]: Analyzing trace with hash 705997848, now seen corresponding path program 6 times [2024-05-06 18:08:28,869 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:28,869 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:28,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:29,062 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:08:29,062 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:29,062 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:29,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:29,389 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:08:29,512 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:08:29,512 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:08:29,564 INFO L85 PathProgramCache]: Analyzing trace with hash -1666059291, now seen corresponding path program 1 times [2024-05-06 18:08:29,564 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:29,565 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:29,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:29,747 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:08:29,748 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:29,748 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:29,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:29,931 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:08:29,983 INFO L85 PathProgramCache]: Analyzing trace with hash -108229454, now seen corresponding path program 2 times [2024-05-06 18:08:29,983 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:29,983 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:30,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:30,174 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:08:30,174 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:30,174 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:30,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:30,361 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:08:30,519 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:08:30,520 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:08:30,578 INFO L85 PathProgramCache]: Analyzing trace with hash -245768674, now seen corresponding path program 3 times [2024-05-06 18:08:30,578 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:30,578 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:30,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:30,777 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:08:30,777 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:30,777 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:30,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:30,981 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:08:31,107 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:08:31,108 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:08:31,164 INFO L85 PathProgramCache]: Analyzing trace with hash 971106730, now seen corresponding path program 4 times [2024-05-06 18:08:31,164 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:31,164 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:31,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:31,502 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:08:31,502 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:31,502 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:31,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:31,720 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:08:31,916 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:08:31,916 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:08:31,972 INFO L85 PathProgramCache]: Analyzing trace with hash 1861370057, now seen corresponding path program 5 times [2024-05-06 18:08:31,973 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:31,973 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:31,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:32,169 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:08:32,170 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:32,171 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:32,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:32,364 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:08:32,409 INFO L85 PathProgramCache]: Analyzing trace with hash 1257801787, now seen corresponding path program 6 times [2024-05-06 18:08:32,409 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:32,409 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:32,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:32,628 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:08:32,629 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:32,629 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:32,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:32,824 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:08:32,972 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:08:32,972 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:08:33,036 INFO L85 PathProgramCache]: Analyzing trace with hash -330838555, now seen corresponding path program 66 times [2024-05-06 18:08:33,036 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:33,036 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:33,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:33,213 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:08:33,213 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:33,214 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:33,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:33,398 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:08:33,456 INFO L85 PathProgramCache]: Analyzing trace with hash -1666059598, now seen corresponding path program 67 times [2024-05-06 18:08:33,456 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:33,457 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:33,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:33,760 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:08:33,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:33,760 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:33,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:33,949 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:08:34,102 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:08:34,102 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:08:34,159 INFO L85 PathProgramCache]: Analyzing trace with hash -474397666, now seen corresponding path program 68 times [2024-05-06 18:08:34,159 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:34,159 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:34,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:34,359 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:08:34,359 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:34,359 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:34,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:34,558 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:08:34,695 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:08:34,695 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:08:34,745 INFO L85 PathProgramCache]: Analyzing trace with hash -1821424726, now seen corresponding path program 69 times [2024-05-06 18:08:34,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:34,745 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:34,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:34,949 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:08:34,949 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:34,950 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:34,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:35,157 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:08:35,313 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:08:35,313 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:08:35,380 INFO L85 PathProgramCache]: Analyzing trace with hash 154966729, now seen corresponding path program 70 times [2024-05-06 18:08:35,380 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:35,380 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:35,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:35,610 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:08:35,610 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:35,611 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:35,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:35,801 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:08:35,859 INFO L85 PathProgramCache]: Analyzing trace with hash -938384837, now seen corresponding path program 71 times [2024-05-06 18:08:35,860 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:35,860 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:35,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:36,168 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:08:36,168 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:36,169 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:36,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:36,358 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:08:36,538 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:08:36,539 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:08:36,618 INFO L85 PathProgramCache]: Analyzing trace with hash -762093154, now seen corresponding path program 72 times [2024-05-06 18:08:36,618 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:36,618 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:36,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:36,780 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:08:36,780 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:36,780 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:36,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:36,939 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:08:37,143 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:08:37,144 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:08:37,610 INFO L85 PathProgramCache]: Analyzing trace with hash 2144917023, now seen corresponding path program 73 times [2024-05-06 18:08:37,611 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:37,611 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:37,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:37,767 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:08:37,767 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:37,767 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:37,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:37,924 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:08:38,072 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:08:38,072 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:08:38,140 INFO L85 PathProgramCache]: Analyzing trace with hash 2067919297, now seen corresponding path program 74 times [2024-05-06 18:08:38,141 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:38,141 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:38,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:38,300 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:08:38,300 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:38,300 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:38,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:38,580 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:08:38,707 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:08:38,708 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:08:38,757 INFO L85 PathProgramCache]: Analyzing trace with hash -319010201, now seen corresponding path program 75 times [2024-05-06 18:08:38,757 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:38,758 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:38,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:38,925 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:08:38,925 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:38,925 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:38,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:39,099 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:08:39,254 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:08:39,255 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:08:39,322 INFO L85 PathProgramCache]: Analyzing trace with hash 2055156922, now seen corresponding path program 76 times [2024-05-06 18:08:39,322 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:39,322 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:39,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:39,476 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:08:39,477 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:39,477 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:39,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:39,633 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:08:39,899 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:08:39,900 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:08:45,098 INFO L85 PathProgramCache]: Analyzing trace with hash 199169406, now seen corresponding path program 77 times [2024-05-06 18:08:45,098 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:45,098 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:45,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:45,253 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:08:45,253 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:45,253 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:45,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:45,405 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:08:45,463 INFO L85 PathProgramCache]: Analyzing trace with hash -553842621, now seen corresponding path program 78 times [2024-05-06 18:08:45,463 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:45,463 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:45,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:45,732 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:08:45,733 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:45,733 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:45,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:45,875 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:08:46,006 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:08:46,007 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:08:46,061 INFO L85 PathProgramCache]: Analyzing trace with hash -1899287758, now seen corresponding path program 79 times [2024-05-06 18:08:46,061 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:46,061 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:46,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:46,212 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:08:46,212 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:46,212 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:46,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:46,378 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:08:46,432 INFO L85 PathProgramCache]: Analyzing trace with hash 1251622661, now seen corresponding path program 80 times [2024-05-06 18:08:46,432 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:46,432 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:46,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:46,584 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:08:46,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:46,584 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:46,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:46,737 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:08:46,792 INFO L85 PathProgramCache]: Analyzing trace with hash -1814343672, now seen corresponding path program 81 times [2024-05-06 18:08:46,792 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:46,792 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:46,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:46,950 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:08:46,951 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:46,951 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:46,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:47,106 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:08:47,161 INFO L85 PathProgramCache]: Analyzing trace with hash 1052106525, now seen corresponding path program 82 times [2024-05-06 18:08:47,161 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:47,161 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:47,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:47,326 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:08:47,327 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:47,327 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:47,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:47,491 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:08:47,547 INFO L85 PathProgramCache]: Analyzing trace with hash -829612346, now seen corresponding path program 83 times [2024-05-06 18:08:47,547 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:47,547 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:47,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:47,847 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:08:47,848 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:47,848 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:47,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:48,029 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 18:08:48,144 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:08:48,144 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:08:48,207 INFO L85 PathProgramCache]: Analyzing trace with hash -442403250, now seen corresponding path program 84 times [2024-05-06 18:08:48,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:48,208 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:48,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:48,384 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:08:48,384 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:48,384 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:48,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:48,559 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:08:48,682 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:08:48,683 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:08:48,737 INFO L85 PathProgramCache]: Analyzing trace with hash -1645138327, now seen corresponding path program 85 times [2024-05-06 18:08:48,738 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:48,738 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:48,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:48,905 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:08:48,905 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:48,906 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:48,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:49,073 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:08:49,128 INFO L85 PathProgramCache]: Analyzing trace with hash 540320421, now seen corresponding path program 86 times [2024-05-06 18:08:49,128 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:49,128 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:49,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:49,300 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:08:49,300 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:49,300 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:49,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:49,468 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:08:49,701 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:08:49,701 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:08:50,679 INFO L85 PathProgramCache]: Analyzing trace with hash 1757065232, now seen corresponding path program 87 times [2024-05-06 18:08:50,679 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:50,679 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:50,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:50,844 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:08:50,845 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:50,845 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:50,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:51,009 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:08:51,064 INFO L85 PathProgramCache]: Analyzing trace with hash 617573400, now seen corresponding path program 88 times [2024-05-06 18:08:51,064 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:51,064 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:51,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:51,239 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:08:51,240 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:51,240 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:51,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:51,411 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:08:51,532 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:08:51,532 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:08:51,590 INFO L85 PathProgramCache]: Analyzing trace with hash 782583609, now seen corresponding path program 89 times [2024-05-06 18:08:51,590 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:51,590 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:51,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:51,761 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:08:51,761 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:51,761 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:51,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:51,929 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:08:51,984 INFO L85 PathProgramCache]: Analyzing trace with hash -1509710891, now seen corresponding path program 90 times [2024-05-06 18:08:51,984 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:51,984 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:52,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:52,158 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:08:52,158 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:52,158 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:52,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:52,331 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:08:52,385 INFO L85 PathProgramCache]: Analyzing trace with hash 443603652, now seen corresponding path program 91 times [2024-05-06 18:08:52,386 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:52,386 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:52,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:52,680 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:08:52,680 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:52,680 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:52,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:52,851 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:08:52,906 INFO L85 PathProgramCache]: Analyzing trace with hash 866812728, now seen corresponding path program 92 times [2024-05-06 18:08:52,906 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:52,907 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:52,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:53,089 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:08:53,089 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:53,089 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:53,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:53,265 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:08:53,446 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:08:53,446 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:08:53,518 INFO L85 PathProgramCache]: Analyzing trace with hash 485748388, now seen corresponding path program 93 times [2024-05-06 18:08:53,518 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:53,518 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:53,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:53,713 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:08:53,713 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:53,714 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:53,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:53,905 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:08:54,054 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:08:54,054 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:08:54,120 INFO L85 PathProgramCache]: Analyzing trace with hash -2121668124, now seen corresponding path program 94 times [2024-05-06 18:08:54,120 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:54,121 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:54,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:54,311 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:08:54,312 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:54,312 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:54,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:54,500 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:08:54,780 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:08:54,781 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:08:54,845 INFO L85 PathProgramCache]: Analyzing trace with hash -853124931, now seen corresponding path program 95 times [2024-05-06 18:08:54,845 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:54,845 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:54,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:55,034 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:08:55,035 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:55,035 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:55,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:55,244 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:08:55,301 INFO L85 PathProgramCache]: Analyzing trace with hash -677068070, now seen corresponding path program 96 times [2024-05-06 18:08:55,301 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:55,302 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:55,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:55,496 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:08:55,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:55,496 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:55,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:55,691 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:08:55,872 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:08:55,872 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:08:55,952 INFO L85 PathProgramCache]: Analyzing trace with hash -1412993533, now seen corresponding path program 97 times [2024-05-06 18:08:55,952 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:55,952 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:55,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:56,151 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:08:56,151 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:56,151 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:56,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:56,333 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:08:56,391 INFO L85 PathProgramCache]: Analyzing trace with hash 2082154034, now seen corresponding path program 98 times [2024-05-06 18:08:56,391 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:56,391 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:56,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:56,584 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:08:56,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:56,584 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:56,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:56,899 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:08:57,071 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:08:57,071 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:08:57,140 INFO L85 PathProgramCache]: Analyzing trace with hash -1101742755, now seen corresponding path program 99 times [2024-05-06 18:08:57,140 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:57,140 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:57,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:57,316 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:08:57,316 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:57,316 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:57,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:57,494 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:08:57,617 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:08:57,618 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:08:57,668 INFO L85 PathProgramCache]: Analyzing trace with hash 205713995, now seen corresponding path program 100 times [2024-05-06 18:08:57,668 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:57,669 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:57,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:57,851 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:08:57,852 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:57,852 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:57,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:58,043 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:08:58,177 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:08:58,178 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:08:58,229 INFO L85 PathProgramCache]: Analyzing trace with hash -206732874, now seen corresponding path program 101 times [2024-05-06 18:08:58,230 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:58,230 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:58,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:58,433 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:08:58,434 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:58,434 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:58,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:58,619 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:08:58,673 INFO L85 PathProgramCache]: Analyzing trace with hash -2113750783, now seen corresponding path program 102 times [2024-05-06 18:08:58,673 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:58,673 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:58,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:58,864 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:08:58,864 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:58,864 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:58,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:59,184 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:08:59,338 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:08:59,339 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:08:59,403 INFO L85 PathProgramCache]: Analyzing trace with hash 1101709802, now seen corresponding path program 103 times [2024-05-06 18:08:59,404 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:59,404 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:59,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:59,590 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:08:59,591 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:08:59,591 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:08:59,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:08:59,769 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:08:59,944 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:08:59,944 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:09:00,008 INFO L85 PathProgramCache]: Analyzing trace with hash -319466590, now seen corresponding path program 3 times [2024-05-06 18:09:00,008 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:00,008 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:00,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:00,192 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:00,193 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:00,193 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:00,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:00,381 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:00,512 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:09:00,513 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:09:00,561 INFO L85 PathProgramCache]: Analyzing trace with hash -1313528666, now seen corresponding path program 4 times [2024-05-06 18:09:00,562 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:00,562 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:00,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:00,752 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:00,752 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:00,752 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:00,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:00,944 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:01,086 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:09:01,087 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:09:01,137 INFO L85 PathProgramCache]: Analyzing trace with hash 1872291131, now seen corresponding path program 5 times [2024-05-06 18:09:01,137 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:01,137 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:01,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:01,316 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:01,316 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:01,316 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:01,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:01,625 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:01,678 INFO L85 PathProgramCache]: Analyzing trace with hash -2088516068, now seen corresponding path program 6 times [2024-05-06 18:09:01,679 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:01,679 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:01,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:01,870 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:09:01,870 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:01,870 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:01,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:02,070 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:09:02,221 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:09:02,221 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:09:02,286 INFO L85 PathProgramCache]: Analyzing trace with hash 1722964421, now seen corresponding path program 7 times [2024-05-06 18:09:02,287 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:02,287 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:02,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:02,468 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:02,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:02,469 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:02,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:02,652 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:02,706 INFO L85 PathProgramCache]: Analyzing trace with hash 77770807, now seen corresponding path program 8 times [2024-05-06 18:09:02,706 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:02,706 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:02,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:02,889 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:02,890 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:02,890 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:02,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:03,073 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:03,126 INFO L85 PathProgramCache]: Analyzing trace with hash -1249042662, now seen corresponding path program 3 times [2024-05-06 18:09:03,126 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:03,126 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:03,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:03,320 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:09:03,321 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:03,321 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:03,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:03,641 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:09:03,790 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:09:03,790 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:09:03,855 INFO L85 PathProgramCache]: Analyzing trace with hash 1178587205, now seen corresponding path program 4 times [2024-05-06 18:09:03,856 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:03,856 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:03,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:04,045 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:04,045 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:04,045 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:04,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:04,234 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:04,360 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:09:04,361 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:09:04,411 INFO L85 PathProgramCache]: Analyzing trace with hash -2118501277, now seen corresponding path program 5 times [2024-05-06 18:09:04,412 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:04,412 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:04,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:04,604 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:04,604 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:04,604 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:04,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:04,796 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:05,152 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:09:05,153 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:09:05,209 INFO L85 PathProgramCache]: Analyzing trace with hash 1771056798, now seen corresponding path program 6 times [2024-05-06 18:09:05,209 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:05,209 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:05,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:05,397 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:05,398 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:05,398 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:05,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:05,577 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:05,632 INFO L85 PathProgramCache]: Analyzing trace with hash -931813095, now seen corresponding path program 7 times [2024-05-06 18:09:05,632 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:05,632 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:05,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:05,830 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:09:05,830 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:05,830 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:05,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:06,141 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:09:06,311 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:09:06,311 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:09:06,383 INFO L85 PathProgramCache]: Analyzing trace with hash -1882531838, now seen corresponding path program 8 times [2024-05-06 18:09:06,384 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:06,384 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:06,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:06,569 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:06,569 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:06,570 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:06,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:06,747 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:06,804 INFO L85 PathProgramCache]: Analyzing trace with hash 1454898003, now seen corresponding path program 3 times [2024-05-06 18:09:06,805 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:06,805 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:06,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:06,996 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:09:06,996 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:06,996 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:07,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:07,193 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:09:07,343 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:09:07,343 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:09:07,405 INFO L85 PathProgramCache]: Analyzing trace with hash 716596926, now seen corresponding path program 4 times [2024-05-06 18:09:07,405 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:07,405 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:07,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:07,596 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:07,596 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:07,596 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:07,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:07,794 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:07,919 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:09:07,920 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:09:07,971 INFO L85 PathProgramCache]: Analyzing trace with hash 739669258, now seen corresponding path program 5 times [2024-05-06 18:09:07,971 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:07,971 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:07,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:08,279 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:08,279 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:08,279 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:08,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:08,475 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:08,612 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:09:08,612 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:09:08,665 INFO L85 PathProgramCache]: Analyzing trace with hash -1719922857, now seen corresponding path program 6 times [2024-05-06 18:09:08,666 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:08,666 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:08,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:08,849 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:08,850 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:08,850 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:08,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:09,036 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:09,091 INFO L85 PathProgramCache]: Analyzing trace with hash -1778000000, now seen corresponding path program 7 times [2024-05-06 18:09:09,091 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:09,091 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:09,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:09,283 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:09:09,284 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:09,284 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:09,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:09,477 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:09:09,652 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:09:09,652 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:09:09,730 INFO L85 PathProgramCache]: Analyzing trace with hash 83065897, now seen corresponding path program 8 times [2024-05-06 18:09:09,730 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:09,731 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:09,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:09,917 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:09,917 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:09,917 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:09,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:10,099 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:10,156 INFO L85 PathProgramCache]: Analyzing trace with hash 1859137071, now seen corresponding path program 3 times [2024-05-06 18:09:10,156 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:10,156 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:10,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:10,472 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:09:10,472 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:10,472 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:10,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:10,668 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:09:10,849 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:09:10,849 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:09:10,923 INFO L85 PathProgramCache]: Analyzing trace with hash 95789210, now seen corresponding path program 4 times [2024-05-06 18:09:10,923 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:10,923 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:10,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:11,118 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:11,118 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:11,119 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:11,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:11,303 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:11,431 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:09:11,431 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:09:11,478 INFO L85 PathProgramCache]: Analyzing trace with hash -1325500754, now seen corresponding path program 5 times [2024-05-06 18:09:11,479 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:11,479 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:11,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:11,668 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:11,668 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:11,668 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:11,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:11,856 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:12,007 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:09:12,008 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:09:12,059 INFO L85 PathProgramCache]: Analyzing trace with hash 58200115, now seen corresponding path program 6 times [2024-05-06 18:09:12,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:12,059 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:12,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:12,249 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:12,250 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:12,250 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:12,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:12,433 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:12,484 INFO L85 PathProgramCache]: Analyzing trace with hash 1804204580, now seen corresponding path program 7 times [2024-05-06 18:09:12,484 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:12,484 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:12,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:12,794 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:09:12,795 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:12,795 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:12,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:12,977 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:09:13,158 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:09:13,158 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:09:13,218 INFO L85 PathProgramCache]: Analyzing trace with hash -1522143283, now seen corresponding path program 8 times [2024-05-06 18:09:13,218 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:13,218 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:13,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:13,398 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:13,399 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:13,399 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:13,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:13,581 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:13,636 INFO L85 PathProgramCache]: Analyzing trace with hash 957570294, now seen corresponding path program 3 times [2024-05-06 18:09:13,636 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:13,637 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:13,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:13,830 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:09:13,831 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:13,831 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:13,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:14,019 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:09:14,176 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:09:14,176 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:09:14,234 INFO L85 PathProgramCache]: Analyzing trace with hash 380884257, now seen corresponding path program 4 times [2024-05-06 18:09:14,234 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:14,234 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:14,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:14,413 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:14,414 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:14,414 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:14,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:14,594 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:14,717 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:09:14,718 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:09:14,768 INFO L85 PathProgramCache]: Analyzing trace with hash -1077488889, now seen corresponding path program 5 times [2024-05-06 18:09:14,769 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:14,769 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:14,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:15,072 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:15,072 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:15,074 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:15,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:15,265 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:15,390 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:09:15,391 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:09:15,441 INFO L85 PathProgramCache]: Analyzing trace with hash -1514685830, now seen corresponding path program 6 times [2024-05-06 18:09:15,442 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:15,442 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:15,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:15,623 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:15,623 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:15,623 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:15,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:15,805 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:15,856 INFO L85 PathProgramCache]: Analyzing trace with hash 289380541, now seen corresponding path program 7 times [2024-05-06 18:09:15,857 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:15,857 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:15,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:16,062 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:09:16,063 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:16,063 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:16,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:16,257 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:09:16,407 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:09:16,407 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:09:16,471 INFO L85 PathProgramCache]: Analyzing trace with hash -187408218, now seen corresponding path program 8 times [2024-05-06 18:09:16,471 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:16,471 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:16,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:16,642 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:16,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:16,643 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:16,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:16,813 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:16,867 INFO L85 PathProgramCache]: Analyzing trace with hash 1885640529, now seen corresponding path program 3 times [2024-05-06 18:09:16,868 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:16,868 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:16,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:17,175 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:09:17,176 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:17,176 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:17,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:17,362 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:09:17,511 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:09:17,511 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:09:17,574 INFO L85 PathProgramCache]: Analyzing trace with hash 641067580, now seen corresponding path program 4 times [2024-05-06 18:09:17,574 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:17,574 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:17,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:17,751 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:17,751 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:17,751 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:17,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:17,933 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:18,058 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:09:18,059 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:09:18,107 INFO L85 PathProgramCache]: Analyzing trace with hash -1601740468, now seen corresponding path program 5 times [2024-05-06 18:09:18,107 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:18,107 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:18,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:18,298 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:18,299 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:18,299 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:18,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:18,494 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:18,623 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:09:18,623 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:09:18,673 INFO L85 PathProgramCache]: Analyzing trace with hash -178103723, now seen corresponding path program 6 times [2024-05-06 18:09:18,674 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:18,674 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:18,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:18,860 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:18,860 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:18,861 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:18,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:19,047 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:19,100 INFO L85 PathProgramCache]: Analyzing trace with hash -1226247102, now seen corresponding path program 7 times [2024-05-06 18:09:19,100 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:19,100 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:19,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:19,417 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:09:19,418 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:19,419 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:19,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:19,619 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:09:19,789 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:09:19,790 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:09:19,865 INFO L85 PathProgramCache]: Analyzing trace with hash 1102633323, now seen corresponding path program 8 times [2024-05-06 18:09:19,865 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:19,865 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:19,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:20,048 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:20,049 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:20,050 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:20,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:20,244 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:20,303 INFO L85 PathProgramCache]: Analyzing trace with hash 233992857, now seen corresponding path program 104 times [2024-05-06 18:09:20,303 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:20,303 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:20,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:20,494 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:09:20,494 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:20,494 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:20,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:20,681 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:09:20,868 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:09:20,869 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:09:20,992 INFO L85 PathProgramCache]: Analyzing trace with hash 1787950980, now seen corresponding path program 105 times [2024-05-06 18:09:20,992 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:20,992 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:21,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:21,283 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:21,283 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:21,283 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:21,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:21,455 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:21,683 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:09:21,683 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:09:21,726 INFO L85 PathProgramCache]: Analyzing trace with hash -408093436, now seen corresponding path program 106 times [2024-05-06 18:09:21,726 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:21,730 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:21,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:21,915 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:21,915 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:21,915 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:21,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:22,120 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:22,262 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:09:22,262 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:09:22,311 INFO L85 PathProgramCache]: Analyzing trace with hash 1114708381, now seen corresponding path program 107 times [2024-05-06 18:09:22,311 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:22,311 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:22,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:22,502 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:22,503 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:22,503 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:22,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:22,686 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:22,745 INFO L85 PathProgramCache]: Analyzing trace with hash 196222458, now seen corresponding path program 108 times [2024-05-06 18:09:22,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:22,745 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:22,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:22,927 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:09:22,927 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:22,927 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:22,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:23,109 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:09:23,285 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:09:23,286 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:09:23,360 INFO L85 PathProgramCache]: Analyzing trace with hash 867242275, now seen corresponding path program 109 times [2024-05-06 18:09:23,360 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:23,360 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:23,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:23,530 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:23,530 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:23,531 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:23,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:23,706 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:23,955 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:09:23,955 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:09:24,010 INFO L85 PathProgramCache]: Analyzing trace with hash 617573371, now seen corresponding path program 110 times [2024-05-06 18:09:24,011 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:24,011 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:24,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:24,180 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:24,180 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:24,180 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:24,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:24,344 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:24,398 INFO L85 PathProgramCache]: Analyzing trace with hash 1964906323, now seen corresponding path program 111 times [2024-05-06 18:09:24,398 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:24,399 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:24,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:24,564 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:24,564 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:24,564 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:24,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:24,730 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:24,974 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:09:24,974 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:09:27,929 INFO L85 PathProgramCache]: Analyzing trace with hash -1510601010, now seen corresponding path program 112 times [2024-05-06 18:09:27,929 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:27,929 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:27,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:28,102 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:28,102 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:28,103 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:28,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:28,277 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:28,333 INFO L85 PathProgramCache]: Analyzing trace with hash 416009970, now seen corresponding path program 113 times [2024-05-06 18:09:28,333 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:28,333 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:28,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:28,510 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:09:28,510 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:28,510 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:28,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:28,816 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:09:28,875 INFO L85 PathProgramCache]: Analyzing trace with hash 11408214, now seen corresponding path program 114 times [2024-05-06 18:09:28,875 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:28,875 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:28,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:29,064 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:29,064 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:29,064 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:29,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:29,252 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:29,312 INFO L85 PathProgramCache]: Analyzing trace with hash 11408214, now seen corresponding path program 115 times [2024-05-06 18:09:29,312 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:29,312 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:29,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:29,497 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:09:29,497 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:29,497 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:29,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:29,681 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:09:29,741 INFO L85 PathProgramCache]: Analyzing trace with hash 353655668, now seen corresponding path program 116 times [2024-05-06 18:09:29,741 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:29,741 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:29,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:29,925 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:29,925 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:29,925 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:29,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:30,111 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:30,336 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:09:30,336 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:09:36,055 INFO L85 PathProgramCache]: Analyzing trace with hash 617572723, now seen corresponding path program 117 times [2024-05-06 18:09:36,056 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:36,056 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:36,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:36,227 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:36,227 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:36,227 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:36,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:36,400 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:36,453 INFO L85 PathProgramCache]: Analyzing trace with hash 1964886253, now seen corresponding path program 118 times [2024-05-06 18:09:36,454 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:36,454 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:36,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:36,624 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:36,625 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:36,625 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:36,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:36,806 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:36,867 INFO L85 PathProgramCache]: Analyzing trace with hash 781932731, now seen corresponding path program 119 times [2024-05-06 18:09:36,867 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:36,867 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:36,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:37,043 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:37,043 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:37,043 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:37,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:37,217 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:37,274 INFO L85 PathProgramCache]: Analyzing trace with hash 781932731, now seen corresponding path program 120 times [2024-05-06 18:09:37,275 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:37,275 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:37,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:37,455 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:09:37,455 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:37,456 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:37,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:37,635 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:09:37,697 INFO L85 PathProgramCache]: Analyzing trace with hash -1529888081, now seen corresponding path program 121 times [2024-05-06 18:09:37,697 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:37,697 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:37,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:38,007 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:38,007 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:38,007 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:38,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:38,181 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:38,310 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:09:38,310 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:09:38,378 INFO L85 PathProgramCache]: Analyzing trace with hash -535051617, now seen corresponding path program 5 times [2024-05-06 18:09:38,378 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:38,378 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:38,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:38,557 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:38,557 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:38,557 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:38,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:38,733 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:38,855 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:09:38,856 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:09:38,919 INFO L85 PathProgramCache]: Analyzing trace with hash -353522760, now seen corresponding path program 6 times [2024-05-06 18:09:38,919 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:38,919 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:38,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:39,086 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:39,086 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:39,086 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:39,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:39,262 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:39,323 INFO L85 PathProgramCache]: Analyzing trace with hash 1925697334, now seen corresponding path program 7 times [2024-05-06 18:09:39,323 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:39,323 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:39,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:39,493 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:39,493 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:39,493 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:39,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:39,661 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:39,719 INFO L85 PathProgramCache]: Analyzing trace with hash -1363859311, now seen corresponding path program 8 times [2024-05-06 18:09:39,719 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:39,720 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:39,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:40,009 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:40,009 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:40,009 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:40,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:40,176 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:40,236 INFO L85 PathProgramCache]: Analyzing trace with hash 1471890086, now seen corresponding path program 5 times [2024-05-06 18:09:40,236 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:40,236 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:40,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:40,417 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:40,417 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:40,417 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:40,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:40,600 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:40,725 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:09:40,725 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:09:40,785 INFO L85 PathProgramCache]: Analyzing trace with hash 1848596078, now seen corresponding path program 6 times [2024-05-06 18:09:40,785 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:40,785 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:40,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:40,965 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:40,965 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:40,965 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:40,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:41,140 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:41,265 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:09:41,265 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:09:41,328 INFO L85 PathProgramCache]: Analyzing trace with hash -729005495, now seen corresponding path program 7 times [2024-05-06 18:09:41,328 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:41,328 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:41,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:41,494 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:41,494 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:41,494 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:41,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:41,659 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:41,715 INFO L85 PathProgramCache]: Analyzing trace with hash -1124332859, now seen corresponding path program 8 times [2024-05-06 18:09:41,715 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:41,715 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:41,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:41,884 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:41,884 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:41,884 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:41,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:42,188 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:42,250 INFO L85 PathProgramCache]: Analyzing trace with hash 240628855, now seen corresponding path program 5 times [2024-05-06 18:09:42,250 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:42,250 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:42,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:42,423 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:42,423 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:42,423 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:42,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:42,597 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:42,717 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:09:42,718 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:09:42,774 INFO L85 PathProgramCache]: Analyzing trace with hash 977593981, now seen corresponding path program 6 times [2024-05-06 18:09:42,774 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:42,774 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:42,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:42,949 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:42,949 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:42,949 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:42,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:43,128 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:43,254 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:09:43,255 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:09:43,318 INFO L85 PathProgramCache]: Analyzing trace with hash 646202522, now seen corresponding path program 7 times [2024-05-06 18:09:43,319 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:43,319 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:43,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:43,486 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:43,486 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:43,486 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:43,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:43,656 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:43,711 INFO L85 PathProgramCache]: Analyzing trace with hash -1442557292, now seen corresponding path program 8 times [2024-05-06 18:09:43,712 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:43,712 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:43,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:43,891 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:43,892 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:43,892 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:43,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:44,196 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:44,257 INFO L85 PathProgramCache]: Analyzing trace with hash -1757769335, now seen corresponding path program 122 times [2024-05-06 18:09:44,258 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:44,258 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:44,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:44,432 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:44,433 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:44,433 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:44,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:44,607 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:44,734 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:09:44,734 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:09:44,793 INFO L85 PathProgramCache]: Analyzing trace with hash 636034859, now seen corresponding path program 123 times [2024-05-06 18:09:44,793 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:44,793 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:44,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:44,965 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:44,965 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:44,965 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:44,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:45,136 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:45,265 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:09:45,265 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:09:45,326 INFO L85 PathProgramCache]: Analyzing trace with hash -1384875348, now seen corresponding path program 124 times [2024-05-06 18:09:45,327 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:45,327 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:45,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:45,496 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:45,497 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:45,497 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:45,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:45,668 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:45,729 INFO L85 PathProgramCache]: Analyzing trace with hash 18538178, now seen corresponding path program 125 times [2024-05-06 18:09:45,729 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:45,729 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:45,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:45,904 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:45,904 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:45,904 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:45,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:46,078 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:46,477 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:09:46,477 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:09:51,716 INFO L85 PathProgramCache]: Analyzing trace with hash -1814343667, now seen corresponding path program 126 times [2024-05-06 18:09:51,716 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:51,717 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:51,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:51,874 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:51,875 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:51,875 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:51,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:52,033 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:52,093 INFO L85 PathProgramCache]: Analyzing trace with hash -410077797, now seen corresponding path program 127 times [2024-05-06 18:09:52,093 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:52,093 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:52,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:52,255 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:09:52,255 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:52,255 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:52,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:52,419 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:09:52,479 INFO L85 PathProgramCache]: Analyzing trace with hash 172491205, now seen corresponding path program 128 times [2024-05-06 18:09:52,479 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:52,480 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:52,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:52,646 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:52,646 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:52,647 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:52,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:52,808 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:52,867 INFO L85 PathProgramCache]: Analyzing trace with hash 172491205, now seen corresponding path program 129 times [2024-05-06 18:09:52,867 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:52,867 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:52,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:53,033 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:09:53,033 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:53,033 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:53,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:53,326 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:09:53,559 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:09:53,559 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:09:54,291 INFO L85 PathProgramCache]: Analyzing trace with hash 1905910004, now seen corresponding path program 130 times [2024-05-06 18:09:54,291 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:54,291 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:54,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:54,456 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:54,456 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:54,456 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:54,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:54,619 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:54,677 INFO L85 PathProgramCache]: Analyzing trace with hash 1923478764, now seen corresponding path program 131 times [2024-05-06 18:09:54,677 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:54,678 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:54,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:54,848 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:54,848 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:54,848 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:54,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:55,017 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:09:55,231 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:09:55,231 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:09:55,662 INFO L85 PathProgramCache]: Analyzing trace with hash 1627196935, now seen corresponding path program 132 times [2024-05-06 18:09:55,662 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:55,663 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:55,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:55,828 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:55,828 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:55,828 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:55,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:56,122 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:56,253 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:09:56,253 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:09:56,306 INFO L85 PathProgramCache]: Analyzing trace with hash 1627196935, now seen corresponding path program 133 times [2024-05-06 18:09:56,306 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:56,307 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:56,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:56,470 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:56,471 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:56,471 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:56,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:56,635 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:56,760 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:09:56,760 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:09:56,812 INFO L85 PathProgramCache]: Analyzing trace with hash -1096501535, now seen corresponding path program 134 times [2024-05-06 18:09:56,813 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:56,813 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:56,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:56,985 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:56,985 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:56,985 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:57,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:57,162 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:57,215 INFO L85 PathProgramCache]: Analyzing trace with hash 368191807, now seen corresponding path program 135 times [2024-05-06 18:09:57,215 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:57,216 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:57,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:57,390 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:57,390 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:57,390 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:57,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:57,563 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:57,692 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:09:57,692 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:09:57,749 INFO L85 PathProgramCache]: Analyzing trace with hash 368191807, now seen corresponding path program 136 times [2024-05-06 18:09:57,749 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:57,749 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:57,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:57,923 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:57,923 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:57,923 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:57,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:58,215 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:58,343 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:09:58,344 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:09:58,408 INFO L85 PathProgramCache]: Analyzing trace with hash -1470954845, now seen corresponding path program 137 times [2024-05-06 18:09:58,408 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:58,408 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:58,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:58,596 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:58,597 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:58,597 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:58,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:58,853 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:58,909 INFO L85 PathProgramCache]: Analyzing trace with hash 336560042, now seen corresponding path program 138 times [2024-05-06 18:09:58,909 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:58,909 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:58,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:59,108 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:59,108 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:59,108 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:59,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:59,293 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:59,471 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:09:59,472 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:09:59,543 INFO L85 PathProgramCache]: Analyzing trace with hash 1311685997, now seen corresponding path program 139 times [2024-05-06 18:09:59,543 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:59,543 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:59,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:59,727 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:09:59,727 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:09:59,727 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:09:59,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:09:59,911 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:10:00,149 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:10:00,149 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:10:01,420 INFO L85 PathProgramCache]: Analyzing trace with hash 826078638, now seen corresponding path program 140 times [2024-05-06 18:10:01,421 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:01,421 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:01,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:01,624 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:10:01,625 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:01,625 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:01,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:01,830 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:10:01,990 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:10:01,990 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:10:02,050 INFO L85 PathProgramCache]: Analyzing trace with hash -161364974, now seen corresponding path program 141 times [2024-05-06 18:10:02,050 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:02,050 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:02,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:02,241 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:10:02,241 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:02,241 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:02,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:02,436 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:10:02,587 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:10:02,588 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:10:02,652 INFO L85 PathProgramCache]: Analyzing trace with hash -707345872, now seen corresponding path program 142 times [2024-05-06 18:10:02,652 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:02,652 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:02,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:02,847 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:10:02,847 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:02,847 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:02,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:03,042 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:10:03,173 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:10:03,174 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:10:03,227 INFO L85 PathProgramCache]: Analyzing trace with hash -452884520, now seen corresponding path program 143 times [2024-05-06 18:10:03,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:03,229 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:03,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:03,565 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:10:03,565 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:03,565 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:03,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:03,760 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:10:03,883 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:10:03,883 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:10:03,950 INFO L85 PathProgramCache]: Analyzing trace with hash -1615106205, now seen corresponding path program 144 times [2024-05-06 18:10:03,950 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:03,950 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:03,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:04,164 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:10:04,165 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:04,165 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:04,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:04,376 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:10:04,528 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:10:04,529 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:10:04,599 INFO L85 PathProgramCache]: Analyzing trace with hash 1841365586, now seen corresponding path program 145 times [2024-05-06 18:10:04,599 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:04,599 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:04,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:04,816 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 2 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:10:04,817 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:04,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:04,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:05,035 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 2 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:10:05,093 INFO L85 PathProgramCache]: Analyzing trace with hash 1247759333, now seen corresponding path program 146 times [2024-05-06 18:10:05,094 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:05,094 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:05,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:05,308 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:10:05,308 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:05,308 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:05,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:05,662 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:10:05,766 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:10:05,766 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:10:05,815 INFO L85 PathProgramCache]: Analyzing trace with hash 842698666, now seen corresponding path program 147 times [2024-05-06 18:10:05,815 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:05,815 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:05,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:06,091 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:10:06,091 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:06,091 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:06,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:06,332 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:10:06,487 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:10:06,487 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:10:06,551 INFO L85 PathProgramCache]: Analyzing trace with hash 842698654, now seen corresponding path program 148 times [2024-05-06 18:10:06,551 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:06,551 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:06,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:06,806 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:10:06,807 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:06,807 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:06,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:07,060 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:10:07,120 INFO L85 PathProgramCache]: Analyzing trace with hash 353855513, now seen corresponding path program 149 times [2024-05-06 18:10:07,120 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:07,120 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:07,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:07,343 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:10:07,343 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:07,343 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:07,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:07,682 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:10:07,924 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:10:07,924 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:10:08,453 INFO L85 PathProgramCache]: Analyzing trace with hash 1852384370, now seen corresponding path program 150 times [2024-05-06 18:10:08,454 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:08,454 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:08,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:08,680 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:10:08,680 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:08,680 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:08,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:08,907 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:10:08,995 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:10:08,995 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:10:09,035 INFO L85 PathProgramCache]: Analyzing trace with hash 2024952042, now seen corresponding path program 151 times [2024-05-06 18:10:09,036 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:09,036 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:09,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:09,273 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:10:09,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:09,273 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:09,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:09,509 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:10:09,682 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:10:09,682 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:10:10,428 INFO L85 PathProgramCache]: Analyzing trace with hash 358769285, now seen corresponding path program 152 times [2024-05-06 18:10:10,429 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:10,429 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:10,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:10,665 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:10:10,665 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:10,665 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:10,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:10,901 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:10:11,086 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:10:11,086 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:10:11,155 INFO L85 PathProgramCache]: Analyzing trace with hash 358769285, now seen corresponding path program 153 times [2024-05-06 18:10:11,155 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:11,155 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:11,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:11,390 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:10:11,390 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:11,390 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:11,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:11,627 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:10:11,785 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:10:11,785 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:10:11,854 INFO L85 PathProgramCache]: Analyzing trace with hash -1763053021, now seen corresponding path program 154 times [2024-05-06 18:10:11,854 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:11,854 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:11,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:12,097 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:10:12,098 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:12,098 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:12,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:12,445 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:10:12,568 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:10:12,568 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:10:12,633 INFO L85 PathProgramCache]: Analyzing trace with hash 1179932221, now seen corresponding path program 155 times [2024-05-06 18:10:12,633 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:12,633 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:12,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:12,878 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:10:12,879 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:12,879 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:12,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:13,118 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:10:13,275 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:10:13,276 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:10:13,339 INFO L85 PathProgramCache]: Analyzing trace with hash 1179932221, now seen corresponding path program 156 times [2024-05-06 18:10:13,340 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:13,340 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:13,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:13,582 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:10:13,582 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:13,582 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:13,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:13,826 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:10:13,982 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:10:13,983 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:10:14,048 INFO L85 PathProgramCache]: Analyzing trace with hash -2076805787, now seen corresponding path program 157 times [2024-05-06 18:10:14,049 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:14,049 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:14,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:14,405 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:10:14,405 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:14,406 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:14,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:14,642 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:10:14,763 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:10:14,764 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:10:14,826 INFO L85 PathProgramCache]: Analyzing trace with hash 849151578, now seen corresponding path program 158 times [2024-05-06 18:10:14,826 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:14,826 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:14,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:15,079 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:10:15,079 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:15,079 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:15,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:15,329 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:10:15,456 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:10:15,457 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:10:15,518 INFO L85 PathProgramCache]: Analyzing trace with hash 161642973, now seen corresponding path program 159 times [2024-05-06 18:10:15,518 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:15,518 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:15,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:15,775 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:10:15,775 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:15,775 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:15,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:16,038 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:10:16,098 INFO L85 PathProgramCache]: Analyzing trace with hash 715965873, now seen corresponding path program 160 times [2024-05-06 18:10:16,098 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:16,098 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:16,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:16,469 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:10:16,469 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:16,469 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:16,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:16,739 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:10:16,819 INFO L85 PathProgramCache]: Analyzing trace with hash -1116302196, now seen corresponding path program 161 times [2024-05-06 18:10:16,819 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:16,819 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:16,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:17,079 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:10:17,079 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:17,079 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:17,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:17,343 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:10:17,534 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:10:17,534 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:10:19,787 INFO L85 PathProgramCache]: Analyzing trace with hash 1179949090, now seen corresponding path program 3 times [2024-05-06 18:10:19,788 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:19,788 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:19,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:20,142 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:10:20,142 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:20,142 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:20,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:20,400 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:10:20,506 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:10:20,506 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:10:20,557 INFO L85 PathProgramCache]: Analyzing trace with hash 59742362, now seen corresponding path program 4 times [2024-05-06 18:10:20,557 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:20,557 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:20,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:20,811 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:10:20,812 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:20,812 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:20,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:21,059 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:10:21,317 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:10:21,317 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:10:22,292 INFO L85 PathProgramCache]: Analyzing trace with hash -1253665852, now seen corresponding path program 1 times [2024-05-06 18:10:22,292 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:22,292 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:22,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:22,583 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:10:22,583 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:22,583 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:22,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:22,960 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 18:10:22,967 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 2 more)] === [2024-05-06 18:10:22,969 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:10:22,969 INFO L85 PathProgramCache]: Analyzing trace with hash 1620800503, now seen corresponding path program 1 times [2024-05-06 18:10:22,972 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:10:22,972 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1046497153] [2024-05-06 18:10:22,972 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:22,972 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:23,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:23,286 INFO L134 CoverageAnalysis]: Checked inductivity of 459 backedges. 96 proven. 3 refuted. 0 times theorem prover too weak. 360 trivial. 0 not checked. [2024-05-06 18:10:23,286 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:10:23,287 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1046497153] [2024-05-06 18:10:23,287 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1046497153] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:10:23,287 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1048134113] [2024-05-06 18:10:23,287 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:23,287 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:10:23,287 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:10:23,326 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:10:23,329 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2024-05-06 18:10:24,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:24,193 INFO L262 TraceCheckSpWp]: Trace formula consists of 917 conjuncts, 9 conjunts are in the unsatisfiable core [2024-05-06 18:10:24,208 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 18:10:24,414 INFO L134 CoverageAnalysis]: Checked inductivity of 459 backedges. 98 proven. 1 refuted. 0 times theorem prover too weak. 360 trivial. 0 not checked. [2024-05-06 18:10:24,415 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-06 18:10:24,657 INFO L134 CoverageAnalysis]: Checked inductivity of 459 backedges. 96 proven. 3 refuted. 0 times theorem prover too weak. 360 trivial. 0 not checked. [2024-05-06 18:10:24,657 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1048134113] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-06 18:10:24,657 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-06 18:10:24,657 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9] total 19 [2024-05-06 18:10:24,659 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [77728396] [2024-05-06 18:10:24,660 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-06 18:10:24,664 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 19 states [2024-05-06 18:10:24,664 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:10:24,667 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2024-05-06 18:10:24,668 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=77, Invalid=265, Unknown=0, NotChecked=0, Total=342 [2024-05-06 18:10:24,668 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:10:24,669 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:10:24,669 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 19 states, 19 states have (on average 16.210526315789473) internal successors, (308), 19 states have internal predecessors, (308), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:10:24,669 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:10:25,036 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:10:25,037 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:10:25,084 INFO L85 PathProgramCache]: Analyzing trace with hash 1167945965, now seen corresponding path program 3 times [2024-05-06 18:10:25,084 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:25,084 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:25,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:25,693 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:10:25,693 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:25,693 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:25,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:25,958 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 18:10:26,027 INFO L85 PathProgramCache]: Analyzing trace with hash 1846587562, now seen corresponding path program 4 times [2024-05-06 18:10:26,027 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:26,027 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:26,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:26,158 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:10:26,158 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:26,158 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:26,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:26,289 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:10:26,423 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:10:26,424 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:10:26,492 INFO L85 PathProgramCache]: Analyzing trace with hash 219663184, now seen corresponding path program 162 times [2024-05-06 18:10:26,492 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:26,493 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:26,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:26,786 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:10:26,787 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:26,787 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:26,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:26,916 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:10:26,977 INFO L85 PathProgramCache]: Analyzing trace with hash -1780374882, now seen corresponding path program 163 times [2024-05-06 18:10:26,977 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:26,977 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:27,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:27,120 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:10:27,120 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:27,121 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:27,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:27,257 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:10:27,386 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:10:27,386 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:10:27,453 INFO L85 PathProgramCache]: Analyzing trace with hash 2005397127, now seen corresponding path program 164 times [2024-05-06 18:10:27,453 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:27,453 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:27,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:27,613 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2024-05-06 18:10:27,613 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:27,613 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:27,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:27,771 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2024-05-06 18:10:27,829 INFO L85 PathProgramCache]: Analyzing trace with hash 2037769799, now seen corresponding path program 165 times [2024-05-06 18:10:27,829 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:27,829 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:27,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:27,987 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2024-05-06 18:10:27,987 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:27,988 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:28,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:28,146 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2024-05-06 18:10:28,389 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:10:28,389 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 18:10:37,086 WARN L854 $PredicateComparison]: unable to prove that (and (forall ((v_~q1~0.offset_In_88 Int) (v_~q1~0.base_In_88 Int)) (= (select (select |c_#memory_int| v_~q1~0.base_In_88) (+ (* c_~q1_front~0 4) v_~q1~0.offset_In_88)) 0)) (forall ((v_~q2~0.base_In_137 Int) (v_~q2_front~0_In_185 Int) (v_~q2~0.offset_In_137 Int)) (let ((.cse0 (select (select |c_#memory_int| v_~q2~0.base_In_137) (+ (* v_~q2_front~0_In_185 4) v_~q2~0.offset_In_137)))) (or (< v_~q2_front~0_In_185 0) (< (+ .cse0 4294967295) 0) (= .cse0 0) (< 4294967295 .cse0))))) is different from false [2024-05-06 18:10:37,087 INFO L85 PathProgramCache]: Analyzing trace with hash 1653443254, now seen corresponding path program 166 times [2024-05-06 18:10:37,087 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:37,088 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:37,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:37,266 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:10:37,266 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:37,266 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:37,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:37,446 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:10:37,512 INFO L85 PathProgramCache]: Analyzing trace with hash -1791668603, now seen corresponding path program 167 times [2024-05-06 18:10:37,513 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:37,513 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:37,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:37,704 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 18:10:37,704 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:37,704 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:37,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:37,893 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 18:10:38,014 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:10:38,015 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:10:38,084 INFO L85 PathProgramCache]: Analyzing trace with hash 1466225327, now seen corresponding path program 168 times [2024-05-06 18:10:38,084 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:38,084 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:38,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:38,266 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 18:10:38,266 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:38,266 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:38,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:38,449 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 18:10:38,580 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:10:38,580 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:10:38,648 INFO L85 PathProgramCache]: Analyzing trace with hash -546499160, now seen corresponding path program 169 times [2024-05-06 18:10:38,649 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:38,649 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:38,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:38,936 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:10:38,936 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:38,936 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:38,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:39,114 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:10:39,253 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:10:39,253 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:10:39,318 INFO L85 PathProgramCache]: Analyzing trace with hash 514466012, now seen corresponding path program 170 times [2024-05-06 18:10:39,318 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:39,318 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:39,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:39,489 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:10:39,490 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:39,490 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:39,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:39,664 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:10:39,794 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:10:39,795 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:10:39,864 INFO L85 PathProgramCache]: Analyzing trace with hash -1497107874, now seen corresponding path program 9 times [2024-05-06 18:10:39,864 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:39,864 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:39,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:40,040 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 18:10:40,040 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:40,040 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:40,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:40,215 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 18:10:40,344 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:10:40,345 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:10:40,409 INFO L85 PathProgramCache]: Analyzing trace with hash -655446951, now seen corresponding path program 10 times [2024-05-06 18:10:40,410 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:40,410 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:40,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:40,575 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:10:40,575 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:40,575 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:40,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:40,859 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:10:40,994 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:10:40,994 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:10:41,063 INFO L85 PathProgramCache]: Analyzing trace with hash -537742641, now seen corresponding path program 9 times [2024-05-06 18:10:41,063 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:41,063 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:41,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:41,232 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 18:10:41,232 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:41,232 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:41,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:41,401 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 18:10:41,526 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:10:41,527 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:10:41,590 INFO L85 PathProgramCache]: Analyzing trace with hash 369633672, now seen corresponding path program 10 times [2024-05-06 18:10:41,591 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:41,591 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:41,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:41,755 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:10:41,755 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:41,755 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:41,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:41,920 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:10:42,051 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:10:42,051 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:10:42,113 INFO L85 PathProgramCache]: Analyzing trace with hash 207878652, now seen corresponding path program 9 times [2024-05-06 18:10:42,113 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:42,113 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:42,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:42,281 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 18:10:42,282 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:42,282 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:42,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:42,450 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 18:10:42,678 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:10:42,678 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:10:42,731 INFO L85 PathProgramCache]: Analyzing trace with hash 543095163, now seen corresponding path program 10 times [2024-05-06 18:10:42,731 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:42,731 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:42,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:42,904 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:10:42,905 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:42,905 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:42,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:43,081 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:10:43,206 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:10:43,206 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:10:43,256 INFO L85 PathProgramCache]: Analyzing trace with hash 334110668, now seen corresponding path program 171 times [2024-05-06 18:10:43,256 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:43,256 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:43,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:43,435 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 18:10:43,435 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:43,435 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:43,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:43,617 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 18:10:43,738 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:10:43,738 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:10:43,789 INFO L85 PathProgramCache]: Analyzing trace with hash 1659839915, now seen corresponding path program 172 times [2024-05-06 18:10:43,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:43,789 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:43,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:43,956 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:10:43,956 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:43,956 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:43,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:44,123 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 18:10:44,270 INFO L349 Elim1Store]: treesize reduction 18, result has 5.3 percent of original size [2024-05-06 18:10:44,271 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 20 treesize of output 4 [2024-05-06 18:10:44,339 INFO L85 PathProgramCache]: Analyzing trace with hash -1024256772, now seen corresponding path program 173 times [2024-05-06 18:10:44,339 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:44,339 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:44,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:44,606 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2024-05-06 18:10:44,606 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:44,606 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:44,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:44,766 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2024-05-06 18:10:44,855 INFO L85 PathProgramCache]: Analyzing trace with hash 368549282, now seen corresponding path program 174 times [2024-05-06 18:10:44,855 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:44,855 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:44,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:44,993 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:10:44,994 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:44,994 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:45,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:45,131 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 18:10:45,194 INFO L85 PathProgramCache]: Analyzing trace with hash -1842315376, now seen corresponding path program 175 times [2024-05-06 18:10:45,194 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:45,194 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:45,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:45,364 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2024-05-06 18:10:45,364 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:45,364 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:45,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:45,534 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2024-05-06 18:10:45,722 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:10:45,722 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:10:45,787 INFO L85 PathProgramCache]: Analyzing trace with hash -1382179796, now seen corresponding path program 176 times [2024-05-06 18:10:45,787 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:45,788 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:45,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:45,977 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2024-05-06 18:10:45,977 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:45,977 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:46,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:46,284 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2024-05-06 18:10:46,414 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 18:10:46,415 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 31 [2024-05-06 18:10:46,474 INFO L85 PathProgramCache]: Analyzing trace with hash 102100316, now seen corresponding path program 177 times [2024-05-06 18:10:46,474 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:46,474 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:46,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:46,673 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2024-05-06 18:10:46,673 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:46,673 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:46,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:46,868 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2024-05-06 18:10:47,031 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:10:47,032 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:10:47,100 INFO L85 PathProgramCache]: Analyzing trace with hash -1878004357, now seen corresponding path program 178 times [2024-05-06 18:10:47,101 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:47,101 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:47,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:47,283 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2024-05-06 18:10:47,284 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:47,284 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:47,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:47,466 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2024-05-06 18:10:47,656 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:10:47,657 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:10:47,739 INFO L85 PathProgramCache]: Analyzing trace with hash 1500269626, now seen corresponding path program 179 times [2024-05-06 18:10:47,739 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:47,739 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:47,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:47,913 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2024-05-06 18:10:47,914 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:47,914 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:47,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:48,188 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2024-05-06 18:10:48,384 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:10:48,384 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:10:48,452 INFO L85 PathProgramCache]: Analyzing trace with hash 1289218093, now seen corresponding path program 180 times [2024-05-06 18:10:48,453 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:48,453 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:48,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:48,623 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2024-05-06 18:10:48,624 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:48,624 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:48,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:48,795 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2024-05-06 18:10:48,979 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:10:48,980 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:10:49,057 INFO L85 PathProgramCache]: Analyzing trace with hash -827297971, now seen corresponding path program 7 times [2024-05-06 18:10:49,058 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:49,058 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:49,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:49,256 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2024-05-06 18:10:49,257 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:49,257 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:49,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:49,454 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2024-05-06 18:10:49,637 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:10:49,637 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:10:49,717 INFO L85 PathProgramCache]: Analyzing trace with hash -879897094, now seen corresponding path program 8 times [2024-05-06 18:10:49,717 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:49,717 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:49,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:49,912 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2024-05-06 18:10:49,912 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:49,912 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:49,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:50,208 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2024-05-06 18:10:50,392 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:10:50,393 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:10:50,465 INFO L85 PathProgramCache]: Analyzing trace with hash -1034609804, now seen corresponding path program 7 times [2024-05-06 18:10:50,465 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:50,465 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:50,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:50,660 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2024-05-06 18:10:50,661 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:50,661 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:50,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:50,859 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2024-05-06 18:10:51,039 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:10:51,040 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:10:51,120 INFO L85 PathProgramCache]: Analyzing trace with hash -491654349, now seen corresponding path program 8 times [2024-05-06 18:10:51,120 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:51,120 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:51,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:51,310 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2024-05-06 18:10:51,310 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:51,311 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:51,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:51,504 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2024-05-06 18:10:51,681 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:10:51,681 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:10:51,738 INFO L85 PathProgramCache]: Analyzing trace with hash -1988513621, now seen corresponding path program 7 times [2024-05-06 18:10:51,738 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:51,738 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:51,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:52,052 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2024-05-06 18:10:52,052 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:52,052 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:52,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:52,257 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2024-05-06 18:10:52,418 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:10:52,418 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:10:52,492 INFO L85 PathProgramCache]: Analyzing trace with hash 741687644, now seen corresponding path program 8 times [2024-05-06 18:10:52,493 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:52,493 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:52,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:52,701 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2024-05-06 18:10:52,702 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:52,702 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:52,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:52,903 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2024-05-06 18:10:53,105 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:10:53,105 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:10:53,186 INFO L85 PathProgramCache]: Analyzing trace with hash 1547594737, now seen corresponding path program 181 times [2024-05-06 18:10:53,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:53,186 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:53,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:53,415 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2024-05-06 18:10:53,415 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:53,415 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:53,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:53,631 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2024-05-06 18:10:53,824 INFO L349 Elim1Store]: treesize reduction 23, result has 51.1 percent of original size [2024-05-06 18:10:53,825 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 63 treesize of output 46 [2024-05-06 18:10:53,909 INFO L85 PathProgramCache]: Analyzing trace with hash 673037270, now seen corresponding path program 182 times [2024-05-06 18:10:53,910 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:53,910 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:54,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:54,207 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2024-05-06 18:10:54,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:54,208 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:54,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:54,408 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2024-05-06 18:10:54,521 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:10:54,531 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Ended with exit code 0 [2024-05-06 18:10:54,731 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable591,SelfDestructingSolverStorable592,SelfDestructingSolverStorable593,SelfDestructingSolverStorable550,SelfDestructingSolverStorable594,SelfDestructingSolverStorable590,SelfDestructingSolverStorable548,SelfDestructingSolverStorable549,SelfDestructingSolverStorable544,SelfDestructingSolverStorable588,SelfDestructingSolverStorable545,SelfDestructingSolverStorable589,SelfDestructingSolverStorable546,SelfDestructingSolverStorable547,SelfDestructingSolverStorable540,SelfDestructingSolverStorable584,SelfDestructingSolverStorable541,SelfDestructingSolverStorable585,SelfDestructingSolverStorable542,SelfDestructingSolverStorable586,SelfDestructingSolverStorable543,SelfDestructingSolverStorable587,SelfDestructingSolverStorable580,SelfDestructingSolverStorable581,SelfDestructingSolverStorable582,SelfDestructingSolverStorable583,SelfDestructingSolverStorable537,SelfDestructingSolverStorable538,SelfDestructingSolverStorable539,SelfDestructingSolverStorable533,SelfDestructingSolverStorable577,SelfDestructingSolverStorable534,SelfDestructingSolverStorable578,SelfDestructingSolverStorable535,SelfDestructingSolverStorable579,SelfDestructingSolverStorable536,SelfDestructingSolverStorable573,SelfDestructingSolverStorable530,SelfDestructingSolverStorable574,SelfDestructingSolverStorable531,SelfDestructingSolverStorable575,SelfDestructingSolverStorable532,SelfDestructingSolverStorable576,SelfDestructingSolverStorable570,SelfDestructingSolverStorable571,SelfDestructingSolverStorable572,SelfDestructingSolverStorable566,SelfDestructingSolverStorable567,SelfDestructingSolverStorable600,SelfDestructingSolverStorable568,SelfDestructingSolverStorable569,SelfDestructingSolverStorable562,SelfDestructingSolverStorable563,SelfDestructingSolverStorable564,SelfDestructingSolverStorable565,3 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable560,SelfDestructingSolverStorable561,SelfDestructingSolverStorable559,SelfDestructingSolverStorable555,SelfDestructingSolverStorable599,SelfDestructingSolverStorable556,SelfDestructingSolverStorable557,SelfDestructingSolverStorable558,SelfDestructingSolverStorable551,SelfDestructingSolverStorable595,SelfDestructingSolverStorable552,SelfDestructingSolverStorable596,SelfDestructingSolverStorable553,SelfDestructingSolverStorable597,SelfDestructingSolverStorable554,SelfDestructingSolverStorable598 [2024-05-06 18:10:54,731 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 2 more)] === [2024-05-06 18:10:54,731 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:10:54,732 INFO L85 PathProgramCache]: Analyzing trace with hash -558622326, now seen corresponding path program 2 times [2024-05-06 18:10:54,732 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:10:54,732 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1014419245] [2024-05-06 18:10:54,732 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:54,732 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:54,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:10:55,069 INFO L134 CoverageAnalysis]: Checked inductivity of 468 backedges. 235 proven. 86 refuted. 0 times theorem prover too weak. 147 trivial. 0 not checked. [2024-05-06 18:10:55,069 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:10:55,070 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1014419245] [2024-05-06 18:10:55,070 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1014419245] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:10:55,070 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [381746202] [2024-05-06 18:10:55,070 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-05-06 18:10:55,070 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:10:55,070 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:10:55,071 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:10:55,073 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2024-05-06 18:10:56,041 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-05-06 18:10:56,041 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-05-06 18:10:56,045 INFO L262 TraceCheckSpWp]: Trace formula consists of 931 conjuncts, 16 conjunts are in the unsatisfiable core [2024-05-06 18:10:56,050 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 18:10:56,595 INFO L134 CoverageAnalysis]: Checked inductivity of 468 backedges. 278 proven. 33 refuted. 0 times theorem prover too weak. 157 trivial. 0 not checked. [2024-05-06 18:10:56,596 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-06 18:10:57,144 INFO L134 CoverageAnalysis]: Checked inductivity of 468 backedges. 49 proven. 262 refuted. 0 times theorem prover too weak. 157 trivial. 0 not checked. [2024-05-06 18:10:57,144 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [381746202] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-06 18:10:57,144 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-06 18:10:57,144 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 15, 15] total 35 [2024-05-06 18:10:57,144 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1803998444] [2024-05-06 18:10:57,145 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-06 18:10:57,145 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 35 states [2024-05-06 18:10:57,146 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:10:57,146 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2024-05-06 18:10:57,147 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=194, Invalid=996, Unknown=0, NotChecked=0, Total=1190 [2024-05-06 18:10:57,147 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:10:57,147 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:10:57,147 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 35 states, 35 states have (on average 18.771428571428572) internal successors, (657), 35 states have internal predecessors, (657), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:10:57,147 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:10:57,147 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:10:59,541 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:10:59,541 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:10:59,567 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2024-05-06 18:10:59,741 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable601 [2024-05-06 18:10:59,742 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 2 more)] === [2024-05-06 18:10:59,742 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:10:59,742 INFO L85 PathProgramCache]: Analyzing trace with hash 935272368, now seen corresponding path program 3 times [2024-05-06 18:10:59,742 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:10:59,742 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1936111977] [2024-05-06 18:10:59,742 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:10:59,743 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:10:59,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:11:00,464 INFO L134 CoverageAnalysis]: Checked inductivity of 529 backedges. 266 proven. 226 refuted. 0 times theorem prover too weak. 37 trivial. 0 not checked. [2024-05-06 18:11:00,465 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:11:00,465 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1936111977] [2024-05-06 18:11:00,465 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1936111977] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:11:00,465 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2026920959] [2024-05-06 18:11:00,465 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-05-06 18:11:00,465 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:11:00,465 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:11:00,466 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:11:00,468 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2024-05-06 18:11:01,371 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2024-05-06 18:11:01,372 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-05-06 18:11:01,374 INFO L262 TraceCheckSpWp]: Trace formula consists of 558 conjuncts, 17 conjunts are in the unsatisfiable core [2024-05-06 18:11:01,378 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 18:11:01,803 INFO L134 CoverageAnalysis]: Checked inductivity of 529 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 523 trivial. 0 not checked. [2024-05-06 18:11:01,803 INFO L323 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-05-06 18:11:01,803 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2026920959] provided 1 perfect and 0 imperfect interpolant sequences [2024-05-06 18:11:01,803 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-05-06 18:11:01,804 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [22] total 28 [2024-05-06 18:11:01,806 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [568332882] [2024-05-06 18:11:01,806 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-05-06 18:11:01,806 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-05-06 18:11:01,806 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:11:01,807 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-05-06 18:11:01,807 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=95, Invalid=661, Unknown=0, NotChecked=0, Total=756 [2024-05-06 18:11:01,807 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:11:01,807 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:11:01,807 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 28.375) internal successors, (227), 8 states have internal predecessors, (227), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:11:01,807 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:11:01,807 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:11:01,807 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:11:02,555 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:11:02,555 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:11:02,555 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:11:02,564 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Ended with exit code 0 [2024-05-06 18:11:02,764 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable602,5 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:11:02,765 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 2 more)] === [2024-05-06 18:11:02,765 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:11:02,765 INFO L85 PathProgramCache]: Analyzing trace with hash 1968765268, now seen corresponding path program 1 times [2024-05-06 18:11:02,765 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:11:02,765 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [107725294] [2024-05-06 18:11:02,765 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:11:02,765 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:11:02,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:11:03,468 INFO L134 CoverageAnalysis]: Checked inductivity of 530 backedges. 266 proven. 226 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2024-05-06 18:11:03,468 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:11:03,468 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [107725294] [2024-05-06 18:11:03,468 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [107725294] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:11:03,468 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [294208277] [2024-05-06 18:11:03,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:11:03,468 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:11:03,468 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:11:03,481 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:11:03,482 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2024-05-06 18:11:04,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:11:04,397 INFO L262 TraceCheckSpWp]: Trace formula consists of 977 conjuncts, 12 conjunts are in the unsatisfiable core [2024-05-06 18:11:04,400 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 18:11:04,935 INFO L134 CoverageAnalysis]: Checked inductivity of 530 backedges. 184 proven. 10 refuted. 0 times theorem prover too weak. 336 trivial. 0 not checked. [2024-05-06 18:11:04,935 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-06 18:11:05,278 INFO L134 CoverageAnalysis]: Checked inductivity of 530 backedges. 162 proven. 32 refuted. 0 times theorem prover too weak. 336 trivial. 0 not checked. [2024-05-06 18:11:05,278 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [294208277] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-06 18:11:05,278 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-06 18:11:05,279 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 12, 12] total 41 [2024-05-06 18:11:05,279 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1477311088] [2024-05-06 18:11:05,279 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-06 18:11:05,280 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 41 states [2024-05-06 18:11:05,280 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:11:05,281 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2024-05-06 18:11:05,282 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=172, Invalid=1468, Unknown=0, NotChecked=0, Total=1640 [2024-05-06 18:11:05,282 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:11:05,282 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:11:05,282 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 41 states, 41 states have (on average 14.317073170731707) internal successors, (587), 41 states have internal predecessors, (587), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:11:05,282 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:11:05,282 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:11:05,282 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:11:05,282 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:11:07,206 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:11:07,207 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:11:07,207 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:11:07,207 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:11:07,226 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Forceful destruction successful, exit code 0 [2024-05-06 18:11:07,416 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable603 [2024-05-06 18:11:07,416 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 2 more)] === [2024-05-06 18:11:07,417 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:11:07,417 INFO L85 PathProgramCache]: Analyzing trace with hash 1987518007, now seen corresponding path program 2 times [2024-05-06 18:11:07,417 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:11:07,417 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [327781793] [2024-05-06 18:11:07,417 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:11:07,417 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:11:07,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:11:08,280 INFO L134 CoverageAnalysis]: Checked inductivity of 588 backedges. 266 proven. 267 refuted. 0 times theorem prover too weak. 55 trivial. 0 not checked. [2024-05-06 18:11:08,281 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:11:08,281 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [327781793] [2024-05-06 18:11:08,281 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [327781793] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:11:08,281 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2053350524] [2024-05-06 18:11:08,281 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-05-06 18:11:08,281 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:11:08,281 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:11:08,282 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:11:08,284 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2024-05-06 18:11:09,217 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-05-06 18:11:09,217 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-05-06 18:11:09,220 INFO L262 TraceCheckSpWp]: Trace formula consists of 1005 conjuncts, 15 conjunts are in the unsatisfiable core [2024-05-06 18:11:09,230 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 18:11:09,716 INFO L134 CoverageAnalysis]: Checked inductivity of 588 backedges. 246 proven. 27 refuted. 0 times theorem prover too weak. 315 trivial. 0 not checked. [2024-05-06 18:11:09,716 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-06 18:11:10,185 INFO L134 CoverageAnalysis]: Checked inductivity of 588 backedges. 208 proven. 65 refuted. 0 times theorem prover too weak. 315 trivial. 0 not checked. [2024-05-06 18:11:10,185 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2053350524] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-06 18:11:10,185 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-06 18:11:10,185 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 15, 15] total 49 [2024-05-06 18:11:10,186 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [626667566] [2024-05-06 18:11:10,186 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-06 18:11:10,187 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 49 states [2024-05-06 18:11:10,187 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:11:10,188 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2024-05-06 18:11:10,188 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=242, Invalid=2110, Unknown=0, NotChecked=0, Total=2352 [2024-05-06 18:11:10,188 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:11:10,188 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:11:10,189 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 49 states, 49 states have (on average 12.959183673469388) internal successors, (635), 49 states have internal predecessors, (635), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:11:10,189 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:11:10,190 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:11:10,190 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:11:10,190 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:11:10,190 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:11:12,469 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:11:12,469 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:11:12,469 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:11:12,469 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:11:12,469 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:11:12,479 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Ended with exit code 0 [2024-05-06 18:11:12,674 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable604,7 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:11:12,674 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 2 more)] === [2024-05-06 18:11:12,675 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:11:12,675 INFO L85 PathProgramCache]: Analyzing trace with hash 1539975706, now seen corresponding path program 3 times [2024-05-06 18:11:12,675 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:11:12,675 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1662723968] [2024-05-06 18:11:12,675 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:11:12,675 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:11:12,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:11:13,031 INFO L134 CoverageAnalysis]: Checked inductivity of 662 backedges. 283 proven. 39 refuted. 0 times theorem prover too weak. 340 trivial. 0 not checked. [2024-05-06 18:11:13,032 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:11:13,032 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1662723968] [2024-05-06 18:11:13,032 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1662723968] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:11:13,032 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [398444598] [2024-05-06 18:11:13,032 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-05-06 18:11:13,032 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:11:13,032 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:11:13,035 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:11:13,035 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2024-05-06 18:11:14,076 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2024-05-06 18:11:14,076 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-05-06 18:11:14,080 INFO L262 TraceCheckSpWp]: Trace formula consists of 805 conjuncts, 20 conjunts are in the unsatisfiable core [2024-05-06 18:11:14,084 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 18:11:14,623 INFO L134 CoverageAnalysis]: Checked inductivity of 662 backedges. 270 proven. 52 refuted. 0 times theorem prover too weak. 340 trivial. 0 not checked. [2024-05-06 18:11:14,624 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-06 18:11:15,229 INFO L134 CoverageAnalysis]: Checked inductivity of 662 backedges. 41 proven. 281 refuted. 0 times theorem prover too weak. 340 trivial. 0 not checked. [2024-05-06 18:11:15,230 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [398444598] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-06 18:11:15,230 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-06 18:11:15,230 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 19, 19] total 38 [2024-05-06 18:11:15,230 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1046917930] [2024-05-06 18:11:15,230 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-06 18:11:15,231 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 38 states [2024-05-06 18:11:15,231 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:11:15,232 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2024-05-06 18:11:15,232 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=254, Invalid=1152, Unknown=0, NotChecked=0, Total=1406 [2024-05-06 18:11:15,232 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:11:15,232 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:11:15,232 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 38 states, 38 states have (on average 15.736842105263158) internal successors, (598), 38 states have internal predecessors, (598), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:11:15,232 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:11:15,232 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:11:15,232 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:11:15,233 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:11:15,233 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:11:15,233 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:11:17,219 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:11:17,220 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:11:17,220 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:11:17,220 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:11:17,220 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:11:17,220 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:11:17,230 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Forceful destruction successful, exit code 0 [2024-05-06 18:11:17,428 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable605 [2024-05-06 18:11:17,429 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 2 more)] === [2024-05-06 18:11:17,429 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:11:17,430 INFO L85 PathProgramCache]: Analyzing trace with hash -1795479172, now seen corresponding path program 4 times [2024-05-06 18:11:17,430 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:11:17,430 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1716507329] [2024-05-06 18:11:17,430 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:11:17,430 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:11:17,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:11:18,567 INFO L134 CoverageAnalysis]: Checked inductivity of 1145 backedges. 405 proven. 533 refuted. 0 times theorem prover too weak. 207 trivial. 0 not checked. [2024-05-06 18:11:18,567 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:11:18,567 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1716507329] [2024-05-06 18:11:18,567 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1716507329] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:11:18,567 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1068095282] [2024-05-06 18:11:18,567 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-05-06 18:11:18,567 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:11:18,568 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:11:18,569 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:11:18,571 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2024-05-06 18:11:19,601 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-05-06 18:11:19,601 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-05-06 18:11:19,606 INFO L262 TraceCheckSpWp]: Trace formula consists of 1220 conjuncts, 4 conjunts are in the unsatisfiable core [2024-05-06 18:11:19,611 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 18:11:19,936 INFO L134 CoverageAnalysis]: Checked inductivity of 1145 backedges. 243 proven. 0 refuted. 0 times theorem prover too weak. 902 trivial. 0 not checked. [2024-05-06 18:11:19,936 INFO L323 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-05-06 18:11:19,936 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1068095282] provided 1 perfect and 0 imperfect interpolant sequences [2024-05-06 18:11:19,936 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-05-06 18:11:19,936 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [27] total 29 [2024-05-06 18:11:19,936 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [725391292] [2024-05-06 18:11:19,936 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-05-06 18:11:19,937 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-05-06 18:11:19,937 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:11:19,937 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-05-06 18:11:19,937 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=118, Invalid=694, Unknown=0, NotChecked=0, Total=812 [2024-05-06 18:11:19,937 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:11:19,938 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:11:19,938 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 63.25) internal successors, (253), 4 states have internal predecessors, (253), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:11:19,938 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:11:19,938 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:11:19,938 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:11:19,938 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:11:19,938 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:11:19,938 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:11:19,938 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:11:20,206 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:11:20,207 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:11:20,207 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:11:20,207 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:11:20,207 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:11:20,207 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:11:20,207 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-05-06 18:11:20,217 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Forceful destruction successful, exit code 0 [2024-05-06 18:11:20,410 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable606,9 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:11:20,413 INFO L420 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 2 more)] === [2024-05-06 18:11:20,413 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:11:20,413 INFO L85 PathProgramCache]: Analyzing trace with hash -395260068, now seen corresponding path program 5 times [2024-05-06 18:11:20,414 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:11:20,414 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1489765101] [2024-05-06 18:11:20,414 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:11:20,414 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:11:20,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:11:20,874 INFO L134 CoverageAnalysis]: Checked inductivity of 343 backedges. 35 proven. 2 refuted. 0 times theorem prover too weak. 306 trivial. 0 not checked. [2024-05-06 18:11:20,875 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:11:20,875 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1489765101] [2024-05-06 18:11:20,875 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1489765101] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:11:20,875 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [429537372] [2024-05-06 18:11:20,875 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-05-06 18:11:20,875 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:11:20,875 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:11:20,876 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:11:20,893 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2024-05-06 18:11:21,931 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 8 check-sat command(s) [2024-05-06 18:11:21,931 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-05-06 18:11:21,935 INFO L262 TraceCheckSpWp]: Trace formula consists of 795 conjuncts, 20 conjunts are in the unsatisfiable core [2024-05-06 18:11:21,939 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 18:11:23,215 INFO L134 CoverageAnalysis]: Checked inductivity of 343 backedges. 47 proven. 12 refuted. 0 times theorem prover too weak. 284 trivial. 0 not checked. [2024-05-06 18:11:23,216 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-06 18:11:23,653 INFO L134 CoverageAnalysis]: Checked inductivity of 343 backedges. 47 proven. 12 refuted. 0 times theorem prover too weak. 284 trivial. 0 not checked. [2024-05-06 18:11:23,654 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [429537372] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-06 18:11:23,654 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-06 18:11:23,654 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 19, 16] total 42 [2024-05-06 18:11:23,654 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [460823482] [2024-05-06 18:11:23,654 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-06 18:11:23,655 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 42 states [2024-05-06 18:11:23,655 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:11:23,655 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2024-05-06 18:11:23,656 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=324, Invalid=1398, Unknown=0, NotChecked=0, Total=1722 [2024-05-06 18:11:23,656 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:11:23,656 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:11:23,656 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 42 states, 42 states have (on average 15.523809523809524) internal successors, (652), 42 states have internal predecessors, (652), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:11:23,656 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:11:23,657 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:11:23,657 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:11:23,657 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:11:23,657 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:11:23,657 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:11:23,657 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 4 states. [2024-05-06 18:11:23,657 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:11:24,647 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:11:24,648 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:11:24,648 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:11:24,648 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:11:24,648 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:11:24,648 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:11:24,648 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-05-06 18:11:24,648 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2024-05-06 18:11:24,660 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Forceful destruction successful, exit code 0 [2024-05-06 18:11:24,858 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable607,10 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:11:24,858 INFO L420 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 2 more)] === [2024-05-06 18:11:24,859 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:11:24,859 INFO L85 PathProgramCache]: Analyzing trace with hash 1726711572, now seen corresponding path program 6 times [2024-05-06 18:11:24,859 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:11:24,859 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1740733612] [2024-05-06 18:11:24,859 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:11:24,859 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:11:24,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:11:25,319 INFO L134 CoverageAnalysis]: Checked inductivity of 369 backedges. 42 proven. 30 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2024-05-06 18:11:25,319 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:11:25,319 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1740733612] [2024-05-06 18:11:25,320 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1740733612] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:11:25,320 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [285703470] [2024-05-06 18:11:25,320 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-05-06 18:11:25,320 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:11:25,320 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:11:25,321 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:11:25,344 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2024-05-06 18:11:26,582 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2024-05-06 18:11:26,582 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-05-06 18:11:26,586 INFO L262 TraceCheckSpWp]: Trace formula consists of 823 conjuncts, 25 conjunts are in the unsatisfiable core [2024-05-06 18:11:26,590 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 18:11:27,247 INFO L134 CoverageAnalysis]: Checked inductivity of 369 backedges. 71 proven. 31 refuted. 0 times theorem prover too weak. 267 trivial. 0 not checked. [2024-05-06 18:11:27,247 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-06 18:11:28,061 INFO L134 CoverageAnalysis]: Checked inductivity of 369 backedges. 55 proven. 53 refuted. 0 times theorem prover too weak. 261 trivial. 0 not checked. [2024-05-06 18:11:28,061 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [285703470] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-06 18:11:28,061 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-06 18:11:28,061 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 18, 22] total 50 [2024-05-06 18:11:28,062 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1127996844] [2024-05-06 18:11:28,062 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-06 18:11:28,062 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 50 states [2024-05-06 18:11:28,062 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:11:28,063 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2024-05-06 18:11:28,064 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=328, Invalid=2122, Unknown=0, NotChecked=0, Total=2450 [2024-05-06 18:11:28,064 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:11:28,064 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:11:28,064 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 50 states, 50 states have (on average 14.74) internal successors, (737), 50 states have internal predecessors, (737), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:11:28,064 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:11:28,064 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:11:28,064 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:11:28,065 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:11:28,065 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:11:28,065 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:11:28,065 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 4 states. [2024-05-06 18:11:28,065 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 29 states. [2024-05-06 18:11:28,065 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:11:32,413 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:11:32,413 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:11:32,413 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:11:32,413 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:11:32,414 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:11:32,414 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:11:32,414 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-05-06 18:11:32,414 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2024-05-06 18:11:32,414 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2024-05-06 18:11:32,424 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Ended with exit code 0 [2024-05-06 18:11:32,624 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable608 [2024-05-06 18:11:32,624 INFO L420 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 2 more)] === [2024-05-06 18:11:32,624 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:11:32,624 INFO L85 PathProgramCache]: Analyzing trace with hash 503514965, now seen corresponding path program 7 times [2024-05-06 18:11:32,625 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:11:32,625 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2051125892] [2024-05-06 18:11:32,625 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:11:32,625 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:11:32,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:11:34,356 INFO L134 CoverageAnalysis]: Checked inductivity of 2861 backedges. 1313 proven. 374 refuted. 0 times theorem prover too weak. 1174 trivial. 0 not checked. [2024-05-06 18:11:34,357 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:11:34,357 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2051125892] [2024-05-06 18:11:34,357 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2051125892] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:11:34,357 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [713375638] [2024-05-06 18:11:34,357 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-05-06 18:11:34,357 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:11:34,357 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:11:34,358 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:11:34,360 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2024-05-06 18:11:35,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:11:35,431 INFO L262 TraceCheckSpWp]: Trace formula consists of 1654 conjuncts, 21 conjunts are in the unsatisfiable core [2024-05-06 18:11:35,436 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 18:11:36,271 INFO L134 CoverageAnalysis]: Checked inductivity of 2861 backedges. 1269 proven. 85 refuted. 0 times theorem prover too weak. 1507 trivial. 0 not checked. [2024-05-06 18:11:36,272 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-06 18:11:37,146 INFO L134 CoverageAnalysis]: Checked inductivity of 2861 backedges. 1183 proven. 171 refuted. 0 times theorem prover too weak. 1507 trivial. 0 not checked. [2024-05-06 18:11:37,146 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [713375638] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-06 18:11:37,146 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-06 18:11:37,146 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 21, 21] total 64 [2024-05-06 18:11:37,146 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1908160741] [2024-05-06 18:11:37,147 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-06 18:11:37,147 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 64 states [2024-05-06 18:11:37,147 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:11:37,148 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 64 interpolants. [2024-05-06 18:11:37,149 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=409, Invalid=3623, Unknown=0, NotChecked=0, Total=4032 [2024-05-06 18:11:37,149 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:11:37,149 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:11:37,150 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 64 states, 64 states have (on average 11.671875) internal successors, (747), 64 states have internal predecessors, (747), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:11:37,150 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:11:37,150 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:11:37,150 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:11:37,150 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:11:37,150 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:11:37,150 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:11:37,150 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 4 states. [2024-05-06 18:11:37,150 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 29 states. [2024-05-06 18:11:37,150 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 58 states. [2024-05-06 18:11:37,150 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:11:40,810 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:11:40,810 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:11:40,810 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:11:40,810 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:11:40,810 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:11:40,810 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:11:40,810 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-05-06 18:11:40,811 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2024-05-06 18:11:40,811 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2024-05-06 18:11:40,811 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2024-05-06 18:11:40,822 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Ended with exit code 0 [2024-05-06 18:11:41,012 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable609,12 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:11:41,012 INFO L420 AbstractCegarLoop]: === Iteration 11 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 2 more)] === [2024-05-06 18:11:41,013 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:11:41,013 INFO L85 PathProgramCache]: Analyzing trace with hash 979776082, now seen corresponding path program 8 times [2024-05-06 18:11:41,013 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:11:41,013 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [742556786] [2024-05-06 18:11:41,013 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:11:41,013 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:11:41,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:11:42,869 INFO L134 CoverageAnalysis]: Checked inductivity of 2959 backedges. 750 proven. 1302 refuted. 0 times theorem prover too weak. 907 trivial. 0 not checked. [2024-05-06 18:11:42,870 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:11:42,870 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [742556786] [2024-05-06 18:11:42,870 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [742556786] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:11:42,870 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [649846122] [2024-05-06 18:11:42,870 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-05-06 18:11:42,870 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:11:42,870 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:11:42,871 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:11:42,873 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2024-05-06 18:11:43,842 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-05-06 18:11:43,842 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-05-06 18:11:43,850 INFO L262 TraceCheckSpWp]: Trace formula consists of 1682 conjuncts, 24 conjunts are in the unsatisfiable core [2024-05-06 18:11:43,858 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 18:11:44,798 INFO L134 CoverageAnalysis]: Checked inductivity of 2959 backedges. 1414 proven. 126 refuted. 0 times theorem prover too weak. 1419 trivial. 0 not checked. [2024-05-06 18:11:44,799 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-06 18:11:45,858 INFO L134 CoverageAnalysis]: Checked inductivity of 2959 backedges. 1321 proven. 219 refuted. 0 times theorem prover too weak. 1419 trivial. 0 not checked. [2024-05-06 18:11:45,858 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [649846122] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-06 18:11:45,858 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-06 18:11:45,858 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 24, 24] total 73 [2024-05-06 18:11:45,858 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1488345483] [2024-05-06 18:11:45,858 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-06 18:11:45,859 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 73 states [2024-05-06 18:11:45,859 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:11:45,860 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 73 interpolants. [2024-05-06 18:11:45,865 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=531, Invalid=4725, Unknown=0, NotChecked=0, Total=5256 [2024-05-06 18:11:45,865 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:11:45,865 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:11:45,866 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 73 states, 73 states have (on average 10.917808219178083) internal successors, (797), 73 states have internal predecessors, (797), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:11:45,866 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:11:45,866 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:11:45,866 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:11:45,866 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:11:45,866 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:11:45,866 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:11:45,866 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 4 states. [2024-05-06 18:11:45,866 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 29 states. [2024-05-06 18:11:45,866 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 58 states. [2024-05-06 18:11:45,866 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 72 states. [2024-05-06 18:11:45,866 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:11:50,209 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:11:50,209 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:11:50,209 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:11:50,209 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:11:50,209 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:11:50,209 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:11:50,209 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-05-06 18:11:50,209 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2024-05-06 18:11:50,209 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2024-05-06 18:11:50,209 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2024-05-06 18:11:50,209 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 81 states. [2024-05-06 18:11:50,222 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Forceful destruction successful, exit code 0 [2024-05-06 18:11:50,409 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable610 [2024-05-06 18:11:50,410 INFO L420 AbstractCegarLoop]: === Iteration 12 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 2 more)] === [2024-05-06 18:11:50,410 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:11:50,410 INFO L85 PathProgramCache]: Analyzing trace with hash 1359664719, now seen corresponding path program 9 times [2024-05-06 18:11:50,410 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:11:50,410 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1239731257] [2024-05-06 18:11:50,410 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:11:50,410 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:11:50,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:11:52,082 INFO L134 CoverageAnalysis]: Checked inductivity of 3073 backedges. 1429 proven. 611 refuted. 0 times theorem prover too weak. 1033 trivial. 0 not checked. [2024-05-06 18:11:52,082 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:11:52,082 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1239731257] [2024-05-06 18:11:52,082 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1239731257] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:11:52,082 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [578549523] [2024-05-06 18:11:52,083 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-05-06 18:11:52,083 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:11:52,083 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:11:52,084 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:11:52,085 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2024-05-06 18:11:56,072 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2024-05-06 18:11:56,073 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-05-06 18:11:56,084 INFO L262 TraceCheckSpWp]: Trace formula consists of 1139 conjuncts, 27 conjunts are in the unsatisfiable core [2024-05-06 18:11:56,090 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 18:11:57,168 INFO L134 CoverageAnalysis]: Checked inductivity of 3073 backedges. 1364 proven. 196 refuted. 0 times theorem prover too weak. 1513 trivial. 0 not checked. [2024-05-06 18:11:57,168 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-06 18:11:58,445 INFO L134 CoverageAnalysis]: Checked inductivity of 3073 backedges. 263 proven. 1297 refuted. 0 times theorem prover too weak. 1513 trivial. 0 not checked. [2024-05-06 18:11:58,446 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [578549523] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-06 18:11:58,446 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-06 18:11:58,446 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27] total 73 [2024-05-06 18:11:58,446 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2130739701] [2024-05-06 18:11:58,446 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-06 18:11:58,447 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 73 states [2024-05-06 18:11:58,447 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:11:58,448 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 73 interpolants. [2024-05-06 18:11:58,449 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=762, Invalid=4494, Unknown=0, NotChecked=0, Total=5256 [2024-05-06 18:11:58,449 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:11:58,449 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:11:58,449 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 73 states, 73 states have (on average 9.287671232876713) internal successors, (678), 73 states have internal predecessors, (678), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:11:58,449 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:11:58,450 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:11:58,450 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:11:58,450 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:11:58,450 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:11:58,450 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:11:58,450 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 4 states. [2024-05-06 18:11:58,450 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 29 states. [2024-05-06 18:11:58,450 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 58 states. [2024-05-06 18:11:58,450 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 72 states. [2024-05-06 18:11:58,450 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 81 states. [2024-05-06 18:11:58,450 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:12:01,287 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:12:01,288 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:12:01,288 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:12:01,288 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:12:01,288 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:12:01,288 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:12:01,288 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-05-06 18:12:01,288 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2024-05-06 18:12:01,288 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2024-05-06 18:12:01,288 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2024-05-06 18:12:01,288 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 81 states. [2024-05-06 18:12:01,288 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2024-05-06 18:12:01,303 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Forceful destruction successful, exit code 0 [2024-05-06 18:12:01,496 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 14 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable611 [2024-05-06 18:12:01,496 INFO L420 AbstractCegarLoop]: === Iteration 13 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 2 more)] === [2024-05-06 18:12:01,496 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:12:01,496 INFO L85 PathProgramCache]: Analyzing trace with hash 1827405823, now seen corresponding path program 10 times [2024-05-06 18:12:01,497 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:12:01,497 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [744892687] [2024-05-06 18:12:01,497 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:12:01,497 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:12:01,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:12:03,406 INFO L134 CoverageAnalysis]: Checked inductivity of 3130 backedges. 1478 proven. 642 refuted. 0 times theorem prover too weak. 1010 trivial. 0 not checked. [2024-05-06 18:12:03,406 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:12:03,406 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [744892687] [2024-05-06 18:12:03,406 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [744892687] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:12:03,406 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [837774047] [2024-05-06 18:12:03,407 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-05-06 18:12:03,407 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:12:03,407 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:12:03,408 INFO L229 MonitoredProcess]: Starting monitored process 15 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:12:03,410 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2024-05-06 18:12:04,874 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-05-06 18:12:04,875 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-05-06 18:12:04,897 INFO L262 TraceCheckSpWp]: Trace formula consists of 1724 conjuncts, 30 conjunts are in the unsatisfiable core [2024-05-06 18:12:04,903 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 18:12:06,091 INFO L134 CoverageAnalysis]: Checked inductivity of 3130 backedges. 1339 proven. 342 refuted. 0 times theorem prover too weak. 1449 trivial. 0 not checked. [2024-05-06 18:12:06,091 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-06 18:12:07,407 INFO L134 CoverageAnalysis]: Checked inductivity of 3130 backedges. 194 proven. 1487 refuted. 0 times theorem prover too weak. 1449 trivial. 0 not checked. [2024-05-06 18:12:07,408 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [837774047] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-06 18:12:07,408 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-06 18:12:07,408 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30] total 82 [2024-05-06 18:12:07,408 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [979246368] [2024-05-06 18:12:07,408 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-06 18:12:07,409 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 82 states [2024-05-06 18:12:07,409 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:12:07,412 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 82 interpolants. [2024-05-06 18:12:07,413 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=926, Invalid=5716, Unknown=0, NotChecked=0, Total=6642 [2024-05-06 18:12:07,413 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:12:07,413 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:12:07,414 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 82 states, 82 states have (on average 8.829268292682928) internal successors, (724), 82 states have internal predecessors, (724), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:12:07,414 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:12:07,414 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:12:07,414 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:12:07,414 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:12:07,414 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:12:07,414 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:12:07,414 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 4 states. [2024-05-06 18:12:07,414 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 29 states. [2024-05-06 18:12:07,415 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 58 states. [2024-05-06 18:12:07,415 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 72 states. [2024-05-06 18:12:07,415 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 81 states. [2024-05-06 18:12:07,415 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 37 states. [2024-05-06 18:12:07,415 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:12:10,412 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:12:10,413 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:12:10,413 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:12:10,413 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:12:10,413 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:12:10,413 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:12:10,413 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-05-06 18:12:10,413 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2024-05-06 18:12:10,413 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2024-05-06 18:12:10,413 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2024-05-06 18:12:10,413 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 81 states. [2024-05-06 18:12:10,413 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2024-05-06 18:12:10,413 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2024-05-06 18:12:10,425 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Ended with exit code 0 [2024-05-06 18:12:10,619 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable612,15 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:12:10,620 INFO L420 AbstractCegarLoop]: === Iteration 14 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 2 more)] === [2024-05-06 18:12:10,620 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:12:10,620 INFO L85 PathProgramCache]: Analyzing trace with hash -56591953, now seen corresponding path program 11 times [2024-05-06 18:12:10,620 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:12:10,620 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1197068878] [2024-05-06 18:12:10,620 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:12:10,621 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:12:10,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:12:12,541 INFO L134 CoverageAnalysis]: Checked inductivity of 3195 backedges. 1549 proven. 649 refuted. 0 times theorem prover too weak. 997 trivial. 0 not checked. [2024-05-06 18:12:12,541 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:12:12,541 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1197068878] [2024-05-06 18:12:12,541 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1197068878] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:12:12,541 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1132753428] [2024-05-06 18:12:12,542 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-05-06 18:12:12,542 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:12:12,542 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:12:12,543 INFO L229 MonitoredProcess]: Starting monitored process 16 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:12:12,545 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2024-05-06 18:12:22,498 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 19 check-sat command(s) [2024-05-06 18:12:22,498 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-05-06 18:12:22,522 INFO L262 TraceCheckSpWp]: Trace formula consists of 1738 conjuncts, 27 conjunts are in the unsatisfiable core [2024-05-06 18:12:22,538 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 18:12:23,045 INFO L134 CoverageAnalysis]: Checked inductivity of 3195 backedges. 1372 proven. 196 refuted. 0 times theorem prover too weak. 1627 trivial. 0 not checked. [2024-05-06 18:12:23,045 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-06 18:12:24,526 INFO L134 CoverageAnalysis]: Checked inductivity of 3195 backedges. 1167 proven. 1101 refuted. 0 times theorem prover too weak. 927 trivial. 0 not checked. [2024-05-06 18:12:24,527 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1132753428] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-06 18:12:24,527 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-06 18:12:24,527 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 6, 28] total 63 [2024-05-06 18:12:24,528 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1485851576] [2024-05-06 18:12:24,528 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-06 18:12:24,529 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 63 states [2024-05-06 18:12:24,529 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:12:24,530 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 63 interpolants. [2024-05-06 18:12:24,530 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=555, Invalid=3351, Unknown=0, NotChecked=0, Total=3906 [2024-05-06 18:12:24,530 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:12:24,531 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:12:24,531 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 63 states, 63 states have (on average 14.65079365079365) internal successors, (923), 63 states have internal predecessors, (923), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:12:24,531 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:12:24,531 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:12:24,531 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:12:24,531 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:12:24,531 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:12:24,531 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:12:24,531 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 4 states. [2024-05-06 18:12:24,531 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 29 states. [2024-05-06 18:12:24,531 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 58 states. [2024-05-06 18:12:24,531 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 72 states. [2024-05-06 18:12:24,532 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 81 states. [2024-05-06 18:12:24,532 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 37 states. [2024-05-06 18:12:24,532 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 41 states. [2024-05-06 18:12:24,532 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:12:26,576 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:12:26,577 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:12:26,577 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:12:26,577 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:12:26,577 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:12:26,577 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:12:26,577 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-05-06 18:12:26,577 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2024-05-06 18:12:26,577 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2024-05-06 18:12:26,577 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2024-05-06 18:12:26,577 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 81 states. [2024-05-06 18:12:26,577 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2024-05-06 18:12:26,577 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2024-05-06 18:12:26,577 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2024-05-06 18:12:26,592 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Forceful destruction successful, exit code 0 [2024-05-06 18:12:26,792 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable613,16 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:12:26,792 INFO L420 AbstractCegarLoop]: === Iteration 15 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 2 more)] === [2024-05-06 18:12:26,792 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:12:26,792 INFO L85 PathProgramCache]: Analyzing trace with hash 1447334814, now seen corresponding path program 12 times [2024-05-06 18:12:26,793 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:12:26,793 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1373382531] [2024-05-06 18:12:26,793 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:12:26,793 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:12:26,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:12:28,325 INFO L134 CoverageAnalysis]: Checked inductivity of 1852 backedges. 332 proven. 844 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-05-06 18:12:28,325 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:12:28,325 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1373382531] [2024-05-06 18:12:28,325 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1373382531] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:12:28,325 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [359613332] [2024-05-06 18:12:28,325 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-05-06 18:12:28,325 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:12:28,325 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:12:28,326 INFO L229 MonitoredProcess]: Starting monitored process 17 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:12:28,328 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2024-05-06 18:12:29,835 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 11 check-sat command(s) [2024-05-06 18:12:29,835 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-05-06 18:12:29,842 INFO L262 TraceCheckSpWp]: Trace formula consists of 1092 conjuncts, 37 conjunts are in the unsatisfiable core [2024-05-06 18:12:29,847 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 18:12:30,883 INFO L134 CoverageAnalysis]: Checked inductivity of 1852 backedges. 693 proven. 123 refuted. 0 times theorem prover too weak. 1036 trivial. 0 not checked. [2024-05-06 18:12:30,883 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-06 18:12:31,970 INFO L134 CoverageAnalysis]: Checked inductivity of 1852 backedges. 666 proven. 195 refuted. 0 times theorem prover too weak. 991 trivial. 0 not checked. [2024-05-06 18:12:31,970 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [359613332] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-06 18:12:31,970 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-06 18:12:31,971 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 24, 28] total 81 [2024-05-06 18:12:31,971 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1569566881] [2024-05-06 18:12:31,971 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-06 18:12:31,972 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 81 states [2024-05-06 18:12:31,972 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:12:31,973 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 81 interpolants. [2024-05-06 18:12:31,974 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=686, Invalid=5794, Unknown=0, NotChecked=0, Total=6480 [2024-05-06 18:12:31,974 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:12:31,974 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:12:31,975 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 81 states, 81 states have (on average 12.135802469135802) internal successors, (983), 81 states have internal predecessors, (983), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:12:31,975 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:12:31,975 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:12:31,975 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:12:31,975 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:12:31,975 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:12:31,975 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:12:31,975 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 4 states. [2024-05-06 18:12:31,975 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 29 states. [2024-05-06 18:12:31,975 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 58 states. [2024-05-06 18:12:31,975 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 72 states. [2024-05-06 18:12:31,975 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 81 states. [2024-05-06 18:12:31,975 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 37 states. [2024-05-06 18:12:31,975 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 41 states. [2024-05-06 18:12:31,975 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 48 states. [2024-05-06 18:12:31,975 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:12:36,800 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:12:36,801 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:12:36,801 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:12:36,801 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:12:36,801 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:12:36,801 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:12:36,801 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-05-06 18:12:36,801 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2024-05-06 18:12:36,801 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2024-05-06 18:12:36,801 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2024-05-06 18:12:36,801 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 81 states. [2024-05-06 18:12:36,801 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2024-05-06 18:12:36,801 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2024-05-06 18:12:36,801 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2024-05-06 18:12:36,801 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 94 states. [2024-05-06 18:12:36,815 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Forceful destruction successful, exit code 0 [2024-05-06 18:12:37,013 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 17 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable614 [2024-05-06 18:12:37,013 INFO L420 AbstractCegarLoop]: === Iteration 16 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 2 more)] === [2024-05-06 18:12:37,013 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:12:37,013 INFO L85 PathProgramCache]: Analyzing trace with hash -1705351047, now seen corresponding path program 13 times [2024-05-06 18:12:37,013 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:12:37,013 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [504084288] [2024-05-06 18:12:37,013 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:12:37,014 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:12:37,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:12:38,798 INFO L134 CoverageAnalysis]: Checked inductivity of 2015 backedges. 461 proven. 890 refuted. 0 times theorem prover too weak. 664 trivial. 0 not checked. [2024-05-06 18:12:38,798 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:12:38,798 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [504084288] [2024-05-06 18:12:38,798 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [504084288] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:12:38,799 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1964133757] [2024-05-06 18:12:38,799 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-05-06 18:12:38,799 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:12:38,799 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:12:38,801 INFO L229 MonitoredProcess]: Starting monitored process 18 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:12:38,803 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2024-05-06 18:12:39,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:12:39,851 INFO L262 TraceCheckSpWp]: Trace formula consists of 1456 conjuncts, 36 conjunts are in the unsatisfiable core [2024-05-06 18:12:39,856 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 18:12:41,132 INFO L134 CoverageAnalysis]: Checked inductivity of 2015 backedges. 1019 proven. 370 refuted. 0 times theorem prover too weak. 626 trivial. 0 not checked. [2024-05-06 18:12:41,133 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-06 18:12:42,744 INFO L134 CoverageAnalysis]: Checked inductivity of 2015 backedges. 903 proven. 486 refuted. 0 times theorem prover too weak. 626 trivial. 0 not checked. [2024-05-06 18:12:42,745 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1964133757] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-06 18:12:42,745 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-06 18:12:42,745 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36, 36] total 100 [2024-05-06 18:12:42,745 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1461679751] [2024-05-06 18:12:42,745 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-06 18:12:42,746 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 100 states [2024-05-06 18:12:42,746 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:12:42,747 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 100 interpolants. [2024-05-06 18:12:42,750 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1377, Invalid=8523, Unknown=0, NotChecked=0, Total=9900 [2024-05-06 18:12:42,750 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:12:42,750 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:12:42,751 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 100 states, 100 states have (on average 8.57) internal successors, (857), 100 states have internal predecessors, (857), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:12:42,751 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:12:42,751 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:12:42,751 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:12:42,751 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:12:42,751 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:12:42,751 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:12:42,751 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 4 states. [2024-05-06 18:12:42,751 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 29 states. [2024-05-06 18:12:42,751 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 58 states. [2024-05-06 18:12:42,751 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 72 states. [2024-05-06 18:12:42,751 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 81 states. [2024-05-06 18:12:42,751 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 37 states. [2024-05-06 18:12:42,751 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 41 states. [2024-05-06 18:12:42,752 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 48 states. [2024-05-06 18:12:42,752 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 94 states. [2024-05-06 18:12:42,752 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:12:45,284 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:12:45,284 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:12:45,284 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:12:45,284 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:12:45,284 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:12:45,284 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:12:45,284 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-05-06 18:12:45,284 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2024-05-06 18:12:45,284 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2024-05-06 18:12:45,284 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2024-05-06 18:12:45,284 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 81 states. [2024-05-06 18:12:45,284 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2024-05-06 18:12:45,284 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2024-05-06 18:12:45,284 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2024-05-06 18:12:45,285 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 94 states. [2024-05-06 18:12:45,285 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2024-05-06 18:12:45,297 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Forceful destruction successful, exit code 0 [2024-05-06 18:12:45,495 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable615,18 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:12:45,495 INFO L420 AbstractCegarLoop]: === Iteration 17 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 2 more)] === [2024-05-06 18:12:45,495 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:12:45,495 INFO L85 PathProgramCache]: Analyzing trace with hash -1890489588, now seen corresponding path program 14 times [2024-05-06 18:12:45,495 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:12:45,496 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1097225150] [2024-05-06 18:12:45,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:12:45,496 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:12:45,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:12:47,403 INFO L134 CoverageAnalysis]: Checked inductivity of 2096 backedges. 549 proven. 925 refuted. 0 times theorem prover too weak. 622 trivial. 0 not checked. [2024-05-06 18:12:47,404 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:12:47,404 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1097225150] [2024-05-06 18:12:47,404 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1097225150] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:12:47,404 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1339979734] [2024-05-06 18:12:47,404 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-05-06 18:12:47,404 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:12:47,404 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:12:47,405 INFO L229 MonitoredProcess]: Starting monitored process 19 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:12:47,410 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2024-05-06 18:12:48,486 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-05-06 18:12:48,486 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-05-06 18:12:48,493 INFO L262 TraceCheckSpWp]: Trace formula consists of 1470 conjuncts, 39 conjunts are in the unsatisfiable core [2024-05-06 18:12:48,498 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 18:12:50,114 INFO L134 CoverageAnalysis]: Checked inductivity of 2096 backedges. 1048 proven. 451 refuted. 0 times theorem prover too weak. 597 trivial. 0 not checked. [2024-05-06 18:12:50,114 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-06 18:12:52,006 INFO L134 CoverageAnalysis]: Checked inductivity of 2096 backedges. 902 proven. 597 refuted. 0 times theorem prover too weak. 597 trivial. 0 not checked. [2024-05-06 18:12:52,006 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1339979734] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-06 18:12:52,006 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-06 18:12:52,007 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 39, 39] total 109 [2024-05-06 18:12:52,007 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1707400391] [2024-05-06 18:12:52,007 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-06 18:12:52,008 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 109 states [2024-05-06 18:12:52,008 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:12:52,009 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 109 interpolants. [2024-05-06 18:12:52,011 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1621, Invalid=10151, Unknown=0, NotChecked=0, Total=11772 [2024-05-06 18:12:52,011 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:12:52,012 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:12:52,012 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 109 states, 109 states have (on average 8.376146788990825) internal successors, (913), 109 states have internal predecessors, (913), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:12:52,012 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:12:52,012 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:12:52,012 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:12:52,012 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:12:52,012 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:12:52,012 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:12:52,012 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 4 states. [2024-05-06 18:12:52,012 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 29 states. [2024-05-06 18:12:52,012 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 58 states. [2024-05-06 18:12:52,012 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 72 states. [2024-05-06 18:12:52,012 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 81 states. [2024-05-06 18:12:52,013 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 37 states. [2024-05-06 18:12:52,013 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 41 states. [2024-05-06 18:12:52,013 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 48 states. [2024-05-06 18:12:52,013 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 94 states. [2024-05-06 18:12:52,013 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 49 states. [2024-05-06 18:12:52,013 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:12:54,460 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:12:54,460 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:12:54,460 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:12:54,460 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:12:54,460 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:12:54,460 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:12:54,460 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-05-06 18:12:54,460 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2024-05-06 18:12:54,461 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2024-05-06 18:12:54,461 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2024-05-06 18:12:54,461 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 81 states. [2024-05-06 18:12:54,461 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2024-05-06 18:12:54,461 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2024-05-06 18:12:54,461 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2024-05-06 18:12:54,461 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 94 states. [2024-05-06 18:12:54,461 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2024-05-06 18:12:54,461 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2024-05-06 18:12:54,484 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Forceful destruction successful, exit code 0 [2024-05-06 18:12:54,661 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 19 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable616 [2024-05-06 18:12:54,661 INFO L420 AbstractCegarLoop]: === Iteration 18 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 2 more)] === [2024-05-06 18:12:54,662 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:12:54,662 INFO L85 PathProgramCache]: Analyzing trace with hash 1232218783, now seen corresponding path program 15 times [2024-05-06 18:12:54,662 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:12:54,662 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [186615782] [2024-05-06 18:12:54,662 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:12:54,662 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:12:54,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:12:56,742 INFO L134 CoverageAnalysis]: Checked inductivity of 2185 backedges. 648 proven. 945 refuted. 0 times theorem prover too weak. 592 trivial. 0 not checked. [2024-05-06 18:12:56,742 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:12:56,742 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [186615782] [2024-05-06 18:12:56,742 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [186615782] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:12:56,743 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1736948170] [2024-05-06 18:12:56,743 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-05-06 18:12:56,743 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:12:56,743 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:12:56,744 INFO L229 MonitoredProcess]: Starting monitored process 20 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:12:56,748 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2024-05-06 18:13:24,310 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 14 check-sat command(s) [2024-05-06 18:13:24,310 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-05-06 18:13:24,343 INFO L262 TraceCheckSpWp]: Trace formula consists of 1435 conjuncts, 48 conjunts are in the unsatisfiable core [2024-05-06 18:13:24,348 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 18:13:25,910 INFO L134 CoverageAnalysis]: Checked inductivity of 2185 backedges. 1056 proven. 540 refuted. 0 times theorem prover too weak. 589 trivial. 0 not checked. [2024-05-06 18:13:25,911 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-06 18:13:28,065 INFO L134 CoverageAnalysis]: Checked inductivity of 2185 backedges. 641 proven. 955 refuted. 0 times theorem prover too weak. 589 trivial. 0 not checked. [2024-05-06 18:13:28,066 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1736948170] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-06 18:13:28,066 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-06 18:13:28,066 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 42, 42] total 118 [2024-05-06 18:13:28,066 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1425827819] [2024-05-06 18:13:28,066 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-06 18:13:28,067 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 118 states [2024-05-06 18:13:28,067 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:13:28,068 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 118 interpolants. [2024-05-06 18:13:28,070 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1989, Invalid=11817, Unknown=0, NotChecked=0, Total=13806 [2024-05-06 18:13:28,070 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:13:28,071 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:13:28,071 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 118 states, 118 states have (on average 7.991525423728813) internal successors, (943), 118 states have internal predecessors, (943), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:13:28,071 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:13:28,071 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:13:28,071 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:13:28,071 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:13:28,071 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:13:28,071 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:13:28,071 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 4 states. [2024-05-06 18:13:28,071 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 29 states. [2024-05-06 18:13:28,071 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 58 states. [2024-05-06 18:13:28,071 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 72 states. [2024-05-06 18:13:28,071 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 81 states. [2024-05-06 18:13:28,072 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 37 states. [2024-05-06 18:13:28,072 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 41 states. [2024-05-06 18:13:28,072 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 48 states. [2024-05-06 18:13:28,072 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 94 states. [2024-05-06 18:13:28,072 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 49 states. [2024-05-06 18:13:28,072 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 53 states. [2024-05-06 18:13:28,072 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:13:30,936 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:13:30,936 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:13:30,936 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:13:30,936 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:13:30,936 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:13:30,936 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:13:30,936 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-05-06 18:13:30,936 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2024-05-06 18:13:30,936 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2024-05-06 18:13:30,936 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2024-05-06 18:13:30,936 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 81 states. [2024-05-06 18:13:30,936 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2024-05-06 18:13:30,936 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2024-05-06 18:13:30,936 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2024-05-06 18:13:30,936 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 94 states. [2024-05-06 18:13:30,936 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2024-05-06 18:13:30,936 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2024-05-06 18:13:30,937 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2024-05-06 18:13:30,954 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Forceful destruction successful, exit code 0 [2024-05-06 18:13:31,152 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable617,20 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:13:31,153 INFO L420 AbstractCegarLoop]: === Iteration 19 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 2 more)] === [2024-05-06 18:13:31,153 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:13:31,153 INFO L85 PathProgramCache]: Analyzing trace with hash 363833138, now seen corresponding path program 16 times [2024-05-06 18:13:31,153 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:13:31,153 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [806505845] [2024-05-06 18:13:31,153 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:13:31,153 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:13:31,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:13:33,392 INFO L134 CoverageAnalysis]: Checked inductivity of 2282 backedges. 758 proven. 952 refuted. 0 times theorem prover too weak. 572 trivial. 0 not checked. [2024-05-06 18:13:33,392 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:13:33,392 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [806505845] [2024-05-06 18:13:33,392 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [806505845] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:13:33,393 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [576668851] [2024-05-06 18:13:33,393 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-05-06 18:13:33,393 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:13:33,393 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:13:33,394 INFO L229 MonitoredProcess]: Starting monitored process 21 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:13:33,395 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2024-05-06 18:13:35,111 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-05-06 18:13:35,111 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-05-06 18:13:35,119 INFO L262 TraceCheckSpWp]: Trace formula consists of 1498 conjuncts, 49 conjunts are in the unsatisfiable core [2024-05-06 18:13:35,124 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 18:13:36,999 INFO L134 CoverageAnalysis]: Checked inductivity of 2282 backedges. 1087 proven. 640 refuted. 0 times theorem prover too weak. 555 trivial. 0 not checked. [2024-05-06 18:13:36,999 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-06 18:13:39,189 INFO L134 CoverageAnalysis]: Checked inductivity of 2282 backedges. 803 proven. 924 refuted. 0 times theorem prover too weak. 555 trivial. 0 not checked. [2024-05-06 18:13:39,189 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [576668851] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-06 18:13:39,189 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-06 18:13:39,189 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [45, 48, 48] total 134 [2024-05-06 18:13:39,189 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [454439591] [2024-05-06 18:13:39,189 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-06 18:13:39,190 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 134 states [2024-05-06 18:13:39,190 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:13:39,194 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 134 interpolants. [2024-05-06 18:13:39,196 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2660, Invalid=15162, Unknown=0, NotChecked=0, Total=17822 [2024-05-06 18:13:39,196 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:13:39,196 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:13:39,197 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 134 states, 134 states have (on average 8.671641791044776) internal successors, (1162), 134 states have internal predecessors, (1162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:13:39,197 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:13:39,197 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:13:39,197 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:13:39,197 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:13:39,197 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:13:39,197 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:13:39,197 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 4 states. [2024-05-06 18:13:39,197 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 29 states. [2024-05-06 18:13:39,197 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 58 states. [2024-05-06 18:13:39,197 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 72 states. [2024-05-06 18:13:39,197 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 81 states. [2024-05-06 18:13:39,197 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 37 states. [2024-05-06 18:13:39,197 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 41 states. [2024-05-06 18:13:39,197 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 48 states. [2024-05-06 18:13:39,197 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 94 states. [2024-05-06 18:13:39,197 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 49 states. [2024-05-06 18:13:39,198 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 53 states. [2024-05-06 18:13:39,198 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 57 states. [2024-05-06 18:13:39,198 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:13:44,061 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:13:44,062 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:13:44,062 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:13:44,062 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:13:44,062 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:13:44,062 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:13:44,062 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-05-06 18:13:44,062 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2024-05-06 18:13:44,062 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2024-05-06 18:13:44,062 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2024-05-06 18:13:44,062 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 81 states. [2024-05-06 18:13:44,062 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2024-05-06 18:13:44,062 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2024-05-06 18:13:44,062 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2024-05-06 18:13:44,062 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 94 states. [2024-05-06 18:13:44,062 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2024-05-06 18:13:44,062 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2024-05-06 18:13:44,062 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2024-05-06 18:13:44,062 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 67 states. [2024-05-06 18:13:44,074 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Forceful destruction successful, exit code 0 [2024-05-06 18:13:44,274 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable618,21 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:13:44,274 INFO L420 AbstractCegarLoop]: === Iteration 20 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 2 more)] === [2024-05-06 18:13:44,274 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:13:44,275 INFO L85 PathProgramCache]: Analyzing trace with hash 276494888, now seen corresponding path program 17 times [2024-05-06 18:13:44,275 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:13:44,275 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1541642712] [2024-05-06 18:13:44,275 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:13:44,275 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:13:44,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:13:45,915 INFO L134 CoverageAnalysis]: Checked inductivity of 2277 backedges. 269 proven. 867 refuted. 0 times theorem prover too weak. 1141 trivial. 0 not checked. [2024-05-06 18:13:45,915 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:13:45,915 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1541642712] [2024-05-06 18:13:45,915 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1541642712] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:13:45,915 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [414758341] [2024-05-06 18:13:45,915 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-05-06 18:13:45,916 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:13:45,916 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:13:45,917 INFO L229 MonitoredProcess]: Starting monitored process 22 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:13:45,918 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2024-05-06 18:15:02,799 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 16 check-sat command(s) [2024-05-06 18:15:02,799 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-05-06 18:15:02,853 INFO L262 TraceCheckSpWp]: Trace formula consists of 1458 conjuncts, 40 conjunts are in the unsatisfiable core [2024-05-06 18:15:02,858 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 18:15:04,885 INFO L134 CoverageAnalysis]: Checked inductivity of 2277 backedges. 737 proven. 495 refuted. 0 times theorem prover too weak. 1045 trivial. 0 not checked. [2024-05-06 18:15:04,886 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-06 18:15:07,249 INFO L134 CoverageAnalysis]: Checked inductivity of 2277 backedges. 744 proven. 488 refuted. 0 times theorem prover too weak. 1045 trivial. 0 not checked. [2024-05-06 18:15:07,249 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [414758341] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-06 18:15:07,249 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-06 18:15:07,250 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 41, 40] total 113 [2024-05-06 18:15:07,250 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1506737179] [2024-05-06 18:15:07,250 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-06 18:15:07,251 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 113 states [2024-05-06 18:15:07,251 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:15:07,252 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 113 interpolants. [2024-05-06 18:15:07,263 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2417, Invalid=10239, Unknown=0, NotChecked=0, Total=12656 [2024-05-06 18:15:07,263 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:15:07,263 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:15:07,264 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 113 states, 113 states have (on average 9.56637168141593) internal successors, (1081), 113 states have internal predecessors, (1081), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:15:07,264 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:15:07,264 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:15:07,264 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:15:07,264 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:15:07,264 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:15:07,264 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:15:07,264 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 4 states. [2024-05-06 18:15:07,264 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 29 states. [2024-05-06 18:15:07,264 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 58 states. [2024-05-06 18:15:07,265 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 72 states. [2024-05-06 18:15:07,265 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 81 states. [2024-05-06 18:15:07,265 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 37 states. [2024-05-06 18:15:07,265 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 41 states. [2024-05-06 18:15:07,265 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 48 states. [2024-05-06 18:15:07,265 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 94 states. [2024-05-06 18:15:07,265 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 49 states. [2024-05-06 18:15:07,265 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 53 states. [2024-05-06 18:15:07,265 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 57 states. [2024-05-06 18:15:07,265 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 67 states. [2024-05-06 18:15:07,265 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:15:11,332 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:15:11,332 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:15:11,332 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:15:11,332 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:15:11,332 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:15:11,332 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:15:11,332 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-05-06 18:15:11,332 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2024-05-06 18:15:11,332 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2024-05-06 18:15:11,333 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2024-05-06 18:15:11,333 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 81 states. [2024-05-06 18:15:11,333 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2024-05-06 18:15:11,333 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2024-05-06 18:15:11,333 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2024-05-06 18:15:11,333 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 94 states. [2024-05-06 18:15:11,333 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2024-05-06 18:15:11,333 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2024-05-06 18:15:11,333 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2024-05-06 18:15:11,333 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 67 states. [2024-05-06 18:15:11,333 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 61 states. [2024-05-06 18:15:11,355 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Ended with exit code 0 [2024-05-06 18:15:11,548 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable619,22 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:15:11,548 INFO L420 AbstractCegarLoop]: === Iteration 21 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 2 more)] === [2024-05-06 18:15:11,549 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:15:11,549 INFO L85 PathProgramCache]: Analyzing trace with hash 1859795176, now seen corresponding path program 18 times [2024-05-06 18:15:11,549 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:15:11,549 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1037480064] [2024-05-06 18:15:11,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:15:11,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:15:11,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:15:13,055 INFO L134 CoverageAnalysis]: Checked inductivity of 2649 backedges. 733 proven. 234 refuted. 0 times theorem prover too weak. 1682 trivial. 0 not checked. [2024-05-06 18:15:13,055 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:15:13,055 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1037480064] [2024-05-06 18:15:13,055 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1037480064] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:15:13,056 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [636233599] [2024-05-06 18:15:13,056 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-05-06 18:15:13,056 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:15:13,056 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:15:13,057 INFO L229 MonitoredProcess]: Starting monitored process 23 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:15:13,058 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2024-05-06 18:16:16,562 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 15 check-sat command(s) [2024-05-06 18:16:16,562 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-05-06 18:16:16,609 INFO L262 TraceCheckSpWp]: Trace formula consists of 1486 conjuncts, 47 conjunts are in the unsatisfiable core [2024-05-06 18:16:16,614 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 18:16:18,635 INFO L134 CoverageAnalysis]: Checked inductivity of 2649 backedges. 691 proven. 240 refuted. 0 times theorem prover too weak. 1718 trivial. 0 not checked. [2024-05-06 18:16:18,635 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-06 18:16:20,182 INFO L134 CoverageAnalysis]: Checked inductivity of 2649 backedges. 670 proven. 261 refuted. 0 times theorem prover too weak. 1718 trivial. 0 not checked. [2024-05-06 18:16:20,183 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [636233599] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-06 18:16:20,183 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-06 18:16:20,183 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 36, 35] total 92 [2024-05-06 18:16:20,183 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [523796214] [2024-05-06 18:16:20,183 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-06 18:16:20,184 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 92 states [2024-05-06 18:16:20,184 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:16:20,185 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 92 interpolants. [2024-05-06 18:16:20,186 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1371, Invalid=7001, Unknown=0, NotChecked=0, Total=8372 [2024-05-06 18:16:20,186 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:16:20,186 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:16:20,186 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 92 states, 92 states have (on average 10.793478260869565) internal successors, (993), 92 states have internal predecessors, (993), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:16:20,187 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:16:20,187 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:16:20,187 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:16:20,187 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:16:20,187 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:16:20,187 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:16:20,187 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 4 states. [2024-05-06 18:16:20,187 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 29 states. [2024-05-06 18:16:20,187 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 58 states. [2024-05-06 18:16:20,187 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 72 states. [2024-05-06 18:16:20,187 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 81 states. [2024-05-06 18:16:20,187 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 37 states. [2024-05-06 18:16:20,187 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 41 states. [2024-05-06 18:16:20,187 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 48 states. [2024-05-06 18:16:20,187 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 94 states. [2024-05-06 18:16:20,187 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 49 states. [2024-05-06 18:16:20,187 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 53 states. [2024-05-06 18:16:20,187 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 57 states. [2024-05-06 18:16:20,187 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 67 states. [2024-05-06 18:16:20,187 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 61 states. [2024-05-06 18:16:20,187 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:16:23,883 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:16:23,883 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:16:23,883 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:16:23,883 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:16:23,883 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:16:23,883 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:16:23,883 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-05-06 18:16:23,883 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2024-05-06 18:16:23,883 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2024-05-06 18:16:23,883 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2024-05-06 18:16:23,883 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 81 states. [2024-05-06 18:16:23,883 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2024-05-06 18:16:23,883 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2024-05-06 18:16:23,883 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2024-05-06 18:16:23,883 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 94 states. [2024-05-06 18:16:23,883 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2024-05-06 18:16:23,884 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2024-05-06 18:16:23,884 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2024-05-06 18:16:23,884 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 67 states. [2024-05-06 18:16:23,884 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 61 states. [2024-05-06 18:16:23,884 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2024-05-06 18:16:23,903 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Forceful destruction successful, exit code 0 [2024-05-06 18:16:24,092 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 23 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable620 [2024-05-06 18:16:24,092 INFO L420 AbstractCegarLoop]: === Iteration 22 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 2 more)] === [2024-05-06 18:16:24,093 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:16:24,093 INFO L85 PathProgramCache]: Analyzing trace with hash 1520853152, now seen corresponding path program 19 times [2024-05-06 18:16:24,093 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:16:24,093 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [702662251] [2024-05-06 18:16:24,093 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:16:24,093 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:16:24,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:16:25,896 INFO L134 CoverageAnalysis]: Checked inductivity of 2771 backedges. 523 proven. 545 refuted. 0 times theorem prover too weak. 1703 trivial. 0 not checked. [2024-05-06 18:16:25,896 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:16:25,896 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [702662251] [2024-05-06 18:16:25,896 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [702662251] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:16:25,896 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1162877650] [2024-05-06 18:16:25,896 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-05-06 18:16:25,896 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:16:25,896 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:16:25,898 INFO L229 MonitoredProcess]: Starting monitored process 24 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:16:25,899 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2024-05-06 18:16:27,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:16:27,075 INFO L262 TraceCheckSpWp]: Trace formula consists of 1542 conjuncts, 36 conjunts are in the unsatisfiable core [2024-05-06 18:16:27,080 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 18:16:28,678 INFO L134 CoverageAnalysis]: Checked inductivity of 2771 backedges. 597 proven. 458 refuted. 0 times theorem prover too weak. 1716 trivial. 0 not checked. [2024-05-06 18:16:28,678 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-06 18:16:29,871 INFO L134 CoverageAnalysis]: Checked inductivity of 2771 backedges. 660 proven. 396 refuted. 0 times theorem prover too weak. 1715 trivial. 0 not checked. [2024-05-06 18:16:29,871 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1162877650] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-06 18:16:29,871 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-06 18:16:29,871 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33, 34] total 87 [2024-05-06 18:16:29,872 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [206692995] [2024-05-06 18:16:29,872 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-06 18:16:29,873 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 87 states [2024-05-06 18:16:29,873 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:16:29,874 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 87 interpolants. [2024-05-06 18:16:29,875 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=874, Invalid=6608, Unknown=0, NotChecked=0, Total=7482 [2024-05-06 18:16:29,875 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:16:29,875 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:16:29,875 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 87 states, 87 states have (on average 10.540229885057471) internal successors, (917), 87 states have internal predecessors, (917), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:16:29,875 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:16:29,875 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:16:29,875 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:16:29,876 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:16:29,876 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:16:29,876 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:16:29,876 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 4 states. [2024-05-06 18:16:29,876 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 29 states. [2024-05-06 18:16:29,876 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 58 states. [2024-05-06 18:16:29,876 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 72 states. [2024-05-06 18:16:29,876 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 81 states. [2024-05-06 18:16:29,876 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 37 states. [2024-05-06 18:16:29,876 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 41 states. [2024-05-06 18:16:29,876 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 48 states. [2024-05-06 18:16:29,876 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 94 states. [2024-05-06 18:16:29,876 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 49 states. [2024-05-06 18:16:29,876 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 53 states. [2024-05-06 18:16:29,876 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 57 states. [2024-05-06 18:16:29,876 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 67 states. [2024-05-06 18:16:29,876 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 61 states. [2024-05-06 18:16:29,876 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 60 states. [2024-05-06 18:16:29,876 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:16:32,457 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:16:32,457 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:16:32,459 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:16:32,459 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:16:32,459 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:16:32,459 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:16:32,459 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-05-06 18:16:32,459 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2024-05-06 18:16:32,459 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2024-05-06 18:16:32,459 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2024-05-06 18:16:32,459 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 81 states. [2024-05-06 18:16:32,459 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2024-05-06 18:16:32,459 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2024-05-06 18:16:32,459 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2024-05-06 18:16:32,459 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 94 states. [2024-05-06 18:16:32,459 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2024-05-06 18:16:32,459 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2024-05-06 18:16:32,460 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2024-05-06 18:16:32,460 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 67 states. [2024-05-06 18:16:32,460 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 61 states. [2024-05-06 18:16:32,460 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2024-05-06 18:16:32,460 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 70 states. [2024-05-06 18:16:32,473 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Forceful destruction successful, exit code 0 [2024-05-06 18:16:32,670 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 24 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable621 [2024-05-06 18:16:32,671 INFO L420 AbstractCegarLoop]: === Iteration 23 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 2 more)] === [2024-05-06 18:16:32,671 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:16:32,671 INFO L85 PathProgramCache]: Analyzing trace with hash -587716846, now seen corresponding path program 20 times [2024-05-06 18:16:32,672 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:16:32,672 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1627895279] [2024-05-06 18:16:32,672 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:16:32,672 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:16:32,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:16:35,699 INFO L134 CoverageAnalysis]: Checked inductivity of 3836 backedges. 672 proven. 1801 refuted. 0 times theorem prover too weak. 1363 trivial. 0 not checked. [2024-05-06 18:16:35,699 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:16:35,699 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1627895279] [2024-05-06 18:16:35,699 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1627895279] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:16:35,699 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1093212172] [2024-05-06 18:16:35,699 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-05-06 18:16:35,699 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:16:35,699 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:16:35,701 INFO L229 MonitoredProcess]: Starting monitored process 25 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:16:35,702 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2024-05-06 18:16:36,884 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-05-06 18:16:36,884 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-05-06 18:16:36,893 INFO L262 TraceCheckSpWp]: Trace formula consists of 1812 conjuncts, 48 conjunts are in the unsatisfiable core [2024-05-06 18:16:36,899 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 18:16:38,962 INFO L134 CoverageAnalysis]: Checked inductivity of 3836 backedges. 1836 proven. 742 refuted. 0 times theorem prover too weak. 1258 trivial. 0 not checked. [2024-05-06 18:16:38,963 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-06 18:16:41,367 INFO L134 CoverageAnalysis]: Checked inductivity of 3836 backedges. 1620 proven. 958 refuted. 0 times theorem prover too weak. 1258 trivial. 0 not checked. [2024-05-06 18:16:41,367 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1093212172] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-06 18:16:41,367 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-06 18:16:41,368 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48, 48] total 136 [2024-05-06 18:16:41,368 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1853072791] [2024-05-06 18:16:41,368 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-06 18:16:41,369 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 136 states [2024-05-06 18:16:41,369 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:16:41,370 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 136 interpolants. [2024-05-06 18:16:41,371 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2479, Invalid=15881, Unknown=0, NotChecked=0, Total=18360 [2024-05-06 18:16:41,371 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:16:41,372 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:16:41,372 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 136 states, 136 states have (on average 8.227941176470589) internal successors, (1119), 136 states have internal predecessors, (1119), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:16:41,372 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:16:41,372 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:16:41,372 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:16:41,372 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:16:41,372 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:16:41,372 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:16:41,372 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 4 states. [2024-05-06 18:16:41,372 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 29 states. [2024-05-06 18:16:41,372 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 58 states. [2024-05-06 18:16:41,372 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 72 states. [2024-05-06 18:16:41,372 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 81 states. [2024-05-06 18:16:41,373 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 37 states. [2024-05-06 18:16:41,373 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 41 states. [2024-05-06 18:16:41,373 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 48 states. [2024-05-06 18:16:41,373 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 94 states. [2024-05-06 18:16:41,373 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 49 states. [2024-05-06 18:16:41,373 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 53 states. [2024-05-06 18:16:41,373 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 57 states. [2024-05-06 18:16:41,373 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 67 states. [2024-05-06 18:16:41,373 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 61 states. [2024-05-06 18:16:41,373 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 60 states. [2024-05-06 18:16:41,373 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 70 states. [2024-05-06 18:16:41,373 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:16:43,469 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:16:43,470 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:16:43,470 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:16:43,470 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:16:43,470 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:16:43,470 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:16:43,470 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-05-06 18:16:43,470 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2024-05-06 18:16:43,470 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2024-05-06 18:16:43,470 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2024-05-06 18:16:43,470 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 81 states. [2024-05-06 18:16:43,470 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2024-05-06 18:16:43,470 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2024-05-06 18:16:43,470 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2024-05-06 18:16:43,470 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 94 states. [2024-05-06 18:16:43,470 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2024-05-06 18:16:43,470 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2024-05-06 18:16:43,470 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2024-05-06 18:16:43,470 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 67 states. [2024-05-06 18:16:43,470 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 61 states. [2024-05-06 18:16:43,470 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2024-05-06 18:16:43,470 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 70 states. [2024-05-06 18:16:43,471 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2024-05-06 18:16:43,484 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Forceful destruction successful, exit code 0 [2024-05-06 18:16:43,681 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable622,25 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:16:43,682 INFO L420 AbstractCegarLoop]: === Iteration 24 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 2 more)] === [2024-05-06 18:16:43,682 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:16:43,682 INFO L85 PathProgramCache]: Analyzing trace with hash 246017378, now seen corresponding path program 21 times [2024-05-06 18:16:43,682 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:16:43,682 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [21301253] [2024-05-06 18:16:43,682 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:16:43,682 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:16:43,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:16:46,995 INFO L134 CoverageAnalysis]: Checked inductivity of 3949 backedges. 798 proven. 1857 refuted. 0 times theorem prover too weak. 1294 trivial. 0 not checked. [2024-05-06 18:16:46,996 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:16:46,996 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [21301253] [2024-05-06 18:16:46,996 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [21301253] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:16:46,996 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [665055907] [2024-05-06 18:16:46,996 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-05-06 18:16:46,996 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:16:46,996 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:16:47,013 INFO L229 MonitoredProcess]: Starting monitored process 26 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:16:47,016 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2024-05-06 18:17:41,169 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 14 check-sat command(s) [2024-05-06 18:17:41,169 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-05-06 18:17:41,214 INFO L262 TraceCheckSpWp]: Trace formula consists of 1770 conjuncts, 57 conjunts are in the unsatisfiable core [2024-05-06 18:17:41,220 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 18:17:44,950 INFO L134 CoverageAnalysis]: Checked inductivity of 3949 backedges. 1677 proven. 451 refuted. 0 times theorem prover too weak. 1821 trivial. 0 not checked. [2024-05-06 18:17:44,950 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-06 18:17:47,405 INFO L134 CoverageAnalysis]: Checked inductivity of 3949 backedges. 1665 proven. 463 refuted. 0 times theorem prover too weak. 1821 trivial. 0 not checked. [2024-05-06 18:17:47,406 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [665055907] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-06 18:17:47,406 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-06 18:17:47,406 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [51, 56, 43] total 146 [2024-05-06 18:17:47,406 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [418446911] [2024-05-06 18:17:47,406 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-06 18:17:47,407 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 146 states [2024-05-06 18:17:47,407 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:17:47,409 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 146 interpolants. [2024-05-06 18:17:47,411 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2826, Invalid=18344, Unknown=0, NotChecked=0, Total=21170 [2024-05-06 18:17:47,411 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:17:47,412 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:17:47,412 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 146 states, 146 states have (on average 9.472602739726028) internal successors, (1383), 146 states have internal predecessors, (1383), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:17:47,412 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:17:47,412 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:17:47,412 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:17:47,412 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:17:47,413 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:17:47,413 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:17:47,413 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 4 states. [2024-05-06 18:17:47,413 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 29 states. [2024-05-06 18:17:47,413 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 58 states. [2024-05-06 18:17:47,413 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 72 states. [2024-05-06 18:17:47,413 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 81 states. [2024-05-06 18:17:47,413 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 37 states. [2024-05-06 18:17:47,413 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 41 states. [2024-05-06 18:17:47,413 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 48 states. [2024-05-06 18:17:47,413 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 94 states. [2024-05-06 18:17:47,413 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 49 states. [2024-05-06 18:17:47,413 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 53 states. [2024-05-06 18:17:47,413 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 57 states. [2024-05-06 18:17:47,413 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 67 states. [2024-05-06 18:17:47,413 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 61 states. [2024-05-06 18:17:47,413 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 60 states. [2024-05-06 18:17:47,413 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 70 states. [2024-05-06 18:17:47,413 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 65 states. [2024-05-06 18:17:47,413 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:17:55,627 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:17:55,627 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:17:55,627 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:17:55,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:17:55,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:17:55,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:17:55,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-05-06 18:17:55,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2024-05-06 18:17:55,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2024-05-06 18:17:55,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2024-05-06 18:17:55,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 81 states. [2024-05-06 18:17:55,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2024-05-06 18:17:55,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2024-05-06 18:17:55,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2024-05-06 18:17:55,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 94 states. [2024-05-06 18:17:55,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2024-05-06 18:17:55,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2024-05-06 18:17:55,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2024-05-06 18:17:55,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 67 states. [2024-05-06 18:17:55,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 61 states. [2024-05-06 18:17:55,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2024-05-06 18:17:55,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 70 states. [2024-05-06 18:17:55,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2024-05-06 18:17:55,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 147 states. [2024-05-06 18:17:55,649 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Forceful destruction successful, exit code 0 [2024-05-06 18:17:55,844 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 26 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable623 [2024-05-06 18:17:55,844 INFO L420 AbstractCegarLoop]: === Iteration 25 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 2 more)] === [2024-05-06 18:17:55,844 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:17:55,845 INFO L85 PathProgramCache]: Analyzing trace with hash 590671242, now seen corresponding path program 22 times [2024-05-06 18:17:55,845 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:17:55,845 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2099707991] [2024-05-06 18:17:55,845 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:55,845 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:56,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:59,322 INFO L134 CoverageAnalysis]: Checked inductivity of 4628 backedges. 938 proven. 1893 refuted. 0 times theorem prover too weak. 1797 trivial. 0 not checked. [2024-05-06 18:17:59,322 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:17:59,322 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2099707991] [2024-05-06 18:17:59,322 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2099707991] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:17:59,322 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1440372925] [2024-05-06 18:17:59,322 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-05-06 18:17:59,322 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:17:59,322 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:17:59,323 INFO L229 MonitoredProcess]: Starting monitored process 27 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:17:59,325 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Waiting until timeout for monitored process [2024-05-06 18:18:01,990 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-05-06 18:18:01,990 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-05-06 18:18:02,002 INFO L262 TraceCheckSpWp]: Trace formula consists of 1924 conjuncts, 54 conjunts are in the unsatisfiable core [2024-05-06 18:18:02,008 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 18:18:04,446 INFO L134 CoverageAnalysis]: Checked inductivity of 4628 backedges. 1902 proven. 976 refuted. 0 times theorem prover too weak. 1750 trivial. 0 not checked. [2024-05-06 18:18:04,446 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-06 18:18:07,614 INFO L134 CoverageAnalysis]: Checked inductivity of 4628 backedges. 1701 proven. 1177 refuted. 0 times theorem prover too weak. 1750 trivial. 0 not checked. [2024-05-06 18:18:07,615 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1440372925] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-06 18:18:07,615 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-06 18:18:07,615 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 54, 54] total 154 [2024-05-06 18:18:07,615 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1165423805] [2024-05-06 18:18:07,615 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-06 18:18:07,616 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 154 states [2024-05-06 18:18:07,616 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:18:07,618 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 154 interpolants. [2024-05-06 18:18:07,619 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3147, Invalid=20415, Unknown=0, NotChecked=0, Total=23562 [2024-05-06 18:18:07,619 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:18:07,619 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:18:07,620 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 154 states, 154 states have (on average 7.961038961038961) internal successors, (1226), 154 states have internal predecessors, (1226), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:18:07,620 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:18:07,620 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:18:07,620 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:18:07,620 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:18:07,620 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:18:07,620 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:18:07,620 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 4 states. [2024-05-06 18:18:07,620 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 29 states. [2024-05-06 18:18:07,620 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 58 states. [2024-05-06 18:18:07,620 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 72 states. [2024-05-06 18:18:07,620 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 81 states. [2024-05-06 18:18:07,620 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 37 states. [2024-05-06 18:18:07,620 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 41 states. [2024-05-06 18:18:07,620 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 48 states. [2024-05-06 18:18:07,620 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 94 states. [2024-05-06 18:18:07,620 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 49 states. [2024-05-06 18:18:07,621 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 53 states. [2024-05-06 18:18:07,621 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 57 states. [2024-05-06 18:18:07,621 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 67 states. [2024-05-06 18:18:07,621 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 61 states. [2024-05-06 18:18:07,621 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 60 states. [2024-05-06 18:18:07,621 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 70 states. [2024-05-06 18:18:07,621 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 65 states. [2024-05-06 18:18:07,621 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 147 states. [2024-05-06 18:18:07,621 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:18:10,134 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:18:10,134 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:18:10,134 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:18:10,134 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:18:10,134 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:18:10,134 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:18:10,134 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-05-06 18:18:10,134 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2024-05-06 18:18:10,134 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2024-05-06 18:18:10,134 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2024-05-06 18:18:10,134 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 81 states. [2024-05-06 18:18:10,134 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2024-05-06 18:18:10,134 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2024-05-06 18:18:10,134 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2024-05-06 18:18:10,134 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 94 states. [2024-05-06 18:18:10,134 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2024-05-06 18:18:10,135 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2024-05-06 18:18:10,135 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2024-05-06 18:18:10,135 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 67 states. [2024-05-06 18:18:10,135 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 61 states. [2024-05-06 18:18:10,135 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2024-05-06 18:18:10,135 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 70 states. [2024-05-06 18:18:10,135 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2024-05-06 18:18:10,135 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 147 states. [2024-05-06 18:18:10,135 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 73 states. [2024-05-06 18:18:10,150 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Forceful destruction successful, exit code 0 [2024-05-06 18:18:10,348 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 27 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable624 [2024-05-06 18:18:10,348 INFO L420 AbstractCegarLoop]: === Iteration 26 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 2 more)] === [2024-05-06 18:18:10,349 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:18:10,349 INFO L85 PathProgramCache]: Analyzing trace with hash -1349766182, now seen corresponding path program 23 times [2024-05-06 18:18:10,349 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:18:10,349 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [73515257] [2024-05-06 18:18:10,349 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:10,349 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:10,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:14,210 INFO L134 CoverageAnalysis]: Checked inductivity of 4757 backedges. 1092 proven. 1909 refuted. 0 times theorem prover too weak. 1756 trivial. 0 not checked. [2024-05-06 18:18:14,210 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:18:14,210 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [73515257] [2024-05-06 18:18:14,210 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [73515257] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:18:14,210 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [397392670] [2024-05-06 18:18:14,210 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-05-06 18:18:14,210 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:18:14,210 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:18:14,211 INFO L229 MonitoredProcess]: Starting monitored process 28 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:18:14,212 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process Received shutdown request... [2024-05-06 18:19:32,811 WARN L340 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Timeout while monitored process is still running, waiting 1000 ms for graceful end [2024-05-06 18:19:32,830 WARN L340 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 (2)] Timeout while monitored process is still running, waiting 1000 ms for graceful end [2024-05-06 18:19:32,831 WARN L340 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Timeout while monitored process is still running, waiting 1000 ms for graceful end [2024-05-06 18:19:33,862 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 (2)] Ended with exit code 0 [2024-05-06 18:19:34,011 WARN L435 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Forcibly destroying the process [2024-05-06 18:19:34,021 WARN L311 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2024-05-06 18:19:34,021 INFO L185 FreeRefinementEngine]: Found 0 perfect and 1 imperfect interpolant sequences. [2024-05-06 18:19:34,021 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [57] total 57 [2024-05-06 18:19:34,021 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [461545479] [2024-05-06 18:19:34,021 INFO L85 oduleStraightlineAll]: Using 1 imperfect interpolants to construct interpolant automaton [2024-05-06 18:19:34,022 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 57 states [2024-05-06 18:19:34,022 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:19:34,023 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2024-05-06 18:19:34,023 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=496, Invalid=2696, Unknown=0, NotChecked=0, Total=3192 [2024-05-06 18:19:34,023 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:19:34,023 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:19:34,024 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 57 states, 57 states have (on average 9.631578947368421) internal successors, (549), 57 states have internal predecessors, (549), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:19:34,024 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 13 states. [2024-05-06 18:19:34,024 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 42 states. [2024-05-06 18:19:34,024 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 8 states. [2024-05-06 18:19:34,024 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 50 states. [2024-05-06 18:19:34,024 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 59 states. [2024-05-06 18:19:34,024 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 31 states. [2024-05-06 18:19:34,024 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 4 states. [2024-05-06 18:19:34,024 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 29 states. [2024-05-06 18:19:34,024 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 58 states. [2024-05-06 18:19:34,024 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 72 states. [2024-05-06 18:19:34,024 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 81 states. [2024-05-06 18:19:34,024 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 37 states. [2024-05-06 18:19:34,024 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 41 states. [2024-05-06 18:19:34,024 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 48 states. [2024-05-06 18:19:34,024 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 94 states. [2024-05-06 18:19:34,024 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 49 states. [2024-05-06 18:19:34,024 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 53 states. [2024-05-06 18:19:34,024 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 57 states. [2024-05-06 18:19:34,024 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 67 states. [2024-05-06 18:19:34,024 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 61 states. [2024-05-06 18:19:34,024 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 60 states. [2024-05-06 18:19:34,025 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 70 states. [2024-05-06 18:19:34,025 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 65 states. [2024-05-06 18:19:34,025 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 147 states. [2024-05-06 18:19:34,025 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 73 states. [2024-05-06 18:19:34,025 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:19:34,035 WARN L435 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Forcibly destroying the process [2024-05-06 18:19:34,035 WARN L435 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Forcibly destroying the process [2024-05-06 18:19:34,036 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable625,28 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:19:34,036 WARN L619 AbstractCegarLoop]: Verification canceled: while executing DepthFirstTraversal. [2024-05-06 18:19:34,038 INFO L805 garLoopResultBuilder]: Registering result TIMEOUT for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (4 of 5 remaining) [2024-05-06 18:19:34,038 INFO L805 garLoopResultBuilder]: Registering result TIMEOUT for location ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (3 of 5 remaining) [2024-05-06 18:19:34,039 INFO L805 garLoopResultBuilder]: Registering result TIMEOUT for location ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (2 of 5 remaining) [2024-05-06 18:19:34,039 INFO L805 garLoopResultBuilder]: Registering result TIMEOUT for location ULTIMATE.startErr2INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (1 of 5 remaining) [2024-05-06 18:19:34,039 INFO L805 garLoopResultBuilder]: Registering result TIMEOUT for location ULTIMATE.startErr3INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (0 of 5 remaining) [2024-05-06 18:19:34,043 INFO L448 BasicCegarLoop]: Path program histogram: [182, 23, 10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 3, 2, 2, 1, 1, 1, 1] [2024-05-06 18:19:34,046 INFO L228 ceAbstractionStarter]: Analysis of concurrent program completed with 1 thread instances [2024-05-06 18:19:34,046 INFO L178 ceAbstractionStarter]: Computing trace abstraction results [2024-05-06 18:19:34,048 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 06.05 06:19:34 BasicIcfg [2024-05-06 18:19:34,048 INFO L131 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2024-05-06 18:19:34,049 INFO L158 Benchmark]: Toolchain (without parser) took 827731.45ms. Allocated memory was 155.2MB in the beginning and 2.7GB in the end (delta: 2.6GB). Free memory was 84.7MB in the beginning and 904.1MB in the end (delta: -819.4MB). Peak memory consumption was 1.8GB. Max. memory is 8.0GB. [2024-05-06 18:19:34,049 INFO L158 Benchmark]: CDTParser took 0.09ms. Allocated memory is still 155.2MB. Free memory is still 86.8MB. There was no memory consumed. Max. memory is 8.0GB. [2024-05-06 18:19:34,053 INFO L158 Benchmark]: CACSL2BoogieTranslator took 225.69ms. Allocated memory was 155.2MB in the beginning and 244.3MB in the end (delta: 89.1MB). Free memory was 84.6MB in the beginning and 210.8MB in the end (delta: -126.2MB). Peak memory consumption was 17.0MB. Max. memory is 8.0GB. [2024-05-06 18:19:34,053 INFO L158 Benchmark]: Boogie Procedure Inliner took 39.88ms. Allocated memory is still 244.3MB. Free memory was 210.8MB in the beginning and 208.1MB in the end (delta: 2.6MB). Peak memory consumption was 2.1MB. Max. memory is 8.0GB. [2024-05-06 18:19:34,053 INFO L158 Benchmark]: Boogie Preprocessor took 29.58ms. Allocated memory is still 244.3MB. Free memory was 208.1MB in the beginning and 205.5MB in the end (delta: 2.6MB). Peak memory consumption was 3.1MB. Max. memory is 8.0GB. [2024-05-06 18:19:34,057 INFO L158 Benchmark]: RCFGBuilder took 746.28ms. Allocated memory is still 244.3MB. Free memory was 205.5MB in the beginning and 146.8MB in the end (delta: 58.7MB). Peak memory consumption was 58.7MB. Max. memory is 8.0GB. [2024-05-06 18:19:34,057 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Forceful destruction successful, exit code 137 [2024-05-06 18:19:34,058 INFO L158 Benchmark]: TraceAbstraction took 826670.86ms. Allocated memory was 244.3MB in the beginning and 2.7GB in the end (delta: 2.5GB). Free memory was 145.8MB in the beginning and 904.1MB in the end (delta: -758.4MB). Peak memory consumption was 1.7GB. Max. memory is 8.0GB. [2024-05-06 18:19:34,059 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.09ms. Allocated memory is still 155.2MB. Free memory is still 86.8MB. There was no memory consumed. Max. memory is 8.0GB. * CACSL2BoogieTranslator took 225.69ms. Allocated memory was 155.2MB in the beginning and 244.3MB in the end (delta: 89.1MB). Free memory was 84.6MB in the beginning and 210.8MB in the end (delta: -126.2MB). Peak memory consumption was 17.0MB. Max. memory is 8.0GB. * Boogie Procedure Inliner took 39.88ms. Allocated memory is still 244.3MB. Free memory was 210.8MB in the beginning and 208.1MB in the end (delta: 2.6MB). Peak memory consumption was 2.1MB. Max. memory is 8.0GB. * Boogie Preprocessor took 29.58ms. Allocated memory is still 244.3MB. Free memory was 208.1MB in the beginning and 205.5MB in the end (delta: 2.6MB). Peak memory consumption was 3.1MB. Max. memory is 8.0GB. * RCFGBuilder took 746.28ms. Allocated memory is still 244.3MB. Free memory was 205.5MB in the beginning and 146.8MB in the end (delta: 58.7MB). Peak memory consumption was 58.7MB. Max. memory is 8.0GB. * TraceAbstraction took 826670.86ms. Allocated memory was 244.3MB in the beginning and 2.7GB in the end (delta: 2.5GB). Free memory was 145.8MB in the beginning and 904.1MB in the end (delta: -758.4MB). Peak memory consumption was 1.7GB. Max. memory is 8.0GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Independence relation #1 benchmarks ThreadSeparatingIndependenceRelation.Independence Queries: [ total: 2646626, independent: 2522459, independent conditional: 2478609, independent unconditional: 43850, dependent: 124167, dependent conditional: 123582, dependent unconditional: 585, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ThreadSeparatingIndependenceRelation.Statistics on underlying relation: UnionIndependenceRelation.Independence Queries: [ total: 2545814, independent: 2522459, independent conditional: 2478609, independent unconditional: 43850, dependent: 23355, dependent conditional: 22770, dependent unconditional: 585, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , UnionIndependenceRelation.Statistics on underlying relations: [ ConditionTransformingIndependenceRelation.Independence Queries: [ total: 2545814, independent: 2522459, independent conditional: 2478609, independent unconditional: 43850, dependent: 23355, dependent conditional: 22770, dependent unconditional: 585, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ConditionTransformingIndependenceRelation.Statistics on underlying relation: DisjunctiveConditionalIndependenceRelation.Independence Queries: [ total: 2545814, independent: 2522459, independent conditional: 2478609, independent unconditional: 43850, dependent: 23355, dependent conditional: 22770, dependent unconditional: 585, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , DisjunctiveConditionalIndependenceRelation.Statistics on underlying relation: ConditionTransformingIndependenceRelation.Independence Queries: [ total: 2649194, independent: 2522459, independent conditional: 1123265, independent unconditional: 1399194, dependent: 126735, dependent conditional: 97395, dependent unconditional: 29340, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ConditionTransformingIndependenceRelation.Statistics on underlying relation: SemanticConditionEliminator.Independence Queries: [ total: 2649194, independent: 2522459, independent conditional: 614658, independent unconditional: 1907801, dependent: 126735, dependent conditional: 63098, dependent unconditional: 63637, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , SemanticConditionEliminator.Statistics on underlying relation: CachedIndependenceRelation.Independence Queries: [ total: 2649194, independent: 2522459, independent conditional: 614658, independent unconditional: 1907801, dependent: 126735, dependent conditional: 63098, dependent unconditional: 63637, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , CachedIndependenceRelation.Statistics on underlying relation: UnionIndependenceRelation.Independence Queries: [ total: 1331, independent: 1128, independent conditional: 8, independent unconditional: 1120, dependent: 203, dependent conditional: 191, dependent unconditional: 12, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , UnionIndependenceRelation.Statistics on underlying relations: [ SyntacticIndependenceRelation.Independence Queries: [ total: 1331, independent: 1121, independent conditional: 0, independent unconditional: 1121, dependent: 210, dependent conditional: 0, dependent unconditional: 210, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ProtectedIndependenceRelation.Independence Queries: [ total: 210, independent: 7, independent conditional: 5, independent unconditional: 2, dependent: 203, dependent conditional: 191, dependent unconditional: 12, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ProtectedIndependenceRelation.Statistics on underlying relation: SemanticIndependenceRelation.Independence Queries: [ total: 210, independent: 7, independent conditional: 5, independent unconditional: 2, dependent: 203, dependent conditional: 191, dependent unconditional: 12, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , SemanticIndependenceRelation.Query Time [ms]: [ total: 513, independent: 25, independent conditional: 19, independent unconditional: 6, dependent: 489, dependent conditional: 407, dependent unconditional: 81, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , Protected Queries: 0 ], Cache Queries: [ total: 2649194, independent: 2521331, independent conditional: 614650, independent unconditional: 1906681, dependent: 126532, dependent conditional: 62907, dependent unconditional: 63625, unknown: 1331, unknown conditional: 199, unknown unconditional: 1132] , Statistics on independence cache: Total cache size (in pairs): 1331, Positive cache size: 1128, Positive conditional cache size: 8, Positive unconditional cache size: 1120, Negative cache size: 203, Negative conditional cache size: 191, Negative unconditional cache size: 12, Unknown cache size: 0, Unknown conditional cache size: 0, Unknown unconditional cache size: 0, Eliminated conditions: 542904, Maximal queried relation: 13, ConditionTransformingIndependenceRelation.Independence Queries: [ total: 2649194, independent: 2522459, independent conditional: 1123265, independent unconditional: 1399194, dependent: 126735, dependent conditional: 97395, dependent unconditional: 29340, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ConditionTransformingIndependenceRelation.Statistics on underlying relation: SemanticConditionEliminator.Independence Queries: [ total: 2649194, independent: 2522459, independent conditional: 614658, independent unconditional: 1907801, dependent: 126735, dependent conditional: 63098, dependent unconditional: 63637, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , SemanticConditionEliminator.Statistics on underlying relation: CachedIndependenceRelation.Independence Queries: [ total: 2649194, independent: 2522459, independent conditional: 614658, independent unconditional: 1907801, dependent: 126735, dependent conditional: 63098, dependent unconditional: 63637, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , CachedIndependenceRelation.Statistics on underlying relation: UnionIndependenceRelation.Independence Queries: [ total: 1331, independent: 1128, independent conditional: 8, independent unconditional: 1120, dependent: 203, dependent conditional: 191, dependent unconditional: 12, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , UnionIndependenceRelation.Statistics on underlying relations: [ SyntacticIndependenceRelation.Independence Queries: [ total: 1331, independent: 1121, independent conditional: 0, independent unconditional: 1121, dependent: 210, dependent conditional: 0, dependent unconditional: 210, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ProtectedIndependenceRelation.Independence Queries: [ total: 210, independent: 7, independent conditional: 5, independent unconditional: 2, dependent: 203, dependent conditional: 191, dependent unconditional: 12, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ProtectedIndependenceRelation.Statistics on underlying relation: SemanticIndependenceRelation.Independence Queries: [ total: 210, independent: 7, independent conditional: 5, independent unconditional: 2, dependent: 203, dependent conditional: 191, dependent unconditional: 12, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , SemanticIndependenceRelation.Query Time [ms]: [ total: 513, independent: 25, independent conditional: 19, independent unconditional: 6, dependent: 489, dependent conditional: 407, dependent unconditional: 81, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , Protected Queries: 0 ], Cache Queries: [ total: 2649194, independent: 2521331, independent conditional: 614650, independent unconditional: 1906681, dependent: 126532, dependent conditional: 62907, dependent unconditional: 63625, unknown: 1331, unknown conditional: 199, unknown unconditional: 1132] , Statistics on independence cache: Total cache size (in pairs): 1331, Positive cache size: 1128, Positive conditional cache size: 8, Positive unconditional cache size: 1120, Negative cache size: 203, Negative conditional cache size: 191, Negative unconditional cache size: 12, Unknown cache size: 0, Unknown conditional cache size: 0, Unknown unconditional cache size: 0, Eliminated conditions: 542904 ], Independence queries for same thread: 100812 - TimeoutResultAtElement [Line: 155]: Timeout (TraceAbstraction) Unable to prove that a call to reach_error is unreachable Cancelled while executing DepthFirstTraversal. - TimeoutResultAtElement [Line: 148]: Timeout (TraceAbstraction) Unable to prove that petrification did provide enough thread instances (tool internal message) Cancelled while executing DepthFirstTraversal. - TimeoutResultAtElement [Line: 147]: Timeout (TraceAbstraction) Unable to prove that petrification did provide enough thread instances (tool internal message) Cancelled while executing DepthFirstTraversal. - TimeoutResultAtElement [Line: 145]: Timeout (TraceAbstraction) Unable to prove that petrification did provide enough thread instances (tool internal message) Cancelled while executing DepthFirstTraversal. - TimeoutResultAtElement [Line: 146]: Timeout (TraceAbstraction) Unable to prove that petrification did provide enough thread instances (tool internal message) Cancelled while executing DepthFirstTraversal. - StatisticsResult: Ultimate Automizer benchmark data with 1 thread instances CFG has 9 procedures, 287 locations, 5 error locations. Started 1 CEGAR loops. OverallTime: 826.5s, OverallIterations: 26, TraceHistogramMax: 0, PathProgramHistogramMax: 182, EmptinessCheckTime: 376.8s, AutomataDifference: 0.0s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: , PredicateUnifierStatistics: No data available, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=0occurred in iteration=0, InterpolantAutomatonStates: 1371, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: No data available, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 1.8s SsaConstructionTime, 238.6s SatisfiabilityAnalysisTime, 102.1s InterpolantComputationTime, 27993 NumberOfCodeBlocks, 27434 NumberOfCodeBlocksAsserted, 170 NumberOfCheckSat, 40692 ConstructedInterpolants, 0 QuantifiedInterpolants, 175711 SizeOfPredicates, 473 NumberOfNonLiveVariables, 32911 ConjunctsInSsa, 758 ConjunctsInUnsatCore, 74 InterpolantComputations, 2 PerfectInterpolantSequences, 118504/155636 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available, ConditionalCommutativityCheckTime: 305.6s, ConditionalCommutativityIAIntegrations: 0, ConditionalCommutativityDFSRestarts: 3, ConditionalCommutativityConditionCalculations: 300, ConditionalCommutativityTraceChecks: 300, ConditionalCommutativityImperfectProofs: 297 RESULT: Ultimate could not prove your program: Timeout Completed graceful shutdown