/root/.sdkman/candidates/java/current/bin/java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data -s ../benchexec/../../../trunk/examples/settings/gemcutter/NewStatesSleep.epf --traceabstraction.dfs.order.used.in.por LOOP_LOCKSTEP --traceabstraction.additional.conditional.commutativity.checking DFS --traceabstraction.criterion.for.conditional.commutativity.checking DEFAULT --traceabstraction.use.limited.checks.recommended.for.dfs true --traceabstraction.limit.for.limited.checks 50 -tc ../benchexec/../../../trunk/examples/toolchains/AutomizerCInline.xml -i ../../../trunk/examples/svcomp/weaver/popl20-more-vector-add.wvr.c -------------------------------------------------------------------------------- This is Ultimate 0.2.4-wip.dk.conditional-comm-17da818-m [2024-05-06 18:17:29,688 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-05-06 18:17:29,730 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/../benchexec/../../../trunk/examples/settings/gemcutter/NewStatesSleep.epf [2024-05-06 18:17:29,733 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-05-06 18:17:29,734 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-05-06 18:17:29,745 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-05-06 18:17:29,746 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-05-06 18:17:29,746 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-05-06 18:17:29,747 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2024-05-06 18:17:29,747 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2024-05-06 18:17:29,747 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-05-06 18:17:29,747 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-05-06 18:17:29,748 INFO L153 SettingsManager]: * Use SBE=true [2024-05-06 18:17:29,748 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-05-06 18:17:29,748 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2024-05-06 18:17:29,748 INFO L153 SettingsManager]: * sizeof long=4 [2024-05-06 18:17:29,749 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-05-06 18:17:29,749 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-05-06 18:17:29,749 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-05-06 18:17:29,749 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2024-05-06 18:17:29,750 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2024-05-06 18:17:29,750 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2024-05-06 18:17:29,750 INFO L153 SettingsManager]: * sizeof long double=12 [2024-05-06 18:17:29,759 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-05-06 18:17:29,759 INFO L153 SettingsManager]: * Use constant arrays=true [2024-05-06 18:17:29,759 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-05-06 18:17:29,760 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-05-06 18:17:29,760 INFO L153 SettingsManager]: * To the following directory=./dump/ [2024-05-06 18:17:29,760 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-05-06 18:17:29,760 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2024-05-06 18:17:29,761 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-05-06 18:17:29,761 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2024-05-06 18:17:29,761 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2024-05-06 18:17:29,761 INFO L153 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2024-05-06 18:17:29,761 INFO L153 SettingsManager]: * Partial Order Reduction in concurrent analysis=SLEEP_NEW_STATES [2024-05-06 18:17:29,762 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2024-05-06 18:17:29,762 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-05-06 18:17:29,762 INFO L153 SettingsManager]: * Automaton type used in concurrency analysis=PARTIAL_ORDER_FA [2024-05-06 18:17:29,762 INFO L153 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2024-05-06 18:17:29,762 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: DFS Order used in POR -> LOOP_LOCKSTEP Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Additional conditional commutativity checking -> DFS Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Criterion for conditional commutativity checking -> DEFAULT Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: use limited checks (recommended for DFS) -> true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Limit for limited checks -> 50 [2024-05-06 18:17:29,901 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-05-06 18:17:29,915 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-05-06 18:17:29,916 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-05-06 18:17:29,917 INFO L270 PluginConnector]: Initializing CDTParser... [2024-05-06 18:17:29,917 INFO L274 PluginConnector]: CDTParser initialized [2024-05-06 18:17:29,918 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/../../../trunk/examples/svcomp/weaver/popl20-more-vector-add.wvr.c [2024-05-06 18:17:31,118 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-05-06 18:17:31,278 INFO L384 CDTParser]: Found 1 translation units. [2024-05-06 18:17:31,278 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/weaver/popl20-more-vector-add.wvr.c [2024-05-06 18:17:31,284 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/data/25b7fe32e/fbb99f526749425daf8b64645f65e9ad/FLAG91415a3b3 [2024-05-06 18:17:31,293 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/data/25b7fe32e/fbb99f526749425daf8b64645f65e9ad [2024-05-06 18:17:31,295 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-05-06 18:17:31,296 INFO L133 ToolchainWalker]: Walking toolchain with 5 elements. [2024-05-06 18:17:31,297 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-05-06 18:17:31,297 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-05-06 18:17:31,300 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-05-06 18:17:31,301 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.05 06:17:31" (1/1) ... [2024-05-06 18:17:31,301 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5598b270 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:17:31, skipping insertion in model container [2024-05-06 18:17:31,302 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.05 06:17:31" (1/1) ... [2024-05-06 18:17:31,318 INFO L177 MainTranslator]: Built tables and reachable declarations [2024-05-06 18:17:31,443 WARN L240 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/weaver/popl20-more-vector-add.wvr.c[2598,2611] [2024-05-06 18:17:31,474 INFO L209 PostProcessor]: Analyzing one entry point: main [2024-05-06 18:17:31,481 INFO L202 MainTranslator]: Completed pre-run [2024-05-06 18:17:31,503 WARN L240 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/weaver/popl20-more-vector-add.wvr.c[2598,2611] [2024-05-06 18:17:31,506 INFO L209 PostProcessor]: Analyzing one entry point: main [2024-05-06 18:17:31,517 INFO L206 MainTranslator]: Completed translation [2024-05-06 18:17:31,519 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:17:31 WrapperNode [2024-05-06 18:17:31,519 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-05-06 18:17:31,520 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-05-06 18:17:31,520 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-05-06 18:17:31,520 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-05-06 18:17:31,525 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:17:31" (1/1) ... [2024-05-06 18:17:31,531 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:17:31" (1/1) ... [2024-05-06 18:17:31,550 INFO L138 Inliner]: procedures = 25, calls = 46, calls flagged for inlining = 11, calls inlined = 17, statements flattened = 203 [2024-05-06 18:17:31,550 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-05-06 18:17:31,551 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-05-06 18:17:31,551 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-05-06 18:17:31,551 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-05-06 18:17:31,558 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:17:31" (1/1) ... [2024-05-06 18:17:31,558 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:17:31" (1/1) ... [2024-05-06 18:17:31,561 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:17:31" (1/1) ... [2024-05-06 18:17:31,561 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:17:31" (1/1) ... [2024-05-06 18:17:31,572 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:17:31" (1/1) ... [2024-05-06 18:17:31,576 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:17:31" (1/1) ... [2024-05-06 18:17:31,577 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:17:31" (1/1) ... [2024-05-06 18:17:31,578 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:17:31" (1/1) ... [2024-05-06 18:17:31,580 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-05-06 18:17:31,581 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-05-06 18:17:31,581 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-05-06 18:17:31,581 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-05-06 18:17:31,582 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:17:31" (1/1) ... [2024-05-06 18:17:31,588 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2024-05-06 18:17:31,602 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:17:31,613 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2024-05-06 18:17:31,615 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2024-05-06 18:17:31,649 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-05-06 18:17:31,649 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2024-05-06 18:17:31,649 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2024-05-06 18:17:31,650 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2024-05-06 18:17:31,650 INFO L130 BoogieDeclarations]: Found specification of procedure thread1 [2024-05-06 18:17:31,650 INFO L138 BoogieDeclarations]: Found implementation of procedure thread1 [2024-05-06 18:17:31,650 INFO L130 BoogieDeclarations]: Found specification of procedure thread2 [2024-05-06 18:17:31,650 INFO L138 BoogieDeclarations]: Found implementation of procedure thread2 [2024-05-06 18:17:31,650 INFO L130 BoogieDeclarations]: Found specification of procedure thread3 [2024-05-06 18:17:31,650 INFO L138 BoogieDeclarations]: Found implementation of procedure thread3 [2024-05-06 18:17:31,650 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2024-05-06 18:17:31,650 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2024-05-06 18:17:31,650 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-05-06 18:17:31,650 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-05-06 18:17:31,650 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2024-05-06 18:17:31,651 WARN L213 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to OneNontrivialStatement [2024-05-06 18:17:31,720 INFO L241 CfgBuilder]: Building ICFG [2024-05-06 18:17:31,722 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2024-05-06 18:17:31,999 INFO L282 CfgBuilder]: Performing block encoding [2024-05-06 18:17:32,009 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-05-06 18:17:32,009 INFO L309 CfgBuilder]: Removed 7 assume(true) statements. [2024-05-06 18:17:32,011 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.05 06:17:32 BoogieIcfgContainer [2024-05-06 18:17:32,011 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-05-06 18:17:32,012 INFO L112 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2024-05-06 18:17:32,012 INFO L270 PluginConnector]: Initializing TraceAbstraction... [2024-05-06 18:17:32,014 INFO L274 PluginConnector]: TraceAbstraction initialized [2024-05-06 18:17:32,015 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 06.05 06:17:31" (1/3) ... [2024-05-06 18:17:32,015 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@39504f07 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.05 06:17:32, skipping insertion in model container [2024-05-06 18:17:32,015 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 06:17:31" (2/3) ... [2024-05-06 18:17:32,015 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@39504f07 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.05 06:17:32, skipping insertion in model container [2024-05-06 18:17:32,015 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.05 06:17:32" (3/3) ... [2024-05-06 18:17:32,016 INFO L112 eAbstractionObserver]: Analyzing ICFG popl20-more-vector-add.wvr.c [2024-05-06 18:17:32,021 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2024-05-06 18:17:32,028 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2024-05-06 18:17:32,028 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2024-05-06 18:17:32,028 INFO L514 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2024-05-06 18:17:32,077 INFO L144 ThreadInstanceAdder]: Constructed 3 joinOtherThreadTransitions. [2024-05-06 18:17:32,111 INFO L100 denceProviderFactory]: Independence Relation #1: [IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=true, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2024-05-06 18:17:32,112 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 [2024-05-06 18:17:32,112 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:17:32,114 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 (exit command is (exit), workingDir is null) [2024-05-06 18:17:32,128 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 (2)] Waiting until timeout for monitored process [2024-05-06 18:17:32,157 INFO L188 artialOrderCegarLoop]: Running PartialOrderCegarLoop with 1 independence relations. [2024-05-06 18:17:32,166 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:17:32,167 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2024-05-06 18:17:32,172 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=PARTIAL_ORDER_FA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopHeads, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@634de0f8, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms], mConComChecker=DFS, mConComCheckerCriterion=DEFAULT, mConComCheckerLimitedChecksCriterion=true, mConComCheckerCriterionLimit=50, mConComCheckerRandomProb=100, mConComCheckerRandomSeed=123, mConComCheckerConditionCriterion=false [2024-05-06 18:17:32,173 INFO L358 AbstractCegarLoop]: Starting to check reachability of 4 error locations. [2024-05-06 18:17:32,412 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:17:34,494 INFO L85 PathProgramCache]: Analyzing trace with hash 1002899142, now seen corresponding path program 1 times [2024-05-06 18:17:34,499 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:34,499 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:34,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:34,884 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:17:34,885 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:34,885 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:34,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:35,016 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:17:35,037 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-05-06 18:17:35,037 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-05-06 18:17:35,143 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:17:37,213 INFO L85 PathProgramCache]: Analyzing trace with hash -1910069838, now seen corresponding path program 1 times [2024-05-06 18:17:37,214 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:37,214 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:37,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:37,555 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 18:17:37,555 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:37,555 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:37,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:37,851 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 18:17:37,852 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-05-06 18:17:37,852 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2024-05-06 18:17:38,064 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:17:40,137 INFO L85 PathProgramCache]: Analyzing trace with hash 320810677, now seen corresponding path program 1 times [2024-05-06 18:17:40,138 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:40,138 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:40,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:40,468 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:17:40,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:40,469 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:40,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:40,674 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:17:40,714 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:17:40,804 INFO L85 PathProgramCache]: Analyzing trace with hash 1335141641, now seen corresponding path program 1 times [2024-05-06 18:17:40,805 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:40,805 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:40,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:41,051 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:17:41,052 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:41,052 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:41,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:41,288 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:17:41,316 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:17:43,400 INFO L85 PathProgramCache]: Analyzing trace with hash -1560281370, now seen corresponding path program 2 times [2024-05-06 18:17:43,400 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:43,400 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:43,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:43,595 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:17:43,596 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:43,596 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:43,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:43,810 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:17:43,841 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 473 treesize of output 449 [2024-05-06 18:17:44,106 INFO L85 PathProgramCache]: Analyzing trace with hash -1124081493, now seen corresponding path program 3 times [2024-05-06 18:17:44,106 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:44,107 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:44,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:44,275 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:17:44,275 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:44,275 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:44,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:44,505 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:17:44,528 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:17:46,593 INFO L85 PathProgramCache]: Analyzing trace with hash 1730535696, now seen corresponding path program 2 times [2024-05-06 18:17:46,593 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:46,593 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:46,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:46,742 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:17:46,742 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:46,743 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:46,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:46,943 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:17:46,965 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:17:47,084 INFO L85 PathProgramCache]: Analyzing trace with hash -1560300495, now seen corresponding path program 4 times [2024-05-06 18:17:47,085 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:47,085 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:47,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:47,214 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:17:47,215 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:47,215 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:47,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:47,362 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:17:47,387 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:17:47,477 INFO L85 PathProgramCache]: Analyzing trace with hash 1335123821, now seen corresponding path program 5 times [2024-05-06 18:17:47,477 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:47,477 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:47,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:47,615 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:17:47,616 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:47,616 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:47,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:47,767 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:17:47,801 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:17:47,873 INFO L85 PathProgramCache]: Analyzing trace with hash -1850681211, now seen corresponding path program 6 times [2024-05-06 18:17:47,874 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:47,874 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:47,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:48,008 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:17:48,009 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:48,009 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:48,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:48,129 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:17:48,173 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:17:48,277 INFO L85 PathProgramCache]: Analyzing trace with hash -1536541959, now seen corresponding path program 7 times [2024-05-06 18:17:48,278 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:48,278 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:48,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:48,422 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:17:48,423 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:48,423 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:48,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:48,536 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:17:48,552 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 972 treesize of output 924 [2024-05-06 18:17:50,673 INFO L85 PathProgramCache]: Analyzing trace with hash -388159737, now seen corresponding path program 8 times [2024-05-06 18:17:50,673 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:50,673 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:50,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:50,834 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:17:50,834 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:50,835 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:50,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:50,953 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:17:50,975 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:17:51,103 INFO L85 PathProgramCache]: Analyzing trace with hash -1536532254, now seen corresponding path program 9 times [2024-05-06 18:17:51,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:51,104 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:51,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:51,238 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:17:51,239 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:51,242 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:51,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:51,359 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:17:51,379 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:17:51,472 INFO L85 PathProgramCache]: Analyzing trace with hash -1850669271, now seen corresponding path program 10 times [2024-05-06 18:17:51,473 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:51,473 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:51,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:51,582 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:17:51,583 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:51,583 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:51,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:51,741 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:17:51,767 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:17:53,811 INFO L85 PathProgramCache]: Analyzing trace with hash -2092560529, now seen corresponding path program 1 times [2024-05-06 18:17:53,811 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:53,811 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:53,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:53,967 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:17:53,967 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:53,967 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:53,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:54,094 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:17:54,124 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:17:54,200 INFO L85 PathProgramCache]: Analyzing trace with hash 191230787, now seen corresponding path program 1 times [2024-05-06 18:17:54,200 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:54,200 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:54,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:54,361 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:17:54,362 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:54,363 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:54,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:54,494 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:17:54,518 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:17:54,591 INFO L85 PathProgramCache]: Analyzing trace with hash 1633187820, now seen corresponding path program 2 times [2024-05-06 18:17:54,591 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:54,591 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:54,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:54,763 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:17:54,763 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:54,763 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:54,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:54,902 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:17:54,918 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 952 treesize of output 904 [2024-05-06 18:17:57,047 INFO L85 PathProgramCache]: Analyzing trace with hash -910784411, now seen corresponding path program 3 times [2024-05-06 18:17:57,048 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:57,048 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:57,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:57,161 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:17:57,161 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:57,162 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:57,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:57,275 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:17:57,349 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:17:59,402 INFO L85 PathProgramCache]: Analyzing trace with hash -682835510, now seen corresponding path program 2 times [2024-05-06 18:17:59,402 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:59,403 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:59,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:59,518 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:17:59,518 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:59,518 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:59,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:59,634 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:17:59,652 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:17:59,721 INFO L85 PathProgramCache]: Analyzing trace with hash 1633168695, now seen corresponding path program 4 times [2024-05-06 18:17:59,721 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:59,721 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:59,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:17:59,835 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:17:59,836 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:17:59,836 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:17:59,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:00,012 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:00,032 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:18:00,098 INFO L85 PathProgramCache]: Analyzing trace with hash 191212967, now seen corresponding path program 5 times [2024-05-06 18:18:00,098 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:00,098 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:00,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:00,210 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:00,210 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:00,210 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:00,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:00,324 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:00,350 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:18:02,405 INFO L85 PathProgramCache]: Analyzing trace with hash -615137013, now seen corresponding path program 6 times [2024-05-06 18:18:02,405 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:02,405 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:02,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:02,558 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:02,559 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:02,559 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:02,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:02,663 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:02,686 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:18:02,775 INFO L85 PathProgramCache]: Analyzing trace with hash -1889377485, now seen corresponding path program 7 times [2024-05-06 18:18:02,776 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:02,776 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:02,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:02,950 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:02,951 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:02,951 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:02,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:03,117 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:03,134 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 952 treesize of output 904 [2024-05-06 18:18:04,494 INFO L85 PathProgramCache]: Analyzing trace with hash 1558840845, now seen corresponding path program 8 times [2024-05-06 18:18:04,495 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:04,495 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:04,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:04,626 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:04,626 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:04,627 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:04,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:04,754 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:04,773 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:18:04,864 INFO L85 PathProgramCache]: Analyzing trace with hash -1889367780, now seen corresponding path program 9 times [2024-05-06 18:18:04,864 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:04,865 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:04,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:04,970 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:04,971 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:04,971 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:04,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:05,073 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:05,094 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:18:05,163 INFO L85 PathProgramCache]: Analyzing trace with hash -615125073, now seen corresponding path program 10 times [2024-05-06 18:18:05,164 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:05,164 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:05,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:05,332 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:05,333 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:05,333 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:05,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:05,437 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:05,460 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:18:07,503 INFO L85 PathProgramCache]: Analyzing trace with hash 1007960118, now seen corresponding path program 1 times [2024-05-06 18:18:07,504 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:07,504 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:07,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:07,613 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:18:07,614 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:07,614 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:07,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:07,724 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:18:07,753 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:18:07,822 INFO L85 PathProgramCache]: Analyzing trace with hash -525238, now seen corresponding path program 1 times [2024-05-06 18:18:07,822 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:07,822 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:07,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:07,991 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:07,991 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:07,991 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:08,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:08,095 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:08,114 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:18:08,176 INFO L85 PathProgramCache]: Analyzing trace with hash -16281659, now seen corresponding path program 2 times [2024-05-06 18:18:08,176 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:08,177 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:08,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:08,282 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:08,282 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:08,282 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:08,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:08,390 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:08,407 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 1930 treesize of output 1834 [2024-05-06 18:18:10,552 INFO L85 PathProgramCache]: Analyzing trace with hash -504730708, now seen corresponding path program 3 times [2024-05-06 18:18:10,552 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:10,552 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:10,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:10,662 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:10,662 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:10,662 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:10,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:10,873 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:10,893 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:18:12,931 INFO L85 PathProgramCache]: Analyzing trace with hash -1877282159, now seen corresponding path program 2 times [2024-05-06 18:18:12,931 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:12,931 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:12,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:13,038 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:13,038 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:13,039 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:13,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:13,145 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:13,163 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:18:13,240 INFO L85 PathProgramCache]: Analyzing trace with hash -16300784, now seen corresponding path program 4 times [2024-05-06 18:18:13,240 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:13,241 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:13,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:13,342 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:13,342 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:13,342 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:13,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:13,501 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:13,522 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:18:15,587 INFO L85 PathProgramCache]: Analyzing trace with hash -543058, now seen corresponding path program 5 times [2024-05-06 18:18:15,588 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:15,588 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:15,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:15,717 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:15,717 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:15,717 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:15,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:15,835 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:15,861 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:18:15,936 INFO L85 PathProgramCache]: Analyzing trace with hash 1087317028, now seen corresponding path program 6 times [2024-05-06 18:18:15,937 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:15,937 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:15,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:16,035 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:16,035 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:16,035 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:16,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:16,140 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:16,162 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:18:16,229 INFO L85 PathProgramCache]: Analyzing trace with hash -652909766, now seen corresponding path program 7 times [2024-05-06 18:18:16,229 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:16,229 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:16,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:16,327 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:16,328 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:16,328 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:16,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:16,488 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:16,503 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 972 treesize of output 924 [2024-05-06 18:18:16,833 INFO L85 PathProgramCache]: Analyzing trace with hash 1234634470, now seen corresponding path program 8 times [2024-05-06 18:18:16,833 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:16,833 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:16,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:16,930 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:16,930 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:16,930 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:16,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:17,027 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:17,046 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:18:18,095 INFO L85 PathProgramCache]: Analyzing trace with hash -652900061, now seen corresponding path program 9 times [2024-05-06 18:18:18,096 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:18,096 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:18,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:18,199 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:18,199 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:18,199 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:18,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:18,296 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:18,323 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:18:18,392 INFO L85 PathProgramCache]: Analyzing trace with hash 1087328968, now seen corresponding path program 10 times [2024-05-06 18:18:18,392 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:18,392 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:18,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:18,500 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:18,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:18,501 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:18,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:18,718 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:18,740 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:18:20,783 INFO L85 PathProgramCache]: Analyzing trace with hash -147166384, now seen corresponding path program 1 times [2024-05-06 18:18:20,784 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:20,784 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:20,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:20,890 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:18:20,890 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:20,891 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:20,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:20,994 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:18:21,023 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:18:23,074 INFO L85 PathProgramCache]: Analyzing trace with hash -1131397916, now seen corresponding path program 1 times [2024-05-06 18:18:23,075 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:23,075 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:23,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:23,174 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:23,174 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:23,174 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:23,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:23,273 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:23,291 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:18:25,343 INFO L85 PathProgramCache]: Analyzing trace with hash -713596309, now seen corresponding path program 2 times [2024-05-06 18:18:25,344 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:25,344 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:25,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:25,639 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:25,639 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:25,639 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:25,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:25,836 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:25,852 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 473 treesize of output 449 [2024-05-06 18:18:27,848 INFO L85 PathProgramCache]: Analyzing trace with hash -646648378, now seen corresponding path program 3 times [2024-05-06 18:18:27,848 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:27,849 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:27,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:27,950 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:27,950 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:27,950 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:27,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:28,051 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:28,069 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:18:28,864 INFO L85 PathProgramCache]: Analyzing trace with hash 1262558635, now seen corresponding path program 2 times [2024-05-06 18:18:28,864 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:28,865 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:28,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:28,978 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:28,978 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:28,978 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:28,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:29,083 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:29,101 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:18:29,185 INFO L85 PathProgramCache]: Analyzing trace with hash -713615434, now seen corresponding path program 4 times [2024-05-06 18:18:29,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:29,186 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:29,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:29,356 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:29,356 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:29,356 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:29,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:29,482 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:29,511 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:18:29,644 INFO L85 PathProgramCache]: Analyzing trace with hash -1131415736, now seen corresponding path program 5 times [2024-05-06 18:18:29,644 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:29,644 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:29,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:29,763 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:29,764 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:29,764 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:29,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:29,866 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:29,900 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:18:29,983 INFO L85 PathProgramCache]: Analyzing trace with hash -243208630, now seen corresponding path program 6 times [2024-05-06 18:18:29,983 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:29,983 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:29,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:30,081 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:30,081 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:30,082 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:30,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:30,183 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:30,201 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:18:30,289 INFO L85 PathProgramCache]: Analyzing trace with hash 1050467796, now seen corresponding path program 7 times [2024-05-06 18:18:30,289 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:30,289 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:30,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:30,385 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:30,386 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:30,386 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:30,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:30,539 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:30,555 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 1930 treesize of output 1834 [2024-05-06 18:18:31,045 INFO L85 PathProgramCache]: Analyzing trace with hash -1795235956, now seen corresponding path program 8 times [2024-05-06 18:18:31,046 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:31,046 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:31,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:31,142 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:31,142 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:31,142 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:31,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:31,237 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:31,264 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:18:31,337 INFO L85 PathProgramCache]: Analyzing trace with hash 1050477501, now seen corresponding path program 9 times [2024-05-06 18:18:31,337 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:31,337 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:31,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:31,434 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:31,434 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:31,434 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:31,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:31,540 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:31,579 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:18:31,637 INFO L85 PathProgramCache]: Analyzing trace with hash -243196690, now seen corresponding path program 10 times [2024-05-06 18:18:31,637 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:31,637 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:31,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:31,733 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:31,733 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:31,733 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:31,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:31,826 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:31,855 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:18:33,969 INFO L85 PathProgramCache]: Analyzing trace with hash -54098505, now seen corresponding path program 1 times [2024-05-06 18:18:33,969 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:33,969 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:33,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:34,082 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:18:34,082 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:34,082 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:34,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:34,188 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:18:34,220 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:18:34,301 INFO L85 PathProgramCache]: Analyzing trace with hash 478381963, now seen corresponding path program 1 times [2024-05-06 18:18:34,301 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:34,301 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:34,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:34,398 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:34,399 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:34,399 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:34,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:34,495 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:34,511 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:18:34,577 INFO L85 PathProgramCache]: Analyzing trace with hash 1944939684, now seen corresponding path program 2 times [2024-05-06 18:18:34,577 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:34,577 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:34,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:34,680 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:34,681 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:34,681 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:34,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:34,779 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:34,797 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 972 treesize of output 924 [2024-05-06 18:18:35,080 INFO L85 PathProgramCache]: Analyzing trace with hash 163588781, now seen corresponding path program 3 times [2024-05-06 18:18:35,081 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:35,081 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:35,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:35,237 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:35,238 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:35,238 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:35,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:35,335 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:35,377 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:18:37,429 INFO L85 PathProgramCache]: Analyzing trace with hash 1355626514, now seen corresponding path program 2 times [2024-05-06 18:18:37,429 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:37,429 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:37,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:37,543 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:37,544 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:37,544 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:37,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:37,651 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:37,673 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:18:37,723 INFO L85 PathProgramCache]: Analyzing trace with hash 1944920559, now seen corresponding path program 4 times [2024-05-06 18:18:37,723 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:37,723 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:37,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:37,832 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:37,832 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:37,833 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:37,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:37,931 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:37,949 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:18:38,026 INFO L85 PathProgramCache]: Analyzing trace with hash 478364143, now seen corresponding path program 5 times [2024-05-06 18:18:38,027 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:38,027 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:38,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:38,125 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:38,125 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:38,125 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:38,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:38,285 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:38,310 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:18:38,728 INFO L85 PathProgramCache]: Analyzing trace with hash 268090307, now seen corresponding path program 6 times [2024-05-06 18:18:38,728 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:38,728 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:38,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:38,823 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:38,823 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:38,823 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:38,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:38,918 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:38,936 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:18:41,005 INFO L85 PathProgramCache]: Analyzing trace with hash -279134341, now seen corresponding path program 7 times [2024-05-06 18:18:41,005 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:41,006 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:41,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:41,105 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:41,105 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:41,106 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:41,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:41,202 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:41,219 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 952 treesize of output 904 [2024-05-06 18:18:41,782 INFO L85 PathProgramCache]: Analyzing trace with hash -63229243, now seen corresponding path program 8 times [2024-05-06 18:18:41,782 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:41,782 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:41,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:41,884 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:41,884 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:41,884 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:41,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:41,982 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:42,002 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:18:42,071 INFO L85 PathProgramCache]: Analyzing trace with hash -279124636, now seen corresponding path program 9 times [2024-05-06 18:18:42,071 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:42,071 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:42,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:42,271 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:42,271 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:42,272 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:42,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:42,368 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:42,386 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:18:42,450 INFO L85 PathProgramCache]: Analyzing trace with hash 268102247, now seen corresponding path program 10 times [2024-05-06 18:18:42,451 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:42,451 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:42,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:42,546 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:42,547 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:42,547 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:42,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:42,645 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:42,677 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:18:42,830 INFO L85 PathProgramCache]: Analyzing trace with hash 1456879537, now seen corresponding path program 1 times [2024-05-06 18:18:42,830 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:42,830 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:42,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:42,924 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:42,924 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:42,924 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:42,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:43,018 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:43,041 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:18:45,091 INFO L85 PathProgramCache]: Analyzing trace with hash -2081373890, now seen corresponding path program 2 times [2024-05-06 18:18:45,091 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:45,091 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:45,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:45,184 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:45,185 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:45,185 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:45,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:45,351 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:45,372 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 473 treesize of output 449 [2024-05-06 18:18:47,504 INFO L85 PathProgramCache]: Analyzing trace with hash -98080429, now seen corresponding path program 3 times [2024-05-06 18:18:47,504 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:47,504 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:47,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:47,600 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:47,600 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:47,600 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:47,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:47,694 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:47,718 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:18:47,864 INFO L85 PathProgramCache]: Analyzing trace with hash 168886212, now seen corresponding path program 4 times [2024-05-06 18:18:47,864 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:47,864 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:47,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:47,964 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:47,965 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:47,965 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:47,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:48,061 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:48,081 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:18:48,138 INFO L85 PathProgramCache]: Analyzing trace with hash 940506010, now seen corresponding path program 5 times [2024-05-06 18:18:48,138 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:48,138 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:48,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:48,234 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:48,235 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:48,235 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:48,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:48,333 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:48,348 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 473 treesize of output 449 [2024-05-06 18:18:48,444 INFO L85 PathProgramCache]: Analyzing trace with hash -909084026, now seen corresponding path program 6 times [2024-05-06 18:18:48,444 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:48,444 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:48,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:48,674 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:48,674 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:48,674 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:48,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:48,781 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:48,801 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:18:48,894 INFO L85 PathProgramCache]: Analyzing trace with hash -11537712, now seen corresponding path program 1 times [2024-05-06 18:18:48,895 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:48,895 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:48,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:49,002 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:18:49,002 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:49,002 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:49,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:49,108 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:18:49,127 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:18:51,197 INFO L85 PathProgramCache]: Analyzing trace with hash -357668353, now seen corresponding path program 2 times [2024-05-06 18:18:51,197 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:51,197 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:51,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:51,304 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:18:51,304 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:51,305 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:51,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:51,411 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:18:51,433 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 473 treesize of output 449 [2024-05-06 18:18:51,648 INFO L85 PathProgramCache]: Analyzing trace with hash 1797183666, now seen corresponding path program 3 times [2024-05-06 18:18:51,649 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:51,649 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:51,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:51,813 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:18:51,814 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:51,814 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:51,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:51,919 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:18:51,937 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:18:54,004 INFO L85 PathProgramCache]: Analyzing trace with hash 1277560471, now seen corresponding path program 1 times [2024-05-06 18:18:54,005 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:54,005 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:54,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:54,117 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:18:54,118 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:54,118 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:54,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:54,229 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:18:54,250 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:18:54,327 INFO L85 PathProgramCache]: Analyzing trace with hash -357701893, now seen corresponding path program 4 times [2024-05-06 18:18:54,327 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:54,327 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:54,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:54,433 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:18:54,433 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:54,433 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:54,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:54,539 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:18:54,560 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:18:54,650 INFO L85 PathProgramCache]: Analyzing trace with hash -11570412, now seen corresponding path program 5 times [2024-05-06 18:18:54,651 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:54,651 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:54,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:54,839 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:18:54,839 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:54,839 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:54,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:54,944 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:18:54,970 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:18:55,304 INFO L85 PathProgramCache]: Analyzing trace with hash -268188226, now seen corresponding path program 6 times [2024-05-06 18:18:55,305 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:55,305 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:55,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:55,407 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:55,407 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:55,407 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:55,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:55,510 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:55,530 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:18:55,608 INFO L85 PathProgramCache]: Analyzing trace with hash 276100335, now seen corresponding path program 7 times [2024-05-06 18:18:55,608 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:55,608 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:55,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:55,709 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:55,709 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:55,709 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:55,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:55,812 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:55,832 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 972 treesize of output 924 [2024-05-06 18:18:58,008 INFO L85 PathProgramCache]: Analyzing trace with hash -30823456, now seen corresponding path program 8 times [2024-05-06 18:18:58,009 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:58,009 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:58,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:58,177 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:58,178 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:18:58,178 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:18:58,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:18:58,279 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:18:58,295 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:00,383 INFO L85 PathProgramCache]: Analyzing trace with hash 276124455, now seen corresponding path program 9 times [2024-05-06 18:19:00,383 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:00,383 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:00,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:00,487 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:00,488 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:00,488 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:00,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:00,595 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:00,622 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:00,745 INFO L85 PathProgramCache]: Analyzing trace with hash -268161406, now seen corresponding path program 10 times [2024-05-06 18:19:00,746 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:00,746 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:00,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:00,847 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:00,847 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:00,847 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:00,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:00,954 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:00,970 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:19:03,026 INFO L85 PathProgramCache]: Analyzing trace with hash 1066443753, now seen corresponding path program 2 times [2024-05-06 18:19:03,026 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:03,026 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:03,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:03,138 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:03,138 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:03,138 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:03,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:03,359 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:03,381 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:05,441 INFO L85 PathProgramCache]: Analyzing trace with hash -1225088731, now seen corresponding path program 11 times [2024-05-06 18:19:05,441 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:05,442 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:05,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:05,545 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:05,546 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:05,546 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:05,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:05,651 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:05,670 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:05,737 INFO L85 PathProgramCache]: Analyzing trace with hash 676955722, now seen corresponding path program 12 times [2024-05-06 18:19:05,737 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:05,737 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:05,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:05,842 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:05,843 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:05,843 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:05,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:05,946 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:05,961 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 473 treesize of output 449 [2024-05-06 18:19:06,156 INFO L85 PathProgramCache]: Analyzing trace with hash -489208377, now seen corresponding path program 13 times [2024-05-06 18:19:06,156 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:06,156 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:06,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:06,261 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:06,261 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:06,262 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:06,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:06,452 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:06,470 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:19:08,521 INFO L85 PathProgramCache]: Analyzing trace with hash 1247968300, now seen corresponding path program 3 times [2024-05-06 18:19:08,522 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:08,522 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:08,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:08,631 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:08,632 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:08,632 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:08,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:08,760 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:08,779 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:08,864 INFO L85 PathProgramCache]: Analyzing trace with hash 676922182, now seen corresponding path program 14 times [2024-05-06 18:19:08,864 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:08,864 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:08,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:08,968 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:08,969 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:08,969 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:08,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:09,073 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:09,096 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:11,163 INFO L85 PathProgramCache]: Analyzing trace with hash -1225121431, now seen corresponding path program 15 times [2024-05-06 18:19:11,163 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:11,163 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:11,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:11,289 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:11,289 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:11,289 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:11,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:11,548 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:11,573 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:11,662 INFO L85 PathProgramCache]: Analyzing trace with hash -1683180599, now seen corresponding path program 16 times [2024-05-06 18:19:11,662 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:11,662 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:11,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:11,763 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:11,764 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:11,764 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:11,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:11,869 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:11,891 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:11,982 INFO L85 PathProgramCache]: Analyzing trace with hash -638990268, now seen corresponding path program 17 times [2024-05-06 18:19:11,982 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:11,982 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:11,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:12,085 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:12,086 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:12,086 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:12,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:12,188 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:12,203 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 952 treesize of output 904 [2024-05-06 18:19:14,338 INFO L85 PathProgramCache]: Analyzing trace with hash 1666138923, now seen corresponding path program 18 times [2024-05-06 18:19:14,338 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:14,339 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:14,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:14,442 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:14,442 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:14,442 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:14,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:14,658 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:14,676 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:14,724 INFO L85 PathProgramCache]: Analyzing trace with hash -638966148, now seen corresponding path program 19 times [2024-05-06 18:19:14,725 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:14,725 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:14,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:14,850 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:14,851 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:14,851 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:14,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:14,979 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:14,996 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:15,045 INFO L85 PathProgramCache]: Analyzing trace with hash -1683153779, now seen corresponding path program 20 times [2024-05-06 18:19:15,046 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:15,046 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:15,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:15,148 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:15,148 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:15,148 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:15,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:15,265 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:15,282 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:19:17,323 INFO L85 PathProgramCache]: Analyzing trace with hash -787364674, now seen corresponding path program 4 times [2024-05-06 18:19:17,324 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:17,324 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:17,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:17,426 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:17,426 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:17,426 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:17,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:17,529 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:17,557 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:17,625 INFO L85 PathProgramCache]: Analyzing trace with hash 108049905, now seen corresponding path program 21 times [2024-05-06 18:19:17,625 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:17,625 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:17,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:17,731 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:17,731 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:17,731 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:17,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:17,912 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:17,928 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:17,985 INFO L85 PathProgramCache]: Analyzing trace with hash -945419522, now seen corresponding path program 22 times [2024-05-06 18:19:17,985 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:17,985 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:18,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:18,089 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:18,090 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:18,090 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:18,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:18,192 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:18,209 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 972 treesize of output 924 [2024-05-06 18:19:18,372 INFO L85 PathProgramCache]: Analyzing trace with hash 756766611, now seen corresponding path program 23 times [2024-05-06 18:19:18,372 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:18,372 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:18,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:18,489 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:18,489 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:18,489 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:18,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:18,594 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:18,624 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:19:18,721 INFO L85 PathProgramCache]: Analyzing trace with hash 310262776, now seen corresponding path program 5 times [2024-05-06 18:19:18,721 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:18,722 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:18,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:18,834 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:18,835 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:18,835 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:18,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:18,946 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:18,975 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:19,046 INFO L85 PathProgramCache]: Analyzing trace with hash -945453062, now seen corresponding path program 24 times [2024-05-06 18:19:19,046 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:19,046 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:19,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:19,216 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:19,217 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:19,217 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:19,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:19,319 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:19,336 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:19,425 INFO L85 PathProgramCache]: Analyzing trace with hash 108017205, now seen corresponding path program 25 times [2024-05-06 18:19:19,425 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:19,425 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:19,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:19,528 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:19,528 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:19,528 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:19,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:19,631 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:19,656 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:21,642 INFO L85 PathProgramCache]: Analyzing trace with hash -1648244355, now seen corresponding path program 26 times [2024-05-06 18:19:21,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:21,643 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:21,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:21,745 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:21,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:21,746 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:21,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:21,846 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:21,863 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:21,967 INFO L85 PathProgramCache]: Analyzing trace with hash 444033296, now seen corresponding path program 27 times [2024-05-06 18:19:21,968 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:21,968 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:21,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:22,074 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:22,074 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:22,074 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:22,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:22,178 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:22,195 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 1930 treesize of output 1834 [2024-05-06 18:19:22,423 INFO L85 PathProgramCache]: Analyzing trace with hash 880131039, now seen corresponding path program 28 times [2024-05-06 18:19:22,424 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:22,424 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:22,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:22,530 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:22,531 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:22,531 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:22,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:22,647 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:22,667 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:24,732 INFO L85 PathProgramCache]: Analyzing trace with hash 444057416, now seen corresponding path program 29 times [2024-05-06 18:19:24,732 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:24,732 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:24,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:24,834 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:24,835 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:24,835 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:24,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:24,937 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:24,955 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:25,018 INFO L85 PathProgramCache]: Analyzing trace with hash -1648217535, now seen corresponding path program 30 times [2024-05-06 18:19:25,019 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:25,019 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:25,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:25,122 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:25,122 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:25,122 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:25,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:25,224 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:25,240 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:19:27,277 INFO L85 PathProgramCache]: Analyzing trace with hash -586539126, now seen corresponding path program 6 times [2024-05-06 18:19:27,277 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:27,278 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:27,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:27,393 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:27,393 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:27,393 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:27,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:27,687 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:27,709 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:27,855 INFO L85 PathProgramCache]: Analyzing trace with hash -831964826, now seen corresponding path program 31 times [2024-05-06 18:19:27,855 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:27,855 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:27,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:27,962 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:27,962 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:27,962 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:27,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:28,066 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:28,088 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:28,156 INFO L85 PathProgramCache]: Analyzing trace with hash -21105111, now seen corresponding path program 32 times [2024-05-06 18:19:28,157 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:28,157 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:28,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:28,262 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:28,262 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:28,262 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:28,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:28,368 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:28,383 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 972 treesize of output 924 [2024-05-06 18:19:28,549 INFO L85 PathProgramCache]: Analyzing trace with hash -654257720, now seen corresponding path program 33 times [2024-05-06 18:19:28,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:28,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:28,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:28,657 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:28,658 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:28,658 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:28,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:28,763 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:28,780 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:19:30,825 INFO L85 PathProgramCache]: Analyzing trace with hash -518189395, now seen corresponding path program 7 times [2024-05-06 18:19:30,825 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:30,825 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:30,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:31,020 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:31,020 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:31,020 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:31,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:31,130 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:31,152 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:31,227 INFO L85 PathProgramCache]: Analyzing trace with hash -21138651, now seen corresponding path program 34 times [2024-05-06 18:19:31,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:31,228 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:31,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:31,336 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:31,336 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:31,336 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:31,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:31,441 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:31,462 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:32,409 INFO L85 PathProgramCache]: Analyzing trace with hash -831997526, now seen corresponding path program 35 times [2024-05-06 18:19:32,410 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:32,410 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:32,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:32,515 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:32,515 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:32,515 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:32,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:32,620 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:32,645 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:34,699 INFO L85 PathProgramCache]: Analyzing trace with hash -1427988888, now seen corresponding path program 36 times [2024-05-06 18:19:34,699 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:34,700 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:34,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:34,801 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:34,801 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:34,802 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:34,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:34,903 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:34,922 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:35,021 INFO L85 PathProgramCache]: Analyzing trace with hash -1317981819, now seen corresponding path program 37 times [2024-05-06 18:19:35,021 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:35,021 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:35,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:35,193 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:35,193 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:35,193 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:35,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:35,295 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:35,310 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 473 treesize of output 449 [2024-05-06 18:19:35,707 INFO L85 PathProgramCache]: Analyzing trace with hash 2092237322, now seen corresponding path program 38 times [2024-05-06 18:19:35,708 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:35,708 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:35,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:35,809 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:35,809 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:35,809 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:35,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:35,909 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:35,926 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:37,968 INFO L85 PathProgramCache]: Analyzing trace with hash -1317957699, now seen corresponding path program 39 times [2024-05-06 18:19:37,968 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:37,968 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:37,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:38,069 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:38,069 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:38,069 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:38,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:38,172 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:38,188 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:38,264 INFO L85 PathProgramCache]: Analyzing trace with hash -1427962068, now seen corresponding path program 40 times [2024-05-06 18:19:38,264 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:38,264 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:38,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:38,365 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:38,365 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:38,365 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:38,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:38,540 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:38,565 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:19:38,623 INFO L85 PathProgramCache]: Analyzing trace with hash 1481680255, now seen corresponding path program 8 times [2024-05-06 18:19:38,623 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:38,623 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:38,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:38,727 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:38,727 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:38,727 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:38,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:38,830 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:38,851 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:40,905 INFO L85 PathProgramCache]: Analyzing trace with hash 1341281554, now seen corresponding path program 41 times [2024-05-06 18:19:40,905 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:40,905 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:40,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:41,016 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:41,016 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:41,016 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:41,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:41,120 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:41,140 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:41,245 INFO L85 PathProgramCache]: Analyzing trace with hash -1369944067, now seen corresponding path program 42 times [2024-05-06 18:19:41,245 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:41,245 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:41,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:41,351 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:41,351 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:41,351 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:41,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:41,464 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:41,477 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 972 treesize of output 924 [2024-05-06 18:19:42,072 INFO L85 PathProgramCache]: Analyzing trace with hash 481407604, now seen corresponding path program 43 times [2024-05-06 18:19:42,072 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:42,072 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:42,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:42,192 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:42,192 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:42,192 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:42,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:42,435 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:42,452 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:19:44,286 INFO L85 PathProgramCache]: Analyzing trace with hash 42356057, now seen corresponding path program 9 times [2024-05-06 18:19:44,286 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:44,287 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:44,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:44,399 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:44,399 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:44,399 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:44,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:44,514 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:44,533 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:44,648 INFO L85 PathProgramCache]: Analyzing trace with hash -1369977607, now seen corresponding path program 44 times [2024-05-06 18:19:44,649 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:44,649 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:44,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:44,755 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:44,755 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:44,755 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:44,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:44,860 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:44,878 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:44,954 INFO L85 PathProgramCache]: Analyzing trace with hash 1341248854, now seen corresponding path program 45 times [2024-05-06 18:19:44,954 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:44,954 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:44,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:45,059 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:45,060 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:45,060 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:45,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:45,165 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:45,190 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:45,299 INFO L85 PathProgramCache]: Analyzing trace with hash 460812604, now seen corresponding path program 46 times [2024-05-06 18:19:45,299 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:45,299 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:45,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:45,479 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:45,480 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:45,480 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:45,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:45,583 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:45,601 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:45,660 INFO L85 PathProgramCache]: Analyzing trace with hash 1400289585, now seen corresponding path program 47 times [2024-05-06 18:19:45,660 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:45,660 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:45,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:45,762 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:45,763 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:45,763 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:45,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:45,865 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:45,880 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 1930 treesize of output 1834 [2024-05-06 18:19:46,162 INFO L85 PathProgramCache]: Analyzing trace with hash 459304926, now seen corresponding path program 48 times [2024-05-06 18:19:46,162 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:46,162 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:46,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:46,265 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:46,265 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:46,265 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:46,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:46,368 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:46,387 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:48,451 INFO L85 PathProgramCache]: Analyzing trace with hash 1400313705, now seen corresponding path program 49 times [2024-05-06 18:19:48,451 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:48,451 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:48,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:48,556 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:48,557 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:48,557 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:48,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:48,659 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:48,678 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:48,822 INFO L85 PathProgramCache]: Analyzing trace with hash 460839424, now seen corresponding path program 50 times [2024-05-06 18:19:48,822 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:48,822 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:48,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:48,925 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:48,925 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:48,926 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:48,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:49,027 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:49,049 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:19:51,096 INFO L85 PathProgramCache]: Analyzing trace with hash -407734485, now seen corresponding path program 10 times [2024-05-06 18:19:51,097 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:51,097 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:51,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:51,205 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:51,205 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:51,206 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:51,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:51,312 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:51,334 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:53,396 INFO L85 PathProgramCache]: Analyzing trace with hash 134212578, now seen corresponding path program 51 times [2024-05-06 18:19:53,396 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:53,396 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:53,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:53,497 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:53,497 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:53,497 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:53,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:53,598 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:53,615 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:55,659 INFO L85 PathProgramCache]: Analyzing trace with hash -134376659, now seen corresponding path program 52 times [2024-05-06 18:19:55,659 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:55,659 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:55,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:55,760 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:55,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:55,760 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:55,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:55,950 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:55,968 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 972 treesize of output 924 [2024-05-06 18:19:56,272 INFO L85 PathProgramCache]: Analyzing trace with hash 129291588, now seen corresponding path program 53 times [2024-05-06 18:19:56,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:56,272 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:56,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:56,374 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:56,375 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:56,375 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:56,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:56,478 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:56,504 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:56,590 INFO L85 PathProgramCache]: Analyzing trace with hash 2025773160, now seen corresponding path program 54 times [2024-05-06 18:19:56,590 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:56,590 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:56,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:56,700 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:56,700 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:56,700 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:56,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:56,811 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:56,831 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:56,896 INFO L85 PathProgramCache]: Analyzing trace with hash -1625540731, now seen corresponding path program 55 times [2024-05-06 18:19:56,896 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:56,896 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:56,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:57,006 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:57,006 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:57,007 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:57,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:57,118 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:57,133 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 952 treesize of output 904 [2024-05-06 18:19:57,196 INFO L85 PathProgramCache]: Analyzing trace with hash 1147845642, now seen corresponding path program 56 times [2024-05-06 18:19:57,196 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:57,196 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:57,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:57,383 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:57,384 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:57,384 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:57,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:57,493 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:57,524 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:57,585 INFO L85 PathProgramCache]: Analyzing trace with hash -1625531026, now seen corresponding path program 57 times [2024-05-06 18:19:57,585 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:57,585 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:57,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:57,695 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:57,695 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:57,695 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:57,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:57,805 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:57,824 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:57,935 INFO L85 PathProgramCache]: Analyzing trace with hash 2025785100, now seen corresponding path program 58 times [2024-05-06 18:19:57,935 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:57,935 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:57,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:58,059 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:58,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:58,059 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:58,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:58,169 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:19:58,191 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:19:58,525 INFO L85 PathProgramCache]: Analyzing trace with hash 1865354084, now seen corresponding path program 59 times [2024-05-06 18:19:58,525 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:58,525 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:58,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:58,687 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:58,687 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:19:58,687 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:19:58,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:19:58,815 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:19:58,835 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:00,947 INFO L85 PathProgramCache]: Analyzing trace with hash 1991402490, now seen corresponding path program 60 times [2024-05-06 18:20:00,947 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:00,947 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:00,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:01,053 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:01,053 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:01,053 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:01,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:01,160 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:01,171 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 1930 treesize of output 1834 [2024-05-06 18:20:01,226 INFO L85 PathProgramCache]: Analyzing trace with hash 1603935782, now seen corresponding path program 61 times [2024-05-06 18:20:01,226 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:01,226 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:01,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:01,332 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:01,333 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:01,333 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:01,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:01,442 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:01,460 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:01,531 INFO L85 PathProgramCache]: Analyzing trace with hash 1991383365, now seen corresponding path program 62 times [2024-05-06 18:20:01,531 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:01,531 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:01,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:01,636 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:01,637 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:01,637 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:01,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:01,742 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:01,760 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:01,823 INFO L85 PathProgramCache]: Analyzing trace with hash 1865336264, now seen corresponding path program 63 times [2024-05-06 18:20:01,823 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:01,823 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:01,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:01,931 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:01,931 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:01,931 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:01,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:02,105 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:02,127 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:02,189 INFO L85 PathProgramCache]: Analyzing trace with hash 45077650, now seen corresponding path program 64 times [2024-05-06 18:20:02,189 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:02,189 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:02,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:02,299 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:02,299 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:02,299 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:02,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:02,413 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:02,430 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:02,509 INFO L85 PathProgramCache]: Analyzing trace with hash 1397407899, now seen corresponding path program 65 times [2024-05-06 18:20:02,509 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:02,509 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:02,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:02,618 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:02,619 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:02,619 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:02,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:02,729 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:02,740 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 473 treesize of output 449 [2024-05-06 18:20:02,800 INFO L85 PathProgramCache]: Analyzing trace with hash 369972660, now seen corresponding path program 66 times [2024-05-06 18:20:02,800 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:02,800 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:02,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:02,909 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:02,909 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:02,909 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:02,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:03,020 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:03,061 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:03,130 INFO L85 PathProgramCache]: Analyzing trace with hash 1397417604, now seen corresponding path program 67 times [2024-05-06 18:20:03,131 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:03,131 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:03,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:03,358 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:03,359 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:03,359 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:03,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:03,469 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:03,487 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:05,552 INFO L85 PathProgramCache]: Analyzing trace with hash 45089590, now seen corresponding path program 68 times [2024-05-06 18:20:05,553 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:05,553 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:05,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:05,661 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:05,662 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:05,662 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:05,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:05,771 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:05,792 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:05,855 INFO L85 PathProgramCache]: Analyzing trace with hash -504637446, now seen corresponding path program 69 times [2024-05-06 18:20:05,855 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:05,855 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:05,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:05,962 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:05,962 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:05,962 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:05,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:06,069 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:06,087 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:06,146 INFO L85 PathProgramCache]: Analyzing trace with hash 1536109092, now seen corresponding path program 70 times [2024-05-06 18:20:06,147 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:06,147 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:06,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:06,255 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:06,255 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:06,255 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:06,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:06,501 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:06,513 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 473 treesize of output 449 [2024-05-06 18:20:06,575 INFO L85 PathProgramCache]: Analyzing trace with hash 374742332, now seen corresponding path program 71 times [2024-05-06 18:20:06,575 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:06,575 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:06,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:06,682 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:06,682 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:06,682 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:06,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:06,789 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:06,807 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:08,871 INFO L85 PathProgramCache]: Analyzing trace with hash 1536089967, now seen corresponding path program 72 times [2024-05-06 18:20:08,871 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:08,871 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:08,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:08,978 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:08,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:08,979 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:08,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:09,089 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:09,107 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:09,208 INFO L85 PathProgramCache]: Analyzing trace with hash -504655266, now seen corresponding path program 73 times [2024-05-06 18:20:09,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:09,208 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:09,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:09,317 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:09,318 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:09,318 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:09,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:09,427 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:09,449 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:09,509 INFO L85 PathProgramCache]: Analyzing trace with hash 799280361, now seen corresponding path program 74 times [2024-05-06 18:20:09,509 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:09,509 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:09,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:09,766 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:09,766 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:09,766 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:09,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:09,878 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:09,897 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:09,951 INFO L85 PathProgramCache]: Analyzing trace with hash -992111836, now seen corresponding path program 75 times [2024-05-06 18:20:09,951 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:09,951 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:09,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:10,063 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:10,064 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:10,064 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:10,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:10,176 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:10,188 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 473 treesize of output 449 [2024-05-06 18:20:10,256 INFO L85 PathProgramCache]: Analyzing trace with hash -690695093, now seen corresponding path program 76 times [2024-05-06 18:20:10,256 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:10,256 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:10,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:10,366 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:10,366 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:10,366 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:10,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:10,475 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:10,492 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:10,556 INFO L85 PathProgramCache]: Analyzing trace with hash -992102131, now seen corresponding path program 77 times [2024-05-06 18:20:10,556 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:10,557 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:10,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:10,666 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:10,666 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:10,667 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:10,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:10,849 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:10,893 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:11,054 INFO L85 PathProgramCache]: Analyzing trace with hash 799292301, now seen corresponding path program 78 times [2024-05-06 18:20:11,054 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:11,054 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:11,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:11,170 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:11,171 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:11,171 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:11,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:11,284 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:11,306 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:11,370 INFO L85 PathProgramCache]: Analyzing trace with hash 1023513027, now seen corresponding path program 79 times [2024-05-06 18:20:11,370 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:11,370 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:11,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:11,479 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:11,479 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:11,479 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:11,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:11,588 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:11,605 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:11,677 INFO L85 PathProgramCache]: Analyzing trace with hash 1664133499, now seen corresponding path program 80 times [2024-05-06 18:20:11,677 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:11,678 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:11,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:11,787 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:11,787 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:11,787 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:11,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:11,898 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:11,937 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 1930 treesize of output 1834 [2024-05-06 18:20:12,000 INFO L85 PathProgramCache]: Analyzing trace with hash 48531653, now seen corresponding path program 81 times [2024-05-06 18:20:12,000 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:12,000 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:12,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:12,190 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:12,191 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:12,191 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:12,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:12,298 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:12,317 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:12,379 INFO L85 PathProgramCache]: Analyzing trace with hash 1664114374, now seen corresponding path program 82 times [2024-05-06 18:20:12,379 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:12,379 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:12,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:12,487 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:12,488 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:12,488 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:12,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:12,595 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:12,614 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:12,678 INFO L85 PathProgramCache]: Analyzing trace with hash 1023495207, now seen corresponding path program 83 times [2024-05-06 18:20:12,678 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:12,679 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:12,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:12,787 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:12,788 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:12,788 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:12,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:12,896 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:12,917 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:13,077 INFO L85 PathProgramCache]: Analyzing trace with hash 1364610931, now seen corresponding path program 84 times [2024-05-06 18:20:13,077 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:13,077 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:13,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:13,190 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:13,190 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:13,190 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:13,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:13,381 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:13,401 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:13,491 INFO L85 PathProgramCache]: Analyzing trace with hash -646733350, now seen corresponding path program 85 times [2024-05-06 18:20:13,491 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:13,491 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:13,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:13,633 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:13,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:13,634 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:13,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:13,779 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:13,793 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 952 treesize of output 904 [2024-05-06 18:20:13,889 INFO L85 PathProgramCache]: Analyzing trace with hash 1426103381, now seen corresponding path program 86 times [2024-05-06 18:20:13,889 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:13,889 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:13,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:14,002 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:14,002 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:14,003 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:14,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:14,114 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:14,133 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:14,211 INFO L85 PathProgramCache]: Analyzing trace with hash -646723645, now seen corresponding path program 87 times [2024-05-06 18:20:14,212 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:14,212 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:14,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:14,323 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:14,323 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:14,323 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:14,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:14,435 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:14,453 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:14,594 INFO L85 PathProgramCache]: Analyzing trace with hash 1364622871, now seen corresponding path program 88 times [2024-05-06 18:20:14,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:14,594 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:14,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:14,704 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:14,704 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:14,705 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:14,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:14,892 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:14,913 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:16,967 INFO L85 PathProgramCache]: Analyzing trace with hash -786273287, now seen corresponding path program 89 times [2024-05-06 18:20:16,968 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:16,968 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:16,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:17,075 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:17,076 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:17,076 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:17,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:17,182 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:17,198 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:17,432 INFO L85 PathProgramCache]: Analyzing trace with hash 1395332613, now seen corresponding path program 90 times [2024-05-06 18:20:17,432 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:17,433 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:17,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:17,538 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:17,539 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:17,539 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:17,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:17,646 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:17,661 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 473 treesize of output 449 [2024-05-06 18:20:17,723 INFO L85 PathProgramCache]: Analyzing trace with hash 305638779, now seen corresponding path program 91 times [2024-05-06 18:20:17,723 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:17,724 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:17,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:17,949 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:17,950 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:17,950 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:17,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:18,066 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:18,082 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:18,164 INFO L85 PathProgramCache]: Analyzing trace with hash 1395313488, now seen corresponding path program 92 times [2024-05-06 18:20:18,164 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:18,164 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:18,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:18,272 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:18,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:18,272 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:18,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:18,388 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:18,404 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:18,466 INFO L85 PathProgramCache]: Analyzing trace with hash -786291107, now seen corresponding path program 93 times [2024-05-06 18:20:18,466 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:18,466 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:18,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:18,653 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:18,654 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:18,654 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:18,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:18,764 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:18,786 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:20,834 INFO L85 PathProgramCache]: Analyzing trace with hash 538375530, now seen corresponding path program 94 times [2024-05-06 18:20:20,835 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:20,835 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:20,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:20,944 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:20,944 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:20,944 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:20,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:21,054 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:21,070 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:21,146 INFO L85 PathProgramCache]: Analyzing trace with hash -490227005, now seen corresponding path program 95 times [2024-05-06 18:20:21,146 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:21,147 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:21,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:21,255 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:21,255 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:21,256 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:21,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:21,366 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:21,381 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 473 treesize of output 449 [2024-05-06 18:20:21,458 INFO L85 PathProgramCache]: Analyzing trace with hash 1982832780, now seen corresponding path program 96 times [2024-05-06 18:20:21,458 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:21,459 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:21,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:21,570 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:21,570 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:21,570 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:21,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:21,681 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:21,700 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:23,766 INFO L85 PathProgramCache]: Analyzing trace with hash -490217300, now seen corresponding path program 97 times [2024-05-06 18:20:23,766 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:23,766 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:23,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:24,024 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:24,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:24,024 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:24,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:24,132 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:24,149 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:24,218 INFO L85 PathProgramCache]: Analyzing trace with hash 538387470, now seen corresponding path program 98 times [2024-05-06 18:20:24,219 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:24,219 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:24,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:24,328 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:24,329 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:24,329 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:24,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:24,438 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:24,458 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:24,715 INFO L85 PathProgramCache]: Analyzing trace with hash 759948322, now seen corresponding path program 99 times [2024-05-06 18:20:24,715 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:24,715 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:24,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:24,821 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:24,821 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:24,821 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:24,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:24,927 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:24,943 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:24,993 INFO L85 PathProgramCache]: Analyzing trace with hash 2083562236, now seen corresponding path program 100 times [2024-05-06 18:20:24,994 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:24,994 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:25,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:25,100 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:25,101 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:25,101 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:25,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:25,208 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:25,220 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 972 treesize of output 924 [2024-05-06 18:20:25,311 INFO L85 PathProgramCache]: Analyzing trace with hash 165920612, now seen corresponding path program 101 times [2024-05-06 18:20:25,311 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:25,311 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:25,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:25,501 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:25,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:25,501 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:25,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:25,610 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:25,627 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:25,673 INFO L85 PathProgramCache]: Analyzing trace with hash 2083543111, now seen corresponding path program 102 times [2024-05-06 18:20:25,673 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:25,673 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:25,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:25,780 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:25,781 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:25,781 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:25,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:25,887 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:25,904 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:25,975 INFO L85 PathProgramCache]: Analyzing trace with hash 759930502, now seen corresponding path program 103 times [2024-05-06 18:20:25,975 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:25,975 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:25,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:26,086 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:26,086 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:26,086 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:26,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:26,195 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:26,216 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:26,296 INFO L85 PathProgramCache]: Analyzing trace with hash 814811426, now seen corresponding path program 104 times [2024-05-06 18:20:26,296 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:26,296 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:26,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:26,403 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:26,403 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:26,403 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:26,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:26,517 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:26,533 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:26,601 INFO L85 PathProgramCache]: Analyzing trace with hash -510648821, now seen corresponding path program 105 times [2024-05-06 18:20:26,601 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:26,601 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:26,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:26,708 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:26,708 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:26,708 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:26,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:26,935 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:26,952 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:29,024 INFO L85 PathProgramCache]: Analyzing trace with hash -272919346, now seen corresponding path program 106 times [2024-05-06 18:20:29,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:29,024 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:29,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:29,178 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:29,178 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:29,178 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:29,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:29,296 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:29,314 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:29,387 INFO L85 PathProgramCache]: Analyzing trace with hash 129435582, now seen corresponding path program 107 times [2024-05-06 18:20:29,387 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:29,387 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:29,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:29,496 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:29,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:29,497 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:29,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:29,606 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:29,625 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:29,703 INFO L85 PathProgramCache]: Analyzing trace with hash -282463535, now seen corresponding path program 108 times [2024-05-06 18:20:29,703 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:29,703 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:29,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:29,813 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:29,813 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:29,813 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:29,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:29,923 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:29,942 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:30,011 INFO L85 PathProgramCache]: Analyzing trace with hash -282463535, now seen corresponding path program 109 times [2024-05-06 18:20:30,011 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:30,011 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:30,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:30,119 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:30,119 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:30,119 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:30,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:30,227 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:30,244 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:30,323 INFO L85 PathProgramCache]: Analyzing trace with hash -1533607204, now seen corresponding path program 110 times [2024-05-06 18:20:30,323 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:30,323 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:30,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:30,512 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:30,512 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:30,512 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:30,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:30,624 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:30,640 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:32,684 INFO L85 PathProgramCache]: Analyzing trace with hash -297182337, now seen corresponding path program 111 times [2024-05-06 18:20:32,684 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:32,684 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:32,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:32,794 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:32,795 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:32,795 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:32,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:32,910 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:32,927 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:32,989 INFO L85 PathProgramCache]: Analyzing trace with hash -622717121, now seen corresponding path program 112 times [2024-05-06 18:20:32,989 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:32,989 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:33,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:33,127 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:33,127 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:33,129 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:33,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:33,241 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:33,257 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:35,317 INFO L85 PathProgramCache]: Analyzing trace with hash -622717121, now seen corresponding path program 113 times [2024-05-06 18:20:35,317 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:35,318 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:35,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:35,429 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:35,430 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:35,430 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:35,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:35,542 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:35,563 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:36,383 INFO L85 PathProgramCache]: Analyzing trace with hash -1430675973, now seen corresponding path program 114 times [2024-05-06 18:20:36,383 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:36,384 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:36,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:36,499 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:36,500 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:36,500 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:36,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:36,613 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:36,631 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:38,782 INFO L85 PathProgramCache]: Analyzing trace with hash -1401281478, now seen corresponding path program 115 times [2024-05-06 18:20:38,782 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:38,783 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:38,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:38,898 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:38,898 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:38,898 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:38,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:39,031 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:39,047 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:39,096 INFO L85 PathProgramCache]: Analyzing trace with hash -490052132, now seen corresponding path program 116 times [2024-05-06 18:20:39,096 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:39,096 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:39,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:39,216 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:39,216 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:39,217 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:39,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:39,329 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:39,346 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:39,400 INFO L85 PathProgramCache]: Analyzing trace with hash 1988253819, now seen corresponding path program 117 times [2024-05-06 18:20:39,400 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:39,400 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:39,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:39,512 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:39,513 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:39,513 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:39,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:39,625 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:39,641 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:39,708 INFO L85 PathProgramCache]: Analyzing trace with hash 1506326973, now seen corresponding path program 118 times [2024-05-06 18:20:39,709 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:39,709 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:39,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:39,826 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:39,826 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:39,826 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:39,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:39,941 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:39,959 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:40,014 INFO L85 PathProgramCache]: Analyzing trace with hash -548503364, now seen corresponding path program 119 times [2024-05-06 18:20:40,014 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:40,014 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:40,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:40,130 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:40,130 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:40,130 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:40,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:40,341 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:40,360 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:40,418 INFO L85 PathProgramCache]: Analyzing trace with hash 176265616, now seen corresponding path program 120 times [2024-05-06 18:20:40,418 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:40,418 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:40,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:40,534 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:40,534 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:40,534 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:40,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:40,648 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:40,666 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:40,733 INFO L85 PathProgramCache]: Analyzing trace with hash 1169267519, now seen corresponding path program 121 times [2024-05-06 18:20:40,733 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:40,733 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:40,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:40,850 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:40,850 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:40,850 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:40,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:40,969 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:40,988 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:41,065 INFO L85 PathProgramCache]: Analyzing trace with hash 1169267519, now seen corresponding path program 122 times [2024-05-06 18:20:41,065 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:41,065 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:41,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:41,183 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:41,183 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:41,183 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:41,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:41,298 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:41,315 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:41,441 INFO L85 PathProgramCache]: Analyzing trace with hash -1615321714, now seen corresponding path program 123 times [2024-05-06 18:20:41,441 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:41,441 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:41,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:41,557 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:41,557 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:41,558 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:41,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:41,775 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:41,792 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:41,857 INFO L85 PathProgramCache]: Analyzing trace with hash 1464635173, now seen corresponding path program 124 times [2024-05-06 18:20:41,857 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:41,858 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:41,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:41,975 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:41,975 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:41,975 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:41,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:42,091 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:42,108 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:42,173 INFO L85 PathProgramCache]: Analyzing trace with hash -1840949137, now seen corresponding path program 125 times [2024-05-06 18:20:42,173 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:42,174 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:42,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:42,292 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:42,292 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:42,292 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:42,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:42,408 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:42,424 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:42,500 INFO L85 PathProgramCache]: Analyzing trace with hash -1234847642, now seen corresponding path program 126 times [2024-05-06 18:20:42,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:42,501 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:42,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:42,618 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:42,618 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:42,618 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:42,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:42,736 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:42,754 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:42,815 INFO L85 PathProgramCache]: Analyzing trace with hash 374429520, now seen corresponding path program 127 times [2024-05-06 18:20:42,816 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:42,816 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:42,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:42,933 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:42,933 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:42,934 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:42,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:43,052 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:43,070 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:43,121 INFO L85 PathProgramCache]: Analyzing trace with hash -1277586009, now seen corresponding path program 128 times [2024-05-06 18:20:43,121 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:43,121 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:43,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:43,328 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:43,328 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:43,328 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:43,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:43,445 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:43,463 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:43,522 INFO L85 PathProgramCache]: Analyzing trace with hash -950459869, now seen corresponding path program 129 times [2024-05-06 18:20:43,523 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:43,523 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:43,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:43,641 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:43,642 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:43,642 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:43,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:43,760 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:43,778 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:43,857 INFO L85 PathProgramCache]: Analyzing trace with hash 600515882, now seen corresponding path program 130 times [2024-05-06 18:20:43,858 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:43,858 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:43,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:43,977 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:43,978 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:43,978 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:43,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:44,095 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:44,111 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:44,206 INFO L85 PathProgramCache]: Analyzing trace with hash 600515882, now seen corresponding path program 131 times [2024-05-06 18:20:44,206 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:44,206 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:44,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:44,324 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:44,325 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:44,325 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:44,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:44,442 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 18:20:44,459 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:44,521 INFO L85 PathProgramCache]: Analyzing trace with hash 1570168537, now seen corresponding path program 132 times [2024-05-06 18:20:44,521 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:44,521 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:44,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:44,727 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:44,727 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:44,727 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:44,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:44,849 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:44,866 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:44,931 INFO L85 PathProgramCache]: Analyzing trace with hash 1430585131, now seen corresponding path program 133 times [2024-05-06 18:20:44,931 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:44,931 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:44,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:45,055 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:45,055 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:45,055 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:45,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:45,177 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:45,193 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:47,279 INFO L85 PathProgramCache]: Analyzing trace with hash 1398466842, now seen corresponding path program 134 times [2024-05-06 18:20:47,280 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:47,280 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:47,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:47,400 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:47,400 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:47,400 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:47,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:47,521 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:47,538 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:47,619 INFO L85 PathProgramCache]: Analyzing trace with hash 402799884, now seen corresponding path program 135 times [2024-05-06 18:20:47,619 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:47,619 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:47,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:47,741 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:47,742 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:47,742 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:47,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:47,862 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:47,880 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:47,948 INFO L85 PathProgramCache]: Analyzing trace with hash -398104741, now seen corresponding path program 136 times [2024-05-06 18:20:47,948 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:47,948 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:47,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:48,180 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:48,180 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:48,180 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:48,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:48,302 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:48,320 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:48,402 INFO L85 PathProgramCache]: Analyzing trace with hash 543655661, now seen corresponding path program 137 times [2024-05-06 18:20:48,402 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:48,402 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:48,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:48,524 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:48,524 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:48,524 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:48,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:48,645 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:48,664 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:48,730 INFO L85 PathProgramCache]: Analyzing trace with hash 1088563841, now seen corresponding path program 138 times [2024-05-06 18:20:48,730 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:48,730 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:48,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:48,856 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:48,857 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:48,857 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:48,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:48,983 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:48,999 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:49,095 INFO L85 PathProgramCache]: Analyzing trace with hash -614258566, now seen corresponding path program 139 times [2024-05-06 18:20:49,096 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:49,096 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:49,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:49,264 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:49,265 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:49,265 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:49,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:49,386 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:49,404 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:49,479 INFO L85 PathProgramCache]: Analyzing trace with hash -1862145628, now seen corresponding path program 140 times [2024-05-06 18:20:49,479 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:49,479 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:49,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:49,686 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:49,686 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:49,686 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:49,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:49,807 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:49,825 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:49,888 INFO L85 PathProgramCache]: Analyzing trace with hash -1862145628, now seen corresponding path program 141 times [2024-05-06 18:20:49,888 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:49,888 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:49,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:50,012 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:50,012 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:50,012 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:50,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:50,137 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 18:20:50,155 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:51,053 INFO L85 PathProgramCache]: Analyzing trace with hash -964239607, now seen corresponding path program 142 times [2024-05-06 18:20:51,053 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:51,053 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:51,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:51,176 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:20:51,176 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:51,176 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:51,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:51,299 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:20:51,315 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:51,365 INFO L85 PathProgramCache]: Analyzing trace with hash 173344001, now seen corresponding path program 143 times [2024-05-06 18:20:51,365 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:51,365 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:51,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:51,497 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:20:51,497 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:51,498 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:51,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:51,629 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:20:51,648 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:53,702 INFO L85 PathProgramCache]: Analyzing trace with hash 1078697484, now seen corresponding path program 144 times [2024-05-06 18:20:53,702 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:53,703 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:53,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:53,926 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:20:53,926 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:53,926 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:53,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:54,050 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:20:54,080 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:56,141 INFO L85 PathProgramCache]: Analyzing trace with hash 1078697484, now seen corresponding path program 145 times [2024-05-06 18:20:56,141 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:56,142 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:56,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:56,265 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:20:56,265 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:56,265 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:56,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:56,391 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 18:20:56,437 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:56,526 INFO L85 PathProgramCache]: Analyzing trace with hash 574863600, now seen corresponding path program 146 times [2024-05-06 18:20:56,526 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:56,526 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:56,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:56,660 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:20:56,661 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:56,661 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:56,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:56,796 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:20:56,814 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:20:56,884 INFO L85 PathProgramCache]: Analyzing trace with hash 652822001, now seen corresponding path program 11 times [2024-05-06 18:20:56,884 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:56,884 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:56,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:57,024 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:20:57,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:57,024 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:57,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:57,255 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:20:57,275 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:57,368 INFO L85 PathProgramCache]: Analyzing trace with hash -1237353860, now seen corresponding path program 1 times [2024-05-06 18:20:57,368 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:57,368 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:57,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:57,505 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:20:57,505 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:57,505 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:57,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:57,642 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 18:20:57,669 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:57,741 INFO L85 PathProgramCache]: Analyzing trace with hash -150995487, now seen corresponding path program 2 times [2024-05-06 18:20:57,741 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:57,741 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:57,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:57,891 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:20:57,891 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:57,891 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:57,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:58,040 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 18:20:58,060 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:58,147 INFO L85 PathProgramCache]: Analyzing trace with hash 1688333752, now seen corresponding path program 3 times [2024-05-06 18:20:58,147 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:58,147 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:58,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:58,300 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:20:58,301 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:58,301 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:58,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:58,453 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:20:58,472 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:20:58,553 INFO L85 PathProgramCache]: Analyzing trace with hash 798739494, now seen corresponding path program 4 times [2024-05-06 18:20:58,553 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:58,553 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:58,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:58,913 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:20:58,913 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:58,913 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:58,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:59,065 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:20:59,078 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 1930 treesize of output 1834 [2024-05-06 18:20:59,158 INFO L85 PathProgramCache]: Analyzing trace with hash -1008878726, now seen corresponding path program 5 times [2024-05-06 18:20:59,158 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:59,158 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:59,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:59,319 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:20:59,319 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:20:59,319 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:20:59,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:20:59,476 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:20:59,496 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:21:01,560 INFO L85 PathProgramCache]: Analyzing trace with hash 705328053, now seen corresponding path program 1 times [2024-05-06 18:21:01,560 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:01,561 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:01,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:01,715 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:21:01,715 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:01,716 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:01,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:01,875 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 18:21:01,885 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 1 more)] === [2024-05-06 18:21:01,886 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:21:01,886 INFO L85 PathProgramCache]: Analyzing trace with hash -566126889, now seen corresponding path program 1 times [2024-05-06 18:21:01,889 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:21:01,890 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1667634287] [2024-05-06 18:21:01,890 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:01,890 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:01,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:02,195 INFO L134 CoverageAnalysis]: Checked inductivity of 390 backedges. 97 proven. 1 refuted. 0 times theorem prover too weak. 292 trivial. 0 not checked. [2024-05-06 18:21:02,196 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:21:02,196 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1667634287] [2024-05-06 18:21:02,196 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1667634287] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:21:02,196 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [767583141] [2024-05-06 18:21:02,196 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:02,196 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:21:02,197 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:21:02,229 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:21:02,230 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2024-05-06 18:21:03,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:03,267 INFO L262 TraceCheckSpWp]: Trace formula consists of 778 conjuncts, 10 conjunts are in the unsatisfiable core [2024-05-06 18:21:03,277 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 18:21:03,584 INFO L134 CoverageAnalysis]: Checked inductivity of 390 backedges. 97 proven. 1 refuted. 0 times theorem prover too weak. 292 trivial. 0 not checked. [2024-05-06 18:21:03,584 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-06 18:21:03,903 INFO L134 CoverageAnalysis]: Checked inductivity of 390 backedges. 97 proven. 1 refuted. 0 times theorem prover too weak. 292 trivial. 0 not checked. [2024-05-06 18:21:03,903 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [767583141] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-06 18:21:03,903 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-06 18:21:03,904 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 11, 11] total 25 [2024-05-06 18:21:03,905 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1639048798] [2024-05-06 18:21:03,905 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-06 18:21:03,908 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 25 states [2024-05-06 18:21:03,909 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:21:03,911 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2024-05-06 18:21:03,911 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=116, Invalid=484, Unknown=0, NotChecked=0, Total=600 [2024-05-06 18:21:03,912 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:21:03,912 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:21:03,913 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 25 states, 25 states have (on average 14.96) internal successors, (374), 25 states have internal predecessors, (374), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:21:03,913 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:21:04,405 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:21:04,477 INFO L85 PathProgramCache]: Analyzing trace with hash 858876178, now seen corresponding path program 3 times [2024-05-06 18:21:04,478 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:04,478 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:04,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:04,802 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 1 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:04,803 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:04,803 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:04,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:04,961 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 1 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:05,014 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:21:05,078 INFO L85 PathProgramCache]: Analyzing trace with hash 113612326, now seen corresponding path program 11 times [2024-05-06 18:21:05,078 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:05,078 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:05,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:05,232 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:05,232 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:05,232 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:05,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:05,526 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:05,542 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:21:05,597 INFO L85 PathProgramCache]: Analyzing trace with hash -772984471, now seen corresponding path program 12 times [2024-05-06 18:21:05,598 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:05,598 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:05,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:05,745 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:05,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:05,746 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:05,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:05,895 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:05,909 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 1930 treesize of output 1834 [2024-05-06 18:21:08,146 INFO L85 PathProgramCache]: Analyzing trace with hash 1807285896, now seen corresponding path program 13 times [2024-05-06 18:21:08,147 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:08,147 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:08,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:08,298 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:08,299 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:08,299 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:08,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:08,441 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:08,458 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:21:08,729 INFO L85 PathProgramCache]: Analyzing trace with hash -2026366099, now seen corresponding path program 4 times [2024-05-06 18:21:08,729 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:08,729 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:08,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:08,884 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:08,885 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:08,885 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:08,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:09,122 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:09,141 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:21:11,195 INFO L85 PathProgramCache]: Analyzing trace with hash -773003596, now seen corresponding path program 14 times [2024-05-06 18:21:11,195 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:11,196 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:11,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:11,345 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:11,345 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:11,345 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:11,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:11,495 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:11,515 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:21:11,578 INFO L85 PathProgramCache]: Analyzing trace with hash 113594506, now seen corresponding path program 15 times [2024-05-06 18:21:11,578 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:11,578 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:11,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:11,728 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:11,728 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:11,728 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:11,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:11,877 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:11,901 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:21:11,964 INFO L85 PathProgramCache]: Analyzing trace with hash -555760952, now seen corresponding path program 16 times [2024-05-06 18:21:11,964 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:11,964 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:11,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:12,109 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:12,109 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:12,110 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:12,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:12,345 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:12,365 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:21:12,445 INFO L85 PathProgramCache]: Analyzing trace with hash -48719594, now seen corresponding path program 17 times [2024-05-06 18:21:12,445 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:12,445 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:12,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:12,589 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:12,589 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:12,589 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:12,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:12,733 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:12,749 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 972 treesize of output 924 [2024-05-06 18:21:14,936 INFO L85 PathProgramCache]: Analyzing trace with hash -1510306678, now seen corresponding path program 18 times [2024-05-06 18:21:14,937 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:14,937 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:14,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:15,082 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:15,083 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:15,083 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:15,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:15,222 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:15,243 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:21:15,333 INFO L85 PathProgramCache]: Analyzing trace with hash -48709889, now seen corresponding path program 19 times [2024-05-06 18:21:15,333 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:15,333 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:15,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:15,482 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:15,482 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:15,482 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:15,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:15,692 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:15,712 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:21:17,769 INFO L85 PathProgramCache]: Analyzing trace with hash -555749012, now seen corresponding path program 20 times [2024-05-06 18:21:17,770 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:17,770 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:17,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:17,909 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:17,910 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:17,910 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:17,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:18,053 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:18,080 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:21:20,125 INFO L85 PathProgramCache]: Analyzing trace with hash 1527027058, now seen corresponding path program 3 times [2024-05-06 18:21:20,125 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:20,126 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:20,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:20,280 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 1 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:20,281 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:20,281 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:20,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:20,436 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 1 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:20,460 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:21:20,567 INFO L85 PathProgramCache]: Analyzing trace with hash -1510741370, now seen corresponding path program 11 times [2024-05-06 18:21:20,567 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:20,567 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:20,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:20,791 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:20,791 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:20,791 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:20,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:20,940 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:20,961 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:21:21,035 INFO L85 PathProgramCache]: Analyzing trace with hash 411658505, now seen corresponding path program 12 times [2024-05-06 18:21:21,035 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:21,035 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:21,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:21,186 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:21,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:21,186 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:21,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:21,335 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:21,350 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 952 treesize of output 904 [2024-05-06 18:21:22,152 INFO L85 PathProgramCache]: Analyzing trace with hash -123487512, now seen corresponding path program 13 times [2024-05-06 18:21:22,152 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:22,152 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:22,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:22,303 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:22,304 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:22,304 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:22,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:22,453 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:22,472 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:21:24,517 INFO L85 PathProgramCache]: Analyzing trace with hash -1358215219, now seen corresponding path program 4 times [2024-05-06 18:21:24,517 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:24,517 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:24,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:24,750 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:24,751 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:24,751 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:24,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:24,900 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:24,918 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:21:25,029 INFO L85 PathProgramCache]: Analyzing trace with hash 411639380, now seen corresponding path program 14 times [2024-05-06 18:21:25,029 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:25,029 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:25,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:25,230 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:25,230 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:25,230 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:25,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:25,379 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:25,409 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:21:25,493 INFO L85 PathProgramCache]: Analyzing trace with hash -1510759190, now seen corresponding path program 15 times [2024-05-06 18:21:25,493 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:25,493 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:25,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:25,635 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:25,635 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:25,636 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:25,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:25,777 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:25,888 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:21:27,957 INFO L85 PathProgramCache]: Analyzing trace with hash -850460056, now seen corresponding path program 16 times [2024-05-06 18:21:27,957 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:27,957 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:27,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:28,101 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:28,101 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:28,102 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:28,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:28,245 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:28,266 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:21:28,355 INFO L85 PathProgramCache]: Analyzing trace with hash -594457226, now seen corresponding path program 17 times [2024-05-06 18:21:28,355 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:28,355 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:28,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:28,500 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:28,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:28,501 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:28,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:28,647 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:28,664 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 1930 treesize of output 1834 [2024-05-06 18:21:30,879 INFO L85 PathProgramCache]: Analyzing trace with hash -1248304086, now seen corresponding path program 18 times [2024-05-06 18:21:30,880 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:30,880 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:30,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:31,024 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:31,025 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:31,025 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:31,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:31,253 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:31,274 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:21:33,332 INFO L85 PathProgramCache]: Analyzing trace with hash -594447521, now seen corresponding path program 19 times [2024-05-06 18:21:33,333 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:33,333 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:33,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:33,475 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:33,475 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:33,475 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:33,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:33,618 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:33,638 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:21:33,768 INFO L85 PathProgramCache]: Analyzing trace with hash -850448116, now seen corresponding path program 20 times [2024-05-06 18:21:33,768 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:33,768 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:33,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:33,913 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:33,913 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:33,914 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:33,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:34,055 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:34,080 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:21:36,125 INFO L85 PathProgramCache]: Analyzing trace with hash 154889683, now seen corresponding path program 3 times [2024-05-06 18:21:36,125 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:36,125 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:36,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:36,281 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 1 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:36,281 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:36,281 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:36,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:36,584 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 1 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:36,608 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:21:36,727 INFO L85 PathProgramCache]: Analyzing trace with hash 637309095, now seen corresponding path program 11 times [2024-05-06 18:21:36,727 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:36,727 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:36,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:36,872 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:36,872 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:36,872 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:36,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:37,017 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:37,034 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:21:37,092 INFO L85 PathProgramCache]: Analyzing trace with hash -1718253816, now seen corresponding path program 12 times [2024-05-06 18:21:37,092 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:37,092 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:37,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:37,237 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:37,238 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:37,238 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:37,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:37,383 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:37,397 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 972 treesize of output 924 [2024-05-06 18:21:37,637 INFO L85 PathProgramCache]: Analyzing trace with hash -1726260023, now seen corresponding path program 13 times [2024-05-06 18:21:37,637 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:37,637 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:37,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:37,935 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:37,935 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:37,935 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:37,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:38,084 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:38,103 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:21:38,165 INFO L85 PathProgramCache]: Analyzing trace with hash 1564614702, now seen corresponding path program 4 times [2024-05-06 18:21:38,165 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:38,166 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:38,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:38,320 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:38,320 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:38,320 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:38,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:38,473 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:38,492 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:21:40,548 INFO L85 PathProgramCache]: Analyzing trace with hash -1718272941, now seen corresponding path program 14 times [2024-05-06 18:21:40,548 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:40,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:40,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:40,696 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:40,696 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:40,696 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:40,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:40,973 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:40,994 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:21:41,077 INFO L85 PathProgramCache]: Analyzing trace with hash 637291275, now seen corresponding path program 15 times [2024-05-06 18:21:41,077 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:41,077 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:41,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:41,225 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:41,225 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:41,225 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:41,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:41,370 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:41,394 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:21:43,441 INFO L85 PathProgramCache]: Analyzing trace with hash 2049557287, now seen corresponding path program 16 times [2024-05-06 18:21:43,441 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:43,441 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:43,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:43,581 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:43,581 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:43,581 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:43,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:43,720 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:43,739 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:21:45,791 INFO L85 PathProgramCache]: Analyzing trace with hash -888232809, now seen corresponding path program 17 times [2024-05-06 18:21:45,791 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:45,791 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:45,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:46,057 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:46,057 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:46,057 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:46,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:46,199 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:46,213 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 952 treesize of output 904 [2024-05-06 18:21:48,361 INFO L85 PathProgramCache]: Analyzing trace with hash -1765412567, now seen corresponding path program 18 times [2024-05-06 18:21:48,361 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:48,361 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:48,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:48,506 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:48,506 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:48,507 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:48,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:48,645 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:48,666 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:21:50,722 INFO L85 PathProgramCache]: Analyzing trace with hash -888223104, now seen corresponding path program 19 times [2024-05-06 18:21:50,722 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:50,722 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:50,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:50,860 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:50,860 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:50,860 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:50,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:51,115 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:51,134 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:21:53,199 INFO L85 PathProgramCache]: Analyzing trace with hash 2049569227, now seen corresponding path program 20 times [2024-05-06 18:21:53,200 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:53,200 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:53,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:53,343 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:53,343 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:53,343 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:53,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:53,487 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:53,522 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:21:53,580 INFO L85 PathProgramCache]: Analyzing trace with hash -36137453, now seen corresponding path program 3 times [2024-05-06 18:21:53,580 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:53,581 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:53,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:53,743 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 1 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:53,744 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:53,744 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:53,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:53,894 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 1 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:53,943 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:21:54,024 INFO L85 PathProgramCache]: Analyzing trace with hash 967387367, now seen corresponding path program 11 times [2024-05-06 18:21:54,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:54,025 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:54,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:54,288 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:54,288 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:54,289 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:54,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:54,438 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:54,459 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:21:56,526 INFO L85 PathProgramCache]: Analyzing trace with hash -75761976, now seen corresponding path program 12 times [2024-05-06 18:21:56,527 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:56,527 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:56,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:56,674 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:56,674 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:56,674 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:56,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:56,821 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:56,836 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 473 treesize of output 449 [2024-05-06 18:21:58,191 INFO L85 PathProgramCache]: Analyzing trace with hash 1946346761, now seen corresponding path program 13 times [2024-05-06 18:21:58,191 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:58,191 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:58,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:58,336 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:58,337 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:21:58,337 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:21:58,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:21:58,565 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:21:58,590 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:22:00,631 INFO L85 PathProgramCache]: Analyzing trace with hash 1373587566, now seen corresponding path program 4 times [2024-05-06 18:22:00,631 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:00,631 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:00,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:00,787 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:00,787 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:00,787 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:00,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:00,948 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:00,969 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:22:03,025 INFO L85 PathProgramCache]: Analyzing trace with hash -75781101, now seen corresponding path program 14 times [2024-05-06 18:22:03,026 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:03,026 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:03,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:03,171 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:03,172 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:03,172 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:03,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:03,315 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:03,357 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:22:05,415 INFO L85 PathProgramCache]: Analyzing trace with hash 967369547, now seen corresponding path program 15 times [2024-05-06 18:22:05,416 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:05,416 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:05,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:05,638 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:05,638 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:05,638 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:05,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:05,786 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:05,810 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:22:07,877 INFO L85 PathProgramCache]: Analyzing trace with hash 480568039, now seen corresponding path program 16 times [2024-05-06 18:22:07,877 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:07,877 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:07,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:08,019 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:08,020 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:08,020 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:08,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:08,159 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:08,177 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:22:08,252 INFO L85 PathProgramCache]: Analyzing trace with hash 2012708055, now seen corresponding path program 17 times [2024-05-06 18:22:08,252 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:08,252 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:08,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:08,486 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:08,487 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:08,487 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:08,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:08,649 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:08,664 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 952 treesize of output 904 [2024-05-06 18:22:10,812 INFO L85 PathProgramCache]: Analyzing trace with hash -2030558999, now seen corresponding path program 18 times [2024-05-06 18:22:10,812 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:10,812 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:10,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:10,960 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:10,960 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:10,961 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:10,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:11,103 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:11,123 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:22:11,729 INFO L85 PathProgramCache]: Analyzing trace with hash 2012717760, now seen corresponding path program 19 times [2024-05-06 18:22:11,729 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:11,729 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:11,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:11,868 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:11,868 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:11,868 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:11,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:12,073 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:12,093 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:22:12,184 INFO L85 PathProgramCache]: Analyzing trace with hash 480579979, now seen corresponding path program 20 times [2024-05-06 18:22:12,184 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:12,184 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:12,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:12,323 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:12,324 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:12,324 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:12,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:12,470 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:12,490 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:22:12,581 INFO L85 PathProgramCache]: Analyzing trace with hash -1574537580, now seen corresponding path program 3 times [2024-05-06 18:22:12,582 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:12,582 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:12,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:12,734 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 1 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:12,735 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:12,735 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:12,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:12,886 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 1 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:12,912 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:22:13,105 INFO L85 PathProgramCache]: Analyzing trace with hash -1670672600, now seen corresponding path program 11 times [2024-05-06 18:22:13,105 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:13,105 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:13,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:13,283 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:13,283 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:13,283 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:13,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:13,449 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:13,468 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:22:13,545 INFO L85 PathProgramCache]: Analyzing trace with hash -251242329, now seen corresponding path program 12 times [2024-05-06 18:22:13,546 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:13,546 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:13,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:13,713 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:13,714 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:13,714 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:13,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:13,882 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:13,898 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 952 treesize of output 904 [2024-05-06 18:22:16,104 INFO L85 PathProgramCache]: Analyzing trace with hash 801423114, now seen corresponding path program 13 times [2024-05-06 18:22:16,104 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:16,104 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:16,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:16,327 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:16,328 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:16,328 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:16,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:16,473 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:16,516 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:22:16,594 INFO L85 PathProgramCache]: Analyzing trace with hash -164812561, now seen corresponding path program 4 times [2024-05-06 18:22:16,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:16,594 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:16,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:16,754 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:16,754 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:16,754 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:16,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:16,911 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:16,931 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:22:17,065 INFO L85 PathProgramCache]: Analyzing trace with hash -251261454, now seen corresponding path program 14 times [2024-05-06 18:22:17,065 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:17,065 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:17,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:17,315 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:17,315 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:17,315 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:17,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:17,492 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:17,512 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:22:17,602 INFO L85 PathProgramCache]: Analyzing trace with hash -1670690420, now seen corresponding path program 15 times [2024-05-06 18:22:17,602 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:17,602 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:17,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:17,772 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:17,773 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:17,773 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:17,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:17,934 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:17,958 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:22:18,045 INFO L85 PathProgramCache]: Analyzing trace with hash 845627270, now seen corresponding path program 16 times [2024-05-06 18:22:18,046 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:18,046 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:18,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:18,205 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:18,205 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:18,206 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:18,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:18,427 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:18,446 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:22:18,518 INFO L85 PathProgramCache]: Analyzing trace with hash 444642328, now seen corresponding path program 17 times [2024-05-06 18:22:18,519 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:18,519 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:18,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:18,679 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:18,679 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:18,679 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:18,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:18,871 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:18,886 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 972 treesize of output 924 [2024-05-06 18:22:19,286 INFO L85 PathProgramCache]: Analyzing trace with hash 899011016, now seen corresponding path program 18 times [2024-05-06 18:22:19,286 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:19,286 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:19,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:19,427 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:19,427 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:19,427 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:19,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:19,635 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:19,654 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:22:21,709 INFO L85 PathProgramCache]: Analyzing trace with hash 444652033, now seen corresponding path program 19 times [2024-05-06 18:22:21,709 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:21,709 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:21,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:21,850 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:21,851 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:21,851 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:21,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:21,991 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:22,010 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:22:22,097 INFO L85 PathProgramCache]: Analyzing trace with hash 845639210, now seen corresponding path program 20 times [2024-05-06 18:22:22,097 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:22,097 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:22,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:22,237 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:22,238 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:22,238 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:22,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:22,447 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:22,467 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:22:22,533 INFO L85 PathProgramCache]: Analyzing trace with hash 1414075636, now seen corresponding path program 7 times [2024-05-06 18:22:22,534 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:22,534 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:22,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:22:22,643 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:22:22,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:22:22,770 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:22:22,850 INFO L85 PathProgramCache]: Analyzing trace with hash 886672475, now seen corresponding path program 8 times [2024-05-06 18:22:22,850 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:22,850 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:22,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:22:22,916 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:22:22,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:22:23,024 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 952 treesize of output 904 [2024-05-06 18:22:23,917 INFO L85 PathProgramCache]: Analyzing trace with hash 1717043670, now seen corresponding path program 9 times [2024-05-06 18:22:23,918 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:23,918 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:23,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:22:23,958 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:22:23,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:22:24,034 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:22:24,103 INFO L85 PathProgramCache]: Analyzing trace with hash 1656708577, now seen corresponding path program 10 times [2024-05-06 18:22:24,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:24,103 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:24,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:24,269 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:24,270 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:24,270 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:24,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:24,419 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:24,438 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:22:24,521 INFO L85 PathProgramCache]: Analyzing trace with hash -181640931, now seen corresponding path program 11 times [2024-05-06 18:22:24,521 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:24,521 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:24,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:24,809 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:24,810 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:24,810 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:24,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:25,131 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:25,145 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 473 treesize of output 449 [2024-05-06 18:22:25,219 INFO L85 PathProgramCache]: Analyzing trace with hash -1335900829, now seen corresponding path program 12 times [2024-05-06 18:22:25,219 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:25,219 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:25,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:25,389 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 37 trivial. 0 not checked. [2024-05-06 18:22:25,390 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:25,390 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:25,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:25,572 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 37 trivial. 0 not checked. [2024-05-06 18:22:25,600 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:22:25,711 INFO L85 PathProgramCache]: Analyzing trace with hash -53234003, now seen corresponding path program 147 times [2024-05-06 18:22:25,712 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:25,712 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:25,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:26,120 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:22:26,121 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:26,121 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:26,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:26,490 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:22:26,510 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:22:26,640 INFO L85 PathProgramCache]: Analyzing trace with hash -1650253374, now seen corresponding path program 148 times [2024-05-06 18:22:26,640 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:26,641 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:26,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:27,014 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:22:27,014 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:27,014 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:27,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:27,253 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:22:27,287 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 1930 treesize of output 1834 [2024-05-06 18:22:29,447 INFO L85 PathProgramCache]: Analyzing trace with hash 381753679, now seen corresponding path program 149 times [2024-05-06 18:22:29,447 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:29,447 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:29,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:29,730 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:22:29,730 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:29,730 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:29,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:29,905 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:22:29,922 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:22:31,971 INFO L85 PathProgramCache]: Analyzing trace with hash -1664924748, now seen corresponding path program 12 times [2024-05-06 18:22:31,972 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:31,972 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:32,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:32,145 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:22:32,146 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:32,146 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:32,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:32,312 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:22:32,381 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:22:32,450 INFO L85 PathProgramCache]: Analyzing trace with hash -1650286914, now seen corresponding path program 150 times [2024-05-06 18:22:32,450 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:32,450 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:32,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:32,641 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:22:32,641 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:32,641 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:32,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:32,853 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:22:32,875 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:22:32,959 INFO L85 PathProgramCache]: Analyzing trace with hash -53266703, now seen corresponding path program 151 times [2024-05-06 18:22:32,960 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:32,960 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:33,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:33,318 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:22:33,319 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:33,319 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:33,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:33,633 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:22:33,698 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:22:33,805 INFO L85 PathProgramCache]: Analyzing trace with hash 514049345, now seen corresponding path program 152 times [2024-05-06 18:22:33,805 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:33,805 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:33,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:34,109 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:34,110 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:34,110 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:34,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:34,294 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:34,314 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:22:36,385 INFO L85 PathProgramCache]: Analyzing trace with hash -1244338740, now seen corresponding path program 153 times [2024-05-06 18:22:36,385 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:36,385 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:36,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:36,652 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:36,653 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:36,653 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:36,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:36,969 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:37,000 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 952 treesize of output 904 [2024-05-06 18:22:37,679 INFO L85 PathProgramCache]: Analyzing trace with hash 80205475, now seen corresponding path program 154 times [2024-05-06 18:22:37,679 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:37,679 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:37,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:37,840 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:37,840 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:37,840 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:37,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:38,004 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:38,024 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:22:38,811 INFO L85 PathProgramCache]: Analyzing trace with hash -1244314620, now seen corresponding path program 155 times [2024-05-06 18:22:38,811 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:38,811 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:38,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:39,079 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:39,079 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:39,079 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:39,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:39,297 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:39,317 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:22:39,393 INFO L85 PathProgramCache]: Analyzing trace with hash 514076165, now seen corresponding path program 156 times [2024-05-06 18:22:39,393 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:39,393 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:39,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:39,579 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:39,579 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:39,579 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:39,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:39,754 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:39,773 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:22:40,135 INFO L85 PathProgramCache]: Analyzing trace with hash 1604509254, now seen corresponding path program 13 times [2024-05-06 18:22:40,136 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:40,136 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:40,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:40,461 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:40,461 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:40,461 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:40,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:40,642 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:40,666 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:22:40,791 INFO L85 PathProgramCache]: Analyzing trace with hash -533697112, now seen corresponding path program 157 times [2024-05-06 18:22:40,791 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:40,792 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:40,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:40,996 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:22:40,996 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:40,996 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:41,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:41,188 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:22:41,208 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:22:41,268 INFO L85 PathProgramCache]: Analyzing trace with hash 635259431, now seen corresponding path program 158 times [2024-05-06 18:22:41,268 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:41,269 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:41,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:41,492 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:22:41,492 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:41,492 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:41,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:41,661 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:22:41,676 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 952 treesize of output 904 [2024-05-06 18:22:41,959 INFO L85 PathProgramCache]: Analyzing trace with hash -1781793398, now seen corresponding path program 159 times [2024-05-06 18:22:41,959 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:41,959 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:41,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:42,121 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:22:42,121 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:42,121 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:42,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:42,309 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:22:42,328 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:22:42,675 INFO L85 PathProgramCache]: Analyzing trace with hash -2033539217, now seen corresponding path program 14 times [2024-05-06 18:22:42,676 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:42,676 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:42,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:42,920 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:22:42,920 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:42,920 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:42,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:43,094 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:22:43,116 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:22:43,199 INFO L85 PathProgramCache]: Analyzing trace with hash 635225891, now seen corresponding path program 160 times [2024-05-06 18:22:43,199 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:43,199 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:43,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:43,364 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:22:43,364 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:43,364 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:43,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:43,529 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:22:43,550 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:22:43,631 INFO L85 PathProgramCache]: Analyzing trace with hash -533729812, now seen corresponding path program 161 times [2024-05-06 18:22:43,632 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:43,632 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:43,662 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:43,878 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:22:43,878 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:43,878 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:43,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:44,061 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:22:44,086 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:22:44,161 INFO L85 PathProgramCache]: Analyzing trace with hash 1528641510, now seen corresponding path program 162 times [2024-05-06 18:22:44,161 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:44,161 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:44,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:44,345 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:44,345 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:44,345 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:44,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:44,528 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:44,549 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:22:46,120 INFO L85 PathProgramCache]: Analyzing trace with hash 143247303, now seen corresponding path program 163 times [2024-05-06 18:22:46,120 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:46,120 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:46,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:46,346 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:46,346 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:46,347 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:46,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:46,500 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:46,515 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 952 treesize of output 904 [2024-05-06 18:22:46,650 INFO L85 PathProgramCache]: Analyzing trace with hash 145699848, now seen corresponding path program 164 times [2024-05-06 18:22:46,650 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:46,650 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:46,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:46,807 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:46,807 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:46,807 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:46,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:46,964 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:46,986 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:22:47,069 INFO L85 PathProgramCache]: Analyzing trace with hash 143271423, now seen corresponding path program 165 times [2024-05-06 18:22:47,069 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:47,069 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:47,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:47,285 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:47,286 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:47,286 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:47,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:47,440 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:47,462 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:22:47,527 INFO L85 PathProgramCache]: Analyzing trace with hash 1528668330, now seen corresponding path program 166 times [2024-05-06 18:22:47,527 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:47,528 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:47,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:47,703 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:47,704 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:47,704 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:47,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:47,852 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:47,869 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:22:49,905 INFO L85 PathProgramCache]: Analyzing trace with hash -1462744383, now seen corresponding path program 15 times [2024-05-06 18:22:49,906 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:49,906 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:49,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:50,135 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:50,135 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:50,135 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:50,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:50,316 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:22:50,379 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:22:50,517 INFO L85 PathProgramCache]: Analyzing trace with hash 1792920846, now seen corresponding path program 167 times [2024-05-06 18:22:50,517 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:50,517 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:50,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:50,698 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:22:50,698 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:50,698 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:50,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:50,878 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:22:50,897 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:22:52,962 INFO L85 PathProgramCache]: Analyzing trace with hash -254027903, now seen corresponding path program 168 times [2024-05-06 18:22:52,962 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:52,962 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:52,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:53,267 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:22:53,267 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:53,267 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:53,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:53,431 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:22:53,449 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 473 treesize of output 449 [2024-05-06 18:22:55,619 INFO L85 PathProgramCache]: Analyzing trace with hash 715070320, now seen corresponding path program 169 times [2024-05-06 18:22:55,620 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:55,620 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:55,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:55,792 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:22:55,792 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:55,792 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:55,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:55,971 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:22:55,992 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:22:58,039 INFO L85 PathProgramCache]: Analyzing trace with hash -1735254955, now seen corresponding path program 16 times [2024-05-06 18:22:58,039 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:58,039 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:58,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:58,331 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:22:58,331 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:22:58,331 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:22:58,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:22:58,495 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:22:58,517 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:00,578 INFO L85 PathProgramCache]: Analyzing trace with hash -254061443, now seen corresponding path program 170 times [2024-05-06 18:23:00,579 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:00,579 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:00,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:00,756 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:00,756 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:00,756 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:00,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:00,918 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:00,940 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:01,042 INFO L85 PathProgramCache]: Analyzing trace with hash 1792888146, now seen corresponding path program 171 times [2024-05-06 18:23:01,043 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:01,043 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:01,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:01,291 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:01,291 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:01,291 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:01,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:01,474 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:01,500 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:01,569 INFO L85 PathProgramCache]: Analyzing trace with hash 810667456, now seen corresponding path program 172 times [2024-05-06 18:23:01,569 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:01,570 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:01,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:01,755 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:01,756 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:01,756 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:01,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:02,043 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:02,065 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:02,196 INFO L85 PathProgramCache]: Analyzing trace with hash -639111891, now seen corresponding path program 173 times [2024-05-06 18:23:02,196 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:02,196 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:02,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:02,541 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:02,541 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:02,541 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:02,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:02,776 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:02,791 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 952 treesize of output 904 [2024-05-06 18:23:03,241 INFO L85 PathProgramCache]: Analyzing trace with hash 1662368610, now seen corresponding path program 174 times [2024-05-06 18:23:03,241 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:03,241 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:03,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:03,419 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:03,419 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:03,419 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:03,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:03,646 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:03,668 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:03,782 INFO L85 PathProgramCache]: Analyzing trace with hash -639087771, now seen corresponding path program 175 times [2024-05-06 18:23:03,782 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:03,782 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:03,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:03,958 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:03,959 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:03,959 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:03,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:04,116 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:04,152 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:04,237 INFO L85 PathProgramCache]: Analyzing trace with hash 810694276, now seen corresponding path program 176 times [2024-05-06 18:23:04,237 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:04,237 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:04,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:04,390 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:04,390 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:04,390 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:04,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:04,626 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:04,645 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:23:04,710 INFO L85 PathProgramCache]: Analyzing trace with hash -1439609561, now seen corresponding path program 17 times [2024-05-06 18:23:04,710 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:04,710 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:04,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:04,865 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:04,865 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:04,865 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:04,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:05,020 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:05,043 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:05,109 INFO L85 PathProgramCache]: Analyzing trace with hash -1331803479, now seen corresponding path program 177 times [2024-05-06 18:23:05,109 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:05,109 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:05,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:05,316 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:05,316 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:05,316 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:05,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:05,468 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:05,487 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:05,566 INFO L85 PathProgramCache]: Analyzing trace with hash 1663765830, now seen corresponding path program 178 times [2024-05-06 18:23:05,566 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:05,566 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:05,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:05,721 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:05,721 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:05,721 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:05,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:05,874 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:05,889 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 1930 treesize of output 1834 [2024-05-06 18:23:06,241 INFO L85 PathProgramCache]: Analyzing trace with hash 37133899, now seen corresponding path program 179 times [2024-05-06 18:23:06,241 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:06,241 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:06,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:06,490 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:06,491 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:06,491 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:06,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:06,668 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:06,686 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:23:08,729 INFO L85 PathProgramCache]: Analyzing trace with hash 1494036144, now seen corresponding path program 18 times [2024-05-06 18:23:08,729 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:08,730 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:08,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:08,891 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:08,891 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:08,891 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:08,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:09,120 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:09,140 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:11,195 INFO L85 PathProgramCache]: Analyzing trace with hash 1663732290, now seen corresponding path program 180 times [2024-05-06 18:23:11,196 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:11,196 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:11,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:11,350 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:11,350 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:11,350 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:11,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:11,504 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:11,523 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:13,579 INFO L85 PathProgramCache]: Analyzing trace with hash -1331836179, now seen corresponding path program 181 times [2024-05-06 18:23:13,580 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:13,580 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:13,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:13,786 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:13,786 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:13,786 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:13,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:13,940 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:13,964 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:14,035 INFO L85 PathProgramCache]: Analyzing trace with hash -101743163, now seen corresponding path program 182 times [2024-05-06 18:23:14,035 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:14,035 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:14,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:14,182 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:14,182 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:14,182 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:14,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:14,329 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:14,345 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:15,019 INFO L85 PathProgramCache]: Analyzing trace with hash 1140929992, now seen corresponding path program 183 times [2024-05-06 18:23:15,019 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:15,020 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:15,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:15,242 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:15,242 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:15,242 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:15,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:15,443 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:15,477 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 972 treesize of output 924 [2024-05-06 18:23:15,720 INFO L85 PathProgramCache]: Analyzing trace with hash 1009092135, now seen corresponding path program 184 times [2024-05-06 18:23:15,720 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:15,720 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:15,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:15,897 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:15,897 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:15,897 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:15,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:16,144 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:16,166 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:18,232 INFO L85 PathProgramCache]: Analyzing trace with hash 1140954112, now seen corresponding path program 185 times [2024-05-06 18:23:18,232 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:18,232 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:18,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:18,381 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:18,381 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:18,381 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:18,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:18,532 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:18,554 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:20,622 INFO L85 PathProgramCache]: Analyzing trace with hash -101716343, now seen corresponding path program 186 times [2024-05-06 18:23:20,622 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:20,622 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:20,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:20,857 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:20,857 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:20,857 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:20,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:21,007 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:21,028 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:23:23,068 INFO L85 PathProgramCache]: Analyzing trace with hash 1592709186, now seen corresponding path program 19 times [2024-05-06 18:23:23,068 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:23,068 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:23,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:23,220 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:23,220 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:23,220 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:23,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:23,440 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:23,462 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:23,591 INFO L85 PathProgramCache]: Analyzing trace with hash 1879347055, now seen corresponding path program 187 times [2024-05-06 18:23:23,591 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:23,592 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:23,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:23,769 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:23,769 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:23,769 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:23,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:23,948 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:23,967 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:24,025 INFO L85 PathProgramCache]: Analyzing trace with hash -1869782720, now seen corresponding path program 188 times [2024-05-06 18:23:24,025 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:24,026 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:24,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:24,257 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:24,258 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:24,258 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:24,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:24,437 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:24,451 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 952 treesize of output 904 [2024-05-06 18:23:25,197 INFO L85 PathProgramCache]: Analyzing trace with hash -2128688751, now seen corresponding path program 189 times [2024-05-06 18:23:25,198 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:25,198 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:25,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:25,380 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:25,380 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:25,380 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:25,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:25,621 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:25,655 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:23:27,696 INFO L85 PathProgramCache]: Analyzing trace with hash -169828106, now seen corresponding path program 20 times [2024-05-06 18:23:27,697 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:27,697 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:27,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:27,856 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:27,857 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:27,857 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:27,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:28,016 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:28,034 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:28,098 INFO L85 PathProgramCache]: Analyzing trace with hash -1869816260, now seen corresponding path program 190 times [2024-05-06 18:23:28,098 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:28,098 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:28,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:28,295 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:28,295 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:28,295 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:28,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:28,446 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:28,463 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:29,150 INFO L85 PathProgramCache]: Analyzing trace with hash 1879314355, now seen corresponding path program 191 times [2024-05-06 18:23:29,150 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:29,151 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:29,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:29,302 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:29,302 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:29,302 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:29,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:29,519 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:29,546 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:29,620 INFO L85 PathProgramCache]: Analyzing trace with hash -743331265, now seen corresponding path program 192 times [2024-05-06 18:23:29,620 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:29,620 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:29,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:29,795 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:29,795 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:29,795 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:29,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:29,972 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:29,991 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:30,071 INFO L85 PathProgramCache]: Analyzing trace with hash -1568431986, now seen corresponding path program 193 times [2024-05-06 18:23:30,072 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:30,072 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:30,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:30,370 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:30,370 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:30,370 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:30,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:30,544 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:30,560 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 952 treesize of output 904 [2024-05-06 18:23:33,796 INFO L85 PathProgramCache]: Analyzing trace with hash -1376750559, now seen corresponding path program 194 times [2024-05-06 18:23:33,797 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:33,797 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:33,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:33,997 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:33,997 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:33,998 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:34,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:34,144 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:34,161 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:34,212 INFO L85 PathProgramCache]: Analyzing trace with hash -1568407866, now seen corresponding path program 195 times [2024-05-06 18:23:34,213 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:34,213 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:34,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:34,363 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:34,363 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:34,363 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:34,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:34,634 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:34,670 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:34,775 INFO L85 PathProgramCache]: Analyzing trace with hash -743304445, now seen corresponding path program 196 times [2024-05-06 18:23:34,776 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:34,776 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:34,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:34,953 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:34,953 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:34,953 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:34,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:35,129 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:35,145 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:23:37,184 INFO L85 PathProgramCache]: Analyzing trace with hash -1928173560, now seen corresponding path program 21 times [2024-05-06 18:23:37,184 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:37,184 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:37,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:37,405 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:37,405 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:37,405 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:37,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:37,606 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:37,627 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:39,693 INFO L85 PathProgramCache]: Analyzing trace with hash 921509477, now seen corresponding path program 197 times [2024-05-06 18:23:39,693 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:39,693 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:39,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:39,892 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:39,892 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:39,893 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:39,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:40,043 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:40,063 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:40,139 INFO L85 PathProgramCache]: Analyzing trace with hash -1497976566, now seen corresponding path program 198 times [2024-05-06 18:23:40,140 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:40,140 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:40,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:40,289 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:40,290 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:40,290 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:40,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:40,503 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:40,519 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 473 treesize of output 449 [2024-05-06 18:23:41,560 INFO L85 PathProgramCache]: Analyzing trace with hash 807367431, now seen corresponding path program 199 times [2024-05-06 18:23:41,561 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:41,561 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:41,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:41,732 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:41,733 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:41,733 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:41,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:41,912 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:41,977 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:42,035 INFO L85 PathProgramCache]: Analyzing trace with hash -752018133, now seen corresponding path program 200 times [2024-05-06 18:23:42,035 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:42,035 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:42,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:42,225 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:42,226 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:42,226 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:42,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:42,411 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:42,430 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:42,501 INFO L85 PathProgramCache]: Analyzing trace with hash -1837724894, now seen corresponding path program 201 times [2024-05-06 18:23:42,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:42,501 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:42,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:42,745 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:42,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:42,746 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:42,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:42,903 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:42,916 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 1930 treesize of output 1834 [2024-05-06 18:23:42,980 INFO L85 PathProgramCache]: Analyzing trace with hash -1134896115, now seen corresponding path program 202 times [2024-05-06 18:23:42,981 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:42,981 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:43,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:43,188 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:43,189 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:43,189 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:43,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:43,353 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:43,402 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:43,469 INFO L85 PathProgramCache]: Analyzing trace with hash -1837715189, now seen corresponding path program 203 times [2024-05-06 18:23:43,470 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:43,470 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:43,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:43,720 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:43,720 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:43,720 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:43,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:43,877 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:43,898 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:43,995 INFO L85 PathProgramCache]: Analyzing trace with hash -752006193, now seen corresponding path program 204 times [2024-05-06 18:23:43,995 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:43,995 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:44,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:44,154 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:44,154 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:44,154 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:44,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:44,393 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:44,448 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:44,525 INFO L85 PathProgramCache]: Analyzing trace with hash 1823657793, now seen corresponding path program 205 times [2024-05-06 18:23:44,525 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:44,525 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:44,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:44,679 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:44,679 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:44,679 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:44,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:44,877 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:44,893 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:44,958 INFO L85 PathProgramCache]: Analyzing trace with hash 698817469, now seen corresponding path program 206 times [2024-05-06 18:23:44,958 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:44,958 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:44,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:45,111 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:45,112 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:45,112 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:45,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:45,323 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:45,336 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 1930 treesize of output 1834 [2024-05-06 18:23:45,408 INFO L85 PathProgramCache]: Analyzing trace with hash 188505795, now seen corresponding path program 207 times [2024-05-06 18:23:45,408 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:45,408 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:45,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:45,585 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:45,586 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:45,586 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:45,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:45,812 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:45,832 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:45,904 INFO L85 PathProgramCache]: Analyzing trace with hash 698798344, now seen corresponding path program 208 times [2024-05-06 18:23:45,904 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:45,904 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:45,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:46,083 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:46,083 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:46,083 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:46,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:46,302 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:46,321 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:46,386 INFO L85 PathProgramCache]: Analyzing trace with hash 1823639973, now seen corresponding path program 209 times [2024-05-06 18:23:46,387 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:46,387 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:46,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:46,565 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:46,566 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:46,566 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:46,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:46,824 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:46,852 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:46,922 INFO L85 PathProgramCache]: Analyzing trace with hash -321623185, now seen corresponding path program 210 times [2024-05-06 18:23:46,922 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:46,923 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:46,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:47,170 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:47,170 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:47,170 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:47,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:47,357 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:47,377 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:47,487 INFO L85 PathProgramCache]: Analyzing trace with hash -1380383394, now seen corresponding path program 211 times [2024-05-06 18:23:47,487 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:47,487 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:47,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:47,740 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:47,740 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:47,740 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:47,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:47,902 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:47,915 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 972 treesize of output 924 [2024-05-06 18:23:47,981 INFO L85 PathProgramCache]: Analyzing trace with hash 157788497, now seen corresponding path program 212 times [2024-05-06 18:23:47,981 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:47,981 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:48,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:48,147 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:48,147 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:48,148 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:48,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:48,362 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:48,383 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:48,464 INFO L85 PathProgramCache]: Analyzing trace with hash -1380373689, now seen corresponding path program 213 times [2024-05-06 18:23:48,465 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:48,465 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:48,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:48,626 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:48,627 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:48,627 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:48,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:48,844 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:48,864 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:48,922 INFO L85 PathProgramCache]: Analyzing trace with hash -321611245, now seen corresponding path program 214 times [2024-05-06 18:23:48,922 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:48,922 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:48,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:49,085 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:49,085 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:49,085 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:49,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:49,250 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:49,271 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:49,339 INFO L85 PathProgramCache]: Analyzing trace with hash 186754173, now seen corresponding path program 215 times [2024-05-06 18:23:49,340 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:49,340 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:49,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:49,572 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:49,572 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:49,572 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:49,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:49,787 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:49,806 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:51,263 INFO L85 PathProgramCache]: Analyzing trace with hash 1494412801, now seen corresponding path program 216 times [2024-05-06 18:23:51,263 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:51,263 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:51,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:51,476 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:51,476 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:51,476 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:51,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:51,676 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:51,690 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 972 treesize of output 924 [2024-05-06 18:23:51,760 INFO L85 PathProgramCache]: Analyzing trace with hash -917842689, now seen corresponding path program 217 times [2024-05-06 18:23:51,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:51,760 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:51,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:51,921 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:51,921 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:51,921 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:52,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:52,184 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:52,203 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:52,403 INFO L85 PathProgramCache]: Analyzing trace with hash 1494393676, now seen corresponding path program 218 times [2024-05-06 18:23:52,403 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:52,403 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:52,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:52,591 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:52,591 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:52,592 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:52,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:52,778 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:52,797 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:52,860 INFO L85 PathProgramCache]: Analyzing trace with hash 186736353, now seen corresponding path program 219 times [2024-05-06 18:23:52,860 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:52,860 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:52,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:53,049 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:53,049 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:53,049 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:53,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:53,391 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:23:53,416 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:53,477 INFO L85 PathProgramCache]: Analyzing trace with hash -1152211348, now seen corresponding path program 220 times [2024-05-06 18:23:53,478 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:53,478 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:53,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:53,670 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:53,670 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:53,670 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:53,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:53,866 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:53,886 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:55,944 INFO L85 PathProgramCache]: Analyzing trace with hash -1358812671, now seen corresponding path program 221 times [2024-05-06 18:23:55,944 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:55,944 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:55,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:56,115 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:56,116 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:56,116 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:56,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:56,282 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:56,296 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 972 treesize of output 924 [2024-05-06 18:23:56,350 INFO L85 PathProgramCache]: Analyzing trace with hash 826480910, now seen corresponding path program 222 times [2024-05-06 18:23:56,354 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:56,354 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:56,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:56,600 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:56,600 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:56,600 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:56,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:56,758 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:56,791 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:56,845 INFO L85 PathProgramCache]: Analyzing trace with hash -1358802966, now seen corresponding path program 223 times [2024-05-06 18:23:56,846 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:56,846 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:56,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:57,004 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:57,005 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:57,005 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:57,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:57,164 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:57,182 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:57,229 INFO L85 PathProgramCache]: Analyzing trace with hash -1152199408, now seen corresponding path program 224 times [2024-05-06 18:23:57,229 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:57,229 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:57,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:57,520 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:57,520 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:57,520 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:57,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:23:57,769 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:23:57,797 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:23:59,868 INFO L85 PathProgramCache]: Analyzing trace with hash -1586583328, now seen corresponding path program 225 times [2024-05-06 18:23:59,868 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:23:59,868 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:23:59,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:00,112 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:00,112 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:00,113 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:00,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:00,324 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:00,344 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:00,415 INFO L85 PathProgramCache]: Analyzing trace with hash -1939442178, now seen corresponding path program 226 times [2024-05-06 18:24:00,415 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:00,416 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:00,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:00,595 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:00,595 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:00,595 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:00,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:00,858 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:00,874 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 952 treesize of output 904 [2024-05-06 18:24:00,970 INFO L85 PathProgramCache]: Analyzing trace with hash 6835362, now seen corresponding path program 227 times [2024-05-06 18:24:00,970 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:00,970 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:01,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:01,136 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:01,136 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:01,137 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:01,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:01,300 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:01,321 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:01,406 INFO L85 PathProgramCache]: Analyzing trace with hash -1939461303, now seen corresponding path program 228 times [2024-05-06 18:24:01,407 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:01,407 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:01,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:01,566 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:01,567 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:01,567 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:01,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:01,729 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:01,748 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:01,831 INFO L85 PathProgramCache]: Analyzing trace with hash -1586601148, now seen corresponding path program 229 times [2024-05-06 18:24:01,831 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:01,831 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:01,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:02,071 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:02,071 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:02,071 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:02,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:02,226 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:02,248 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:02,325 INFO L85 PathProgramCache]: Analyzing trace with hash -360908400, now seen corresponding path program 230 times [2024-05-06 18:24:02,325 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:02,325 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:02,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:02,505 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:24:02,505 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:02,506 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:02,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:02,663 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:24:02,680 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:04,744 INFO L85 PathProgramCache]: Analyzing trace with hash 1696742237, now seen corresponding path program 231 times [2024-05-06 18:24:04,744 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:04,744 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:04,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:04,906 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:24:04,906 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:04,906 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:04,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:05,072 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:24:05,085 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 952 treesize of output 904 [2024-05-06 18:24:05,160 INFO L85 PathProgramCache]: Analyzing trace with hash 1059402546, now seen corresponding path program 232 times [2024-05-06 18:24:05,161 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:05,161 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:05,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:05,419 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:24:05,420 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:05,420 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:05,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:05,606 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:24:05,633 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:05,726 INFO L85 PathProgramCache]: Analyzing trace with hash 1696751942, now seen corresponding path program 233 times [2024-05-06 18:24:05,726 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:05,726 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:05,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:05,914 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:24:05,914 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:05,914 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:05,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:06,102 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:24:06,125 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:06,188 INFO L85 PathProgramCache]: Analyzing trace with hash -360896460, now seen corresponding path program 234 times [2024-05-06 18:24:06,188 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:06,188 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:06,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:06,405 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:24:06,405 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:06,406 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:06,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:06,698 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:24:06,720 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:08,772 INFO L85 PathProgramCache]: Analyzing trace with hash -1286111940, now seen corresponding path program 235 times [2024-05-06 18:24:08,772 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:08,772 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:08,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:08,935 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:08,935 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:08,936 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:08,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:09,096 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:09,115 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:09,202 INFO L85 PathProgramCache]: Analyzing trace with hash -1214763742, now seen corresponding path program 236 times [2024-05-06 18:24:09,202 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:09,202 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:09,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:09,361 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:09,361 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:09,361 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:09,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:09,544 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:09,565 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 1930 treesize of output 1834 [2024-05-06 18:24:09,660 INFO L85 PathProgramCache]: Analyzing trace with hash 997030398, now seen corresponding path program 237 times [2024-05-06 18:24:09,661 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:09,661 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:09,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:09,816 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:09,816 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:09,816 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:09,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:10,116 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:10,135 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:10,257 INFO L85 PathProgramCache]: Analyzing trace with hash -1214782867, now seen corresponding path program 238 times [2024-05-06 18:24:10,258 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:10,258 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:10,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:10,414 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:10,414 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:10,414 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:10,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:10,576 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:10,620 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:10,712 INFO L85 PathProgramCache]: Analyzing trace with hash -1286129760, now seen corresponding path program 239 times [2024-05-06 18:24:10,712 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:10,712 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:10,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:10,876 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:10,876 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:10,876 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:10,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:11,051 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:11,075 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:11,152 INFO L85 PathProgramCache]: Analyzing trace with hash 1452544941, now seen corresponding path program 240 times [2024-05-06 18:24:11,152 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:11,152 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:11,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:11,325 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:24:11,325 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:11,325 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:11,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:11,614 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:24:11,643 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:11,774 INFO L85 PathProgramCache]: Analyzing trace with hash 2079220960, now seen corresponding path program 241 times [2024-05-06 18:24:11,774 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:11,774 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:11,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:11,957 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:24:11,957 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:11,957 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:11,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:12,140 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:24:12,166 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 972 treesize of output 924 [2024-05-06 18:24:12,257 INFO L85 PathProgramCache]: Analyzing trace with hash 31341071, now seen corresponding path program 242 times [2024-05-06 18:24:12,257 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:12,257 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:12,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:12,438 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:24:12,439 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:12,439 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:12,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:12,729 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:24:12,759 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:14,815 INFO L85 PathProgramCache]: Analyzing trace with hash 2079230665, now seen corresponding path program 243 times [2024-05-06 18:24:14,815 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:14,816 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:14,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:15,009 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:24:15,009 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:15,009 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:15,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:15,315 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:24:15,337 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:15,478 INFO L85 PathProgramCache]: Analyzing trace with hash 1452556881, now seen corresponding path program 244 times [2024-05-06 18:24:15,478 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:15,478 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:15,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:15,646 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:24:15,647 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:15,647 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:15,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:15,814 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 18:24:15,837 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:16,005 INFO L85 PathProgramCache]: Analyzing trace with hash 1298013823, now seen corresponding path program 245 times [2024-05-06 18:24:16,005 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:16,005 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:16,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:16,171 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:16,171 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:16,171 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:16,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:16,332 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:16,354 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:16,418 INFO L85 PathProgramCache]: Analyzing trace with hash 1583723583, now seen corresponding path program 246 times [2024-05-06 18:24:16,418 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:16,418 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:16,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:16,584 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:16,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:16,584 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:16,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:16,872 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:16,887 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 473 treesize of output 449 [2024-05-06 18:24:16,977 INFO L85 PathProgramCache]: Analyzing trace with hash 1850791553, now seen corresponding path program 247 times [2024-05-06 18:24:16,977 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:16,977 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:17,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:17,147 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:17,147 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:17,147 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:17,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:17,324 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:17,346 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:17,424 INFO L85 PathProgramCache]: Analyzing trace with hash 1583704458, now seen corresponding path program 248 times [2024-05-06 18:24:17,424 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:17,424 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:17,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:17,593 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:17,593 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:17,594 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:17,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:17,762 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:17,786 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:18,364 INFO L85 PathProgramCache]: Analyzing trace with hash 1297996003, now seen corresponding path program 249 times [2024-05-06 18:24:18,365 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:18,365 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:18,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:18,537 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:18,537 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:18,537 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:18,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:18,707 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:18,728 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:20,789 INFO L85 PathProgramCache]: Analyzing trace with hash -705627649, now seen corresponding path program 250 times [2024-05-06 18:24:20,790 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:20,790 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:20,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:21,037 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:21,037 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:21,037 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:21,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:21,216 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:21,238 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:22,136 INFO L85 PathProgramCache]: Analyzing trace with hash -399619890, now seen corresponding path program 251 times [2024-05-06 18:24:22,136 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:22,136 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:22,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:22,301 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:22,301 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:22,301 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:22,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:22,466 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:22,488 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:22,590 INFO L85 PathProgramCache]: Analyzing trace with hash -1688349333, now seen corresponding path program 252 times [2024-05-06 18:24:22,591 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:22,591 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:22,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:22,761 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:22,761 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:22,761 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:22,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:22,930 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:22,953 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:23,043 INFO L85 PathProgramCache]: Analyzing trace with hash -799221055, now seen corresponding path program 253 times [2024-05-06 18:24:23,044 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:23,044 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:23,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:23,310 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:23,310 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:23,311 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:23,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:23,504 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:23,525 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:23,612 INFO L85 PathProgramCache]: Analyzing trace with hash 993951790, now seen corresponding path program 254 times [2024-05-06 18:24:23,612 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:23,613 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:23,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:23,840 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:23,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:23,841 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:23,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:24,041 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:24,064 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:24,137 INFO L85 PathProgramCache]: Analyzing trace with hash 993951790, now seen corresponding path program 255 times [2024-05-06 18:24:24,138 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:24,138 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:24,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:24,334 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:24,335 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:24,335 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:24,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:24,528 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:24,551 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:24,747 INFO L85 PathProgramCache]: Analyzing trace with hash 478618335, now seen corresponding path program 256 times [2024-05-06 18:24:24,748 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:24,748 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:24,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:24,948 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:24,948 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:24,948 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:25,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:25,271 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:25,293 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:25,369 INFO L85 PathProgramCache]: Analyzing trace with hash 1952267228, now seen corresponding path program 257 times [2024-05-06 18:24:25,369 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:25,369 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:25,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:25,571 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:25,571 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:25,571 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:25,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:25,771 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:25,792 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:25,857 INFO L85 PathProgramCache]: Analyzing trace with hash 390742658, now seen corresponding path program 258 times [2024-05-06 18:24:25,857 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:25,857 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:25,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:26,064 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:26,064 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:26,064 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:26,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:26,265 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:26,287 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:26,393 INFO L85 PathProgramCache]: Analyzing trace with hash 390742658, now seen corresponding path program 259 times [2024-05-06 18:24:26,393 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:26,393 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:26,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:26,566 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:26,566 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:26,566 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:26,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:26,857 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:26,878 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:26,949 INFO L85 PathProgramCache]: Analyzing trace with hash 1841562750, now seen corresponding path program 260 times [2024-05-06 18:24:26,949 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:26,949 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:26,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:27,125 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:27,126 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:27,126 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:27,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:27,305 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:27,327 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:27,404 INFO L85 PathProgramCache]: Analyzing trace with hash 1253871127, now seen corresponding path program 261 times [2024-05-06 18:24:27,404 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:27,404 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:27,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:27,584 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:27,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:27,584 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:27,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:27,769 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:27,791 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:27,878 INFO L85 PathProgramCache]: Analyzing trace with hash 215299999, now seen corresponding path program 262 times [2024-05-06 18:24:27,878 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:27,878 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:27,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:28,062 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:28,063 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:28,063 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:28,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:28,359 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:28,380 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:28,446 INFO L85 PathProgramCache]: Analyzing trace with hash -1915633896, now seen corresponding path program 263 times [2024-05-06 18:24:28,446 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:28,446 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:28,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:28,627 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:28,628 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:28,628 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:28,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:28,811 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:28,833 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:28,912 INFO L85 PathProgramCache]: Analyzing trace with hash 744892096, now seen corresponding path program 264 times [2024-05-06 18:24:28,912 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:28,912 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:28,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:29,093 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:29,093 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:29,093 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:29,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:29,276 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:29,297 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:29,363 INFO L85 PathProgramCache]: Analyzing trace with hash 1616819225, now seen corresponding path program 265 times [2024-05-06 18:24:29,363 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:29,363 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:29,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:29,546 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:29,546 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:29,547 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:29,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:29,832 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:29,853 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:31,924 INFO L85 PathProgramCache]: Analyzing trace with hash -1418210861, now seen corresponding path program 266 times [2024-05-06 18:24:31,925 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:31,925 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:31,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:32,107 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:32,108 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:32,108 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:32,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:32,289 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:32,310 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:32,489 INFO L85 PathProgramCache]: Analyzing trace with hash -1014863012, now seen corresponding path program 267 times [2024-05-06 18:24:32,489 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:32,489 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:32,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:32,674 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:32,675 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:32,675 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:32,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:32,859 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:32,875 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:34,918 INFO L85 PathProgramCache]: Analyzing trace with hash -1014863012, now seen corresponding path program 268 times [2024-05-06 18:24:34,919 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:34,919 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:34,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:35,105 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:35,105 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:35,105 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:35,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:35,415 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:35,443 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:35,547 INFO L85 PathProgramCache]: Analyzing trace with hash -325754261, now seen corresponding path program 269 times [2024-05-06 18:24:35,548 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:35,548 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:35,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:35,754 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:35,754 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:35,755 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:35,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:35,966 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:35,993 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:36,082 INFO L85 PathProgramCache]: Analyzing trace with hash -1508446744, now seen corresponding path program 270 times [2024-05-06 18:24:36,083 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:36,083 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:36,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:36,296 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:36,297 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:36,297 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:36,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:36,519 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:36,564 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:36,638 INFO L85 PathProgramCache]: Analyzing trace with hash 482791948, now seen corresponding path program 271 times [2024-05-06 18:24:36,638 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:36,638 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:36,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:36,844 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:36,844 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:36,844 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:36,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:37,164 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:37,184 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:37,268 INFO L85 PathProgramCache]: Analyzing trace with hash 2081649257, now seen corresponding path program 272 times [2024-05-06 18:24:37,268 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:37,268 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:37,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:37,475 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:37,476 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:37,476 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:37,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:37,687 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:37,706 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:37,771 INFO L85 PathProgramCache]: Analyzing trace with hash 106618285, now seen corresponding path program 273 times [2024-05-06 18:24:37,771 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:37,772 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:37,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:37,976 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:37,976 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:37,976 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:38,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:38,180 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:38,198 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:38,524 INFO L85 PathProgramCache]: Analyzing trace with hash -989799702, now seen corresponding path program 274 times [2024-05-06 18:24:38,524 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:38,524 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:38,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:38,859 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:38,860 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:38,860 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:38,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:39,040 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:24:39,059 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:39,149 INFO L85 PathProgramCache]: Analyzing trace with hash -619018944, now seen corresponding path program 275 times [2024-05-06 18:24:39,150 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:39,150 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:39,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:40,233 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:24:40,234 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:40,234 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:40,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:40,560 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:24:40,580 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:40,690 INFO L85 PathProgramCache]: Analyzing trace with hash -2009717331, now seen corresponding path program 276 times [2024-05-06 18:24:40,690 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:40,690 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:40,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:41,122 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:24:41,122 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:41,122 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:41,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:41,460 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:24:41,482 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:43,530 INFO L85 PathProgramCache]: Analyzing trace with hash -2009717331, now seen corresponding path program 277 times [2024-05-06 18:24:43,530 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:43,530 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:43,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:43,934 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:24:43,934 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:43,934 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:43,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:44,263 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:24:44,284 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:46,332 INFO L85 PathProgramCache]: Analyzing trace with hash 1396951708, now seen corresponding path program 278 times [2024-05-06 18:24:46,332 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:46,332 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:46,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:46,659 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 1 proven. 12 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:24:46,659 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:46,659 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:46,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:47,089 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 1 proven. 12 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:24:47,110 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:47,189 INFO L85 PathProgramCache]: Analyzing trace with hash 355830728, now seen corresponding path program 279 times [2024-05-06 18:24:47,189 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:47,189 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:47,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:47,565 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 1 proven. 12 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:24:47,566 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:47,566 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:47,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:47,952 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 1 proven. 12 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:24:47,973 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:48,065 INFO L85 PathProgramCache]: Analyzing trace with hash -1854148579, now seen corresponding path program 280 times [2024-05-06 18:24:48,065 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:48,065 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:48,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:48,537 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 1 proven. 12 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:24:48,537 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:48,537 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:48,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:48,931 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 1 proven. 12 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:24:48,951 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:49,030 INFO L85 PathProgramCache]: Analyzing trace with hash -1644030359, now seen corresponding path program 281 times [2024-05-06 18:24:49,031 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:49,031 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:49,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:49,407 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 1 proven. 12 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:24:49,407 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:49,407 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:49,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:49,880 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 1 proven. 12 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:24:49,898 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:49,951 INFO L85 PathProgramCache]: Analyzing trace with hash 574667166, now seen corresponding path program 282 times [2024-05-06 18:24:49,951 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:49,952 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:49,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:50,339 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 1 proven. 12 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:24:50,340 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:50,340 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:50,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:50,666 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 1 proven. 12 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:24:50,696 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:51,605 INFO L85 PathProgramCache]: Analyzing trace with hash 634813706, now seen corresponding path program 283 times [2024-05-06 18:24:51,606 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:51,606 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:51,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:52,018 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 1 proven. 12 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:24:52,018 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:52,018 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:52,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:52,350 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 1 proven. 12 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:24:52,371 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:52,470 INFO L85 PathProgramCache]: Analyzing trace with hash 1179721886, now seen corresponding path program 284 times [2024-05-06 18:24:52,471 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:52,471 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:52,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:52,884 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 1 proven. 12 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:24:52,884 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:52,884 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:52,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:53,212 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 1 proven. 12 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:24:53,228 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:53,286 INFO L85 PathProgramCache]: Analyzing trace with hash -2083326467, now seen corresponding path program 285 times [2024-05-06 18:24:53,286 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:53,286 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:53,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:53,835 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 1 proven. 12 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:24:53,835 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:53,835 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:53,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:54,324 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 1 proven. 12 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:24:54,346 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:56,404 INFO L85 PathProgramCache]: Analyzing trace with hash -158610303, now seen corresponding path program 286 times [2024-05-06 18:24:56,405 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:56,405 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:56,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:56,819 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 1 proven. 12 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:24:56,819 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:56,819 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:56,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:57,343 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 1 proven. 12 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:24:57,383 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:57,531 INFO L85 PathProgramCache]: Analyzing trace with hash -158610303, now seen corresponding path program 287 times [2024-05-06 18:24:57,532 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:57,532 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:57,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:57,902 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 1 proven. 12 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:24:57,902 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:57,902 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:57,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:58,261 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 1 proven. 12 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:24:58,278 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:24:58,369 INFO L85 PathProgramCache]: Analyzing trace with hash 1004435852, now seen corresponding path program 288 times [2024-05-06 18:24:58,369 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:58,369 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:58,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:58,808 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 2 proven. 12 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:24:58,809 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:24:58,809 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:24:58,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:24:59,176 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 2 proven. 12 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:24:59,202 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:25:01,262 INFO L85 PathProgramCache]: Analyzing trace with hash 1072741086, now seen corresponding path program 289 times [2024-05-06 18:25:01,263 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:01,263 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:01,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:25:01,804 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 1 proven. 13 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:25:01,804 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:01,804 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:01,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:25:02,189 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 1 proven. 13 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:25:02,211 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:25:02,277 INFO L85 PathProgramCache]: Analyzing trace with hash -1104763953, now seen corresponding path program 290 times [2024-05-06 18:25:02,277 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:02,278 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:02,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:25:02,749 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 1 proven. 13 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:25:02,750 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:02,750 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:02,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:25:03,197 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 1 proven. 13 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:25:03,251 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:25:03,317 INFO L85 PathProgramCache]: Analyzing trace with hash -1104763953, now seen corresponding path program 291 times [2024-05-06 18:25:03,317 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:03,317 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:03,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:25:03,829 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 1 proven. 13 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:25:03,829 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:03,830 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:03,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:25:04,372 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 1 proven. 13 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:25:04,394 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:25:06,467 INFO L85 PathProgramCache]: Analyzing trace with hash -294764083, now seen corresponding path program 292 times [2024-05-06 18:25:06,467 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:06,468 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:06,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:25:06,862 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 2 proven. 13 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:25:06,863 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:06,863 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:06,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:25:07,351 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 2 proven. 13 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:25:07,371 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:25:07,439 INFO L85 PathProgramCache]: Analyzing trace with hash -1513163506, now seen corresponding path program 22 times [2024-05-06 18:25:07,439 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:07,440 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:07,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:25:07,847 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 2 proven. 13 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:25:07,847 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:07,847 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:07,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:25:08,323 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 2 proven. 13 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:25:08,344 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:25:10,409 INFO L85 PathProgramCache]: Analyzing trace with hash 336572159, now seen corresponding path program 6 times [2024-05-06 18:25:10,410 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:10,410 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:10,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:25:10,811 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 2 proven. 13 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:25:10,811 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:10,812 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:10,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:25:11,308 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 2 proven. 13 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:25:11,330 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:25:13,401 INFO L85 PathProgramCache]: Analyzing trace with hash 2092090532, now seen corresponding path program 7 times [2024-05-06 18:25:13,401 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:13,401 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:13,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:25:14,627 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 1 proven. 15 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:25:14,628 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:14,628 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:14,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:25:15,221 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 1 proven. 15 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:25:15,243 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:25:15,315 INFO L85 PathProgramCache]: Analyzing trace with hash 144642645, now seen corresponding path program 8 times [2024-05-06 18:25:15,316 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:15,316 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:15,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:25:16,374 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 3 proven. 14 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:25:16,375 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:16,375 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:16,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:25:17,086 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 3 proven. 14 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:25:17,109 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:25:17,194 INFO L85 PathProgramCache]: Analyzing trace with hash 188955433, now seen corresponding path program 9 times [2024-05-06 18:25:17,194 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:17,195 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:17,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:25:17,825 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 3 proven. 14 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:25:17,825 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:17,825 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:17,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:25:18,530 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 3 proven. 14 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:25:18,545 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 972 treesize of output 924 [2024-05-06 18:25:18,610 INFO L85 PathProgramCache]: Analyzing trace with hash 1562651863, now seen corresponding path program 10 times [2024-05-06 18:25:18,610 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:18,611 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:18,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:25:18,821 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 33 trivial. 0 not checked. [2024-05-06 18:25:18,821 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:18,821 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:18,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:25:19,033 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 33 trivial. 0 not checked. [2024-05-06 18:25:19,051 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:25:21,096 INFO L85 PathProgramCache]: Analyzing trace with hash -158553800, now seen corresponding path program 2 times [2024-05-06 18:25:21,096 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:21,096 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:21,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:25:21,732 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 2 proven. 15 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:25:21,732 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:21,733 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:21,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:25:22,364 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 2 proven. 15 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-05-06 18:25:22,377 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2024-05-06 18:25:22,405 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Ended with exit code 0 [2024-05-06 18:25:22,592 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable790,SelfDestructingSolverStorable670,SelfDestructingSolverStorable791,SelfDestructingSolverStorable550,SelfDestructingSolverStorable671,SelfDestructingSolverStorable792,SelfDestructingSolverStorable548,SelfDestructingSolverStorable669,SelfDestructingSolverStorable549,SelfDestructingSolverStorable544,SelfDestructingSolverStorable665,SelfDestructingSolverStorable786,SelfDestructingSolverStorable545,SelfDestructingSolverStorable666,SelfDestructingSolverStorable787,SelfDestructingSolverStorable546,SelfDestructingSolverStorable667,SelfDestructingSolverStorable788,SelfDestructingSolverStorable547,SelfDestructingSolverStorable668,SelfDestructingSolverStorable789,SelfDestructingSolverStorable540,SelfDestructingSolverStorable661,SelfDestructingSolverStorable782,SelfDestructingSolverStorable541,SelfDestructingSolverStorable662,SelfDestructingSolverStorable783,SelfDestructingSolverStorable542,SelfDestructingSolverStorable663,SelfDestructingSolverStorable784,SelfDestructingSolverStorable543,SelfDestructingSolverStorable664,SelfDestructingSolverStorable785,SelfDestructingSolverStorable780,SelfDestructingSolverStorable660,SelfDestructingSolverStorable781,SelfDestructingSolverStorable537,SelfDestructingSolverStorable658,SelfDestructingSolverStorable779,SelfDestructingSolverStorable538,SelfDestructingSolverStorable659,SelfDestructingSolverStorable539,SelfDestructingSolverStorable533,SelfDestructingSolverStorable654,SelfDestructingSolverStorable775,SelfDestructingSolverStorable896,SelfDestructingSolverStorable534,SelfDestructingSolverStorable655,SelfDestructingSolverStorable776,SelfDestructingSolverStorable897,SelfDestructingSolverStorable535,SelfDestructingSolverStorable656,SelfDestructingSolverStorable777,SelfDestructingSolverStorable898,SelfDestructingSolverStorable536,SelfDestructingSolverStorable657,SelfDestructingSolverStorable778,SelfDestructingSolverStorable899,SelfDestructingSolverStorable650,SelfDestructingSolverStorable771,SelfDestructingSolverStorable892,SelfDestructingSolverStorable530,SelfDestructingSolverStorable651,SelfDestructingSolverStorable772,SelfDestructingSolverStorable893,SelfDestructingSolverStorable531,SelfDestructingSolverStorable652,SelfDestructingSolverStorable773,SelfDestructingSolverStorable894,SelfDestructingSolverStorable532,SelfDestructingSolverStorable653,SelfDestructingSolverStorable774,SelfDestructingSolverStorable895,SelfDestructingSolverStorable690,SelfDestructingSolverStorable570,SelfDestructingSolverStorable691,SelfDestructingSolverStorable571,SelfDestructingSolverStorable692,SelfDestructingSolverStorable572,SelfDestructingSolverStorable693,SelfDestructingSolverStorable566,SelfDestructingSolverStorable687,SelfDestructingSolverStorable567,SelfDestructingSolverStorable688,SelfDestructingSolverStorable568,SelfDestructingSolverStorable689,SelfDestructingSolverStorable569,SelfDestructingSolverStorable562,SelfDestructingSolverStorable683,SelfDestructingSolverStorable563,SelfDestructingSolverStorable684,SelfDestructingSolverStorable564,SelfDestructingSolverStorable685,SelfDestructingSolverStorable565,SelfDestructingSolverStorable686,SelfDestructingSolverStorable680,SelfDestructingSolverStorable560,SelfDestructingSolverStorable681,SelfDestructingSolverStorable561,SelfDestructingSolverStorable682,SelfDestructingSolverStorable559,SelfDestructingSolverStorable555,SelfDestructingSolverStorable676,SelfDestructingSolverStorable797,SelfDestructingSolverStorable556,SelfDestructingSolverStorable677,SelfDestructingSolverStorable798,SelfDestructingSolverStorable557,SelfDestructingSolverStorable678,SelfDestructingSolverStorable799,SelfDestructingSolverStorable558,SelfDestructingSolverStorable679,SelfDestructingSolverStorable551,SelfDestructingSolverStorable672,SelfDestructingSolverStorable793,SelfDestructingSolverStorable552,SelfDestructingSolverStorable673,SelfDestructingSolverStorable794,SelfDestructingSolverStorable553,SelfDestructingSolverStorable674,SelfDestructingSolverStorable795,SelfDestructingSolverStorable554,SelfDestructingSolverStorable675,SelfDestructingSolverStorable796,SelfDestructingSolverStorable508,SelfDestructingSolverStorable629,SelfDestructingSolverStorable509,SelfDestructingSolverStorable504,SelfDestructingSolverStorable625,SelfDestructingSolverStorable746,SelfDestructingSolverStorable867,SelfDestructingSolverStorable505,SelfDestructingSolverStorable626,SelfDestructingSolverStorable747,SelfDestructingSolverStorable868,SelfDestructingSolverStorable506,SelfDestructingSolverStorable627,SelfDestructingSolverStorable748,SelfDestructingSolverStorable869,SelfDestructingSolverStorable507,SelfDestructingSolverStorable628,SelfDestructingSolverStorable749,SelfDestructingSolverStorable500,SelfDestructingSolverStorable621,SelfDestructingSolverStorable742,SelfDestructingSolverStorable863,SelfDestructingSolverStorable501,SelfDestructingSolverStorable622,SelfDestructingSolverStorable743,SelfDestructingSolverStorable864,SelfDestructingSolverStorable502,SelfDestructingSolverStorable623,SelfDestructingSolverStorable744,SelfDestructingSolverStorable865,SelfDestructingSolverStorable503,SelfDestructingSolverStorable624,SelfDestructingSolverStorable745,SelfDestructingSolverStorable866,SelfDestructingSolverStorable860,SelfDestructingSolverStorable740,SelfDestructingSolverStorable861,SelfDestructingSolverStorable620,SelfDestructingSolverStorable741,SelfDestructingSolverStorable862,SelfDestructingSolverStorable618,SelfDestructingSolverStorable739,SelfDestructingSolverStorable619,SelfDestructingSolverStorable614,SelfDestructingSolverStorable735,SelfDestructingSolverStorable856,SelfDestructingSolverStorable615,SelfDestructingSolverStorable736,SelfDestructingSolverStorable857,SelfDestructingSolverStorable616,SelfDestructingSolverStorable737,SelfDestructingSolverStorable858,SelfDestructingSolverStorable617,SelfDestructingSolverStorable738,SelfDestructingSolverStorable859,SelfDestructingSolverStorable610,SelfDestructingSolverStorable731,SelfDestructingSolverStorable852,SelfDestructingSolverStorable611,SelfDestructingSolverStorable732,SelfDestructingSolverStorable853,SelfDestructingSolverStorable612,SelfDestructingSolverStorable733,SelfDestructingSolverStorable854,SelfDestructingSolverStorable613,SelfDestructingSolverStorable734,SelfDestructingSolverStorable855,SelfDestructingSolverStorable850,SelfDestructingSolverStorable730,SelfDestructingSolverStorable851,SelfDestructingSolverStorable890,SelfDestructingSolverStorable770,SelfDestructingSolverStorable891,SelfDestructingSolverStorable526,SelfDestructingSolverStorable647,SelfDestructingSolverStorable768,SelfDestructingSolverStorable889,SelfDestructingSolverStorable527,SelfDestructingSolverStorable648,SelfDestructingSolverStorable769,SelfDestructingSolverStorable528,SelfDestructingSolverStorable649,SelfDestructingSolverStorable529,SelfDestructingSolverStorable522,SelfDestructingSolverStorable643,SelfDestructingSolverStorable764,SelfDestructingSolverStorable885,SelfDestructingSolverStorable523,SelfDestructingSolverStorable644,SelfDestructingSolverStorable765,SelfDestructingSolverStorable886,SelfDestructingSolverStorable524,SelfDestructingSolverStorable645,SelfDestructingSolverStorable766,SelfDestructingSolverStorable887,SelfDestructingSolverStorable525,SelfDestructingSolverStorable646,SelfDestructingSolverStorable767,SelfDestructingSolverStorable888,SelfDestructingSolverStorable760,SelfDestructingSolverStorable881,SelfDestructingSolverStorable640,SelfDestructingSolverStorable761,SelfDestructingSolverStorable882,SelfDestructingSolverStorable520,SelfDestructingSolverStorable641,SelfDestructingSolverStorable762,SelfDestructingSolverStorable883,SelfDestructingSolverStorable521,SelfDestructingSolverStorable642,SelfDestructingSolverStorable763,SelfDestructingSolverStorable884,SelfDestructingSolverStorable880,SelfDestructingSolverStorable519,SelfDestructingSolverStorable515,SelfDestructingSolverStorable636,SelfDestructingSolverStorable757,SelfDestructingSolverStorable878,SelfDestructingSolverStorable516,SelfDestructingSolverStorable637,SelfDestructingSolverStorable758,SelfDestructingSolverStorable879,SelfDestructingSolverStorable517,SelfDestructingSolverStorable638,SelfDestructingSolverStorable759,SelfDestructingSolverStorable518,SelfDestructingSolverStorable639,SelfDestructingSolverStorable511,SelfDestructingSolverStorable632,SelfDestructingSolverStorable753,SelfDestructingSolverStorable874,SelfDestructingSolverStorable512,SelfDestructingSolverStorable633,SelfDestructingSolverStorable754,SelfDestructingSolverStorable875,SelfDestructingSolverStorable513,SelfDestructingSolverStorable634,SelfDestructingSolverStorable755,SelfDestructingSolverStorable876,SelfDestructingSolverStorable514,SelfDestructingSolverStorable635,SelfDestructingSolverStorable756,SelfDestructingSolverStorable877,SelfDestructingSolverStorable870,SelfDestructingSolverStorable750,SelfDestructingSolverStorable871,SelfDestructingSolverStorable630,SelfDestructingSolverStorable751,SelfDestructingSolverStorable872,SelfDestructingSolverStorable510,SelfDestructingSolverStorable631,SelfDestructingSolverStorable752,SelfDestructingSolverStorable873,SelfDestructingSolverStorable706,SelfDestructingSolverStorable827,SelfDestructingSolverStorable707,SelfDestructingSolverStorable828,SelfDestructingSolverStorable708,SelfDestructingSolverStorable829,SelfDestructingSolverStorable709,SelfDestructingSolverStorable702,SelfDestructingSolverStorable823,SelfDestructingSolverStorable703,SelfDestructingSolverStorable824,SelfDestructingSolverStorable704,SelfDestructingSolverStorable825,SelfDestructingSolverStorable705,SelfDestructingSolverStorable826,SelfDestructingSolverStorable820,SelfDestructingSolverStorable700,SelfDestructingSolverStorable821,SelfDestructingSolverStorable701,SelfDestructingSolverStorable822,SelfDestructingSolverStorable816,SelfDestructingSolverStorable817,SelfDestructingSolverStorable818,SelfDestructingSolverStorable819,SelfDestructingSolverStorable812,SelfDestructingSolverStorable813,SelfDestructingSolverStorable814,SelfDestructingSolverStorable815,SelfDestructingSolverStorable810,SelfDestructingSolverStorable811,SelfDestructingSolverStorable607,SelfDestructingSolverStorable728,SelfDestructingSolverStorable849,SelfDestructingSolverStorable608,SelfDestructingSolverStorable729,SelfDestructingSolverStorable609,SelfDestructingSolverStorable603,SelfDestructingSolverStorable724,SelfDestructingSolverStorable845,SelfDestructingSolverStorable604,SelfDestructingSolverStorable725,SelfDestructingSolverStorable846,SelfDestructingSolverStorable605,SelfDestructingSolverStorable726,SelfDestructingSolverStorable847,SelfDestructingSolverStorable606,SelfDestructingSolverStorable727,SelfDestructingSolverStorable848,SelfDestructingSolverStorable720,SelfDestructingSolverStorable841,SelfDestructingSolverStorable600,SelfDestructingSolverStorable721,SelfDestructingSolverStorable842,SelfDestructingSolverStorable601,SelfDestructingSolverStorable722,SelfDestructingSolverStorable843,SelfDestructingSolverStorable602,SelfDestructingSolverStorable723,SelfDestructingSolverStorable844,SelfDestructingSolverStorable840,3 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable717,SelfDestructingSolverStorable838,SelfDestructingSolverStorable718,SelfDestructingSolverStorable839,SelfDestructingSolverStorable719,SelfDestructingSolverStorable713,SelfDestructingSolverStorable834,SelfDestructingSolverStorable714,SelfDestructingSolverStorable835,SelfDestructingSolverStorable715,SelfDestructingSolverStorable836,SelfDestructingSolverStorable716,SelfDestructingSolverStorable837,SelfDestructingSolverStorable830,SelfDestructingSolverStorable710,SelfDestructingSolverStorable831,SelfDestructingSolverStorable711,SelfDestructingSolverStorable832,SelfDestructingSolverStorable712,SelfDestructingSolverStorable833,SelfDestructingSolverStorable908,SelfDestructingSolverStorable909,SelfDestructingSolverStorable904,SelfDestructingSolverStorable905,SelfDestructingSolverStorable906,SelfDestructingSolverStorable907,SelfDestructingSolverStorable900,SelfDestructingSolverStorable901,SelfDestructingSolverStorable902,SelfDestructingSolverStorable903,SelfDestructingSolverStorable809,SelfDestructingSolverStorable805,SelfDestructingSolverStorable806,SelfDestructingSolverStorable807,SelfDestructingSolverStorable808,SelfDestructingSolverStorable801,SelfDestructingSolverStorable802,SelfDestructingSolverStorable803,SelfDestructingSolverStorable804,SelfDestructingSolverStorable800,SelfDestructingSolverStorable915,SelfDestructingSolverStorable916,SelfDestructingSolverStorable917,SelfDestructingSolverStorable911,SelfDestructingSolverStorable912,SelfDestructingSolverStorable913,SelfDestructingSolverStorable914,SelfDestructingSolverStorable910,SelfDestructingSolverStorable496,SelfDestructingSolverStorable497,SelfDestructingSolverStorable498,SelfDestructingSolverStorable499,SelfDestructingSolverStorable470,SelfDestructingSolverStorable591,SelfDestructingSolverStorable471,SelfDestructingSolverStorable592,SelfDestructingSolverStorable472,SelfDestructingSolverStorable593,SelfDestructingSolverStorable473,SelfDestructingSolverStorable594,SelfDestructingSolverStorable590,SelfDestructingSolverStorable467,SelfDestructingSolverStorable588,SelfDestructingSolverStorable468,SelfDestructingSolverStorable589,SelfDestructingSolverStorable469,SelfDestructingSolverStorable463,SelfDestructingSolverStorable584,SelfDestructingSolverStorable464,SelfDestructingSolverStorable585,SelfDestructingSolverStorable465,SelfDestructingSolverStorable586,SelfDestructingSolverStorable466,SelfDestructingSolverStorable587,SelfDestructingSolverStorable580,SelfDestructingSolverStorable581,SelfDestructingSolverStorable582,SelfDestructingSolverStorable462,SelfDestructingSolverStorable583,SelfDestructingSolverStorable577,SelfDestructingSolverStorable698,SelfDestructingSolverStorable578,SelfDestructingSolverStorable699,SelfDestructingSolverStorable579,SelfDestructingSolverStorable573,SelfDestructingSolverStorable694,SelfDestructingSolverStorable574,SelfDestructingSolverStorable695,SelfDestructingSolverStorable575,SelfDestructingSolverStorable696,SelfDestructingSolverStorable576,SelfDestructingSolverStorable697,SelfDestructingSolverStorable492,SelfDestructingSolverStorable493,SelfDestructingSolverStorable494,SelfDestructingSolverStorable495,SelfDestructingSolverStorable490,SelfDestructingSolverStorable491,SelfDestructingSolverStorable489,SelfDestructingSolverStorable485,SelfDestructingSolverStorable486,SelfDestructingSolverStorable487,SelfDestructingSolverStorable488,SelfDestructingSolverStorable481,SelfDestructingSolverStorable482,SelfDestructingSolverStorable483,SelfDestructingSolverStorable484,SelfDestructingSolverStorable480,SelfDestructingSolverStorable478,SelfDestructingSolverStorable599,SelfDestructingSolverStorable479,SelfDestructingSolverStorable474,SelfDestructingSolverStorable595,SelfDestructingSolverStorable475,SelfDestructingSolverStorable596,SelfDestructingSolverStorable476,SelfDestructingSolverStorable597,SelfDestructingSolverStorable477,SelfDestructingSolverStorable598 [2024-05-06 18:25:22,594 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 1 more)] === [2024-05-06 18:25:22,594 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 18:25:22,594 INFO L85 PathProgramCache]: Analyzing trace with hash -1964987494, now seen corresponding path program 2 times [2024-05-06 18:25:22,595 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 18:25:22,595 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1866846490] [2024-05-06 18:25:22,595 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:22,595 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:22,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:25:23,966 INFO L134 CoverageAnalysis]: Checked inductivity of 422 backedges. 174 proven. 220 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 18:25:23,967 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 18:25:23,967 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1866846490] [2024-05-06 18:25:23,967 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1866846490] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 18:25:23,967 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [97918047] [2024-05-06 18:25:23,967 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-05-06 18:25:23,967 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 18:25:23,967 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 18:25:23,980 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 18:25:24,024 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2024-05-06 18:25:26,145 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-05-06 18:25:26,146 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2024-05-06 18:25:26,149 INFO L262 TraceCheckSpWp]: Trace formula consists of 826 conjuncts, 14 conjunts are in the unsatisfiable core [2024-05-06 18:25:26,153 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 18:25:26,738 INFO L134 CoverageAnalysis]: Checked inductivity of 422 backedges. 129 proven. 19 refuted. 0 times theorem prover too weak. 274 trivial. 0 not checked. [2024-05-06 18:25:26,738 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-06 18:25:27,400 INFO L134 CoverageAnalysis]: Checked inductivity of 422 backedges. 139 proven. 9 refuted. 0 times theorem prover too weak. 274 trivial. 0 not checked. [2024-05-06 18:25:27,400 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [97918047] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-06 18:25:27,401 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-06 18:25:27,401 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [41, 15, 15] total 63 [2024-05-06 18:25:27,401 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [175657237] [2024-05-06 18:25:27,401 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-06 18:25:27,402 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 63 states [2024-05-06 18:25:27,402 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 18:25:27,403 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 63 interpolants. [2024-05-06 18:25:27,404 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=316, Invalid=3590, Unknown=0, NotChecked=0, Total=3906 [2024-05-06 18:25:27,404 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:25:27,404 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 18:25:27,405 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 63 states, 63 states have (on average 8.777777777777779) internal successors, (553), 63 states have internal predecessors, (553), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 18:25:27,405 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 14 states. [2024-05-06 18:25:27,405 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 18:25:28,509 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:25:28,555 INFO L85 PathProgramCache]: Analyzing trace with hash 1215537109, now seen corresponding path program 5 times [2024-05-06 18:25:28,555 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:28,555 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:28,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:25:29,452 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 2 proven. 24 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:25:29,452 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:29,452 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:29,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:25:29,699 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 2 proven. 24 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:25:29,771 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:25:29,853 INFO L85 PathProgramCache]: Analyzing trace with hash 1967623721, now seen corresponding path program 21 times [2024-05-06 18:25:29,854 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:29,854 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:29,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:29,914 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:25:29,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:30,001 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:25:32,052 INFO L85 PathProgramCache]: Analyzing trace with hash 866793926, now seen corresponding path program 22 times [2024-05-06 18:25:32,052 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:32,052 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:32,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:32,099 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:25:32,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:32,174 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 972 treesize of output 924 [2024-05-06 18:25:32,873 INFO L85 PathProgramCache]: Analyzing trace with hash 1100808651, now seen corresponding path program 23 times [2024-05-06 18:25:32,873 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:32,873 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:32,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:32,923 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:25:32,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:33,003 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:25:33,064 INFO L85 PathProgramCache]: Analyzing trace with hash -1669705168, now seen corresponding path program 6 times [2024-05-06 18:25:33,064 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:33,065 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:33,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:33,119 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:25:33,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:33,211 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:25:35,272 INFO L85 PathProgramCache]: Analyzing trace with hash 866774801, now seen corresponding path program 24 times [2024-05-06 18:25:35,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:35,273 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:35,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:35,352 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:25:35,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:35,439 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:25:35,508 INFO L85 PathProgramCache]: Analyzing trace with hash 1967605901, now seen corresponding path program 25 times [2024-05-06 18:25:35,509 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:35,509 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:35,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:35,559 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:25:35,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:35,663 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:25:37,728 INFO L85 PathProgramCache]: Analyzing trace with hash 134032229, now seen corresponding path program 26 times [2024-05-06 18:25:37,728 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:37,728 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:37,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:37,779 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:25:37,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:37,852 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:25:37,935 INFO L85 PathProgramCache]: Analyzing trace with hash -139967463, now seen corresponding path program 27 times [2024-05-06 18:25:37,935 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:37,935 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:37,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:37,987 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:25:38,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:38,054 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 473 treesize of output 449 [2024-05-06 18:25:40,183 INFO L85 PathProgramCache]: Analyzing trace with hash -44023321, now seen corresponding path program 28 times [2024-05-06 18:25:40,183 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:40,183 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:40,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:40,232 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:25:40,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:40,434 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:25:40,505 INFO L85 PathProgramCache]: Analyzing trace with hash -139957758, now seen corresponding path program 29 times [2024-05-06 18:25:40,505 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:40,505 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:40,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:40,612 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:25:40,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:40,792 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:25:40,907 INFO L85 PathProgramCache]: Analyzing trace with hash 134044169, now seen corresponding path program 30 times [2024-05-06 18:25:40,907 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:40,907 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:40,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:40,961 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:25:40,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:41,043 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:25:41,101 INFO L85 PathProgramCache]: Analyzing trace with hash -955319729, now seen corresponding path program 5 times [2024-05-06 18:25:41,102 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:41,102 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:41,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:25:41,390 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 2 proven. 24 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:25:41,391 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:41,391 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:41,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:25:41,703 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 2 proven. 24 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:25:41,727 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:25:41,856 INFO L85 PathProgramCache]: Analyzing trace with hash 488728099, now seen corresponding path program 21 times [2024-05-06 18:25:41,857 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:41,857 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:41,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:41,935 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:25:41,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:42,066 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:25:42,190 INFO L85 PathProgramCache]: Analyzing trace with hash -2029297396, now seen corresponding path program 22 times [2024-05-06 18:25:42,191 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:42,191 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:42,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:42,266 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:25:42,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:42,394 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 1930 treesize of output 1834 [2024-05-06 18:25:44,140 INFO L85 PathProgramCache]: Analyzing trace with hash 1516290885, now seen corresponding path program 23 times [2024-05-06 18:25:44,140 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:44,140 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:44,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:44,344 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:25:44,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:44,410 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:25:46,456 INFO L85 PathProgramCache]: Analyzing trace with hash 454405290, now seen corresponding path program 6 times [2024-05-06 18:25:46,456 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:46,456 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:46,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:46,684 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:25:46,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:46,829 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:25:46,906 INFO L85 PathProgramCache]: Analyzing trace with hash -2029316521, now seen corresponding path program 24 times [2024-05-06 18:25:46,906 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:46,906 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:46,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:46,953 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:25:46,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:47,016 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:25:47,726 INFO L85 PathProgramCache]: Analyzing trace with hash 488710279, now seen corresponding path program 25 times [2024-05-06 18:25:47,726 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:47,727 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:47,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:47,812 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:25:47,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:47,892 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:25:48,006 INFO L85 PathProgramCache]: Analyzing trace with hash 1388548651, now seen corresponding path program 26 times [2024-05-06 18:25:48,006 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:48,006 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:48,048 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:48,048 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:25:48,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:48,116 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:25:48,252 INFO L85 PathProgramCache]: Analyzing trace with hash 95335955, now seen corresponding path program 27 times [2024-05-06 18:25:48,252 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:48,252 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:48,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:48,332 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:25:48,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:48,395 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 972 treesize of output 924 [2024-05-06 18:25:49,326 INFO L85 PathProgramCache]: Analyzing trace with hash -1339551955, now seen corresponding path program 28 times [2024-05-06 18:25:49,326 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:49,327 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:49,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:49,376 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:25:49,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:49,440 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:25:49,518 INFO L85 PathProgramCache]: Analyzing trace with hash 95345660, now seen corresponding path program 29 times [2024-05-06 18:25:49,518 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:49,518 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:49,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:49,565 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:25:49,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:49,628 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:25:49,712 INFO L85 PathProgramCache]: Analyzing trace with hash 1388560591, now seen corresponding path program 30 times [2024-05-06 18:25:49,712 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:49,712 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:49,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:49,760 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:25:49,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:49,834 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:25:49,897 INFO L85 PathProgramCache]: Analyzing trace with hash 2014476630, now seen corresponding path program 5 times [2024-05-06 18:25:49,898 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:49,898 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:49,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:25:50,076 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 2 proven. 24 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:25:50,076 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:50,077 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:50,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:25:50,249 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 2 proven. 24 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:25:50,271 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:25:50,352 INFO L85 PathProgramCache]: Analyzing trace with hash 563260778, now seen corresponding path program 21 times [2024-05-06 18:25:50,352 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:50,352 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:50,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:50,402 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:25:50,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:50,473 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:25:52,535 INFO L85 PathProgramCache]: Analyzing trace with hash 281215653, now seen corresponding path program 22 times [2024-05-06 18:25:52,536 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:52,536 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:52,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:52,582 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:25:52,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:52,658 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 473 treesize of output 449 [2024-05-06 18:25:54,006 INFO L85 PathProgramCache]: Analyzing trace with hash 127751372, now seen corresponding path program 23 times [2024-05-06 18:25:54,007 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:54,007 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:54,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:54,056 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:25:54,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:54,161 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:25:54,241 INFO L85 PathProgramCache]: Analyzing trace with hash -870765647, now seen corresponding path program 6 times [2024-05-06 18:25:54,242 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:54,242 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:54,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:54,298 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:25:54,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:54,373 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:25:54,488 INFO L85 PathProgramCache]: Analyzing trace with hash 281196528, now seen corresponding path program 24 times [2024-05-06 18:25:54,488 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:54,489 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:54,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:54,620 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:25:54,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:54,688 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:25:54,774 INFO L85 PathProgramCache]: Analyzing trace with hash 563242958, now seen corresponding path program 25 times [2024-05-06 18:25:54,775 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:54,775 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:54,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:54,824 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:25:54,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:54,897 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:25:54,980 INFO L85 PathProgramCache]: Analyzing trace with hash -372068604, now seen corresponding path program 26 times [2024-05-06 18:25:54,981 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:54,981 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:55,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:55,026 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:25:55,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:55,089 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:25:55,145 INFO L85 PathProgramCache]: Analyzing trace with hash 1350775898, now seen corresponding path program 27 times [2024-05-06 18:25:55,145 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:55,145 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:55,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:55,190 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:25:55,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:55,253 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 473 treesize of output 449 [2024-05-06 18:25:55,464 INFO L85 PathProgramCache]: Analyzing trace with hash -1075619386, now seen corresponding path program 28 times [2024-05-06 18:25:55,465 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:55,465 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:55,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:55,510 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:25:55,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:55,576 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:25:57,639 INFO L85 PathProgramCache]: Analyzing trace with hash 1350785603, now seen corresponding path program 29 times [2024-05-06 18:25:57,639 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:57,640 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:57,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:57,685 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:25:57,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:57,749 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:25:59,807 INFO L85 PathProgramCache]: Analyzing trace with hash -372056664, now seen corresponding path program 30 times [2024-05-06 18:25:59,807 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:25:59,807 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:25:59,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:59,851 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:25:59,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:25:59,915 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:26:01,957 INFO L85 PathProgramCache]: Analyzing trace with hash 1409322544, now seen corresponding path program 5 times [2024-05-06 18:26:01,957 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:01,957 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:01,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:02,137 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 2 proven. 24 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:26:02,137 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:02,137 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:02,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:02,312 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 2 proven. 24 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:26:02,335 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:26:04,389 INFO L85 PathProgramCache]: Analyzing trace with hash 1380640708, now seen corresponding path program 21 times [2024-05-06 18:26:04,390 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:04,390 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:04,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:04,436 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:26:04,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:04,499 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:26:04,694 INFO L85 PathProgramCache]: Analyzing trace with hash -149810293, now seen corresponding path program 22 times [2024-05-06 18:26:04,694 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:04,694 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:04,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:04,739 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:26:04,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:04,798 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 952 treesize of output 904 [2024-05-06 18:26:05,304 INFO L85 PathProgramCache]: Analyzing trace with hash -349151066, now seen corresponding path program 23 times [2024-05-06 18:26:05,304 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:05,304 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:05,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:05,353 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:26:05,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:05,416 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:26:05,527 INFO L85 PathProgramCache]: Analyzing trace with hash -1475919733, now seen corresponding path program 6 times [2024-05-06 18:26:05,527 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:05,527 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:05,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:05,578 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:26:05,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:05,645 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:26:05,723 INFO L85 PathProgramCache]: Analyzing trace with hash -149829418, now seen corresponding path program 24 times [2024-05-06 18:26:05,723 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:05,723 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:05,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:05,772 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:26:05,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:05,839 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:26:06,548 INFO L85 PathProgramCache]: Analyzing trace with hash 1380622888, now seen corresponding path program 25 times [2024-05-06 18:26:06,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:06,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:06,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:06,595 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:26:06,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:06,664 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:26:08,733 INFO L85 PathProgramCache]: Analyzing trace with hash -428832918, now seen corresponding path program 26 times [2024-05-06 18:26:08,733 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:08,733 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:08,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:08,777 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:26:08,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:08,840 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:26:08,916 INFO L85 PathProgramCache]: Analyzing trace with hash -408917836, now seen corresponding path program 27 times [2024-05-06 18:26:08,916 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:08,916 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:08,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:08,961 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:26:08,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:09,021 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 972 treesize of output 924 [2024-05-06 18:26:09,847 INFO L85 PathProgramCache]: Analyzing trace with hash 208449708, now seen corresponding path program 28 times [2024-05-06 18:26:09,847 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:09,847 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:09,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:09,895 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:26:09,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:09,959 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:26:10,029 INFO L85 PathProgramCache]: Analyzing trace with hash -408908131, now seen corresponding path program 29 times [2024-05-06 18:26:10,029 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:10,029 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:10,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:10,077 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:26:10,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:10,144 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:26:10,286 INFO L85 PathProgramCache]: Analyzing trace with hash -428820978, now seen corresponding path program 30 times [2024-05-06 18:26:10,287 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:10,287 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:10,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:10,337 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:26:10,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:10,403 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:26:12,446 INFO L85 PathProgramCache]: Analyzing trace with hash -280983849, now seen corresponding path program 5 times [2024-05-06 18:26:12,446 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:12,446 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:12,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:12,893 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 2 proven. 24 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:26:12,893 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:12,893 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:12,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:13,066 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 2 proven. 24 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:26:13,088 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:26:13,166 INFO L85 PathProgramCache]: Analyzing trace with hash 559415467, now seen corresponding path program 21 times [2024-05-06 18:26:13,166 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:13,166 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:13,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:13,211 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:26:13,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:13,275 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:26:13,349 INFO L85 PathProgramCache]: Analyzing trace with hash 162011012, now seen corresponding path program 22 times [2024-05-06 18:26:13,349 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:13,350 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:13,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:13,410 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:26:13,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:13,497 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 1930 treesize of output 1834 [2024-05-06 18:26:13,755 INFO L85 PathProgramCache]: Analyzing trace with hash 727374797, now seen corresponding path program 23 times [2024-05-06 18:26:13,755 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:13,755 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:13,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:13,804 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:26:13,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:13,870 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:26:14,076 INFO L85 PathProgramCache]: Analyzing trace with hash 1128741170, now seen corresponding path program 6 times [2024-05-06 18:26:14,076 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:14,076 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:14,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:14,128 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:26:14,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:14,208 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:26:16,275 INFO L85 PathProgramCache]: Analyzing trace with hash 161991887, now seen corresponding path program 24 times [2024-05-06 18:26:16,275 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:16,275 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:16,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:16,322 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:26:16,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:16,388 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:26:16,462 INFO L85 PathProgramCache]: Analyzing trace with hash 559397647, now seen corresponding path program 25 times [2024-05-06 18:26:16,462 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:16,462 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:16,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:16,509 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:26:16,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:16,578 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:26:16,659 INFO L85 PathProgramCache]: Analyzing trace with hash 539197091, now seen corresponding path program 26 times [2024-05-06 18:26:16,659 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:16,659 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:16,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:16,705 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:26:16,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:16,797 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:26:18,841 INFO L85 PathProgramCache]: Analyzing trace with hash -464758629, now seen corresponding path program 27 times [2024-05-06 18:26:18,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:18,841 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:19,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:19,074 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:26:19,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:19,127 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 952 treesize of output 904 [2024-05-06 18:26:19,477 INFO L85 PathProgramCache]: Analyzing trace with hash -1522614875, now seen corresponding path program 28 times [2024-05-06 18:26:19,477 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:19,477 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:19,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:19,521 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:26:19,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:19,583 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:26:19,706 INFO L85 PathProgramCache]: Analyzing trace with hash -464748924, now seen corresponding path program 29 times [2024-05-06 18:26:19,706 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:19,707 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:19,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:19,748 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:26:19,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:19,812 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:26:19,881 INFO L85 PathProgramCache]: Analyzing trace with hash 539209031, now seen corresponding path program 30 times [2024-05-06 18:26:19,881 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:19,881 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:19,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:19,925 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:26:19,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:19,988 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:26:22,032 INFO L85 PathProgramCache]: Analyzing trace with hash -1064080751, now seen corresponding path program 13 times [2024-05-06 18:26:22,033 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:22,033 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:22,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:22,078 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:26:22,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:22,138 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:26:22,247 INFO L85 PathProgramCache]: Analyzing trace with hash 1373235806, now seen corresponding path program 14 times [2024-05-06 18:26:22,247 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:22,247 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:22,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:22,290 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:26:22,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:22,347 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 473 treesize of output 449 [2024-05-06 18:26:24,617 INFO L85 PathProgramCache]: Analyzing trace with hash -379362253, now seen corresponding path program 15 times [2024-05-06 18:26:24,617 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:24,617 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:24,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:24,669 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:26:24,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:24,731 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:26:24,800 INFO L85 PathProgramCache]: Analyzing trace with hash 1565460708, now seen corresponding path program 16 times [2024-05-06 18:26:24,800 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:24,800 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:24,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:24,845 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:26:24,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:24,907 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:26:24,977 INFO L85 PathProgramCache]: Analyzing trace with hash 1284642426, now seen corresponding path program 17 times [2024-05-06 18:26:24,977 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:24,977 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:25,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:25,023 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:26:25,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:26:25,084 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 952 treesize of output 904 [2024-05-06 18:26:25,160 INFO L85 PathProgramCache]: Analyzing trace with hash 1169210278, now seen corresponding path program 18 times [2024-05-06 18:26:25,160 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:25,160 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:25,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:25,563 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 99 trivial. 0 not checked. [2024-05-06 18:26:25,563 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:25,563 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:25,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:25,655 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 97 trivial. 0 not checked. [2024-05-06 18:26:25,673 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:26:25,741 INFO L85 PathProgramCache]: Analyzing trace with hash -1530473488, now seen corresponding path program 293 times [2024-05-06 18:26:25,742 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:25,742 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:25,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:26,365 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 1 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:26,366 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:26,366 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:26,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:26,681 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 1 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:26,701 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:26:26,768 INFO L85 PathProgramCache]: Analyzing trace with hash -200037153, now seen corresponding path program 294 times [2024-05-06 18:26:26,768 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:26,769 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:26,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:26,972 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 1 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:26,972 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:26,972 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:27,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:27,180 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 1 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:27,198 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 972 treesize of output 924 [2024-05-06 18:26:29,343 INFO L85 PathProgramCache]: Analyzing trace with hash -1906183726, now seen corresponding path program 295 times [2024-05-06 18:26:29,343 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:29,343 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:29,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:29,597 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 1 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:29,598 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:29,598 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:29,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:29,818 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 1 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:29,837 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:26:31,883 INFO L85 PathProgramCache]: Analyzing trace with hash 1055682487, now seen corresponding path program 23 times [2024-05-06 18:26:31,883 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:31,883 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:31,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:32,351 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:26:32,352 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:32,352 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:32,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:32,566 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:26:32,598 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:26:32,671 INFO L85 PathProgramCache]: Analyzing trace with hash -200070693, now seen corresponding path program 296 times [2024-05-06 18:26:32,671 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:32,671 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:32,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:32,925 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 1 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:32,925 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:32,925 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:32,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:33,126 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 1 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:33,168 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:26:33,242 INFO L85 PathProgramCache]: Analyzing trace with hash -1530506188, now seen corresponding path program 297 times [2024-05-06 18:26:33,242 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:33,242 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:33,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:33,442 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 1 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:33,442 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:33,442 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:33,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:33,641 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 1 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:33,736 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:26:33,798 INFO L85 PathProgramCache]: Analyzing trace with hash 1941250206, now seen corresponding path program 298 times [2024-05-06 18:26:33,798 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:33,798 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:33,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:34,072 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:34,072 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:34,072 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:34,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:34,285 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:34,305 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:26:34,390 INFO L85 PathProgramCache]: Analyzing trace with hash 49214991, now seen corresponding path program 299 times [2024-05-06 18:26:34,391 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:34,391 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:34,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:34,598 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:34,599 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:34,599 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:34,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:34,804 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:34,819 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 473 treesize of output 449 [2024-05-06 18:26:34,992 INFO L85 PathProgramCache]: Analyzing trace with hash 1525665472, now seen corresponding path program 300 times [2024-05-06 18:26:34,992 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:34,992 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:35,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:35,280 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:35,280 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:35,280 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:35,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:35,481 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:35,498 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:26:35,563 INFO L85 PathProgramCache]: Analyzing trace with hash 49239111, now seen corresponding path program 301 times [2024-05-06 18:26:35,563 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:35,563 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:35,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:35,763 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:35,763 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:35,763 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:35,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:35,963 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:35,980 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:26:36,043 INFO L85 PathProgramCache]: Analyzing trace with hash 1941277026, now seen corresponding path program 302 times [2024-05-06 18:26:36,043 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:36,043 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:36,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:36,325 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:36,325 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:36,325 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:36,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:36,523 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:36,539 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:26:38,608 INFO L85 PathProgramCache]: Analyzing trace with hash 1961170185, now seen corresponding path program 24 times [2024-05-06 18:26:38,608 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:38,608 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:38,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:38,787 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 2 proven. 24 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:38,787 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:38,787 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:38,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:38,962 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 2 proven. 24 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:38,983 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:26:39,142 INFO L85 PathProgramCache]: Analyzing trace with hash -996991995, now seen corresponding path program 303 times [2024-05-06 18:26:39,142 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:39,142 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:39,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:39,342 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 1 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:39,342 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:39,342 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:39,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:39,544 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 1 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:39,560 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:26:41,686 INFO L85 PathProgramCache]: Analyzing trace with hash -841980054, now seen corresponding path program 304 times [2024-05-06 18:26:41,686 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:41,686 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:41,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:41,890 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 1 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:41,890 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:41,890 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:41,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:42,093 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 1 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:42,108 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 1930 treesize of output 1834 [2024-05-06 18:26:44,256 INFO L85 PathProgramCache]: Analyzing trace with hash -331577177, now seen corresponding path program 305 times [2024-05-06 18:26:44,257 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:44,257 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:44,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:44,468 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 1 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:44,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:44,469 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:44,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:44,676 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 1 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:44,695 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:26:46,743 INFO L85 PathProgramCache]: Analyzing trace with hash -560304372, now seen corresponding path program 25 times [2024-05-06 18:26:46,743 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:46,743 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:46,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:47,057 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:26:47,057 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:47,057 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:47,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:47,280 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:26:47,318 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:26:49,372 INFO L85 PathProgramCache]: Analyzing trace with hash -842013594, now seen corresponding path program 306 times [2024-05-06 18:26:49,372 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:49,372 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:49,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:49,574 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 1 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:49,574 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:49,574 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:49,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:49,778 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 1 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:49,797 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:26:49,876 INFO L85 PathProgramCache]: Analyzing trace with hash -997024695, now seen corresponding path program 307 times [2024-05-06 18:26:49,876 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:49,876 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:49,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:50,081 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 1 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:50,081 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:50,081 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:50,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:50,281 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 1 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:50,303 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:26:52,345 INFO L85 PathProgramCache]: Analyzing trace with hash -1057719063, now seen corresponding path program 308 times [2024-05-06 18:26:52,346 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:52,346 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:52,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:52,566 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:52,567 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:52,567 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:52,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:52,894 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:52,913 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:26:52,990 INFO L85 PathProgramCache]: Analyzing trace with hash 1570448164, now seen corresponding path program 309 times [2024-05-06 18:26:52,990 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:52,991 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:53,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:53,193 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:53,193 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:53,193 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:53,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:53,396 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:53,411 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 972 treesize of output 924 [2024-05-06 18:26:53,993 INFO L85 PathProgramCache]: Analyzing trace with hash 1439253579, now seen corresponding path program 310 times [2024-05-06 18:26:53,993 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:53,993 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:54,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:54,197 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:54,198 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:54,198 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:54,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:54,465 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:54,485 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:26:54,860 INFO L85 PathProgramCache]: Analyzing trace with hash 1570472284, now seen corresponding path program 311 times [2024-05-06 18:26:54,861 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:54,861 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:54,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:55,063 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:55,063 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:55,063 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:55,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:55,266 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:55,285 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:26:55,368 INFO L85 PathProgramCache]: Analyzing trace with hash -1057692243, now seen corresponding path program 312 times [2024-05-06 18:26:55,369 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:55,369 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:55,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:55,705 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:55,705 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:55,705 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:55,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:55,912 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:55,934 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:26:55,997 INFO L85 PathProgramCache]: Analyzing trace with hash 349876126, now seen corresponding path program 26 times [2024-05-06 18:26:55,998 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:55,998 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:56,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:56,173 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 2 proven. 24 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:56,173 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:56,173 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:56,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:56,351 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 2 proven. 24 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:26:56,372 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:26:56,517 INFO L85 PathProgramCache]: Analyzing trace with hash 946691857, now seen corresponding path program 313 times [2024-05-06 18:26:56,517 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:56,517 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:56,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:56,722 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:26:56,722 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:56,722 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:56,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:56,927 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:26:56,946 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:26:57,017 INFO L85 PathProgramCache]: Analyzing trace with hash -717322786, now seen corresponding path program 314 times [2024-05-06 18:26:57,017 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:57,017 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:57,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:57,226 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:26:57,226 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:57,226 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:57,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:26:57,575 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:26:57,591 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 1930 treesize of output 1834 [2024-05-06 18:26:59,816 INFO L85 PathProgramCache]: Analyzing trace with hash -762169165, now seen corresponding path program 315 times [2024-05-06 18:26:59,816 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:26:59,816 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:26:59,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:00,024 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:27:00,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:00,024 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:00,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:00,232 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:27:00,251 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:27:02,305 INFO L85 PathProgramCache]: Analyzing trace with hash 806120728, now seen corresponding path program 27 times [2024-05-06 18:27:02,306 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:02,306 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:02,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:02,591 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:27:02,591 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:02,591 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:02,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:02,883 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:27:02,991 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:27:03,203 INFO L85 PathProgramCache]: Analyzing trace with hash -717356326, now seen corresponding path program 316 times [2024-05-06 18:27:03,203 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:03,203 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:03,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:03,446 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:27:03,447 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:03,447 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:03,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:03,835 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:27:03,870 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:27:05,992 INFO L85 PathProgramCache]: Analyzing trace with hash 946659157, now seen corresponding path program 317 times [2024-05-06 18:27:05,993 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:05,993 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:06,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:06,236 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:27:06,236 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:06,236 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:06,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:06,476 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:27:06,513 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:27:06,624 INFO L85 PathProgramCache]: Analyzing trace with hash -104047523, now seen corresponding path program 318 times [2024-05-06 18:27:06,625 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:06,625 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:06,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:06,862 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:06,863 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:06,863 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:06,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:07,098 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:07,130 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:27:09,231 INFO L85 PathProgramCache]: Analyzing trace with hash 1069494832, now seen corresponding path program 319 times [2024-05-06 18:27:09,231 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:09,231 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:09,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:09,468 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:09,469 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:09,469 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:09,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:09,720 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:09,755 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 972 treesize of output 924 [2024-05-06 18:27:12,086 INFO L85 PathProgramCache]: Analyzing trace with hash -1205397825, now seen corresponding path program 320 times [2024-05-06 18:27:12,086 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:12,086 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:12,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:12,455 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:12,455 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:12,455 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:12,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:12,704 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:12,746 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:27:14,833 INFO L85 PathProgramCache]: Analyzing trace with hash 1069518952, now seen corresponding path program 321 times [2024-05-06 18:27:14,833 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:14,833 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:14,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:15,073 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:15,074 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:15,074 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:15,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:15,329 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:15,370 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:27:15,545 INFO L85 PathProgramCache]: Analyzing trace with hash -104020703, now seen corresponding path program 322 times [2024-05-06 18:27:15,545 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:15,545 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:15,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:15,797 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:15,798 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:15,798 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:15,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:16,045 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:16,082 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:27:18,160 INFO L85 PathProgramCache]: Analyzing trace with hash 419977386, now seen corresponding path program 28 times [2024-05-06 18:27:18,160 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:18,161 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:18,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:18,382 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 2 proven. 24 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:18,382 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:18,382 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:18,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:18,722 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 2 proven. 24 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:18,763 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:27:18,895 INFO L85 PathProgramCache]: Analyzing trace with hash 1134750790, now seen corresponding path program 323 times [2024-05-06 18:27:18,895 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:18,895 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:18,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:19,150 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:27:19,151 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:19,151 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:19,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:19,401 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:27:19,440 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:27:19,634 INFO L85 PathProgramCache]: Analyzing trace with hash 817536841, now seen corresponding path program 324 times [2024-05-06 18:27:19,635 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:19,635 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:19,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:19,890 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:27:19,891 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:19,891 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:19,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:20,148 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:27:20,178 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 952 treesize of output 904 [2024-05-06 18:27:20,759 INFO L85 PathProgramCache]: Analyzing trace with hash -426160984, now seen corresponding path program 325 times [2024-05-06 18:27:20,759 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:20,759 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:20,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:21,006 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:27:21,007 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:21,007 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:21,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:21,386 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:27:21,422 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:27:21,555 INFO L85 PathProgramCache]: Analyzing trace with hash 1853110669, now seen corresponding path program 29 times [2024-05-06 18:27:21,555 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:21,555 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:21,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:21,829 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:27:21,829 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:21,829 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:21,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:22,094 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:27:22,134 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:27:22,305 INFO L85 PathProgramCache]: Analyzing trace with hash 817503301, now seen corresponding path program 326 times [2024-05-06 18:27:22,305 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:22,306 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:22,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:22,555 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:27:22,556 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:22,556 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:22,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:22,806 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:27:22,843 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:27:23,113 INFO L85 PathProgramCache]: Analyzing trace with hash 1134718090, now seen corresponding path program 327 times [2024-05-06 18:27:23,113 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:23,113 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:23,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:23,368 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:27:23,368 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:23,368 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:23,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:23,753 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:27:23,802 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:27:25,946 INFO L85 PathProgramCache]: Analyzing trace with hash 1808412552, now seen corresponding path program 328 times [2024-05-06 18:27:25,946 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:25,947 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:25,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:26,197 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:26,197 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:26,197 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:26,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:26,443 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:26,482 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:27:26,659 INFO L85 PathProgramCache]: Analyzing trace with hash 226215013, now seen corresponding path program 329 times [2024-05-06 18:27:26,659 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:26,659 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:26,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:26,904 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:26,905 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:26,905 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:26,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:27,152 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:27,179 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 972 treesize of output 924 [2024-05-06 18:27:27,522 INFO L85 PathProgramCache]: Analyzing trace with hash -1577268438, now seen corresponding path program 330 times [2024-05-06 18:27:27,522 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:27,522 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:27,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:27,770 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:27,770 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:27,770 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:27,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:28,149 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:28,188 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:27:28,337 INFO L85 PathProgramCache]: Analyzing trace with hash 226239133, now seen corresponding path program 331 times [2024-05-06 18:27:28,337 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:28,337 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:28,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:28,589 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:28,589 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:28,590 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:28,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:28,834 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:28,907 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:27:29,132 INFO L85 PathProgramCache]: Analyzing trace with hash 1808439372, now seen corresponding path program 332 times [2024-05-06 18:27:29,132 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:29,132 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:29,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:29,381 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:29,381 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:29,381 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:29,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:29,793 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:29,839 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:27:31,945 INFO L85 PathProgramCache]: Analyzing trace with hash -1256798113, now seen corresponding path program 30 times [2024-05-06 18:27:31,945 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:31,945 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:32,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:32,192 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 2 proven. 24 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:32,193 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:32,193 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:32,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:32,409 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 2 proven. 24 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:32,456 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:27:32,608 INFO L85 PathProgramCache]: Analyzing trace with hash -2058959310, now seen corresponding path program 333 times [2024-05-06 18:27:32,608 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:32,608 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:32,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:32,874 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:27:32,874 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:32,874 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:32,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:33,143 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:27:33,186 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:27:33,332 INFO L85 PathProgramCache]: Analyzing trace with hash 596771549, now seen corresponding path program 334 times [2024-05-06 18:27:33,332 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:33,332 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:33,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:33,678 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:27:33,678 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:33,678 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:33,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:33,925 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:27:33,952 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 473 treesize of output 449 [2024-05-06 18:27:36,205 INFO L85 PathProgramCache]: Analyzing trace with hash 1320049556, now seen corresponding path program 335 times [2024-05-06 18:27:36,205 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:36,206 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:36,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:36,459 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:27:36,459 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:36,459 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:36,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:36,722 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:27:36,768 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:27:38,862 INFO L85 PathProgramCache]: Analyzing trace with hash 1781417593, now seen corresponding path program 31 times [2024-05-06 18:27:38,862 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:38,863 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:38,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:39,144 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:27:39,144 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:39,144 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:39,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:39,545 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:27:39,590 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:27:41,691 INFO L85 PathProgramCache]: Analyzing trace with hash 596738009, now seen corresponding path program 336 times [2024-05-06 18:27:41,691 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:41,691 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:41,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:42,014 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:27:42,015 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:42,015 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:42,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:42,329 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:27:42,378 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:27:42,606 INFO L85 PathProgramCache]: Analyzing trace with hash -2058992010, now seen corresponding path program 337 times [2024-05-06 18:27:42,606 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:42,606 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:42,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:42,919 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:27:42,919 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:42,919 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:42,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:43,229 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:27:43,282 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:27:43,493 INFO L85 PathProgramCache]: Analyzing trace with hash -2067186660, now seen corresponding path program 338 times [2024-05-06 18:27:43,494 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:43,494 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:43,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:43,820 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:43,820 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:43,821 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:43,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:44,227 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:44,271 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:27:44,424 INFO L85 PathProgramCache]: Analyzing trace with hash 341723729, now seen corresponding path program 339 times [2024-05-06 18:27:44,424 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:44,424 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:44,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:44,692 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:44,692 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:44,693 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:44,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:44,968 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:45,000 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 1930 treesize of output 1834 [2024-05-06 18:27:45,631 INFO L85 PathProgramCache]: Analyzing trace with hash 2003501758, now seen corresponding path program 340 times [2024-05-06 18:27:45,632 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:45,632 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:45,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:45,893 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:45,893 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:45,893 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:45,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:46,141 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:46,180 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:27:46,418 INFO L85 PathProgramCache]: Analyzing trace with hash 341747849, now seen corresponding path program 341 times [2024-05-06 18:27:46,418 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:46,418 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:46,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:46,730 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:46,731 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:46,731 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:46,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:47,039 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:47,074 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:27:47,240 INFO L85 PathProgramCache]: Analyzing trace with hash -2067159840, now seen corresponding path program 342 times [2024-05-06 18:27:47,240 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:47,240 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:47,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:47,490 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:47,490 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:47,491 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:47,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:47,732 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:47,764 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:27:47,900 INFO L85 PathProgramCache]: Analyzing trace with hash -634619829, now seen corresponding path program 32 times [2024-05-06 18:27:47,900 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:47,900 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:47,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:48,115 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 2 proven. 24 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:48,116 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:48,116 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:48,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:48,326 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 2 proven. 24 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:48,365 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:27:48,514 INFO L85 PathProgramCache]: Analyzing trace with hash -1733679422, now seen corresponding path program 343 times [2024-05-06 18:27:48,515 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:48,515 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:48,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:27:48,568 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:27:48,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:27:48,656 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:27:50,776 INFO L85 PathProgramCache]: Analyzing trace with hash 2090513485, now seen corresponding path program 344 times [2024-05-06 18:27:50,776 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:50,776 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:50,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:27:50,844 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:27:50,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:27:50,931 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 1930 treesize of output 1834 [2024-05-06 18:27:51,146 INFO L85 PathProgramCache]: Analyzing trace with hash 381409316, now seen corresponding path program 345 times [2024-05-06 18:27:51,147 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:51,147 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:51,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:27:51,298 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 18:27:51,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 18:27:51,432 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:27:51,562 INFO L85 PathProgramCache]: Analyzing trace with hash -1381811384, now seen corresponding path program 346 times [2024-05-06 18:27:51,563 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:51,563 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:51,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:52,507 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 1 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:52,508 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:52,508 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:52,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:52,798 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 1 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:52,836 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:27:52,953 INFO L85 PathProgramCache]: Analyzing trace with hash 113520805, now seen corresponding path program 347 times [2024-05-06 18:27:52,954 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:52,954 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:53,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:53,244 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 1 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:53,244 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:53,244 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:53,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:53,537 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 1 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:53,565 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 952 treesize of output 904 [2024-05-06 18:27:53,739 INFO L85 PathProgramCache]: Analyzing trace with hash -775821590, now seen corresponding path program 348 times [2024-05-06 18:27:53,739 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:53,739 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:53,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:55,263 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 99 trivial. 0 not checked. [2024-05-06 18:27:55,263 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:55,263 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:55,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:55,620 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 99 trivial. 0 not checked. [2024-05-06 18:27:55,757 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:27:55,930 INFO L85 PathProgramCache]: Analyzing trace with hash 113530510, now seen corresponding path program 349 times [2024-05-06 18:27:55,931 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:55,931 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:56,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:56,473 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 1 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:56,473 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:56,473 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:56,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:56,848 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 1 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:56,919 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:27:59,033 INFO L85 PathProgramCache]: Analyzing trace with hash -1381799444, now seen corresponding path program 350 times [2024-05-06 18:27:59,033 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:59,033 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:59,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:59,324 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 1 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:27:59,324 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:27:59,324 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:27:59,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:27:59,598 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 1 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:28:00,057 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:28:00,236 INFO L85 PathProgramCache]: Analyzing trace with hash 346418308, now seen corresponding path program 351 times [2024-05-06 18:28:00,236 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:00,237 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:00,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:01,485 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:28:01,485 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:01,486 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:01,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:01,882 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:28:01,925 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:28:02,081 INFO L85 PathProgramCache]: Analyzing trace with hash -2145933606, now seen corresponding path program 352 times [2024-05-06 18:28:02,081 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:02,081 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:02,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:02,358 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:28:02,358 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:02,359 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:02,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:02,649 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 73 trivial. 0 not checked. [2024-05-06 18:28:02,678 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 952 treesize of output 904 [2024-05-06 18:28:02,808 INFO L85 PathProgramCache]: Analyzing trace with hash -2099431610, now seen corresponding path program 353 times [2024-05-06 18:28:02,809 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:02,809 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:02,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:03,134 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 99 trivial. 0 not checked. [2024-05-06 18:28:03,134 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:03,135 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:03,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:03,286 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 99 trivial. 0 not checked. [2024-05-06 18:28:03,287 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-05-06 18:28:03,290 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=504, Invalid=15498, Unknown=0, NotChecked=0, Total=16002 [2024-05-06 18:28:03,638 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:28:05,727 INFO L85 PathProgramCache]: Analyzing trace with hash 2042985164, now seen corresponding path program 33 times [2024-05-06 18:28:05,727 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:05,728 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:05,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:06,106 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 7 proven. 54 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:28:06,106 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:06,106 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:06,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:06,416 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 7 proven. 54 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:28:06,460 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:28:08,541 INFO L85 PathProgramCache]: Analyzing trace with hash 1417532768, now seen corresponding path program 354 times [2024-05-06 18:28:08,541 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:08,541 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:08,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:08,806 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 22 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:28:08,806 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:08,806 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:08,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:09,072 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 22 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:28:09,114 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:28:09,287 INFO L85 PathProgramCache]: Analyzing trace with hash 993843567, now seen corresponding path program 355 times [2024-05-06 18:28:09,288 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:09,288 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:09,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:09,557 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 22 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:28:09,558 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:09,558 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:09,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:09,963 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 22 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:28:09,994 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 952 treesize of output 904 [2024-05-06 18:28:10,341 INFO L85 PathProgramCache]: Analyzing trace with hash 744380226, now seen corresponding path program 356 times [2024-05-06 18:28:10,341 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:10,341 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:10,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:10,686 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 22 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:28:10,686 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:10,686 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:10,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:10,961 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 22 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:28:11,010 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:28:13,110 INFO L85 PathProgramCache]: Analyzing trace with hash -842257113, now seen corresponding path program 34 times [2024-05-06 18:28:13,110 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:13,110 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:13,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:13,375 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 22 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:28:13,375 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:13,375 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:13,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:13,645 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 22 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:28:13,687 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:28:13,877 INFO L85 PathProgramCache]: Analyzing trace with hash 993824442, now seen corresponding path program 357 times [2024-05-06 18:28:13,877 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:13,877 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:13,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:14,136 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 22 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:28:14,136 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:14,136 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:14,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:14,437 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 22 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:28:14,478 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:28:14,692 INFO L85 PathProgramCache]: Analyzing trace with hash 1417514948, now seen corresponding path program 358 times [2024-05-06 18:28:14,693 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:14,693 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:14,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:14,950 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 22 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:28:14,951 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:14,951 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:14,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:15,204 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 22 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:28:15,244 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:28:15,411 INFO L85 PathProgramCache]: Analyzing trace with hash 1994037838, now seen corresponding path program 359 times [2024-05-06 18:28:15,412 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:15,412 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:15,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:15,686 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 6 proven. 54 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:28:15,686 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:15,686 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:15,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:16,046 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 6 proven. 54 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:28:16,089 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:28:18,191 INFO L85 PathProgramCache]: Analyzing trace with hash 1685631568, now seen corresponding path program 360 times [2024-05-06 18:28:18,191 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:18,191 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:18,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:18,462 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 6 proven. 54 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:28:18,463 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:18,463 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:18,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:18,736 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 6 proven. 54 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:28:18,763 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 1930 treesize of output 1834 [2024-05-06 18:28:21,263 INFO L85 PathProgramCache]: Analyzing trace with hash 714971792, now seen corresponding path program 361 times [2024-05-06 18:28:21,264 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:21,264 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:21,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:21,543 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 6 proven. 54 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:28:21,543 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:21,543 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:21,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:21,898 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 6 proven. 54 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:28:21,931 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:28:22,103 INFO L85 PathProgramCache]: Analyzing trace with hash 1994049778, now seen corresponding path program 362 times [2024-05-06 18:28:22,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:22,103 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:22,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:22,370 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 6 proven. 54 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:28:22,371 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:22,371 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:22,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:22,653 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 6 proven. 54 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:28:22,696 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:28:22,837 INFO L85 PathProgramCache]: Analyzing trace with hash 310080825, now seen corresponding path program 35 times [2024-05-06 18:28:22,837 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:22,837 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:22,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:23,157 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 7 proven. 53 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:28:23,157 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:23,157 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:23,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:23,547 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 7 proven. 53 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:28:23,591 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:28:23,761 INFO L85 PathProgramCache]: Analyzing trace with hash -1484987763, now seen corresponding path program 363 times [2024-05-06 18:28:23,761 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:23,761 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:23,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:24,019 INFO L134 CoverageAnalysis]: Checked inductivity of 133 backedges. 21 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:28:24,020 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:24,020 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:24,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:24,271 INFO L134 CoverageAnalysis]: Checked inductivity of 133 backedges. 21 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:28:24,298 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 972 treesize of output 924 [2024-05-06 18:28:26,634 INFO L85 PathProgramCache]: Analyzing trace with hash -1144074961, now seen corresponding path program 364 times [2024-05-06 18:28:26,635 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:26,635 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:26,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:26,993 INFO L134 CoverageAnalysis]: Checked inductivity of 133 backedges. 21 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:28:26,993 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:26,993 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:27,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:27,255 INFO L134 CoverageAnalysis]: Checked inductivity of 133 backedges. 21 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:28:27,295 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:28:29,379 INFO L85 PathProgramCache]: Analyzing trace with hash 1719805844, now seen corresponding path program 36 times [2024-05-06 18:28:29,379 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:29,379 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:29,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:29,641 INFO L134 CoverageAnalysis]: Checked inductivity of 133 backedges. 21 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:28:29,641 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:29,641 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:29,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:29,916 INFO L134 CoverageAnalysis]: Checked inductivity of 133 backedges. 21 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:28:29,948 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:28:31,155 INFO L85 PathProgramCache]: Analyzing trace with hash 1210001197, now seen corresponding path program 365 times [2024-05-06 18:28:31,155 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:31,155 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:31,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:31,495 INFO L134 CoverageAnalysis]: Checked inductivity of 133 backedges. 21 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:28:31,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:31,496 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:31,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:31,751 INFO L134 CoverageAnalysis]: Checked inductivity of 133 backedges. 21 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:28:31,791 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:28:33,884 INFO L85 PathProgramCache]: Analyzing trace with hash -1485005583, now seen corresponding path program 366 times [2024-05-06 18:28:33,884 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:33,884 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:33,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:34,138 INFO L134 CoverageAnalysis]: Checked inductivity of 133 backedges. 21 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:28:34,138 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:34,138 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:34,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:34,390 INFO L134 CoverageAnalysis]: Checked inductivity of 133 backedges. 21 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:28:34,437 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:28:34,789 INFO L85 PathProgramCache]: Analyzing trace with hash -629631359, now seen corresponding path program 367 times [2024-05-06 18:28:34,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:34,789 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:34,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:35,150 INFO L134 CoverageAnalysis]: Checked inductivity of 133 backedges. 6 proven. 53 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:28:35,150 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:35,150 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:35,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:35,423 INFO L134 CoverageAnalysis]: Checked inductivity of 133 backedges. 6 proven. 53 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:28:35,461 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:28:37,603 INFO L85 PathProgramCache]: Analyzing trace with hash 1956265085, now seen corresponding path program 368 times [2024-05-06 18:28:37,603 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:37,603 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:37,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:37,895 INFO L134 CoverageAnalysis]: Checked inductivity of 133 backedges. 6 proven. 53 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:28:37,896 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:37,896 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:37,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:38,187 INFO L134 CoverageAnalysis]: Checked inductivity of 133 backedges. 6 proven. 53 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:28:38,222 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 972 treesize of output 924 [2024-05-06 18:28:38,761 INFO L85 PathProgramCache]: Analyzing trace with hash 514676227, now seen corresponding path program 369 times [2024-05-06 18:28:38,761 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:38,761 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:38,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:39,150 INFO L134 CoverageAnalysis]: Checked inductivity of 133 backedges. 6 proven. 53 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:28:39,150 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:39,151 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:39,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:39,424 INFO L134 CoverageAnalysis]: Checked inductivity of 133 backedges. 6 proven. 53 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:28:39,465 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:28:40,562 INFO L85 PathProgramCache]: Analyzing trace with hash -629619419, now seen corresponding path program 370 times [2024-05-06 18:28:40,563 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:40,563 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:40,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:40,851 INFO L134 CoverageAnalysis]: Checked inductivity of 133 backedges. 6 proven. 53 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:28:40,851 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:40,851 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:40,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:41,231 INFO L134 CoverageAnalysis]: Checked inductivity of 133 backedges. 6 proven. 53 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:28:41,263 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:28:41,419 INFO L85 PathProgramCache]: Analyzing trace with hash 107416045, now seen corresponding path program 37 times [2024-05-06 18:28:41,419 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:41,419 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:41,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:41,717 INFO L134 CoverageAnalysis]: Checked inductivity of 133 backedges. 7 proven. 52 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:28:41,717 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:41,717 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:41,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:42,021 INFO L134 CoverageAnalysis]: Checked inductivity of 133 backedges. 7 proven. 52 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:28:42,090 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:28:44,196 INFO L85 PathProgramCache]: Analyzing trace with hash -209452479, now seen corresponding path program 371 times [2024-05-06 18:28:44,196 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:44,196 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:44,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:44,465 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 20 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:28:44,465 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:44,466 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:44,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:44,807 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 20 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:28:44,839 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 972 treesize of output 924 [2024-05-06 18:28:47,200 INFO L85 PathProgramCache]: Analyzing trace with hash 579653603, now seen corresponding path program 372 times [2024-05-06 18:28:47,200 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:47,200 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:47,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:47,474 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 20 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:28:47,475 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:47,475 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:47,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:47,748 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 20 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:28:47,792 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:28:47,967 INFO L85 PathProgramCache]: Analyzing trace with hash 1517141064, now seen corresponding path program 38 times [2024-05-06 18:28:47,968 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:47,968 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:48,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:48,318 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 20 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:28:48,318 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:48,318 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:48,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:48,587 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 20 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:28:48,625 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:28:48,899 INFO L85 PathProgramCache]: Analyzing trace with hash 2096889337, now seen corresponding path program 373 times [2024-05-06 18:28:48,900 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:48,900 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:48,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:49,155 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 20 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:28:49,155 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:49,155 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:49,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:49,496 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 20 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:28:49,534 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:28:49,728 INFO L85 PathProgramCache]: Analyzing trace with hash -209470299, now seen corresponding path program 374 times [2024-05-06 18:28:49,728 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:49,728 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:49,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:49,980 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 20 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:28:49,980 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:49,980 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:50,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:50,232 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 20 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:28:50,275 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:28:50,417 INFO L85 PathProgramCache]: Analyzing trace with hash -1545520051, now seen corresponding path program 375 times [2024-05-06 18:28:50,417 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:50,417 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:50,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:50,694 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 6 proven. 52 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:28:50,694 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:50,694 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:50,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:51,051 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 6 proven. 52 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:28:51,087 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:28:53,231 INFO L85 PathProgramCache]: Analyzing trace with hash -666480591, now seen corresponding path program 376 times [2024-05-06 18:28:53,232 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:53,232 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:53,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:53,522 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 6 proven. 52 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:28:53,523 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:53,523 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:53,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:53,887 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 6 proven. 52 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:28:53,923 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 952 treesize of output 904 [2024-05-06 18:28:56,780 INFO L85 PathProgramCache]: Analyzing trace with hash 813938895, now seen corresponding path program 377 times [2024-05-06 18:28:56,781 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:56,781 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:56,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:57,148 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 6 proven. 52 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:28:57,148 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:57,148 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:57,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:57,437 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 6 proven. 52 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:28:57,479 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:28:57,632 INFO L85 PathProgramCache]: Analyzing trace with hash -1545508111, now seen corresponding path program 378 times [2024-05-06 18:28:57,632 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:57,632 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:57,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:57,904 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 6 proven. 52 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:28:57,904 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:28:57,905 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:28:57,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:28:58,261 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 6 proven. 52 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:28:58,327 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:29:00,407 INFO L85 PathProgramCache]: Analyzing trace with hash -1569906822, now seen corresponding path program 39 times [2024-05-06 18:29:00,407 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:00,407 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:00,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:00,704 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 7 proven. 51 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:29:00,704 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:00,704 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:00,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:00,995 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 7 proven. 51 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:29:01,041 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:29:01,345 INFO L85 PathProgramCache]: Analyzing trace with hash 92480142, now seen corresponding path program 379 times [2024-05-06 18:29:01,345 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:01,345 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:01,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:01,601 INFO L134 CoverageAnalysis]: Checked inductivity of 131 backedges. 19 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:29:01,601 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:01,601 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:01,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:01,857 INFO L134 CoverageAnalysis]: Checked inductivity of 131 backedges. 19 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:29:01,887 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 952 treesize of output 904 [2024-05-06 18:29:02,291 INFO L85 PathProgramCache]: Analyzing trace with hash -1320873744, now seen corresponding path program 380 times [2024-05-06 18:29:02,292 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:02,292 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:02,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:02,547 INFO L134 CoverageAnalysis]: Checked inductivity of 131 backedges. 19 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:29:02,548 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:02,548 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:02,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:02,879 INFO L134 CoverageAnalysis]: Checked inductivity of 131 backedges. 19 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:29:02,918 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:29:03,050 INFO L85 PathProgramCache]: Analyzing trace with hash -160181803, now seen corresponding path program 40 times [2024-05-06 18:29:03,050 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:03,050 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:03,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:03,313 INFO L134 CoverageAnalysis]: Checked inductivity of 131 backedges. 19 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:29:03,314 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:03,314 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:03,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:03,580 INFO L134 CoverageAnalysis]: Checked inductivity of 131 backedges. 19 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:29:03,622 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:29:03,791 INFO L85 PathProgramCache]: Analyzing trace with hash -1428101300, now seen corresponding path program 381 times [2024-05-06 18:29:03,791 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:03,791 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:03,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:04,110 INFO L134 CoverageAnalysis]: Checked inductivity of 131 backedges. 19 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:29:04,110 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:04,110 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:04,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:04,358 INFO L134 CoverageAnalysis]: Checked inductivity of 131 backedges. 19 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:29:04,392 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:29:04,585 INFO L85 PathProgramCache]: Analyzing trace with hash 92462322, now seen corresponding path program 382 times [2024-05-06 18:29:04,585 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:04,585 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:04,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:04,835 INFO L134 CoverageAnalysis]: Checked inductivity of 131 backedges. 19 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:29:04,835 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:04,835 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:04,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:05,150 INFO L134 CoverageAnalysis]: Checked inductivity of 131 backedges. 19 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:29:05,188 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:29:05,408 INFO L85 PathProgramCache]: Analyzing trace with hash -1020845728, now seen corresponding path program 383 times [2024-05-06 18:29:05,408 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:05,408 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:05,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:05,779 INFO L134 CoverageAnalysis]: Checked inductivity of 131 backedges. 6 proven. 51 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:29:05,780 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:05,780 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:05,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:06,146 INFO L134 CoverageAnalysis]: Checked inductivity of 131 backedges. 6 proven. 51 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:29:06,185 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:29:08,301 INFO L85 PathProgramCache]: Analyzing trace with hash -1581445762, now seen corresponding path program 384 times [2024-05-06 18:29:08,301 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:08,302 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:08,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:08,572 INFO L134 CoverageAnalysis]: Checked inductivity of 131 backedges. 6 proven. 51 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:29:08,572 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:08,572 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:08,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:08,846 INFO L134 CoverageAnalysis]: Checked inductivity of 131 backedges. 6 proven. 51 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:29:08,873 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 473 treesize of output 449 [2024-05-06 18:29:09,447 INFO L85 PathProgramCache]: Analyzing trace with hash -1780177630, now seen corresponding path program 385 times [2024-05-06 18:29:09,447 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:09,447 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:09,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:09,857 INFO L134 CoverageAnalysis]: Checked inductivity of 131 backedges. 6 proven. 51 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:29:09,857 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:09,857 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:09,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:10,129 INFO L134 CoverageAnalysis]: Checked inductivity of 131 backedges. 6 proven. 51 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:29:10,168 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:29:10,289 INFO L85 PathProgramCache]: Analyzing trace with hash -1020833788, now seen corresponding path program 386 times [2024-05-06 18:29:10,289 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:10,289 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:10,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:10,557 INFO L134 CoverageAnalysis]: Checked inductivity of 131 backedges. 6 proven. 51 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:29:10,557 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:10,557 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:10,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:10,947 INFO L134 CoverageAnalysis]: Checked inductivity of 131 backedges. 6 proven. 51 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:29:10,995 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:29:11,144 INFO L85 PathProgramCache]: Analyzing trace with hash 2141713358, now seen corresponding path program 387 times [2024-05-06 18:29:11,144 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:11,144 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:11,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:11,391 INFO L134 CoverageAnalysis]: Checked inductivity of 130 backedges. 5 proven. 51 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:29:11,391 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:11,391 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:11,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:11,719 INFO L134 CoverageAnalysis]: Checked inductivity of 130 backedges. 5 proven. 51 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:29:11,759 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:29:11,952 INFO L85 PathProgramCache]: Analyzing trace with hash 1968605377, now seen corresponding path program 388 times [2024-05-06 18:29:11,952 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:11,952 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:12,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:12,201 INFO L134 CoverageAnalysis]: Checked inductivity of 130 backedges. 5 proven. 51 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:29:12,201 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:12,201 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:12,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:12,444 INFO L134 CoverageAnalysis]: Checked inductivity of 130 backedges. 5 proven. 51 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:29:12,479 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:29:14,558 INFO L85 PathProgramCache]: Analyzing trace with hash 2074504256, now seen corresponding path program 389 times [2024-05-06 18:29:14,558 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:14,559 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:14,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:14,923 INFO L134 CoverageAnalysis]: Checked inductivity of 131 backedges. 18 proven. 36 refuted. 0 times theorem prover too weak. 77 trivial. 0 not checked. [2024-05-06 18:29:14,923 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:14,924 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:14,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:15,179 INFO L134 CoverageAnalysis]: Checked inductivity of 131 backedges. 18 proven. 36 refuted. 0 times theorem prover too weak. 77 trivial. 0 not checked. [2024-05-06 18:29:15,205 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:29:15,327 INFO L85 PathProgramCache]: Analyzing trace with hash -114876770, now seen corresponding path program 390 times [2024-05-06 18:29:15,327 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:15,327 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:15,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:15,651 INFO L134 CoverageAnalysis]: Checked inductivity of 131 backedges. 18 proven. 36 refuted. 0 times theorem prover too weak. 77 trivial. 0 not checked. [2024-05-06 18:29:15,651 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:15,652 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:15,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:15,917 INFO L134 CoverageAnalysis]: Checked inductivity of 131 backedges. 18 proven. 36 refuted. 0 times theorem prover too weak. 77 trivial. 0 not checked. [2024-05-06 18:29:15,940 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 972 treesize of output 924 [2024-05-06 18:29:16,286 INFO L85 PathProgramCache]: Analyzing trace with hash 733788162, now seen corresponding path program 391 times [2024-05-06 18:29:16,287 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:16,287 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:16,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:16,621 INFO L134 CoverageAnalysis]: Checked inductivity of 131 backedges. 18 proven. 36 refuted. 0 times theorem prover too weak. 77 trivial. 0 not checked. [2024-05-06 18:29:16,621 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:16,621 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:16,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:16,892 INFO L134 CoverageAnalysis]: Checked inductivity of 131 backedges. 18 proven. 36 refuted. 0 times theorem prover too weak. 77 trivial. 0 not checked. [2024-05-06 18:29:16,930 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:29:17,047 INFO L85 PathProgramCache]: Analyzing trace with hash 1179539183, now seen corresponding path program 392 times [2024-05-06 18:29:17,048 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:17,048 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:17,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:17,308 INFO L134 CoverageAnalysis]: Checked inductivity of 131 backedges. 18 proven. 36 refuted. 0 times theorem prover too weak. 77 trivial. 0 not checked. [2024-05-06 18:29:17,308 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:17,309 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:17,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:17,632 INFO L134 CoverageAnalysis]: Checked inductivity of 131 backedges. 18 proven. 36 refuted. 0 times theorem prover too weak. 77 trivial. 0 not checked. [2024-05-06 18:29:17,675 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:29:19,758 INFO L85 PathProgramCache]: Analyzing trace with hash -1935193954, now seen corresponding path program 41 times [2024-05-06 18:29:19,758 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:19,758 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:19,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:20,044 INFO L134 CoverageAnalysis]: Checked inductivity of 131 backedges. 7 proven. 50 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:29:20,044 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:20,044 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:20,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:20,412 INFO L134 CoverageAnalysis]: Checked inductivity of 131 backedges. 7 proven. 50 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2024-05-06 18:29:20,457 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:29:20,621 INFO L85 PathProgramCache]: Analyzing trace with hash -1419486542, now seen corresponding path program 393 times [2024-05-06 18:29:20,622 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:20,622 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:20,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:20,877 INFO L134 CoverageAnalysis]: Checked inductivity of 130 backedges. 18 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:29:20,877 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:20,877 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:20,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:21,192 INFO L134 CoverageAnalysis]: Checked inductivity of 130 backedges. 18 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:29:21,268 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 972 treesize of output 924 [2024-05-06 18:29:22,378 INFO L85 PathProgramCache]: Analyzing trace with hash 1673056276, now seen corresponding path program 394 times [2024-05-06 18:29:22,378 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:22,378 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:22,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:22,644 INFO L134 CoverageAnalysis]: Checked inductivity of 130 backedges. 18 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:29:22,645 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:22,645 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:22,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:22,957 INFO L134 CoverageAnalysis]: Checked inductivity of 130 backedges. 18 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:29:22,995 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 29 [2024-05-06 18:29:23,132 INFO L85 PathProgramCache]: Analyzing trace with hash -525468935, now seen corresponding path program 42 times [2024-05-06 18:29:23,132 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:23,133 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:23,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:23,403 INFO L134 CoverageAnalysis]: Checked inductivity of 130 backedges. 18 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:29:23,404 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:23,404 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:23,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:23,726 INFO L134 CoverageAnalysis]: Checked inductivity of 130 backedges. 18 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:29:23,760 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:29:23,911 INFO L85 PathProgramCache]: Analyzing trace with hash -1054428248, now seen corresponding path program 395 times [2024-05-06 18:29:23,912 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:23,912 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:23,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:24,166 INFO L134 CoverageAnalysis]: Checked inductivity of 130 backedges. 18 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:29:24,166 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:24,166 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:24,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:24,475 INFO L134 CoverageAnalysis]: Checked inductivity of 130 backedges. 18 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:29:24,511 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 37 [2024-05-06 18:29:24,641 INFO L85 PathProgramCache]: Analyzing trace with hash -1419504362, now seen corresponding path program 396 times [2024-05-06 18:29:24,642 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:24,642 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:24,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:24,895 INFO L134 CoverageAnalysis]: Checked inductivity of 130 backedges. 18 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:29:24,895 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 18:29:24,895 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 18:29:24,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 18:29:25,208 INFO L134 CoverageAnalysis]: Checked inductivity of 130 backedges. 18 proven. 36 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-05-06 18:29:25,248 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 972 treesize of output 924 Received shutdown request... [2024-05-06 18:29:25,366 WARN L340 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 (2)] Timeout while monitored process is still running, waiting 1000 ms for graceful end [2024-05-06 18:29:25,366 WARN L340 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Timeout while monitored process is still running, waiting 1000 ms for graceful end [2024-05-06 18:29:25,366 WARN L340 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Timeout while monitored process is still running, waiting 1000 ms for graceful end [2024-05-06 18:29:25,383 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2024-05-06 18:29:25,566 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1109,SelfDestructingSolverStorable1108,SelfDestructingSolverStorable1229,SelfDestructingSolverStorable1107,SelfDestructingSolverStorable1228,SelfDestructingSolverStorable1106,SelfDestructingSolverStorable1227,SelfDestructingSolverStorable1105,SelfDestructingSolverStorable1226,SelfDestructingSolverStorable1104,SelfDestructingSolverStorable1225,SelfDestructingSolverStorable1103,SelfDestructingSolverStorable1224,SelfDestructingSolverStorable1102,SelfDestructingSolverStorable1223,SelfDestructingSolverStorable1101,SelfDestructingSolverStorable1222,SelfDestructingSolverStorable1100,SelfDestructingSolverStorable1221,SelfDestructingSolverStorable1220,SelfDestructingSolverStorable1230,SelfDestructingSolverStorable1119,SelfDestructingSolverStorable1118,SelfDestructingSolverStorable1117,SelfDestructingSolverStorable1116,SelfDestructingSolverStorable1115,SelfDestructingSolverStorable1114,SelfDestructingSolverStorable1235,SelfDestructingSolverStorable1113,SelfDestructingSolverStorable1234,SelfDestructingSolverStorable1112,SelfDestructingSolverStorable1233,SelfDestructingSolverStorable1111,SelfDestructingSolverStorable1232,SelfDestructingSolverStorable1110,SelfDestructingSolverStorable1231,SelfDestructingSolverStorable1209,SelfDestructingSolverStorable1208,SelfDestructingSolverStorable1207,SelfDestructingSolverStorable1206,SelfDestructingSolverStorable1205,SelfDestructingSolverStorable1204,SelfDestructingSolverStorable1203,SelfDestructingSolverStorable1202,SelfDestructingSolverStorable1201,SelfDestructingSolverStorable1200,SelfDestructingSolverStorable1219,SelfDestructingSolverStorable1218,SelfDestructingSolverStorable1217,SelfDestructingSolverStorable1216,SelfDestructingSolverStorable1215,SelfDestructingSolverStorable1214,SelfDestructingSolverStorable1213,SelfDestructingSolverStorable1212,SelfDestructingSolverStorable1211,SelfDestructingSolverStorable1210,SelfDestructingSolverStorable990,SelfDestructingSolverStorable988,SelfDestructingSolverStorable989,SelfDestructingSolverStorable984,SelfDestructingSolverStorable985,SelfDestructingSolverStorable986,SelfDestructingSolverStorable987,SelfDestructingSolverStorable980,SelfDestructingSolverStorable981,SelfDestructingSolverStorable982,SelfDestructingSolverStorable983,SelfDestructingSolverStorable977,SelfDestructingSolverStorable978,SelfDestructingSolverStorable979,SelfDestructingSolverStorable973,SelfDestructingSolverStorable974,SelfDestructingSolverStorable975,SelfDestructingSolverStorable976,SelfDestructingSolverStorable970,SelfDestructingSolverStorable971,SelfDestructingSolverStorable972,SelfDestructingSolverStorable1087,SelfDestructingSolverStorable1086,SelfDestructingSolverStorable1085,SelfDestructingSolverStorable1084,SelfDestructingSolverStorable1083,SelfDestructingSolverStorable1082,SelfDestructingSolverStorable1081,SelfDestructingSolverStorable1080,SelfDestructingSolverStorable1089,SelfDestructingSolverStorable1088,SelfDestructingSolverStorable1098,SelfDestructingSolverStorable1097,SelfDestructingSolverStorable1096,SelfDestructingSolverStorable1095,SelfDestructingSolverStorable1094,SelfDestructingSolverStorable1093,SelfDestructingSolverStorable1092,SelfDestructingSolverStorable1091,SelfDestructingSolverStorable1090,SelfDestructingSolverStorable999,SelfDestructingSolverStorable995,4 /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable996,SelfDestructingSolverStorable997,SelfDestructingSolverStorable998,SelfDestructingSolverStorable991,SelfDestructingSolverStorable992,SelfDestructingSolverStorable993,SelfDestructingSolverStorable994,SelfDestructingSolverStorable1099,SelfDestructingSolverStorable1065,SelfDestructingSolverStorable1186,SelfDestructingSolverStorable1064,SelfDestructingSolverStorable1185,SelfDestructingSolverStorable1063,SelfDestructingSolverStorable1184,SelfDestructingSolverStorable1062,SelfDestructingSolverStorable1183,SelfDestructingSolverStorable1061,SelfDestructingSolverStorable1182,SelfDestructingSolverStorable1060,SelfDestructingSolverStorable1181,SelfDestructingSolverStorable1180,SelfDestructingSolverStorable948,SelfDestructingSolverStorable949,SelfDestructingSolverStorable944,SelfDestructingSolverStorable945,SelfDestructingSolverStorable946,SelfDestructingSolverStorable947,SelfDestructingSolverStorable940,SelfDestructingSolverStorable941,SelfDestructingSolverStorable942,SelfDestructingSolverStorable943,SelfDestructingSolverStorable1069,SelfDestructingSolverStorable1068,SelfDestructingSolverStorable1189,SelfDestructingSolverStorable1067,SelfDestructingSolverStorable1188,SelfDestructingSolverStorable1066,SelfDestructingSolverStorable1187,SelfDestructingSolverStorable1076,SelfDestructingSolverStorable1197,SelfDestructingSolverStorable1075,SelfDestructingSolverStorable1196,SelfDestructingSolverStorable1074,SelfDestructingSolverStorable1195,SelfDestructingSolverStorable1073,SelfDestructingSolverStorable1194,SelfDestructingSolverStorable1072,SelfDestructingSolverStorable1193,SelfDestructingSolverStorable1071,SelfDestructingSolverStorable1192,SelfDestructingSolverStorable1070,SelfDestructingSolverStorable1191,SelfDestructingSolverStorable1190,SelfDestructingSolverStorable937,SelfDestructingSolverStorable938,SelfDestructingSolverStorable939,SelfDestructingSolverStorable933,SelfDestructingSolverStorable934,SelfDestructingSolverStorable935,SelfDestructingSolverStorable936,SelfDestructingSolverStorable930,SelfDestructingSolverStorable931,SelfDestructingSolverStorable932,SelfDestructingSolverStorable1079,SelfDestructingSolverStorable1078,SelfDestructingSolverStorable1199,SelfDestructingSolverStorable1077,SelfDestructingSolverStorable1198,SelfDestructingSolverStorable1043,SelfDestructingSolverStorable1164,SelfDestructingSolverStorable1042,SelfDestructingSolverStorable1163,SelfDestructingSolverStorable1041,SelfDestructingSolverStorable1162,SelfDestructingSolverStorable1040,SelfDestructingSolverStorable1161,SelfDestructingSolverStorable1160,SelfDestructingSolverStorable966,SelfDestructingSolverStorable967,SelfDestructingSolverStorable968,SelfDestructingSolverStorable969,SelfDestructingSolverStorable962,SelfDestructingSolverStorable963,SelfDestructingSolverStorable964,SelfDestructingSolverStorable1049,SelfDestructingSolverStorable965,SelfDestructingSolverStorable1048,SelfDestructingSolverStorable1169,SelfDestructingSolverStorable1047,SelfDestructingSolverStorable1168,SelfDestructingSolverStorable1046,SelfDestructingSolverStorable1167,SelfDestructingSolverStorable960,SelfDestructingSolverStorable1045,SelfDestructingSolverStorable1166,SelfDestructingSolverStorable961,SelfDestructingSolverStorable1044,SelfDestructingSolverStorable1165,SelfDestructingSolverStorable1054,SelfDestructingSolverStorable1175,SelfDestructingSolverStorable1053,SelfDestructingSolverStorable1174,SelfDestructingSolverStorable1052,SelfDestructingSolverStorable1173,SelfDestructingSolverStorable1051,SelfDestructingSolverStorable1172,SelfDestructingSolverStorable1050,SelfDestructingSolverStorable1171,SelfDestructingSolverStorable1170,SelfDestructingSolverStorable959,SelfDestructingSolverStorable955,SelfDestructingSolverStorable956,SelfDestructingSolverStorable957,SelfDestructingSolverStorable958,SelfDestructingSolverStorable951,SelfDestructingSolverStorable952,SelfDestructingSolverStorable953,SelfDestructingSolverStorable954,SelfDestructingSolverStorable1059,SelfDestructingSolverStorable1058,SelfDestructingSolverStorable1179,SelfDestructingSolverStorable1057,SelfDestructingSolverStorable1178,SelfDestructingSolverStorable1056,SelfDestructingSolverStorable1177,SelfDestructingSolverStorable950,SelfDestructingSolverStorable1055,SelfDestructingSolverStorable1176,SelfDestructingSolverStorable1021,SelfDestructingSolverStorable1142,SelfDestructingSolverStorable1020,SelfDestructingSolverStorable1141,SelfDestructingSolverStorable1140,SelfDestructingSolverStorable1029,SelfDestructingSolverStorable1028,SelfDestructingSolverStorable1149,SelfDestructingSolverStorable1027,SelfDestructingSolverStorable1148,SelfDestructingSolverStorable1026,SelfDestructingSolverStorable1147,SelfDestructingSolverStorable1025,SelfDestructingSolverStorable1146,SelfDestructingSolverStorable1024,SelfDestructingSolverStorable1145,SelfDestructingSolverStorable1023,SelfDestructingSolverStorable1144,SelfDestructingSolverStorable1022,SelfDestructingSolverStorable1143,SelfDestructingSolverStorable1032,SelfDestructingSolverStorable1153,SelfDestructingSolverStorable1031,SelfDestructingSolverStorable1152,SelfDestructingSolverStorable1030,SelfDestructingSolverStorable1151,SelfDestructingSolverStorable1150,SelfDestructingSolverStorable1039,SelfDestructingSolverStorable1038,SelfDestructingSolverStorable1159,SelfDestructingSolverStorable1037,SelfDestructingSolverStorable1158,SelfDestructingSolverStorable1036,SelfDestructingSolverStorable1157,SelfDestructingSolverStorable1035,SelfDestructingSolverStorable1156,SelfDestructingSolverStorable1034,SelfDestructingSolverStorable1155,SelfDestructingSolverStorable1033,SelfDestructingSolverStorable1154,SelfDestructingSolverStorable1120,SelfDestructingSolverStorable926,SelfDestructingSolverStorable927,SelfDestructingSolverStorable928,SelfDestructingSolverStorable929,SelfDestructingSolverStorable922,SelfDestructingSolverStorable923,SelfDestructingSolverStorable924,SelfDestructingSolverStorable1009,SelfDestructingSolverStorable925,SelfDestructingSolverStorable1008,SelfDestructingSolverStorable1129,SelfDestructingSolverStorable1007,SelfDestructingSolverStorable1128,SelfDestructingSolverStorable1006,SelfDestructingSolverStorable1127,SelfDestructingSolverStorable920,SelfDestructingSolverStorable1005,SelfDestructingSolverStorable1126,SelfDestructingSolverStorable921,SelfDestructingSolverStorable1004,SelfDestructingSolverStorable1125,SelfDestructingSolverStorable1003,SelfDestructingSolverStorable1124,SelfDestructingSolverStorable1002,SelfDestructingSolverStorable1123,SelfDestructingSolverStorable1001,SelfDestructingSolverStorable1122,SelfDestructingSolverStorable1000,SelfDestructingSolverStorable1121,SelfDestructingSolverStorable1010,SelfDestructingSolverStorable1131,SelfDestructingSolverStorable1130,SelfDestructingSolverStorable919,SelfDestructingSolverStorable918,SelfDestructingSolverStorable1019,SelfDestructingSolverStorable1018,SelfDestructingSolverStorable1139,SelfDestructingSolverStorable1017,SelfDestructingSolverStorable1138,SelfDestructingSolverStorable1016,SelfDestructingSolverStorable1137,SelfDestructingSolverStorable1015,SelfDestructingSolverStorable1136,SelfDestructingSolverStorable1014,SelfDestructingSolverStorable1135,SelfDestructingSolverStorable1013,SelfDestructingSolverStorable1134,SelfDestructingSolverStorable1012,SelfDestructingSolverStorable1133,SelfDestructingSolverStorable1011,SelfDestructingSolverStorable1132 [2024-05-06 18:29:25,567 WARN L619 AbstractCegarLoop]: Verification canceled: while PolyPacSimplificationTermWalker was simplifying a ∨-3-2-2-1 term,while PolyPacSimplificationTermWalker was simplifying 2 xjuncts wrt. a ∧-3-2-1 context. [2024-05-06 18:29:25,569 INFO L805 garLoopResultBuilder]: Registering result TIMEOUT for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (3 of 4 remaining) [2024-05-06 18:29:25,569 INFO L805 garLoopResultBuilder]: Registering result TIMEOUT for location ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (2 of 4 remaining) [2024-05-06 18:29:25,569 INFO L805 garLoopResultBuilder]: Registering result TIMEOUT for location ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (1 of 4 remaining) [2024-05-06 18:29:25,569 INFO L805 garLoopResultBuilder]: Registering result TIMEOUT for location ULTIMATE.startErr2INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (0 of 4 remaining) [2024-05-06 18:29:25,579 INFO L448 BasicCegarLoop]: Path program histogram: [396, 42, 30, 30, 30, 30, 30, 18, 10, 6, 6, 6, 6, 6, 2, 2, 1, 1] [2024-05-06 18:29:25,580 FATAL L? ?]: The Plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction has thrown an exception: java.lang.AssertionError: clock still running: ConditionalCommutativityCheckTime at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.CegarLoopStatisticsGenerator.getValue(CegarLoopStatisticsGenerator.java:172) at de.uni_freiburg.informatik.ultimate.util.statistics.StatisticsData.aggregateBenchmarkData(StatisticsData.java:60) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.executeCegarLoop(TraceAbstractionStarter.java:418) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.analyseProgram(TraceAbstractionStarter.java:302) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.analyseConcurrentProgram(TraceAbstractionStarter.java:225) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.runCegarLoops(TraceAbstractionStarter.java:173) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.(TraceAbstractionStarter.java:154) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver.finish(TraceAbstractionObserver.java:124) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:167) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:150) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:127) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:233) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:227) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:144) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:106) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:319) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.run(DefaultToolchainJob.java:145) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:63) [2024-05-06 18:29:25,595 INFO L158 Benchmark]: Toolchain (without parser) took 714298.77ms. Allocated memory was 254.8MB in the beginning and 3.7GB in the end (delta: 3.4GB). Free memory was 182.7MB in the beginning and 796.9MB in the end (delta: -614.3MB). Peak memory consumption was 2.8GB. Max. memory is 8.0GB. [2024-05-06 18:29:25,596 INFO L158 Benchmark]: CDTParser took 0.09ms. Allocated memory is still 180.4MB. Free memory is still 145.4MB. There was no memory consumed. Max. memory is 8.0GB. [2024-05-06 18:29:25,596 INFO L158 Benchmark]: CACSL2BoogieTranslator took 222.94ms. Allocated memory is still 254.8MB. Free memory was 182.5MB in the beginning and 220.5MB in the end (delta: -38.0MB). Peak memory consumption was 14.1MB. Max. memory is 8.0GB. [2024-05-06 18:29:25,596 INFO L158 Benchmark]: Boogie Procedure Inliner took 30.03ms. Allocated memory is still 254.8MB. Free memory was 220.5MB in the beginning and 218.4MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 8.0GB. [2024-05-06 18:29:25,596 INFO L158 Benchmark]: Boogie Preprocessor took 29.80ms. Allocated memory is still 254.8MB. Free memory was 218.4MB in the beginning and 216.3MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 8.0GB. [2024-05-06 18:29:25,596 INFO L158 Benchmark]: RCFGBuilder took 429.77ms. Allocated memory is still 254.8MB. Free memory was 216.3MB in the beginning and 192.2MB in the end (delta: 24.1MB). Peak memory consumption was 24.1MB. Max. memory is 8.0GB. [2024-05-06 18:29:25,597 INFO L158 Benchmark]: TraceAbstraction took 713582.10ms. Allocated memory was 254.8MB in the beginning and 3.7GB in the end (delta: 3.4GB). Free memory was 191.1MB in the beginning and 796.9MB in the end (delta: -605.8MB). Peak memory consumption was 2.8GB. Max. memory is 8.0GB. [2024-05-06 18:29:25,597 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.09ms. Allocated memory is still 180.4MB. Free memory is still 145.4MB. There was no memory consumed. Max. memory is 8.0GB. * CACSL2BoogieTranslator took 222.94ms. Allocated memory is still 254.8MB. Free memory was 182.5MB in the beginning and 220.5MB in the end (delta: -38.0MB). Peak memory consumption was 14.1MB. Max. memory is 8.0GB. * Boogie Procedure Inliner took 30.03ms. Allocated memory is still 254.8MB. Free memory was 220.5MB in the beginning and 218.4MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 8.0GB. * Boogie Preprocessor took 29.80ms. Allocated memory is still 254.8MB. Free memory was 218.4MB in the beginning and 216.3MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 8.0GB. * RCFGBuilder took 429.77ms. Allocated memory is still 254.8MB. Free memory was 216.3MB in the beginning and 192.2MB in the end (delta: 24.1MB). Peak memory consumption was 24.1MB. Max. memory is 8.0GB. * TraceAbstraction took 713582.10ms. Allocated memory was 254.8MB in the beginning and 3.7GB in the end (delta: 3.4GB). Free memory was 191.1MB in the beginning and 796.9MB in the end (delta: -605.8MB). Peak memory consumption was 2.8GB. Max. memory is 8.0GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Independence relation #1 benchmarks ThreadSeparatingIndependenceRelation.Independence Queries: [ total: 100371, independent: 95364, independent conditional: 51171, independent unconditional: 44193, dependent: 5007, dependent conditional: 4347, dependent unconditional: 660, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ThreadSeparatingIndependenceRelation.Statistics on underlying relation: UnionIndependenceRelation.Independence Queries: [ total: 96680, independent: 95364, independent conditional: 51171, independent unconditional: 44193, dependent: 1316, dependent conditional: 656, dependent unconditional: 660, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , UnionIndependenceRelation.Statistics on underlying relations: [ ConditionTransformingIndependenceRelation.Independence Queries: [ total: 96680, independent: 95364, independent conditional: 51171, independent unconditional: 44193, dependent: 1316, dependent conditional: 656, dependent unconditional: 660, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ConditionTransformingIndependenceRelation.Statistics on underlying relation: DisjunctiveConditionalIndependenceRelation.Independence Queries: [ total: 96680, independent: 95364, independent conditional: 51171, independent unconditional: 44193, dependent: 1316, dependent conditional: 656, dependent unconditional: 660, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , DisjunctiveConditionalIndependenceRelation.Statistics on underlying relation: ConditionTransformingIndependenceRelation.Independence Queries: [ total: 98652, independent: 95364, independent conditional: 2461, independent unconditional: 92903, dependent: 3288, dependent conditional: 656, dependent unconditional: 2632, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ConditionTransformingIndependenceRelation.Statistics on underlying relation: SemanticConditionEliminator.Independence Queries: [ total: 98652, independent: 95364, independent conditional: 763, independent unconditional: 94601, dependent: 3288, dependent conditional: 0, dependent unconditional: 3288, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , SemanticConditionEliminator.Statistics on underlying relation: CachedIndependenceRelation.Independence Queries: [ total: 98652, independent: 95364, independent conditional: 763, independent unconditional: 94601, dependent: 3288, dependent conditional: 0, dependent unconditional: 3288, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , CachedIndependenceRelation.Statistics on underlying relation: UnionIndependenceRelation.Independence Queries: [ total: 1540, independent: 1504, independent conditional: 0, independent unconditional: 1504, dependent: 36, dependent conditional: 0, dependent unconditional: 36, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , UnionIndependenceRelation.Statistics on underlying relations: [ SyntacticIndependenceRelation.Independence Queries: [ total: 1540, independent: 1504, independent conditional: 0, independent unconditional: 1504, dependent: 36, dependent conditional: 0, dependent unconditional: 36, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ProtectedIndependenceRelation.Independence Queries: [ total: 36, independent: 0, independent conditional: 0, independent unconditional: 0, dependent: 36, dependent conditional: 0, dependent unconditional: 36, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ProtectedIndependenceRelation.Statistics on underlying relation: SemanticIndependenceRelation.Independence Queries: [ total: 36, independent: 0, independent conditional: 0, independent unconditional: 0, dependent: 36, dependent conditional: 0, dependent unconditional: 36, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , SemanticIndependenceRelation.Query Time [ms]: [ total: 89, independent: 0, independent conditional: 0, independent unconditional: 0, dependent: 89, dependent conditional: 0, dependent unconditional: 89, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , Protected Queries: 0 ], Cache Queries: [ total: 98652, independent: 93860, independent conditional: 763, independent unconditional: 93097, dependent: 3252, dependent conditional: 0, dependent unconditional: 3252, unknown: 1540, unknown conditional: 0, unknown unconditional: 1540] , Statistics on independence cache: Total cache size (in pairs): 1540, Positive cache size: 1504, Positive conditional cache size: 0, Positive unconditional cache size: 1504, Negative cache size: 36, Negative conditional cache size: 0, Negative unconditional cache size: 36, Unknown cache size: 0, Unknown conditional cache size: 0, Unknown unconditional cache size: 0, Eliminated conditions: 2354, Maximal queried relation: 1, ConditionTransformingIndependenceRelation.Independence Queries: [ total: 98652, independent: 95364, independent conditional: 2461, independent unconditional: 92903, dependent: 3288, dependent conditional: 656, dependent unconditional: 2632, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ConditionTransformingIndependenceRelation.Statistics on underlying relation: SemanticConditionEliminator.Independence Queries: [ total: 98652, independent: 95364, independent conditional: 763, independent unconditional: 94601, dependent: 3288, dependent conditional: 0, dependent unconditional: 3288, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , SemanticConditionEliminator.Statistics on underlying relation: CachedIndependenceRelation.Independence Queries: [ total: 98652, independent: 95364, independent conditional: 763, independent unconditional: 94601, dependent: 3288, dependent conditional: 0, dependent unconditional: 3288, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , CachedIndependenceRelation.Statistics on underlying relation: UnionIndependenceRelation.Independence Queries: [ total: 1540, independent: 1504, independent conditional: 0, independent unconditional: 1504, dependent: 36, dependent conditional: 0, dependent unconditional: 36, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , UnionIndependenceRelation.Statistics on underlying relations: [ SyntacticIndependenceRelation.Independence Queries: [ total: 1540, independent: 1504, independent conditional: 0, independent unconditional: 1504, dependent: 36, dependent conditional: 0, dependent unconditional: 36, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ProtectedIndependenceRelation.Independence Queries: [ total: 36, independent: 0, independent conditional: 0, independent unconditional: 0, dependent: 36, dependent conditional: 0, dependent unconditional: 36, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ProtectedIndependenceRelation.Statistics on underlying relation: SemanticIndependenceRelation.Independence Queries: [ total: 36, independent: 0, independent conditional: 0, independent unconditional: 0, dependent: 36, dependent conditional: 0, dependent unconditional: 36, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , SemanticIndependenceRelation.Query Time [ms]: [ total: 89, independent: 0, independent conditional: 0, independent unconditional: 0, dependent: 89, dependent conditional: 0, dependent unconditional: 89, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , Protected Queries: 0 ], Cache Queries: [ total: 98652, independent: 93860, independent conditional: 763, independent unconditional: 93097, dependent: 3252, dependent conditional: 0, dependent unconditional: 3252, unknown: 1540, unknown conditional: 0, unknown unconditional: 1540] , Statistics on independence cache: Total cache size (in pairs): 1540, Positive cache size: 1504, Positive conditional cache size: 0, Positive unconditional cache size: 1504, Negative cache size: 36, Negative conditional cache size: 0, Negative unconditional cache size: 36, Unknown cache size: 0, Unknown conditional cache size: 0, Unknown unconditional cache size: 0, Eliminated conditions: 2354 ], Independence queries for same thread: 3691 - ExceptionOrErrorResult: AssertionError: clock still running: ConditionalCommutativityCheckTime de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: AssertionError: clock still running: ConditionalCommutativityCheckTime: de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.CegarLoopStatisticsGenerator.getValue(CegarLoopStatisticsGenerator.java:172) RESULT: Ultimate could not prove your program: Toolchain returned no result. Completed graceful shutdown