/root/.sdkman/candidates/java/current/bin/java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data -s ../benchexec/../../../trunk/examples/settings/gemcutter/NewStatesSleep.epf --traceabstraction.dfs.order.used.in.por LOOP_LOCKSTEP --traceabstraction.additional.conditional.commutativity.checking DFS --traceabstraction.criterion.for.conditional.commutativity.checking DEFAULT -tc ../benchexec/../../../trunk/examples/toolchains/AutomizerCInline.xml -i ../../../trunk/examples/svcomp/weaver/popl20-more-buffer-mult.wvr.c -------------------------------------------------------------------------------- This is Ultimate 0.2.4-wip.dk.conditional-comm-17da818-m [2024-05-06 04:00:09,189 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-05-06 04:00:09,220 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/../benchexec/../../../trunk/examples/settings/gemcutter/NewStatesSleep.epf [2024-05-06 04:00:09,223 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-05-06 04:00:09,224 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-05-06 04:00:09,236 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-05-06 04:00:09,237 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-05-06 04:00:09,237 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-05-06 04:00:09,237 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2024-05-06 04:00:09,238 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2024-05-06 04:00:09,238 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-05-06 04:00:09,238 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-05-06 04:00:09,239 INFO L153 SettingsManager]: * Use SBE=true [2024-05-06 04:00:09,239 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-05-06 04:00:09,239 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2024-05-06 04:00:09,239 INFO L153 SettingsManager]: * sizeof long=4 [2024-05-06 04:00:09,240 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-05-06 04:00:09,240 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-05-06 04:00:09,240 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-05-06 04:00:09,240 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2024-05-06 04:00:09,240 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2024-05-06 04:00:09,241 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2024-05-06 04:00:09,241 INFO L153 SettingsManager]: * sizeof long double=12 [2024-05-06 04:00:09,241 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-05-06 04:00:09,242 INFO L153 SettingsManager]: * Use constant arrays=true [2024-05-06 04:00:09,242 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-05-06 04:00:09,242 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-05-06 04:00:09,242 INFO L153 SettingsManager]: * To the following directory=./dump/ [2024-05-06 04:00:09,242 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-05-06 04:00:09,243 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2024-05-06 04:00:09,243 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-05-06 04:00:09,243 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2024-05-06 04:00:09,243 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2024-05-06 04:00:09,244 INFO L153 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2024-05-06 04:00:09,244 INFO L153 SettingsManager]: * Partial Order Reduction in concurrent analysis=SLEEP_NEW_STATES [2024-05-06 04:00:09,244 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2024-05-06 04:00:09,244 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-05-06 04:00:09,244 INFO L153 SettingsManager]: * Automaton type used in concurrency analysis=PARTIAL_ORDER_FA [2024-05-06 04:00:09,245 INFO L153 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2024-05-06 04:00:09,245 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: DFS Order used in POR -> LOOP_LOCKSTEP Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Additional conditional commutativity checking -> DFS Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: Criterion for conditional commutativity checking -> DEFAULT [2024-05-06 04:00:09,468 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-05-06 04:00:09,486 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-05-06 04:00:09,488 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-05-06 04:00:09,489 INFO L270 PluginConnector]: Initializing CDTParser... [2024-05-06 04:00:09,497 INFO L274 PluginConnector]: CDTParser initialized [2024-05-06 04:00:09,498 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/../../../trunk/examples/svcomp/weaver/popl20-more-buffer-mult.wvr.c [2024-05-06 04:00:10,676 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-05-06 04:00:10,847 INFO L384 CDTParser]: Found 1 translation units. [2024-05-06 04:00:10,848 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/weaver/popl20-more-buffer-mult.wvr.c [2024-05-06 04:00:10,860 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/data/5795d4b87/ca5a4aeae9824e0f9c8b667a89fc1581/FLAG8085ff9fd [2024-05-06 04:00:10,873 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/data/5795d4b87/ca5a4aeae9824e0f9c8b667a89fc1581 [2024-05-06 04:00:10,876 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-05-06 04:00:10,878 INFO L133 ToolchainWalker]: Walking toolchain with 5 elements. [2024-05-06 04:00:10,880 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-05-06 04:00:10,880 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-05-06 04:00:10,883 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-05-06 04:00:10,884 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.05 04:00:10" (1/1) ... [2024-05-06 04:00:10,885 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@777ffccf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 04:00:10, skipping insertion in model container [2024-05-06 04:00:10,885 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.05 04:00:10" (1/1) ... [2024-05-06 04:00:10,921 INFO L177 MainTranslator]: Built tables and reachable declarations [2024-05-06 04:00:11,082 WARN L240 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/weaver/popl20-more-buffer-mult.wvr.c[4218,4231] [2024-05-06 04:00:11,089 INFO L209 PostProcessor]: Analyzing one entry point: main [2024-05-06 04:00:11,095 INFO L202 MainTranslator]: Completed pre-run [2024-05-06 04:00:11,115 WARN L240 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/weaver/popl20-more-buffer-mult.wvr.c[4218,4231] [2024-05-06 04:00:11,118 INFO L209 PostProcessor]: Analyzing one entry point: main [2024-05-06 04:00:11,125 WARN L675 CHandler]: The function __VERIFIER_atomic_begin is called, but not defined or handled by StandardFunctionHandler. [2024-05-06 04:00:11,125 WARN L675 CHandler]: The function __VERIFIER_atomic_end is called, but not defined or handled by StandardFunctionHandler. [2024-05-06 04:00:11,131 INFO L206 MainTranslator]: Completed translation [2024-05-06 04:00:11,131 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 04:00:11 WrapperNode [2024-05-06 04:00:11,131 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-05-06 04:00:11,132 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-05-06 04:00:11,132 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-05-06 04:00:11,132 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-05-06 04:00:11,137 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 04:00:11" (1/1) ... [2024-05-06 04:00:11,147 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 04:00:11" (1/1) ... [2024-05-06 04:00:11,176 INFO L138 Inliner]: procedures = 27, calls = 80, calls flagged for inlining = 18, calls inlined = 22, statements flattened = 316 [2024-05-06 04:00:11,176 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-05-06 04:00:11,177 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-05-06 04:00:11,177 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-05-06 04:00:11,177 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-05-06 04:00:11,183 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 04:00:11" (1/1) ... [2024-05-06 04:00:11,184 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 04:00:11" (1/1) ... [2024-05-06 04:00:11,186 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 04:00:11" (1/1) ... [2024-05-06 04:00:11,186 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 04:00:11" (1/1) ... [2024-05-06 04:00:11,193 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 04:00:11" (1/1) ... [2024-05-06 04:00:11,195 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 04:00:11" (1/1) ... [2024-05-06 04:00:11,197 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 04:00:11" (1/1) ... [2024-05-06 04:00:11,198 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 04:00:11" (1/1) ... [2024-05-06 04:00:11,200 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-05-06 04:00:11,201 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-05-06 04:00:11,201 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-05-06 04:00:11,201 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-05-06 04:00:11,201 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 04:00:11" (1/1) ... [2024-05-06 04:00:11,205 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2024-05-06 04:00:11,215 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 04:00:11,226 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2024-05-06 04:00:11,292 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2024-05-06 04:00:11,308 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-05-06 04:00:11,308 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2024-05-06 04:00:11,308 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2024-05-06 04:00:11,308 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2024-05-06 04:00:11,309 INFO L130 BoogieDeclarations]: Found specification of procedure thread1 [2024-05-06 04:00:11,309 INFO L138 BoogieDeclarations]: Found implementation of procedure thread1 [2024-05-06 04:00:11,309 INFO L130 BoogieDeclarations]: Found specification of procedure thread2 [2024-05-06 04:00:11,309 INFO L138 BoogieDeclarations]: Found implementation of procedure thread2 [2024-05-06 04:00:11,309 INFO L130 BoogieDeclarations]: Found specification of procedure thread3 [2024-05-06 04:00:11,309 INFO L138 BoogieDeclarations]: Found implementation of procedure thread3 [2024-05-06 04:00:11,310 INFO L130 BoogieDeclarations]: Found specification of procedure thread4 [2024-05-06 04:00:11,311 INFO L138 BoogieDeclarations]: Found implementation of procedure thread4 [2024-05-06 04:00:11,311 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2024-05-06 04:00:11,311 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_end [2024-05-06 04:00:11,311 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_atomic_begin [2024-05-06 04:00:11,311 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2024-05-06 04:00:11,312 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-05-06 04:00:11,312 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-05-06 04:00:11,312 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2024-05-06 04:00:11,313 WARN L213 CfgBuilder]: User set CodeBlockSize to SequenceOfStatements but program contains fork statements. Overwriting the user preferences and setting CodeBlockSize to OneNontrivialStatement [2024-05-06 04:00:11,433 INFO L241 CfgBuilder]: Building ICFG [2024-05-06 04:00:11,435 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2024-05-06 04:00:11,770 INFO L282 CfgBuilder]: Performing block encoding [2024-05-06 04:00:11,893 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-05-06 04:00:11,894 INFO L309 CfgBuilder]: Removed 6 assume(true) statements. [2024-05-06 04:00:11,895 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.05 04:00:11 BoogieIcfgContainer [2024-05-06 04:00:11,895 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-05-06 04:00:11,897 INFO L112 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2024-05-06 04:00:11,897 INFO L270 PluginConnector]: Initializing TraceAbstraction... [2024-05-06 04:00:11,899 INFO L274 PluginConnector]: TraceAbstraction initialized [2024-05-06 04:00:11,899 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 06.05 04:00:10" (1/3) ... [2024-05-06 04:00:11,900 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@400fe040 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.05 04:00:11, skipping insertion in model container [2024-05-06 04:00:11,900 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.05 04:00:11" (2/3) ... [2024-05-06 04:00:11,900 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@400fe040 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.05 04:00:11, skipping insertion in model container [2024-05-06 04:00:11,900 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.05 04:00:11" (3/3) ... [2024-05-06 04:00:11,901 INFO L112 eAbstractionObserver]: Analyzing ICFG popl20-more-buffer-mult.wvr.c [2024-05-06 04:00:11,906 WARN L145 ceAbstractionStarter]: Switching off computation of Hoare annotation because input is a concurrent program [2024-05-06 04:00:11,913 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2024-05-06 04:00:11,913 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2024-05-06 04:00:11,913 INFO L514 ceAbstractionStarter]: Constructing petrified ICFG for 1 thread instances. [2024-05-06 04:00:11,960 INFO L144 ThreadInstanceAdder]: Constructed 4 joinOtherThreadTransitions. [2024-05-06 04:00:11,990 INFO L100 denceProviderFactory]: Independence Relation #1: [IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=true, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2024-05-06 04:00:11,990 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 [2024-05-06 04:00:11,990 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 04:00:11,992 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 (exit command is (exit), workingDir is null) [2024-05-06 04:00:11,997 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 (2)] Waiting until timeout for monitored process [2024-05-06 04:00:12,046 INFO L188 artialOrderCegarLoop]: Running PartialOrderCegarLoop with 1 independence relations. [2024-05-06 04:00:12,068 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 04:00:12,070 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2024-05-06 04:00:12,075 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=PARTIAL_ORDER_FA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopHeads, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@34ff74fa, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms], mConComChecker=DFS, mConComCheckerCriterion=DEFAULT, mConComCheckerLimitedChecksCriterion=false, mConComCheckerCriterionLimit=1, mConComCheckerRandomProb=100, mConComCheckerRandomSeed=123, mConComCheckerConditionCriterion=false [2024-05-06 04:00:12,075 INFO L358 AbstractCegarLoop]: Starting to check reachability of 5 error locations. [2024-05-06 04:00:12,586 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:00:12,639 INFO L85 PathProgramCache]: Analyzing trace with hash -1264897234, now seen corresponding path program 1 times [2024-05-06 04:00:12,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:12,643 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:12,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:12,965 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 04:00:12,966 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:12,966 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:13,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:13,055 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 04:00:13,078 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-05-06 04:00:13,079 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-05-06 04:00:13,274 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:00:13,331 INFO L85 PathProgramCache]: Analyzing trace with hash 750604411, now seen corresponding path program 1 times [2024-05-06 04:00:13,332 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:13,332 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:13,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:13,707 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-06 04:00:13,707 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:13,707 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:13,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:13,887 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-06 04:00:13,887 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-05-06 04:00:13,888 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2024-05-06 04:00:14,157 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:00:14,198 INFO L85 PathProgramCache]: Analyzing trace with hash -476508331, now seen corresponding path program 1 times [2024-05-06 04:00:14,198 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:14,198 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:14,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:14,392 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-06 04:00:14,392 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:14,392 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:14,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:14,510 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-06 04:00:14,511 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-05-06 04:00:14,511 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=143, Unknown=0, NotChecked=0, Total=182 [2024-05-06 04:00:14,701 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:00:14,748 INFO L85 PathProgramCache]: Analyzing trace with hash -1585306233, now seen corresponding path program 1 times [2024-05-06 04:00:14,749 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:14,749 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:14,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:15,004 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:00:15,004 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:15,004 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:15,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:15,158 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:00:15,232 INFO L85 PathProgramCache]: Analyzing trace with hash -1899852116, now seen corresponding path program 2 times [2024-05-06 04:00:15,233 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:15,233 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:15,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:15,413 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:00:15,414 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:15,414 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:15,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:15,567 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:00:15,714 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:00:15,765 INFO L85 PathProgramCache]: Analyzing trace with hash 352895570, now seen corresponding path program 1 times [2024-05-06 04:00:15,765 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:15,766 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:15,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:15,940 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:00:15,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:15,940 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:15,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:16,156 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:00:16,249 INFO L85 PathProgramCache]: Analyzing trace with hash -1945138376, now seen corresponding path program 2 times [2024-05-06 04:00:16,249 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:16,249 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:16,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:16,434 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:00:16,434 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:16,435 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:16,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:16,692 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:00:16,804 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:00:16,842 INFO L85 PathProgramCache]: Analyzing trace with hash 709174153, now seen corresponding path program 3 times [2024-05-06 04:00:16,842 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:16,843 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:16,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:17,097 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:00:17,098 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:17,098 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:17,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:17,316 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:00:17,395 INFO L85 PathProgramCache]: Analyzing trace with hash 509563105, now seen corresponding path program 4 times [2024-05-06 04:00:17,395 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:17,395 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:17,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:17,626 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:00:17,626 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:17,626 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:17,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:17,871 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:00:18,122 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:00:18,123 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:00:18,818 INFO L85 PathProgramCache]: Analyzing trace with hash -891221064, now seen corresponding path program 5 times [2024-05-06 04:00:18,818 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:18,818 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:18,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:19,091 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 04:00:19,091 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:19,091 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:19,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:19,300 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 04:00:19,586 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:00:19,586 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:00:26,619 INFO L85 PathProgramCache]: Analyzing trace with hash 1277604235, now seen corresponding path program 6 times [2024-05-06 04:00:26,620 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:26,620 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:26,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:26,820 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:00:26,821 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:26,821 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:26,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:27,093 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:00:27,161 INFO L85 PathProgramCache]: Analyzing trace with hash -2080372961, now seen corresponding path program 7 times [2024-05-06 04:00:27,161 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:27,161 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:27,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:27,401 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:00:27,401 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:27,402 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:27,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:27,641 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:00:27,765 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:00:27,765 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 04:00:27,954 INFO L85 PathProgramCache]: Analyzing trace with hash 1173252875, now seen corresponding path program 8 times [2024-05-06 04:00:27,954 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:27,955 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:27,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:28,197 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 04:00:28,197 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:28,198 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:28,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:28,482 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 04:00:28,612 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:00:28,651 INFO L85 PathProgramCache]: Analyzing trace with hash 2011101617, now seen corresponding path program 9 times [2024-05-06 04:00:28,651 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:28,651 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:28,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:28,909 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 04:00:28,909 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:28,909 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:28,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:29,159 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 04:00:29,284 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:00:29,328 INFO L85 PathProgramCache]: Analyzing trace with hash -2121681854, now seen corresponding path program 10 times [2024-05-06 04:00:29,328 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:29,328 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:29,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:29,596 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:00:29,597 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:29,597 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:29,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:29,796 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:00:29,855 INFO L85 PathProgramCache]: Analyzing trace with hash -1347627192, now seen corresponding path program 11 times [2024-05-06 04:00:29,855 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:29,856 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:29,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:30,046 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:00:30,046 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:30,046 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:30,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:30,239 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:00:30,359 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:00:30,359 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 04:00:31,344 INFO L85 PathProgramCache]: Analyzing trace with hash -2008104048, now seen corresponding path program 12 times [2024-05-06 04:00:31,345 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:31,345 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:31,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:31,553 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:00:31,553 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:31,553 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:31,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:31,743 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:00:31,980 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:00:31,980 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:00:32,481 INFO L85 PathProgramCache]: Analyzing trace with hash 967718707, now seen corresponding path program 13 times [2024-05-06 04:00:32,481 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:32,481 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:32,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:32,725 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:00:32,725 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:32,725 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:32,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:32,906 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:00:33,003 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:00:33,034 INFO L85 PathProgramCache]: Analyzing trace with hash -2030198306, now seen corresponding path program 14 times [2024-05-06 04:00:33,034 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:33,035 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:33,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:33,212 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:00:33,213 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:33,213 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:33,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:33,386 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:00:33,442 INFO L85 PathProgramCache]: Analyzing trace with hash 1488362796, now seen corresponding path program 15 times [2024-05-06 04:00:33,442 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:33,443 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:33,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:33,692 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:00:33,693 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:33,693 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:33,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:33,953 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:00:34,192 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:00:34,193 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:00:34,689 INFO L85 PathProgramCache]: Analyzing trace with hash 92564967, now seen corresponding path program 16 times [2024-05-06 04:00:34,689 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:34,689 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:34,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:34,879 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:00:34,880 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:34,880 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:34,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:35,077 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:00:35,139 INFO L85 PathProgramCache]: Analyzing trace with hash -1425452459, now seen corresponding path program 17 times [2024-05-06 04:00:35,139 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:35,139 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:35,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:35,376 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:00:35,376 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:35,376 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:35,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:35,543 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:00:35,599 INFO L85 PathProgramCache]: Analyzing trace with hash -1239352401, now seen corresponding path program 18 times [2024-05-06 04:00:35,599 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:35,599 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:35,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:35,762 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:00:35,762 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:35,763 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:35,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:35,994 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:00:36,054 INFO L85 PathProgramCache]: Analyzing trace with hash 234782103, now seen corresponding path program 19 times [2024-05-06 04:00:36,055 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:36,055 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:36,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:36,278 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:00:36,278 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:36,278 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:36,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:36,439 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:00:36,579 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:00:36,580 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 04:00:36,739 INFO L85 PathProgramCache]: Analyzing trace with hash -65490316, now seen corresponding path program 20 times [2024-05-06 04:00:36,740 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:36,740 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:36,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:36,912 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:00:36,913 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:36,913 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:36,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:37,058 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:00:37,283 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:00:37,283 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:00:37,882 INFO L85 PathProgramCache]: Analyzing trace with hash -2030198954, now seen corresponding path program 21 times [2024-05-06 04:00:37,882 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:37,882 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:37,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:38,026 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:00:38,026 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:38,026 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:38,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:38,167 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:00:38,222 INFO L85 PathProgramCache]: Analyzing trace with hash 1488342726, now seen corresponding path program 22 times [2024-05-06 04:00:38,222 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:38,222 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:38,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:38,366 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:00:38,366 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:38,367 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:38,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:38,510 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:00:38,564 INFO L85 PathProgramCache]: Analyzing trace with hash -1106014882, now seen corresponding path program 23 times [2024-05-06 04:00:38,564 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:38,565 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:38,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:38,785 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:00:38,786 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:38,786 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:38,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:38,971 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:00:39,031 INFO L85 PathProgramCache]: Analyzing trace with hash 73277896, now seen corresponding path program 24 times [2024-05-06 04:00:39,032 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:39,032 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:39,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:39,186 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:00:39,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:39,186 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:39,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:39,334 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:00:39,450 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:00:39,451 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 04:00:39,586 INFO L85 PathProgramCache]: Analyzing trace with hash 2020603108, now seen corresponding path program 1 times [2024-05-06 04:00:39,587 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:39,587 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:39,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:39,736 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 04:00:39,736 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:39,736 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:39,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:39,887 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 04:00:40,045 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:00:40,083 INFO L85 PathProgramCache]: Analyzing trace with hash -1785812232, now seen corresponding path program 2 times [2024-05-06 04:00:40,083 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:40,083 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:40,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:40,237 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 04:00:40,238 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:40,238 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:40,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:40,397 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 04:00:40,494 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:00:40,537 INFO L85 PathProgramCache]: Analyzing trace with hash 2053496923, now seen corresponding path program 3 times [2024-05-06 04:00:40,537 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:40,538 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:40,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:40,686 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:00:40,686 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:40,686 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:40,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:40,834 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:00:40,887 INFO L85 PathProgramCache]: Analyzing trace with hash -766103985, now seen corresponding path program 4 times [2024-05-06 04:00:40,888 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:40,888 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:40,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:41,040 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:00:41,040 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:41,041 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:41,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:41,255 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:00:41,364 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:00:41,364 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 04:00:43,504 INFO L85 PathProgramCache]: Analyzing trace with hash -1180684201, now seen corresponding path program 5 times [2024-05-06 04:00:43,505 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:43,505 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:43,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:43,649 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:00:43,649 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:43,649 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:43,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:43,792 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:00:43,848 INFO L85 PathProgramCache]: Analyzing trace with hash -63797974, now seen corresponding path program 6 times [2024-05-06 04:00:43,848 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:43,849 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:43,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:43,988 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:00:43,989 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:43,989 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:44,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:44,128 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:00:44,183 INFO L85 PathProgramCache]: Analyzing trace with hash 221129471, now seen corresponding path program 1 times [2024-05-06 04:00:44,183 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:44,183 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:44,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:44,334 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:00:44,334 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:44,334 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:44,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:44,557 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:00:44,672 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:00:44,672 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 04:00:44,786 INFO L85 PathProgramCache]: Analyzing trace with hash 1108608747, now seen corresponding path program 2 times [2024-05-06 04:00:44,786 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:44,786 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:44,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:44,933 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 04:00:44,934 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:44,934 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:44,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:45,080 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 04:00:45,172 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:00:45,213 INFO L85 PathProgramCache]: Analyzing trace with hash 7133649, now seen corresponding path program 3 times [2024-05-06 04:00:45,214 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:45,214 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:45,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:45,365 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 04:00:45,365 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:45,365 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:45,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:45,524 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 04:00:45,625 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:00:45,657 INFO L85 PathProgramCache]: Analyzing trace with hash -1205549022, now seen corresponding path program 4 times [2024-05-06 04:00:45,657 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:45,657 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:45,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:45,945 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:00:45,945 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:45,945 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:45,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:46,130 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:00:46,192 INFO L85 PathProgramCache]: Analyzing trace with hash 1282686824, now seen corresponding path program 5 times [2024-05-06 04:00:46,193 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:46,193 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:46,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:46,354 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:00:46,354 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:46,354 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:46,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:46,498 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:00:46,614 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:00:46,614 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 04:00:46,752 INFO L85 PathProgramCache]: Analyzing trace with hash -1978551376, now seen corresponding path program 6 times [2024-05-06 04:00:46,752 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:46,752 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:46,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:46,897 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:00:46,898 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:46,898 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:46,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:47,040 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:00:47,102 INFO L85 PathProgramCache]: Analyzing trace with hash -1600833574, now seen corresponding path program 1 times [2024-05-06 04:00:47,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:47,103 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:47,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:47,257 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 04:00:47,257 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:47,257 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:47,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:47,514 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 04:00:47,628 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:00:47,629 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 04:00:47,761 INFO L85 PathProgramCache]: Analyzing trace with hash 637439622, now seen corresponding path program 2 times [2024-05-06 04:00:47,761 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:47,762 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:47,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:47,909 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 04:00:47,909 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:47,909 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:47,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:48,056 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 04:00:48,152 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:00:48,191 INFO L85 PathProgramCache]: Analyzing trace with hash -1714207338, now seen corresponding path program 3 times [2024-05-06 04:00:48,191 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:48,192 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:48,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:48,342 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 04:00:48,342 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:48,342 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:48,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:48,494 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 04:00:48,629 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:00:48,667 INFO L85 PathProgramCache]: Analyzing trace with hash -2001569155, now seen corresponding path program 4 times [2024-05-06 04:00:48,667 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:48,667 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:48,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:48,818 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:00:48,818 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:48,818 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:48,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:49,042 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:00:49,100 INFO L85 PathProgramCache]: Analyzing trace with hash -1919100819, now seen corresponding path program 5 times [2024-05-06 04:00:49,100 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:49,100 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:49,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:49,248 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:00:49,248 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:49,248 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:49,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:49,395 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:00:49,508 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:00:49,509 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 04:00:49,645 INFO L85 PathProgramCache]: Analyzing trace with hash -64566795, now seen corresponding path program 6 times [2024-05-06 04:00:49,646 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:49,646 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:49,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:49,788 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:00:49,788 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:49,788 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:49,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:49,932 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:00:49,989 INFO L85 PathProgramCache]: Analyzing trace with hash -154603358, now seen corresponding path program 25 times [2024-05-06 04:00:49,990 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:49,990 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:50,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:50,144 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 04:00:50,144 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:50,144 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:50,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:50,296 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 04:00:50,410 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:00:50,410 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 04:00:50,686 INFO L85 PathProgramCache]: Analyzing trace with hash 98163022, now seen corresponding path program 26 times [2024-05-06 04:00:50,687 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:50,687 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:50,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:50,833 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 04:00:50,833 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:50,833 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:50,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:50,980 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 04:00:51,076 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:00:51,111 INFO L85 PathProgramCache]: Analyzing trace with hash -1251912754, now seen corresponding path program 27 times [2024-05-06 04:00:51,111 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:51,111 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:51,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:51,262 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 04:00:51,262 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:51,263 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:51,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:51,423 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 04:00:51,553 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:00:51,588 INFO L85 PathProgramCache]: Analyzing trace with hash -84814011, now seen corresponding path program 28 times [2024-05-06 04:00:51,589 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:51,589 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:51,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:51,737 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:00:51,737 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:51,737 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:51,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:51,882 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:00:51,935 INFO L85 PathProgramCache]: Analyzing trace with hash 1665733797, now seen corresponding path program 29 times [2024-05-06 04:00:51,936 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:51,936 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:51,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:52,190 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:00:52,190 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:52,190 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:52,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:52,377 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:00:52,495 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:00:52,496 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 04:00:52,635 INFO L85 PathProgramCache]: Analyzing trace with hash 967095341, now seen corresponding path program 30 times [2024-05-06 04:00:52,635 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:52,635 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:52,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:52,815 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:00:52,815 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:00:52,815 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:00:52,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:00:52,962 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:00:53,175 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:00:53,175 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:01:01,757 WARN L854 $PredicateComparison]: unable to prove that (and (forall ((v_~q2~0.base_In_10 Int) (v_~q2~0.offset_In_10 Int)) (= (select (select |c_#memory_int| v_~q2~0.base_In_10) (+ (* c_~q2_front~0 4) v_~q2~0.offset_In_10)) 0)) (forall ((v_~q1~0.offset_In_30 Int) (v_~q1_front~0_In_49 Int) (v_~q1~0.base_In_30 Int)) (let ((.cse0 (select (select |c_#memory_int| v_~q1~0.base_In_30) (+ (* v_~q1_front~0_In_49 4) v_~q1~0.offset_In_30)))) (or (< 4294967295 .cse0) (= .cse0 0) (< (+ .cse0 4294967295) 0) (< v_~q1_front~0_In_49 0))))) is different from false [2024-05-06 04:01:01,760 INFO L85 PathProgramCache]: Analyzing trace with hash 1029788170, now seen corresponding path program 31 times [2024-05-06 04:01:01,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:01:01,760 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:01:01,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:01:01,986 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:01:01,986 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:01:01,986 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:01:02,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:01:02,165 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:01:02,305 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:01:02,305 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 04:01:02,463 INFO L85 PathProgramCache]: Analyzing trace with hash -531160901, now seen corresponding path program 32 times [2024-05-06 04:01:02,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:01:02,464 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:01:02,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:01:02,645 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:01:02,645 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:01:02,646 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:01:02,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:01:02,919 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:01:03,150 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:01:03,151 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:01:03,637 INFO L85 PathProgramCache]: Analyzing trace with hash 655509330, now seen corresponding path program 33 times [2024-05-06 04:01:03,638 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:01:03,638 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:01:03,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:01:03,787 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:01:03,787 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:01:03,787 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:01:03,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:01:03,935 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:01:03,992 INFO L85 PathProgramCache]: Analyzing trace with hash -1415698614, now seen corresponding path program 34 times [2024-05-06 04:01:03,992 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:01:03,992 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:01:04,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:01:04,145 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:01:04,146 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:01:04,146 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:01:04,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:01:04,294 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:01:04,514 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:01:04,515 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:01:07,229 INFO L85 PathProgramCache]: Analyzing trace with hash 713882118, now seen corresponding path program 35 times [2024-05-06 04:01:07,230 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:01:07,230 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:01:07,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:01:07,381 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:01:07,381 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:01:07,381 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:01:07,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:01:07,523 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:01:07,737 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:01:07,737 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 04:01:07,844 INFO L85 PathProgramCache]: Analyzing trace with hash 655510046, now seen corresponding path program 36 times [2024-05-06 04:01:07,844 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:01:07,844 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:01:07,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:01:07,986 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:01:07,987 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:01:07,987 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:01:08,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:01:08,130 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:01:08,223 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:01:08,253 INFO L85 PathProgramCache]: Analyzing trace with hash -1154024194, now seen corresponding path program 37 times [2024-05-06 04:01:08,254 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:01:08,254 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:01:08,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:01:08,396 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:01:08,397 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:01:08,397 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:01:08,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:01:08,545 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:01:08,715 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:01:08,715 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:01:14,237 WARN L293 SmtUtils]: Spent 5.07s on a formula simplification. DAG size of input: 33 DAG size of output: 14 (called from [L 210] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.abduction.Abducer.solveAbductionProblem) [2024-05-06 04:01:14,268 INFO L85 PathProgramCache]: Analyzing trace with hash 1916269675, now seen corresponding path program 1 times [2024-05-06 04:01:14,268 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:01:14,268 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:01:14,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:01:14,481 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:01:14,482 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:01:14,482 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:01:14,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:01:14,649 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:01:14,886 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:01:14,886 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:01:15,750 INFO L85 PathProgramCache]: Analyzing trace with hash 54284200, now seen corresponding path program 2 times [2024-05-06 04:01:15,750 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:01:15,751 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:01:15,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:01:15,907 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:01:15,908 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:01:15,910 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:01:15,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:01:16,069 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:01:16,289 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:01:16,289 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:01:16,815 INFO L85 PathProgramCache]: Analyzing trace with hash -908016158, now seen corresponding path program 1 times [2024-05-06 04:01:16,815 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:01:16,815 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:01:16,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:01:16,952 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:01:16,952 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:01:16,952 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:01:16,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:01:17,084 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:01:17,304 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:01:17,304 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:01:18,013 INFO L85 PathProgramCache]: Analyzing trace with hash 1276261393, now seen corresponding path program 2 times [2024-05-06 04:01:18,014 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:01:18,014 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:01:18,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:01:18,165 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:01:18,165 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:01:18,165 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:01:18,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:01:18,437 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:01:18,663 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:01:18,663 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:01:25,501 INFO L85 PathProgramCache]: Analyzing trace with hash -1414764145, now seen corresponding path program 1 times [2024-05-06 04:01:25,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:01:25,502 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:01:25,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:01:25,638 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:01:25,638 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:01:25,638 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:01:25,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:01:25,787 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:01:25,994 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:01:25,994 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:01:28,780 INFO L85 PathProgramCache]: Analyzing trace with hash 391078660, now seen corresponding path program 2 times [2024-05-06 04:01:28,781 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:01:28,781 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:01:28,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:01:28,939 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:01:28,939 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:01:28,939 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:01:28,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:01:29,114 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:01:29,348 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:01:29,349 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:01:30,222 INFO L85 PathProgramCache]: Analyzing trace with hash -1154016253, now seen corresponding path program 1 times [2024-05-06 04:01:30,222 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:01:30,222 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:01:30,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:01:30,367 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:01:30,367 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:01:30,368 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:01:30,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:01:30,518 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:01:30,755 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:01:30,755 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:01:31,564 INFO L85 PathProgramCache]: Analyzing trace with hash -1527500016, now seen corresponding path program 2 times [2024-05-06 04:01:31,564 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:01:31,564 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:01:31,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:01:31,736 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:01:31,736 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:01:31,736 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:01:31,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:01:31,884 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:01:32,102 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:01:32,102 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:01:34,774 INFO L85 PathProgramCache]: Analyzing trace with hash 655510322, now seen corresponding path program 1 times [2024-05-06 04:01:34,774 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:01:34,774 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:01:34,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:01:35,007 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:01:35,008 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:01:35,008 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:01:35,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:01:35,139 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:01:35,352 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:01:35,353 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:01:37,859 INFO L85 PathProgramCache]: Analyzing trace with hash -1262901055, now seen corresponding path program 2 times [2024-05-06 04:01:37,859 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:01:37,859 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:01:37,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:01:38,007 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:01:38,007 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:01:38,007 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:01:38,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:01:38,151 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:01:38,336 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:01:38,336 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:01:38,967 INFO L85 PathProgramCache]: Analyzing trace with hash 713882149, now seen corresponding path program 1 times [2024-05-06 04:01:38,967 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:01:38,967 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:01:38,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:01:39,105 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:01:39,106 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:01:39,106 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:01:39,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:01:39,235 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:01:39,409 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:01:39,410 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:01:39,947 INFO L85 PathProgramCache]: Analyzing trace with hash -954655954, now seen corresponding path program 2 times [2024-05-06 04:01:39,947 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:01:39,947 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:01:39,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:01:40,109 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:01:40,110 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:01:40,110 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:01:40,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:01:40,263 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:01:40,486 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:01:40,487 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:02:09,794 WARN L293 SmtUtils]: Spent 18.53s on a formula simplification. DAG size of input: 33 DAG size of output: 28 (called from [L 210] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.abduction.Abducer.solveAbductionProblem) [2024-05-06 04:02:11,802 WARN L854 $PredicateComparison]: unable to prove that (and (forall ((v_~q2~0.base_In_25 Int) (v_~q2~0.offset_In_25 Int)) (= (select (select |c_#memory_int| v_~q2~0.base_In_25) (+ (* c_~q2_front~0 4) v_~q2~0.offset_In_25)) 0)) (forall ((v_~q1_front~0_In_68 Int) (v_~q1~0.base_In_48 Int) (v_~q1~0.offset_In_48 Int)) (let ((.cse0 (select (select |c_#memory_int| v_~q1~0.base_In_48) (+ (* v_~q1_front~0_In_68 4) v_~q1~0.offset_In_48)))) (or (< v_~q1_front~0_In_68 0) (< 4294967295 .cse0) (< (+ .cse0 4294967295) 0) (= .cse0 0))))) is different from false [2024-05-06 04:02:11,803 INFO L85 PathProgramCache]: Analyzing trace with hash -531160875, now seen corresponding path program 38 times [2024-05-06 04:02:11,804 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:11,804 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:11,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:11,943 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:02:11,943 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:11,943 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:11,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:12,120 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:02:12,332 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:02:12,333 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:02:14,975 INFO L85 PathProgramCache]: Analyzing trace with hash -841516418, now seen corresponding path program 39 times [2024-05-06 04:02:14,976 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:14,976 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:14,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:15,250 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:02:15,250 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:15,250 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:15,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:15,399 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:02:15,526 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:02:15,526 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 04:02:15,669 INFO L85 PathProgramCache]: Analyzing trace with hash -1670724113, now seen corresponding path program 40 times [2024-05-06 04:02:15,670 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:15,670 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:15,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:15,794 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:02:15,794 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:15,794 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:15,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:15,915 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:02:16,004 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:02:16,043 INFO L85 PathProgramCache]: Analyzing trace with hash -252839091, now seen corresponding path program 41 times [2024-05-06 04:02:16,043 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:16,043 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:16,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:16,170 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:02:16,170 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:16,170 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:16,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:16,294 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:02:16,481 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:02:16,481 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:02:17,048 INFO L85 PathProgramCache]: Analyzing trace with hash 1044133257, now seen corresponding path program 42 times [2024-05-06 04:02:17,048 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:17,049 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:17,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:17,177 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:02:17,177 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:17,177 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:17,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:17,304 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:02:17,396 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:02:17,397 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 04:02:17,526 INFO L85 PathProgramCache]: Analyzing trace with hash 1044133257, now seen corresponding path program 43 times [2024-05-06 04:02:17,526 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:17,526 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:17,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:17,759 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:02:17,759 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:17,759 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:17,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:17,903 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:02:18,002 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:02:18,051 INFO L85 PathProgramCache]: Analyzing trace with hash -1991606541, now seen corresponding path program 44 times [2024-05-06 04:02:18,051 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:18,051 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:18,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:18,180 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:02:18,180 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:18,180 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:18,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:18,309 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:02:18,407 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:02:18,447 INFO L85 PathProgramCache]: Analyzing trace with hash -1610259759, now seen corresponding path program 45 times [2024-05-06 04:02:18,447 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:18,448 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:18,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:18,580 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:02:18,580 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:18,580 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:18,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:18,713 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:02:18,792 INFO L85 PathProgramCache]: Analyzing trace with hash -862134108, now seen corresponding path program 46 times [2024-05-06 04:02:18,792 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:18,792 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:18,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:18,910 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:02:18,910 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:18,910 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:18,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:19,028 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:02:19,086 INFO L85 PathProgramCache]: Analyzing trace with hash 707997994, now seen corresponding path program 47 times [2024-05-06 04:02:19,086 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:19,087 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:19,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:19,322 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:02:19,322 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:19,322 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:19,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:19,593 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:02:19,799 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:02:19,800 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:02:22,439 INFO L85 PathProgramCache]: Analyzing trace with hash 707997983, now seen corresponding path program 48 times [2024-05-06 04:02:22,439 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:22,439 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:22,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:22,593 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:02:22,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:22,594 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:22,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:22,742 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:02:22,793 INFO L85 PathProgramCache]: Analyzing trace with hash 1781256423, now seen corresponding path program 49 times [2024-05-06 04:02:22,793 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:22,793 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:22,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:22,943 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:02:22,944 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:22,944 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:22,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:23,093 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:02:23,144 INFO L85 PathProgramCache]: Analyzing trace with hash 1090019266, now seen corresponding path program 50 times [2024-05-06 04:02:23,144 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:23,144 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:23,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:23,297 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:02:23,298 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:23,298 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:23,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:23,453 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:02:23,565 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:02:23,566 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:02:23,806 INFO L85 PathProgramCache]: Analyzing trace with hash -1197732050, now seen corresponding path program 51 times [2024-05-06 04:02:23,806 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:23,806 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:23,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:23,970 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:02:23,970 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:23,971 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:23,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:24,134 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:02:24,232 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:02:24,265 INFO L85 PathProgramCache]: Analyzing trace with hash 1525012982, now seen corresponding path program 52 times [2024-05-06 04:02:24,265 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:24,266 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:24,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:24,431 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:02:24,431 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:24,431 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:24,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:24,596 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:02:24,692 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:02:24,728 INFO L85 PathProgramCache]: Analyzing trace with hash 713836615, now seen corresponding path program 53 times [2024-05-06 04:02:24,728 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:24,728 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:24,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:24,889 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:02:24,890 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:24,890 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:24,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:25,052 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:02:25,106 INFO L85 PathProgramCache]: Analyzing trace with hash 654099436, now seen corresponding path program 54 times [2024-05-06 04:02:25,106 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:25,106 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:25,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:25,270 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:02:25,270 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:25,270 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:25,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:25,535 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:02:25,644 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:02:25,644 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:02:25,804 INFO L85 PathProgramCache]: Analyzing trace with hash 854310933, now seen corresponding path program 55 times [2024-05-06 04:02:25,804 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:25,805 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:25,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:25,965 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:02:25,965 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:25,965 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:25,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:26,131 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:02:26,337 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:02:26,337 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:02:26,990 INFO L85 PathProgramCache]: Analyzing trace with hash -30107780, now seen corresponding path program 56 times [2024-05-06 04:02:27,004 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:27,004 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:27,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:27,158 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:02:27,158 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:27,158 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:27,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:27,293 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:02:27,348 INFO L85 PathProgramCache]: Analyzing trace with hash -933340312, now seen corresponding path program 57 times [2024-05-06 04:02:27,349 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:27,349 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:27,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:27,487 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:02:27,487 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:27,487 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:27,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:27,626 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:02:27,681 INFO L85 PathProgramCache]: Analyzing trace with hash 1131222260, now seen corresponding path program 58 times [2024-05-06 04:02:27,682 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:27,682 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:27,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:27,931 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:02:27,932 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:27,932 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:27,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:28,081 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:02:28,306 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:02:28,307 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:02:28,965 INFO L85 PathProgramCache]: Analyzing trace with hash 1930088257, now seen corresponding path program 59 times [2024-05-06 04:02:28,965 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:28,965 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:28,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:29,111 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:02:29,112 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:29,112 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:29,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:29,253 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:02:29,362 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:02:29,362 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:02:29,490 INFO L85 PathProgramCache]: Analyzing trace with hash 1211565268, now seen corresponding path program 60 times [2024-05-06 04:02:29,490 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:29,490 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:29,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:29,638 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:02:29,638 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:29,639 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:29,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:29,788 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:02:29,962 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:02:29,963 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:02:46,798 WARN L293 SmtUtils]: Spent 14.14s on a formula simplification. DAG size of input: 33 DAG size of output: 28 (called from [L 210] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.abduction.Abducer.solveAbductionProblem) [2024-05-06 04:02:48,806 WARN L854 $PredicateComparison]: unable to prove that (and (forall ((v_~q1_front~0_In_79 Int) (v_~q1~0.base_In_59 Int) (v_~q1~0.offset_In_59 Int)) (let ((.cse0 (select (select |c_#memory_int| v_~q1~0.base_In_59) (+ (* v_~q1_front~0_In_79 4) v_~q1~0.offset_In_59)))) (or (< (+ 4294967295 .cse0) 0) (< 4294967295 .cse0) (= 0 .cse0) (< v_~q1_front~0_In_79 0)))) (forall ((v_~q2~0.base_In_36 Int) (v_~q2~0.offset_In_36 Int)) (= (select (select |c_#memory_int| v_~q2~0.base_In_36) (+ (* c_~q2_front~0 4) v_~q2~0.offset_In_36)) 0))) is different from false [2024-05-06 04:02:48,807 INFO L85 PathProgramCache]: Analyzing trace with hash 1211565268, now seen corresponding path program 61 times [2024-05-06 04:02:48,808 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:48,808 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:48,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:48,958 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:02:48,960 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:48,961 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:48,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:49,118 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:02:49,224 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:02:49,268 INFO L85 PathProgramCache]: Analyzing trace with hash -1096181488, now seen corresponding path program 62 times [2024-05-06 04:02:49,268 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:49,268 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:49,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:49,418 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:02:49,419 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:49,419 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:49,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:49,569 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:02:49,667 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:02:49,701 INFO L85 PathProgramCache]: Analyzing trace with hash 378113100, now seen corresponding path program 63 times [2024-05-06 04:02:49,702 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:49,702 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:49,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:49,855 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:02:49,855 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:49,855 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:49,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:50,010 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:02:50,108 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:02:50,143 INFO L85 PathProgramCache]: Analyzing trace with hash -1163394926, now seen corresponding path program 64 times [2024-05-06 04:02:50,143 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:50,143 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:50,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:50,301 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:02:50,301 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:50,301 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:50,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:50,640 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:02:50,851 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:02:50,851 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:02:58,019 INFO L85 PathProgramCache]: Analyzing trace with hash 378129969, now seen corresponding path program 1 times [2024-05-06 04:02:58,019 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:58,019 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:58,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:58,178 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:02:58,178 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:58,180 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:58,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:58,375 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:02:58,563 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:02:58,563 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:02:59,216 INFO L85 PathProgramCache]: Analyzing trace with hash -608430942, now seen corresponding path program 2 times [2024-05-06 04:02:59,216 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:59,216 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:59,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:59,382 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:02:59,382 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:02:59,382 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:02:59,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:02:59,661 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:02:59,890 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:02:59,890 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:03:00,471 INFO L85 PathProgramCache]: Analyzing trace with hash -1096180933, now seen corresponding path program 1 times [2024-05-06 04:03:00,472 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:00,472 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:00,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:00,622 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:03:00,622 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:00,622 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:00,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:00,771 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:03:00,980 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:03:00,980 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:03:02,136 INFO L85 PathProgramCache]: Analyzing trace with hash 1089557208, now seen corresponding path program 2 times [2024-05-06 04:03:02,136 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:02,136 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:02,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:02,307 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:03:02,307 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:02,307 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:02,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:02,476 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:03:02,657 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:03:02,657 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:03:03,265 INFO L85 PathProgramCache]: Analyzing trace with hash 1211565299, now seen corresponding path program 1 times [2024-05-06 04:03:03,265 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:03,265 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:03,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:03,415 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:03:03,416 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:03,416 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:03,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:03,569 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:03:03,774 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:03:03,774 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:03:04,234 INFO L85 PathProgramCache]: Analyzing trace with hash -634169312, now seen corresponding path program 2 times [2024-05-06 04:03:04,235 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:04,235 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:04,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:04,415 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:03:04,415 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:04,415 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:04,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:04,585 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:03:04,763 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:03:04,764 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:03:11,551 INFO L85 PathProgramCache]: Analyzing trace with hash -1762032578, now seen corresponding path program 65 times [2024-05-06 04:03:11,551 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:11,552 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:11,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:11,845 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:03:11,845 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:11,845 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:11,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:12,003 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-05-06 04:03:12,207 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:03:12,208 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:03:30,844 WARN L293 SmtUtils]: Spent 16.13s on a formula simplification. DAG size of input: 33 DAG size of output: 30 (called from [L 210] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.abduction.Abducer.solveAbductionProblem) [2024-05-06 04:03:30,931 INFO L85 PathProgramCache]: Analyzing trace with hash 106159413, now seen corresponding path program 66 times [2024-05-06 04:03:30,931 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:30,931 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:30,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:31,129 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:03:31,129 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:31,129 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:31,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:31,328 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:03:31,457 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:03:31,515 INFO L85 PathProgramCache]: Analyzing trace with hash -611029139, now seen corresponding path program 67 times [2024-05-06 04:03:31,516 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:31,516 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:31,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:31,706 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:03:31,706 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:31,707 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:31,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:31,855 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:03:31,909 INFO L85 PathProgramCache]: Analyzing trace with hash -1762033274, now seen corresponding path program 68 times [2024-05-06 04:03:31,909 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:31,909 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:31,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:32,257 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:03:32,258 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:32,258 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:32,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:32,408 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:03:32,521 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:03:32,521 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:03:32,673 INFO L85 PathProgramCache]: Analyzing trace with hash -296805329, now seen corresponding path program 69 times [2024-05-06 04:03:32,673 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:32,673 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:32,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:32,821 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:03:32,821 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:32,821 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:32,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:32,965 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:03:33,169 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:03:33,169 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:03:44,550 INFO L85 PathProgramCache]: Analyzing trace with hash -611029756, now seen corresponding path program 70 times [2024-05-06 04:03:44,550 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:44,550 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:44,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:44,714 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:03:44,714 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:44,714 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:44,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:44,991 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:03:45,047 INFO L85 PathProgramCache]: Analyzing trace with hash -1762052384, now seen corresponding path program 71 times [2024-05-06 04:03:45,047 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:45,047 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:45,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:45,233 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:03:45,234 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:45,234 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:45,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:45,386 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:03:45,443 INFO L85 PathProgramCache]: Analyzing trace with hash 1210951804, now seen corresponding path program 72 times [2024-05-06 04:03:45,443 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:45,443 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:45,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:45,609 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:03:45,609 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:45,609 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:45,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:45,771 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:03:45,827 INFO L85 PathProgramCache]: Analyzing trace with hash -1115198878, now seen corresponding path program 73 times [2024-05-06 04:03:45,828 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:45,828 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:45,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:45,996 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:03:45,996 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:45,997 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:46,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:46,187 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:03:46,285 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:03:46,316 INFO L85 PathProgramCache]: Analyzing trace with hash -1322550119, now seen corresponding path program 74 times [2024-05-06 04:03:46,316 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:46,316 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:46,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:46,480 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 04:03:46,480 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:46,480 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:46,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:46,747 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 04:03:46,839 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:03:46,871 INFO L85 PathProgramCache]: Analyzing trace with hash -1322519336, now seen corresponding path program 1 times [2024-05-06 04:03:46,871 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:46,872 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:46,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:47,031 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:03:47,031 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:47,031 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:47,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:47,197 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:03:47,249 INFO L85 PathProgramCache]: Analyzing trace with hash 1951574395, now seen corresponding path program 2 times [2024-05-06 04:03:47,249 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:47,249 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:47,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:47,420 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:03:47,420 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:47,420 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:47,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:47,585 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:03:47,704 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:03:47,704 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:03:47,840 INFO L85 PathProgramCache]: Analyzing trace with hash -1693347865, now seen corresponding path program 3 times [2024-05-06 04:03:47,840 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:47,840 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:47,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:48,015 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 04:03:48,015 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:48,015 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:48,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:48,189 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 04:03:48,289 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:03:48,322 INFO L85 PathProgramCache]: Analyzing trace with hash -954175395, now seen corresponding path program 4 times [2024-05-06 04:03:48,322 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:48,322 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:48,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:48,599 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 04:03:48,600 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:48,600 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:48,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:48,772 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 04:03:48,889 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:03:48,889 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:03:49,061 INFO L85 PathProgramCache]: Analyzing trace with hash -716725764, now seen corresponding path program 5 times [2024-05-06 04:03:49,061 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:49,061 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:49,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:49,225 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:03:49,226 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:49,226 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:49,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:49,390 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:03:49,447 INFO L85 PathProgramCache]: Analyzing trace with hash -1618620754, now seen corresponding path program 6 times [2024-05-06 04:03:49,447 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:49,447 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:49,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:49,612 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:03:49,612 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:49,612 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:49,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:49,783 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:03:49,889 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:03:49,928 INFO L85 PathProgramCache]: Analyzing trace with hash 1481358697, now seen corresponding path program 1 times [2024-05-06 04:03:49,928 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:49,928 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:49,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:50,087 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:03:50,088 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:50,088 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:50,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:50,343 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:03:50,397 INFO L85 PathProgramCache]: Analyzing trace with hash -1322519798, now seen corresponding path program 2 times [2024-05-06 04:03:50,398 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:50,398 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:50,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:50,558 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:03:50,558 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:50,558 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:50,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:50,718 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:03:50,849 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:03:50,850 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:03:50,977 INFO L85 PathProgramCache]: Analyzing trace with hash 1154210422, now seen corresponding path program 3 times [2024-05-06 04:03:50,977 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:50,978 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:51,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:51,155 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 04:03:51,155 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:51,155 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:51,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:51,327 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 04:03:51,448 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:03:51,488 INFO L85 PathProgramCache]: Analyzing trace with hash 1420785582, now seen corresponding path program 4 times [2024-05-06 04:03:51,488 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:51,488 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:51,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:51,659 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 04:03:51,659 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:51,659 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:51,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:51,831 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 04:03:51,956 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:03:51,956 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:03:52,074 INFO L85 PathProgramCache]: Analyzing trace with hash 1037629901, now seen corresponding path program 5 times [2024-05-06 04:03:52,074 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:52,074 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:52,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:52,374 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:03:52,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:52,374 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:52,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:52,556 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:03:52,610 INFO L85 PathProgramCache]: Analyzing trace with hash -1451432257, now seen corresponding path program 6 times [2024-05-06 04:03:52,610 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:52,611 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:52,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:52,779 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:03:52,779 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:52,779 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:52,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:52,944 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:03:53,048 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:03:53,086 INFO L85 PathProgramCache]: Analyzing trace with hash 2125995706, now seen corresponding path program 1 times [2024-05-06 04:03:53,086 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:53,086 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:53,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:53,245 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:03:53,245 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:53,245 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:53,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:53,402 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:03:53,457 INFO L85 PathProgramCache]: Analyzing trace with hash 1481358297, now seen corresponding path program 2 times [2024-05-06 04:03:53,457 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:53,457 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:53,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:53,628 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:03:53,628 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:53,628 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:53,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:53,892 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:03:54,003 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:03:54,003 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:03:54,118 INFO L85 PathProgramCache]: Analyzing trace with hash -1225169851, now seen corresponding path program 3 times [2024-05-06 04:03:54,118 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:54,118 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:54,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:54,308 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 04:03:54,308 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:54,308 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:54,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:54,508 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 04:03:54,607 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:03:54,649 INFO L85 PathProgramCache]: Analyzing trace with hash 674441151, now seen corresponding path program 4 times [2024-05-06 04:03:54,650 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:54,650 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:54,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:54,866 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 04:03:54,866 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:54,866 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:54,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:55,070 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 04:03:55,185 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:03:55,185 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:03:55,611 INFO L85 PathProgramCache]: Analyzing trace with hash -594453922, now seen corresponding path program 5 times [2024-05-06 04:03:55,612 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:55,612 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:55,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:55,787 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:03:55,787 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:55,788 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:55,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:55,994 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:03:56,047 INFO L85 PathProgramCache]: Analyzing trace with hash 356923280, now seen corresponding path program 6 times [2024-05-06 04:03:56,048 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:56,048 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:56,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:56,366 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:03:56,366 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:56,366 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:56,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:56,530 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:03:56,632 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:03:56,675 INFO L85 PathProgramCache]: Analyzing trace with hash -1316892852, now seen corresponding path program 75 times [2024-05-06 04:03:56,675 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:56,675 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:56,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:56,833 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:03:56,833 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:56,834 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:56,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:56,992 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:03:57,047 INFO L85 PathProgramCache]: Analyzing trace with hash 2125995399, now seen corresponding path program 76 times [2024-05-06 04:03:57,047 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:57,047 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:57,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:57,246 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:03:57,246 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:57,246 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:57,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:57,413 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:03:57,544 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:03:57,545 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:03:57,692 INFO L85 PathProgramCache]: Analyzing trace with hash 1710766067, now seen corresponding path program 77 times [2024-05-06 04:03:57,692 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:57,692 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:57,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:57,864 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 04:03:57,864 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:57,864 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:57,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:58,138 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 04:03:58,232 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:03:58,269 INFO L85 PathProgramCache]: Analyzing trace with hash 1494141393, now seen corresponding path program 78 times [2024-05-06 04:03:58,269 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:58,269 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:58,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:58,443 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 04:03:58,444 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:58,444 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:58,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:58,619 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 04:03:58,728 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:03:58,728 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:03:58,850 INFO L85 PathProgramCache]: Analyzing trace with hash -2002463376, now seen corresponding path program 79 times [2024-05-06 04:03:58,851 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:58,851 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:58,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:59,020 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:03:59,020 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:59,020 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:59,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:59,184 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:03:59,238 INFO L85 PathProgramCache]: Analyzing trace with hash 1942048546, now seen corresponding path program 80 times [2024-05-06 04:03:59,239 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:59,239 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:59,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:59,406 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:03:59,406 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:59,406 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:59,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:03:59,568 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:03:59,681 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:03:59,681 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:03:59,792 INFO L85 PathProgramCache]: Analyzing trace with hash -933158779, now seen corresponding path program 81 times [2024-05-06 04:03:59,792 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:03:59,792 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:03:59,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:00,041 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:04:00,041 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:00,042 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:00,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:00,181 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:04:00,376 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:04:00,376 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:04:01,332 INFO L85 PathProgramCache]: Analyzing trace with hash 1136849780, now seen corresponding path program 82 times [2024-05-06 04:04:01,333 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:01,333 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:01,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:01,495 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:04:01,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:01,496 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:01,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:01,672 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:04:01,794 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:04:01,794 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:04:01,912 INFO L85 PathProgramCache]: Analyzing trace with hash 882605672, now seen corresponding path program 83 times [2024-05-06 04:04:01,912 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:01,912 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:01,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:02,054 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:04:02,054 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:02,054 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:02,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:02,196 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:04:02,293 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:04:02,325 INFO L85 PathProgramCache]: Analyzing trace with hash 1590972924, now seen corresponding path program 84 times [2024-05-06 04:04:02,325 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:02,325 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:02,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:02,475 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:04:02,475 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:02,475 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:02,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:02,718 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2024-05-06 04:04:02,831 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:04:02,832 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:04:02,952 INFO L85 PathProgramCache]: Analyzing trace with hash -1062802847, now seen corresponding path program 85 times [2024-05-06 04:04:02,952 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:02,952 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:02,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:03,089 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:03,089 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:03,090 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:03,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:03,218 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:03,445 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:04:03,446 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:04:04,063 INFO L85 PathProgramCache]: Analyzing trace with hash -435644763, now seen corresponding path program 86 times [2024-05-06 04:04:04,064 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:04,064 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:04,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:04,206 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:04,206 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:04,207 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:04,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:04,347 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:04,399 INFO L85 PathProgramCache]: Analyzing trace with hash 762393194, now seen corresponding path program 87 times [2024-05-06 04:04:04,399 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:04,399 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:04,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:04,535 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:04,535 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:04,535 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:04,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:04,689 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 3 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:04,783 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:04:04,817 INFO L85 PathProgramCache]: Analyzing trace with hash -722280231, now seen corresponding path program 88 times [2024-05-06 04:04:04,817 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:04,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:04,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:05,049 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:05,050 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:05,050 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:05,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:05,202 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:05,261 INFO L85 PathProgramCache]: Analyzing trace with hash -915849830, now seen corresponding path program 89 times [2024-05-06 04:04:05,262 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:05,262 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:05,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:05,402 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:05,403 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:05,403 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:05,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:05,537 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:05,595 INFO L85 PathProgramCache]: Analyzing trace with hash 1845809455, now seen corresponding path program 90 times [2024-05-06 04:04:05,595 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:05,595 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:05,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:05,738 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:05,738 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:05,738 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:05,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:05,887 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:05,947 INFO L85 PathProgramCache]: Analyzing trace with hash 44039282, now seen corresponding path program 91 times [2024-05-06 04:04:05,947 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:05,947 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:05,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:06,115 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:06,115 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:06,115 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:06,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:06,286 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:06,345 INFO L85 PathProgramCache]: Analyzing trace with hash -1286503827, now seen corresponding path program 92 times [2024-05-06 04:04:06,345 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:06,345 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:06,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:06,511 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 04:04:06,511 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:06,511 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:06,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:06,772 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 04:04:06,856 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:04:06,856 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 04:04:06,950 INFO L85 PathProgramCache]: Analyzing trace with hash -1033739815, now seen corresponding path program 93 times [2024-05-06 04:04:06,951 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:06,951 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:06,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:07,100 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:07,100 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:07,101 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:07,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:07,259 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:07,332 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:04:07,375 INFO L85 PathProgramCache]: Analyzing trace with hash -1981162333, now seen corresponding path program 94 times [2024-05-06 04:04:07,375 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:07,376 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:07,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:07,537 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:07,537 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:07,537 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:07,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:07,693 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:07,821 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:04:07,860 INFO L85 PathProgramCache]: Analyzing trace with hash -1064761712, now seen corresponding path program 95 times [2024-05-06 04:04:07,860 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:07,860 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:07,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:08,011 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:08,011 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:08,011 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:08,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:08,176 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:08,229 INFO L85 PathProgramCache]: Analyzing trace with hash 1352126138, now seen corresponding path program 96 times [2024-05-06 04:04:08,229 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:08,230 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:08,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:08,492 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:08,492 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:08,492 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:08,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:08,657 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:08,750 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:04:08,750 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 04:04:08,857 INFO L85 PathProgramCache]: Analyzing trace with hash -2112557182, now seen corresponding path program 97 times [2024-05-06 04:04:08,857 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:08,857 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:08,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:09,012 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:09,013 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:09,013 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:09,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:09,166 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:09,387 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:04:09,387 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:04:10,154 INFO L85 PathProgramCache]: Analyzing trace with hash -627918939, now seen corresponding path program 98 times [2024-05-06 04:04:10,154 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:10,154 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:10,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:10,318 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:10,318 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:10,318 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:10,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:10,477 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:10,535 INFO L85 PathProgramCache]: Analyzing trace with hash -2134651411, now seen corresponding path program 99 times [2024-05-06 04:04:10,535 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:10,535 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:10,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:10,812 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:10,812 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:10,813 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:10,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:10,994 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:11,105 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:04:11,147 INFO L85 PathProgramCache]: Analyzing trace with hash 1594389326, now seen corresponding path program 100 times [2024-05-06 04:04:11,147 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:11,147 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:11,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:11,314 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:11,314 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:11,314 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:11,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:11,485 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:11,550 INFO L85 PathProgramCache]: Analyzing trace with hash -2113537604, now seen corresponding path program 101 times [2024-05-06 04:04:11,550 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:11,550 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:11,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:11,724 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:11,724 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:11,724 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:11,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:11,899 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:11,957 INFO L85 PathProgramCache]: Analyzing trace with hash -1095155431, now seen corresponding path program 102 times [2024-05-06 04:04:11,957 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:11,958 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:11,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:12,141 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:12,141 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:12,141 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:12,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:12,325 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:12,385 INFO L85 PathProgramCache]: Analyzing trace with hash 409921247, now seen corresponding path program 103 times [2024-05-06 04:04:12,385 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:12,385 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:12,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:12,681 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:12,682 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:12,682 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:12,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:12,913 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:13,068 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:04:13,068 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:04:13,204 INFO L85 PathProgramCache]: Analyzing trace with hash -1671681717, now seen corresponding path program 104 times [2024-05-06 04:04:13,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:13,205 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:13,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:13,393 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 04:04:13,394 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:13,394 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:13,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:13,607 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 04:04:13,723 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:04:13,764 INFO L85 PathProgramCache]: Analyzing trace with hash -282524807, now seen corresponding path program 105 times [2024-05-06 04:04:13,764 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:13,764 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:13,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:13,962 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 04:04:13,962 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:13,962 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:13,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:14,167 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 04:04:14,266 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:04:14,298 INFO L85 PathProgramCache]: Analyzing trace with hash 2027308452, now seen corresponding path program 106 times [2024-05-06 04:04:14,298 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:14,298 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:14,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:14,488 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:14,488 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:14,488 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:14,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:14,657 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:14,711 INFO L85 PathProgramCache]: Analyzing trace with hash -1577946577, now seen corresponding path program 107 times [2024-05-06 04:04:14,711 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:14,711 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:14,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:14,988 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:14,988 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:14,988 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:15,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:15,167 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:15,284 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:04:15,284 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:04:15,414 INFO L85 PathProgramCache]: Analyzing trace with hash 619586328, now seen corresponding path program 108 times [2024-05-06 04:04:15,414 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:15,414 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:15,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:15,591 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:15,592 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:15,592 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:15,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:15,779 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:15,842 INFO L85 PathProgramCache]: Analyzing trace with hash 667620121, now seen corresponding path program 109 times [2024-05-06 04:04:15,842 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:15,842 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:15,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:16,010 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:16,010 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:16,010 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:16,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:16,176 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:16,282 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:04:16,282 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:04:16,392 INFO L85 PathProgramCache]: Analyzing trace with hash 487844996, now seen corresponding path program 110 times [2024-05-06 04:04:16,392 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:16,393 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:16,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:16,563 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:16,563 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:16,563 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:16,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:16,743 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:16,942 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:04:16,974 INFO L85 PathProgramCache]: Analyzing trace with hash -2056673440, now seen corresponding path program 111 times [2024-05-06 04:04:16,974 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:16,974 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:16,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:17,150 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:17,150 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:17,151 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:17,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:17,322 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:17,433 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:04:17,473 INFO L85 PathProgramCache]: Analyzing trace with hash -1192787171, now seen corresponding path program 112 times [2024-05-06 04:04:17,473 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:17,474 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:17,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:17,669 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:17,670 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:17,670 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:17,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:17,874 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:17,927 INFO L85 PathProgramCache]: Analyzing trace with hash 1678304214, now seen corresponding path program 113 times [2024-05-06 04:04:17,927 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:17,927 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:17,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:18,105 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:04:18,105 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:18,105 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:18,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:18,284 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:04:18,396 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:04:18,396 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:04:18,513 INFO L85 PathProgramCache]: Analyzing trace with hash -177024385, now seen corresponding path program 114 times [2024-05-06 04:04:18,513 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:18,513 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:18,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:18,695 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:18,695 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:18,695 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:18,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:18,878 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:19,106 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:04:19,107 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:04:19,301 INFO L85 PathProgramCache]: Analyzing trace with hash -1919376593, now seen corresponding path program 3 times [2024-05-06 04:04:19,302 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:19,302 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:19,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:19,479 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:19,480 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:19,480 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:19,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:19,652 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:19,745 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:04:19,776 INFO L85 PathProgramCache]: Analyzing trace with hash 628868629, now seen corresponding path program 4 times [2024-05-06 04:04:19,776 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:19,776 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:19,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:19,950 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:19,950 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:19,951 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:19,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:20,141 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:20,249 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:04:20,287 INFO L85 PathProgramCache]: Analyzing trace with hash 1240459400, now seen corresponding path program 5 times [2024-05-06 04:04:20,287 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:20,287 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:20,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:20,477 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:20,477 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:20,477 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:20,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:20,669 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:20,722 INFO L85 PathProgramCache]: Analyzing trace with hash -200463413, now seen corresponding path program 6 times [2024-05-06 04:04:20,722 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:20,722 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:20,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:20,933 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:04:20,934 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:20,934 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:20,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:21,244 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:04:21,356 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:04:21,356 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:04:21,465 INFO L85 PathProgramCache]: Analyzing trace with hash 40014772, now seen corresponding path program 7 times [2024-05-06 04:04:21,466 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:21,466 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:21,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:21,655 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:21,655 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:21,655 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:21,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:21,845 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:21,912 INFO L85 PathProgramCache]: Analyzing trace with hash 1671548518, now seen corresponding path program 8 times [2024-05-06 04:04:21,912 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:21,912 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:21,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:22,074 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:22,074 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:22,074 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:22,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:22,233 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:22,288 INFO L85 PathProgramCache]: Analyzing trace with hash -1812261771, now seen corresponding path program 3 times [2024-05-06 04:04:22,288 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:22,288 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:22,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:22,460 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:22,460 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:22,460 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:22,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:22,641 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:22,767 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:04:22,767 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:04:22,892 INFO L85 PathProgramCache]: Analyzing trace with hash -1798531872, now seen corresponding path program 4 times [2024-05-06 04:04:22,892 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:22,892 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:22,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:23,055 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:23,055 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:23,055 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:23,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:23,363 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:23,471 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:04:23,505 INFO L85 PathProgramCache]: Analyzing trace with hash 80087684, now seen corresponding path program 5 times [2024-05-06 04:04:23,505 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:23,505 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:23,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:23,732 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:23,732 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:23,732 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:23,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:23,916 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:24,008 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:04:24,044 INFO L85 PathProgramCache]: Analyzing trace with hash 69636729, now seen corresponding path program 6 times [2024-05-06 04:04:24,044 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:24,044 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:24,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:24,218 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:24,218 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:24,218 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:24,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:24,390 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:24,442 INFO L85 PathProgramCache]: Analyzing trace with hash -2136227846, now seen corresponding path program 7 times [2024-05-06 04:04:24,442 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:24,442 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:24,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:24,633 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:04:24,633 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:24,633 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:24,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:24,820 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:04:24,930 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:04:24,931 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:04:25,067 INFO L85 PathProgramCache]: Analyzing trace with hash 279340963, now seen corresponding path program 8 times [2024-05-06 04:04:25,068 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:25,068 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:25,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:25,242 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:25,242 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:25,242 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:25,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:25,414 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:25,473 INFO L85 PathProgramCache]: Analyzing trace with hash -1000925976, now seen corresponding path program 3 times [2024-05-06 04:04:25,473 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:25,473 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:25,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:25,760 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:25,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:25,760 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:25,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:25,937 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:26,070 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:04:26,070 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:04:26,194 INFO L85 PathProgramCache]: Analyzing trace with hash -184281581, now seen corresponding path program 4 times [2024-05-06 04:04:26,194 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:26,195 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:26,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:26,356 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:26,356 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:26,357 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:26,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:26,517 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:26,611 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:04:26,650 INFO L85 PathProgramCache]: Analyzing trace with hash -1417760847, now seen corresponding path program 5 times [2024-05-06 04:04:26,651 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:26,651 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:26,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:26,818 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:26,818 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:26,818 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:26,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:26,983 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:27,090 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:04:27,137 INFO L85 PathProgramCache]: Analyzing trace with hash 312657004, now seen corresponding path program 6 times [2024-05-06 04:04:27,137 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:27,138 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:27,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:27,313 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:27,314 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:27,314 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:27,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:27,472 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:27,524 INFO L85 PathProgramCache]: Analyzing trace with hash 1102433383, now seen corresponding path program 7 times [2024-05-06 04:04:27,525 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:27,525 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:27,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:27,803 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:04:27,804 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:27,804 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:27,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:27,968 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:04:28,079 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:04:28,080 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:04:28,235 INFO L85 PathProgramCache]: Analyzing trace with hash 1672653648, now seen corresponding path program 8 times [2024-05-06 04:04:28,235 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:28,235 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:28,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:28,391 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:28,392 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:28,392 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:28,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:28,550 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:28,605 INFO L85 PathProgramCache]: Analyzing trace with hash -298293034, now seen corresponding path program 3 times [2024-05-06 04:04:28,605 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:28,605 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:28,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:28,781 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:28,783 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:28,784 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:28,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:29,000 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:29,128 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:04:29,129 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:04:29,253 INFO L85 PathProgramCache]: Analyzing trace with hash -1318744703, now seen corresponding path program 4 times [2024-05-06 04:04:29,253 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:29,254 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:29,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:29,412 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:29,412 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:29,413 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:29,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:29,580 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:29,660 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:04:29,687 INFO L85 PathProgramCache]: Analyzing trace with hash 2068588035, now seen corresponding path program 5 times [2024-05-06 04:04:29,687 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:29,687 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:29,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:29,849 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:29,850 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:29,850 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:29,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:30,144 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:30,243 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:04:30,275 INFO L85 PathProgramCache]: Analyzing trace with hash 1647787866, now seen corresponding path program 6 times [2024-05-06 04:04:30,275 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:30,276 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:30,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:30,453 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:30,453 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:30,454 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:30,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:30,616 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:30,676 INFO L85 PathProgramCache]: Analyzing trace with hash -458182855, now seen corresponding path program 7 times [2024-05-06 04:04:30,676 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:30,676 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:30,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:30,851 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:04:30,852 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:30,852 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:30,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:31,018 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:04:31,146 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:04:31,146 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:04:31,265 INFO L85 PathProgramCache]: Analyzing trace with hash -2025055582, now seen corresponding path program 8 times [2024-05-06 04:04:31,265 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:31,265 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:31,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:31,420 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:31,420 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:31,420 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:31,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:31,575 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:31,629 INFO L85 PathProgramCache]: Analyzing trace with hash 56691787, now seen corresponding path program 3 times [2024-05-06 04:04:31,630 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:31,630 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:31,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:31,804 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:31,804 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:31,804 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:31,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:32,107 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:32,256 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:04:32,256 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:04:32,405 INFO L85 PathProgramCache]: Analyzing trace with hash -1881503178, now seen corresponding path program 4 times [2024-05-06 04:04:32,405 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:32,405 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:32,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:32,622 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:32,622 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:32,622 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:32,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:32,802 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:32,917 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:04:32,962 INFO L85 PathProgramCache]: Analyzing trace with hash 1802944494, now seen corresponding path program 5 times [2024-05-06 04:04:32,963 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:32,963 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:32,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:33,148 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:33,148 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:33,148 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:33,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:33,328 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:33,446 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:04:33,488 INFO L85 PathProgramCache]: Analyzing trace with hash -2017598129, now seen corresponding path program 6 times [2024-05-06 04:04:33,488 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:33,488 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:33,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:33,666 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:33,675 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:33,675 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:33,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:33,849 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:33,909 INFO L85 PathProgramCache]: Analyzing trace with hash 1878968292, now seen corresponding path program 7 times [2024-05-06 04:04:33,909 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:33,909 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:33,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:34,096 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:04:34,096 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:34,096 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:34,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:34,287 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:04:34,405 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:04:34,405 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:04:34,526 INFO L85 PathProgramCache]: Analyzing trace with hash -1173462515, now seen corresponding path program 8 times [2024-05-06 04:04:34,526 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:34,526 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:34,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:34,680 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:34,681 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:34,681 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:34,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:34,960 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:35,016 INFO L85 PathProgramCache]: Analyzing trace with hash 471106616, now seen corresponding path program 3 times [2024-05-06 04:04:35,016 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:35,016 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:35,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:35,185 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:35,185 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:35,185 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:35,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:35,355 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:35,482 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:04:35,482 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:04:35,603 INFO L85 PathProgramCache]: Analyzing trace with hash -2064311965, now seen corresponding path program 4 times [2024-05-06 04:04:35,604 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:35,604 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:35,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:35,769 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:35,769 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:35,769 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:35,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:35,930 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:36,032 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:04:36,069 INFO L85 PathProgramCache]: Analyzing trace with hash 430839393, now seen corresponding path program 5 times [2024-05-06 04:04:36,069 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:36,070 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:36,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:36,239 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:36,239 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:36,240 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:36,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:36,401 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:36,497 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:04:36,526 INFO L85 PathProgramCache]: Analyzing trace with hash -1164158020, now seen corresponding path program 6 times [2024-05-06 04:04:36,526 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:36,526 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:36,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:36,704 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:36,704 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:36,704 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:36,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:36,900 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:36,962 INFO L85 PathProgramCache]: Analyzing trace with hash -1729159401, now seen corresponding path program 7 times [2024-05-06 04:04:36,963 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:36,963 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:36,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:37,269 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:04:37,269 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:37,269 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:37,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:37,450 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:04:37,573 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:04:37,573 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:04:37,701 INFO L85 PathProgramCache]: Analyzing trace with hash -176100864, now seen corresponding path program 8 times [2024-05-06 04:04:37,702 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:37,702 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:37,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:37,859 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:37,859 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:37,859 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:37,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:38,014 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:38,071 INFO L85 PathProgramCache]: Analyzing trace with hash -2028394578, now seen corresponding path program 115 times [2024-05-06 04:04:38,071 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:38,071 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:38,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:38,243 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:38,244 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:38,244 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:38,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:38,410 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:38,539 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:04:38,539 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:04:38,672 INFO L85 PathProgramCache]: Analyzing trace with hash 1285038681, now seen corresponding path program 116 times [2024-05-06 04:04:38,672 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:38,672 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:38,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:38,830 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:38,830 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:38,830 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:38,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:38,989 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:39,089 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:04:39,141 INFO L85 PathProgramCache]: Analyzing trace with hash 1181494315, now seen corresponding path program 117 times [2024-05-06 04:04:39,141 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:39,141 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:39,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:39,306 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:39,306 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:39,306 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:39,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:39,600 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:04:39,706 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:04:39,746 INFO L85 PathProgramCache]: Analyzing trace with hash -164025806, now seen corresponding path program 118 times [2024-05-06 04:04:39,746 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:39,746 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:39,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:39,903 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:39,903 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:39,903 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:39,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:40,064 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:40,119 INFO L85 PathProgramCache]: Analyzing trace with hash -789831839, now seen corresponding path program 119 times [2024-05-06 04:04:40,119 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:40,119 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:40,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:40,283 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:04:40,283 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:40,283 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:40,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:40,446 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:04:40,574 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:04:40,574 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:04:40,705 INFO L85 PathProgramCache]: Analyzing trace with hash 410350794, now seen corresponding path program 120 times [2024-05-06 04:04:40,705 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:40,705 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:40,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:40,859 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:40,859 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:40,859 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:40,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:41,022 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:41,118 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:04:41,161 INFO L85 PathProgramCache]: Analyzing trace with hash -2134651440, now seen corresponding path program 121 times [2024-05-06 04:04:41,161 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:41,161 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:41,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:41,308 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:41,308 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:41,309 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:41,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:41,458 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:41,513 INFO L85 PathProgramCache]: Analyzing trace with hash -1749684358, now seen corresponding path program 122 times [2024-05-06 04:04:41,514 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:41,514 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:41,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:41,669 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:41,669 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:41,669 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:41,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:41,959 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:42,159 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:04:42,159 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:04:54,207 INFO L85 PathProgramCache]: Analyzing trace with hash -2114427723, now seen corresponding path program 123 times [2024-05-06 04:04:54,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:54,208 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:54,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:54,379 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:54,379 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:54,379 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:54,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:54,544 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:54,597 INFO L85 PathProgramCache]: Analyzing trace with hash -1122749113, now seen corresponding path program 124 times [2024-05-06 04:04:54,597 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:54,597 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:54,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:54,763 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:54,763 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:54,763 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:54,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:54,938 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:54,991 INFO L85 PathProgramCache]: Analyzing trace with hash -445483267, now seen corresponding path program 125 times [2024-05-06 04:04:54,992 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:54,992 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:55,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:55,179 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:04:55,179 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:55,179 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:55,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:55,626 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:04:55,688 INFO L85 PathProgramCache]: Analyzing trace with hash -445483267, now seen corresponding path program 126 times [2024-05-06 04:04:55,688 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:55,688 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:55,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:55,882 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:55,882 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:55,882 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:55,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:56,054 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:56,108 INFO L85 PathProgramCache]: Analyzing trace with hash -925078519, now seen corresponding path program 127 times [2024-05-06 04:04:56,108 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:56,108 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:56,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:56,276 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:56,277 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:56,277 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:56,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:56,448 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:56,567 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:04:56,567 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 04:04:56,695 INFO L85 PathProgramCache]: Analyzing trace with hash 2009350210, now seen corresponding path program 128 times [2024-05-06 04:04:56,696 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:56,696 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:56,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:56,839 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:56,839 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:56,840 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:56,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:56,987 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:04:57,207 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:04:57,208 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:04:58,054 INFO L85 PathProgramCache]: Analyzing trace with hash -2134652088, now seen corresponding path program 129 times [2024-05-06 04:04:58,055 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:58,055 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:58,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:58,216 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:58,217 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:58,217 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:58,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:58,374 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:58,424 INFO L85 PathProgramCache]: Analyzing trace with hash -1749704428, now seen corresponding path program 130 times [2024-05-06 04:04:58,424 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:58,424 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:58,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:58,742 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:58,742 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:58,743 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:58,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:58,914 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:58,967 INFO L85 PathProgramCache]: Analyzing trace with hash 1593738448, now seen corresponding path program 131 times [2024-05-06 04:04:58,968 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:58,968 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:58,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:59,131 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:04:59,131 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:59,131 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:59,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:59,293 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:04:59,346 INFO L85 PathProgramCache]: Analyzing trace with hash 1593738448, now seen corresponding path program 132 times [2024-05-06 04:04:59,346 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:59,346 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:59,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:59,509 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:59,509 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:59,509 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:59,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:59,681 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:59,732 INFO L85 PathProgramCache]: Analyzing trace with hash -2133714794, now seen corresponding path program 133 times [2024-05-06 04:04:59,732 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:59,732 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:59,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:04:59,898 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:04:59,899 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:04:59,899 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:04:59,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:00,074 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:05:00,182 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:05:00,182 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 04:05:00,292 INFO L85 PathProgramCache]: Analyzing trace with hash -1971660842, now seen corresponding path program 7 times [2024-05-06 04:05:00,292 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:00,292 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:00,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:00,495 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:05:00,495 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:00,495 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:00,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:00,698 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:05:00,793 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:05:00,829 INFO L85 PathProgramCache]: Analyzing trace with hash -991943098, now seen corresponding path program 8 times [2024-05-06 04:05:00,829 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:00,829 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:00,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:01,143 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:05:01,143 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:01,143 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:01,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:01,298 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:05:01,396 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:05:01,442 INFO L85 PathProgramCache]: Analyzing trace with hash 458282957, now seen corresponding path program 9 times [2024-05-06 04:05:01,442 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:01,442 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:01,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:01,591 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:05:01,591 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:01,591 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:01,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:01,740 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:05:01,793 INFO L85 PathProgramCache]: Analyzing trace with hash 1321870621, now seen corresponding path program 10 times [2024-05-06 04:05:01,793 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:01,793 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:01,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:01,951 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:05:01,951 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:01,951 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:01,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:02,107 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:05:02,222 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:05:02,222 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 04:05:02,345 INFO L85 PathProgramCache]: Analyzing trace with hash -123764059, now seen corresponding path program 11 times [2024-05-06 04:05:02,345 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:02,345 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:02,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:02,495 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:05:02,495 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:02,495 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:02,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:02,641 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:05:02,698 INFO L85 PathProgramCache]: Analyzing trace with hash 2011042552, now seen corresponding path program 12 times [2024-05-06 04:05:02,699 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:02,699 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:02,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:02,845 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:05:02,845 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:02,845 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:02,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:02,996 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:05:03,052 INFO L85 PathProgramCache]: Analyzing trace with hash 1014998605, now seen corresponding path program 7 times [2024-05-06 04:05:03,052 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:03,052 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:03,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:03,374 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 04:05:03,375 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:03,375 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:03,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:03,541 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 04:05:03,653 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:05:03,654 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 04:05:03,775 INFO L85 PathProgramCache]: Analyzing trace with hash -1098383943, now seen corresponding path program 8 times [2024-05-06 04:05:03,775 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:03,776 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:03,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:03,927 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:05:03,927 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:03,927 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:03,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:04,085 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:05:04,178 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:05:04,219 INFO L85 PathProgramCache]: Analyzing trace with hash 309836995, now seen corresponding path program 9 times [2024-05-06 04:05:04,219 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:04,219 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:04,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:04,375 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:05:04,376 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:04,376 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:04,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:04,529 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:05:04,628 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:05:04,679 INFO L85 PathProgramCache]: Analyzing trace with hash -148628880, now seen corresponding path program 10 times [2024-05-06 04:05:04,679 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:04,679 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:04,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:04,827 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:05:04,827 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:04,828 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:04,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:04,976 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:05:05,030 INFO L85 PathProgramCache]: Analyzing trace with hash -312527142, now seen corresponding path program 11 times [2024-05-06 04:05:05,030 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:05,030 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:05,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:05,186 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:05:05,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:05,186 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:05,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:05,342 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:05:05,455 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:05:05,455 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 04:05:05,573 INFO L85 PathProgramCache]: Analyzing trace with hash -2083004510, now seen corresponding path program 12 times [2024-05-06 04:05:05,573 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:05,573 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:05,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:05,720 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:05:05,720 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:05,720 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:05,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:06,043 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:05:06,101 INFO L85 PathProgramCache]: Analyzing trace with hash -1298130228, now seen corresponding path program 7 times [2024-05-06 04:05:06,101 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:06,101 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:06,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:06,263 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 04:05:06,263 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:06,264 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:06,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:06,424 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 04:05:06,518 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:05:06,518 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 04:05:06,609 INFO L85 PathProgramCache]: Analyzing trace with hash -957774344, now seen corresponding path program 8 times [2024-05-06 04:05:06,609 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:06,609 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:06,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:06,760 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:05:06,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:06,760 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:06,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:06,910 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:05:07,004 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:05:07,049 INFO L85 PathProgramCache]: Analyzing trace with hash 373767268, now seen corresponding path program 9 times [2024-05-06 04:05:07,049 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:07,049 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:07,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:07,202 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:05:07,202 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:07,202 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:07,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:07,355 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:05:07,457 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:05:07,494 INFO L85 PathProgramCache]: Analyzing trace with hash -2106022289, now seen corresponding path program 10 times [2024-05-06 04:05:07,494 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:07,494 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:07,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:07,650 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:05:07,651 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:07,651 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:07,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:07,799 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:05:07,853 INFO L85 PathProgramCache]: Analyzing trace with hash -862180677, now seen corresponding path program 11 times [2024-05-06 04:05:07,854 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:07,854 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:07,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:08,010 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:05:08,011 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:08,011 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:08,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:08,310 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:05:08,403 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:05:08,404 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 04:05:08,520 INFO L85 PathProgramCache]: Analyzing trace with hash 2010273731, now seen corresponding path program 12 times [2024-05-06 04:05:08,520 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:08,520 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:08,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:08,670 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:05:08,670 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:08,670 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:08,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:08,824 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:05:08,881 INFO L85 PathProgramCache]: Analyzing trace with hash 1933371248, now seen corresponding path program 134 times [2024-05-06 04:05:08,881 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:08,881 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:08,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:09,059 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 04:05:09,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:09,060 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:09,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:09,233 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 04:05:09,349 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:05:09,349 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 04:05:09,465 INFO L85 PathProgramCache]: Analyzing trace with hash 1155083164, now seen corresponding path program 135 times [2024-05-06 04:05:09,466 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:09,466 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:09,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:09,629 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:05:09,629 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:09,630 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:09,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:09,791 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:05:09,904 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:05:09,939 INFO L85 PathProgramCache]: Analyzing trace with hash 1447840576, now seen corresponding path program 136 times [2024-05-06 04:05:09,939 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:09,939 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:09,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:10,093 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:05:10,094 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:10,094 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:10,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:10,248 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:05:10,350 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:05:10,393 INFO L85 PathProgramCache]: Analyzing trace with hash 1990026515, now seen corresponding path program 137 times [2024-05-06 04:05:10,394 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:10,394 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:10,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:10,541 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:05:10,541 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:10,541 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:10,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:10,688 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:05:10,742 INFO L85 PathProgramCache]: Analyzing trace with hash 1561280663, now seen corresponding path program 138 times [2024-05-06 04:05:10,742 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:10,742 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:10,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:11,037 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:05:11,037 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:11,037 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:11,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:11,196 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:05:11,309 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:05:11,309 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 04:05:11,446 INFO L85 PathProgramCache]: Analyzing trace with hash -628542305, now seen corresponding path program 139 times [2024-05-06 04:05:11,446 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:11,446 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:11,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:11,590 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:05:11,590 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:11,590 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:11,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:11,740 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:05:11,917 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:05:11,917 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:05:14,772 INFO L85 PathProgramCache]: Analyzing trace with hash 1845809460, now seen corresponding path program 140 times [2024-05-06 04:05:14,773 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:14,773 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:14,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:14,927 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:05:14,927 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:14,927 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:14,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:15,094 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:05:15,153 INFO L85 PathProgramCache]: Analyzing trace with hash 1385519280, now seen corresponding path program 141 times [2024-05-06 04:05:15,153 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:15,153 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:15,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:15,352 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:05:15,353 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:15,353 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:15,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:15,555 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:05:15,613 INFO L85 PathProgramCache]: Analyzing trace with hash 1425580, now seen corresponding path program 142 times [2024-05-06 04:05:15,613 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:15,613 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:15,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:15,798 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:05:15,799 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:15,799 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:15,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:16,196 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:05:16,282 INFO L85 PathProgramCache]: Analyzing trace with hash 1425580, now seen corresponding path program 143 times [2024-05-06 04:05:16,282 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:16,283 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:16,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:16,436 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:05:16,436 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:16,436 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:16,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:16,583 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:05:16,802 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:05:16,802 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:05:33,442 WARN L293 SmtUtils]: Spent 14.15s on a formula simplification. DAG size of input: 33 DAG size of output: 28 (called from [L 210] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.abduction.Abducer.solveAbductionProblem) [2024-05-06 04:05:35,449 WARN L854 $PredicateComparison]: unable to prove that (and (forall ((v_~q1~0.offset_In_98 Int) (v_~q1~0.base_In_98 Int) (v_~q1_front~0_In_140 Int)) (let ((.cse0 (select (select |c_#memory_int| v_~q1~0.base_In_98) (+ (* v_~q1_front~0_In_140 4) v_~q1~0.offset_In_98)))) (or (< (+ 4294967295 .cse0) 0) (< 4294967295 .cse0) (< v_~q1_front~0_In_140 0) (= .cse0 0)))) (forall ((v_~q2~0.base_In_115 Int) (v_~q2~0.offset_In_115 Int)) (= (select (select |c_#memory_int| v_~q2~0.base_In_115) (+ (* c_~q2_front~0 4) v_~q2~0.offset_In_115)) 0))) is different from false [2024-05-06 04:05:35,452 INFO L85 PathProgramCache]: Analyzing trace with hash -479074167, now seen corresponding path program 144 times [2024-05-06 04:05:35,452 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:35,452 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:35,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:35,602 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:05:35,602 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:35,602 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:35,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:35,753 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:05:35,808 INFO L85 PathProgramCache]: Analyzing trace with hash -828746047, now seen corresponding path program 145 times [2024-05-06 04:05:35,809 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:35,809 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:35,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:35,962 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:05:35,963 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:35,963 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:35,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:36,114 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-05-06 04:05:36,242 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:05:36,242 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:05:37,202 INFO L85 PathProgramCache]: Analyzing trace with hash -1855964644, now seen corresponding path program 146 times [2024-05-06 04:05:37,202 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:37,202 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:37,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:37,360 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:05:37,360 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:37,360 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:37,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:37,514 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:05:37,720 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:05:37,720 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:05:50,350 WARN L293 SmtUtils]: Spent 9.00s on a formula simplification. DAG size of input: 34 DAG size of output: 14 (called from [L 210] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.abduction.Abducer.solveAbductionProblem) [2024-05-06 04:05:50,388 INFO L85 PathProgramCache]: Analyzing trace with hash -1855964644, now seen corresponding path program 147 times [2024-05-06 04:05:50,389 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:50,389 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:50,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:50,547 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:05:50,547 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:50,547 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:50,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:50,709 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:05:50,823 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:05:50,870 INFO L85 PathProgramCache]: Analyzing trace with hash -1700328248, now seen corresponding path program 148 times [2024-05-06 04:05:50,870 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:50,870 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:50,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:51,032 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:05:51,033 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:51,033 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:51,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:51,197 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:05:51,309 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:05:51,367 INFO L85 PathProgramCache]: Analyzing trace with hash -1170567276, now seen corresponding path program 149 times [2024-05-06 04:05:51,367 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:51,368 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:51,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:51,549 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:05:51,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:51,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:51,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:51,716 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:05:51,769 INFO L85 PathProgramCache]: Analyzing trace with hash -1170567276, now seen corresponding path program 150 times [2024-05-06 04:05:51,770 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:51,770 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:51,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:51,937 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:05:51,937 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:51,937 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:51,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:52,114 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:05:52,210 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:05:52,254 INFO L85 PathProgramCache]: Analyzing trace with hash -1927846326, now seen corresponding path program 151 times [2024-05-06 04:05:52,255 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:52,255 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:52,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:52,423 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:05:52,423 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:52,423 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:52,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:52,607 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:05:52,821 INFO L85 PathProgramCache]: Analyzing trace with hash -166352257, now seen corresponding path program 152 times [2024-05-06 04:05:52,821 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:52,821 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:52,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:52,984 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:05:52,985 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:52,985 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:53,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:53,156 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:05:53,269 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:05:53,269 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:05:53,380 INFO L85 PathProgramCache]: Analyzing trace with hash -950701438, now seen corresponding path program 153 times [2024-05-06 04:05:53,381 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:53,381 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:53,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:53,559 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:05:53,559 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:05:53,559 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:05:53,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:05:53,739 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:05:53,931 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:05:53,931 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:06:02,473 WARN L854 $PredicateComparison]: unable to prove that (and (forall ((v_~q1~0.base_In_100 Int) (v_~q1~0.offset_In_100 Int) (v_~q1_front~0_In_145 Int)) (let ((.cse0 (select (select |c_#memory_int| v_~q1~0.base_In_100) (+ v_~q1~0.offset_In_100 (* v_~q1_front~0_In_145 4))))) (or (< 4294967295 .cse0) (< (+ 4294967295 .cse0) 0) (< v_~q1_front~0_In_145 0) (= .cse0 0)))) (forall ((v_~q2~0.offset_In_122 Int) (v_~q2~0.base_In_122 Int)) (= (select (select |c_#memory_int| v_~q2~0.base_In_122) (+ (* c_~q2_front~0 4) v_~q2~0.offset_In_122)) 0))) is different from false [2024-05-06 04:06:02,475 INFO L85 PathProgramCache]: Analyzing trace with hash -1331351467, now seen corresponding path program 154 times [2024-05-06 04:06:02,475 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:02,475 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:02,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:02,649 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:06:02,649 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:02,649 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:02,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:02,826 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:06:02,958 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:06:02,958 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:06:03,101 INFO L85 PathProgramCache]: Analyzing trace with hash 1677778343, now seen corresponding path program 155 times [2024-05-06 04:06:03,101 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:03,102 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:03,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:03,274 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:06:03,274 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:03,274 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:03,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:03,447 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:06:03,593 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:06:03,593 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:06:03,718 INFO L85 PathProgramCache]: Analyzing trace with hash 471521943, now seen corresponding path program 156 times [2024-05-06 04:06:03,718 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:03,718 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:03,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:04,059 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:06:04,060 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:04,060 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:04,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:04,233 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:06:04,329 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:06:04,375 INFO L85 PathProgramCache]: Analyzing trace with hash 1732279213, now seen corresponding path program 157 times [2024-05-06 04:06:04,375 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:04,375 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:04,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:04,551 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:06:04,551 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:04,551 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:04,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:04,726 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:06:04,864 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:06:04,864 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 04:06:04,983 INFO L85 PathProgramCache]: Analyzing trace with hash 1369784018, now seen corresponding path program 158 times [2024-05-06 04:06:04,983 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:04,983 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:05,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:05,167 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:06:05,168 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:05,168 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:05,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:05,360 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:06:05,475 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:06:05,540 INFO L85 PathProgramCache]: Analyzing trace with hash -486367542, now seen corresponding path program 159 times [2024-05-06 04:06:05,541 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:05,541 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:05,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:05,731 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:06:05,731 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:05,731 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:05,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:05,935 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:06:06,039 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:06:06,072 INFO L85 PathProgramCache]: Analyzing trace with hash 1362566457, now seen corresponding path program 160 times [2024-05-06 04:06:06,073 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:06,073 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:06,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:06,416 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 2 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:06:06,417 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:06,417 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:06,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:06,614 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 2 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:06:06,674 INFO L85 PathProgramCache]: Analyzing trace with hash -710111942, now seen corresponding path program 161 times [2024-05-06 04:06:06,674 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:06,674 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:06,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:06,913 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:06:06,913 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:06,913 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:06,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:07,128 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:06:07,245 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:06:07,245 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 04:06:07,375 INFO L85 PathProgramCache]: Analyzing trace with hash 2064883069, now seen corresponding path program 162 times [2024-05-06 04:06:07,375 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:07,375 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:07,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:07,602 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:06:07,602 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:07,602 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:07,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:07,824 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:06:07,923 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:06:07,966 INFO L85 PathProgramCache]: Analyzing trace with hash -413133441, now seen corresponding path program 163 times [2024-05-06 04:06:07,967 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:07,967 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:07,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:08,182 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:06:08,182 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:08,182 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:08,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:08,401 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:06:08,511 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:06:08,550 INFO L85 PathProgramCache]: Analyzing trace with hash -413133453, now seen corresponding path program 164 times [2024-05-06 04:06:08,550 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:08,550 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:08,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:08,899 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:06:08,899 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:08,899 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:08,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:09,112 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:06:09,170 INFO L85 PathProgramCache]: Analyzing trace with hash 77765696, now seen corresponding path program 165 times [2024-05-06 04:06:09,170 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:09,170 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:09,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:09,368 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:06:09,368 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:09,369 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:09,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:09,566 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:06:09,797 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:06:09,797 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:06:26,417 WARN L293 SmtUtils]: Spent 14.17s on a formula simplification. DAG size of input: 33 DAG size of output: 28 (called from [L 210] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.abduction.Abducer.solveAbductionProblem) [2024-05-06 04:06:28,422 WARN L854 $PredicateComparison]: unable to prove that (and (forall ((v_~q2~0.base_In_128 Int) (v_~q2~0.offset_In_128 Int)) (= (select (select |c_#memory_int| v_~q2~0.base_In_128) (+ (* c_~q2_front~0 4) v_~q2~0.offset_In_128)) 0)) (forall ((v_~q1~0.offset_In_105 Int) (v_~q1~0.base_In_105 Int) (v_~q1_front~0_In_150 Int)) (let ((.cse0 (select (select |c_#memory_int| v_~q1~0.base_In_105) (+ v_~q1~0.offset_In_105 (* v_~q1_front~0_In_150 4))))) (or (< 4294967295 .cse0) (< (+ 4294967295 .cse0) 0) (< v_~q1_front~0_In_150 0) (= 0 .cse0))))) is different from false [2024-05-06 04:06:28,424 INFO L85 PathProgramCache]: Analyzing trace with hash 2131944473, now seen corresponding path program 166 times [2024-05-06 04:06:28,424 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:28,424 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:28,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:28,638 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:06:28,638 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:28,639 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:28,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:28,844 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:06:28,960 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:06:28,961 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 04:06:29,109 INFO L85 PathProgramCache]: Analyzing trace with hash 1665770091, now seen corresponding path program 167 times [2024-05-06 04:06:29,109 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:29,109 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:29,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:29,316 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:06:29,316 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:29,316 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:29,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:29,658 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:06:29,746 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:06:29,780 INFO L85 PathProgramCache]: Analyzing trace with hash 99266129, now seen corresponding path program 168 times [2024-05-06 04:06:29,781 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:29,781 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:29,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:29,992 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:06:29,992 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:29,992 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:30,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:30,210 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-05-06 04:06:30,364 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:06:30,364 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:06:30,533 INFO L85 PathProgramCache]: Analyzing trace with hash 905506220, now seen corresponding path program 169 times [2024-05-06 04:06:30,533 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:30,533 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:30,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:30,824 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 04:06:30,824 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:30,824 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:30,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:31,072 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 04:06:31,294 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:06:31,294 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:06:50,193 WARN L293 SmtUtils]: Spent 16.25s on a formula simplification. DAG size of input: 33 DAG size of output: 28 (called from [L 210] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.abduction.Abducer.solveAbductionProblem) [2024-05-06 04:06:52,201 WARN L854 $PredicateComparison]: unable to prove that (and (forall ((v_~q1~0.base_In_108 Int) (v_~q1~0.offset_In_108 Int) (v_~q1_front~0_In_153 Int)) (let ((.cse0 (select (select |c_#memory_int| v_~q1~0.base_In_108) (+ (* v_~q1_front~0_In_153 4) v_~q1~0.offset_In_108)))) (or (< v_~q1_front~0_In_153 0) (< (+ 4294967295 .cse0) 0) (= .cse0 0) (< 4294967295 .cse0)))) (forall ((v_~q2~0.offset_In_130 Int) (v_~q2~0.base_In_130 Int)) (= (select (select |c_#memory_int| v_~q2~0.base_In_130) (+ (* c_~q2_front~0 4) v_~q2~0.offset_In_130)) 0))) is different from false [2024-05-06 04:06:52,203 INFO L85 PathProgramCache]: Analyzing trace with hash 905506220, now seen corresponding path program 170 times [2024-05-06 04:06:52,203 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:52,203 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:52,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:52,420 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 04:06:52,421 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:52,421 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:52,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:52,635 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 04:06:52,747 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:06:52,795 INFO L85 PathProgramCache]: Analyzing trace with hash -1994077384, now seen corresponding path program 171 times [2024-05-06 04:06:52,795 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:52,795 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:53,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:53,232 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 04:06:53,233 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:53,233 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:53,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:53,471 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 04:06:53,590 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:06:53,590 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 04:06:53,716 INFO L85 PathProgramCache]: Analyzing trace with hash -1994077384, now seen corresponding path program 172 times [2024-05-06 04:06:53,717 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:53,717 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:53,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:53,945 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 04:06:53,945 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:53,945 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:53,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:54,175 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 04:06:54,278 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:06:54,321 INFO L85 PathProgramCache]: Analyzing trace with hash -1686855900, now seen corresponding path program 173 times [2024-05-06 04:06:54,321 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:54,321 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:54,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:54,549 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 04:06:54,550 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:54,550 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:54,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:54,763 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 04:06:54,866 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:06:54,909 INFO L85 PathProgramCache]: Analyzing trace with hash -1686855900, now seen corresponding path program 174 times [2024-05-06 04:06:54,910 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:54,910 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:54,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:55,129 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 04:06:55,130 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:55,130 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:55,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:55,475 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 04:06:55,587 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:06:55,637 INFO L85 PathProgramCache]: Analyzing trace with hash -752924486, now seen corresponding path program 175 times [2024-05-06 04:06:55,637 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:55,637 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:55,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:55,852 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 04:06:55,853 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:55,853 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:55,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:56,080 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 04:06:56,193 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:06:56,193 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 04:06:56,324 INFO L85 PathProgramCache]: Analyzing trace with hash 589129403, now seen corresponding path program 176 times [2024-05-06 04:06:56,324 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:56,324 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:56,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:56,564 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 04:06:56,565 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:56,565 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:56,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:56,804 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 04:06:56,909 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:06:56,955 INFO L85 PathProgramCache]: Analyzing trace with hash 1083143169, now seen corresponding path program 177 times [2024-05-06 04:06:56,956 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:56,956 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:56,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:57,197 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 04:06:57,197 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:57,197 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:57,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:57,442 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2024-05-06 04:06:57,551 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:06:57,591 INFO L85 PathProgramCache]: Analyzing trace with hash -1130112014, now seen corresponding path program 178 times [2024-05-06 04:06:57,591 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:57,592 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:57,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:57,958 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:06:57,958 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:57,959 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:57,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:58,213 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:06:58,272 INFO L85 PathProgramCache]: Analyzing trace with hash -673733224, now seen corresponding path program 179 times [2024-05-06 04:06:58,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:58,272 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:58,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:58,522 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:06:58,522 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:58,522 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:58,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:58,769 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:06:58,878 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:06:58,879 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 04:06:59,103 INFO L85 PathProgramCache]: Analyzing trace with hash -1837570592, now seen corresponding path program 180 times [2024-05-06 04:06:59,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:59,103 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:59,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:59,349 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:06:59,349 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:59,349 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:59,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:59,589 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:06:59,644 INFO L85 PathProgramCache]: Analyzing trace with hash -2053306125, now seen corresponding path program 181 times [2024-05-06 04:06:59,644 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:59,645 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:06:59,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:06:59,883 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:06:59,883 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:06:59,884 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:00,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:00,244 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:07:00,458 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:07:00,459 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:07:01,420 INFO L85 PathProgramCache]: Analyzing trace with hash -1686839031, now seen corresponding path program 3 times [2024-05-06 04:07:01,420 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:01,420 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:01,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:01,668 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 04:07:01,668 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:01,668 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:01,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:01,885 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 04:07:01,988 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:07:01,988 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 04:07:02,096 INFO L85 PathProgramCache]: Analyzing trace with hash -752401541, now seen corresponding path program 4 times [2024-05-06 04:07:02,096 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:02,096 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:02,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:02,346 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 04:07:02,347 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:02,347 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:02,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:02,569 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 04:07:02,658 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:07:02,700 INFO L85 PathProgramCache]: Analyzing trace with hash -1849610431, now seen corresponding path program 5 times [2024-05-06 04:07:02,700 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:02,700 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:02,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:02,919 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 04:07:02,919 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:02,919 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:03,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:03,269 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-05-06 04:07:03,489 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:07:03,490 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:07:04,813 INFO L85 PathProgramCache]: Analyzing trace with hash 1326051795, now seen corresponding path program 1 times [2024-05-06 04:07:04,814 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:04,814 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:04,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:05,081 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 04:07:05,082 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:05,082 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:05,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:05,348 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 04:07:05,359 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION, ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES, ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (and 2 more)] === [2024-05-06 04:07:05,360 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2024-05-06 04:07:05,360 INFO L85 PathProgramCache]: Analyzing trace with hash -249473579, now seen corresponding path program 1 times [2024-05-06 04:07:05,363 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-05-06 04:07:05,363 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1287609961] [2024-05-06 04:07:05,363 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:05,364 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:05,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:05,666 INFO L134 CoverageAnalysis]: Checked inductivity of 459 backedges. 109 proven. 146 refuted. 0 times theorem prover too weak. 204 trivial. 0 not checked. [2024-05-06 04:07:05,667 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-05-06 04:07:05,667 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1287609961] [2024-05-06 04:07:05,667 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1287609961] provided 0 perfect and 1 imperfect interpolant sequences [2024-05-06 04:07:05,667 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1110231737] [2024-05-06 04:07:05,668 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:05,668 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-05-06 04:07:05,668 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 [2024-05-06 04:07:05,698 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-05-06 04:07:05,699 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2024-05-06 04:07:06,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:06,613 INFO L262 TraceCheckSpWp]: Trace formula consists of 844 conjuncts, 9 conjunts are in the unsatisfiable core [2024-05-06 04:07:06,622 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2024-05-06 04:07:06,827 INFO L134 CoverageAnalysis]: Checked inductivity of 459 backedges. 98 proven. 1 refuted. 0 times theorem prover too weak. 360 trivial. 0 not checked. [2024-05-06 04:07:06,827 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2024-05-06 04:07:07,071 INFO L134 CoverageAnalysis]: Checked inductivity of 459 backedges. 96 proven. 3 refuted. 0 times theorem prover too weak. 360 trivial. 0 not checked. [2024-05-06 04:07:07,071 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1110231737] provided 0 perfect and 2 imperfect interpolant sequences [2024-05-06 04:07:07,071 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-05-06 04:07:07,072 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9] total 19 [2024-05-06 04:07:07,073 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1259592170] [2024-05-06 04:07:07,073 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-05-06 04:07:07,076 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 19 states [2024-05-06 04:07:07,076 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-05-06 04:07:07,078 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2024-05-06 04:07:07,078 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=77, Invalid=265, Unknown=0, NotChecked=0, Total=342 [2024-05-06 04:07:07,079 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-05-06 04:07:07,079 INFO L495 AbstractCegarLoop]: Abstraction has currently 0 states, but on-demand construction may add more states [2024-05-06 04:07:07,079 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 19 states, 19 states have (on average 15.842105263157896) internal successors, (301), 19 states have internal predecessors, (301), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-05-06 04:07:07,080 INFO L154 InterpolantAutomaton]: Switched to On-DemandConstruction mode: deterministic interpolant automaton has 2 states. [2024-05-06 04:07:07,595 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:07:07,646 INFO L85 PathProgramCache]: Analyzing trace with hash 97054817, now seen corresponding path program 3 times [2024-05-06 04:07:07,647 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:07,647 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:07,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 04:07:07,802 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 04:07:07,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 04:07:07,996 INFO L85 PathProgramCache]: Analyzing trace with hash -1286267118, now seen corresponding path program 4 times [2024-05-06 04:07:07,996 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:07,996 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:08,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:08,176 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:07:08,176 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:08,176 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:08,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:08,316 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:07:08,421 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:07:08,466 INFO L85 PathProgramCache]: Analyzing trace with hash -1725239752, now seen corresponding path program 182 times [2024-05-06 04:07:08,466 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:08,466 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:08,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:08,601 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:07:08,601 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:08,601 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:08,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:08,752 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-05-06 04:07:08,817 INFO L85 PathProgramCache]: Analyzing trace with hash -1942823918, now seen corresponding path program 183 times [2024-05-06 04:07:08,817 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:08,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:08,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:09,335 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 3 proven. 13 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 04:07:09,335 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:09,336 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:09,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:09,509 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 3 proven. 13 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-05-06 04:07:09,619 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:07:09,671 INFO L85 PathProgramCache]: Analyzing trace with hash 1276141679, now seen corresponding path program 184 times [2024-05-06 04:07:09,671 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:09,671 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:09,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:09,953 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 2 proven. 11 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:07:09,954 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:09,954 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:09,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:10,152 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 2 proven. 11 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:07:10,214 INFO L85 PathProgramCache]: Analyzing trace with hash 905687227, now seen corresponding path program 185 times [2024-05-06 04:07:10,214 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:10,214 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:10,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:10,373 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2024-05-06 04:07:10,373 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:10,373 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:10,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:10,658 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2024-05-06 04:07:10,884 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:07:10,884 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:07:15,925 INFO L85 PathProgramCache]: Analyzing trace with hash 824967838, now seen corresponding path program 186 times [2024-05-06 04:07:15,925 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:15,926 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:15,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:16,117 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 04:07:16,118 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:16,118 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:16,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:16,282 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 04:07:16,513 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:07:16,514 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:07:36,093 WARN L293 SmtUtils]: Spent 17.01s on a formula simplification. DAG size of input: 33 DAG size of output: 28 (called from [L 210] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.abduction.Abducer.solveAbductionProblem) [2024-05-06 04:07:38,105 WARN L854 $PredicateComparison]: unable to prove that (and (forall ((v_~q2~0.base_In_138 Int) (v_~q2~0.offset_In_138 Int)) (= (select (select |c_#memory_int| v_~q2~0.base_In_138) (+ (* c_~q2_front~0 4) v_~q2~0.offset_In_138)) 0)) (forall ((v_~q1~0.base_In_122 Int) (v_~q1_front~0_In_171 Int) (v_~q1~0.offset_In_122 Int)) (let ((.cse0 (select (select |c_#memory_int| v_~q1~0.base_In_122) (+ v_~q1~0.offset_In_122 (* v_~q1_front~0_In_171 4))))) (or (= .cse0 0) (< v_~q1_front~0_In_171 0) (< 4294967295 .cse0) (< (+ .cse0 4294967295) 0))))) is different from false [2024-05-06 04:07:38,108 INFO L85 PathProgramCache]: Analyzing trace with hash 2088473701, now seen corresponding path program 187 times [2024-05-06 04:07:38,108 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:38,108 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:38,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:38,332 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2024-05-06 04:07:38,332 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:38,333 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:38,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:38,490 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2024-05-06 04:07:38,557 INFO L85 PathProgramCache]: Analyzing trace with hash -862359559, now seen corresponding path program 188 times [2024-05-06 04:07:38,557 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:38,557 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:38,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:38,756 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 1 proven. 12 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 04:07:38,757 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:38,757 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:38,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:39,136 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 1 proven. 12 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2024-05-06 04:07:39,256 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:07:39,256 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 04:07:39,398 INFO L85 PathProgramCache]: Analyzing trace with hash 866140773, now seen corresponding path program 189 times [2024-05-06 04:07:39,398 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:39,398 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:39,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:39,556 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 04:07:39,556 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:39,556 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:39,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:39,710 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 04:07:39,821 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:07:39,862 INFO L85 PathProgramCache]: Analyzing trace with hash 1080561047, now seen corresponding path program 190 times [2024-05-06 04:07:39,862 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:39,862 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:39,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:40,027 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 04:07:40,027 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:40,027 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:40,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:40,206 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 04:07:40,330 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:07:40,379 INFO L85 PathProgramCache]: Analyzing trace with hash -459433444, now seen corresponding path program 191 times [2024-05-06 04:07:40,379 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:40,379 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:40,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:40,539 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 04:07:40,539 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:40,540 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:40,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:40,698 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 04:07:40,759 INFO L85 PathProgramCache]: Analyzing trace with hash -1357534034, now seen corresponding path program 192 times [2024-05-06 04:07:40,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:40,760 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:40,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:40,964 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 1 proven. 12 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:07:40,964 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:40,964 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:40,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:41,170 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 1 proven. 12 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:07:41,295 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:07:41,296 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 20 [2024-05-06 04:07:41,440 INFO L85 PathProgramCache]: Analyzing trace with hash -291915146, now seen corresponding path program 193 times [2024-05-06 04:07:41,441 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:41,441 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:41,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:41,708 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 04:07:41,708 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:41,708 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:41,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:41,861 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 04:07:42,122 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:07:42,123 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:07:49,575 INFO L85 PathProgramCache]: Analyzing trace with hash 334868377, now seen corresponding path program 194 times [2024-05-06 04:07:49,575 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:49,575 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:49,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:49,726 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 04:07:49,726 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:49,727 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:49,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:49,879 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 04:07:49,986 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 4 [2024-05-06 04:07:50,033 INFO L85 PathProgramCache]: Analyzing trace with hash -314009404, now seen corresponding path program 195 times [2024-05-06 04:07:50,034 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:50,034 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:50,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:50,185 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 04:07:50,185 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:50,185 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:50,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:50,336 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 5 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2024-05-06 04:07:50,397 INFO L85 PathProgramCache]: Analyzing trace with hash -1144356090, now seen corresponding path program 196 times [2024-05-06 04:07:50,397 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:50,398 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:50,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:50,488 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 23 trivial. 0 not checked. [2024-05-06 04:07:50,489 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:50,489 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:50,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:50,577 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 23 trivial. 0 not checked. [2024-05-06 04:07:50,579 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-05-06 04:07:50,588 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=174, Invalid=2400, Unknown=8, NotChecked=840, Total=3422 [2024-05-06 04:07:50,785 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:07:50,886 INFO L85 PathProgramCache]: Analyzing trace with hash 97054817, now seen corresponding path program 5 times [2024-05-06 04:07:50,886 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:50,886 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:50,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 04:07:50,967 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 04:07:50,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 04:07:51,150 INFO L85 PathProgramCache]: Analyzing trace with hash -1286267118, now seen corresponding path program 6 times [2024-05-06 04:07:51,150 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:51,150 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:51,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:51,437 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 04:07:51,437 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:51,437 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:51,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:51,497 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2024-05-06 04:07:51,498 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-05-06 04:07:51,498 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=177, Invalid=2499, Unknown=8, NotChecked=856, Total=3540 [2024-05-06 04:07:51,658 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:07:51,746 INFO L85 PathProgramCache]: Analyzing trace with hash 97054817, now seen corresponding path program 7 times [2024-05-06 04:07:51,746 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:51,746 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:51,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 04:07:51,787 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-05-06 04:07:51,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-05-06 04:07:52,194 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:07:52,273 INFO L85 PathProgramCache]: Analyzing trace with hash 265409842, now seen corresponding path program 197 times [2024-05-06 04:07:52,274 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:52,274 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:52,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:52,463 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 13 proven. 17 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-06 04:07:52,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:52,464 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:52,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:52,668 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 13 proven. 17 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2024-05-06 04:07:52,951 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:07:52,951 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:07:59,766 INFO L85 PathProgramCache]: Analyzing trace with hash -702113739, now seen corresponding path program 198 times [2024-05-06 04:07:59,767 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:59,767 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:07:59,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:07:59,972 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2024-05-06 04:07:59,972 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:07:59,972 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:00,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:00,170 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2024-05-06 04:08:00,308 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:08:00,362 INFO L85 PathProgramCache]: Analyzing trace with hash -107019825, now seen corresponding path program 199 times [2024-05-06 04:08:00,363 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:00,363 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:00,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:00,575 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2024-05-06 04:08:00,575 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:00,575 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:00,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:00,946 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2024-05-06 04:08:01,424 INFO L85 PathProgramCache]: Analyzing trace with hash -1862823297, now seen corresponding path program 200 times [2024-05-06 04:08:01,424 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:01,424 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:01,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:01,653 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2024-05-06 04:08:01,653 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:01,654 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:01,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:01,852 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2024-05-06 04:08:02,021 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:08:02,022 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:08:02,206 INFO L85 PathProgramCache]: Analyzing trace with hash -1625310344, now seen corresponding path program 201 times [2024-05-06 04:08:02,206 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:02,206 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:02,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:02,422 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2024-05-06 04:08:02,422 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:02,422 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:02,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:02,646 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2024-05-06 04:08:02,758 INFO L85 PathProgramCache]: Analyzing trace with hash 1444882409, now seen corresponding path program 202 times [2024-05-06 04:08:02,758 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:02,758 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:02,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:02,969 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2024-05-06 04:08:02,969 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:02,970 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:03,000 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:03,297 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2024-05-06 04:08:03,439 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:08:03,440 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:08:03,594 INFO L85 PathProgramCache]: Analyzing trace with hash -33223318, now seen corresponding path program 203 times [2024-05-06 04:08:03,595 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:03,595 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:03,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:03,808 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2024-05-06 04:08:03,808 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:03,808 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:03,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:04,004 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2024-05-06 04:08:04,103 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:08:04,156 INFO L85 PathProgramCache]: Analyzing trace with hash -1029921990, now seen corresponding path program 204 times [2024-05-06 04:08:04,156 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:04,156 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:04,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:04,364 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2024-05-06 04:08:04,364 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:04,364 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:04,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:04,568 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2024-05-06 04:08:04,784 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:08:04,784 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:08:07,388 INFO L85 PathProgramCache]: Analyzing trace with hash -1021339674, now seen corresponding path program 205 times [2024-05-06 04:08:07,388 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:07,389 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:07,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:07,591 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2024-05-06 04:08:07,592 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:07,592 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:07,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:07,897 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2024-05-06 04:08:08,167 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:08:08,167 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:08:10,962 INFO L85 PathProgramCache]: Analyzing trace with hash -393910643, now seen corresponding path program 206 times [2024-05-06 04:08:10,962 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:10,962 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:11,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:11,204 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2024-05-06 04:08:11,205 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:11,205 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:11,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:11,424 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2024-05-06 04:08:11,742 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:08:11,742 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:08:38,097 WARN L293 SmtUtils]: Spent 20.14s on a formula simplification. DAG size of input: 33 DAG size of output: 28 (called from [L 210] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.abduction.Abducer.solveAbductionProblem) [2024-05-06 04:08:40,102 WARN L854 $PredicateComparison]: unable to prove that (and (forall ((v_~q1~0.base_In_132 Int) (v_~q1_front~0_In_200 Int)) (let ((.cse0 (select (select |c_#memory_int| v_~q1~0.base_In_132) (+ (* v_~q1_front~0_In_200 4) c_~q1~0.offset)))) (or (= 0 .cse0) (< v_~q1_front~0_In_200 0) (< 4294967295 .cse0) (< (+ 4294967295 .cse0) 0)))) (forall ((v_~q2~0.offset_In_153 Int) (v_~q2~0.base_In_153 Int)) (= (select (select |c_#memory_int| v_~q2~0.base_In_153) (+ (* c_~q2_front~0 4) v_~q2~0.offset_In_153)) 0))) is different from false [2024-05-06 04:08:40,104 INFO L85 PathProgramCache]: Analyzing trace with hash -37353266, now seen corresponding path program 207 times [2024-05-06 04:08:40,104 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:40,104 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:40,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:40,335 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2024-05-06 04:08:40,335 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:40,335 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:40,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:40,671 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2024-05-06 04:08:40,941 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:08:40,941 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:08:41,635 INFO L85 PathProgramCache]: Analyzing trace with hash -32946457, now seen corresponding path program 208 times [2024-05-06 04:08:41,636 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:41,636 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:41,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:41,831 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2024-05-06 04:08:41,832 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:41,832 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:41,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:42,022 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2024-05-06 04:08:42,103 INFO L85 PathProgramCache]: Analyzing trace with hash -1021339299, now seen corresponding path program 209 times [2024-05-06 04:08:42,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:42,103 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:42,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:42,301 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2024-05-06 04:08:42,301 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:42,301 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:42,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:42,508 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2024-05-06 04:08:42,626 INFO L85 PathProgramCache]: Analyzing trace with hash -1596746337, now seen corresponding path program 210 times [2024-05-06 04:08:42,626 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:42,626 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:42,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:42,825 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2024-05-06 04:08:42,826 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:42,826 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:42,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:43,126 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2024-05-06 04:08:43,248 INFO L85 PathProgramCache]: Analyzing trace with hash 2040471967, now seen corresponding path program 211 times [2024-05-06 04:08:43,249 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:43,249 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:43,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:43,455 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2024-05-06 04:08:43,456 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:43,456 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:43,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:43,673 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2024-05-06 04:08:43,841 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:08:43,841 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:08:44,021 INFO L85 PathProgramCache]: Analyzing trace with hash -2121193215, now seen corresponding path program 212 times [2024-05-06 04:08:44,021 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:44,021 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:44,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:44,235 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:08:44,235 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:44,235 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:44,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:44,449 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:08:44,543 INFO L85 PathProgramCache]: Analyzing trace with hash 1642813234, now seen corresponding path program 213 times [2024-05-06 04:08:44,544 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:44,544 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:44,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:44,776 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:08:44,777 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:44,777 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:44,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:45,115 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:08:45,218 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:08:45,267 INFO L85 PathProgramCache]: Analyzing trace with hash 2029948265, now seen corresponding path program 214 times [2024-05-06 04:08:45,268 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:45,268 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:45,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:45,495 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:08:45,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:45,496 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:45,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:45,721 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:08:46,703 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:08:46,759 INFO L85 PathProgramCache]: Analyzing trace with hash 1119429483, now seen corresponding path program 215 times [2024-05-06 04:08:46,759 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:46,759 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:46,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:46,985 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:08:46,985 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:46,986 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:47,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:47,211 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:08:47,343 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:08:47,387 INFO L85 PathProgramCache]: Analyzing trace with hash 2029979048, now seen corresponding path program 7 times [2024-05-06 04:08:47,387 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:47,387 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:47,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:47,705 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:08:47,705 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:47,706 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:47,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:47,929 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:08:48,094 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:08:48,095 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:08:48,226 INFO L85 PathProgramCache]: Analyzing trace with hash 56387863, now seen corresponding path program 8 times [2024-05-06 04:08:48,226 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:48,226 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:48,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:48,464 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:08:48,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:48,464 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:48,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:48,703 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:08:48,809 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:08:48,879 INFO L85 PathProgramCache]: Analyzing trace with hash 1748024621, now seen corresponding path program 9 times [2024-05-06 04:08:48,879 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:48,879 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:48,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:49,115 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:08:49,116 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:49,116 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:49,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:49,351 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:08:49,600 INFO L85 PathProgramCache]: Analyzing trace with hash 851703678, now seen corresponding path program 10 times [2024-05-06 04:08:49,601 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:49,601 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:49,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:49,922 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:08:49,922 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:49,922 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:49,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:50,149 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:08:50,298 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:08:50,299 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:08:50,426 INFO L85 PathProgramCache]: Analyzing trace with hash -1802134055, now seen corresponding path program 11 times [2024-05-06 04:08:50,426 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:50,427 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:50,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:50,660 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:08:50,660 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:50,660 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:50,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:50,897 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:08:50,986 INFO L85 PathProgramCache]: Analyzing trace with hash -978979318, now seen corresponding path program 12 times [2024-05-06 04:08:50,986 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:50,986 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:51,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:51,257 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:08:51,258 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:51,258 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:51,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:51,618 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:08:51,721 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:08:51,777 INFO L85 PathProgramCache]: Analyzing trace with hash 342577817, now seen corresponding path program 7 times [2024-05-06 04:08:51,777 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:51,777 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:51,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:52,005 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:08:52,006 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:52,006 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:52,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:52,235 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:08:52,462 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:08:52,462 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:08:52,667 INFO L85 PathProgramCache]: Analyzing trace with hash 1210653510, now seen corresponding path program 8 times [2024-05-06 04:08:52,667 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:52,667 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:52,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:52,907 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:08:52,907 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:52,907 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:52,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:53,156 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:08:53,262 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:08:53,311 INFO L85 PathProgramCache]: Analyzing trace with hash -1124445986, now seen corresponding path program 9 times [2024-05-06 04:08:53,311 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:53,311 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:53,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:53,561 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:08:53,561 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:53,561 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:53,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:53,917 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:08:54,175 INFO L85 PathProgramCache]: Analyzing trace with hash 1953391599, now seen corresponding path program 10 times [2024-05-06 04:08:54,175 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:54,175 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:54,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:54,403 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:08:54,404 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:54,404 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:54,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:54,631 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:08:54,801 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:08:54,801 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:08:55,013 INFO L85 PathProgramCache]: Analyzing trace with hash -647868408, now seen corresponding path program 11 times [2024-05-06 04:08:55,013 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:55,013 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:55,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:55,271 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:08:55,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:55,272 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:55,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:55,518 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:08:55,633 INFO L85 PathProgramCache]: Analyzing trace with hash 168745081, now seen corresponding path program 12 times [2024-05-06 04:08:55,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:55,634 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:55,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:56,003 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:08:56,003 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:56,003 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:56,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:56,252 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:08:56,359 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:08:56,433 INFO L85 PathProgramCache]: Analyzing trace with hash 1119429514, now seen corresponding path program 7 times [2024-05-06 04:08:56,434 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:56,434 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:56,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:56,658 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:08:56,658 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:56,658 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:56,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:56,878 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:08:57,112 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:08:57,113 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:08:57,311 INFO L85 PathProgramCache]: Analyzing trace with hash -2054633099, now seen corresponding path program 8 times [2024-05-06 04:08:57,311 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:57,311 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:57,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:57,548 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:08:57,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:57,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:57,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:57,891 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:08:57,997 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:08:58,049 INFO L85 PathProgramCache]: Analyzing trace with hash 730884239, now seen corresponding path program 9 times [2024-05-06 04:08:58,050 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:58,050 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:58,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:58,291 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:08:58,292 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:58,292 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:58,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:58,529 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:08:58,755 INFO L85 PathProgramCache]: Analyzing trace with hash 882398304, now seen corresponding path program 10 times [2024-05-06 04:08:58,755 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:58,755 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:58,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:58,982 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:08:58,982 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:58,982 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:59,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:59,207 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:08:59,405 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:08:59,405 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:08:59,616 INFO L85 PathProgramCache]: Analyzing trace with hash 381812279, now seen corresponding path program 11 times [2024-05-06 04:08:59,617 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:59,617 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:59,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:08:59,852 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:08:59,853 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:08:59,853 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:08:59,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:09:00,196 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:09:00,311 INFO L85 PathProgramCache]: Analyzing trace with hash 1849407208, now seen corresponding path program 12 times [2024-05-06 04:09:00,311 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:09:00,311 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:09:00,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:09:00,556 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:09:00,556 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:09:00,556 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:09:00,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:09:00,802 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:09:00,929 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:09:01,017 INFO L85 PathProgramCache]: Analyzing trace with hash -102436740, now seen corresponding path program 216 times [2024-05-06 04:09:01,018 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:09:01,018 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:09:01,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:09:01,242 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:09:01,242 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:09:01,242 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:09:01,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:09:01,477 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:09:01,708 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:09:01,709 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:09:01,890 INFO L85 PathProgramCache]: Analyzing trace with hash 575630531, now seen corresponding path program 217 times [2024-05-06 04:09:01,890 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:09:01,891 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:09:01,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:09:02,224 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:09:02,224 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:09:02,224 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:09:02,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:09:02,459 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:09:02,562 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:09:02,620 INFO L85 PathProgramCache]: Analyzing trace with hash 664678145, now seen corresponding path program 218 times [2024-05-06 04:09:02,620 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:09:02,620 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:09:02,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:09:02,858 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:09:02,859 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:09:02,859 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:09:02,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:09:03,109 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:09:03,371 INFO L85 PathProgramCache]: Analyzing trace with hash -1504683950, now seen corresponding path program 219 times [2024-05-06 04:09:03,371 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:09:03,380 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:09:03,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:09:03,626 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:09:03,626 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:09:03,626 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:09:03,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:09:03,976 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:09:04,131 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:09:04,131 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:09:04,296 INFO L85 PathProgramCache]: Analyzing trace with hash -1282891387, now seen corresponding path program 220 times [2024-05-06 04:09:04,297 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:09:04,297 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:09:04,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:09:04,546 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:09:04,546 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:09:04,546 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:09:04,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:09:04,787 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:09:04,879 INFO L85 PathProgramCache]: Analyzing trace with hash -202981706, now seen corresponding path program 221 times [2024-05-06 04:09:04,879 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:09:04,879 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:09:04,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:09:05,158 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:09:05,159 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:09:05,159 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:09:05,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:09:05,401 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:09:05,679 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:09:05,679 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:09:06,523 INFO L85 PathProgramCache]: Analyzing trace with hash -1804434107, now seen corresponding path program 222 times [2024-05-06 04:09:06,523 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:09:06,523 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:09:06,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:09:06,741 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:09:06,742 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:09:06,742 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:09:06,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:09:06,958 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:09:07,360 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:09:07,360 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:09:10,534 INFO L85 PathProgramCache]: Analyzing trace with hash -612396906, now seen corresponding path program 223 times [2024-05-06 04:09:10,535 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:09:10,535 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:09:10,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:09:10,742 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 0 proven. 17 refuted. 0 times theorem prover too weak. 44 trivial. 0 not checked. [2024-05-06 04:09:10,742 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:09:10,742 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:09:10,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:09:10,948 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 0 proven. 17 refuted. 0 times theorem prover too weak. 44 trivial. 0 not checked. [2024-05-06 04:09:11,201 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:09:11,201 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:09:19,921 WARN L854 $PredicateComparison]: unable to prove that (and (forall ((v_~q2~0.offset_In_187 Int) (v_~q2~0.base_In_187 Int)) (= (select (select |c_#memory_int| v_~q2~0.base_In_187) (+ (* c_~q2_front~0 4) v_~q2~0.offset_In_187)) 0)) (forall ((v_~q1_front~0_In_258 Int) (v_~q1~0.offset_In_136 Int) (v_~q1~0.base_In_136 Int)) (let ((.cse0 (select (select |c_#memory_int| v_~q1~0.base_In_136) (+ (* v_~q1_front~0_In_258 4) v_~q1~0.offset_In_136)))) (or (< v_~q1_front~0_In_258 0) (= .cse0 0) (< 4294967295 .cse0) (< (+ .cse0 4294967295) 0))))) is different from false [2024-05-06 04:09:19,923 INFO L85 PathProgramCache]: Analyzing trace with hash 1642813223, now seen corresponding path program 224 times [2024-05-06 04:09:19,923 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:09:19,923 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:09:19,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:09:20,147 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:09:20,147 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:09:20,147 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:09:20,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:09:20,367 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:09:20,460 INFO L85 PathProgramCache]: Analyzing trace with hash -1804430097, now seen corresponding path program 225 times [2024-05-06 04:09:20,461 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:09:20,461 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:09:20,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:09:20,688 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:09:20,689 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:09:20,689 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:09:20,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:09:20,941 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:09:21,194 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:09:21,194 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:09:38,015 WARN L293 SmtUtils]: Spent 14.33s on a formula simplification. DAG size of input: 33 DAG size of output: 28 (called from [L 210] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.abduction.Abducer.solveAbductionProblem) [2024-05-06 04:09:40,021 WARN L854 $PredicateComparison]: unable to prove that (and (forall ((v_~q2~0.offset_In_188 Int) (v_~q2~0.base_In_188 Int)) (= (select (select |c_#memory_int| v_~q2~0.base_In_188) (+ (* c_~q2_front~0 4) v_~q2~0.offset_In_188)) 0)) (forall ((v_~q1~0.offset_In_137 Int) (v_~q1~0.base_In_137 Int) (v_~q1_front~0_In_260 Int)) (let ((.cse0 (select (select |c_#memory_int| v_~q1~0.base_In_137) (+ (* v_~q1_front~0_In_260 4) v_~q1~0.offset_In_137)))) (or (< v_~q1_front~0_In_260 0) (< (+ 4294967295 .cse0) 0) (< 4294967295 .cse0) (= .cse0 0))))) is different from false [2024-05-06 04:09:40,023 INFO L85 PathProgramCache]: Analyzing trace with hash 1070141503, now seen corresponding path program 226 times [2024-05-06 04:09:40,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:09:40,024 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:09:40,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:09:40,388 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:09:40,388 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:09:40,388 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:09:40,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:09:40,631 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:09:40,915 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:09:40,915 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:09:41,428 INFO L85 PathProgramCache]: Analyzing trace with hash -1332479368, now seen corresponding path program 227 times [2024-05-06 04:09:41,429 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:09:41,429 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:09:41,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:09:41,662 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:09:41,662 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:09:41,662 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:09:41,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:09:41,888 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:09:42,082 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:09:42,082 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:09:42,270 INFO L85 PathProgramCache]: Analyzing trace with hash 1642813412, now seen corresponding path program 228 times [2024-05-06 04:09:42,270 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:09:42,270 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:09:42,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:09:42,589 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:09:42,589 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:09:42,589 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:09:42,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:09:42,804 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:09:42,936 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:09:43,002 INFO L85 PathProgramCache]: Analyzing trace with hash -612390912, now seen corresponding path program 229 times [2024-05-06 04:09:43,002 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:09:43,002 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:09:43,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:09:43,224 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:09:43,224 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:09:43,224 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:09:43,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:09:43,443 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:09:43,615 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:09:43,616 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:09:43,789 INFO L85 PathProgramCache]: Analyzing trace with hash 1284277673, now seen corresponding path program 230 times [2024-05-06 04:09:43,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:09:43,789 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:09:43,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:09:44,017 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:09:44,017 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:09:44,017 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:09:44,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:09:44,359 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:09:44,470 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:09:44,522 INFO L85 PathProgramCache]: Analyzing trace with hash 1157903067, now seen corresponding path program 231 times [2024-05-06 04:09:44,522 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:09:44,522 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:09:44,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:09:44,750 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:09:44,751 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:09:44,751 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:09:44,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:09:44,978 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:09:45,239 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:09:45,240 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:09:46,633 INFO L85 PathProgramCache]: Analyzing trace with hash -612366123, now seen corresponding path program 6 times [2024-05-06 04:09:46,633 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:09:46,633 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:09:46,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:09:46,847 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:09:46,848 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:09:46,848 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:09:46,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:09:47,061 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:09:47,307 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:09:47,307 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:10:10,240 WARN L293 SmtUtils]: Spent 20.23s on a formula simplification. DAG size of input: 33 DAG size of output: 28 (called from [L 210] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.abduction.Abducer.solveAbductionProblem) [2024-05-06 04:10:12,246 WARN L854 $PredicateComparison]: unable to prove that (and (forall ((v_~q1~0.offset_In_140 Int) (v_~q1~0.base_In_140 Int) (v_~q1_front~0_In_267 Int)) (let ((.cse0 (select (select |c_#memory_int| v_~q1~0.base_In_140) (+ v_~q1~0.offset_In_140 (* v_~q1_front~0_In_267 4))))) (or (< (+ .cse0 4294967295) 0) (< 4294967295 .cse0) (< v_~q1_front~0_In_267 0) (= .cse0 0)))) (forall ((v_~q2~0.offset_In_195 Int) (v_~q2~0.base_In_195 Int)) (= (select (select |c_#memory_int| v_~q2~0.base_In_195) (+ (* c_~q2_front~0 4) v_~q2~0.offset_In_195)) 0))) is different from false [2024-05-06 04:10:12,249 INFO L85 PathProgramCache]: Analyzing trace with hash -1525083498, now seen corresponding path program 7 times [2024-05-06 04:10:12,249 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:10:12,249 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:10:12,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:10:12,492 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:10:12,492 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:10:12,492 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:10:12,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:10:12,730 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:10:13,001 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:10:13,001 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:10:15,637 INFO L85 PathProgramCache]: Analyzing trace with hash 1642814215, now seen corresponding path program 3 times [2024-05-06 04:10:15,637 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:10:15,637 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:10:15,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:10:15,855 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:10:15,855 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:10:15,855 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:10:15,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:10:16,187 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:10:16,493 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:10:16,493 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:10:27,520 WARN L293 SmtUtils]: Spent 8.12s on a formula simplification that was a NOOP. DAG size: 37 (called from [L 210] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.abduction.Abducer.solveAbductionProblem) [2024-05-06 04:10:29,759 INFO L85 PathProgramCache]: Analyzing trace with hash 1671567524, now seen corresponding path program 4 times [2024-05-06 04:10:29,759 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:10:29,759 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:10:29,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:10:30,031 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:10:30,032 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:10:30,032 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:10:30,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:10:30,309 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:10:30,594 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:10:30,594 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:10:31,149 INFO L85 PathProgramCache]: Analyzing trace with hash -1332479337, now seen corresponding path program 3 times [2024-05-06 04:10:31,149 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:10:31,149 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:10:31,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:10:31,374 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:10:31,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:10:31,374 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:10:31,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:10:31,600 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:10:31,899 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:10:31,899 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:10:32,434 INFO L85 PathProgramCache]: Analyzing trace with hash 411826964, now seen corresponding path program 4 times [2024-05-06 04:10:32,434 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:10:32,434 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:10:32,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:10:32,681 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:10:32,681 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:10:32,681 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:10:32,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:10:32,926 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:10:33,169 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:10:33,169 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:10:45,243 INFO L85 PathProgramCache]: Analyzing trace with hash -2121193206, now seen corresponding path program 232 times [2024-05-06 04:10:45,244 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:10:45,244 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:10:45,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:10:45,510 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:10:45,510 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:10:45,510 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:10:45,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:10:45,785 INFO L134 CoverageAnalysis]: Checked inductivity of 61 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2024-05-06 04:10:46,095 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:10:46,096 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:11:04,940 WARN L293 SmtUtils]: Spent 16.22s on a formula simplification. DAG size of input: 33 DAG size of output: 28 (called from [L 210] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.abduction.Abducer.solveAbductionProblem) [2024-05-06 04:11:06,946 WARN L854 $PredicateComparison]: unable to prove that (and (forall ((v_~q1~0.offset_In_146 Int) (v_~q1_front~0_In_273 Int) (v_~q1~0.base_In_146 Int)) (let ((.cse0 (select (select |c_#memory_int| v_~q1~0.base_In_146) (+ v_~q1~0.offset_In_146 (* v_~q1_front~0_In_273 4))))) (or (= .cse0 0) (< (+ 4294967295 .cse0) 0) (< 4294967295 .cse0) (< v_~q1_front~0_In_273 0)))) (forall ((v_~q2~0.offset_In_201 Int) (v_~q2~0.base_In_201 Int)) (= (select (select |c_#memory_int| v_~q2~0.base_In_201) (+ (* c_~q2_front~0 4) v_~q2~0.offset_In_201)) 0))) is different from false [2024-05-06 04:11:06,949 INFO L85 PathProgramCache]: Analyzing trace with hash 58744321, now seen corresponding path program 233 times [2024-05-06 04:11:06,949 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:11:06,949 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:11:06,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:11:07,227 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:11:07,227 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:11:07,227 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:11:07,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:11:07,482 INFO L134 CoverageAnalysis]: Checked inductivity of 62 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2024-05-06 04:11:07,766 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:11:07,766 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:11:08,657 INFO L85 PathProgramCache]: Analyzing trace with hash 1114939249, now seen corresponding path program 234 times [2024-05-06 04:11:08,658 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:11:08,658 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:11:08,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:11:08,866 INFO L134 CoverageAnalysis]: Checked inductivity of 54 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 04:11:08,866 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:11:08,866 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:11:08,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:11:09,073 INFO L134 CoverageAnalysis]: Checked inductivity of 54 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-05-06 04:11:09,242 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:11:09,242 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:11:09,450 INFO L85 PathProgramCache]: Analyzing trace with hash 203379199, now seen corresponding path program 235 times [2024-05-06 04:11:09,450 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:11:09,450 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:11:09,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:11:09,656 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 04:11:09,656 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:11:09,656 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:11:09,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:11:09,859 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 04:11:10,111 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:11:10,112 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:11:14,965 INFO L85 PathProgramCache]: Analyzing trace with hash 2009788724, now seen corresponding path program 236 times [2024-05-06 04:11:14,965 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:11:14,965 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:11:15,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:11:15,212 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 04:11:15,212 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:11:15,212 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:11:15,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:11:15,436 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 04:11:15,559 INFO L85 PathProgramCache]: Analyzing trace with hash -2121058128, now seen corresponding path program 237 times [2024-05-06 04:11:15,560 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:11:15,560 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:11:15,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:11:15,849 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 04:11:15,850 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:11:15,850 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:11:15,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:11:16,073 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 04:11:16,199 INFO L85 PathProgramCache]: Analyzing trace with hash -1328291668, now seen corresponding path program 238 times [2024-05-06 04:11:16,200 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:11:16,200 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:11:16,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:11:16,416 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 04:11:16,416 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:11:16,416 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:11:16,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:11:16,728 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2024-05-06 04:11:17,018 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:11:17,019 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:11:17,616 INFO L85 PathProgramCache]: Analyzing trace with hash 1772632427, now seen corresponding path program 239 times [2024-05-06 04:11:17,616 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:11:17,617 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:11:17,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:11:17,833 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2024-05-06 04:11:17,833 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:11:17,833 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:11:17,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:11:18,050 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2024-05-06 04:11:18,208 INFO L349 Elim1Store]: treesize reduction 4, result has 50.0 percent of original size [2024-05-06 04:11:18,208 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 42 treesize of output 22 [2024-05-06 04:11:18,531 INFO L85 PathProgramCache]: Analyzing trace with hash -1247988792, now seen corresponding path program 240 times [2024-05-06 04:11:18,531 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:11:18,531 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:11:18,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:11:18,722 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2024-05-06 04:11:18,723 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:11:18,723 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:11:18,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:11:19,036 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2024-05-06 04:11:19,334 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:11:19,335 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:11:24,636 INFO L85 PathProgramCache]: Analyzing trace with hash -1247988792, now seen corresponding path program 241 times [2024-05-06 04:11:24,636 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:11:24,636 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:11:24,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:11:24,940 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2024-05-06 04:11:24,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:11:24,940 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:11:24,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:11:25,145 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2024-05-06 04:11:25,249 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:11:25,302 INFO L85 PathProgramCache]: Analyzing trace with hash -32946020, now seen corresponding path program 242 times [2024-05-06 04:11:25,302 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:11:25,302 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:11:25,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:11:25,497 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2024-05-06 04:11:25,498 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:11:25,498 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:11:25,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:11:25,809 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2024-05-06 04:11:25,914 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 6 [2024-05-06 04:11:25,990 INFO L85 PathProgramCache]: Analyzing trace with hash -1021325760, now seen corresponding path program 243 times [2024-05-06 04:11:25,991 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:11:25,991 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:11:26,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:11:26,190 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2024-05-06 04:11:26,190 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:11:26,190 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:11:26,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:11:26,384 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2024-05-06 04:11:26,815 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:11:26,815 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:11:28,287 INFO L85 PathProgramCache]: Analyzing trace with hash 163585519, now seen corresponding path program 244 times [2024-05-06 04:11:28,287 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:11:28,287 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:11:28,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:11:28,464 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:11:28,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:11:28,464 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:11:28,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:11:28,761 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:11:29,220 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:11:29,220 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:11:48,014 WARN L293 SmtUtils]: Spent 16.16s on a formula simplification. DAG size of input: 33 DAG size of output: 28 (called from [L 210] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.abduction.Abducer.solveAbductionProblem) [2024-05-06 04:11:50,021 WARN L854 $PredicateComparison]: unable to prove that (and (forall ((v_~q1~0.offset_In_152 Int) (v_~q1~0.base_In_152 Int) (v_~q1_front~0_In_287 Int)) (let ((.cse0 (select (select |c_#memory_int| v_~q1~0.base_In_152) (+ v_~q1~0.offset_In_152 (* v_~q1_front~0_In_287 4))))) (or (< 4294967295 .cse0) (< v_~q1_front~0_In_287 0) (< (+ .cse0 4294967295) 0) (= .cse0 0)))) (forall ((v_~q2~0.base_In_213 Int) (v_~q2~0.offset_In_213 Int)) (= (select (select |c_#memory_int| v_~q2~0.base_In_213) (+ (* c_~q2_front~0 4) v_~q2~0.offset_In_213)) 0))) is different from false [2024-05-06 04:11:50,024 INFO L85 PathProgramCache]: Analyzing trace with hash -1708053876, now seen corresponding path program 8 times [2024-05-06 04:11:50,025 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:11:50,025 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:11:50,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:11:50,226 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:11:50,227 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:11:50,227 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:11:50,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:11:50,432 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:11:50,684 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:11:50,684 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:11:58,141 INFO L85 PathProgramCache]: Analyzing trace with hash 776185456, now seen corresponding path program 5 times [2024-05-06 04:11:58,141 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:11:58,141 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:11:58,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:11:58,359 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:11:58,359 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:11:58,359 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:11:58,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:11:58,560 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:11:58,846 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:11:58,846 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:12:21,937 WARN L293 SmtUtils]: Spent 20.51s on a formula simplification. DAG size of input: 33 DAG size of output: 28 (called from [L 210] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.abduction.Abducer.solveAbductionProblem) [2024-05-06 04:12:23,941 WARN L854 $PredicateComparison]: unable to prove that (and (forall ((v_~q2~0.base_In_215 Int) (v_~q2~0.offset_In_215 Int)) (= (select (select |c_#memory_int| v_~q2~0.base_In_215) (+ (* c_~q2_front~0 4) v_~q2~0.offset_In_215)) 0)) (forall ((v_~q1~0.base_In_154 Int) (v_~q1~0.offset_In_154 Int) (v_~q1_front~0_In_289 Int)) (let ((.cse0 (select (select |c_#memory_int| v_~q1~0.base_In_154) (+ (* v_~q1_front~0_In_289 4) v_~q1~0.offset_In_154)))) (or (< v_~q1_front~0_In_289 0) (< (+ 4294967295 .cse0) 0) (< 4294967295 .cse0) (= .cse0 0))))) is different from false [2024-05-06 04:12:23,942 INFO L85 PathProgramCache]: Analyzing trace with hash 163585550, now seen corresponding path program 5 times [2024-05-06 04:12:23,942 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:12:23,943 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:12:23,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:12:24,122 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:12:24,123 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:12:24,123 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:12:24,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:12:24,303 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:12:24,571 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:12:24,571 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:12:27,378 INFO L85 PathProgramCache]: Analyzing trace with hash 1529297587, now seen corresponding path program 245 times [2024-05-06 04:12:27,378 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:12:27,378 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:12:27,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:12:27,582 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:12:27,583 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:12:27,583 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:12:27,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:12:27,783 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2024-05-06 04:12:28,060 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:12:28,061 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:12:28,825 INFO L85 PathProgramCache]: Analyzing trace with hash 506664552, now seen corresponding path program 246 times [2024-05-06 04:12:28,825 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:12:28,825 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:12:28,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:12:29,004 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:12:29,004 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:12:29,004 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:12:29,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:12:29,179 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:12:29,504 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:12:29,504 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:12:48,336 WARN L293 SmtUtils]: Spent 16.11s on a formula simplification. DAG size of input: 33 DAG size of output: 28 (called from [L 210] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.abduction.Abducer.solveAbductionProblem) [2024-05-06 04:12:50,340 WARN L854 $PredicateComparison]: unable to prove that (and (forall ((v_~q2~0.base_In_218 Int) (v_~q2~0.offset_In_218 Int)) (= (select (select |c_#memory_int| v_~q2~0.base_In_218) (+ (* c_~q2_front~0 4) v_~q2~0.offset_In_218)) 0)) (forall ((v_~q1_front~0_In_292 Int) (v_~q1~0.offset_In_157 Int) (v_~q1~0.base_In_157 Int)) (let ((.cse0 (select (select |c_#memory_int| v_~q1~0.base_In_157) (+ (* v_~q1_front~0_In_292 4) v_~q1~0.offset_In_157)))) (or (= .cse0 0) (< 4294967295 .cse0) (< v_~q1_front~0_In_292 0) (< (+ 4294967295 .cse0) 0))))) is different from false [2024-05-06 04:12:50,341 INFO L85 PathProgramCache]: Analyzing trace with hash -1389141031, now seen corresponding path program 247 times [2024-05-06 04:12:50,341 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:12:50,341 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:12:50,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:12:50,521 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:12:50,521 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:12:50,521 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:12:50,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:12:50,702 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:12:51,000 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:12:51,001 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:13:07,668 WARN L293 SmtUtils]: Spent 14.14s on a formula simplification. DAG size of input: 33 DAG size of output: 28 (called from [L 210] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.abduction.Abducer.solveAbductionProblem) [2024-05-06 04:13:09,675 WARN L854 $PredicateComparison]: unable to prove that (and (forall ((v_~q1~0.offset_In_158 Int) (v_~q1_front~0_In_293 Int) (v_~q1~0.base_In_158 Int)) (let ((.cse0 (select (select |c_#memory_int| v_~q1~0.base_In_158) (+ v_~q1~0.offset_In_158 (* v_~q1_front~0_In_293 4))))) (or (= .cse0 0) (< (+ .cse0 4294967295) 0) (< v_~q1_front~0_In_293 0) (< 4294967295 .cse0)))) (forall ((v_~q2~0.offset_In_219 Int) (v_~q2~0.base_In_219 Int)) (= (select (select |c_#memory_int| v_~q2~0.base_In_219) (+ (* c_~q2_front~0 4) v_~q2~0.offset_In_219)) 0))) is different from false [2024-05-06 04:13:09,678 INFO L85 PathProgramCache]: Analyzing trace with hash -1889695578, now seen corresponding path program 248 times [2024-05-06 04:13:09,678 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:13:09,678 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:13:09,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:13:09,891 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:13:09,891 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:13:09,891 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:13:09,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:13:10,256 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:13:10,559 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:13:10,559 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:13:25,280 WARN L293 SmtUtils]: Spent 12.13s on a formula simplification. DAG size of input: 33 DAG size of output: 28 (called from [L 210] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.abduction.Abducer.solveAbductionProblem) [2024-05-06 04:13:27,285 WARN L854 $PredicateComparison]: unable to prove that (and (forall ((v_~q2~0.offset_In_220 Int) (v_~q2~0.base_In_220 Int)) (= (select (select |c_#memory_int| v_~q2~0.base_In_220) (+ (* c_~q2_front~0 4) v_~q2~0.offset_In_220)) 0)) (forall ((v_~q1~0.offset_In_159 Int) (v_~q1~0.base_In_159 Int) (v_~q1_front~0_In_294 Int)) (let ((.cse0 (select (select |c_#memory_int| v_~q1~0.base_In_159) (+ v_~q1~0.offset_In_159 (* v_~q1_front~0_In_294 4))))) (or (= .cse0 0) (< 4294967295 .cse0) (< (+ .cse0 4294967295) 0) (< v_~q1_front~0_In_294 0))))) is different from false [2024-05-06 04:13:27,287 INFO L85 PathProgramCache]: Analyzing trace with hash 925020308, now seen corresponding path program 249 times [2024-05-06 04:13:27,287 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:13:27,288 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:13:27,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:13:27,492 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:13:27,492 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:13:27,493 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:13:27,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:13:27,676 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:13:27,801 INFO L85 PathProgramCache]: Analyzing trace with hash -1389140656, now seen corresponding path program 250 times [2024-05-06 04:13:27,801 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:13:27,801 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:13:27,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:13:27,993 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:13:27,993 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-05-06 04:13:27,993 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-05-06 04:13:28,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-05-06 04:13:28,204 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2024-05-06 04:13:28,574 INFO L349 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2024-05-06 04:13:28,575 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 96 treesize of output 51 [2024-05-06 04:13:37,328 WARN L293 SmtUtils]: Spent 6.06s on a formula simplification. DAG size of input: 33 DAG size of output: 28 (called from [L 210] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.abduction.Abducer.solveAbductionProblem) Received shutdown request... [2024-05-06 04:13:38,223 WARN L340 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 (2)] Timeout while monitored process is still running, waiting 1000 ms for graceful end [2024-05-06 04:13:38,223 WARN L340 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Timeout while monitored process is still running, waiting 1000 ms for graceful end [2024-05-06 04:13:38,223 WARN L340 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Timeout while monitored process is still running, waiting 1000 ms for graceful end [2024-05-06 04:13:39,252 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:1000 (2)] Ended with exit code 0 [2024-05-06 04:13:39,255 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UGemCutter-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2024-05-06 04:13:39,335 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable790,SelfDestructingSolverStorable670,SelfDestructingSolverStorable791,SelfDestructingSolverStorable671,SelfDestructingSolverStorable792,SelfDestructingSolverStorable669,SelfDestructingSolverStorable665,SelfDestructingSolverStorable786,SelfDestructingSolverStorable666,SelfDestructingSolverStorable787,SelfDestructingSolverStorable667,SelfDestructingSolverStorable788,SelfDestructingSolverStorable668,SelfDestructingSolverStorable789,SelfDestructingSolverStorable661,SelfDestructingSolverStorable782,SelfDestructingSolverStorable662,SelfDestructingSolverStorable783,SelfDestructingSolverStorable663,SelfDestructingSolverStorable784,SelfDestructingSolverStorable664,SelfDestructingSolverStorable785,SelfDestructingSolverStorable780,SelfDestructingSolverStorable660,SelfDestructingSolverStorable781,SelfDestructingSolverStorable658,SelfDestructingSolverStorable779,SelfDestructingSolverStorable659,SelfDestructingSolverStorable654,SelfDestructingSolverStorable775,SelfDestructingSolverStorable655,SelfDestructingSolverStorable776,SelfDestructingSolverStorable656,SelfDestructingSolverStorable777,SelfDestructingSolverStorable657,SelfDestructingSolverStorable778,SelfDestructingSolverStorable650,SelfDestructingSolverStorable771,SelfDestructingSolverStorable651,SelfDestructingSolverStorable772,SelfDestructingSolverStorable652,SelfDestructingSolverStorable773,SelfDestructingSolverStorable653,SelfDestructingSolverStorable774,SelfDestructingSolverStorable690,SelfDestructingSolverStorable691,SelfDestructingSolverStorable692,SelfDestructingSolverStorable693,SelfDestructingSolverStorable687,SelfDestructingSolverStorable688,SelfDestructingSolverStorable689,SelfDestructingSolverStorable683,SelfDestructingSolverStorable684,SelfDestructingSolverStorable685,SelfDestructingSolverStorable686,SelfDestructingSolverStorable680,SelfDestructingSolverStorable681,SelfDestructingSolverStorable682,SelfDestructingSolverStorable676,SelfDestructingSolverStorable677,SelfDestructingSolverStorable678,SelfDestructingSolverStorable679,SelfDestructingSolverStorable672,SelfDestructingSolverStorable793,SelfDestructingSolverStorable673,SelfDestructingSolverStorable794,SelfDestructingSolverStorable674,SelfDestructingSolverStorable795,SelfDestructingSolverStorable675,SelfDestructingSolverStorable629,SelfDestructingSolverStorable625,SelfDestructingSolverStorable746,SelfDestructingSolverStorable626,SelfDestructingSolverStorable747,SelfDestructingSolverStorable627,SelfDestructingSolverStorable748,SelfDestructingSolverStorable628,SelfDestructingSolverStorable749,SelfDestructingSolverStorable621,SelfDestructingSolverStorable742,SelfDestructingSolverStorable622,SelfDestructingSolverStorable743,SelfDestructingSolverStorable623,SelfDestructingSolverStorable744,SelfDestructingSolverStorable624,SelfDestructingSolverStorable745,SelfDestructingSolverStorable740,SelfDestructingSolverStorable620,SelfDestructingSolverStorable741,SelfDestructingSolverStorable618,SelfDestructingSolverStorable739,SelfDestructingSolverStorable619,SelfDestructingSolverStorable614,SelfDestructingSolverStorable735,SelfDestructingSolverStorable615,SelfDestructingSolverStorable736,SelfDestructingSolverStorable616,SelfDestructingSolverStorable737,SelfDestructingSolverStorable617,SelfDestructingSolverStorable738,SelfDestructingSolverStorable610,SelfDestructingSolverStorable731,SelfDestructingSolverStorable611,SelfDestructingSolverStorable732,SelfDestructingSolverStorable612,SelfDestructingSolverStorable733,SelfDestructingSolverStorable613,SelfDestructingSolverStorable734,SelfDestructingSolverStorable730,SelfDestructingSolverStorable770,SelfDestructingSolverStorable647,SelfDestructingSolverStorable768,SelfDestructingSolverStorable648,SelfDestructingSolverStorable769,SelfDestructingSolverStorable649,SelfDestructingSolverStorable643,SelfDestructingSolverStorable764,SelfDestructingSolverStorable644,SelfDestructingSolverStorable765,SelfDestructingSolverStorable645,SelfDestructingSolverStorable766,SelfDestructingSolverStorable646,SelfDestructingSolverStorable767,SelfDestructingSolverStorable760,SelfDestructingSolverStorable640,SelfDestructingSolverStorable761,SelfDestructingSolverStorable641,SelfDestructingSolverStorable762,SelfDestructingSolverStorable642,SelfDestructingSolverStorable763,SelfDestructingSolverStorable636,SelfDestructingSolverStorable757,SelfDestructingSolverStorable637,SelfDestructingSolverStorable758,SelfDestructingSolverStorable638,SelfDestructingSolverStorable759,SelfDestructingSolverStorable639,SelfDestructingSolverStorable632,SelfDestructingSolverStorable753,SelfDestructingSolverStorable633,SelfDestructingSolverStorable754,SelfDestructingSolverStorable634,SelfDestructingSolverStorable755,SelfDestructingSolverStorable635,SelfDestructingSolverStorable756,SelfDestructingSolverStorable750,SelfDestructingSolverStorable630,SelfDestructingSolverStorable751,SelfDestructingSolverStorable631,SelfDestructingSolverStorable752,SelfDestructingSolverStorable706,SelfDestructingSolverStorable707,SelfDestructingSolverStorable708,SelfDestructingSolverStorable709,SelfDestructingSolverStorable702,SelfDestructingSolverStorable703,SelfDestructingSolverStorable704,SelfDestructingSolverStorable705,SelfDestructingSolverStorable700,SelfDestructingSolverStorable701,SelfDestructingSolverStorable607,SelfDestructingSolverStorable728,SelfDestructingSolverStorable608,SelfDestructingSolverStorable729,SelfDestructingSolverStorable609,SelfDestructingSolverStorable603,SelfDestructingSolverStorable724,SelfDestructingSolverStorable604,SelfDestructingSolverStorable725,SelfDestructingSolverStorable605,SelfDestructingSolverStorable726,SelfDestructingSolverStorable606,SelfDestructingSolverStorable727,SelfDestructingSolverStorable720,SelfDestructingSolverStorable600,SelfDestructingSolverStorable721,SelfDestructingSolverStorable601,SelfDestructingSolverStorable722,SelfDestructingSolverStorable602,SelfDestructingSolverStorable723,SelfDestructingSolverStorable717,SelfDestructingSolverStorable718,SelfDestructingSolverStorable719,SelfDestructingSolverStorable713,SelfDestructingSolverStorable714,SelfDestructingSolverStorable715,SelfDestructingSolverStorable716,SelfDestructingSolverStorable710,SelfDestructingSolverStorable711,SelfDestructingSolverStorable712,SelfDestructingSolverStorable698,SelfDestructingSolverStorable699,SelfDestructingSolverStorable694,SelfDestructingSolverStorable695,SelfDestructingSolverStorable696,SelfDestructingSolverStorable697,SelfDestructingSolverStorable599,SelfDestructingSolverStorable596,SelfDestructingSolverStorable597,SelfDestructingSolverStorable598 [2024-05-06 04:13:39,335 WARN L619 AbstractCegarLoop]: Verification canceled: while executing Executor. [2024-05-06 04:13:39,337 INFO L805 garLoopResultBuilder]: Registering result TIMEOUT for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (4 of 5 remaining) [2024-05-06 04:13:39,337 INFO L805 garLoopResultBuilder]: Registering result TIMEOUT for location ULTIMATE.startErr0INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (3 of 5 remaining) [2024-05-06 04:13:39,337 INFO L805 garLoopResultBuilder]: Registering result TIMEOUT for location ULTIMATE.startErr1INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (2 of 5 remaining) [2024-05-06 04:13:39,337 INFO L805 garLoopResultBuilder]: Registering result TIMEOUT for location ULTIMATE.startErr2INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (1 of 5 remaining) [2024-05-06 04:13:39,337 INFO L805 garLoopResultBuilder]: Registering result TIMEOUT for location ULTIMATE.startErr3INUSE_VIOLATIONSUFFICIENT_THREAD_INSTANCES (0 of 5 remaining) [2024-05-06 04:13:39,344 INFO L448 BasicCegarLoop]: Path program histogram: [250, 12, 12, 12, 12, 12, 12, 8, 8, 8, 8, 8, 8, 8, 7, 5, 5, 1, 1, 1, 1, 1] [2024-05-06 04:13:39,345 FATAL L? ?]: The Plugin de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction has thrown an exception: java.lang.AssertionError: clock still running: ConditionalCommutativityCheckTime at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.CegarLoopStatisticsGenerator.getValue(CegarLoopStatisticsGenerator.java:172) at de.uni_freiburg.informatik.ultimate.util.statistics.StatisticsData.aggregateBenchmarkData(StatisticsData.java:60) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.executeCegarLoop(TraceAbstractionStarter.java:418) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.analyseProgram(TraceAbstractionStarter.java:302) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.analyseConcurrentProgram(TraceAbstractionStarter.java:225) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.runCegarLoops(TraceAbstractionStarter.java:173) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.(TraceAbstractionStarter.java:154) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver.finish(TraceAbstractionObserver.java:124) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:167) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:150) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:127) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:233) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:227) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:144) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:106) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:319) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.run(DefaultToolchainJob.java:145) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:63) [2024-05-06 04:13:39,348 INFO L158 Benchmark]: Toolchain (without parser) took 808470.28ms. Allocated memory was 266.3MB in the beginning and 3.1GB in the end (delta: 2.8GB). Free memory was 196.1MB in the beginning and 1.3GB in the end (delta: -1.1GB). Peak memory consumption was 1.8GB. Max. memory is 8.0GB. [2024-05-06 04:13:39,348 INFO L158 Benchmark]: CDTParser took 0.11ms. Allocated memory is still 153.1MB. Free memory is still 86.2MB. There was no memory consumed. Max. memory is 8.0GB. [2024-05-06 04:13:39,348 INFO L158 Benchmark]: CACSL2BoogieTranslator took 251.48ms. Allocated memory is still 266.3MB. Free memory was 196.1MB in the beginning and 182.9MB in the end (delta: 13.3MB). Peak memory consumption was 13.6MB. Max. memory is 8.0GB. [2024-05-06 04:13:39,348 INFO L158 Benchmark]: Boogie Procedure Inliner took 44.58ms. Allocated memory is still 266.3MB. Free memory was 182.9MB in the beginning and 180.4MB in the end (delta: 2.5MB). Peak memory consumption was 2.1MB. Max. memory is 8.0GB. [2024-05-06 04:13:39,348 INFO L158 Benchmark]: Boogie Preprocessor took 23.36ms. Allocated memory is still 266.3MB. Free memory was 179.9MB in the beginning and 177.8MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 8.0GB. [2024-05-06 04:13:39,348 INFO L158 Benchmark]: RCFGBuilder took 694.32ms. Allocated memory is still 266.3MB. Free memory was 177.8MB in the beginning and 126.9MB in the end (delta: 50.8MB). Peak memory consumption was 50.3MB. Max. memory is 8.0GB. [2024-05-06 04:13:39,349 INFO L158 Benchmark]: TraceAbstraction took 807450.87ms. Allocated memory was 266.3MB in the beginning and 3.1GB in the end (delta: 2.8GB). Free memory was 125.9MB in the beginning and 1.3GB in the end (delta: -1.1GB). Peak memory consumption was 1.7GB. Max. memory is 8.0GB. [2024-05-06 04:13:39,349 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.11ms. Allocated memory is still 153.1MB. Free memory is still 86.2MB. There was no memory consumed. Max. memory is 8.0GB. * CACSL2BoogieTranslator took 251.48ms. Allocated memory is still 266.3MB. Free memory was 196.1MB in the beginning and 182.9MB in the end (delta: 13.3MB). Peak memory consumption was 13.6MB. Max. memory is 8.0GB. * Boogie Procedure Inliner took 44.58ms. Allocated memory is still 266.3MB. Free memory was 182.9MB in the beginning and 180.4MB in the end (delta: 2.5MB). Peak memory consumption was 2.1MB. Max. memory is 8.0GB. * Boogie Preprocessor took 23.36ms. Allocated memory is still 266.3MB. Free memory was 179.9MB in the beginning and 177.8MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 8.0GB. * RCFGBuilder took 694.32ms. Allocated memory is still 266.3MB. Free memory was 177.8MB in the beginning and 126.9MB in the end (delta: 50.8MB). Peak memory consumption was 50.3MB. Max. memory is 8.0GB. * TraceAbstraction took 807450.87ms. Allocated memory was 266.3MB in the beginning and 3.1GB in the end (delta: 2.8GB). Free memory was 125.9MB in the beginning and 1.3GB in the end (delta: -1.1GB). Peak memory consumption was 1.7GB. Max. memory is 8.0GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Independence relation #1 benchmarks ThreadSeparatingIndependenceRelation.Independence Queries: [ total: 69077, independent: 65024, independent conditional: 42909, independent unconditional: 22115, dependent: 4053, dependent conditional: 3738, dependent unconditional: 315, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ThreadSeparatingIndependenceRelation.Statistics on underlying relation: UnionIndependenceRelation.Independence Queries: [ total: 65799, independent: 65024, independent conditional: 42909, independent unconditional: 22115, dependent: 775, dependent conditional: 460, dependent unconditional: 315, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , UnionIndependenceRelation.Statistics on underlying relations: [ ConditionTransformingIndependenceRelation.Independence Queries: [ total: 65799, independent: 65024, independent conditional: 42909, independent unconditional: 22115, dependent: 775, dependent conditional: 460, dependent unconditional: 315, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ConditionTransformingIndependenceRelation.Statistics on underlying relation: DisjunctiveConditionalIndependenceRelation.Independence Queries: [ total: 65799, independent: 65024, independent conditional: 42909, independent unconditional: 22115, dependent: 775, dependent conditional: 460, dependent unconditional: 315, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , DisjunctiveConditionalIndependenceRelation.Statistics on underlying relation: ConditionTransformingIndependenceRelation.Independence Queries: [ total: 67021, independent: 65024, independent conditional: 8406, independent unconditional: 56618, dependent: 1997, dependent conditional: 650, dependent unconditional: 1347, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ConditionTransformingIndependenceRelation.Statistics on underlying relation: SemanticConditionEliminator.Independence Queries: [ total: 67021, independent: 65024, independent conditional: 2554, independent unconditional: 62470, dependent: 1997, dependent conditional: 333, dependent unconditional: 1664, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , SemanticConditionEliminator.Statistics on underlying relation: CachedIndependenceRelation.Independence Queries: [ total: 67021, independent: 65024, independent conditional: 2554, independent unconditional: 62470, dependent: 1997, dependent conditional: 333, dependent unconditional: 1664, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , CachedIndependenceRelation.Statistics on underlying relation: UnionIndependenceRelation.Independence Queries: [ total: 1055, independent: 1027, independent conditional: 4, independent unconditional: 1023, dependent: 28, dependent conditional: 16, dependent unconditional: 12, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , UnionIndependenceRelation.Statistics on underlying relations: [ SyntacticIndependenceRelation.Independence Queries: [ total: 1055, independent: 1021, independent conditional: 0, independent unconditional: 1021, dependent: 34, dependent conditional: 0, dependent unconditional: 34, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ProtectedIndependenceRelation.Independence Queries: [ total: 34, independent: 6, independent conditional: 4, independent unconditional: 2, dependent: 28, dependent conditional: 16, dependent unconditional: 12, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ProtectedIndependenceRelation.Statistics on underlying relation: SemanticIndependenceRelation.Independence Queries: [ total: 34, independent: 6, independent conditional: 4, independent unconditional: 2, dependent: 28, dependent conditional: 16, dependent unconditional: 12, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , SemanticIndependenceRelation.Query Time [ms]: [ total: 135, independent: 12, independent conditional: 6, independent unconditional: 6, dependent: 123, dependent conditional: 46, dependent unconditional: 77, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , Protected Queries: 0 ], Cache Queries: [ total: 67021, independent: 63997, independent conditional: 2550, independent unconditional: 61447, dependent: 1969, dependent conditional: 317, dependent unconditional: 1652, unknown: 1055, unknown conditional: 20, unknown unconditional: 1035] , Statistics on independence cache: Total cache size (in pairs): 1055, Positive cache size: 1027, Positive conditional cache size: 4, Positive unconditional cache size: 1023, Negative cache size: 28, Negative conditional cache size: 16, Negative unconditional cache size: 12, Unknown cache size: 0, Unknown conditional cache size: 0, Unknown unconditional cache size: 0, Eliminated conditions: 6169, Maximal queried relation: 2, ConditionTransformingIndependenceRelation.Independence Queries: [ total: 67021, independent: 65024, independent conditional: 8406, independent unconditional: 56618, dependent: 1997, dependent conditional: 650, dependent unconditional: 1347, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ConditionTransformingIndependenceRelation.Statistics on underlying relation: SemanticConditionEliminator.Independence Queries: [ total: 67021, independent: 65024, independent conditional: 2554, independent unconditional: 62470, dependent: 1997, dependent conditional: 333, dependent unconditional: 1664, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , SemanticConditionEliminator.Statistics on underlying relation: CachedIndependenceRelation.Independence Queries: [ total: 67021, independent: 65024, independent conditional: 2554, independent unconditional: 62470, dependent: 1997, dependent conditional: 333, dependent unconditional: 1664, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , CachedIndependenceRelation.Statistics on underlying relation: UnionIndependenceRelation.Independence Queries: [ total: 1055, independent: 1027, independent conditional: 4, independent unconditional: 1023, dependent: 28, dependent conditional: 16, dependent unconditional: 12, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , UnionIndependenceRelation.Statistics on underlying relations: [ SyntacticIndependenceRelation.Independence Queries: [ total: 1055, independent: 1021, independent conditional: 0, independent unconditional: 1021, dependent: 34, dependent conditional: 0, dependent unconditional: 34, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ProtectedIndependenceRelation.Independence Queries: [ total: 34, independent: 6, independent conditional: 4, independent unconditional: 2, dependent: 28, dependent conditional: 16, dependent unconditional: 12, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , ProtectedIndependenceRelation.Statistics on underlying relation: SemanticIndependenceRelation.Independence Queries: [ total: 34, independent: 6, independent conditional: 4, independent unconditional: 2, dependent: 28, dependent conditional: 16, dependent unconditional: 12, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , SemanticIndependenceRelation.Query Time [ms]: [ total: 135, independent: 12, independent conditional: 6, independent unconditional: 6, dependent: 123, dependent conditional: 46, dependent unconditional: 77, unknown: 0, unknown conditional: 0, unknown unconditional: 0] , Protected Queries: 0 ], Cache Queries: [ total: 67021, independent: 63997, independent conditional: 2550, independent unconditional: 61447, dependent: 1969, dependent conditional: 317, dependent unconditional: 1652, unknown: 1055, unknown conditional: 20, unknown unconditional: 1035] , Statistics on independence cache: Total cache size (in pairs): 1055, Positive cache size: 1027, Positive conditional cache size: 4, Positive unconditional cache size: 1023, Negative cache size: 28, Negative conditional cache size: 16, Negative unconditional cache size: 12, Unknown cache size: 0, Unknown conditional cache size: 0, Unknown unconditional cache size: 0, Eliminated conditions: 6169 ], Independence queries for same thread: 3278 - ExceptionOrErrorResult: AssertionError: clock still running: ConditionalCommutativityCheckTime de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: AssertionError: clock still running: ConditionalCommutativityCheckTime: de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.CegarLoopStatisticsGenerator.getValue(CegarLoopStatisticsGenerator.java:172) RESULT: Ultimate could not prove your program: Toolchain returned no result. Completed graceful shutdown