java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data --rcfgbuilder.command.for.external.solver 'z3 SMTLIB2_COMPLIANT=true -memory:4096 -smt2 -in -t:12000' -tc ../../../trunk/examples/toolchains/AutomizerBplInlineTransformed.xml --icfgtransformation.transformationtype MAP_ELIMINATION_MONNIAUX --rcfgbuilder.size.of.a.code.block SingleStatement --icfgtransformation.map.elimination.monniaux.number.of.cells 1 -i ../../../trunk/examples/programs/real-life/GuiTestExample.bpl -------------------------------------------------------------------------------- This is Ultimate 0.1.24-7aa59a0 [2019-05-23 09:36:42,029 INFO L146 ILogger]: Resetting all preferences to default values... [2019-05-23 09:36:42,031 INFO L146 ILogger]: Resetting UltimateCore preferences to default values [2019-05-23 09:36:42,047 INFO L146 ILogger]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-05-23 09:36:42,047 INFO L146 ILogger]: Resetting Boogie Preprocessor preferences to default values [2019-05-23 09:36:42,051 INFO L146 ILogger]: Resetting Boogie Procedure Inliner preferences to default values [2019-05-23 09:36:42,052 INFO L146 ILogger]: Resetting Abstract Interpretation preferences to default values [2019-05-23 09:36:42,055 INFO L146 ILogger]: Resetting LassoRanker preferences to default values [2019-05-23 09:36:42,057 INFO L146 ILogger]: Resetting Reaching Definitions preferences to default values [2019-05-23 09:36:42,065 INFO L146 ILogger]: Resetting SyntaxChecker preferences to default values [2019-05-23 09:36:42,066 INFO L146 ILogger]: Büchi Program Product provides no preferences, ignoring... [2019-05-23 09:36:42,066 INFO L146 ILogger]: Resetting LTL2Aut preferences to default values [2019-05-23 09:36:42,067 INFO L146 ILogger]: Resetting PEA to Boogie preferences to default values [2019-05-23 09:36:42,068 INFO L146 ILogger]: Resetting BlockEncodingV2 preferences to default values [2019-05-23 09:36:42,072 INFO L146 ILogger]: Resetting ChcToBoogie preferences to default values [2019-05-23 09:36:42,073 INFO L146 ILogger]: Resetting AutomataScriptInterpreter preferences to default values [2019-05-23 09:36:42,074 INFO L146 ILogger]: Resetting BuchiAutomizer preferences to default values [2019-05-23 09:36:42,078 INFO L146 ILogger]: Resetting CACSL2BoogieTranslator preferences to default values [2019-05-23 09:36:42,082 INFO L146 ILogger]: Resetting CodeCheck preferences to default values [2019-05-23 09:36:42,085 INFO L146 ILogger]: Resetting InvariantSynthesis preferences to default values [2019-05-23 09:36:42,087 INFO L146 ILogger]: Resetting RCFGBuilder preferences to default values [2019-05-23 09:36:42,088 INFO L146 ILogger]: Resetting TraceAbstraction preferences to default values [2019-05-23 09:36:42,091 INFO L146 ILogger]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-05-23 09:36:42,091 INFO L146 ILogger]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-05-23 09:36:42,092 INFO L146 ILogger]: Resetting TreeAutomizer preferences to default values [2019-05-23 09:36:42,093 INFO L146 ILogger]: Resetting IcfgToChc preferences to default values [2019-05-23 09:36:42,093 INFO L146 ILogger]: Resetting IcfgTransformer preferences to default values [2019-05-23 09:36:42,094 INFO L146 ILogger]: ReqToTest provides no preferences, ignoring... [2019-05-23 09:36:42,094 INFO L146 ILogger]: Resetting Boogie Printer preferences to default values [2019-05-23 09:36:42,095 INFO L146 ILogger]: Resetting ChcSmtPrinter preferences to default values [2019-05-23 09:36:42,096 INFO L146 ILogger]: Resetting ReqPrinter preferences to default values [2019-05-23 09:36:42,097 INFO L146 ILogger]: Resetting Witness Printer preferences to default values [2019-05-23 09:36:42,098 INFO L146 ILogger]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-05-23 09:36:42,098 INFO L146 ILogger]: Resetting CDTParser preferences to default values [2019-05-23 09:36:42,099 INFO L146 ILogger]: AutomataScriptParser provides no preferences, ignoring... [2019-05-23 09:36:42,099 INFO L146 ILogger]: ReqParser provides no preferences, ignoring... [2019-05-23 09:36:42,099 INFO L146 ILogger]: Resetting SmtParser preferences to default values [2019-05-23 09:36:42,100 INFO L146 ILogger]: Resetting Witness Parser preferences to default values [2019-05-23 09:36:42,101 INFO L146 ILogger]: Finished resetting all preferences to default values... Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder: Command for external solver -> z3 SMTLIB2_COMPLIANT=true -memory:4096 -smt2 -in -t:12000 Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation: TransformationType -> MAP_ELIMINATION_MONNIAUX Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder: Size of a code block -> SingleStatement Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation: Map elimination Monniaux: number of cells -> 1 [2019-05-23 09:36:42,147 INFO L146 ILogger]: Repository-Root is: /tmp [2019-05-23 09:36:42,160 INFO L146 ILogger]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-05-23 09:36:42,166 INFO L146 ILogger]: [Toolchain 1]: Toolchain selected. [2019-05-23 09:36:42,167 INFO L146 ILogger]: Initializing Boogie PL CUP Parser... [2019-05-23 09:36:42,168 INFO L146 ILogger]: Boogie PL CUP Parser initialized [2019-05-23 09:36:42,169 INFO L146 ILogger]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/programs/real-life/GuiTestExample.bpl [2019-05-23 09:36:42,169 INFO L146 ILogger]: Parsing: '/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/programs/real-life/GuiTestExample.bpl' [2019-05-23 09:36:42,242 INFO L146 ILogger]: ####################### [Toolchain 1] ####################### [2019-05-23 09:36:42,244 INFO L146 ILogger]: Walking toolchain with 5 elements. [2019-05-23 09:36:42,244 INFO L146 ILogger]: ------------------------Boogie Procedure Inliner---------------------------- [2019-05-23 09:36:42,245 INFO L146 ILogger]: Initializing Boogie Procedure Inliner... [2019-05-23 09:36:42,245 INFO L146 ILogger]: Boogie Procedure Inliner initialized [2019-05-23 09:36:42,263 INFO L146 ILogger]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "GuiTestExample.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 09:36:42" (1/1) ... [2019-05-23 09:36:42,295 INFO L146 ILogger]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "GuiTestExample.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 09:36:42" (1/1) ... [2019-05-23 09:36:42,311 WARN L146 ILogger]: Program contained no entry procedure! [2019-05-23 09:36:42,311 WARN L146 ILogger]: Missing entry procedures: [ULTIMATE.start] [2019-05-23 09:36:42,312 WARN L146 ILogger]: Fallback enabled. All procedures will be processed. [2019-05-23 09:36:42,362 INFO L146 ILogger]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-05-23 09:36:42,363 INFO L146 ILogger]: ------------------------Boogie Preprocessor---------------------------- [2019-05-23 09:36:42,363 INFO L146 ILogger]: Initializing Boogie Preprocessor... [2019-05-23 09:36:42,364 INFO L146 ILogger]: Boogie Preprocessor initialized [2019-05-23 09:36:42,376 INFO L146 ILogger]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "GuiTestExample.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 09:36:42" (1/1) ... [2019-05-23 09:36:42,376 INFO L146 ILogger]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "GuiTestExample.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 09:36:42" (1/1) ... [2019-05-23 09:36:42,384 INFO L146 ILogger]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "GuiTestExample.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 09:36:42" (1/1) ... [2019-05-23 09:36:42,384 INFO L146 ILogger]: Executing the observer StructExpander from plugin Boogie Preprocessor for "GuiTestExample.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 09:36:42" (1/1) ... [2019-05-23 09:36:42,402 INFO L146 ILogger]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "GuiTestExample.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 09:36:42" (1/1) ... [2019-05-23 09:36:42,412 INFO L146 ILogger]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "GuiTestExample.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 09:36:42" (1/1) ... [2019-05-23 09:36:42,419 INFO L146 ILogger]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "GuiTestExample.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 09:36:42" (1/1) ... [2019-05-23 09:36:42,428 INFO L146 ILogger]: ------------------------ END Boogie Preprocessor---------------------------- [2019-05-23 09:36:42,429 INFO L146 ILogger]: ------------------------RCFGBuilder---------------------------- [2019-05-23 09:36:42,429 INFO L146 ILogger]: Initializing RCFGBuilder... [2019-05-23 09:36:42,430 INFO L146 ILogger]: RCFGBuilder initialized [2019-05-23 09:36:42,430 INFO L146 ILogger]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "GuiTestExample.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 09:36:42" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:4096 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:4096 -smt2 -in -t:12000 [2019-05-23 09:36:42,508 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$3$$la$init$ra$$4885 given in one single declaration [2019-05-23 09:36:42,509 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$3$$la$init$ra$$4885 [2019-05-23 09:36:42,509 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$3$$la$init$ra$$4885 [2019-05-23 09:36:42,509 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$2$actionPerformed$4553 given in one single declaration [2019-05-23 09:36:42,510 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$2$actionPerformed$4553 [2019-05-23 09:36:42,510 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$2$actionPerformed$4553 [2019-05-23 09:36:42,510 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$3$actionPerformed$4886 given in one single declaration [2019-05-23 09:36:42,510 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$3$actionPerformed$4886 [2019-05-23 09:36:42,510 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$3$actionPerformed$4886 [2019-05-23 09:36:42,511 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$$la$init$ra$$1805 given in one single declaration [2019-05-23 09:36:42,511 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$$la$init$ra$$1805 [2019-05-23 09:36:42,511 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$$la$init$ra$$1805 [2019-05-23 09:36:42,511 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$1$$la$init$ra$$1802 given in one single declaration [2019-05-23 09:36:42,512 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$1$$la$init$ra$$1802 [2019-05-23 09:36:42,512 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$1$$la$init$ra$$1802 [2019-05-23 09:36:42,512 INFO L146 ILogger]: Found specification of procedure void$javax.swing.SwingUtilities$invokeLater$4940 [2019-05-23 09:36:42,512 INFO L146 ILogger]: Found specification of procedure void$javax.swing.JFrame$setLayout$1827 [2019-05-23 09:36:42,512 INFO L146 ILogger]: Specification and implementation of procedure javax.swing.JButton$SimpleFrame2Cons$access$0$1806 given in one single declaration [2019-05-23 09:36:42,513 INFO L146 ILogger]: Found specification of procedure javax.swing.JButton$SimpleFrame2Cons$access$0$1806 [2019-05-23 09:36:42,513 INFO L146 ILogger]: Found implementation of procedure javax.swing.JButton$SimpleFrame2Cons$access$0$1806 [2019-05-23 09:36:42,513 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$2$$la$init$ra$$4552 given in one single declaration [2019-05-23 09:36:42,513 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$2$$la$init$ra$$4552 [2019-05-23 09:36:42,513 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$2$$la$init$ra$$4552 [2019-05-23 09:36:42,514 INFO L146 ILogger]: Found specification of procedure void$java.awt.Frame$setResizable$1858 [2019-05-23 09:36:42,514 INFO L146 ILogger]: Specification and implementation of procedure java.awt.Dimension$java.awt.Toolkit$getScreenSize$3246 given in one single declaration [2019-05-23 09:36:42,514 INFO L146 ILogger]: Found specification of procedure java.awt.Dimension$java.awt.Toolkit$getScreenSize$3246 [2019-05-23 09:36:42,514 INFO L146 ILogger]: Found implementation of procedure java.awt.Dimension$java.awt.Toolkit$getScreenSize$3246 [2019-05-23 09:36:42,515 INFO L146 ILogger]: Specification and implementation of procedure void$javax.swing.JFrame$$la$init$ra$$1809 given in one single declaration [2019-05-23 09:36:42,515 INFO L146 ILogger]: Found specification of procedure void$javax.swing.JFrame$$la$init$ra$$1809 [2019-05-23 09:36:42,515 INFO L146 ILogger]: Found implementation of procedure void$javax.swing.JFrame$$la$init$ra$$1809 [2019-05-23 09:36:42,515 INFO L146 ILogger]: Specification and implementation of procedure int$SimpleFrame2Cons$access$2$1808 given in one single declaration [2019-05-23 09:36:42,515 INFO L146 ILogger]: Found specification of procedure int$SimpleFrame2Cons$access$2$1808 [2019-05-23 09:36:42,516 INFO L146 ILogger]: Found implementation of procedure int$SimpleFrame2Cons$access$2$1808 [2019-05-23 09:36:42,516 INFO L146 ILogger]: Found specification of procedure void$javax.swing.JFrame$setDefaultCloseOperation$1816 [2019-05-23 09:36:42,516 INFO L146 ILogger]: Found specification of procedure void$javax.swing.AbstractButton$addActionListener$4123 [2019-05-23 09:36:42,516 INFO L146 ILogger]: Found specification of procedure void$java.awt.Window$setLocation$1913 [2019-05-23 09:36:42,516 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$4$$la$init$ra$$4887 given in one single declaration [2019-05-23 09:36:42,516 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$4$$la$init$ra$$4887 [2019-05-23 09:36:42,517 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$4$$la$init$ra$$4887 [2019-05-23 09:36:42,517 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$4$actionPerformed$4888 given in one single declaration [2019-05-23 09:36:42,517 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$4$actionPerformed$4888 [2019-05-23 09:36:42,517 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$4$actionPerformed$4888 [2019-05-23 09:36:42,517 INFO L146 ILogger]: Found specification of procedure void$javax.swing.AbstractButton$setEnabled$4131 [2019-05-23 09:36:42,518 INFO L146 ILogger]: Found specification of procedure void$java.awt.Window$setVisible$1918 [2019-05-23 09:36:42,518 INFO L146 ILogger]: Found specification of procedure int$java.awt.Component$getHeight$2305 [2019-05-23 09:36:42,518 INFO L146 ILogger]: Found specification of procedure void$java.awt.Window$pack$1909 [2019-05-23 09:36:42,518 INFO L146 ILogger]: Found specification of procedure java.awt.Toolkit$java.awt.Toolkit$getDefaultToolkit$3255 [2019-05-23 09:36:42,518 INFO L146 ILogger]: Found specification of procedure int$java.awt.Component$getWidth$2304 [2019-05-23 09:36:42,519 INFO L146 ILogger]: Found specification of procedure void$java.awt.Frame$setTitle$1852 [2019-05-23 09:36:42,519 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$access$1$1807 given in one single declaration [2019-05-23 09:36:42,519 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$access$1$1807 [2019-05-23 09:36:42,519 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$access$1$1807 [2019-05-23 09:36:42,519 INFO L146 ILogger]: Found specification of procedure void$java.awt.FlowLayout$$la$init$ra$$4889 [2019-05-23 09:36:42,520 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$1$run$1803 given in one single declaration [2019-05-23 09:36:42,520 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$1$run$1803 [2019-05-23 09:36:42,520 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$1$run$1803 [2019-05-23 09:36:42,520 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$main$1804 given in one single declaration [2019-05-23 09:36:42,520 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$main$1804 [2019-05-23 09:36:42,521 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$main$1804 [2019-05-23 09:36:42,521 INFO L146 ILogger]: Found specification of procedure void$javax.swing.JButton$$la$init$ra$$2558 [2019-05-23 09:36:42,521 INFO L146 ILogger]: Specification and implementation of procedure $EFG_Procedure given in one single declaration [2019-05-23 09:36:42,521 INFO L146 ILogger]: Found specification of procedure $EFG_Procedure [2019-05-23 09:36:42,521 INFO L146 ILogger]: Found implementation of procedure $EFG_Procedure [2019-05-23 09:36:42,522 INFO L146 ILogger]: Found specification of procedure java.awt.Component$java.awt.Container$add$2075 [2019-05-23 09:36:42,522 INFO L146 ILogger]: Found specification of procedure void$java.lang.Object$$la$init$ra$$38 [2019-05-23 09:36:42,804 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 09:36:42,935 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 09:36:43,048 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 09:36:43,190 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 09:36:43,482 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 09:36:43,527 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 09:36:43,540 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 09:36:43,546 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 09:36:43,611 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 09:36:43,625 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 09:36:43,667 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 09:36:44,582 INFO L146 ILogger]: Using library mode [2019-05-23 09:36:44,583 INFO L146 ILogger]: Removed 44 assume(true) statements. [2019-05-23 09:36:44,585 INFO L146 ILogger]: Adding new model GuiTestExample.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.05 09:36:44 BoogieIcfgContainer [2019-05-23 09:36:44,585 INFO L146 ILogger]: ------------------------ END RCFGBuilder---------------------------- [2019-05-23 09:36:44,585 INFO L146 ILogger]: ------------------------IcfgTransformer---------------------------- [2019-05-23 09:36:44,585 INFO L146 ILogger]: Initializing IcfgTransformer... [2019-05-23 09:36:44,586 INFO L146 ILogger]: IcfgTransformer initialized [2019-05-23 09:36:44,589 INFO L146 ILogger]: Executing the observer IcfgTransformationObserver from plugin IcfgTransformer for "GuiTestExample.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.05 09:36:44" (1/1) ... [2019-05-23 09:36:44,659 INFO L146 ILogger]: Adding new model GuiTestExample.bpl de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 23.05 09:36:44 BasicIcfg [2019-05-23 09:36:44,659 INFO L146 ILogger]: ------------------------ END IcfgTransformer---------------------------- [2019-05-23 09:36:44,661 INFO L146 ILogger]: ------------------------TraceAbstraction---------------------------- [2019-05-23 09:36:44,661 INFO L146 ILogger]: Initializing TraceAbstraction... [2019-05-23 09:36:44,664 INFO L146 ILogger]: TraceAbstraction initialized [2019-05-23 09:36:44,664 INFO L146 ILogger]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "GuiTestExample.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 09:36:42" (1/3) ... [2019-05-23 09:36:44,665 INFO L146 ILogger]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@593dc8a3 and model type GuiTestExample.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.05 09:36:44, skipping insertion in model container [2019-05-23 09:36:44,666 INFO L146 ILogger]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "GuiTestExample.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.05 09:36:44" (2/3) ... [2019-05-23 09:36:44,666 INFO L146 ILogger]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@593dc8a3 and model type GuiTestExample.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 23.05 09:36:44, skipping insertion in model container [2019-05-23 09:36:44,666 INFO L146 ILogger]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "GuiTestExample.bpl de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 23.05 09:36:44" (3/3) ... [2019-05-23 09:36:44,668 INFO L146 ILogger]: Analyzing ICFG GuiTestExample.bplME [2019-05-23 09:36:44,677 INFO L146 ILogger]: Automizer settings: Hoare:false NWA Interpolation:ForwardPredicates Determinization: PREDICATE_ABSTRACTION [2019-05-23 09:36:44,689 INFO L146 ILogger]: Appying trace abstraction to program that has 87 error locations. [2019-05-23 09:36:44,703 INFO L146 ILogger]: Starting to check reachability of 87 error locations. [2019-05-23 09:36:44,725 INFO L146 ILogger]: Using default assertion order modulation [2019-05-23 09:36:44,726 INFO L146 ILogger]: Interprodecural is true [2019-05-23 09:36:44,726 INFO L146 ILogger]: Hoare is false [2019-05-23 09:36:44,726 INFO L146 ILogger]: Compute interpolants for ForwardPredicates [2019-05-23 09:36:44,726 INFO L146 ILogger]: Backedges is STRAIGHT_LINE [2019-05-23 09:36:44,726 INFO L146 ILogger]: Determinization is PREDICATE_ABSTRACTION [2019-05-23 09:36:44,726 INFO L146 ILogger]: Difference is false [2019-05-23 09:36:44,726 INFO L146 ILogger]: Minimize is MINIMIZE_SEVPA [2019-05-23 09:36:44,727 INFO L146 ILogger]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-05-23 09:36:44,775 INFO L146 ILogger]: Start isEmpty. Operand 645 states. [2019-05-23 09:36:44,784 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 4 [2019-05-23 09:36:44,784 INFO L146 ILogger]: Found error trace [2019-05-23 09:36:44,785 INFO L146 ILogger]: trace histogram [1, 1, 1] [2019-05-23 09:36:44,790 INFO L146 ILogger]: === Iteration 1 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT]=== [2019-05-23 09:36:44,796 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 09:36:44,797 INFO L146 ILogger]: Analyzing trace with hash 767125, now seen corresponding path program 1 times [2019-05-23 09:36:44,854 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 09:36:44,878 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 09:36:44,882 WARN L146 ILogger]: Trace formula consists of 5 conjuncts, 3 conjunts are in the unsatisfiable core [2019-05-23 09:36:44,887 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 09:36:44,980 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 09:36:44,983 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 09:36:44,983 INFO L146 ILogger]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-05-23 09:36:44,987 INFO L146 ILogger]: Interpolant automaton has 4 states [2019-05-23 09:36:45,000 INFO L146 ILogger]: Constructing interpolant automaton starting with 4 interpolants. [2019-05-23 09:36:45,000 INFO L146 ILogger]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-05-23 09:36:45,002 INFO L146 ILogger]: Start difference. First operand 645 states. Second operand 4 states. [2019-05-23 09:36:45,195 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 09:36:45,196 INFO L146 ILogger]: Finished difference Result 640 states and 642 transitions. [2019-05-23 09:36:45,200 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-05-23 09:36:45,201 INFO L146 ILogger]: Start accepts. Automaton has 4 states. Word has length 3 [2019-05-23 09:36:45,202 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 09:36:45,228 INFO L146 ILogger]: With dead ends: 640 [2019-05-23 09:36:45,228 INFO L146 ILogger]: Without dead ends: 558 [2019-05-23 09:36:45,229 INFO L146 ILogger]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-05-23 09:36:45,246 INFO L146 ILogger]: Start minimizeSevpa. Operand 558 states. [2019-05-23 09:36:45,296 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 558 to 558. [2019-05-23 09:36:45,298 INFO L146 ILogger]: Start removeUnreachable. Operand 558 states. [2019-05-23 09:36:45,304 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 558 states to 558 states and 564 transitions. [2019-05-23 09:36:45,307 INFO L146 ILogger]: Start accepts. Automaton has 558 states and 564 transitions. Word has length 3 [2019-05-23 09:36:45,307 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 09:36:45,308 INFO L146 ILogger]: Abstraction has 558 states and 564 transitions. [2019-05-23 09:36:45,309 INFO L146 ILogger]: Interpolant automaton has 4 states. [2019-05-23 09:36:45,309 INFO L146 ILogger]: Start isEmpty. Operand 558 states and 564 transitions. [2019-05-23 09:36:45,309 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 5 [2019-05-23 09:36:45,310 INFO L146 ILogger]: Found error trace [2019-05-23 09:36:45,310 INFO L146 ILogger]: trace histogram [1, 1, 1, 1] [2019-05-23 09:36:45,313 INFO L146 ILogger]: === Iteration 2 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT]=== [2019-05-23 09:36:45,313 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 09:36:45,314 INFO L146 ILogger]: Analyzing trace with hash 23874049, now seen corresponding path program 1 times [2019-05-23 09:36:45,315 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 09:36:45,317 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 09:36:45,318 WARN L146 ILogger]: Trace formula consists of 6 conjuncts, 3 conjunts are in the unsatisfiable core [2019-05-23 09:36:45,319 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 09:36:45,362 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 09:36:45,362 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 09:36:45,362 INFO L146 ILogger]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-05-23 09:36:45,364 INFO L146 ILogger]: Interpolant automaton has 4 states [2019-05-23 09:36:45,364 INFO L146 ILogger]: Constructing interpolant automaton starting with 4 interpolants. [2019-05-23 09:36:45,365 INFO L146 ILogger]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-05-23 09:36:45,365 INFO L146 ILogger]: Start difference. First operand 558 states and 564 transitions. Second operand 4 states. [2019-05-23 09:36:45,417 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 09:36:45,417 INFO L146 ILogger]: Finished difference Result 557 states and 563 transitions. [2019-05-23 09:36:45,426 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-05-23 09:36:45,426 INFO L146 ILogger]: Start accepts. Automaton has 4 states. Word has length 4 [2019-05-23 09:36:45,426 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 09:36:45,430 INFO L146 ILogger]: With dead ends: 557 [2019-05-23 09:36:45,431 INFO L146 ILogger]: Without dead ends: 557 [2019-05-23 09:36:45,437 INFO L146 ILogger]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-05-23 09:36:45,439 INFO L146 ILogger]: Start minimizeSevpa. Operand 557 states. [2019-05-23 09:36:45,474 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 557 to 557. [2019-05-23 09:36:45,480 INFO L146 ILogger]: Start removeUnreachable. Operand 557 states. [2019-05-23 09:36:45,482 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 557 states to 557 states and 563 transitions. [2019-05-23 09:36:45,483 INFO L146 ILogger]: Start accepts. Automaton has 557 states and 563 transitions. Word has length 4 [2019-05-23 09:36:45,483 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 09:36:45,484 INFO L146 ILogger]: Abstraction has 557 states and 563 transitions. [2019-05-23 09:36:45,484 INFO L146 ILogger]: Interpolant automaton has 4 states. [2019-05-23 09:36:45,484 INFO L146 ILogger]: Start isEmpty. Operand 557 states and 563 transitions. [2019-05-23 09:36:45,485 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 6 [2019-05-23 09:36:45,485 INFO L146 ILogger]: Found error trace [2019-05-23 09:36:45,485 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1] [2019-05-23 09:36:45,489 INFO L146 ILogger]: === Iteration 3 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT]=== [2019-05-23 09:36:45,489 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 09:36:45,489 INFO L146 ILogger]: Analyzing trace with hash 741050664, now seen corresponding path program 1 times [2019-05-23 09:36:45,491 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 09:36:45,494 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 09:36:45,494 INFO L146 ILogger]: Trace formula consists of 7 conjuncts, 3 conjunts are in the unsatisfiable core [2019-05-23 09:36:45,495 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 09:36:45,608 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 09:36:45,608 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 09:36:45,608 INFO L146 ILogger]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-05-23 09:36:45,609 INFO L146 ILogger]: Interpolant automaton has 4 states [2019-05-23 09:36:45,610 INFO L146 ILogger]: Constructing interpolant automaton starting with 4 interpolants. [2019-05-23 09:36:45,610 INFO L146 ILogger]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-05-23 09:36:45,610 INFO L146 ILogger]: Start difference. First operand 557 states and 563 transitions. Second operand 4 states. [2019-05-23 09:36:45,704 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 09:36:45,704 INFO L146 ILogger]: Finished difference Result 556 states and 562 transitions. [2019-05-23 09:36:45,704 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-05-23 09:36:45,705 INFO L146 ILogger]: Start accepts. Automaton has 4 states. Word has length 5 [2019-05-23 09:36:45,705 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 09:36:45,708 INFO L146 ILogger]: With dead ends: 556 [2019-05-23 09:36:45,708 INFO L146 ILogger]: Without dead ends: 551 [2019-05-23 09:36:45,709 INFO L146 ILogger]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-05-23 09:36:45,710 INFO L146 ILogger]: Start minimizeSevpa. Operand 551 states. [2019-05-23 09:36:45,719 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 551 to 551. [2019-05-23 09:36:45,720 INFO L146 ILogger]: Start removeUnreachable. Operand 551 states. [2019-05-23 09:36:45,722 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 551 states to 551 states and 558 transitions. [2019-05-23 09:36:45,744 INFO L146 ILogger]: Start accepts. Automaton has 551 states and 558 transitions. Word has length 5 [2019-05-23 09:36:45,744 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 09:36:45,746 INFO L146 ILogger]: Abstraction has 551 states and 558 transitions. [2019-05-23 09:36:45,746 INFO L146 ILogger]: Interpolant automaton has 4 states. [2019-05-23 09:36:45,746 INFO L146 ILogger]: Start isEmpty. Operand 551 states and 558 transitions. [2019-05-23 09:36:45,747 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 6 [2019-05-23 09:36:45,747 INFO L146 ILogger]: Found error trace [2019-05-23 09:36:45,747 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1] [2019-05-23 09:36:45,749 INFO L146 ILogger]: === Iteration 4 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT]=== [2019-05-23 09:36:45,750 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 09:36:45,750 INFO L146 ILogger]: Analyzing trace with hash 742004970, now seen corresponding path program 1 times [2019-05-23 09:36:45,751 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 09:36:45,754 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 09:36:45,755 INFO L146 ILogger]: Trace formula consists of 7 conjuncts, 3 conjunts are in the unsatisfiable core [2019-05-23 09:36:45,755 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 09:36:45,787 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 09:36:45,787 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 09:36:45,787 INFO L146 ILogger]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-05-23 09:36:45,787 INFO L146 ILogger]: Interpolant automaton has 4 states [2019-05-23 09:36:45,788 INFO L146 ILogger]: Constructing interpolant automaton starting with 4 interpolants. [2019-05-23 09:36:45,788 INFO L146 ILogger]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-05-23 09:36:45,788 INFO L146 ILogger]: Start difference. First operand 551 states and 558 transitions. Second operand 4 states. [2019-05-23 09:36:45,953 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 09:36:45,953 INFO L146 ILogger]: Finished difference Result 539 states and 546 transitions. [2019-05-23 09:36:45,954 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-05-23 09:36:45,954 INFO L146 ILogger]: Start accepts. Automaton has 4 states. Word has length 5 [2019-05-23 09:36:45,954 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 09:36:45,957 INFO L146 ILogger]: With dead ends: 539 [2019-05-23 09:36:45,957 INFO L146 ILogger]: Without dead ends: 521 [2019-05-23 09:36:45,958 INFO L146 ILogger]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-05-23 09:36:45,959 INFO L146 ILogger]: Start minimizeSevpa. Operand 521 states. [2019-05-23 09:36:45,967 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 521 to 521. [2019-05-23 09:36:45,967 INFO L146 ILogger]: Start removeUnreachable. Operand 521 states. [2019-05-23 09:36:45,969 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 521 states to 521 states and 528 transitions. [2019-05-23 09:36:45,970 INFO L146 ILogger]: Start accepts. Automaton has 521 states and 528 transitions. Word has length 5 [2019-05-23 09:36:45,970 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 09:36:45,970 INFO L146 ILogger]: Abstraction has 521 states and 528 transitions. [2019-05-23 09:36:45,970 INFO L146 ILogger]: Interpolant automaton has 4 states. [2019-05-23 09:36:45,970 INFO L146 ILogger]: Start isEmpty. Operand 521 states and 528 transitions. [2019-05-23 09:36:45,971 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 6 [2019-05-23 09:36:45,971 INFO L146 ILogger]: Found error trace [2019-05-23 09:36:45,971 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1] [2019-05-23 09:36:45,974 INFO L146 ILogger]: === Iteration 5 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT]=== [2019-05-23 09:36:45,974 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 09:36:45,974 INFO L146 ILogger]: Analyzing trace with hash 735323842, now seen corresponding path program 1 times [2019-05-23 09:36:45,975 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 09:36:45,978 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 09:36:45,979 INFO L146 ILogger]: Trace formula consists of 7 conjuncts, 3 conjunts are in the unsatisfiable core [2019-05-23 09:36:45,979 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 09:36:46,104 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 09:36:46,105 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 09:36:46,105 INFO L146 ILogger]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-05-23 09:36:46,105 INFO L146 ILogger]: Interpolant automaton has 4 states [2019-05-23 09:36:46,106 INFO L146 ILogger]: Constructing interpolant automaton starting with 4 interpolants. [2019-05-23 09:36:46,106 INFO L146 ILogger]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-05-23 09:36:46,106 INFO L146 ILogger]: Start difference. First operand 521 states and 528 transitions. Second operand 4 states. [2019-05-23 09:36:46,181 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 09:36:46,181 INFO L146 ILogger]: Finished difference Result 520 states and 527 transitions. [2019-05-23 09:36:46,182 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-05-23 09:36:46,182 INFO L146 ILogger]: Start accepts. Automaton has 4 states. Word has length 5 [2019-05-23 09:36:46,182 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 09:36:46,185 INFO L146 ILogger]: With dead ends: 520 [2019-05-23 09:36:46,185 INFO L146 ILogger]: Without dead ends: 515 [2019-05-23 09:36:46,185 INFO L146 ILogger]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-05-23 09:36:46,187 INFO L146 ILogger]: Start minimizeSevpa. Operand 515 states. [2019-05-23 09:36:46,194 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 515 to 515. [2019-05-23 09:36:46,194 INFO L146 ILogger]: Start removeUnreachable. Operand 515 states. [2019-05-23 09:36:46,196 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 515 states to 515 states and 523 transitions. [2019-05-23 09:36:46,197 INFO L146 ILogger]: Start accepts. Automaton has 515 states and 523 transitions. Word has length 5 [2019-05-23 09:36:46,197 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 09:36:46,197 INFO L146 ILogger]: Abstraction has 515 states and 523 transitions. [2019-05-23 09:36:46,197 INFO L146 ILogger]: Interpolant automaton has 4 states. [2019-05-23 09:36:46,197 INFO L146 ILogger]: Start isEmpty. Operand 515 states and 523 transitions. [2019-05-23 09:36:46,198 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 6 [2019-05-23 09:36:46,198 INFO L146 ILogger]: Found error trace [2019-05-23 09:36:46,198 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1] [2019-05-23 09:36:46,201 INFO L146 ILogger]: === Iteration 6 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT]=== [2019-05-23 09:36:46,201 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 09:36:46,201 INFO L146 ILogger]: Analyzing trace with hash 730552317, now seen corresponding path program 1 times [2019-05-23 09:36:46,203 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 09:36:46,205 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 09:36:46,206 INFO L146 ILogger]: Trace formula consists of 7 conjuncts, 3 conjunts are in the unsatisfiable core [2019-05-23 09:36:46,206 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 09:36:46,228 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 09:36:46,229 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 09:36:46,229 INFO L146 ILogger]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-05-23 09:36:46,229 INFO L146 ILogger]: Interpolant automaton has 4 states [2019-05-23 09:36:46,230 INFO L146 ILogger]: Constructing interpolant automaton starting with 4 interpolants. [2019-05-23 09:36:46,230 INFO L146 ILogger]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-05-23 09:36:46,231 INFO L146 ILogger]: Start difference. First operand 515 states and 523 transitions. Second operand 4 states. [2019-05-23 09:36:46,279 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 09:36:46,280 INFO L146 ILogger]: Finished difference Result 514 states and 522 transitions. [2019-05-23 09:36:46,280 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-05-23 09:36:46,280 INFO L146 ILogger]: Start accepts. Automaton has 4 states. Word has length 5 [2019-05-23 09:36:46,280 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 09:36:46,283 INFO L146 ILogger]: With dead ends: 514 [2019-05-23 09:36:46,283 INFO L146 ILogger]: Without dead ends: 509 [2019-05-23 09:36:46,284 INFO L146 ILogger]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-05-23 09:36:46,285 INFO L146 ILogger]: Start minimizeSevpa. Operand 509 states. [2019-05-23 09:36:46,291 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 509 to 509. [2019-05-23 09:36:46,291 INFO L146 ILogger]: Start removeUnreachable. Operand 509 states. [2019-05-23 09:36:46,293 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 509 states to 509 states and 518 transitions. [2019-05-23 09:36:46,293 INFO L146 ILogger]: Start accepts. Automaton has 509 states and 518 transitions. Word has length 5 [2019-05-23 09:36:46,294 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 09:36:46,294 INFO L146 ILogger]: Abstraction has 509 states and 518 transitions. [2019-05-23 09:36:46,294 INFO L146 ILogger]: Interpolant automaton has 4 states. [2019-05-23 09:36:46,294 INFO L146 ILogger]: Start isEmpty. Operand 509 states and 518 transitions. [2019-05-23 09:36:46,295 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 7 [2019-05-23 09:36:46,295 INFO L146 ILogger]: Found error trace [2019-05-23 09:36:46,295 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1, 1] [2019-05-23 09:36:46,297 INFO L146 ILogger]: === Iteration 7 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT]=== [2019-05-23 09:36:46,297 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 09:36:46,297 INFO L146 ILogger]: Analyzing trace with hash 1468151470, now seen corresponding path program 1 times [2019-05-23 09:36:46,298 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 09:36:46,301 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 09:36:46,302 WARN L146 ILogger]: Trace formula consists of 8 conjuncts, 4 conjunts are in the unsatisfiable core [2019-05-23 09:36:46,302 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 09:36:46,365 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 09:36:46,365 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 09:36:46,365 INFO L146 ILogger]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-05-23 09:36:46,365 INFO L146 ILogger]: Interpolant automaton has 5 states [2019-05-23 09:36:46,366 INFO L146 ILogger]: Constructing interpolant automaton starting with 5 interpolants. [2019-05-23 09:36:46,366 INFO L146 ILogger]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-05-23 09:36:46,366 INFO L146 ILogger]: Start difference. First operand 509 states and 518 transitions. Second operand 5 states. [2019-05-23 09:36:46,473 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 09:36:46,473 INFO L146 ILogger]: Finished difference Result 508 states and 517 transitions. [2019-05-23 09:36:46,474 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-05-23 09:36:46,474 INFO L146 ILogger]: Start accepts. Automaton has 5 states. Word has length 6 [2019-05-23 09:36:46,474 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 09:36:46,476 INFO L146 ILogger]: With dead ends: 508 [2019-05-23 09:36:46,477 INFO L146 ILogger]: Without dead ends: 508 [2019-05-23 09:36:46,477 INFO L146 ILogger]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-05-23 09:36:46,478 INFO L146 ILogger]: Start minimizeSevpa. Operand 508 states. [2019-05-23 09:36:46,485 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 508 to 508. [2019-05-23 09:36:46,485 INFO L146 ILogger]: Start removeUnreachable. Operand 508 states. [2019-05-23 09:36:46,487 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 508 states to 508 states and 517 transitions. [2019-05-23 09:36:46,487 INFO L146 ILogger]: Start accepts. Automaton has 508 states and 517 transitions. Word has length 6 [2019-05-23 09:36:46,487 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 09:36:46,487 INFO L146 ILogger]: Abstraction has 508 states and 517 transitions. [2019-05-23 09:36:46,487 INFO L146 ILogger]: Interpolant automaton has 5 states. [2019-05-23 09:36:46,488 INFO L146 ILogger]: Start isEmpty. Operand 508 states and 517 transitions. [2019-05-23 09:36:46,488 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 8 [2019-05-23 09:36:46,488 INFO L146 ILogger]: Found error trace [2019-05-23 09:36:46,488 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2019-05-23 09:36:46,493 INFO L146 ILogger]: === Iteration 8 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT]=== [2019-05-23 09:36:46,493 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 09:36:46,494 INFO L146 ILogger]: Analyzing trace with hash 437427531, now seen corresponding path program 1 times [2019-05-23 09:36:46,497 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 09:36:46,501 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 09:36:46,502 INFO L146 ILogger]: Trace formula consists of 9 conjuncts, 3 conjunts are in the unsatisfiable core [2019-05-23 09:36:46,506 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 09:36:46,521 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 09:36:46,522 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 09:36:46,522 INFO L146 ILogger]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-05-23 09:36:46,522 INFO L146 ILogger]: Interpolant automaton has 4 states [2019-05-23 09:36:46,522 INFO L146 ILogger]: Constructing interpolant automaton starting with 4 interpolants. [2019-05-23 09:36:46,523 INFO L146 ILogger]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-05-23 09:36:46,523 INFO L146 ILogger]: Start difference. First operand 508 states and 517 transitions. Second operand 4 states. [2019-05-23 09:36:46,557 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 09:36:46,557 INFO L146 ILogger]: Finished difference Result 507 states and 516 transitions. [2019-05-23 09:36:46,558 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-05-23 09:36:46,558 INFO L146 ILogger]: Start accepts. Automaton has 4 states. Word has length 7 [2019-05-23 09:36:46,558 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 09:36:46,560 INFO L146 ILogger]: With dead ends: 507 [2019-05-23 09:36:46,561 INFO L146 ILogger]: Without dead ends: 507 [2019-05-23 09:36:46,561 INFO L146 ILogger]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-05-23 09:36:46,562 INFO L146 ILogger]: Start minimizeSevpa. Operand 507 states. [2019-05-23 09:36:46,569 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 507 to 507. [2019-05-23 09:36:46,569 INFO L146 ILogger]: Start removeUnreachable. Operand 507 states. [2019-05-23 09:36:46,571 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 507 states to 507 states and 516 transitions. [2019-05-23 09:36:46,572 INFO L146 ILogger]: Start accepts. Automaton has 507 states and 516 transitions. Word has length 7 [2019-05-23 09:36:46,572 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 09:36:46,572 INFO L146 ILogger]: Abstraction has 507 states and 516 transitions. [2019-05-23 09:36:46,572 INFO L146 ILogger]: Interpolant automaton has 4 states. [2019-05-23 09:36:46,573 INFO L146 ILogger]: Start isEmpty. Operand 507 states and 516 transitions. [2019-05-23 09:36:46,573 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 8 [2019-05-23 09:36:46,573 INFO L146 ILogger]: Found error trace [2019-05-23 09:36:46,574 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2019-05-23 09:36:46,575 INFO L146 ILogger]: === Iteration 9 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT]=== [2019-05-23 09:36:46,575 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 09:36:46,576 INFO L146 ILogger]: Analyzing trace with hash 102232374, now seen corresponding path program 1 times [2019-05-23 09:36:46,577 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 09:36:46,580 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 09:36:46,581 INFO L146 ILogger]: Trace formula consists of 9 conjuncts, 4 conjunts are in the unsatisfiable core [2019-05-23 09:36:46,582 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 09:36:46,805 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 09:36:46,806 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 09:36:46,806 INFO L146 ILogger]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-05-23 09:36:46,806 INFO L146 ILogger]: Interpolant automaton has 5 states [2019-05-23 09:36:46,807 INFO L146 ILogger]: Constructing interpolant automaton starting with 5 interpolants. [2019-05-23 09:36:46,807 INFO L146 ILogger]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-05-23 09:36:46,807 INFO L146 ILogger]: Start difference. First operand 507 states and 516 transitions. Second operand 5 states. [2019-05-23 09:36:47,125 WARN L146 ILogger]: Spent 107.00 ms on a formula simplification that was a NOOP. DAG size: 11 [2019-05-23 09:36:47,290 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 09:36:47,290 INFO L146 ILogger]: Finished difference Result 506 states and 515 transitions. [2019-05-23 09:36:47,291 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-05-23 09:36:47,291 INFO L146 ILogger]: Start accepts. Automaton has 5 states. Word has length 7 [2019-05-23 09:36:47,291 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 09:36:47,294 INFO L146 ILogger]: With dead ends: 506 [2019-05-23 09:36:47,294 INFO L146 ILogger]: Without dead ends: 506 [2019-05-23 09:36:47,295 INFO L146 ILogger]: 0 DeclaredPredicates, 8 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-05-23 09:36:47,296 INFO L146 ILogger]: Start minimizeSevpa. Operand 506 states. [2019-05-23 09:36:47,303 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 506 to 506. [2019-05-23 09:36:47,303 INFO L146 ILogger]: Start removeUnreachable. Operand 506 states. [2019-05-23 09:36:47,305 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 506 states to 506 states and 515 transitions. [2019-05-23 09:36:47,305 INFO L146 ILogger]: Start accepts. Automaton has 506 states and 515 transitions. Word has length 7 [2019-05-23 09:36:47,305 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 09:36:47,306 INFO L146 ILogger]: Abstraction has 506 states and 515 transitions. [2019-05-23 09:36:47,306 INFO L146 ILogger]: Interpolant automaton has 5 states. [2019-05-23 09:36:47,306 INFO L146 ILogger]: Start isEmpty. Operand 506 states and 515 transitions. [2019-05-23 09:36:47,306 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 10 [2019-05-23 09:36:47,307 INFO L146 ILogger]: Found error trace [2019-05-23 09:36:47,307 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-05-23 09:36:47,307 INFO L146 ILogger]: === Iteration 10 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT]=== [2019-05-23 09:36:47,308 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 09:36:47,308 INFO L146 ILogger]: Analyzing trace with hash -538909933, now seen corresponding path program 1 times [2019-05-23 09:36:47,309 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 09:36:47,312 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 09:36:47,313 INFO L146 ILogger]: Trace formula consists of 11 conjuncts, 4 conjunts are in the unsatisfiable core [2019-05-23 09:36:47,314 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 09:36:47,491 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 09:36:47,492 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 09:36:47,492 INFO L146 ILogger]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-05-23 09:36:47,492 INFO L146 ILogger]: Interpolant automaton has 5 states [2019-05-23 09:36:47,492 INFO L146 ILogger]: Constructing interpolant automaton starting with 5 interpolants. [2019-05-23 09:36:47,493 INFO L146 ILogger]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-05-23 09:36:47,493 INFO L146 ILogger]: Start difference. First operand 506 states and 515 transitions. Second operand 5 states. [2019-05-23 09:36:47,591 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 09:36:47,593 INFO L146 ILogger]: Finished difference Result 505 states and 514 transitions. [2019-05-23 09:36:47,596 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-05-23 09:36:47,596 INFO L146 ILogger]: Start accepts. Automaton has 5 states. Word has length 9 [2019-05-23 09:36:47,596 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 09:36:47,599 INFO L146 ILogger]: With dead ends: 505 [2019-05-23 09:36:47,599 INFO L146 ILogger]: Without dead ends: 505 [2019-05-23 09:36:47,599 INFO L146 ILogger]: 0 DeclaredPredicates, 10 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-05-23 09:36:47,600 INFO L146 ILogger]: Start minimizeSevpa. Operand 505 states. [2019-05-23 09:36:47,606 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 505 to 505. [2019-05-23 09:36:47,607 INFO L146 ILogger]: Start removeUnreachable. Operand 505 states. [2019-05-23 09:36:47,608 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 505 states to 505 states and 514 transitions. [2019-05-23 09:36:47,609 INFO L146 ILogger]: Start accepts. Automaton has 505 states and 514 transitions. Word has length 9 [2019-05-23 09:36:47,609 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 09:36:47,609 INFO L146 ILogger]: Abstraction has 505 states and 514 transitions. [2019-05-23 09:36:47,609 INFO L146 ILogger]: Interpolant automaton has 5 states. [2019-05-23 09:36:47,609 INFO L146 ILogger]: Start isEmpty. Operand 505 states and 514 transitions. [2019-05-23 09:36:47,610 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 11 [2019-05-23 09:36:47,610 INFO L146 ILogger]: Found error trace [2019-05-23 09:36:47,610 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-05-23 09:36:47,611 INFO L146 ILogger]: === Iteration 11 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT]=== [2019-05-23 09:36:47,611 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 09:36:47,611 INFO L146 ILogger]: Analyzing trace with hash -895437985, now seen corresponding path program 1 times [2019-05-23 09:36:47,612 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 09:36:47,615 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 09:36:47,616 INFO L146 ILogger]: Trace formula consists of 12 conjuncts, 5 conjunts are in the unsatisfiable core [2019-05-23 09:36:47,617 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 09:36:47,691 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 09:36:47,692 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 09:36:47,692 INFO L146 ILogger]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-05-23 09:36:47,692 INFO L146 ILogger]: Interpolant automaton has 6 states [2019-05-23 09:36:47,692 INFO L146 ILogger]: Constructing interpolant automaton starting with 6 interpolants. [2019-05-23 09:36:47,693 INFO L146 ILogger]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-05-23 09:36:47,693 INFO L146 ILogger]: Start difference. First operand 505 states and 514 transitions. Second operand 6 states. [2019-05-23 09:36:47,986 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 09:36:47,986 INFO L146 ILogger]: Finished difference Result 504 states and 513 transitions. [2019-05-23 09:36:47,987 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-05-23 09:36:47,987 INFO L146 ILogger]: Start accepts. Automaton has 6 states. Word has length 10 [2019-05-23 09:36:47,987 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 09:36:47,989 INFO L146 ILogger]: With dead ends: 504 [2019-05-23 09:36:47,989 INFO L146 ILogger]: Without dead ends: 494 [2019-05-23 09:36:47,990 INFO L146 ILogger]: 0 DeclaredPredicates, 12 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-05-23 09:36:47,991 INFO L146 ILogger]: Start minimizeSevpa. Operand 494 states. [2019-05-23 09:36:47,997 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 494 to 494. [2019-05-23 09:36:47,998 INFO L146 ILogger]: Start removeUnreachable. Operand 494 states. [2019-05-23 09:36:47,999 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 494 states to 494 states and 504 transitions. [2019-05-23 09:36:47,999 INFO L146 ILogger]: Start accepts. Automaton has 494 states and 504 transitions. Word has length 10 [2019-05-23 09:36:48,000 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 09:36:48,000 INFO L146 ILogger]: Abstraction has 494 states and 504 transitions. [2019-05-23 09:36:48,000 INFO L146 ILogger]: Interpolant automaton has 6 states. [2019-05-23 09:36:48,000 INFO L146 ILogger]: Start isEmpty. Operand 494 states and 504 transitions. [2019-05-23 09:36:48,001 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 13 [2019-05-23 09:36:48,001 INFO L146 ILogger]: Found error trace [2019-05-23 09:36:48,001 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-05-23 09:36:48,002 INFO L146 ILogger]: === Iteration 12 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT]=== [2019-05-23 09:36:48,002 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 09:36:48,002 INFO L146 ILogger]: Analyzing trace with hash -213657467, now seen corresponding path program 1 times [2019-05-23 09:36:48,004 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 09:36:48,008 INFO L146 ILogger]: Conjunction of SSA is sat [2019-05-23 09:36:48,012 INFO L146 ILogger]: Conjunction of SSA is sat [2019-05-23 09:36:48,025 INFO L146 ILogger]: Counterexample might be feasible [2019-05-23 09:36:48,038 INFO L146 ILogger]: Did not count any witness invariants because Icfg is not BoogieIcfg [2019-05-23 09:36:48,040 INFO L146 ILogger]: Adding new model GuiTestExample.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 23.05 09:36:48 BasicIcfg [2019-05-23 09:36:48,040 INFO L146 ILogger]: ------------------------ END TraceAbstraction---------------------------- [2019-05-23 09:36:48,043 INFO L146 ILogger]: Toolchain (without parser) took 5798.31 ms. Allocated memory was 137.9 MB in the beginning and 200.8 MB in the end (delta: 62.9 MB). Free memory was 106.4 MB in the beginning and 59.0 MB in the end (delta: 47.4 MB). Peak memory consumption was 110.3 MB. Max. memory is 7.1 GB. [2019-05-23 09:36:48,045 INFO L146 ILogger]: Boogie PL CUP Parser took 0.20 ms. Allocated memory is still 137.9 MB. Free memory was 108.9 MB in the beginning and 108.7 MB in the end (delta: 210.0 kB). Peak memory consumption was 210.0 kB. Max. memory is 7.1 GB. [2019-05-23 09:36:48,046 INFO L146 ILogger]: Boogie Procedure Inliner took 118.24 ms. Allocated memory is still 137.9 MB. Free memory was 106.2 MB in the beginning and 102.4 MB in the end (delta: 3.8 MB). Peak memory consumption was 3.8 MB. Max. memory is 7.1 GB. [2019-05-23 09:36:48,048 INFO L146 ILogger]: Boogie Preprocessor took 65.52 ms. Allocated memory is still 137.9 MB. Free memory was 102.4 MB in the beginning and 100.0 MB in the end (delta: 2.4 MB). Peak memory consumption was 2.4 MB. Max. memory is 7.1 GB. [2019-05-23 09:36:48,049 INFO L146 ILogger]: RCFGBuilder took 2155.73 ms. Allocated memory was 137.9 MB in the beginning and 178.8 MB in the end (delta: 40.9 MB). Free memory was 100.0 MB in the beginning and 104.5 MB in the end (delta: -4.5 MB). Peak memory consumption was 48.8 MB. Max. memory is 7.1 GB. [2019-05-23 09:36:48,050 INFO L146 ILogger]: IcfgTransformer took 74.13 ms. Allocated memory is still 178.8 MB. Free memory was 104.5 MB in the beginning and 99.0 MB in the end (delta: 5.5 MB). Peak memory consumption was 5.5 MB. Max. memory is 7.1 GB. [2019-05-23 09:36:48,051 INFO L146 ILogger]: TraceAbstraction took 3379.37 ms. Allocated memory was 178.8 MB in the beginning and 200.8 MB in the end (delta: 22.0 MB). Free memory was 99.0 MB in the beginning and 59.0 MB in the end (delta: 40.0 MB). Peak memory consumption was 62.0 MB. Max. memory is 7.1 GB. [2019-05-23 09:36:48,061 INFO L146 ILogger]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * Boogie PL CUP Parser took 0.20 ms. Allocated memory is still 137.9 MB. Free memory was 108.9 MB in the beginning and 108.7 MB in the end (delta: 210.0 kB). Peak memory consumption was 210.0 kB. Max. memory is 7.1 GB. * Boogie Procedure Inliner took 118.24 ms. Allocated memory is still 137.9 MB. Free memory was 106.2 MB in the beginning and 102.4 MB in the end (delta: 3.8 MB). Peak memory consumption was 3.8 MB. Max. memory is 7.1 GB. * Boogie Preprocessor took 65.52 ms. Allocated memory is still 137.9 MB. Free memory was 102.4 MB in the beginning and 100.0 MB in the end (delta: 2.4 MB). Peak memory consumption was 2.4 MB. Max. memory is 7.1 GB. * RCFGBuilder took 2155.73 ms. Allocated memory was 137.9 MB in the beginning and 178.8 MB in the end (delta: 40.9 MB). Free memory was 100.0 MB in the beginning and 104.5 MB in the end (delta: -4.5 MB). Peak memory consumption was 48.8 MB. Max. memory is 7.1 GB. * IcfgTransformer took 74.13 ms. Allocated memory is still 178.8 MB. Free memory was 104.5 MB in the beginning and 99.0 MB in the end (delta: 5.5 MB). Peak memory consumption was 5.5 MB. Max. memory is 7.1 GB. * TraceAbstraction took 3379.37 ms. Allocated memory was 178.8 MB in the beginning and 200.8 MB in the end (delta: 22.0 MB). Free memory was 99.0 MB in the beginning and 59.0 MB in the end (delta: 40.0 MB). Peak memory consumption was 62.0 MB. Max. memory is 7.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 658]: assertion can be violated assertion can be violated We found a FailurePath: [L642] requires void$SimpleFrame2Cons$4$actionPerformed$4888$__this != $null; [L651] r0125 := void$SimpleFrame2Cons$4$actionPerformed$4888$__this; [L653] r1126 := void$SimpleFrame2Cons$4$actionPerformed$4888$param_0; [L655] $r2129 := SimpleFrame2Cons$SimpleFrame2Cons$4$this$0763; [L390] r083 := $param_0; [L392] $r185 := javax.swing.JButton$SimpleFrame2Cons$event2227; [L394] __ret := $r185; [L658] assert $r3130 != $null; - StatisticsResult: Ultimate Automizer benchmark data CFG has 16 procedures, 645 locations, 87 error locations. UNSAFE Result, 3.3s OverallTime, 12 OverallIterations, 1 TraceHistogramMax, 1.7s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 5874 SDtfs, 1503 SDslu, 12880 SDs, 0 SdLazy, 82 SolverSat, 11 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.6s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 71 GetRequests, 28 SyntacticMatches, 0 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.7s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=645occurred in iteration=0, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.2s AutomataMinimizationTime, 11 MinimizatonAttempts, 0 StatesRemovedByMinimization, 0 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.0s SatisfiabilityAnalysisTime, 1.0s InterpolantComputationTime, 78 NumberOfCodeBlocks, 78 NumberOfCodeBlocksAsserted, 12 NumberOfCheckSat, 55 ConstructedInterpolants, 0 QuantifiedInterpolants, 1026 SizeOfPredicates, 16 NumberOfNonLiveVariables, 88 ConjunctsInSsa, 38 ConjunctsInUnsatCore, 11 InterpolantComputations, 11 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...