java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data --rcfgbuilder.command.for.external.solver 'z3 SMTLIB2_COMPLIANT=true -memory:4096 -smt2 -in -t:12000' -tc ../../../trunk/examples/toolchains/AutomizerBplInlineTransformed.xml --icfgtransformation.transformationtype MAP_ELIMINATION_MONNIAUX --rcfgbuilder.size.of.a.code.block SingleStatement --icfgtransformation.map.elimination.monniaux.number.of.cells 1 -i ../../../trunk/examples/programs/real-life/GuiTestExampleUnsafe.bpl -------------------------------------------------------------------------------- This is Ultimate 0.1.24-7aa59a0 [2019-05-23 09:36:42,294 INFO L146 ILogger]: Resetting all preferences to default values... [2019-05-23 09:36:42,299 INFO L146 ILogger]: Resetting UltimateCore preferences to default values [2019-05-23 09:36:42,317 INFO L146 ILogger]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-05-23 09:36:42,318 INFO L146 ILogger]: Resetting Boogie Preprocessor preferences to default values [2019-05-23 09:36:42,320 INFO L146 ILogger]: Resetting Boogie Procedure Inliner preferences to default values [2019-05-23 09:36:42,321 INFO L146 ILogger]: Resetting Abstract Interpretation preferences to default values [2019-05-23 09:36:42,324 INFO L146 ILogger]: Resetting LassoRanker preferences to default values [2019-05-23 09:36:42,326 INFO L146 ILogger]: Resetting Reaching Definitions preferences to default values [2019-05-23 09:36:42,327 INFO L146 ILogger]: Resetting SyntaxChecker preferences to default values [2019-05-23 09:36:42,335 INFO L146 ILogger]: Büchi Program Product provides no preferences, ignoring... [2019-05-23 09:36:42,336 INFO L146 ILogger]: Resetting LTL2Aut preferences to default values [2019-05-23 09:36:42,338 INFO L146 ILogger]: Resetting PEA to Boogie preferences to default values [2019-05-23 09:36:42,339 INFO L146 ILogger]: Resetting BlockEncodingV2 preferences to default values [2019-05-23 09:36:42,342 INFO L146 ILogger]: Resetting ChcToBoogie preferences to default values [2019-05-23 09:36:42,344 INFO L146 ILogger]: Resetting AutomataScriptInterpreter preferences to default values [2019-05-23 09:36:42,345 INFO L146 ILogger]: Resetting BuchiAutomizer preferences to default values [2019-05-23 09:36:42,349 INFO L146 ILogger]: Resetting CACSL2BoogieTranslator preferences to default values [2019-05-23 09:36:42,353 INFO L146 ILogger]: Resetting CodeCheck preferences to default values [2019-05-23 09:36:42,356 INFO L146 ILogger]: Resetting InvariantSynthesis preferences to default values [2019-05-23 09:36:42,357 INFO L146 ILogger]: Resetting RCFGBuilder preferences to default values [2019-05-23 09:36:42,358 INFO L146 ILogger]: Resetting TraceAbstraction preferences to default values [2019-05-23 09:36:42,361 INFO L146 ILogger]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-05-23 09:36:42,362 INFO L146 ILogger]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-05-23 09:36:42,362 INFO L146 ILogger]: Resetting TreeAutomizer preferences to default values [2019-05-23 09:36:42,363 INFO L146 ILogger]: Resetting IcfgToChc preferences to default values [2019-05-23 09:36:42,363 INFO L146 ILogger]: Resetting IcfgTransformer preferences to default values [2019-05-23 09:36:42,364 INFO L146 ILogger]: ReqToTest provides no preferences, ignoring... [2019-05-23 09:36:42,367 INFO L146 ILogger]: Resetting Boogie Printer preferences to default values [2019-05-23 09:36:42,368 INFO L146 ILogger]: Resetting ChcSmtPrinter preferences to default values [2019-05-23 09:36:42,369 INFO L146 ILogger]: Resetting ReqPrinter preferences to default values [2019-05-23 09:36:42,372 INFO L146 ILogger]: Resetting Witness Printer preferences to default values [2019-05-23 09:36:42,374 INFO L146 ILogger]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-05-23 09:36:42,374 INFO L146 ILogger]: Resetting CDTParser preferences to default values [2019-05-23 09:36:42,375 INFO L146 ILogger]: AutomataScriptParser provides no preferences, ignoring... [2019-05-23 09:36:42,375 INFO L146 ILogger]: ReqParser provides no preferences, ignoring... [2019-05-23 09:36:42,375 INFO L146 ILogger]: Resetting SmtParser preferences to default values [2019-05-23 09:36:42,377 INFO L146 ILogger]: Resetting Witness Parser preferences to default values [2019-05-23 09:36:42,377 INFO L146 ILogger]: Finished resetting all preferences to default values... Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder: Command for external solver -> z3 SMTLIB2_COMPLIANT=true -memory:4096 -smt2 -in -t:12000 Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation: TransformationType -> MAP_ELIMINATION_MONNIAUX Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder: Size of a code block -> SingleStatement Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation: Map elimination Monniaux: number of cells -> 1 [2019-05-23 09:36:42,414 INFO L146 ILogger]: Repository-Root is: /tmp [2019-05-23 09:36:42,426 INFO L146 ILogger]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-05-23 09:36:42,430 INFO L146 ILogger]: [Toolchain 1]: Toolchain selected. [2019-05-23 09:36:42,431 INFO L146 ILogger]: Initializing Boogie PL CUP Parser... [2019-05-23 09:36:42,432 INFO L146 ILogger]: Boogie PL CUP Parser initialized [2019-05-23 09:36:42,433 INFO L146 ILogger]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/programs/real-life/GuiTestExampleUnsafe.bpl [2019-05-23 09:36:42,433 INFO L146 ILogger]: Parsing: '/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/programs/real-life/GuiTestExampleUnsafe.bpl' [2019-05-23 09:36:42,500 INFO L146 ILogger]: ####################### [Toolchain 1] ####################### [2019-05-23 09:36:42,502 INFO L146 ILogger]: Walking toolchain with 5 elements. [2019-05-23 09:36:42,503 INFO L146 ILogger]: ------------------------Boogie Procedure Inliner---------------------------- [2019-05-23 09:36:42,503 INFO L146 ILogger]: Initializing Boogie Procedure Inliner... [2019-05-23 09:36:42,503 INFO L146 ILogger]: Boogie Procedure Inliner initialized [2019-05-23 09:36:42,520 INFO L146 ILogger]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 09:36:42" (1/1) ... [2019-05-23 09:36:42,537 INFO L146 ILogger]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 09:36:42" (1/1) ... [2019-05-23 09:36:42,546 WARN L146 ILogger]: Program contained no entry procedure! [2019-05-23 09:36:42,546 WARN L146 ILogger]: Missing entry procedures: [ULTIMATE.start] [2019-05-23 09:36:42,547 WARN L146 ILogger]: Fallback enabled. All procedures will be processed. [2019-05-23 09:36:42,587 INFO L146 ILogger]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-05-23 09:36:42,588 INFO L146 ILogger]: ------------------------Boogie Preprocessor---------------------------- [2019-05-23 09:36:42,588 INFO L146 ILogger]: Initializing Boogie Preprocessor... [2019-05-23 09:36:42,588 INFO L146 ILogger]: Boogie Preprocessor initialized [2019-05-23 09:36:42,600 INFO L146 ILogger]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 09:36:42" (1/1) ... [2019-05-23 09:36:42,600 INFO L146 ILogger]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 09:36:42" (1/1) ... [2019-05-23 09:36:42,609 INFO L146 ILogger]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 09:36:42" (1/1) ... [2019-05-23 09:36:42,610 INFO L146 ILogger]: Executing the observer StructExpander from plugin Boogie Preprocessor for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 09:36:42" (1/1) ... [2019-05-23 09:36:42,628 INFO L146 ILogger]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 09:36:42" (1/1) ... [2019-05-23 09:36:42,635 INFO L146 ILogger]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 09:36:42" (1/1) ... [2019-05-23 09:36:42,645 INFO L146 ILogger]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 09:36:42" (1/1) ... [2019-05-23 09:36:42,659 INFO L146 ILogger]: ------------------------ END Boogie Preprocessor---------------------------- [2019-05-23 09:36:42,660 INFO L146 ILogger]: ------------------------RCFGBuilder---------------------------- [2019-05-23 09:36:42,660 INFO L146 ILogger]: Initializing RCFGBuilder... [2019-05-23 09:36:42,660 INFO L146 ILogger]: RCFGBuilder initialized [2019-05-23 09:36:42,664 INFO L146 ILogger]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 09:36:42" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:4096 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:4096 -smt2 -in -t:12000 [2019-05-23 09:36:42,734 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$3$$la$init$ra$$4885 given in one single declaration [2019-05-23 09:36:42,734 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$3$$la$init$ra$$4885 [2019-05-23 09:36:42,734 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$3$$la$init$ra$$4885 [2019-05-23 09:36:42,735 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$2$actionPerformed$4553 given in one single declaration [2019-05-23 09:36:42,735 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$2$actionPerformed$4553 [2019-05-23 09:36:42,735 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$2$actionPerformed$4553 [2019-05-23 09:36:42,735 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$3$actionPerformed$4886 given in one single declaration [2019-05-23 09:36:42,736 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$3$actionPerformed$4886 [2019-05-23 09:36:42,736 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$3$actionPerformed$4886 [2019-05-23 09:36:42,736 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$$la$init$ra$$1805 given in one single declaration [2019-05-23 09:36:42,736 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$$la$init$ra$$1805 [2019-05-23 09:36:42,736 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$$la$init$ra$$1805 [2019-05-23 09:36:42,737 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$1$$la$init$ra$$1802 given in one single declaration [2019-05-23 09:36:42,737 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$1$$la$init$ra$$1802 [2019-05-23 09:36:42,737 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$1$$la$init$ra$$1802 [2019-05-23 09:36:42,737 INFO L146 ILogger]: Found specification of procedure void$javax.swing.SwingUtilities$invokeLater$4940 [2019-05-23 09:36:42,737 INFO L146 ILogger]: Found specification of procedure void$javax.swing.JFrame$setLayout$1827 [2019-05-23 09:36:42,738 INFO L146 ILogger]: Specification and implementation of procedure javax.swing.JButton$SimpleFrame2Cons$access$0$1806 given in one single declaration [2019-05-23 09:36:42,738 INFO L146 ILogger]: Found specification of procedure javax.swing.JButton$SimpleFrame2Cons$access$0$1806 [2019-05-23 09:36:42,739 INFO L146 ILogger]: Found implementation of procedure javax.swing.JButton$SimpleFrame2Cons$access$0$1806 [2019-05-23 09:36:42,739 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$2$$la$init$ra$$4552 given in one single declaration [2019-05-23 09:36:42,739 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$2$$la$init$ra$$4552 [2019-05-23 09:36:42,739 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$2$$la$init$ra$$4552 [2019-05-23 09:36:42,739 INFO L146 ILogger]: Found specification of procedure void$java.awt.Frame$setResizable$1858 [2019-05-23 09:36:42,740 INFO L146 ILogger]: Specification and implementation of procedure java.awt.Dimension$java.awt.Toolkit$getScreenSize$3246 given in one single declaration [2019-05-23 09:36:42,740 INFO L146 ILogger]: Found specification of procedure java.awt.Dimension$java.awt.Toolkit$getScreenSize$3246 [2019-05-23 09:36:42,740 INFO L146 ILogger]: Found implementation of procedure java.awt.Dimension$java.awt.Toolkit$getScreenSize$3246 [2019-05-23 09:36:42,740 INFO L146 ILogger]: Specification and implementation of procedure void$javax.swing.JFrame$$la$init$ra$$1809 given in one single declaration [2019-05-23 09:36:42,740 INFO L146 ILogger]: Found specification of procedure void$javax.swing.JFrame$$la$init$ra$$1809 [2019-05-23 09:36:42,741 INFO L146 ILogger]: Found implementation of procedure void$javax.swing.JFrame$$la$init$ra$$1809 [2019-05-23 09:36:42,742 INFO L146 ILogger]: Specification and implementation of procedure int$SimpleFrame2Cons$access$2$1808 given in one single declaration [2019-05-23 09:36:42,742 INFO L146 ILogger]: Found specification of procedure int$SimpleFrame2Cons$access$2$1808 [2019-05-23 09:36:42,742 INFO L146 ILogger]: Found implementation of procedure int$SimpleFrame2Cons$access$2$1808 [2019-05-23 09:36:42,742 INFO L146 ILogger]: Found specification of procedure void$javax.swing.JFrame$setDefaultCloseOperation$1816 [2019-05-23 09:36:42,742 INFO L146 ILogger]: Found specification of procedure void$javax.swing.AbstractButton$addActionListener$4123 [2019-05-23 09:36:42,742 INFO L146 ILogger]: Found specification of procedure void$java.awt.Window$setLocation$1913 [2019-05-23 09:36:42,743 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$4$$la$init$ra$$4887 given in one single declaration [2019-05-23 09:36:42,743 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$4$$la$init$ra$$4887 [2019-05-23 09:36:42,743 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$4$$la$init$ra$$4887 [2019-05-23 09:36:42,743 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$4$actionPerformed$4888 given in one single declaration [2019-05-23 09:36:42,743 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$4$actionPerformed$4888 [2019-05-23 09:36:42,744 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$4$actionPerformed$4888 [2019-05-23 09:36:42,744 INFO L146 ILogger]: Found specification of procedure void$javax.swing.AbstractButton$setEnabled$4131 [2019-05-23 09:36:42,744 INFO L146 ILogger]: Found specification of procedure void$java.awt.Window$setVisible$1918 [2019-05-23 09:36:42,744 INFO L146 ILogger]: Found specification of procedure int$java.awt.Component$getHeight$2305 [2019-05-23 09:36:42,744 INFO L146 ILogger]: Found specification of procedure void$java.awt.Window$pack$1909 [2019-05-23 09:36:42,745 INFO L146 ILogger]: Found specification of procedure java.awt.Toolkit$java.awt.Toolkit$getDefaultToolkit$3255 [2019-05-23 09:36:42,745 INFO L146 ILogger]: Found specification of procedure int$java.awt.Component$getWidth$2304 [2019-05-23 09:36:42,745 INFO L146 ILogger]: Found specification of procedure void$java.awt.Frame$setTitle$1852 [2019-05-23 09:36:42,745 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$access$1$1807 given in one single declaration [2019-05-23 09:36:42,745 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$access$1$1807 [2019-05-23 09:36:42,746 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$access$1$1807 [2019-05-23 09:36:42,746 INFO L146 ILogger]: Found specification of procedure void$java.awt.FlowLayout$$la$init$ra$$4889 [2019-05-23 09:36:42,746 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$1$run$1803 given in one single declaration [2019-05-23 09:36:42,746 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$1$run$1803 [2019-05-23 09:36:42,746 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$1$run$1803 [2019-05-23 09:36:42,747 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$main$1804 given in one single declaration [2019-05-23 09:36:42,747 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$main$1804 [2019-05-23 09:36:42,747 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$main$1804 [2019-05-23 09:36:42,747 INFO L146 ILogger]: Found specification of procedure void$javax.swing.JButton$$la$init$ra$$2558 [2019-05-23 09:36:42,748 INFO L146 ILogger]: Specification and implementation of procedure $EFG_Procedure given in one single declaration [2019-05-23 09:36:42,748 INFO L146 ILogger]: Found specification of procedure $EFG_Procedure [2019-05-23 09:36:42,748 INFO L146 ILogger]: Found implementation of procedure $EFG_Procedure [2019-05-23 09:36:42,748 INFO L146 ILogger]: Found specification of procedure java.awt.Component$java.awt.Container$add$2075 [2019-05-23 09:36:42,748 INFO L146 ILogger]: Found specification of procedure void$java.lang.Object$$la$init$ra$$38 [2019-05-23 09:36:43,034 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 09:36:43,223 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 09:36:43,420 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 09:36:43,499 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 09:36:43,992 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 09:36:44,004 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 09:36:44,015 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 09:36:44,024 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 09:36:44,037 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 09:36:44,045 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 09:36:44,083 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 09:36:44,912 INFO L146 ILogger]: Using library mode [2019-05-23 09:36:44,913 INFO L146 ILogger]: Removed 44 assume(true) statements. [2019-05-23 09:36:44,914 INFO L146 ILogger]: Adding new model GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.05 09:36:44 BoogieIcfgContainer [2019-05-23 09:36:44,914 INFO L146 ILogger]: ------------------------ END RCFGBuilder---------------------------- [2019-05-23 09:36:44,915 INFO L146 ILogger]: ------------------------IcfgTransformer---------------------------- [2019-05-23 09:36:44,915 INFO L146 ILogger]: Initializing IcfgTransformer... [2019-05-23 09:36:44,916 INFO L146 ILogger]: IcfgTransformer initialized [2019-05-23 09:36:44,920 INFO L146 ILogger]: Executing the observer IcfgTransformationObserver from plugin IcfgTransformer for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.05 09:36:44" (1/1) ... [2019-05-23 09:36:44,995 INFO L146 ILogger]: Adding new model GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 23.05 09:36:44 BasicIcfg [2019-05-23 09:36:44,995 INFO L146 ILogger]: ------------------------ END IcfgTransformer---------------------------- [2019-05-23 09:36:44,997 INFO L146 ILogger]: ------------------------TraceAbstraction---------------------------- [2019-05-23 09:36:44,997 INFO L146 ILogger]: Initializing TraceAbstraction... [2019-05-23 09:36:45,003 INFO L146 ILogger]: TraceAbstraction initialized [2019-05-23 09:36:45,006 INFO L146 ILogger]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 09:36:42" (1/3) ... [2019-05-23 09:36:45,008 INFO L146 ILogger]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@14cca619 and model type GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.05 09:36:45, skipping insertion in model container [2019-05-23 09:36:45,008 INFO L146 ILogger]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.05 09:36:44" (2/3) ... [2019-05-23 09:36:45,009 INFO L146 ILogger]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@14cca619 and model type GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 23.05 09:36:45, skipping insertion in model container [2019-05-23 09:36:45,009 INFO L146 ILogger]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 23.05 09:36:44" (3/3) ... [2019-05-23 09:36:45,011 INFO L146 ILogger]: Analyzing ICFG GuiTestExampleUnsafe.bplME [2019-05-23 09:36:45,021 INFO L146 ILogger]: Automizer settings: Hoare:false NWA Interpolation:ForwardPredicates Determinization: PREDICATE_ABSTRACTION [2019-05-23 09:36:45,036 INFO L146 ILogger]: Appying trace abstraction to program that has 87 error locations. [2019-05-23 09:36:45,057 INFO L146 ILogger]: Starting to check reachability of 87 error locations. [2019-05-23 09:36:45,084 INFO L146 ILogger]: Using default assertion order modulation [2019-05-23 09:36:45,084 INFO L146 ILogger]: Interprodecural is true [2019-05-23 09:36:45,085 INFO L146 ILogger]: Hoare is false [2019-05-23 09:36:45,085 INFO L146 ILogger]: Compute interpolants for ForwardPredicates [2019-05-23 09:36:45,085 INFO L146 ILogger]: Backedges is STRAIGHT_LINE [2019-05-23 09:36:45,085 INFO L146 ILogger]: Determinization is PREDICATE_ABSTRACTION [2019-05-23 09:36:45,085 INFO L146 ILogger]: Difference is false [2019-05-23 09:36:45,085 INFO L146 ILogger]: Minimize is MINIMIZE_SEVPA [2019-05-23 09:36:45,086 INFO L146 ILogger]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-05-23 09:36:45,137 INFO L146 ILogger]: Start isEmpty. Operand 645 states. [2019-05-23 09:36:45,150 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 4 [2019-05-23 09:36:45,150 INFO L146 ILogger]: Found error trace [2019-05-23 09:36:45,151 INFO L146 ILogger]: trace histogram [1, 1, 1] [2019-05-23 09:36:45,157 INFO L146 ILogger]: === Iteration 1 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT]=== [2019-05-23 09:36:45,164 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 09:36:45,164 INFO L146 ILogger]: Analyzing trace with hash 767125, now seen corresponding path program 1 times [2019-05-23 09:36:45,217 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 09:36:45,240 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 09:36:45,243 WARN L146 ILogger]: Trace formula consists of 5 conjuncts, 3 conjunts are in the unsatisfiable core [2019-05-23 09:36:45,248 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 09:36:45,352 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 09:36:45,354 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 09:36:45,355 INFO L146 ILogger]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-05-23 09:36:45,358 INFO L146 ILogger]: Interpolant automaton has 4 states [2019-05-23 09:36:45,369 INFO L146 ILogger]: Constructing interpolant automaton starting with 4 interpolants. [2019-05-23 09:36:45,370 INFO L146 ILogger]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-05-23 09:36:45,373 INFO L146 ILogger]: Start difference. First operand 645 states. Second operand 4 states. [2019-05-23 09:36:45,607 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 09:36:45,607 INFO L146 ILogger]: Finished difference Result 640 states and 642 transitions. [2019-05-23 09:36:45,609 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-05-23 09:36:45,611 INFO L146 ILogger]: Start accepts. Automaton has 4 states. Word has length 3 [2019-05-23 09:36:45,611 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 09:36:45,654 INFO L146 ILogger]: With dead ends: 640 [2019-05-23 09:36:45,654 INFO L146 ILogger]: Without dead ends: 558 [2019-05-23 09:36:45,657 INFO L146 ILogger]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-05-23 09:36:45,682 INFO L146 ILogger]: Start minimizeSevpa. Operand 558 states. [2019-05-23 09:36:45,753 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 558 to 558. [2019-05-23 09:36:45,755 INFO L146 ILogger]: Start removeUnreachable. Operand 558 states. [2019-05-23 09:36:45,765 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 558 states to 558 states and 564 transitions. [2019-05-23 09:36:45,766 INFO L146 ILogger]: Start accepts. Automaton has 558 states and 564 transitions. Word has length 3 [2019-05-23 09:36:45,767 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 09:36:45,767 INFO L146 ILogger]: Abstraction has 558 states and 564 transitions. [2019-05-23 09:36:45,767 INFO L146 ILogger]: Interpolant automaton has 4 states. [2019-05-23 09:36:45,767 INFO L146 ILogger]: Start isEmpty. Operand 558 states and 564 transitions. [2019-05-23 09:36:45,769 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 5 [2019-05-23 09:36:45,769 INFO L146 ILogger]: Found error trace [2019-05-23 09:36:45,769 INFO L146 ILogger]: trace histogram [1, 1, 1, 1] [2019-05-23 09:36:45,772 INFO L146 ILogger]: === Iteration 2 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT]=== [2019-05-23 09:36:45,773 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 09:36:45,774 INFO L146 ILogger]: Analyzing trace with hash 23874049, now seen corresponding path program 1 times [2019-05-23 09:36:45,775 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 09:36:45,778 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 09:36:45,779 WARN L146 ILogger]: Trace formula consists of 6 conjuncts, 3 conjunts are in the unsatisfiable core [2019-05-23 09:36:45,779 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 09:36:45,806 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 09:36:45,807 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 09:36:45,807 INFO L146 ILogger]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-05-23 09:36:45,808 INFO L146 ILogger]: Interpolant automaton has 4 states [2019-05-23 09:36:45,809 INFO L146 ILogger]: Constructing interpolant automaton starting with 4 interpolants. [2019-05-23 09:36:45,809 INFO L146 ILogger]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-05-23 09:36:45,809 INFO L146 ILogger]: Start difference. First operand 558 states and 564 transitions. Second operand 4 states. [2019-05-23 09:36:45,871 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 09:36:45,871 INFO L146 ILogger]: Finished difference Result 557 states and 563 transitions. [2019-05-23 09:36:45,873 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-05-23 09:36:45,873 INFO L146 ILogger]: Start accepts. Automaton has 4 states. Word has length 4 [2019-05-23 09:36:45,873 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 09:36:45,877 INFO L146 ILogger]: With dead ends: 557 [2019-05-23 09:36:45,877 INFO L146 ILogger]: Without dead ends: 557 [2019-05-23 09:36:45,879 INFO L146 ILogger]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-05-23 09:36:45,880 INFO L146 ILogger]: Start minimizeSevpa. Operand 557 states. [2019-05-23 09:36:45,913 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 557 to 557. [2019-05-23 09:36:45,913 INFO L146 ILogger]: Start removeUnreachable. Operand 557 states. [2019-05-23 09:36:45,920 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 557 states to 557 states and 563 transitions. [2019-05-23 09:36:45,921 INFO L146 ILogger]: Start accepts. Automaton has 557 states and 563 transitions. Word has length 4 [2019-05-23 09:36:45,921 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 09:36:45,921 INFO L146 ILogger]: Abstraction has 557 states and 563 transitions. [2019-05-23 09:36:45,922 INFO L146 ILogger]: Interpolant automaton has 4 states. [2019-05-23 09:36:45,922 INFO L146 ILogger]: Start isEmpty. Operand 557 states and 563 transitions. [2019-05-23 09:36:45,923 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 6 [2019-05-23 09:36:45,923 INFO L146 ILogger]: Found error trace [2019-05-23 09:36:45,923 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1] [2019-05-23 09:36:45,932 INFO L146 ILogger]: === Iteration 3 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT]=== [2019-05-23 09:36:45,932 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 09:36:45,933 INFO L146 ILogger]: Analyzing trace with hash 741050664, now seen corresponding path program 1 times [2019-05-23 09:36:45,936 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 09:36:45,939 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 09:36:45,941 INFO L146 ILogger]: Trace formula consists of 7 conjuncts, 3 conjunts are in the unsatisfiable core [2019-05-23 09:36:45,941 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 09:36:46,064 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 09:36:46,065 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 09:36:46,066 INFO L146 ILogger]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-05-23 09:36:46,066 INFO L146 ILogger]: Interpolant automaton has 4 states [2019-05-23 09:36:46,066 INFO L146 ILogger]: Constructing interpolant automaton starting with 4 interpolants. [2019-05-23 09:36:46,067 INFO L146 ILogger]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-05-23 09:36:46,067 INFO L146 ILogger]: Start difference. First operand 557 states and 563 transitions. Second operand 4 states. [2019-05-23 09:36:46,159 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 09:36:46,163 INFO L146 ILogger]: Finished difference Result 556 states and 562 transitions. [2019-05-23 09:36:46,164 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-05-23 09:36:46,164 INFO L146 ILogger]: Start accepts. Automaton has 4 states. Word has length 5 [2019-05-23 09:36:46,164 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 09:36:46,167 INFO L146 ILogger]: With dead ends: 556 [2019-05-23 09:36:46,168 INFO L146 ILogger]: Without dead ends: 551 [2019-05-23 09:36:46,168 INFO L146 ILogger]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-05-23 09:36:46,170 INFO L146 ILogger]: Start minimizeSevpa. Operand 551 states. [2019-05-23 09:36:46,202 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 551 to 551. [2019-05-23 09:36:46,202 INFO L146 ILogger]: Start removeUnreachable. Operand 551 states. [2019-05-23 09:36:46,204 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 551 states to 551 states and 558 transitions. [2019-05-23 09:36:46,204 INFO L146 ILogger]: Start accepts. Automaton has 551 states and 558 transitions. Word has length 5 [2019-05-23 09:36:46,204 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 09:36:46,205 INFO L146 ILogger]: Abstraction has 551 states and 558 transitions. [2019-05-23 09:36:46,205 INFO L146 ILogger]: Interpolant automaton has 4 states. [2019-05-23 09:36:46,205 INFO L146 ILogger]: Start isEmpty. Operand 551 states and 558 transitions. [2019-05-23 09:36:46,205 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 6 [2019-05-23 09:36:46,206 INFO L146 ILogger]: Found error trace [2019-05-23 09:36:46,206 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1] [2019-05-23 09:36:46,208 INFO L146 ILogger]: === Iteration 4 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT]=== [2019-05-23 09:36:46,209 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 09:36:46,210 INFO L146 ILogger]: Analyzing trace with hash 742004970, now seen corresponding path program 1 times [2019-05-23 09:36:46,211 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 09:36:46,214 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 09:36:46,216 INFO L146 ILogger]: Trace formula consists of 7 conjuncts, 3 conjunts are in the unsatisfiable core [2019-05-23 09:36:46,217 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 09:36:46,240 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 09:36:46,241 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 09:36:46,241 INFO L146 ILogger]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-05-23 09:36:46,241 INFO L146 ILogger]: Interpolant automaton has 4 states [2019-05-23 09:36:46,242 INFO L146 ILogger]: Constructing interpolant automaton starting with 4 interpolants. [2019-05-23 09:36:46,242 INFO L146 ILogger]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-05-23 09:36:46,242 INFO L146 ILogger]: Start difference. First operand 551 states and 558 transitions. Second operand 4 states. [2019-05-23 09:36:46,453 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 09:36:46,453 INFO L146 ILogger]: Finished difference Result 539 states and 546 transitions. [2019-05-23 09:36:46,454 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-05-23 09:36:46,454 INFO L146 ILogger]: Start accepts. Automaton has 4 states. Word has length 5 [2019-05-23 09:36:46,454 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 09:36:46,457 INFO L146 ILogger]: With dead ends: 539 [2019-05-23 09:36:46,457 INFO L146 ILogger]: Without dead ends: 521 [2019-05-23 09:36:46,458 INFO L146 ILogger]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-05-23 09:36:46,460 INFO L146 ILogger]: Start minimizeSevpa. Operand 521 states. [2019-05-23 09:36:46,469 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 521 to 521. [2019-05-23 09:36:46,470 INFO L146 ILogger]: Start removeUnreachable. Operand 521 states. [2019-05-23 09:36:46,472 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 521 states to 521 states and 528 transitions. [2019-05-23 09:36:46,472 INFO L146 ILogger]: Start accepts. Automaton has 521 states and 528 transitions. Word has length 5 [2019-05-23 09:36:46,472 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 09:36:46,472 INFO L146 ILogger]: Abstraction has 521 states and 528 transitions. [2019-05-23 09:36:46,472 INFO L146 ILogger]: Interpolant automaton has 4 states. [2019-05-23 09:36:46,473 INFO L146 ILogger]: Start isEmpty. Operand 521 states and 528 transitions. [2019-05-23 09:36:46,473 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 6 [2019-05-23 09:36:46,473 INFO L146 ILogger]: Found error trace [2019-05-23 09:36:46,474 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1] [2019-05-23 09:36:46,476 INFO L146 ILogger]: === Iteration 5 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT]=== [2019-05-23 09:36:46,477 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 09:36:46,477 INFO L146 ILogger]: Analyzing trace with hash 735323842, now seen corresponding path program 1 times [2019-05-23 09:36:46,478 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 09:36:46,481 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 09:36:46,481 INFO L146 ILogger]: Trace formula consists of 7 conjuncts, 3 conjunts are in the unsatisfiable core [2019-05-23 09:36:46,482 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 09:36:46,594 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 09:36:46,595 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 09:36:46,595 INFO L146 ILogger]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-05-23 09:36:46,595 INFO L146 ILogger]: Interpolant automaton has 4 states [2019-05-23 09:36:46,595 INFO L146 ILogger]: Constructing interpolant automaton starting with 4 interpolants. [2019-05-23 09:36:46,596 INFO L146 ILogger]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-05-23 09:36:46,596 INFO L146 ILogger]: Start difference. First operand 521 states and 528 transitions. Second operand 4 states. [2019-05-23 09:36:46,693 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 09:36:46,693 INFO L146 ILogger]: Finished difference Result 520 states and 527 transitions. [2019-05-23 09:36:46,693 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-05-23 09:36:46,694 INFO L146 ILogger]: Start accepts. Automaton has 4 states. Word has length 5 [2019-05-23 09:36:46,694 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 09:36:46,696 INFO L146 ILogger]: With dead ends: 520 [2019-05-23 09:36:46,697 INFO L146 ILogger]: Without dead ends: 515 [2019-05-23 09:36:46,697 INFO L146 ILogger]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-05-23 09:36:46,698 INFO L146 ILogger]: Start minimizeSevpa. Operand 515 states. [2019-05-23 09:36:46,705 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 515 to 515. [2019-05-23 09:36:46,705 INFO L146 ILogger]: Start removeUnreachable. Operand 515 states. [2019-05-23 09:36:46,707 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 515 states to 515 states and 523 transitions. [2019-05-23 09:36:46,707 INFO L146 ILogger]: Start accepts. Automaton has 515 states and 523 transitions. Word has length 5 [2019-05-23 09:36:46,708 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 09:36:46,708 INFO L146 ILogger]: Abstraction has 515 states and 523 transitions. [2019-05-23 09:36:46,708 INFO L146 ILogger]: Interpolant automaton has 4 states. [2019-05-23 09:36:46,708 INFO L146 ILogger]: Start isEmpty. Operand 515 states and 523 transitions. [2019-05-23 09:36:46,709 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 6 [2019-05-23 09:36:46,709 INFO L146 ILogger]: Found error trace [2019-05-23 09:36:46,709 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1] [2019-05-23 09:36:46,715 INFO L146 ILogger]: === Iteration 6 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT]=== [2019-05-23 09:36:46,715 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 09:36:46,715 INFO L146 ILogger]: Analyzing trace with hash 730552317, now seen corresponding path program 1 times [2019-05-23 09:36:46,716 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 09:36:46,722 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 09:36:46,723 INFO L146 ILogger]: Trace formula consists of 7 conjuncts, 3 conjunts are in the unsatisfiable core [2019-05-23 09:36:46,723 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 09:36:46,794 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 09:36:46,795 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 09:36:46,795 INFO L146 ILogger]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-05-23 09:36:46,795 INFO L146 ILogger]: Interpolant automaton has 4 states [2019-05-23 09:36:46,796 INFO L146 ILogger]: Constructing interpolant automaton starting with 4 interpolants. [2019-05-23 09:36:46,796 INFO L146 ILogger]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-05-23 09:36:46,796 INFO L146 ILogger]: Start difference. First operand 515 states and 523 transitions. Second operand 4 states. [2019-05-23 09:36:46,820 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 09:36:46,820 INFO L146 ILogger]: Finished difference Result 514 states and 522 transitions. [2019-05-23 09:36:46,820 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-05-23 09:36:46,821 INFO L146 ILogger]: Start accepts. Automaton has 4 states. Word has length 5 [2019-05-23 09:36:46,821 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 09:36:46,823 INFO L146 ILogger]: With dead ends: 514 [2019-05-23 09:36:46,823 INFO L146 ILogger]: Without dead ends: 509 [2019-05-23 09:36:46,824 INFO L146 ILogger]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-05-23 09:36:46,825 INFO L146 ILogger]: Start minimizeSevpa. Operand 509 states. [2019-05-23 09:36:46,832 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 509 to 509. [2019-05-23 09:36:46,832 INFO L146 ILogger]: Start removeUnreachable. Operand 509 states. [2019-05-23 09:36:46,834 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 509 states to 509 states and 518 transitions. [2019-05-23 09:36:46,834 INFO L146 ILogger]: Start accepts. Automaton has 509 states and 518 transitions. Word has length 5 [2019-05-23 09:36:46,834 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 09:36:46,834 INFO L146 ILogger]: Abstraction has 509 states and 518 transitions. [2019-05-23 09:36:46,835 INFO L146 ILogger]: Interpolant automaton has 4 states. [2019-05-23 09:36:46,835 INFO L146 ILogger]: Start isEmpty. Operand 509 states and 518 transitions. [2019-05-23 09:36:46,835 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 7 [2019-05-23 09:36:46,836 INFO L146 ILogger]: Found error trace [2019-05-23 09:36:46,836 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1, 1] [2019-05-23 09:36:46,837 INFO L146 ILogger]: === Iteration 7 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT]=== [2019-05-23 09:36:46,838 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 09:36:46,838 INFO L146 ILogger]: Analyzing trace with hash 1468151470, now seen corresponding path program 1 times [2019-05-23 09:36:46,842 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 09:36:46,845 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 09:36:46,845 WARN L146 ILogger]: Trace formula consists of 8 conjuncts, 4 conjunts are in the unsatisfiable core [2019-05-23 09:36:46,846 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 09:36:46,907 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 09:36:46,908 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 09:36:46,908 INFO L146 ILogger]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-05-23 09:36:46,908 INFO L146 ILogger]: Interpolant automaton has 5 states [2019-05-23 09:36:46,908 INFO L146 ILogger]: Constructing interpolant automaton starting with 5 interpolants. [2019-05-23 09:36:46,909 INFO L146 ILogger]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-05-23 09:36:46,909 INFO L146 ILogger]: Start difference. First operand 509 states and 518 transitions. Second operand 5 states. [2019-05-23 09:36:46,999 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 09:36:47,000 INFO L146 ILogger]: Finished difference Result 508 states and 517 transitions. [2019-05-23 09:36:47,000 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-05-23 09:36:47,000 INFO L146 ILogger]: Start accepts. Automaton has 5 states. Word has length 6 [2019-05-23 09:36:47,000 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 09:36:47,003 INFO L146 ILogger]: With dead ends: 508 [2019-05-23 09:36:47,003 INFO L146 ILogger]: Without dead ends: 508 [2019-05-23 09:36:47,004 INFO L146 ILogger]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-05-23 09:36:47,005 INFO L146 ILogger]: Start minimizeSevpa. Operand 508 states. [2019-05-23 09:36:47,011 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 508 to 508. [2019-05-23 09:36:47,011 INFO L146 ILogger]: Start removeUnreachable. Operand 508 states. [2019-05-23 09:36:47,012 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 508 states to 508 states and 517 transitions. [2019-05-23 09:36:47,013 INFO L146 ILogger]: Start accepts. Automaton has 508 states and 517 transitions. Word has length 6 [2019-05-23 09:36:47,013 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 09:36:47,013 INFO L146 ILogger]: Abstraction has 508 states and 517 transitions. [2019-05-23 09:36:47,013 INFO L146 ILogger]: Interpolant automaton has 5 states. [2019-05-23 09:36:47,013 INFO L146 ILogger]: Start isEmpty. Operand 508 states and 517 transitions. [2019-05-23 09:36:47,014 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 8 [2019-05-23 09:36:47,014 INFO L146 ILogger]: Found error trace [2019-05-23 09:36:47,014 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2019-05-23 09:36:47,016 INFO L146 ILogger]: === Iteration 8 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT]=== [2019-05-23 09:36:47,016 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 09:36:47,017 INFO L146 ILogger]: Analyzing trace with hash 437427531, now seen corresponding path program 1 times [2019-05-23 09:36:47,018 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 09:36:47,023 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 09:36:47,024 INFO L146 ILogger]: Trace formula consists of 9 conjuncts, 3 conjunts are in the unsatisfiable core [2019-05-23 09:36:47,024 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 09:36:47,045 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 09:36:47,046 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 09:36:47,046 INFO L146 ILogger]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-05-23 09:36:47,046 INFO L146 ILogger]: Interpolant automaton has 4 states [2019-05-23 09:36:47,046 INFO L146 ILogger]: Constructing interpolant automaton starting with 4 interpolants. [2019-05-23 09:36:47,047 INFO L146 ILogger]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-05-23 09:36:47,047 INFO L146 ILogger]: Start difference. First operand 508 states and 517 transitions. Second operand 4 states. [2019-05-23 09:36:47,111 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 09:36:47,111 INFO L146 ILogger]: Finished difference Result 507 states and 516 transitions. [2019-05-23 09:36:47,111 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-05-23 09:36:47,112 INFO L146 ILogger]: Start accepts. Automaton has 4 states. Word has length 7 [2019-05-23 09:36:47,112 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 09:36:47,114 INFO L146 ILogger]: With dead ends: 507 [2019-05-23 09:36:47,114 INFO L146 ILogger]: Without dead ends: 507 [2019-05-23 09:36:47,115 INFO L146 ILogger]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-05-23 09:36:47,116 INFO L146 ILogger]: Start minimizeSevpa. Operand 507 states. [2019-05-23 09:36:47,122 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 507 to 507. [2019-05-23 09:36:47,122 INFO L146 ILogger]: Start removeUnreachable. Operand 507 states. [2019-05-23 09:36:47,124 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 507 states to 507 states and 516 transitions. [2019-05-23 09:36:47,124 INFO L146 ILogger]: Start accepts. Automaton has 507 states and 516 transitions. Word has length 7 [2019-05-23 09:36:47,124 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 09:36:47,124 INFO L146 ILogger]: Abstraction has 507 states and 516 transitions. [2019-05-23 09:36:47,124 INFO L146 ILogger]: Interpolant automaton has 4 states. [2019-05-23 09:36:47,125 INFO L146 ILogger]: Start isEmpty. Operand 507 states and 516 transitions. [2019-05-23 09:36:47,125 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 8 [2019-05-23 09:36:47,125 INFO L146 ILogger]: Found error trace [2019-05-23 09:36:47,125 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2019-05-23 09:36:47,127 INFO L146 ILogger]: === Iteration 9 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT]=== [2019-05-23 09:36:47,127 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 09:36:47,128 INFO L146 ILogger]: Analyzing trace with hash 102232374, now seen corresponding path program 1 times [2019-05-23 09:36:47,129 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 09:36:47,132 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 09:36:47,132 INFO L146 ILogger]: Trace formula consists of 9 conjuncts, 4 conjunts are in the unsatisfiable core [2019-05-23 09:36:47,133 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 09:36:47,340 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 09:36:47,341 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 09:36:47,341 INFO L146 ILogger]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-05-23 09:36:47,342 INFO L146 ILogger]: Interpolant automaton has 5 states [2019-05-23 09:36:47,342 INFO L146 ILogger]: Constructing interpolant automaton starting with 5 interpolants. [2019-05-23 09:36:47,342 INFO L146 ILogger]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-05-23 09:36:47,343 INFO L146 ILogger]: Start difference. First operand 507 states and 516 transitions. Second operand 5 states. [2019-05-23 09:36:47,604 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 09:36:47,604 INFO L146 ILogger]: Finished difference Result 506 states and 515 transitions. [2019-05-23 09:36:47,605 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-05-23 09:36:47,606 INFO L146 ILogger]: Start accepts. Automaton has 5 states. Word has length 7 [2019-05-23 09:36:47,606 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 09:36:47,608 INFO L146 ILogger]: With dead ends: 506 [2019-05-23 09:36:47,609 INFO L146 ILogger]: Without dead ends: 506 [2019-05-23 09:36:47,609 INFO L146 ILogger]: 0 DeclaredPredicates, 8 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-05-23 09:36:47,610 INFO L146 ILogger]: Start minimizeSevpa. Operand 506 states. [2019-05-23 09:36:47,619 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 506 to 506. [2019-05-23 09:36:47,620 INFO L146 ILogger]: Start removeUnreachable. Operand 506 states. [2019-05-23 09:36:47,622 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 506 states to 506 states and 515 transitions. [2019-05-23 09:36:47,622 INFO L146 ILogger]: Start accepts. Automaton has 506 states and 515 transitions. Word has length 7 [2019-05-23 09:36:47,623 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 09:36:47,623 INFO L146 ILogger]: Abstraction has 506 states and 515 transitions. [2019-05-23 09:36:47,623 INFO L146 ILogger]: Interpolant automaton has 5 states. [2019-05-23 09:36:47,623 INFO L146 ILogger]: Start isEmpty. Operand 506 states and 515 transitions. [2019-05-23 09:36:47,624 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 10 [2019-05-23 09:36:47,624 INFO L146 ILogger]: Found error trace [2019-05-23 09:36:47,624 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-05-23 09:36:47,626 INFO L146 ILogger]: === Iteration 10 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT]=== [2019-05-23 09:36:47,627 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 09:36:47,627 INFO L146 ILogger]: Analyzing trace with hash -538909933, now seen corresponding path program 1 times [2019-05-23 09:36:47,628 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 09:36:47,635 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 09:36:47,637 INFO L146 ILogger]: Trace formula consists of 11 conjuncts, 4 conjunts are in the unsatisfiable core [2019-05-23 09:36:47,638 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 09:36:47,836 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 09:36:47,836 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 09:36:47,837 INFO L146 ILogger]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-05-23 09:36:47,837 INFO L146 ILogger]: Interpolant automaton has 5 states [2019-05-23 09:36:47,837 INFO L146 ILogger]: Constructing interpolant automaton starting with 5 interpolants. [2019-05-23 09:36:47,837 INFO L146 ILogger]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-05-23 09:36:47,838 INFO L146 ILogger]: Start difference. First operand 506 states and 515 transitions. Second operand 5 states. [2019-05-23 09:36:48,204 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 09:36:48,204 INFO L146 ILogger]: Finished difference Result 505 states and 514 transitions. [2019-05-23 09:36:48,208 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-05-23 09:36:48,209 INFO L146 ILogger]: Start accepts. Automaton has 5 states. Word has length 9 [2019-05-23 09:36:48,209 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 09:36:48,212 INFO L146 ILogger]: With dead ends: 505 [2019-05-23 09:36:48,212 INFO L146 ILogger]: Without dead ends: 505 [2019-05-23 09:36:48,213 INFO L146 ILogger]: 0 DeclaredPredicates, 10 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-05-23 09:36:48,215 INFO L146 ILogger]: Start minimizeSevpa. Operand 505 states. [2019-05-23 09:36:48,225 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 505 to 505. [2019-05-23 09:36:48,225 INFO L146 ILogger]: Start removeUnreachable. Operand 505 states. [2019-05-23 09:36:48,230 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 505 states to 505 states and 514 transitions. [2019-05-23 09:36:48,230 INFO L146 ILogger]: Start accepts. Automaton has 505 states and 514 transitions. Word has length 9 [2019-05-23 09:36:48,230 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 09:36:48,231 INFO L146 ILogger]: Abstraction has 505 states and 514 transitions. [2019-05-23 09:36:48,231 INFO L146 ILogger]: Interpolant automaton has 5 states. [2019-05-23 09:36:48,231 INFO L146 ILogger]: Start isEmpty. Operand 505 states and 514 transitions. [2019-05-23 09:36:48,232 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 11 [2019-05-23 09:36:48,232 INFO L146 ILogger]: Found error trace [2019-05-23 09:36:48,232 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-05-23 09:36:48,233 INFO L146 ILogger]: === Iteration 11 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT]=== [2019-05-23 09:36:48,234 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 09:36:48,235 INFO L146 ILogger]: Analyzing trace with hash -895437985, now seen corresponding path program 1 times [2019-05-23 09:36:48,236 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 09:36:48,242 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 09:36:48,244 INFO L146 ILogger]: Trace formula consists of 12 conjuncts, 5 conjunts are in the unsatisfiable core [2019-05-23 09:36:48,246 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 09:36:48,548 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 09:36:48,548 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 09:36:48,548 INFO L146 ILogger]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-05-23 09:36:48,549 INFO L146 ILogger]: Interpolant automaton has 6 states [2019-05-23 09:36:48,549 INFO L146 ILogger]: Constructing interpolant automaton starting with 6 interpolants. [2019-05-23 09:36:48,549 INFO L146 ILogger]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-05-23 09:36:48,550 INFO L146 ILogger]: Start difference. First operand 505 states and 514 transitions. Second operand 6 states. [2019-05-23 09:36:48,833 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 09:36:48,833 INFO L146 ILogger]: Finished difference Result 504 states and 513 transitions. [2019-05-23 09:36:48,833 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-05-23 09:36:48,833 INFO L146 ILogger]: Start accepts. Automaton has 6 states. Word has length 10 [2019-05-23 09:36:48,834 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 09:36:48,836 INFO L146 ILogger]: With dead ends: 504 [2019-05-23 09:36:48,836 INFO L146 ILogger]: Without dead ends: 494 [2019-05-23 09:36:48,837 INFO L146 ILogger]: 0 DeclaredPredicates, 12 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-05-23 09:36:48,838 INFO L146 ILogger]: Start minimizeSevpa. Operand 494 states. [2019-05-23 09:36:48,845 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 494 to 494. [2019-05-23 09:36:48,845 INFO L146 ILogger]: Start removeUnreachable. Operand 494 states. [2019-05-23 09:36:48,847 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 494 states to 494 states and 504 transitions. [2019-05-23 09:36:48,847 INFO L146 ILogger]: Start accepts. Automaton has 494 states and 504 transitions. Word has length 10 [2019-05-23 09:36:48,848 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 09:36:48,848 INFO L146 ILogger]: Abstraction has 494 states and 504 transitions. [2019-05-23 09:36:48,848 INFO L146 ILogger]: Interpolant automaton has 6 states. [2019-05-23 09:36:48,848 INFO L146 ILogger]: Start isEmpty. Operand 494 states and 504 transitions. [2019-05-23 09:36:48,849 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 13 [2019-05-23 09:36:48,849 INFO L146 ILogger]: Found error trace [2019-05-23 09:36:48,849 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-05-23 09:36:48,850 INFO L146 ILogger]: === Iteration 12 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT]=== [2019-05-23 09:36:48,850 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 09:36:48,850 INFO L146 ILogger]: Analyzing trace with hash -1371145850, now seen corresponding path program 1 times [2019-05-23 09:36:48,852 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 09:36:48,855 INFO L146 ILogger]: Conjunction of SSA is sat [2019-05-23 09:36:48,859 INFO L146 ILogger]: Conjunction of SSA is sat [2019-05-23 09:36:48,877 INFO L146 ILogger]: Counterexample might be feasible [2019-05-23 09:36:48,889 INFO L146 ILogger]: Did not count any witness invariants because Icfg is not BoogieIcfg [2019-05-23 09:36:48,891 INFO L146 ILogger]: Adding new model GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 23.05 09:36:48 BasicIcfg [2019-05-23 09:36:48,891 INFO L146 ILogger]: ------------------------ END TraceAbstraction---------------------------- [2019-05-23 09:36:48,895 INFO L146 ILogger]: Toolchain (without parser) took 6391.14 ms. Allocated memory was 138.4 MB in the beginning and 201.3 MB in the end (delta: 62.9 MB). Free memory was 106.7 MB in the beginning and 56.5 MB in the end (delta: 50.2 MB). Peak memory consumption was 113.1 MB. Max. memory is 7.1 GB. [2019-05-23 09:36:48,897 INFO L146 ILogger]: Boogie PL CUP Parser took 0.19 ms. Allocated memory is still 138.4 MB. Free memory was 109.4 MB in the beginning and 109.2 MB in the end (delta: 209.7 kB). Peak memory consumption was 209.7 kB. Max. memory is 7.1 GB. [2019-05-23 09:36:48,898 INFO L146 ILogger]: Boogie Procedure Inliner took 84.97 ms. Allocated memory is still 138.4 MB. Free memory was 106.7 MB in the beginning and 102.9 MB in the end (delta: 3.8 MB). Peak memory consumption was 3.8 MB. Max. memory is 7.1 GB. [2019-05-23 09:36:48,899 INFO L146 ILogger]: Boogie Preprocessor took 71.47 ms. Allocated memory is still 138.4 MB. Free memory was 102.9 MB in the beginning and 100.6 MB in the end (delta: 2.4 MB). Peak memory consumption was 2.4 MB. Max. memory is 7.1 GB. [2019-05-23 09:36:48,901 INFO L146 ILogger]: RCFGBuilder took 2254.82 ms. Allocated memory was 138.4 MB in the beginning and 178.3 MB in the end (delta: 39.8 MB). Free memory was 100.6 MB in the beginning and 103.7 MB in the end (delta: -3.1 MB). Peak memory consumption was 48.8 MB. Max. memory is 7.1 GB. [2019-05-23 09:36:48,902 INFO L146 ILogger]: IcfgTransformer took 80.20 ms. Allocated memory is still 178.3 MB. Free memory was 103.7 MB in the beginning and 98.2 MB in the end (delta: 5.5 MB). Peak memory consumption was 5.5 MB. Max. memory is 7.1 GB. [2019-05-23 09:36:48,903 INFO L146 ILogger]: TraceAbstraction took 3894.54 ms. Allocated memory was 178.3 MB in the beginning and 201.3 MB in the end (delta: 23.1 MB). Free memory was 98.2 MB in the beginning and 56.5 MB in the end (delta: 41.7 MB). Peak memory consumption was 64.8 MB. Max. memory is 7.1 GB. [2019-05-23 09:36:48,910 INFO L146 ILogger]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * Boogie PL CUP Parser took 0.19 ms. Allocated memory is still 138.4 MB. Free memory was 109.4 MB in the beginning and 109.2 MB in the end (delta: 209.7 kB). Peak memory consumption was 209.7 kB. Max. memory is 7.1 GB. * Boogie Procedure Inliner took 84.97 ms. Allocated memory is still 138.4 MB. Free memory was 106.7 MB in the beginning and 102.9 MB in the end (delta: 3.8 MB). Peak memory consumption was 3.8 MB. Max. memory is 7.1 GB. * Boogie Preprocessor took 71.47 ms. Allocated memory is still 138.4 MB. Free memory was 102.9 MB in the beginning and 100.6 MB in the end (delta: 2.4 MB). Peak memory consumption was 2.4 MB. Max. memory is 7.1 GB. * RCFGBuilder took 2254.82 ms. Allocated memory was 138.4 MB in the beginning and 178.3 MB in the end (delta: 39.8 MB). Free memory was 100.6 MB in the beginning and 103.7 MB in the end (delta: -3.1 MB). Peak memory consumption was 48.8 MB. Max. memory is 7.1 GB. * IcfgTransformer took 80.20 ms. Allocated memory is still 178.3 MB. Free memory was 103.7 MB in the beginning and 98.2 MB in the end (delta: 5.5 MB). Peak memory consumption was 5.5 MB. Max. memory is 7.1 GB. * TraceAbstraction took 3894.54 ms. Allocated memory was 178.3 MB in the beginning and 201.3 MB in the end (delta: 23.1 MB). Free memory was 98.2 MB in the beginning and 56.5 MB in the end (delta: 41.7 MB). Peak memory consumption was 64.8 MB. Max. memory is 7.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 481]: assertion can be violated assertion can be violated We found a FailurePath: [L462-L464] requires void$SimpleFrame2Cons$2$actionPerformed$4553$__this != $null; [L474] r098 := void$SimpleFrame2Cons$2$actionPerformed$4553$__this; [L476] r199 := void$SimpleFrame2Cons$2$actionPerformed$4553$param_0; [L478] $r2102 := SimpleFrame2Cons$SimpleFrame2Cons$2$this$0711; [L390] r083 := $param_0; [L392] $r185 := javax.swing.JButton$SimpleFrame2Cons$event2227; [L394] __ret := $r185; [L481] assert $r3103 != $null; - StatisticsResult: Ultimate Automizer benchmark data CFG has 16 procedures, 645 locations, 87 error locations. UNSAFE Result, 3.8s OverallTime, 12 OverallIterations, 1 TraceHistogramMax, 1.9s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 5874 SDtfs, 1503 SDslu, 12880 SDs, 0 SdLazy, 82 SolverSat, 11 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.7s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 71 GetRequests, 28 SyntacticMatches, 0 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 2.0s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=645occurred in iteration=0, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.2s AutomataMinimizationTime, 11 MinimizatonAttempts, 0 StatesRemovedByMinimization, 0 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.0s SatisfiabilityAnalysisTime, 1.2s InterpolantComputationTime, 78 NumberOfCodeBlocks, 78 NumberOfCodeBlocksAsserted, 12 NumberOfCheckSat, 55 ConstructedInterpolants, 0 QuantifiedInterpolants, 1026 SizeOfPredicates, 16 NumberOfNonLiveVariables, 88 ConjunctsInSsa, 38 ConjunctsInUnsatCore, 11 InterpolantComputations, 11 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...