java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data --rcfgbuilder.command.for.external.solver 'z3 SMTLIB2_COMPLIANT=true -memory:4096 -smt2 -in -t:12000' -tc ../../../trunk/examples/toolchains/AutomizerBplInlineTransformed.xml --icfgtransformation.transformationtype MAP_ELIMINATION_MONNIAUX --rcfgbuilder.size.of.a.code.block SingleStatement --icfgtransformation.map.elimination.monniaux.number.of.cells 2 -i ../../../trunk/examples/programs/real-life/GuiTestExampleUnsafe.bpl -------------------------------------------------------------------------------- This is Ultimate 0.1.24-7aa59a0 [2019-05-23 10:02:40,603 INFO L146 ILogger]: Resetting all preferences to default values... [2019-05-23 10:02:40,607 INFO L146 ILogger]: Resetting UltimateCore preferences to default values [2019-05-23 10:02:40,622 INFO L146 ILogger]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-05-23 10:02:40,622 INFO L146 ILogger]: Resetting Boogie Preprocessor preferences to default values [2019-05-23 10:02:40,624 INFO L146 ILogger]: Resetting Boogie Procedure Inliner preferences to default values [2019-05-23 10:02:40,626 INFO L146 ILogger]: Resetting Abstract Interpretation preferences to default values [2019-05-23 10:02:40,630 INFO L146 ILogger]: Resetting LassoRanker preferences to default values [2019-05-23 10:02:40,632 INFO L146 ILogger]: Resetting Reaching Definitions preferences to default values [2019-05-23 10:02:40,635 INFO L146 ILogger]: Resetting SyntaxChecker preferences to default values [2019-05-23 10:02:40,636 INFO L146 ILogger]: Büchi Program Product provides no preferences, ignoring... [2019-05-23 10:02:40,636 INFO L146 ILogger]: Resetting LTL2Aut preferences to default values [2019-05-23 10:02:40,637 INFO L146 ILogger]: Resetting PEA to Boogie preferences to default values [2019-05-23 10:02:40,640 INFO L146 ILogger]: Resetting BlockEncodingV2 preferences to default values [2019-05-23 10:02:40,641 INFO L146 ILogger]: Resetting ChcToBoogie preferences to default values [2019-05-23 10:02:40,642 INFO L146 ILogger]: Resetting AutomataScriptInterpreter preferences to default values [2019-05-23 10:02:40,649 INFO L146 ILogger]: Resetting BuchiAutomizer preferences to default values [2019-05-23 10:02:40,652 INFO L146 ILogger]: Resetting CACSL2BoogieTranslator preferences to default values [2019-05-23 10:02:40,656 INFO L146 ILogger]: Resetting CodeCheck preferences to default values [2019-05-23 10:02:40,660 INFO L146 ILogger]: Resetting InvariantSynthesis preferences to default values [2019-05-23 10:02:40,661 INFO L146 ILogger]: Resetting RCFGBuilder preferences to default values [2019-05-23 10:02:40,662 INFO L146 ILogger]: Resetting TraceAbstraction preferences to default values [2019-05-23 10:02:40,666 INFO L146 ILogger]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-05-23 10:02:40,667 INFO L146 ILogger]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-05-23 10:02:40,667 INFO L146 ILogger]: Resetting TreeAutomizer preferences to default values [2019-05-23 10:02:40,668 INFO L146 ILogger]: Resetting IcfgToChc preferences to default values [2019-05-23 10:02:40,668 INFO L146 ILogger]: Resetting IcfgTransformer preferences to default values [2019-05-23 10:02:40,670 INFO L146 ILogger]: ReqToTest provides no preferences, ignoring... [2019-05-23 10:02:40,670 INFO L146 ILogger]: Resetting Boogie Printer preferences to default values [2019-05-23 10:02:40,671 INFO L146 ILogger]: Resetting ChcSmtPrinter preferences to default values [2019-05-23 10:02:40,671 INFO L146 ILogger]: Resetting ReqPrinter preferences to default values [2019-05-23 10:02:40,674 INFO L146 ILogger]: Resetting Witness Printer preferences to default values [2019-05-23 10:02:40,675 INFO L146 ILogger]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-05-23 10:02:40,675 INFO L146 ILogger]: Resetting CDTParser preferences to default values [2019-05-23 10:02:40,676 INFO L146 ILogger]: AutomataScriptParser provides no preferences, ignoring... [2019-05-23 10:02:40,676 INFO L146 ILogger]: ReqParser provides no preferences, ignoring... [2019-05-23 10:02:40,677 INFO L146 ILogger]: Resetting SmtParser preferences to default values [2019-05-23 10:02:40,678 INFO L146 ILogger]: Resetting Witness Parser preferences to default values [2019-05-23 10:02:40,679 INFO L146 ILogger]: Finished resetting all preferences to default values... Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder: Command for external solver -> z3 SMTLIB2_COMPLIANT=true -memory:4096 -smt2 -in -t:12000 Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation: TransformationType -> MAP_ELIMINATION_MONNIAUX Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder: Size of a code block -> SingleStatement Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation: Map elimination Monniaux: number of cells -> 2 [2019-05-23 10:02:40,739 INFO L146 ILogger]: Repository-Root is: /tmp [2019-05-23 10:02:40,761 INFO L146 ILogger]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-05-23 10:02:40,764 INFO L146 ILogger]: [Toolchain 1]: Toolchain selected. [2019-05-23 10:02:40,766 INFO L146 ILogger]: Initializing Boogie PL CUP Parser... [2019-05-23 10:02:40,767 INFO L146 ILogger]: Boogie PL CUP Parser initialized [2019-05-23 10:02:40,767 INFO L146 ILogger]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/programs/real-life/GuiTestExampleUnsafe.bpl [2019-05-23 10:02:40,768 INFO L146 ILogger]: Parsing: '/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/programs/real-life/GuiTestExampleUnsafe.bpl' [2019-05-23 10:02:40,839 INFO L146 ILogger]: ####################### [Toolchain 1] ####################### [2019-05-23 10:02:40,841 INFO L146 ILogger]: Walking toolchain with 5 elements. [2019-05-23 10:02:40,842 INFO L146 ILogger]: ------------------------Boogie Procedure Inliner---------------------------- [2019-05-23 10:02:40,842 INFO L146 ILogger]: Initializing Boogie Procedure Inliner... [2019-05-23 10:02:40,842 INFO L146 ILogger]: Boogie Procedure Inliner initialized [2019-05-23 10:02:40,859 INFO L146 ILogger]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 10:02:40" (1/1) ... [2019-05-23 10:02:40,876 INFO L146 ILogger]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 10:02:40" (1/1) ... [2019-05-23 10:02:40,885 WARN L146 ILogger]: Program contained no entry procedure! [2019-05-23 10:02:40,885 WARN L146 ILogger]: Missing entry procedures: [ULTIMATE.start] [2019-05-23 10:02:40,885 WARN L146 ILogger]: Fallback enabled. All procedures will be processed. [2019-05-23 10:02:40,944 INFO L146 ILogger]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-05-23 10:02:40,951 INFO L146 ILogger]: ------------------------Boogie Preprocessor---------------------------- [2019-05-23 10:02:40,951 INFO L146 ILogger]: Initializing Boogie Preprocessor... [2019-05-23 10:02:40,951 INFO L146 ILogger]: Boogie Preprocessor initialized [2019-05-23 10:02:40,962 INFO L146 ILogger]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 10:02:40" (1/1) ... [2019-05-23 10:02:40,962 INFO L146 ILogger]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 10:02:40" (1/1) ... [2019-05-23 10:02:40,986 INFO L146 ILogger]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 10:02:40" (1/1) ... [2019-05-23 10:02:40,986 INFO L146 ILogger]: Executing the observer StructExpander from plugin Boogie Preprocessor for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 10:02:40" (1/1) ... [2019-05-23 10:02:40,998 INFO L146 ILogger]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 10:02:40" (1/1) ... [2019-05-23 10:02:41,004 INFO L146 ILogger]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 10:02:40" (1/1) ... [2019-05-23 10:02:41,011 INFO L146 ILogger]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 10:02:40" (1/1) ... [2019-05-23 10:02:41,026 INFO L146 ILogger]: ------------------------ END Boogie Preprocessor---------------------------- [2019-05-23 10:02:41,026 INFO L146 ILogger]: ------------------------RCFGBuilder---------------------------- [2019-05-23 10:02:41,027 INFO L146 ILogger]: Initializing RCFGBuilder... [2019-05-23 10:02:41,027 INFO L146 ILogger]: RCFGBuilder initialized [2019-05-23 10:02:41,031 INFO L146 ILogger]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 10:02:40" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:4096 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:4096 -smt2 -in -t:12000 [2019-05-23 10:02:41,108 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$3$$la$init$ra$$4885 given in one single declaration [2019-05-23 10:02:41,108 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$3$$la$init$ra$$4885 [2019-05-23 10:02:41,108 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$3$$la$init$ra$$4885 [2019-05-23 10:02:41,109 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$2$actionPerformed$4553 given in one single declaration [2019-05-23 10:02:41,109 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$2$actionPerformed$4553 [2019-05-23 10:02:41,109 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$2$actionPerformed$4553 [2019-05-23 10:02:41,109 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$3$actionPerformed$4886 given in one single declaration [2019-05-23 10:02:41,110 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$3$actionPerformed$4886 [2019-05-23 10:02:41,110 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$3$actionPerformed$4886 [2019-05-23 10:02:41,110 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$$la$init$ra$$1805 given in one single declaration [2019-05-23 10:02:41,110 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$$la$init$ra$$1805 [2019-05-23 10:02:41,110 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$$la$init$ra$$1805 [2019-05-23 10:02:41,111 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$1$$la$init$ra$$1802 given in one single declaration [2019-05-23 10:02:41,112 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$1$$la$init$ra$$1802 [2019-05-23 10:02:41,112 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$1$$la$init$ra$$1802 [2019-05-23 10:02:41,112 INFO L146 ILogger]: Found specification of procedure void$javax.swing.SwingUtilities$invokeLater$4940 [2019-05-23 10:02:41,112 INFO L146 ILogger]: Found specification of procedure void$javax.swing.JFrame$setLayout$1827 [2019-05-23 10:02:41,112 INFO L146 ILogger]: Specification and implementation of procedure javax.swing.JButton$SimpleFrame2Cons$access$0$1806 given in one single declaration [2019-05-23 10:02:41,113 INFO L146 ILogger]: Found specification of procedure javax.swing.JButton$SimpleFrame2Cons$access$0$1806 [2019-05-23 10:02:41,113 INFO L146 ILogger]: Found implementation of procedure javax.swing.JButton$SimpleFrame2Cons$access$0$1806 [2019-05-23 10:02:41,114 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$2$$la$init$ra$$4552 given in one single declaration [2019-05-23 10:02:41,114 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$2$$la$init$ra$$4552 [2019-05-23 10:02:41,114 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$2$$la$init$ra$$4552 [2019-05-23 10:02:41,114 INFO L146 ILogger]: Found specification of procedure void$java.awt.Frame$setResizable$1858 [2019-05-23 10:02:41,114 INFO L146 ILogger]: Specification and implementation of procedure java.awt.Dimension$java.awt.Toolkit$getScreenSize$3246 given in one single declaration [2019-05-23 10:02:41,115 INFO L146 ILogger]: Found specification of procedure java.awt.Dimension$java.awt.Toolkit$getScreenSize$3246 [2019-05-23 10:02:41,115 INFO L146 ILogger]: Found implementation of procedure java.awt.Dimension$java.awt.Toolkit$getScreenSize$3246 [2019-05-23 10:02:41,115 INFO L146 ILogger]: Specification and implementation of procedure void$javax.swing.JFrame$$la$init$ra$$1809 given in one single declaration [2019-05-23 10:02:41,115 INFO L146 ILogger]: Found specification of procedure void$javax.swing.JFrame$$la$init$ra$$1809 [2019-05-23 10:02:41,115 INFO L146 ILogger]: Found implementation of procedure void$javax.swing.JFrame$$la$init$ra$$1809 [2019-05-23 10:02:41,116 INFO L146 ILogger]: Specification and implementation of procedure int$SimpleFrame2Cons$access$2$1808 given in one single declaration [2019-05-23 10:02:41,117 INFO L146 ILogger]: Found specification of procedure int$SimpleFrame2Cons$access$2$1808 [2019-05-23 10:02:41,117 INFO L146 ILogger]: Found implementation of procedure int$SimpleFrame2Cons$access$2$1808 [2019-05-23 10:02:41,117 INFO L146 ILogger]: Found specification of procedure void$javax.swing.JFrame$setDefaultCloseOperation$1816 [2019-05-23 10:02:41,117 INFO L146 ILogger]: Found specification of procedure void$javax.swing.AbstractButton$addActionListener$4123 [2019-05-23 10:02:41,117 INFO L146 ILogger]: Found specification of procedure void$java.awt.Window$setLocation$1913 [2019-05-23 10:02:41,119 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$4$$la$init$ra$$4887 given in one single declaration [2019-05-23 10:02:41,120 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$4$$la$init$ra$$4887 [2019-05-23 10:02:41,120 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$4$$la$init$ra$$4887 [2019-05-23 10:02:41,120 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$4$actionPerformed$4888 given in one single declaration [2019-05-23 10:02:41,120 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$4$actionPerformed$4888 [2019-05-23 10:02:41,120 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$4$actionPerformed$4888 [2019-05-23 10:02:41,120 INFO L146 ILogger]: Found specification of procedure void$javax.swing.AbstractButton$setEnabled$4131 [2019-05-23 10:02:41,124 INFO L146 ILogger]: Found specification of procedure void$java.awt.Window$setVisible$1918 [2019-05-23 10:02:41,124 INFO L146 ILogger]: Found specification of procedure int$java.awt.Component$getHeight$2305 [2019-05-23 10:02:41,124 INFO L146 ILogger]: Found specification of procedure void$java.awt.Window$pack$1909 [2019-05-23 10:02:41,124 INFO L146 ILogger]: Found specification of procedure java.awt.Toolkit$java.awt.Toolkit$getDefaultToolkit$3255 [2019-05-23 10:02:41,124 INFO L146 ILogger]: Found specification of procedure int$java.awt.Component$getWidth$2304 [2019-05-23 10:02:41,125 INFO L146 ILogger]: Found specification of procedure void$java.awt.Frame$setTitle$1852 [2019-05-23 10:02:41,125 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$access$1$1807 given in one single declaration [2019-05-23 10:02:41,125 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$access$1$1807 [2019-05-23 10:02:41,125 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$access$1$1807 [2019-05-23 10:02:41,125 INFO L146 ILogger]: Found specification of procedure void$java.awt.FlowLayout$$la$init$ra$$4889 [2019-05-23 10:02:41,126 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$1$run$1803 given in one single declaration [2019-05-23 10:02:41,126 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$1$run$1803 [2019-05-23 10:02:41,126 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$1$run$1803 [2019-05-23 10:02:41,126 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$main$1804 given in one single declaration [2019-05-23 10:02:41,126 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$main$1804 [2019-05-23 10:02:41,127 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$main$1804 [2019-05-23 10:02:41,127 INFO L146 ILogger]: Found specification of procedure void$javax.swing.JButton$$la$init$ra$$2558 [2019-05-23 10:02:41,127 INFO L146 ILogger]: Specification and implementation of procedure $EFG_Procedure given in one single declaration [2019-05-23 10:02:41,127 INFO L146 ILogger]: Found specification of procedure $EFG_Procedure [2019-05-23 10:02:41,127 INFO L146 ILogger]: Found implementation of procedure $EFG_Procedure [2019-05-23 10:02:41,127 INFO L146 ILogger]: Found specification of procedure java.awt.Component$java.awt.Container$add$2075 [2019-05-23 10:02:41,128 INFO L146 ILogger]: Found specification of procedure void$java.lang.Object$$la$init$ra$$38 [2019-05-23 10:02:41,487 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 10:02:41,624 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 10:02:41,834 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 10:02:41,889 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 10:02:42,363 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 10:02:42,371 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 10:02:42,382 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 10:02:42,388 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 10:02:42,412 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 10:02:42,419 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 10:02:42,454 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 10:02:43,242 INFO L146 ILogger]: Using library mode [2019-05-23 10:02:43,243 INFO L146 ILogger]: Removed 44 assume(true) statements. [2019-05-23 10:02:43,245 INFO L146 ILogger]: Adding new model GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.05 10:02:43 BoogieIcfgContainer [2019-05-23 10:02:43,245 INFO L146 ILogger]: ------------------------ END RCFGBuilder---------------------------- [2019-05-23 10:02:43,245 INFO L146 ILogger]: ------------------------IcfgTransformer---------------------------- [2019-05-23 10:02:43,246 INFO L146 ILogger]: Initializing IcfgTransformer... [2019-05-23 10:02:43,247 INFO L146 ILogger]: IcfgTransformer initialized [2019-05-23 10:02:43,250 INFO L146 ILogger]: Executing the observer IcfgTransformationObserver from plugin IcfgTransformer for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.05 10:02:43" (1/1) ... [2019-05-23 10:02:43,330 INFO L146 ILogger]: Adding new model GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 23.05 10:02:43 BasicIcfg [2019-05-23 10:02:43,331 INFO L146 ILogger]: ------------------------ END IcfgTransformer---------------------------- [2019-05-23 10:02:43,332 INFO L146 ILogger]: ------------------------TraceAbstraction---------------------------- [2019-05-23 10:02:43,332 INFO L146 ILogger]: Initializing TraceAbstraction... [2019-05-23 10:02:43,335 INFO L146 ILogger]: TraceAbstraction initialized [2019-05-23 10:02:43,336 INFO L146 ILogger]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 10:02:40" (1/3) ... [2019-05-23 10:02:43,337 INFO L146 ILogger]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7038dd27 and model type GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.05 10:02:43, skipping insertion in model container [2019-05-23 10:02:43,337 INFO L146 ILogger]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.05 10:02:43" (2/3) ... [2019-05-23 10:02:43,337 INFO L146 ILogger]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7038dd27 and model type GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 23.05 10:02:43, skipping insertion in model container [2019-05-23 10:02:43,337 INFO L146 ILogger]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 23.05 10:02:43" (3/3) ... [2019-05-23 10:02:43,339 INFO L146 ILogger]: Analyzing ICFG GuiTestExampleUnsafe.bplME [2019-05-23 10:02:43,346 INFO L146 ILogger]: Automizer settings: Hoare:false NWA Interpolation:ForwardPredicates Determinization: PREDICATE_ABSTRACTION [2019-05-23 10:02:43,354 INFO L146 ILogger]: Appying trace abstraction to program that has 87 error locations. [2019-05-23 10:02:43,368 INFO L146 ILogger]: Starting to check reachability of 87 error locations. [2019-05-23 10:02:43,389 INFO L146 ILogger]: Using default assertion order modulation [2019-05-23 10:02:43,390 INFO L146 ILogger]: Interprodecural is true [2019-05-23 10:02:43,390 INFO L146 ILogger]: Hoare is false [2019-05-23 10:02:43,390 INFO L146 ILogger]: Compute interpolants for ForwardPredicates [2019-05-23 10:02:43,390 INFO L146 ILogger]: Backedges is STRAIGHT_LINE [2019-05-23 10:02:43,390 INFO L146 ILogger]: Determinization is PREDICATE_ABSTRACTION [2019-05-23 10:02:43,390 INFO L146 ILogger]: Difference is false [2019-05-23 10:02:43,390 INFO L146 ILogger]: Minimize is MINIMIZE_SEVPA [2019-05-23 10:02:43,391 INFO L146 ILogger]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-05-23 10:02:43,435 INFO L146 ILogger]: Start isEmpty. Operand 645 states. [2019-05-23 10:02:43,449 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 4 [2019-05-23 10:02:43,450 INFO L146 ILogger]: Found error trace [2019-05-23 10:02:43,451 INFO L146 ILogger]: trace histogram [1, 1, 1] [2019-05-23 10:02:43,459 INFO L146 ILogger]: === Iteration 1 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT]=== [2019-05-23 10:02:43,464 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 10:02:43,465 INFO L146 ILogger]: Analyzing trace with hash 767125, now seen corresponding path program 1 times [2019-05-23 10:02:43,518 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 10:02:43,541 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 10:02:43,545 WARN L146 ILogger]: Trace formula consists of 5 conjuncts, 3 conjunts are in the unsatisfiable core [2019-05-23 10:02:43,550 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 10:02:43,636 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 10:02:43,639 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 10:02:43,640 INFO L146 ILogger]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-05-23 10:02:43,644 INFO L146 ILogger]: Interpolant automaton has 4 states [2019-05-23 10:02:43,660 INFO L146 ILogger]: Constructing interpolant automaton starting with 4 interpolants. [2019-05-23 10:02:43,661 INFO L146 ILogger]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-05-23 10:02:43,664 INFO L146 ILogger]: Start difference. First operand 645 states. Second operand 4 states. [2019-05-23 10:02:43,827 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 10:02:43,827 INFO L146 ILogger]: Finished difference Result 640 states and 642 transitions. [2019-05-23 10:02:43,828 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-05-23 10:02:43,830 INFO L146 ILogger]: Start accepts. Automaton has 4 states. Word has length 3 [2019-05-23 10:02:43,830 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 10:02:43,860 INFO L146 ILogger]: With dead ends: 640 [2019-05-23 10:02:43,861 INFO L146 ILogger]: Without dead ends: 558 [2019-05-23 10:02:43,863 INFO L146 ILogger]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-05-23 10:02:43,881 INFO L146 ILogger]: Start minimizeSevpa. Operand 558 states. [2019-05-23 10:02:43,931 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 558 to 558. [2019-05-23 10:02:43,933 INFO L146 ILogger]: Start removeUnreachable. Operand 558 states. [2019-05-23 10:02:43,938 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 558 states to 558 states and 564 transitions. [2019-05-23 10:02:43,939 INFO L146 ILogger]: Start accepts. Automaton has 558 states and 564 transitions. Word has length 3 [2019-05-23 10:02:43,940 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 10:02:43,940 INFO L146 ILogger]: Abstraction has 558 states and 564 transitions. [2019-05-23 10:02:43,940 INFO L146 ILogger]: Interpolant automaton has 4 states. [2019-05-23 10:02:43,940 INFO L146 ILogger]: Start isEmpty. Operand 558 states and 564 transitions. [2019-05-23 10:02:43,941 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 5 [2019-05-23 10:02:43,941 INFO L146 ILogger]: Found error trace [2019-05-23 10:02:43,941 INFO L146 ILogger]: trace histogram [1, 1, 1, 1] [2019-05-23 10:02:43,944 INFO L146 ILogger]: === Iteration 2 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT]=== [2019-05-23 10:02:43,945 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 10:02:43,945 INFO L146 ILogger]: Analyzing trace with hash 23874049, now seen corresponding path program 1 times [2019-05-23 10:02:43,946 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 10:02:43,949 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 10:02:43,949 WARN L146 ILogger]: Trace formula consists of 6 conjuncts, 3 conjunts are in the unsatisfiable core [2019-05-23 10:02:43,950 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 10:02:43,975 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 10:02:43,976 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 10:02:43,976 INFO L146 ILogger]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-05-23 10:02:43,978 INFO L146 ILogger]: Interpolant automaton has 4 states [2019-05-23 10:02:43,978 INFO L146 ILogger]: Constructing interpolant automaton starting with 4 interpolants. [2019-05-23 10:02:43,979 INFO L146 ILogger]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-05-23 10:02:43,979 INFO L146 ILogger]: Start difference. First operand 558 states and 564 transitions. Second operand 4 states. [2019-05-23 10:02:44,033 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 10:02:44,033 INFO L146 ILogger]: Finished difference Result 557 states and 563 transitions. [2019-05-23 10:02:44,035 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-05-23 10:02:44,035 INFO L146 ILogger]: Start accepts. Automaton has 4 states. Word has length 4 [2019-05-23 10:02:44,035 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 10:02:44,042 INFO L146 ILogger]: With dead ends: 557 [2019-05-23 10:02:44,043 INFO L146 ILogger]: Without dead ends: 557 [2019-05-23 10:02:44,046 INFO L146 ILogger]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-05-23 10:02:44,048 INFO L146 ILogger]: Start minimizeSevpa. Operand 557 states. [2019-05-23 10:02:44,085 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 557 to 557. [2019-05-23 10:02:44,086 INFO L146 ILogger]: Start removeUnreachable. Operand 557 states. [2019-05-23 10:02:44,089 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 557 states to 557 states and 563 transitions. [2019-05-23 10:02:44,089 INFO L146 ILogger]: Start accepts. Automaton has 557 states and 563 transitions. Word has length 4 [2019-05-23 10:02:44,089 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 10:02:44,090 INFO L146 ILogger]: Abstraction has 557 states and 563 transitions. [2019-05-23 10:02:44,090 INFO L146 ILogger]: Interpolant automaton has 4 states. [2019-05-23 10:02:44,090 INFO L146 ILogger]: Start isEmpty. Operand 557 states and 563 transitions. [2019-05-23 10:02:44,091 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 6 [2019-05-23 10:02:44,091 INFO L146 ILogger]: Found error trace [2019-05-23 10:02:44,091 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1] [2019-05-23 10:02:44,094 INFO L146 ILogger]: === Iteration 3 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT]=== [2019-05-23 10:02:44,095 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 10:02:44,095 INFO L146 ILogger]: Analyzing trace with hash 741050664, now seen corresponding path program 1 times [2019-05-23 10:02:44,097 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 10:02:44,100 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 10:02:44,100 INFO L146 ILogger]: Trace formula consists of 7 conjuncts, 3 conjunts are in the unsatisfiable core [2019-05-23 10:02:44,101 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 10:02:44,228 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 10:02:44,228 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 10:02:44,229 INFO L146 ILogger]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-05-23 10:02:44,229 INFO L146 ILogger]: Interpolant automaton has 4 states [2019-05-23 10:02:44,230 INFO L146 ILogger]: Constructing interpolant automaton starting with 4 interpolants. [2019-05-23 10:02:44,230 INFO L146 ILogger]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-05-23 10:02:44,230 INFO L146 ILogger]: Start difference. First operand 557 states and 563 transitions. Second operand 4 states. [2019-05-23 10:02:44,321 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 10:02:44,322 INFO L146 ILogger]: Finished difference Result 556 states and 562 transitions. [2019-05-23 10:02:44,322 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-05-23 10:02:44,322 INFO L146 ILogger]: Start accepts. Automaton has 4 states. Word has length 5 [2019-05-23 10:02:44,322 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 10:02:44,325 INFO L146 ILogger]: With dead ends: 556 [2019-05-23 10:02:44,325 INFO L146 ILogger]: Without dead ends: 551 [2019-05-23 10:02:44,327 INFO L146 ILogger]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-05-23 10:02:44,328 INFO L146 ILogger]: Start minimizeSevpa. Operand 551 states. [2019-05-23 10:02:44,336 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 551 to 551. [2019-05-23 10:02:44,337 INFO L146 ILogger]: Start removeUnreachable. Operand 551 states. [2019-05-23 10:02:44,338 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 551 states to 551 states and 558 transitions. [2019-05-23 10:02:44,339 INFO L146 ILogger]: Start accepts. Automaton has 551 states and 558 transitions. Word has length 5 [2019-05-23 10:02:44,339 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 10:02:44,339 INFO L146 ILogger]: Abstraction has 551 states and 558 transitions. [2019-05-23 10:02:44,339 INFO L146 ILogger]: Interpolant automaton has 4 states. [2019-05-23 10:02:44,339 INFO L146 ILogger]: Start isEmpty. Operand 551 states and 558 transitions. [2019-05-23 10:02:44,340 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 6 [2019-05-23 10:02:44,340 INFO L146 ILogger]: Found error trace [2019-05-23 10:02:44,340 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1] [2019-05-23 10:02:44,344 INFO L146 ILogger]: === Iteration 4 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT]=== [2019-05-23 10:02:44,344 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 10:02:44,345 INFO L146 ILogger]: Analyzing trace with hash 735323842, now seen corresponding path program 1 times [2019-05-23 10:02:44,346 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 10:02:44,349 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 10:02:44,349 INFO L146 ILogger]: Trace formula consists of 7 conjuncts, 3 conjunts are in the unsatisfiable core [2019-05-23 10:02:44,350 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 10:02:44,385 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 10:02:44,385 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 10:02:44,385 INFO L146 ILogger]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-05-23 10:02:44,386 INFO L146 ILogger]: Interpolant automaton has 4 states [2019-05-23 10:02:44,386 INFO L146 ILogger]: Constructing interpolant automaton starting with 4 interpolants. [2019-05-23 10:02:44,386 INFO L146 ILogger]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-05-23 10:02:44,386 INFO L146 ILogger]: Start difference. First operand 551 states and 558 transitions. Second operand 4 states. [2019-05-23 10:02:44,453 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 10:02:44,454 INFO L146 ILogger]: Finished difference Result 550 states and 557 transitions. [2019-05-23 10:02:44,454 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-05-23 10:02:44,454 INFO L146 ILogger]: Start accepts. Automaton has 4 states. Word has length 5 [2019-05-23 10:02:44,454 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 10:02:44,457 INFO L146 ILogger]: With dead ends: 550 [2019-05-23 10:02:44,457 INFO L146 ILogger]: Without dead ends: 545 [2019-05-23 10:02:44,458 INFO L146 ILogger]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-05-23 10:02:44,459 INFO L146 ILogger]: Start minimizeSevpa. Operand 545 states. [2019-05-23 10:02:44,467 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 545 to 545. [2019-05-23 10:02:44,467 INFO L146 ILogger]: Start removeUnreachable. Operand 545 states. [2019-05-23 10:02:44,469 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 545 states to 545 states and 553 transitions. [2019-05-23 10:02:44,469 INFO L146 ILogger]: Start accepts. Automaton has 545 states and 553 transitions. Word has length 5 [2019-05-23 10:02:44,469 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 10:02:44,469 INFO L146 ILogger]: Abstraction has 545 states and 553 transitions. [2019-05-23 10:02:44,470 INFO L146 ILogger]: Interpolant automaton has 4 states. [2019-05-23 10:02:44,470 INFO L146 ILogger]: Start isEmpty. Operand 545 states and 553 transitions. [2019-05-23 10:02:44,470 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 6 [2019-05-23 10:02:44,470 INFO L146 ILogger]: Found error trace [2019-05-23 10:02:44,471 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1] [2019-05-23 10:02:44,473 INFO L146 ILogger]: === Iteration 5 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT]=== [2019-05-23 10:02:44,473 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 10:02:44,473 INFO L146 ILogger]: Analyzing trace with hash 730552317, now seen corresponding path program 1 times [2019-05-23 10:02:44,475 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 10:02:44,477 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 10:02:44,478 INFO L146 ILogger]: Trace formula consists of 7 conjuncts, 3 conjunts are in the unsatisfiable core [2019-05-23 10:02:44,479 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 10:02:44,532 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 10:02:44,532 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 10:02:44,532 INFO L146 ILogger]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-05-23 10:02:44,533 INFO L146 ILogger]: Interpolant automaton has 4 states [2019-05-23 10:02:44,533 INFO L146 ILogger]: Constructing interpolant automaton starting with 4 interpolants. [2019-05-23 10:02:44,533 INFO L146 ILogger]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-05-23 10:02:44,533 INFO L146 ILogger]: Start difference. First operand 545 states and 553 transitions. Second operand 4 states. [2019-05-23 10:02:44,563 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 10:02:44,563 INFO L146 ILogger]: Finished difference Result 544 states and 552 transitions. [2019-05-23 10:02:44,563 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-05-23 10:02:44,563 INFO L146 ILogger]: Start accepts. Automaton has 4 states. Word has length 5 [2019-05-23 10:02:44,564 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 10:02:44,567 INFO L146 ILogger]: With dead ends: 544 [2019-05-23 10:02:44,567 INFO L146 ILogger]: Without dead ends: 539 [2019-05-23 10:02:44,568 INFO L146 ILogger]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-05-23 10:02:44,569 INFO L146 ILogger]: Start minimizeSevpa. Operand 539 states. [2019-05-23 10:02:44,576 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 539 to 539. [2019-05-23 10:02:44,576 INFO L146 ILogger]: Start removeUnreachable. Operand 539 states. [2019-05-23 10:02:44,578 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 539 states to 539 states and 548 transitions. [2019-05-23 10:02:44,578 INFO L146 ILogger]: Start accepts. Automaton has 539 states and 548 transitions. Word has length 5 [2019-05-23 10:02:44,578 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 10:02:44,579 INFO L146 ILogger]: Abstraction has 539 states and 548 transitions. [2019-05-23 10:02:44,579 INFO L146 ILogger]: Interpolant automaton has 4 states. [2019-05-23 10:02:44,579 INFO L146 ILogger]: Start isEmpty. Operand 539 states and 548 transitions. [2019-05-23 10:02:44,580 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 6 [2019-05-23 10:02:44,580 INFO L146 ILogger]: Found error trace [2019-05-23 10:02:44,580 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1] [2019-05-23 10:02:44,583 INFO L146 ILogger]: === Iteration 6 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT]=== [2019-05-23 10:02:44,583 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 10:02:44,583 INFO L146 ILogger]: Analyzing trace with hash 742004970, now seen corresponding path program 1 times [2019-05-23 10:02:44,585 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 10:02:44,590 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 10:02:44,591 INFO L146 ILogger]: Trace formula consists of 7 conjuncts, 3 conjunts are in the unsatisfiable core [2019-05-23 10:02:44,591 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 10:02:44,636 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 10:02:44,636 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 10:02:44,636 INFO L146 ILogger]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-05-23 10:02:44,637 INFO L146 ILogger]: Interpolant automaton has 4 states [2019-05-23 10:02:44,637 INFO L146 ILogger]: Constructing interpolant automaton starting with 4 interpolants. [2019-05-23 10:02:44,637 INFO L146 ILogger]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-05-23 10:02:44,637 INFO L146 ILogger]: Start difference. First operand 539 states and 548 transitions. Second operand 4 states. [2019-05-23 10:02:44,853 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 10:02:44,853 INFO L146 ILogger]: Finished difference Result 527 states and 536 transitions. [2019-05-23 10:02:44,854 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-05-23 10:02:44,854 INFO L146 ILogger]: Start accepts. Automaton has 4 states. Word has length 5 [2019-05-23 10:02:44,854 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 10:02:44,857 INFO L146 ILogger]: With dead ends: 527 [2019-05-23 10:02:44,857 INFO L146 ILogger]: Without dead ends: 509 [2019-05-23 10:02:44,858 INFO L146 ILogger]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-05-23 10:02:44,859 INFO L146 ILogger]: Start minimizeSevpa. Operand 509 states. [2019-05-23 10:02:44,866 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 509 to 509. [2019-05-23 10:02:44,867 INFO L146 ILogger]: Start removeUnreachable. Operand 509 states. [2019-05-23 10:02:44,868 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 509 states to 509 states and 518 transitions. [2019-05-23 10:02:44,869 INFO L146 ILogger]: Start accepts. Automaton has 509 states and 518 transitions. Word has length 5 [2019-05-23 10:02:44,869 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 10:02:44,869 INFO L146 ILogger]: Abstraction has 509 states and 518 transitions. [2019-05-23 10:02:44,869 INFO L146 ILogger]: Interpolant automaton has 4 states. [2019-05-23 10:02:44,869 INFO L146 ILogger]: Start isEmpty. Operand 509 states and 518 transitions. [2019-05-23 10:02:44,870 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 7 [2019-05-23 10:02:44,870 INFO L146 ILogger]: Found error trace [2019-05-23 10:02:44,870 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1, 1] [2019-05-23 10:02:44,872 INFO L146 ILogger]: === Iteration 7 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT]=== [2019-05-23 10:02:44,872 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 10:02:44,873 INFO L146 ILogger]: Analyzing trace with hash 1468151470, now seen corresponding path program 1 times [2019-05-23 10:02:44,874 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 10:02:44,877 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 10:02:44,877 WARN L146 ILogger]: Trace formula consists of 8 conjuncts, 4 conjunts are in the unsatisfiable core [2019-05-23 10:02:44,878 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 10:02:45,023 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 10:02:45,023 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 10:02:45,023 INFO L146 ILogger]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-05-23 10:02:45,024 INFO L146 ILogger]: Interpolant automaton has 5 states [2019-05-23 10:02:45,024 INFO L146 ILogger]: Constructing interpolant automaton starting with 5 interpolants. [2019-05-23 10:02:45,024 INFO L146 ILogger]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-05-23 10:02:45,024 INFO L146 ILogger]: Start difference. First operand 509 states and 518 transitions. Second operand 5 states. [2019-05-23 10:02:45,260 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 10:02:45,261 INFO L146 ILogger]: Finished difference Result 508 states and 517 transitions. [2019-05-23 10:02:45,261 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-05-23 10:02:45,261 INFO L146 ILogger]: Start accepts. Automaton has 5 states. Word has length 6 [2019-05-23 10:02:45,262 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 10:02:45,265 INFO L146 ILogger]: With dead ends: 508 [2019-05-23 10:02:45,265 INFO L146 ILogger]: Without dead ends: 508 [2019-05-23 10:02:45,266 INFO L146 ILogger]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-05-23 10:02:45,268 INFO L146 ILogger]: Start minimizeSevpa. Operand 508 states. [2019-05-23 10:02:45,277 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 508 to 508. [2019-05-23 10:02:45,278 INFO L146 ILogger]: Start removeUnreachable. Operand 508 states. [2019-05-23 10:02:45,280 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 508 states to 508 states and 517 transitions. [2019-05-23 10:02:45,280 INFO L146 ILogger]: Start accepts. Automaton has 508 states and 517 transitions. Word has length 6 [2019-05-23 10:02:45,281 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 10:02:45,281 INFO L146 ILogger]: Abstraction has 508 states and 517 transitions. [2019-05-23 10:02:45,281 INFO L146 ILogger]: Interpolant automaton has 5 states. [2019-05-23 10:02:45,281 INFO L146 ILogger]: Start isEmpty. Operand 508 states and 517 transitions. [2019-05-23 10:02:45,282 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 8 [2019-05-23 10:02:45,282 INFO L146 ILogger]: Found error trace [2019-05-23 10:02:45,282 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2019-05-23 10:02:45,289 INFO L146 ILogger]: === Iteration 8 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT]=== [2019-05-23 10:02:45,290 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 10:02:45,290 INFO L146 ILogger]: Analyzing trace with hash 437427531, now seen corresponding path program 1 times [2019-05-23 10:02:45,291 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 10:02:45,299 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 10:02:45,301 INFO L146 ILogger]: Trace formula consists of 9 conjuncts, 3 conjunts are in the unsatisfiable core [2019-05-23 10:02:45,302 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 10:02:45,417 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 10:02:45,418 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 10:02:45,419 INFO L146 ILogger]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-05-23 10:02:45,419 INFO L146 ILogger]: Interpolant automaton has 4 states [2019-05-23 10:02:45,420 INFO L146 ILogger]: Constructing interpolant automaton starting with 4 interpolants. [2019-05-23 10:02:45,420 INFO L146 ILogger]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-05-23 10:02:45,420 INFO L146 ILogger]: Start difference. First operand 508 states and 517 transitions. Second operand 4 states. [2019-05-23 10:02:45,586 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 10:02:45,587 INFO L146 ILogger]: Finished difference Result 507 states and 516 transitions. [2019-05-23 10:02:45,587 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-05-23 10:02:45,587 INFO L146 ILogger]: Start accepts. Automaton has 4 states. Word has length 7 [2019-05-23 10:02:45,588 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 10:02:45,590 INFO L146 ILogger]: With dead ends: 507 [2019-05-23 10:02:45,590 INFO L146 ILogger]: Without dead ends: 507 [2019-05-23 10:02:45,591 INFO L146 ILogger]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-05-23 10:02:45,593 INFO L146 ILogger]: Start minimizeSevpa. Operand 507 states. [2019-05-23 10:02:45,600 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 507 to 507. [2019-05-23 10:02:45,600 INFO L146 ILogger]: Start removeUnreachable. Operand 507 states. [2019-05-23 10:02:45,602 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 507 states to 507 states and 516 transitions. [2019-05-23 10:02:45,602 INFO L146 ILogger]: Start accepts. Automaton has 507 states and 516 transitions. Word has length 7 [2019-05-23 10:02:45,602 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 10:02:45,602 INFO L146 ILogger]: Abstraction has 507 states and 516 transitions. [2019-05-23 10:02:45,602 INFO L146 ILogger]: Interpolant automaton has 4 states. [2019-05-23 10:02:45,602 INFO L146 ILogger]: Start isEmpty. Operand 507 states and 516 transitions. [2019-05-23 10:02:45,603 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 8 [2019-05-23 10:02:45,603 INFO L146 ILogger]: Found error trace [2019-05-23 10:02:45,603 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2019-05-23 10:02:45,609 INFO L146 ILogger]: === Iteration 9 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT]=== [2019-05-23 10:02:45,609 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 10:02:45,609 INFO L146 ILogger]: Analyzing trace with hash 102232374, now seen corresponding path program 1 times [2019-05-23 10:02:45,610 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 10:02:45,615 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 10:02:45,616 INFO L146 ILogger]: Trace formula consists of 9 conjuncts, 4 conjunts are in the unsatisfiable core [2019-05-23 10:02:45,616 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 10:02:45,834 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 10:02:45,835 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 10:02:45,835 INFO L146 ILogger]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-05-23 10:02:45,835 INFO L146 ILogger]: Interpolant automaton has 5 states [2019-05-23 10:02:45,836 INFO L146 ILogger]: Constructing interpolant automaton starting with 5 interpolants. [2019-05-23 10:02:45,836 INFO L146 ILogger]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-05-23 10:02:45,836 INFO L146 ILogger]: Start difference. First operand 507 states and 516 transitions. Second operand 5 states. [2019-05-23 10:02:46,073 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 10:02:46,074 INFO L146 ILogger]: Finished difference Result 506 states and 515 transitions. [2019-05-23 10:02:46,074 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-05-23 10:02:46,074 INFO L146 ILogger]: Start accepts. Automaton has 5 states. Word has length 7 [2019-05-23 10:02:46,075 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 10:02:46,077 INFO L146 ILogger]: With dead ends: 506 [2019-05-23 10:02:46,077 INFO L146 ILogger]: Without dead ends: 506 [2019-05-23 10:02:46,078 INFO L146 ILogger]: 0 DeclaredPredicates, 8 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-05-23 10:02:46,080 INFO L146 ILogger]: Start minimizeSevpa. Operand 506 states. [2019-05-23 10:02:46,087 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 506 to 506. [2019-05-23 10:02:46,087 INFO L146 ILogger]: Start removeUnreachable. Operand 506 states. [2019-05-23 10:02:46,089 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 506 states to 506 states and 515 transitions. [2019-05-23 10:02:46,090 INFO L146 ILogger]: Start accepts. Automaton has 506 states and 515 transitions. Word has length 7 [2019-05-23 10:02:46,090 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 10:02:46,090 INFO L146 ILogger]: Abstraction has 506 states and 515 transitions. [2019-05-23 10:02:46,090 INFO L146 ILogger]: Interpolant automaton has 5 states. [2019-05-23 10:02:46,091 INFO L146 ILogger]: Start isEmpty. Operand 506 states and 515 transitions. [2019-05-23 10:02:46,091 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 10 [2019-05-23 10:02:46,091 INFO L146 ILogger]: Found error trace [2019-05-23 10:02:46,091 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-05-23 10:02:46,093 INFO L146 ILogger]: === Iteration 10 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT]=== [2019-05-23 10:02:46,093 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 10:02:46,093 INFO L146 ILogger]: Analyzing trace with hash -538909933, now seen corresponding path program 1 times [2019-05-23 10:02:46,094 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 10:02:46,097 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 10:02:46,098 INFO L146 ILogger]: Trace formula consists of 11 conjuncts, 4 conjunts are in the unsatisfiable core [2019-05-23 10:02:46,099 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 10:02:46,203 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 10:02:46,204 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 10:02:46,204 INFO L146 ILogger]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-05-23 10:02:46,204 INFO L146 ILogger]: Interpolant automaton has 5 states [2019-05-23 10:02:46,204 INFO L146 ILogger]: Constructing interpolant automaton starting with 5 interpolants. [2019-05-23 10:02:46,204 INFO L146 ILogger]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-05-23 10:02:46,205 INFO L146 ILogger]: Start difference. First operand 506 states and 515 transitions. Second operand 5 states. [2019-05-23 10:02:46,547 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 10:02:46,548 INFO L146 ILogger]: Finished difference Result 505 states and 514 transitions. [2019-05-23 10:02:46,548 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-05-23 10:02:46,548 INFO L146 ILogger]: Start accepts. Automaton has 5 states. Word has length 9 [2019-05-23 10:02:46,548 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 10:02:46,554 INFO L146 ILogger]: With dead ends: 505 [2019-05-23 10:02:46,554 INFO L146 ILogger]: Without dead ends: 505 [2019-05-23 10:02:46,555 INFO L146 ILogger]: 0 DeclaredPredicates, 10 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-05-23 10:02:46,556 INFO L146 ILogger]: Start minimizeSevpa. Operand 505 states. [2019-05-23 10:02:46,562 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 505 to 505. [2019-05-23 10:02:46,562 INFO L146 ILogger]: Start removeUnreachable. Operand 505 states. [2019-05-23 10:02:46,563 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 505 states to 505 states and 514 transitions. [2019-05-23 10:02:46,563 INFO L146 ILogger]: Start accepts. Automaton has 505 states and 514 transitions. Word has length 9 [2019-05-23 10:02:46,564 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 10:02:46,564 INFO L146 ILogger]: Abstraction has 505 states and 514 transitions. [2019-05-23 10:02:46,564 INFO L146 ILogger]: Interpolant automaton has 5 states. [2019-05-23 10:02:46,564 INFO L146 ILogger]: Start isEmpty. Operand 505 states and 514 transitions. [2019-05-23 10:02:46,565 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 11 [2019-05-23 10:02:46,565 INFO L146 ILogger]: Found error trace [2019-05-23 10:02:46,565 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-05-23 10:02:46,566 INFO L146 ILogger]: === Iteration 11 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT]=== [2019-05-23 10:02:46,567 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 10:02:46,567 INFO L146 ILogger]: Analyzing trace with hash -895437985, now seen corresponding path program 1 times [2019-05-23 10:02:46,568 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 10:02:46,571 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 10:02:46,571 INFO L146 ILogger]: Trace formula consists of 12 conjuncts, 5 conjunts are in the unsatisfiable core [2019-05-23 10:02:46,572 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 10:02:46,619 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 10:02:46,620 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 10:02:46,620 INFO L146 ILogger]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-05-23 10:02:46,620 INFO L146 ILogger]: Interpolant automaton has 6 states [2019-05-23 10:02:46,621 INFO L146 ILogger]: Constructing interpolant automaton starting with 6 interpolants. [2019-05-23 10:02:46,621 INFO L146 ILogger]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-05-23 10:02:46,621 INFO L146 ILogger]: Start difference. First operand 505 states and 514 transitions. Second operand 6 states. [2019-05-23 10:02:46,888 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 10:02:46,889 INFO L146 ILogger]: Finished difference Result 504 states and 513 transitions. [2019-05-23 10:02:46,889 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-05-23 10:02:46,889 INFO L146 ILogger]: Start accepts. Automaton has 6 states. Word has length 10 [2019-05-23 10:02:46,889 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 10:02:46,891 INFO L146 ILogger]: With dead ends: 504 [2019-05-23 10:02:46,891 INFO L146 ILogger]: Without dead ends: 494 [2019-05-23 10:02:46,892 INFO L146 ILogger]: 0 DeclaredPredicates, 12 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-05-23 10:02:46,893 INFO L146 ILogger]: Start minimizeSevpa. Operand 494 states. [2019-05-23 10:02:46,900 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 494 to 494. [2019-05-23 10:02:46,900 INFO L146 ILogger]: Start removeUnreachable. Operand 494 states. [2019-05-23 10:02:46,901 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 494 states to 494 states and 504 transitions. [2019-05-23 10:02:46,902 INFO L146 ILogger]: Start accepts. Automaton has 494 states and 504 transitions. Word has length 10 [2019-05-23 10:02:46,902 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 10:02:46,902 INFO L146 ILogger]: Abstraction has 494 states and 504 transitions. [2019-05-23 10:02:46,902 INFO L146 ILogger]: Interpolant automaton has 6 states. [2019-05-23 10:02:46,902 INFO L146 ILogger]: Start isEmpty. Operand 494 states and 504 transitions. [2019-05-23 10:02:46,903 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 13 [2019-05-23 10:02:46,903 INFO L146 ILogger]: Found error trace [2019-05-23 10:02:46,903 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-05-23 10:02:46,904 INFO L146 ILogger]: === Iteration 12 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT]=== [2019-05-23 10:02:46,904 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 10:02:46,905 INFO L146 ILogger]: Analyzing trace with hash -213657467, now seen corresponding path program 1 times [2019-05-23 10:02:46,906 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 10:02:46,910 INFO L146 ILogger]: Conjunction of SSA is sat [2019-05-23 10:02:46,914 INFO L146 ILogger]: Conjunction of SSA is sat [2019-05-23 10:02:46,921 INFO L146 ILogger]: Counterexample might be feasible [2019-05-23 10:02:46,933 INFO L146 ILogger]: Did not count any witness invariants because Icfg is not BoogieIcfg [2019-05-23 10:02:46,935 INFO L146 ILogger]: Adding new model GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 23.05 10:02:46 BasicIcfg [2019-05-23 10:02:46,935 INFO L146 ILogger]: ------------------------ END TraceAbstraction---------------------------- [2019-05-23 10:02:46,938 INFO L146 ILogger]: Toolchain (without parser) took 6096.27 ms. Allocated memory was 134.2 MB in the beginning and 197.1 MB in the end (delta: 62.9 MB). Free memory was 110.3 MB in the beginning and 58.1 MB in the end (delta: 52.2 MB). Peak memory consumption was 115.1 MB. Max. memory is 7.1 GB. [2019-05-23 10:02:46,939 INFO L146 ILogger]: Boogie PL CUP Parser took 0.18 ms. Allocated memory is still 134.2 MB. Free memory was 113.0 MB in the beginning and 112.8 MB in the end (delta: 209.7 kB). Peak memory consumption was 209.7 kB. Max. memory is 7.1 GB. [2019-05-23 10:02:46,940 INFO L146 ILogger]: Boogie Procedure Inliner took 102.72 ms. Allocated memory is still 134.2 MB. Free memory was 110.3 MB in the beginning and 106.5 MB in the end (delta: 3.8 MB). Peak memory consumption was 3.8 MB. Max. memory is 7.1 GB. [2019-05-23 10:02:46,941 INFO L146 ILogger]: Boogie Preprocessor took 75.03 ms. Allocated memory is still 134.2 MB. Free memory was 106.5 MB in the beginning and 104.1 MB in the end (delta: 2.4 MB). Peak memory consumption was 2.4 MB. Max. memory is 7.1 GB. [2019-05-23 10:02:46,942 INFO L146 ILogger]: RCFGBuilder took 2218.54 ms. Allocated memory was 134.2 MB in the beginning and 169.9 MB in the end (delta: 35.7 MB). Free memory was 104.1 MB in the beginning and 102.8 MB in the end (delta: 1.3 MB). Peak memory consumption was 50.1 MB. Max. memory is 7.1 GB. [2019-05-23 10:02:46,943 INFO L146 ILogger]: IcfgTransformer took 85.71 ms. Allocated memory is still 169.9 MB. Free memory was 102.1 MB in the beginning and 96.7 MB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 7.1 GB. [2019-05-23 10:02:46,944 INFO L146 ILogger]: TraceAbstraction took 3602.95 ms. Allocated memory was 169.9 MB in the beginning and 197.1 MB in the end (delta: 27.3 MB). Free memory was 96.7 MB in the beginning and 58.1 MB in the end (delta: 38.6 MB). Peak memory consumption was 65.9 MB. Max. memory is 7.1 GB. [2019-05-23 10:02:46,949 INFO L146 ILogger]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * Boogie PL CUP Parser took 0.18 ms. Allocated memory is still 134.2 MB. Free memory was 113.0 MB in the beginning and 112.8 MB in the end (delta: 209.7 kB). Peak memory consumption was 209.7 kB. Max. memory is 7.1 GB. * Boogie Procedure Inliner took 102.72 ms. Allocated memory is still 134.2 MB. Free memory was 110.3 MB in the beginning and 106.5 MB in the end (delta: 3.8 MB). Peak memory consumption was 3.8 MB. Max. memory is 7.1 GB. * Boogie Preprocessor took 75.03 ms. Allocated memory is still 134.2 MB. Free memory was 106.5 MB in the beginning and 104.1 MB in the end (delta: 2.4 MB). Peak memory consumption was 2.4 MB. Max. memory is 7.1 GB. * RCFGBuilder took 2218.54 ms. Allocated memory was 134.2 MB in the beginning and 169.9 MB in the end (delta: 35.7 MB). Free memory was 104.1 MB in the beginning and 102.8 MB in the end (delta: 1.3 MB). Peak memory consumption was 50.1 MB. Max. memory is 7.1 GB. * IcfgTransformer took 85.71 ms. Allocated memory is still 169.9 MB. Free memory was 102.1 MB in the beginning and 96.7 MB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 7.1 GB. * TraceAbstraction took 3602.95 ms. Allocated memory was 169.9 MB in the beginning and 197.1 MB in the end (delta: 27.3 MB). Free memory was 96.7 MB in the beginning and 58.1 MB in the end (delta: 38.6 MB). Peak memory consumption was 65.9 MB. Max. memory is 7.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 658]: assertion can be violated assertion can be violated We found a FailurePath: [L642] requires void$SimpleFrame2Cons$4$actionPerformed$4888$__this != $null; [L651] r0125 := void$SimpleFrame2Cons$4$actionPerformed$4888$__this; [L653] r1126 := void$SimpleFrame2Cons$4$actionPerformed$4888$param_0; [L655] $r2129 := SimpleFrame2Cons$SimpleFrame2Cons$4$this$0763; [L390] r083 := $param_0; [L392] $r185 := javax.swing.JButton$SimpleFrame2Cons$event2227; [L394] __ret := $r185; [L658] assert $r3130 != $null; - StatisticsResult: Ultimate Automizer benchmark data CFG has 16 procedures, 645 locations, 87 error locations. UNSAFE Result, 3.5s OverallTime, 12 OverallIterations, 1 TraceHistogramMax, 1.9s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 5924 SDtfs, 1503 SDslu, 12980 SDs, 0 SdLazy, 82 SolverSat, 11 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.7s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 71 GetRequests, 28 SyntacticMatches, 0 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.8s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=645occurred in iteration=0, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.2s AutomataMinimizationTime, 11 MinimizatonAttempts, 0 StatesRemovedByMinimization, 0 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.0s SatisfiabilityAnalysisTime, 1.0s InterpolantComputationTime, 78 NumberOfCodeBlocks, 78 NumberOfCodeBlocksAsserted, 12 NumberOfCheckSat, 55 ConstructedInterpolants, 0 QuantifiedInterpolants, 1026 SizeOfPredicates, 16 NumberOfNonLiveVariables, 88 ConjunctsInSsa, 38 ConjunctsInUnsatCore, 11 InterpolantComputations, 11 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...