java -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data --rcfgbuilder.command.for.external.solver 'z3 SMTLIB2_COMPLIANT=true -memory:4096 -smt2 -in -t:12000' -tc ../../../trunk/examples/toolchains/AutomizerBplInline.xml --rcfgbuilder.size.of.a.code.block SingleStatement -i ../../../trunk/examples/programs/real-life/GuiTestExampleUnsafe.bpl -------------------------------------------------------------------------------- This is Ultimate 0.1.24-7aa59a0 [2019-05-23 09:21:57,025 INFO L146 ILogger]: Resetting all preferences to default values... [2019-05-23 09:21:57,027 INFO L146 ILogger]: Resetting UltimateCore preferences to default values [2019-05-23 09:21:57,039 INFO L146 ILogger]: Ultimate Commandline Interface provides no preferences, ignoring... [2019-05-23 09:21:57,039 INFO L146 ILogger]: Resetting Boogie Preprocessor preferences to default values [2019-05-23 09:21:57,040 INFO L146 ILogger]: Resetting Boogie Procedure Inliner preferences to default values [2019-05-23 09:21:57,042 INFO L146 ILogger]: Resetting Abstract Interpretation preferences to default values [2019-05-23 09:21:57,043 INFO L146 ILogger]: Resetting LassoRanker preferences to default values [2019-05-23 09:21:57,045 INFO L146 ILogger]: Resetting Reaching Definitions preferences to default values [2019-05-23 09:21:57,046 INFO L146 ILogger]: Resetting SyntaxChecker preferences to default values [2019-05-23 09:21:57,047 INFO L146 ILogger]: Büchi Program Product provides no preferences, ignoring... [2019-05-23 09:21:57,047 INFO L146 ILogger]: Resetting LTL2Aut preferences to default values [2019-05-23 09:21:57,048 INFO L146 ILogger]: Resetting PEA to Boogie preferences to default values [2019-05-23 09:21:57,049 INFO L146 ILogger]: Resetting BlockEncodingV2 preferences to default values [2019-05-23 09:21:57,050 INFO L146 ILogger]: Resetting ChcToBoogie preferences to default values [2019-05-23 09:21:57,051 INFO L146 ILogger]: Resetting AutomataScriptInterpreter preferences to default values [2019-05-23 09:21:57,052 INFO L146 ILogger]: Resetting BuchiAutomizer preferences to default values [2019-05-23 09:21:57,054 INFO L146 ILogger]: Resetting CACSL2BoogieTranslator preferences to default values [2019-05-23 09:21:57,056 INFO L146 ILogger]: Resetting CodeCheck preferences to default values [2019-05-23 09:21:57,058 INFO L146 ILogger]: Resetting InvariantSynthesis preferences to default values [2019-05-23 09:21:57,059 INFO L146 ILogger]: Resetting RCFGBuilder preferences to default values [2019-05-23 09:21:57,060 INFO L146 ILogger]: Resetting TraceAbstraction preferences to default values [2019-05-23 09:21:57,062 INFO L146 ILogger]: TraceAbstractionConcurrent provides no preferences, ignoring... [2019-05-23 09:21:57,063 INFO L146 ILogger]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2019-05-23 09:21:57,063 INFO L146 ILogger]: Resetting TreeAutomizer preferences to default values [2019-05-23 09:21:57,064 INFO L146 ILogger]: Resetting IcfgToChc preferences to default values [2019-05-23 09:21:57,064 INFO L146 ILogger]: Resetting IcfgTransformer preferences to default values [2019-05-23 09:21:57,066 INFO L146 ILogger]: ReqToTest provides no preferences, ignoring... [2019-05-23 09:21:57,066 INFO L146 ILogger]: Resetting Boogie Printer preferences to default values [2019-05-23 09:21:57,067 INFO L146 ILogger]: Resetting ChcSmtPrinter preferences to default values [2019-05-23 09:21:57,067 INFO L146 ILogger]: Resetting ReqPrinter preferences to default values [2019-05-23 09:21:57,068 INFO L146 ILogger]: Resetting Witness Printer preferences to default values [2019-05-23 09:21:57,069 INFO L146 ILogger]: Boogie PL CUP Parser provides no preferences, ignoring... [2019-05-23 09:21:57,070 INFO L146 ILogger]: Resetting CDTParser preferences to default values [2019-05-23 09:21:57,071 INFO L146 ILogger]: AutomataScriptParser provides no preferences, ignoring... [2019-05-23 09:21:57,071 INFO L146 ILogger]: ReqParser provides no preferences, ignoring... [2019-05-23 09:21:57,071 INFO L146 ILogger]: Resetting SmtParser preferences to default values [2019-05-23 09:21:57,072 INFO L146 ILogger]: Resetting Witness Parser preferences to default values [2019-05-23 09:21:57,073 INFO L146 ILogger]: Finished resetting all preferences to default values... Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder: Command for external solver -> z3 SMTLIB2_COMPLIANT=true -memory:4096 -smt2 -in -t:12000 Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder: Size of a code block -> SingleStatement [2019-05-23 09:21:57,103 INFO L146 ILogger]: Repository-Root is: /tmp [2019-05-23 09:21:57,121 INFO L146 ILogger]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2019-05-23 09:21:57,124 INFO L146 ILogger]: [Toolchain 1]: Toolchain selected. [2019-05-23 09:21:57,126 INFO L146 ILogger]: Initializing Boogie PL CUP Parser... [2019-05-23 09:21:57,127 INFO L146 ILogger]: Boogie PL CUP Parser initialized [2019-05-23 09:21:57,127 INFO L146 ILogger]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/programs/real-life/GuiTestExampleUnsafe.bpl [2019-05-23 09:21:57,128 INFO L146 ILogger]: Parsing: '/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/programs/real-life/GuiTestExampleUnsafe.bpl' [2019-05-23 09:21:57,198 INFO L146 ILogger]: ####################### [Toolchain 1] ####################### [2019-05-23 09:21:57,200 INFO L146 ILogger]: Walking toolchain with 4 elements. [2019-05-23 09:21:57,200 INFO L146 ILogger]: ------------------------Boogie Procedure Inliner---------------------------- [2019-05-23 09:21:57,201 INFO L146 ILogger]: Initializing Boogie Procedure Inliner... [2019-05-23 09:21:57,201 INFO L146 ILogger]: Boogie Procedure Inliner initialized [2019-05-23 09:21:57,217 INFO L146 ILogger]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 09:21:57" (1/1) ... [2019-05-23 09:21:57,235 INFO L146 ILogger]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 09:21:57" (1/1) ... [2019-05-23 09:21:57,244 WARN L146 ILogger]: Program contained no entry procedure! [2019-05-23 09:21:57,245 WARN L146 ILogger]: Missing entry procedures: [ULTIMATE.start] [2019-05-23 09:21:57,245 WARN L146 ILogger]: Fallback enabled. All procedures will be processed. [2019-05-23 09:21:57,285 INFO L146 ILogger]: ------------------------ END Boogie Procedure Inliner---------------------------- [2019-05-23 09:21:57,286 INFO L146 ILogger]: ------------------------Boogie Preprocessor---------------------------- [2019-05-23 09:21:57,286 INFO L146 ILogger]: Initializing Boogie Preprocessor... [2019-05-23 09:21:57,286 INFO L146 ILogger]: Boogie Preprocessor initialized [2019-05-23 09:21:57,308 INFO L146 ILogger]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 09:21:57" (1/1) ... [2019-05-23 09:21:57,308 INFO L146 ILogger]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 09:21:57" (1/1) ... [2019-05-23 09:21:57,331 INFO L146 ILogger]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 09:21:57" (1/1) ... [2019-05-23 09:21:57,335 INFO L146 ILogger]: Executing the observer StructExpander from plugin Boogie Preprocessor for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 09:21:57" (1/1) ... [2019-05-23 09:21:57,360 INFO L146 ILogger]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 09:21:57" (1/1) ... [2019-05-23 09:21:57,368 INFO L146 ILogger]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 09:21:57" (1/1) ... [2019-05-23 09:21:57,373 INFO L146 ILogger]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 09:21:57" (1/1) ... [2019-05-23 09:21:57,380 INFO L146 ILogger]: ------------------------ END Boogie Preprocessor---------------------------- [2019-05-23 09:21:57,381 INFO L146 ILogger]: ------------------------RCFGBuilder---------------------------- [2019-05-23 09:21:57,381 INFO L146 ILogger]: Initializing RCFGBuilder... [2019-05-23 09:21:57,381 INFO L146 ILogger]: RCFGBuilder initialized [2019-05-23 09:21:57,382 INFO L146 ILogger]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 09:21:57" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:4096 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:4096 -smt2 -in -t:12000 [2019-05-23 09:21:57,469 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$3$$la$init$ra$$4885 given in one single declaration [2019-05-23 09:21:57,470 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$3$$la$init$ra$$4885 [2019-05-23 09:21:57,470 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$3$$la$init$ra$$4885 [2019-05-23 09:21:57,470 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$2$actionPerformed$4553 given in one single declaration [2019-05-23 09:21:57,470 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$2$actionPerformed$4553 [2019-05-23 09:21:57,471 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$2$actionPerformed$4553 [2019-05-23 09:21:57,471 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$3$actionPerformed$4886 given in one single declaration [2019-05-23 09:21:57,472 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$3$actionPerformed$4886 [2019-05-23 09:21:57,472 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$3$actionPerformed$4886 [2019-05-23 09:21:57,472 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$$la$init$ra$$1805 given in one single declaration [2019-05-23 09:21:57,472 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$$la$init$ra$$1805 [2019-05-23 09:21:57,473 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$$la$init$ra$$1805 [2019-05-23 09:21:57,473 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$1$$la$init$ra$$1802 given in one single declaration [2019-05-23 09:21:57,473 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$1$$la$init$ra$$1802 [2019-05-23 09:21:57,473 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$1$$la$init$ra$$1802 [2019-05-23 09:21:57,473 INFO L146 ILogger]: Found specification of procedure void$javax.swing.SwingUtilities$invokeLater$4940 [2019-05-23 09:21:57,474 INFO L146 ILogger]: Found specification of procedure void$javax.swing.JFrame$setLayout$1827 [2019-05-23 09:21:57,475 INFO L146 ILogger]: Specification and implementation of procedure javax.swing.JButton$SimpleFrame2Cons$access$0$1806 given in one single declaration [2019-05-23 09:21:57,475 INFO L146 ILogger]: Found specification of procedure javax.swing.JButton$SimpleFrame2Cons$access$0$1806 [2019-05-23 09:21:57,475 INFO L146 ILogger]: Found implementation of procedure javax.swing.JButton$SimpleFrame2Cons$access$0$1806 [2019-05-23 09:21:57,476 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$2$$la$init$ra$$4552 given in one single declaration [2019-05-23 09:21:57,476 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$2$$la$init$ra$$4552 [2019-05-23 09:21:57,477 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$2$$la$init$ra$$4552 [2019-05-23 09:21:57,477 INFO L146 ILogger]: Found specification of procedure void$java.awt.Frame$setResizable$1858 [2019-05-23 09:21:57,477 INFO L146 ILogger]: Specification and implementation of procedure java.awt.Dimension$java.awt.Toolkit$getScreenSize$3246 given in one single declaration [2019-05-23 09:21:57,477 INFO L146 ILogger]: Found specification of procedure java.awt.Dimension$java.awt.Toolkit$getScreenSize$3246 [2019-05-23 09:21:57,477 INFO L146 ILogger]: Found implementation of procedure java.awt.Dimension$java.awt.Toolkit$getScreenSize$3246 [2019-05-23 09:21:57,478 INFO L146 ILogger]: Specification and implementation of procedure void$javax.swing.JFrame$$la$init$ra$$1809 given in one single declaration [2019-05-23 09:21:57,478 INFO L146 ILogger]: Found specification of procedure void$javax.swing.JFrame$$la$init$ra$$1809 [2019-05-23 09:21:57,478 INFO L146 ILogger]: Found implementation of procedure void$javax.swing.JFrame$$la$init$ra$$1809 [2019-05-23 09:21:57,479 INFO L146 ILogger]: Specification and implementation of procedure int$SimpleFrame2Cons$access$2$1808 given in one single declaration [2019-05-23 09:21:57,480 INFO L146 ILogger]: Found specification of procedure int$SimpleFrame2Cons$access$2$1808 [2019-05-23 09:21:57,480 INFO L146 ILogger]: Found implementation of procedure int$SimpleFrame2Cons$access$2$1808 [2019-05-23 09:21:57,480 INFO L146 ILogger]: Found specification of procedure void$javax.swing.JFrame$setDefaultCloseOperation$1816 [2019-05-23 09:21:57,480 INFO L146 ILogger]: Found specification of procedure void$javax.swing.AbstractButton$addActionListener$4123 [2019-05-23 09:21:57,481 INFO L146 ILogger]: Found specification of procedure void$java.awt.Window$setLocation$1913 [2019-05-23 09:21:57,484 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$4$$la$init$ra$$4887 given in one single declaration [2019-05-23 09:21:57,484 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$4$$la$init$ra$$4887 [2019-05-23 09:21:57,484 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$4$$la$init$ra$$4887 [2019-05-23 09:21:57,484 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$4$actionPerformed$4888 given in one single declaration [2019-05-23 09:21:57,484 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$4$actionPerformed$4888 [2019-05-23 09:21:57,485 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$4$actionPerformed$4888 [2019-05-23 09:21:57,485 INFO L146 ILogger]: Found specification of procedure void$javax.swing.AbstractButton$setEnabled$4131 [2019-05-23 09:21:57,485 INFO L146 ILogger]: Found specification of procedure void$java.awt.Window$setVisible$1918 [2019-05-23 09:21:57,485 INFO L146 ILogger]: Found specification of procedure int$java.awt.Component$getHeight$2305 [2019-05-23 09:21:57,485 INFO L146 ILogger]: Found specification of procedure void$java.awt.Window$pack$1909 [2019-05-23 09:21:57,490 INFO L146 ILogger]: Found specification of procedure java.awt.Toolkit$java.awt.Toolkit$getDefaultToolkit$3255 [2019-05-23 09:21:57,490 INFO L146 ILogger]: Found specification of procedure int$java.awt.Component$getWidth$2304 [2019-05-23 09:21:57,490 INFO L146 ILogger]: Found specification of procedure void$java.awt.Frame$setTitle$1852 [2019-05-23 09:21:57,491 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$access$1$1807 given in one single declaration [2019-05-23 09:21:57,491 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$access$1$1807 [2019-05-23 09:21:57,491 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$access$1$1807 [2019-05-23 09:21:57,491 INFO L146 ILogger]: Found specification of procedure void$java.awt.FlowLayout$$la$init$ra$$4889 [2019-05-23 09:21:57,491 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$1$run$1803 given in one single declaration [2019-05-23 09:21:57,492 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$1$run$1803 [2019-05-23 09:21:57,492 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$1$run$1803 [2019-05-23 09:21:57,492 INFO L146 ILogger]: Specification and implementation of procedure void$SimpleFrame2Cons$main$1804 given in one single declaration [2019-05-23 09:21:57,492 INFO L146 ILogger]: Found specification of procedure void$SimpleFrame2Cons$main$1804 [2019-05-23 09:21:57,493 INFO L146 ILogger]: Found implementation of procedure void$SimpleFrame2Cons$main$1804 [2019-05-23 09:21:57,493 INFO L146 ILogger]: Found specification of procedure void$javax.swing.JButton$$la$init$ra$$2558 [2019-05-23 09:21:57,493 INFO L146 ILogger]: Specification and implementation of procedure $EFG_Procedure given in one single declaration [2019-05-23 09:21:57,493 INFO L146 ILogger]: Found specification of procedure $EFG_Procedure [2019-05-23 09:21:57,493 INFO L146 ILogger]: Found implementation of procedure $EFG_Procedure [2019-05-23 09:21:57,494 INFO L146 ILogger]: Found specification of procedure java.awt.Component$java.awt.Container$add$2075 [2019-05-23 09:21:57,495 INFO L146 ILogger]: Found specification of procedure void$java.lang.Object$$la$init$ra$$38 [2019-05-23 09:21:57,806 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 09:21:57,878 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 09:21:57,967 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 09:21:58,049 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 09:21:58,555 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 09:21:58,562 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 09:21:58,578 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 09:21:58,586 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 09:21:58,608 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 09:21:58,618 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 09:21:58,659 WARN L146 ILogger]: Label in the middle of a codeblock. [2019-05-23 09:21:59,629 INFO L146 ILogger]: Using library mode [2019-05-23 09:21:59,629 INFO L146 ILogger]: Removed 44 assume(true) statements. [2019-05-23 09:21:59,631 INFO L146 ILogger]: Adding new model GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.05 09:21:59 BoogieIcfgContainer [2019-05-23 09:21:59,631 INFO L146 ILogger]: ------------------------ END RCFGBuilder---------------------------- [2019-05-23 09:21:59,633 INFO L146 ILogger]: ------------------------TraceAbstraction---------------------------- [2019-05-23 09:21:59,633 INFO L146 ILogger]: Initializing TraceAbstraction... [2019-05-23 09:21:59,636 INFO L146 ILogger]: TraceAbstraction initialized [2019-05-23 09:21:59,637 INFO L146 ILogger]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.05 09:21:57" (1/2) ... [2019-05-23 09:21:59,638 INFO L146 ILogger]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2263aa0c and model type GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.05 09:21:59, skipping insertion in model container [2019-05-23 09:21:59,638 INFO L146 ILogger]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.05 09:21:59" (2/2) ... [2019-05-23 09:21:59,640 INFO L146 ILogger]: Analyzing ICFG GuiTestExampleUnsafe.bpl [2019-05-23 09:21:59,650 INFO L146 ILogger]: Automizer settings: Hoare:false NWA Interpolation:ForwardPredicates Determinization: PREDICATE_ABSTRACTION [2019-05-23 09:21:59,659 INFO L146 ILogger]: Appying trace abstraction to program that has 87 error locations. [2019-05-23 09:21:59,674 INFO L146 ILogger]: Starting to check reachability of 87 error locations. [2019-05-23 09:21:59,696 INFO L146 ILogger]: Using default assertion order modulation [2019-05-23 09:21:59,697 INFO L146 ILogger]: Interprodecural is true [2019-05-23 09:21:59,697 INFO L146 ILogger]: Hoare is false [2019-05-23 09:21:59,697 INFO L146 ILogger]: Compute interpolants for ForwardPredicates [2019-05-23 09:21:59,697 INFO L146 ILogger]: Backedges is STRAIGHT_LINE [2019-05-23 09:21:59,697 INFO L146 ILogger]: Determinization is PREDICATE_ABSTRACTION [2019-05-23 09:21:59,698 INFO L146 ILogger]: Difference is false [2019-05-23 09:21:59,698 INFO L146 ILogger]: Minimize is MINIMIZE_SEVPA [2019-05-23 09:21:59,698 INFO L146 ILogger]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2019-05-23 09:21:59,742 INFO L146 ILogger]: Start isEmpty. Operand 645 states. [2019-05-23 09:21:59,751 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 4 [2019-05-23 09:21:59,751 INFO L146 ILogger]: Found error trace [2019-05-23 09:21:59,752 INFO L146 ILogger]: trace histogram [1, 1, 1] [2019-05-23 09:21:59,757 INFO L146 ILogger]: === Iteration 1 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT]=== [2019-05-23 09:21:59,763 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 09:21:59,763 INFO L146 ILogger]: Analyzing trace with hash 261193, now seen corresponding path program 1 times [2019-05-23 09:21:59,822 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 09:21:59,843 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 09:21:59,846 WARN L146 ILogger]: Trace formula consists of 5 conjuncts, 3 conjunts are in the unsatisfiable core [2019-05-23 09:21:59,849 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 09:21:59,925 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 09:21:59,927 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 09:21:59,927 INFO L146 ILogger]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-05-23 09:21:59,932 INFO L146 ILogger]: Interpolant automaton has 4 states [2019-05-23 09:21:59,946 INFO L146 ILogger]: Constructing interpolant automaton starting with 4 interpolants. [2019-05-23 09:21:59,947 INFO L146 ILogger]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-05-23 09:21:59,950 INFO L146 ILogger]: Start difference. First operand 645 states. Second operand 4 states. [2019-05-23 09:22:00,055 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 09:22:00,055 INFO L146 ILogger]: Finished difference Result 640 states and 642 transitions. [2019-05-23 09:22:00,056 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-05-23 09:22:00,057 INFO L146 ILogger]: Start accepts. Automaton has 4 states. Word has length 3 [2019-05-23 09:22:00,057 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 09:22:00,096 INFO L146 ILogger]: With dead ends: 640 [2019-05-23 09:22:00,096 INFO L146 ILogger]: Without dead ends: 558 [2019-05-23 09:22:00,101 INFO L146 ILogger]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-05-23 09:22:00,132 INFO L146 ILogger]: Start minimizeSevpa. Operand 558 states. [2019-05-23 09:22:00,189 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 558 to 558. [2019-05-23 09:22:00,190 INFO L146 ILogger]: Start removeUnreachable. Operand 558 states. [2019-05-23 09:22:00,196 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 558 states to 558 states and 564 transitions. [2019-05-23 09:22:00,197 INFO L146 ILogger]: Start accepts. Automaton has 558 states and 564 transitions. Word has length 3 [2019-05-23 09:22:00,198 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 09:22:00,198 INFO L146 ILogger]: Abstraction has 558 states and 564 transitions. [2019-05-23 09:22:00,198 INFO L146 ILogger]: Interpolant automaton has 4 states. [2019-05-23 09:22:00,198 INFO L146 ILogger]: Start isEmpty. Operand 558 states and 564 transitions. [2019-05-23 09:22:00,199 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 5 [2019-05-23 09:22:00,199 INFO L146 ILogger]: Found error trace [2019-05-23 09:22:00,199 INFO L146 ILogger]: trace histogram [1, 1, 1, 1] [2019-05-23 09:22:00,202 INFO L146 ILogger]: === Iteration 2 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT]=== [2019-05-23 09:22:00,203 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 09:22:00,203 INFO L146 ILogger]: Analyzing trace with hash 16224195, now seen corresponding path program 1 times [2019-05-23 09:22:00,204 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 09:22:00,207 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 09:22:00,207 WARN L146 ILogger]: Trace formula consists of 6 conjuncts, 3 conjunts are in the unsatisfiable core [2019-05-23 09:22:00,208 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 09:22:00,243 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 09:22:00,243 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 09:22:00,244 INFO L146 ILogger]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-05-23 09:22:00,245 INFO L146 ILogger]: Interpolant automaton has 4 states [2019-05-23 09:22:00,246 INFO L146 ILogger]: Constructing interpolant automaton starting with 4 interpolants. [2019-05-23 09:22:00,246 INFO L146 ILogger]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-05-23 09:22:00,247 INFO L146 ILogger]: Start difference. First operand 558 states and 564 transitions. Second operand 4 states. [2019-05-23 09:22:00,296 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 09:22:00,296 INFO L146 ILogger]: Finished difference Result 557 states and 563 transitions. [2019-05-23 09:22:00,301 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-05-23 09:22:00,301 INFO L146 ILogger]: Start accepts. Automaton has 4 states. Word has length 4 [2019-05-23 09:22:00,301 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 09:22:00,309 INFO L146 ILogger]: With dead ends: 557 [2019-05-23 09:22:00,312 INFO L146 ILogger]: Without dead ends: 557 [2019-05-23 09:22:00,313 INFO L146 ILogger]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-05-23 09:22:00,318 INFO L146 ILogger]: Start minimizeSevpa. Operand 557 states. [2019-05-23 09:22:00,360 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 557 to 557. [2019-05-23 09:22:00,361 INFO L146 ILogger]: Start removeUnreachable. Operand 557 states. [2019-05-23 09:22:00,368 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 557 states to 557 states and 563 transitions. [2019-05-23 09:22:00,368 INFO L146 ILogger]: Start accepts. Automaton has 557 states and 563 transitions. Word has length 4 [2019-05-23 09:22:00,372 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 09:22:00,372 INFO L146 ILogger]: Abstraction has 557 states and 563 transitions. [2019-05-23 09:22:00,372 INFO L146 ILogger]: Interpolant automaton has 4 states. [2019-05-23 09:22:00,372 INFO L146 ILogger]: Start isEmpty. Operand 557 states and 563 transitions. [2019-05-23 09:22:00,373 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 6 [2019-05-23 09:22:00,373 INFO L146 ILogger]: Found error trace [2019-05-23 09:22:00,373 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1] [2019-05-23 09:22:00,377 INFO L146 ILogger]: === Iteration 3 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT]=== [2019-05-23 09:22:00,378 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 09:22:00,379 INFO L146 ILogger]: Analyzing trace with hash 260557076, now seen corresponding path program 1 times [2019-05-23 09:22:00,380 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 09:22:00,385 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 09:22:00,385 INFO L146 ILogger]: Trace formula consists of 7 conjuncts, 3 conjunts are in the unsatisfiable core [2019-05-23 09:22:00,386 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 09:22:00,500 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 09:22:00,501 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 09:22:00,501 INFO L146 ILogger]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-05-23 09:22:00,501 INFO L146 ILogger]: Interpolant automaton has 4 states [2019-05-23 09:22:00,502 INFO L146 ILogger]: Constructing interpolant automaton starting with 4 interpolants. [2019-05-23 09:22:00,502 INFO L146 ILogger]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-05-23 09:22:00,502 INFO L146 ILogger]: Start difference. First operand 557 states and 563 transitions. Second operand 4 states. [2019-05-23 09:22:00,561 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 09:22:00,562 INFO L146 ILogger]: Finished difference Result 556 states and 562 transitions. [2019-05-23 09:22:00,562 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-05-23 09:22:00,562 INFO L146 ILogger]: Start accepts. Automaton has 4 states. Word has length 5 [2019-05-23 09:22:00,562 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 09:22:00,565 INFO L146 ILogger]: With dead ends: 556 [2019-05-23 09:22:00,565 INFO L146 ILogger]: Without dead ends: 551 [2019-05-23 09:22:00,566 INFO L146 ILogger]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-05-23 09:22:00,568 INFO L146 ILogger]: Start minimizeSevpa. Operand 551 states. [2019-05-23 09:22:00,579 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 551 to 551. [2019-05-23 09:22:00,579 INFO L146 ILogger]: Start removeUnreachable. Operand 551 states. [2019-05-23 09:22:00,581 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 551 states to 551 states and 558 transitions. [2019-05-23 09:22:00,581 INFO L146 ILogger]: Start accepts. Automaton has 551 states and 558 transitions. Word has length 5 [2019-05-23 09:22:00,582 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 09:22:00,582 INFO L146 ILogger]: Abstraction has 551 states and 558 transitions. [2019-05-23 09:22:00,582 INFO L146 ILogger]: Interpolant automaton has 4 states. [2019-05-23 09:22:00,582 INFO L146 ILogger]: Start isEmpty. Operand 551 states and 558 transitions. [2019-05-23 09:22:00,583 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 6 [2019-05-23 09:22:00,583 INFO L146 ILogger]: Found error trace [2019-05-23 09:22:00,583 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1] [2019-05-23 09:22:00,588 INFO L146 ILogger]: === Iteration 4 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT]=== [2019-05-23 09:22:00,588 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 09:22:00,589 INFO L146 ILogger]: Analyzing trace with hash 81147768, now seen corresponding path program 1 times [2019-05-23 09:22:00,590 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 09:22:00,592 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 09:22:00,593 INFO L146 ILogger]: Trace formula consists of 7 conjuncts, 3 conjunts are in the unsatisfiable core [2019-05-23 09:22:00,594 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 09:22:00,709 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 09:22:00,709 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 09:22:00,709 INFO L146 ILogger]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-05-23 09:22:00,709 INFO L146 ILogger]: Interpolant automaton has 4 states [2019-05-23 09:22:00,710 INFO L146 ILogger]: Constructing interpolant automaton starting with 4 interpolants. [2019-05-23 09:22:00,710 INFO L146 ILogger]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-05-23 09:22:00,710 INFO L146 ILogger]: Start difference. First operand 551 states and 558 transitions. Second operand 4 states. [2019-05-23 09:22:00,957 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 09:22:00,957 INFO L146 ILogger]: Finished difference Result 539 states and 546 transitions. [2019-05-23 09:22:00,958 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-05-23 09:22:00,958 INFO L146 ILogger]: Start accepts. Automaton has 4 states. Word has length 5 [2019-05-23 09:22:00,958 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 09:22:00,961 INFO L146 ILogger]: With dead ends: 539 [2019-05-23 09:22:00,961 INFO L146 ILogger]: Without dead ends: 521 [2019-05-23 09:22:00,962 INFO L146 ILogger]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-05-23 09:22:00,963 INFO L146 ILogger]: Start minimizeSevpa. Operand 521 states. [2019-05-23 09:22:00,971 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 521 to 521. [2019-05-23 09:22:00,971 INFO L146 ILogger]: Start removeUnreachable. Operand 521 states. [2019-05-23 09:22:00,973 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 521 states to 521 states and 528 transitions. [2019-05-23 09:22:00,973 INFO L146 ILogger]: Start accepts. Automaton has 521 states and 528 transitions. Word has length 5 [2019-05-23 09:22:00,974 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 09:22:00,974 INFO L146 ILogger]: Abstraction has 521 states and 528 transitions. [2019-05-23 09:22:00,974 INFO L146 ILogger]: Interpolant automaton has 4 states. [2019-05-23 09:22:00,974 INFO L146 ILogger]: Start isEmpty. Operand 521 states and 528 transitions. [2019-05-23 09:22:00,975 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 6 [2019-05-23 09:22:00,975 INFO L146 ILogger]: Found error trace [2019-05-23 09:22:00,975 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1] [2019-05-23 09:22:00,978 INFO L146 ILogger]: === Iteration 5 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT]=== [2019-05-23 09:22:00,978 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 09:22:00,978 INFO L146 ILogger]: Analyzing trace with hash 277734566, now seen corresponding path program 1 times [2019-05-23 09:22:00,979 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 09:22:00,982 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 09:22:00,983 INFO L146 ILogger]: Trace formula consists of 7 conjuncts, 3 conjunts are in the unsatisfiable core [2019-05-23 09:22:00,983 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 09:22:01,057 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 09:22:01,058 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 09:22:01,058 INFO L146 ILogger]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-05-23 09:22:01,058 INFO L146 ILogger]: Interpolant automaton has 4 states [2019-05-23 09:22:01,058 INFO L146 ILogger]: Constructing interpolant automaton starting with 4 interpolants. [2019-05-23 09:22:01,059 INFO L146 ILogger]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-05-23 09:22:01,059 INFO L146 ILogger]: Start difference. First operand 521 states and 528 transitions. Second operand 4 states. [2019-05-23 09:22:01,083 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 09:22:01,084 INFO L146 ILogger]: Finished difference Result 520 states and 527 transitions. [2019-05-23 09:22:01,084 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-05-23 09:22:01,084 INFO L146 ILogger]: Start accepts. Automaton has 4 states. Word has length 5 [2019-05-23 09:22:01,084 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 09:22:01,086 INFO L146 ILogger]: With dead ends: 520 [2019-05-23 09:22:01,087 INFO L146 ILogger]: Without dead ends: 515 [2019-05-23 09:22:01,087 INFO L146 ILogger]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-05-23 09:22:01,088 INFO L146 ILogger]: Start minimizeSevpa. Operand 515 states. [2019-05-23 09:22:01,095 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 515 to 515. [2019-05-23 09:22:01,095 INFO L146 ILogger]: Start removeUnreachable. Operand 515 states. [2019-05-23 09:22:01,098 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 515 states to 515 states and 523 transitions. [2019-05-23 09:22:01,098 INFO L146 ILogger]: Start accepts. Automaton has 515 states and 523 transitions. Word has length 5 [2019-05-23 09:22:01,098 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 09:22:01,099 INFO L146 ILogger]: Abstraction has 515 states and 523 transitions. [2019-05-23 09:22:01,099 INFO L146 ILogger]: Interpolant automaton has 4 states. [2019-05-23 09:22:01,099 INFO L146 ILogger]: Start isEmpty. Operand 515 states and 523 transitions. [2019-05-23 09:22:01,099 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 6 [2019-05-23 09:22:01,099 INFO L146 ILogger]: Found error trace [2019-05-23 09:22:01,100 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1] [2019-05-23 09:22:01,104 INFO L146 ILogger]: === Iteration 6 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT]=== [2019-05-23 09:22:01,105 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 09:22:01,105 INFO L146 ILogger]: Analyzing trace with hash 28660961, now seen corresponding path program 1 times [2019-05-23 09:22:01,106 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 09:22:01,109 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 09:22:01,109 INFO L146 ILogger]: Trace formula consists of 7 conjuncts, 3 conjunts are in the unsatisfiable core [2019-05-23 09:22:01,110 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 09:22:01,121 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 09:22:01,121 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 09:22:01,121 INFO L146 ILogger]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2019-05-23 09:22:01,121 INFO L146 ILogger]: Interpolant automaton has 4 states [2019-05-23 09:22:01,122 INFO L146 ILogger]: Constructing interpolant automaton starting with 4 interpolants. [2019-05-23 09:22:01,122 INFO L146 ILogger]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-05-23 09:22:01,122 INFO L146 ILogger]: Start difference. First operand 515 states and 523 transitions. Second operand 4 states. [2019-05-23 09:22:01,175 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 09:22:01,176 INFO L146 ILogger]: Finished difference Result 514 states and 522 transitions. [2019-05-23 09:22:01,176 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-05-23 09:22:01,176 INFO L146 ILogger]: Start accepts. Automaton has 4 states. Word has length 5 [2019-05-23 09:22:01,176 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 09:22:01,179 INFO L146 ILogger]: With dead ends: 514 [2019-05-23 09:22:01,179 INFO L146 ILogger]: Without dead ends: 509 [2019-05-23 09:22:01,179 INFO L146 ILogger]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-05-23 09:22:01,181 INFO L146 ILogger]: Start minimizeSevpa. Operand 509 states. [2019-05-23 09:22:01,187 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 509 to 509. [2019-05-23 09:22:01,188 INFO L146 ILogger]: Start removeUnreachable. Operand 509 states. [2019-05-23 09:22:01,189 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 509 states to 509 states and 518 transitions. [2019-05-23 09:22:01,190 INFO L146 ILogger]: Start accepts. Automaton has 509 states and 518 transitions. Word has length 5 [2019-05-23 09:22:01,190 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 09:22:01,190 INFO L146 ILogger]: Abstraction has 509 states and 518 transitions. [2019-05-23 09:22:01,190 INFO L146 ILogger]: Interpolant automaton has 4 states. [2019-05-23 09:22:01,190 INFO L146 ILogger]: Start isEmpty. Operand 509 states and 518 transitions. [2019-05-23 09:22:01,191 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 7 [2019-05-23 09:22:01,191 INFO L146 ILogger]: Found error trace [2019-05-23 09:22:01,191 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1, 1] [2019-05-23 09:22:01,193 INFO L146 ILogger]: === Iteration 7 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT]=== [2019-05-23 09:22:01,193 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 09:22:01,194 INFO L146 ILogger]: Analyzing trace with hash -1588400763, now seen corresponding path program 1 times [2019-05-23 09:22:01,195 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 09:22:01,198 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 09:22:01,198 WARN L146 ILogger]: Trace formula consists of 8 conjuncts, 4 conjunts are in the unsatisfiable core [2019-05-23 09:22:01,199 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 09:22:01,318 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 09:22:01,318 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 09:22:01,318 INFO L146 ILogger]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-05-23 09:22:01,318 INFO L146 ILogger]: Interpolant automaton has 5 states [2019-05-23 09:22:01,319 INFO L146 ILogger]: Constructing interpolant automaton starting with 5 interpolants. [2019-05-23 09:22:01,319 INFO L146 ILogger]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-05-23 09:22:01,319 INFO L146 ILogger]: Start difference. First operand 509 states and 518 transitions. Second operand 5 states. [2019-05-23 09:22:01,373 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 09:22:01,373 INFO L146 ILogger]: Finished difference Result 508 states and 517 transitions. [2019-05-23 09:22:01,374 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-05-23 09:22:01,374 INFO L146 ILogger]: Start accepts. Automaton has 5 states. Word has length 6 [2019-05-23 09:22:01,374 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 09:22:01,377 INFO L146 ILogger]: With dead ends: 508 [2019-05-23 09:22:01,377 INFO L146 ILogger]: Without dead ends: 508 [2019-05-23 09:22:01,377 INFO L146 ILogger]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-05-23 09:22:01,378 INFO L146 ILogger]: Start minimizeSevpa. Operand 508 states. [2019-05-23 09:22:01,385 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 508 to 508. [2019-05-23 09:22:01,385 INFO L146 ILogger]: Start removeUnreachable. Operand 508 states. [2019-05-23 09:22:01,387 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 508 states to 508 states and 517 transitions. [2019-05-23 09:22:01,387 INFO L146 ILogger]: Start accepts. Automaton has 508 states and 517 transitions. Word has length 6 [2019-05-23 09:22:01,387 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 09:22:01,387 INFO L146 ILogger]: Abstraction has 508 states and 517 transitions. [2019-05-23 09:22:01,387 INFO L146 ILogger]: Interpolant automaton has 5 states. [2019-05-23 09:22:01,387 INFO L146 ILogger]: Start isEmpty. Operand 508 states and 517 transitions. [2019-05-23 09:22:01,388 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 8 [2019-05-23 09:22:01,388 INFO L146 ILogger]: Found error trace [2019-05-23 09:22:01,388 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2019-05-23 09:22:01,390 INFO L146 ILogger]: === Iteration 8 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT]=== [2019-05-23 09:22:01,391 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 09:22:01,391 INFO L146 ILogger]: Analyzing trace with hash 673596666, now seen corresponding path program 1 times [2019-05-23 09:22:01,392 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 09:22:01,395 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 09:22:01,396 INFO L146 ILogger]: Trace formula consists of 9 conjuncts, 4 conjunts are in the unsatisfiable core [2019-05-23 09:22:01,396 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 09:22:01,622 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 09:22:01,622 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 09:22:01,623 INFO L146 ILogger]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-05-23 09:22:01,624 INFO L146 ILogger]: Interpolant automaton has 5 states [2019-05-23 09:22:01,624 INFO L146 ILogger]: Constructing interpolant automaton starting with 5 interpolants. [2019-05-23 09:22:01,625 INFO L146 ILogger]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-05-23 09:22:01,626 INFO L146 ILogger]: Start difference. First operand 508 states and 517 transitions. Second operand 5 states. [2019-05-23 09:22:02,116 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 09:22:02,117 INFO L146 ILogger]: Finished difference Result 507 states and 516 transitions. [2019-05-23 09:22:02,117 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-05-23 09:22:02,118 INFO L146 ILogger]: Start accepts. Automaton has 5 states. Word has length 7 [2019-05-23 09:22:02,118 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 09:22:02,120 INFO L146 ILogger]: With dead ends: 507 [2019-05-23 09:22:02,120 INFO L146 ILogger]: Without dead ends: 507 [2019-05-23 09:22:02,121 INFO L146 ILogger]: 0 DeclaredPredicates, 8 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-05-23 09:22:02,123 INFO L146 ILogger]: Start minimizeSevpa. Operand 507 states. [2019-05-23 09:22:02,129 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 507 to 507. [2019-05-23 09:22:02,129 INFO L146 ILogger]: Start removeUnreachable. Operand 507 states. [2019-05-23 09:22:02,131 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 507 states to 507 states and 516 transitions. [2019-05-23 09:22:02,131 INFO L146 ILogger]: Start accepts. Automaton has 507 states and 516 transitions. Word has length 7 [2019-05-23 09:22:02,131 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 09:22:02,131 INFO L146 ILogger]: Abstraction has 507 states and 516 transitions. [2019-05-23 09:22:02,132 INFO L146 ILogger]: Interpolant automaton has 5 states. [2019-05-23 09:22:02,132 INFO L146 ILogger]: Start isEmpty. Operand 507 states and 516 transitions. [2019-05-23 09:22:02,132 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 8 [2019-05-23 09:22:02,132 INFO L146 ILogger]: Found error trace [2019-05-23 09:22:02,133 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2019-05-23 09:22:02,134 INFO L146 ILogger]: === Iteration 9 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT]=== [2019-05-23 09:22:02,138 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 09:22:02,139 INFO L146 ILogger]: Analyzing trace with hash 1440708068, now seen corresponding path program 1 times [2019-05-23 09:22:02,140 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 09:22:02,143 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 09:22:02,144 INFO L146 ILogger]: Trace formula consists of 9 conjuncts, 3 conjunts are in the unsatisfiable core [2019-05-23 09:22:02,145 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 09:22:02,262 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 09:22:02,262 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 09:22:02,263 INFO L146 ILogger]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2019-05-23 09:22:02,263 INFO L146 ILogger]: Interpolant automaton has 4 states [2019-05-23 09:22:02,263 INFO L146 ILogger]: Constructing interpolant automaton starting with 4 interpolants. [2019-05-23 09:22:02,263 INFO L146 ILogger]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2019-05-23 09:22:02,264 INFO L146 ILogger]: Start difference. First operand 507 states and 516 transitions. Second operand 4 states. [2019-05-23 09:22:02,432 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 09:22:02,432 INFO L146 ILogger]: Finished difference Result 506 states and 515 transitions. [2019-05-23 09:22:02,433 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2019-05-23 09:22:02,433 INFO L146 ILogger]: Start accepts. Automaton has 4 states. Word has length 7 [2019-05-23 09:22:02,434 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 09:22:02,436 INFO L146 ILogger]: With dead ends: 506 [2019-05-23 09:22:02,437 INFO L146 ILogger]: Without dead ends: 506 [2019-05-23 09:22:02,437 INFO L146 ILogger]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2019-05-23 09:22:02,438 INFO L146 ILogger]: Start minimizeSevpa. Operand 506 states. [2019-05-23 09:22:02,445 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 506 to 506. [2019-05-23 09:22:02,445 INFO L146 ILogger]: Start removeUnreachable. Operand 506 states. [2019-05-23 09:22:02,447 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 506 states to 506 states and 515 transitions. [2019-05-23 09:22:02,447 INFO L146 ILogger]: Start accepts. Automaton has 506 states and 515 transitions. Word has length 7 [2019-05-23 09:22:02,447 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 09:22:02,447 INFO L146 ILogger]: Abstraction has 506 states and 515 transitions. [2019-05-23 09:22:02,448 INFO L146 ILogger]: Interpolant automaton has 4 states. [2019-05-23 09:22:02,448 INFO L146 ILogger]: Start isEmpty. Operand 506 states and 515 transitions. [2019-05-23 09:22:02,448 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 10 [2019-05-23 09:22:02,448 INFO L146 ILogger]: Found error trace [2019-05-23 09:22:02,449 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-05-23 09:22:02,451 INFO L146 ILogger]: === Iteration 10 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT]=== [2019-05-23 09:22:02,451 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 09:22:02,452 INFO L146 ILogger]: Analyzing trace with hash 1540994566, now seen corresponding path program 1 times [2019-05-23 09:22:02,453 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 09:22:02,460 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 09:22:02,461 INFO L146 ILogger]: Trace formula consists of 11 conjuncts, 4 conjunts are in the unsatisfiable core [2019-05-23 09:22:02,461 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 09:22:02,556 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 09:22:02,557 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 09:22:02,557 INFO L146 ILogger]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2019-05-23 09:22:02,557 INFO L146 ILogger]: Interpolant automaton has 5 states [2019-05-23 09:22:02,558 INFO L146 ILogger]: Constructing interpolant automaton starting with 5 interpolants. [2019-05-23 09:22:02,558 INFO L146 ILogger]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2019-05-23 09:22:02,558 INFO L146 ILogger]: Start difference. First operand 506 states and 515 transitions. Second operand 5 states. [2019-05-23 09:22:02,918 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 09:22:02,919 INFO L146 ILogger]: Finished difference Result 505 states and 514 transitions. [2019-05-23 09:22:02,919 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2019-05-23 09:22:02,919 INFO L146 ILogger]: Start accepts. Automaton has 5 states. Word has length 9 [2019-05-23 09:22:02,919 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 09:22:02,922 INFO L146 ILogger]: With dead ends: 505 [2019-05-23 09:22:02,922 INFO L146 ILogger]: Without dead ends: 505 [2019-05-23 09:22:02,922 INFO L146 ILogger]: 0 DeclaredPredicates, 10 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2019-05-23 09:22:02,924 INFO L146 ILogger]: Start minimizeSevpa. Operand 505 states. [2019-05-23 09:22:02,931 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 505 to 505. [2019-05-23 09:22:02,931 INFO L146 ILogger]: Start removeUnreachable. Operand 505 states. [2019-05-23 09:22:02,933 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 505 states to 505 states and 514 transitions. [2019-05-23 09:22:02,933 INFO L146 ILogger]: Start accepts. Automaton has 505 states and 514 transitions. Word has length 9 [2019-05-23 09:22:02,933 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 09:22:02,933 INFO L146 ILogger]: Abstraction has 505 states and 514 transitions. [2019-05-23 09:22:02,933 INFO L146 ILogger]: Interpolant automaton has 5 states. [2019-05-23 09:22:02,933 INFO L146 ILogger]: Start isEmpty. Operand 505 states and 514 transitions. [2019-05-23 09:22:02,934 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 11 [2019-05-23 09:22:02,934 INFO L146 ILogger]: Found error trace [2019-05-23 09:22:02,934 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-05-23 09:22:02,936 INFO L146 ILogger]: === Iteration 11 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT]=== [2019-05-23 09:22:02,936 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 09:22:02,936 INFO L146 ILogger]: Analyzing trace with hash -1134431000, now seen corresponding path program 1 times [2019-05-23 09:22:02,937 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 09:22:02,941 INFO L146 ILogger]: Conjunction of SSA is unsat [2019-05-23 09:22:02,942 INFO L146 ILogger]: Trace formula consists of 12 conjuncts, 5 conjunts are in the unsatisfiable core [2019-05-23 09:22:02,942 INFO L146 ILogger]: Computing forward predicates... [2019-05-23 09:22:03,073 INFO L146 ILogger]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2019-05-23 09:22:03,073 INFO L146 ILogger]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2019-05-23 09:22:03,073 INFO L146 ILogger]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2019-05-23 09:22:03,074 INFO L146 ILogger]: Interpolant automaton has 6 states [2019-05-23 09:22:03,074 INFO L146 ILogger]: Constructing interpolant automaton starting with 6 interpolants. [2019-05-23 09:22:03,075 INFO L146 ILogger]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2019-05-23 09:22:03,075 INFO L146 ILogger]: Start difference. First operand 505 states and 514 transitions. Second operand 6 states. [2019-05-23 09:22:03,321 INFO L146 ILogger]: Subtrahend was deterministic. Have not used determinization. [2019-05-23 09:22:03,322 INFO L146 ILogger]: Finished difference Result 504 states and 513 transitions. [2019-05-23 09:22:03,322 INFO L146 ILogger]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2019-05-23 09:22:03,322 INFO L146 ILogger]: Start accepts. Automaton has 6 states. Word has length 10 [2019-05-23 09:22:03,322 INFO L146 ILogger]: Finished accepts. some prefix is accepted. [2019-05-23 09:22:03,325 INFO L146 ILogger]: With dead ends: 504 [2019-05-23 09:22:03,325 INFO L146 ILogger]: Without dead ends: 494 [2019-05-23 09:22:03,325 INFO L146 ILogger]: 0 DeclaredPredicates, 12 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2019-05-23 09:22:03,326 INFO L146 ILogger]: Start minimizeSevpa. Operand 494 states. [2019-05-23 09:22:03,334 INFO L146 ILogger]: Finished minimizeSevpa. Reduced states from 494 to 494. [2019-05-23 09:22:03,334 INFO L146 ILogger]: Start removeUnreachable. Operand 494 states. [2019-05-23 09:22:03,335 INFO L146 ILogger]: Finished removeUnreachable. Reduced from 494 states to 494 states and 504 transitions. [2019-05-23 09:22:03,336 INFO L146 ILogger]: Start accepts. Automaton has 494 states and 504 transitions. Word has length 10 [2019-05-23 09:22:03,336 INFO L146 ILogger]: Finished accepts. word is rejected. [2019-05-23 09:22:03,336 INFO L146 ILogger]: Abstraction has 494 states and 504 transitions. [2019-05-23 09:22:03,336 INFO L146 ILogger]: Interpolant automaton has 6 states. [2019-05-23 09:22:03,336 INFO L146 ILogger]: Start isEmpty. Operand 494 states and 504 transitions. [2019-05-23 09:22:03,337 INFO L146 ILogger]: Finished isEmpty. Found accepting run of length 13 [2019-05-23 09:22:03,337 INFO L146 ILogger]: Found error trace [2019-05-23 09:22:03,337 INFO L146 ILogger]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2019-05-23 09:22:03,339 INFO L146 ILogger]: === Iteration 12 === [void$SimpleFrame2Cons$3$$la$init$ra$$4885Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$actionPerformed$4553Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err29ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err4ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err9ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err16ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err6ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err11ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err27ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err3ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err14ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$$la$init$ra$$1805Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$$la$init$ra$$1802Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err25ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err19ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err29ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err9ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err11ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err14ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err15ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err20ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err33ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err8ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err5ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err28ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err16ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err12ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err6ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$1$run$1803Err7ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err18ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err22ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err4ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err26ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err27ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err30ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err23ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err35ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err24ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err32ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err17ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err34ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err31ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err21ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err13ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$1$run$1803Err10ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$$la$init$ra$$4887Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$4$actionPerformed$4888Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, void$SimpleFrame2Cons$main$1804Err2ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$main$1804Err0ASSERT_VIOLATIONASSERT, void$SimpleFrame2Cons$2$$la$init$ra$$4552Err0ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr2ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr3ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr8ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr5ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr4ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr0ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr6ASSERT_VIOLATIONASSERT, $EFG_ProcedureErr1ASSERT_VIOLATIONPRE_CONDITIONandASSERT, $EFG_ProcedureErr7ASSERT_VIOLATIONPRE_CONDITIONandASSERT]=== [2019-05-23 09:22:03,339 INFO L146 ILogger]: Initialized classic predicate unifier [2019-05-23 09:22:03,340 INFO L146 ILogger]: Analyzing trace with hash -118089624, now seen corresponding path program 1 times [2019-05-23 09:22:03,341 INFO L146 ILogger]: Using refinement strategy FixedRefinementStrategy [2019-05-23 09:22:03,347 INFO L146 ILogger]: Conjunction of SSA is sat [2019-05-23 09:22:03,356 INFO L146 ILogger]: Conjunction of SSA is sat [2019-05-23 09:22:03,373 INFO L146 ILogger]: Counterexample might be feasible [2019-05-23 09:22:03,387 INFO L146 ILogger]: Adding new model GuiTestExampleUnsafe.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 23.05 09:22:03 BoogieIcfgContainer [2019-05-23 09:22:03,388 INFO L146 ILogger]: ------------------------ END TraceAbstraction---------------------------- [2019-05-23 09:22:03,390 INFO L146 ILogger]: Toolchain (without parser) took 6190.12 ms. Allocated memory was 133.2 MB in the beginning and 196.1 MB in the end (delta: 62.9 MB). Free memory was 107.8 MB in the beginning and 65.0 MB in the end (delta: 42.8 MB). Peak memory consumption was 105.7 MB. Max. memory is 7.1 GB. [2019-05-23 09:22:03,391 INFO L146 ILogger]: Boogie PL CUP Parser took 0.20 ms. Allocated memory is still 133.2 MB. Free memory is still 110.3 MB. There was no memory consumed. Max. memory is 7.1 GB. [2019-05-23 09:22:03,392 INFO L146 ILogger]: Boogie Procedure Inliner took 84.91 ms. Allocated memory is still 133.2 MB. Free memory was 107.8 MB in the beginning and 103.9 MB in the end (delta: 3.9 MB). Peak memory consumption was 3.9 MB. Max. memory is 7.1 GB. [2019-05-23 09:22:03,393 INFO L146 ILogger]: Boogie Preprocessor took 94.73 ms. Allocated memory is still 133.2 MB. Free memory was 103.9 MB in the beginning and 101.8 MB in the end (delta: 2.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 7.1 GB. [2019-05-23 09:22:03,394 INFO L146 ILogger]: RCFGBuilder took 2250.38 ms. Allocated memory was 133.2 MB in the beginning and 171.4 MB in the end (delta: 38.3 MB). Free memory was 101.8 MB in the beginning and 102.6 MB in the end (delta: -767.7 kB). Peak memory consumption was 48.8 MB. Max. memory is 7.1 GB. [2019-05-23 09:22:03,395 INFO L146 ILogger]: TraceAbstraction took 3754.66 ms. Allocated memory was 171.4 MB in the beginning and 196.1 MB in the end (delta: 24.6 MB). Free memory was 102.6 MB in the beginning and 65.0 MB in the end (delta: 37.6 MB). Peak memory consumption was 62.2 MB. Max. memory is 7.1 GB. [2019-05-23 09:22:03,399 INFO L146 ILogger]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * Boogie PL CUP Parser took 0.20 ms. Allocated memory is still 133.2 MB. Free memory is still 110.3 MB. There was no memory consumed. Max. memory is 7.1 GB. * Boogie Procedure Inliner took 84.91 ms. Allocated memory is still 133.2 MB. Free memory was 107.8 MB in the beginning and 103.9 MB in the end (delta: 3.9 MB). Peak memory consumption was 3.9 MB. Max. memory is 7.1 GB. * Boogie Preprocessor took 94.73 ms. Allocated memory is still 133.2 MB. Free memory was 103.9 MB in the beginning and 101.8 MB in the end (delta: 2.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 7.1 GB. * RCFGBuilder took 2250.38 ms. Allocated memory was 133.2 MB in the beginning and 171.4 MB in the end (delta: 38.3 MB). Free memory was 101.8 MB in the beginning and 102.6 MB in the end (delta: -767.7 kB). Peak memory consumption was 48.8 MB. Max. memory is 7.1 GB. * TraceAbstraction took 3754.66 ms. Allocated memory was 171.4 MB in the beginning and 196.1 MB in the end (delta: 24.6 MB). Free memory was 102.6 MB in the beginning and 65.0 MB in the end (delta: 37.6 MB). Peak memory consumption was 62.2 MB. Max. memory is 7.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 481]: assertion can be violated assertion can be violated We found a FailurePath: [L462-L464] requires void$SimpleFrame2Cons$2$actionPerformed$4553$__this != $null; [L474] r098 := void$SimpleFrame2Cons$2$actionPerformed$4553$__this; [L476] r199 := void$SimpleFrame2Cons$2$actionPerformed$4553$param_0; [L478] $r2102 := SimpleFrame2Cons$SimpleFrame2Cons$2$this$0711; [L390] r083 := $param_0; [L392] $r185 := javax.swing.JButton$SimpleFrame2Cons$event2227; [L394] __ret := $r185; [L481] assert $r3103 != $null; - StatisticsResult: Ultimate Automizer benchmark data CFG has 16 procedures, 645 locations, 87 error locations. UNSAFE Result, 3.6s OverallTime, 12 OverallIterations, 1 TraceHistogramMax, 1.9s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 5874 SDtfs, 1503 SDslu, 12881 SDs, 0 SdLazy, 82 SolverSat, 11 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.7s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 71 GetRequests, 28 SyntacticMatches, 0 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.9s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=645occurred in iteration=0, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.2s AutomataMinimizationTime, 11 MinimizatonAttempts, 0 StatesRemovedByMinimization, 0 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.0s SatisfiabilityAnalysisTime, 1.1s InterpolantComputationTime, 78 NumberOfCodeBlocks, 78 NumberOfCodeBlocksAsserted, 12 NumberOfCheckSat, 55 ConstructedInterpolants, 0 QuantifiedInterpolants, 1026 SizeOfPredicates, 16 NumberOfNonLiveVariables, 88 ConjunctsInSsa, 38 ConjunctsInUnsatCore, 11 InterpolantComputations, 11 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Received shutdown request...