env GraphEmpireOG.Timeout=-1 benchexec/../run-test.sh Library-ProofsTest 'de.uni_freiburg.informatik.ultimate.lib.proofs.owickigries.OGProofProducerTest$GraphEmpireOG' NoDataRace.18_read_write_lock.ats false -------------------------------------------------------------------------------- Thanks for using JUnit! Support its development at https://junit.org/sponsoring Test plan execution started. Number of static tests: 1 ╷ ├─ JUnit Jupiter └─ JUnit Jupiter finished after 6 ms. ├─ JUnit Vintage │ ├─ GraphEmpireOG │ │ ├─ NoDataRace_18_read_write_lock_ats │ │ │ tags: [] │ │ │ uniqueId: [engine:junit-vintage]/[runner:de.uni_freiburg.informatik.ultimate.lib.proofs.owickigries.OGProofProducerTest$GraphEmpireOG]/[test:NoDataRace_18_read_write_lock_ats(de.uni_freiburg.informatik.ultimate.lib.proofs.owickigries.OGProofProducerTest$GraphEmpireOG)] │ │ │ parent: [engine:junit-vintage]/[runner:de.uni_freiburg.informatik.ultimate.lib.proofs.owickigries.OGProofProducerTest$GraphEmpireOG] │ │ │ source: ClassSource [className = 'de.uni_freiburg.informatik.ultimate.lib.proofs.owickigries.OGProofProducerTest$GraphEmpireOG', filePosition = null] [WARN]: Using environment timeout: -1ms [INFO]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/adds/z3 [INFO]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/adds/z3 SMTLIB2_COMPLIANT=true -t:1000 -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) [INFO]: [MP /storage/repos/ultimate/releaseScripts/default/adds/z3 SMTLIB2_COMPLIANT=true -t:1000 -memory:2024 -smt2 -in (1)] Waiting until timeout for monitored process [INFO]: Initialized classic predicate unifier [INFO]: Initialized classic predicate unifier [INFO]: Initialized classic predicate unifier [INFO]: Number of proof automata: 3 [INFO]: 60 / 77 letters are loopers in proof 0 [INFO]: 53 / 77 letters are loopers in proof 1 [INFO]: 53 / 77 letters are loopers in proof 2 [INFO]: Loopers in proof automata: min=53, max=60, median=53 [INFO]: Start finitePrefix. Operand will be constructed on-demand [INFO]: 0/52 cut-off events. [INFO]: For 19/20 co-relation queries the response was YES. [INFO]: Finished finitePrefix Result has 97 conditions, 52 events. 0/52 cut-off events. For 19/20 co-relation queries the response was YES. Maximal size of possible extension queue 2. Compared 17 event pairs, 0 based on Foata normal form. 5/56 useless extension candidates. Maximal degree in co-relation 0. Up to 15 conditions per place. [INFO]: OwickiGriesTestSuite setup time: 582ms [INFO]: Constructing Owicki-Gries proof for Petri program that has 79 places, 77 transitions, 158 flow. [INFO]: Computed Owicki-Gries annotation with 9 ghost variables, 16 ghost updates, and overall size 4529 [INFO]: Computed Owicki-Gries annotation with 9 ghost variables, 16 ghost updates, and overall size 4529 Assertions: l50 : 1#false l52 : 2#false l51 : 27#(and (or (and (not |v_[l49]_1|) |v_[l7, l10, l34, l72]_1| |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|) (and (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) |v_[l73, l61]_1| |v_[l51]_1|) (and (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l73, l61]_1|) |v_[l24]_1| |v_[l51]_1|) (and |v_[l31, l8]_1| (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|) (and (not |v_[l49]_1|) (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) |v_[l73, l61]_1| |v_[l51]_1|)) (or (not (and (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l73, l61]_1|) |v_[l24]_1| |v_[l51]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)))) (or (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)) (not (and (not |v_[l49]_1|) (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) |v_[l73, l61]_1| |v_[l51]_1|))) (or (not (and |v_[l31, l8]_1| (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (= |thr1Thread1of1ForFork0_#t~nondet2| |#race~x~0|) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)))) (or (not (and (not |v_[l49]_1|) |v_[l7, l10, l34, l72]_1| |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)))) |v_[l51]_1|) l10 : 35#(and (not |v_[l49]_1|) |v_[l7, l10, l34, l72]_1| (or (not (and (not |v_[l49]_1|) |v_[l7, l10, l34, l72]_1| |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)))) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|) l54 : 43#(and (not |v_[l49]_1|) (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1| (or (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)) (not (and (not |v_[l49]_1|) (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) |v_[l73, l61]_1| |v_[l51]_1|))) (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) |v_[l73, l61]_1| |v_[l51]_1|) l53 : 60#(and (or (not (and (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l73, l61]_1|) |v_[l24]_1| |v_[l51]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)))) (or (and (not |v_[l49]_1|) |v_[l7, l10, l34, l72]_1| |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|) (and (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) |v_[l73, l61]_1| |v_[l51]_1|) (and (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l73, l61]_1|) |v_[l24]_1| |v_[l51]_1|) (and |v_[l31, l8]_1| (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|)) (or (not (and |v_[l31, l8]_1| (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (= |thr1Thread1of1ForFork0_#t~nondet2| |#race~x~0|) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)))) (or (not (and (not |v_[l49]_1|) |v_[l7, l10, l34, l72]_1| |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)))) |v_[l15, l38, l53, l21, l11, l45, l64]_1|) l12 : 68#(and (not |v_[l49]_1|) (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1| (or (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)) (not (and (not |v_[l49]_1|) (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) |v_[l73, l61]_1| |v_[l51]_1|))) (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) |v_[l73, l61]_1| |v_[l51]_1|) l56 : 69#false l11 : 86#(and (or (not (and (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l73, l61]_1|) |v_[l24]_1| |v_[l51]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)))) (or (and (not |v_[l49]_1|) |v_[l7, l10, l34, l72]_1| |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|) (and (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) |v_[l73, l61]_1| |v_[l51]_1|) (and (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l73, l61]_1|) |v_[l24]_1| |v_[l51]_1|) (and |v_[l31, l8]_1| (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|)) (or (not (and |v_[l31, l8]_1| (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (= |thr1Thread1of1ForFork0_#t~nondet2| |#race~x~0|) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)))) (or (not (and (not |v_[l49]_1|) |v_[l7, l10, l34, l72]_1| |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)))) |v_[l15, l38, l53, l21, l11, l45, l64]_1|) l55 : 95#(and (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l51]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l49]_1|) l14 : 103#(and (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l51]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l49]_1|) l58 : 104#false l13 : 112#(and (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l51]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l49]_1|) l57 : 120#(and (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l51]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l49]_1|) l16 : 128#(and (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l51]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l49]_1|) l15 : 145#(and (or (not (and (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l73, l61]_1|) |v_[l24]_1| |v_[l51]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)))) (or (and (not |v_[l49]_1|) |v_[l7, l10, l34, l72]_1| |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|) (and (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) |v_[l73, l61]_1| |v_[l51]_1|) (and (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l73, l61]_1|) |v_[l24]_1| |v_[l51]_1|) (and |v_[l31, l8]_1| (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|)) (or (not (and |v_[l31, l8]_1| (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (= |thr1Thread1of1ForFork0_#t~nondet2| |#race~x~0|) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)))) (or (not (and (not |v_[l49]_1|) |v_[l7, l10, l34, l72]_1| |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)))) |v_[l15, l38, l53, l21, l11, l45, l64]_1|) l59 : 146#false l18 : 147#false l17 : 155#(and (not |v_[l49]_1|) (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1| (or (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)) (not (and (not |v_[l49]_1|) (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) |v_[l73, l61]_1| |v_[l51]_1|))) (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) |v_[l73, l61]_1| |v_[l51]_1|) l19 : 163#(and (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l51]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l49]_1|) l61 : 174#(and (or (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)) (not (and (not |v_[l49]_1|) (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) |v_[l73, l61]_1| |v_[l51]_1|))) (or (and (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) |v_[l73, l61]_1| |v_[l51]_1|) (and (not |v_[l49]_1|) (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) |v_[l73, l61]_1| |v_[l51]_1|)) |v_[l73, l61]_1|) l60 : 182#(and (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l51]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l49]_1|) l63 : 190#(and (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l51]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l49]_1|) l62 : 198#(and (not |v_[l49]_1|) (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1| (or (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)) (not (and (not |v_[l49]_1|) (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) |v_[l73, l61]_1| |v_[l51]_1|))) (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) |v_[l73, l61]_1| |v_[l51]_1|) l21 : 215#(and (or (not (and (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l73, l61]_1|) |v_[l24]_1| |v_[l51]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)))) (or (and (not |v_[l49]_1|) |v_[l7, l10, l34, l72]_1| |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|) (and (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) |v_[l73, l61]_1| |v_[l51]_1|) (and (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l73, l61]_1|) |v_[l24]_1| |v_[l51]_1|) (and |v_[l31, l8]_1| (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|)) (or (not (and |v_[l31, l8]_1| (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (= |thr1Thread1of1ForFork0_#t~nondet2| |#race~x~0|) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)))) (or (not (and (not |v_[l49]_1|) |v_[l7, l10, l34, l72]_1| |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)))) |v_[l15, l38, l53, l21, l11, l45, l64]_1|) l65 : 216#false l20 : 224#(and (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l51]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l49]_1|) l64 : 241#(and (or (not (and (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l73, l61]_1|) |v_[l24]_1| |v_[l51]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)))) (or (and (not |v_[l49]_1|) |v_[l7, l10, l34, l72]_1| |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|) (and (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) |v_[l73, l61]_1| |v_[l51]_1|) (and (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l73, l61]_1|) |v_[l24]_1| |v_[l51]_1|) (and |v_[l31, l8]_1| (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|)) (or (not (and |v_[l31, l8]_1| (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (= |thr1Thread1of1ForFork0_#t~nondet2| |#race~x~0|) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)))) (or (not (and (not |v_[l49]_1|) |v_[l7, l10, l34, l72]_1| |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)))) |v_[l15, l38, l53, l21, l11, l45, l64]_1|) l23 : 249#(and (not |v_[l49]_1|) (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1| (or (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)) (not (and (not |v_[l49]_1|) (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) |v_[l73, l61]_1| |v_[l51]_1|))) (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) |v_[l73, l61]_1| |v_[l51]_1|) l67 : 250#false l22 : 251#false l66 : 252#false l25 : 260#(and (not |v_[l49]_1|) (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1| (or (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)) (not (and (not |v_[l49]_1|) (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) |v_[l73, l61]_1| |v_[l51]_1|))) (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) |v_[l73, l61]_1| |v_[l51]_1|) l69 : 261#false l24 : 269#(and (or (not (and (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l73, l61]_1|) |v_[l24]_1| |v_[l51]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)))) (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l73, l61]_1|) |v_[l24]_1| |v_[l51]_1|) l68 : 270#false l27 : 271#false l26 : 272#false l29 : 280#(and (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l51]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l49]_1|) l28 : 281#false l0 : 282#false l70 : 290#(and (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l51]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l49]_1|) l1 : 298#(and (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l51]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l49]_1|) l2 : 306#(and (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l51]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l49]_1|) l72 : 314#(and (not |v_[l49]_1|) |v_[l7, l10, l34, l72]_1| (or (not (and (not |v_[l49]_1|) |v_[l7, l10, l34, l72]_1| |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)))) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|) l3 : 322#(and (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l51]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l49]_1|) l71 : 330#(and (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l51]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l49]_1|) l4 : 338#(and (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l51]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l49]_1|) l30 : 339#false l74 : 340#false l5 : 348#(and (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l51]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l49]_1|) l73 : 359#(and (or (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)) (not (and (not |v_[l49]_1|) (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) |v_[l73, l61]_1| |v_[l51]_1|))) (or (and (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) |v_[l73, l61]_1| |v_[l51]_1|) (and (not |v_[l49]_1|) (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) |v_[l73, l61]_1| |v_[l51]_1|)) |v_[l73, l61]_1|) l6 : 360#false l32 : 368#(and (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l51]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l49]_1|) l76 : 376#(and (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l51]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l49]_1|) l7 : 384#(and (not |v_[l49]_1|) |v_[l7, l10, l34, l72]_1| (or (not (and (not |v_[l49]_1|) |v_[l7, l10, l34, l72]_1| |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)))) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|) l31 : 392#(and |v_[l31, l8]_1| (not |v_[l49]_1|) (or (not (and |v_[l31, l8]_1| (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (= |thr1Thread1of1ForFork0_#t~nondet2| |#race~x~0|) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)))) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|) l75 : 400#(and (not |v_[l49]_1|) (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1| (or (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)) (not (and (not |v_[l49]_1|) (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) |v_[l73, l61]_1| |v_[l51]_1|))) (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) |v_[l73, l61]_1| |v_[l51]_1|) l8 : 408#(and |v_[l31, l8]_1| (not |v_[l49]_1|) (or (not (and |v_[l31, l8]_1| (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (= |thr1Thread1of1ForFork0_#t~nondet2| |#race~x~0|) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)))) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|) l34 : 416#(and (not |v_[l49]_1|) |v_[l7, l10, l34, l72]_1| (or (not (and (not |v_[l49]_1|) |v_[l7, l10, l34, l72]_1| |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)))) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|) l78 : 424#(and (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l51]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l49]_1|) l9 : 432#(and (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l51]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l49]_1|) l33 : 440#(and (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l51]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l49]_1|) l77 : 448#(and (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l51]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l49]_1|) l36 : 456#(and (not |v_[l49]_1|) (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1| (or (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)) (not (and (not |v_[l49]_1|) (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) |v_[l73, l61]_1| |v_[l51]_1|))) (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) |v_[l73, l61]_1| |v_[l51]_1|) l35 : 464#(and (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l51]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l49]_1|) l38 : 481#(and (or (not (and (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l73, l61]_1|) |v_[l24]_1| |v_[l51]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)))) (or (and (not |v_[l49]_1|) |v_[l7, l10, l34, l72]_1| |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|) (and (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) |v_[l73, l61]_1| |v_[l51]_1|) (and (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l73, l61]_1|) |v_[l24]_1| |v_[l51]_1|) (and |v_[l31, l8]_1| (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|)) (or (not (and |v_[l31, l8]_1| (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (= |thr1Thread1of1ForFork0_#t~nondet2| |#race~x~0|) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)))) (or (not (and (not |v_[l49]_1|) |v_[l7, l10, l34, l72]_1| |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)))) |v_[l15, l38, l53, l21, l11, l45, l64]_1|) l37 : 489#(and (not |v_[l49]_1|) (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1| (or (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)) (not (and (not |v_[l49]_1|) (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) |v_[l73, l61]_1| |v_[l51]_1|))) (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) |v_[l73, l61]_1| |v_[l51]_1|) l39 : 490#false l41 : 498#(and (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l51]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l49]_1|) l40 : 499#false l43 : 500#false l42 : 501#false l45 : 518#(and (or (not (and (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l73, l61]_1|) |v_[l24]_1| |v_[l51]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)))) (or (and (not |v_[l49]_1|) |v_[l7, l10, l34, l72]_1| |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|) (and (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) |v_[l73, l61]_1| |v_[l51]_1|) (and (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l73, l61]_1|) |v_[l24]_1| |v_[l51]_1|) (and |v_[l31, l8]_1| (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|)) (or (not (and |v_[l31, l8]_1| (not |v_[l49]_1|) |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (= |thr1Thread1of1ForFork0_#t~nondet2| |#race~x~0|) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)))) (or (not (and (not |v_[l49]_1|) |v_[l7, l10, l34, l72]_1| |v_[l15, l38, l53, l21, l11, l45, l64]_1| (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l51]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)))) |v_[l15, l38, l53, l21, l11, l45, l64]_1|) l44 : 526#(and (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l51]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l49]_1|) l47 : 534#(and (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l51]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l49]_1|) l46 : 542#(and (not |v_[l49]_1|) (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1| (or (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)) (not (and (not |v_[l49]_1|) (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) |v_[l73, l61]_1| |v_[l51]_1|))) (not |v_[l7, l10, l34, l72]_1|) (not |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) |v_[l73, l61]_1| |v_[l51]_1|) l49 : 550#(and (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l51]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l49]_1|) l48 : 558#(and (not |v_[l15, l38, l53, l21, l11, l45, l64]_1|) |v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1| (not |v_[l7, l10, l34, l72]_1|) (not |v_[l51]_1|) (not |v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1|) (not |v_[l31, l8]_1|) (not |v_[l24]_1|) (not |v_[l73, l61]_1|) |v_[l49]_1|) Ghost Variables (and initial values): v_[l51]_1 : false v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1 : true v_[l7, l10, l34, l72]_1 : false v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1 : false v_[l31, l8]_1 : false v_[l49]_1 : true v_[l15, l38, l53, l21, l11, l45, l64]_1 : false v_[l24]_1 : false v_[l73, l61]_1 : false Ghost Updates: [69][64] : (v_[l31, l8]_1) := (false) [64][33] : (v_[l7, l10, l34, l72]_1, v_[l73, l61]_1) := (true, false) [28][34] : (v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1) := (false) [72][3] : (v_[l24]_1) := (false) [29][36] : (v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1) := (false) [71][40] : (v_[l31, l8]_1, v_[l24]_1) := (false, true) [34][43] : (v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1) := (false) [61][75] : (v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1) := (false) [68][14] : (v_[l7, l10, l34, l72]_1, v_[l31, l8]_1) := (false, true) [76][15] : (v_[l51]_1, v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1) := (false, false) [77][16] : (v_[l51]_1, v_[l77, l35, l41, l55, l14, l44, l47, l13, l57, l16, l48, l19, l60, l63, l20, l29, l70, l1, l2, l3, l71, l4, l5, l32, l76, l78, l9, l33]_1, v_[l49]_1, v_[l15, l38, l53, l21, l11, l45, l64]_1, v_[l73, l61]_1) := (true, false, false, true, true) [39][48] : (v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1, v_[l15, l38, l53, l21, l11, l45, l64]_1) := (true, false) [15][19] : (v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1) := (false) [43][52] : (v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1) := (false) [21][26] : (v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1) := (false) [51][61] : (v_[l36, l25, l17, l37, l54, l12, l62, l75, l46, l23]_1) := (true) [INFO]: EmpireComputation time [ms]: 34, EmpireComputation statistics: empire size: 6, empire law size: 74, empire annotation size: 80, number of regions: 9, Min number of regions per territory: 2, Max number of regions per territory: 3, Median number of regions per territory: 3, Min number of places per region: 1, Max number of places per region: 28, Median number of places per region: 2, Empire validity check time [ms]: 0, EmpireToOwickiGries time [ms]: 46, Owicki-Gries validity check time [ms]: 0 │ │ │ duration: 701 ms │ │ │ status: ✔ SUCCESSFUL │ └─ GraphEmpireOG finished after 707 ms. └─ JUnit Vintage finished after 719 ms. ├─ JUnit Platform Suite └─ JUnit Platform Suite finished after 0 ms. Test plan execution finished. Number of all tests: 1  Test run finished after 764 ms [ 4 containers found ] [ 0 containers skipped ] [ 4 containers started ] [ 0 containers aborted ] [ 4 containers successful ] [ 0 containers failed ] [ 1 tests found ] [ 0 tests skipped ] [ 1 tests started ] [ 0 tests aborted ] [ 1 tests successful ] [ 0 tests failed ]