env GraphEmpireOG.Timeout=-1 benchexec/../run-test.sh Library-ProofsTest 'de.uni_freiburg.informatik.ultimate.lib.proofs.owickigries.OGProofProducerTest$GraphEmpireOG' ReachSafety.18_read_write_lock.ats true -------------------------------------------------------------------------------- Thanks for using JUnit! Support its development at https://junit.org/sponsoring Test plan execution started. Number of static tests: 1 ╷ ├─ JUnit Jupiter └─ JUnit Jupiter finished after 6 ms. ├─ JUnit Vintage │ ├─ GraphEmpireOG │ │ ├─ ReachSafety_18_read_write_lock_ats │ │ │ tags: [] │ │ │ uniqueId: [engine:junit-vintage]/[runner:de.uni_freiburg.informatik.ultimate.lib.proofs.owickigries.OGProofProducerTest$GraphEmpireOG]/[test:ReachSafety_18_read_write_lock_ats(de.uni_freiburg.informatik.ultimate.lib.proofs.owickigries.OGProofProducerTest$GraphEmpireOG)] │ │ │ parent: [engine:junit-vintage]/[runner:de.uni_freiburg.informatik.ultimate.lib.proofs.owickigries.OGProofProducerTest$GraphEmpireOG] │ │ │ source: ClassSource [className = 'de.uni_freiburg.informatik.ultimate.lib.proofs.owickigries.OGProofProducerTest$GraphEmpireOG', filePosition = null] [WARN]: Using environment timeout: -1ms [INFO]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/adds/z3 [INFO]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/adds/z3 SMTLIB2_COMPLIANT=true -t:1000 -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) [INFO]: [MP /storage/repos/ultimate/releaseScripts/default/adds/z3 SMTLIB2_COMPLIANT=true -t:1000 -memory:2024 -smt2 -in (1)] Waiting until timeout for monitored process [INFO]: Initialized classic predicate unifier [INFO]: Initialized classic predicate unifier [INFO]: Initialized classic predicate unifier [INFO]: Start isDeterministic. Operand 8 states and 418 transitions. [INFO]: Finished isDeterministic. Operand is deterministic. [INFO]: Starting Floyd-Hoare check of an automaton with has 8 states, 8 states have (on average 52.25) internal successors, (418), 8 states have internal predecessors, (418), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [INFO]: Floyd-Hoare annotation has 418 edges. 418 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. 0 times interpolants missing. [INFO]: Start isDeterministic. Operand 3 states and 157 transitions. [INFO]: Finished isDeterministic. Operand is deterministic. [INFO]: Starting Floyd-Hoare check of an automaton with has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 3 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [INFO]: Floyd-Hoare annotation has 157 edges. 157 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. 0 times interpolants missing. [INFO]: Start isDeterministic. Operand 3 states and 154 transitions. [INFO]: Finished isDeterministic. Operand is deterministic. [INFO]: Starting Floyd-Hoare check of an automaton with has 3 states, 3 states have (on average 51.333333333333336) internal successors, (154), 3 states have internal predecessors, (154), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [INFO]: Floyd-Hoare annotation has 154 edges. 154 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. 0 times interpolants missing. [INFO]: Number of proof automata: 3 [INFO]: 48 / 65 letters are loopers in proof 0 [INFO]: 46 / 65 letters are loopers in proof 1 [INFO]: 46 / 65 letters are loopers in proof 2 [INFO]: Loopers in proof automata: min=46, max=48, median=46 [INFO]: Start finitePrefix. Operand will be constructed on-demand [INFO]: 2/50 cut-off events. [INFO]: For 19/19 co-relation queries the response was YES. [INFO]: Finished finitePrefix Result has 105 conditions, 50 events. 2/50 cut-off events. For 19/19 co-relation queries the response was YES. Maximal size of possible extension queue 3. Compared 23 event pairs, 2 based on Foata normal form. 2/50 useless extension candidates. Maximal degree in co-relation 41. Up to 15 conditions per place. [INFO]: OwickiGriesTestSuite setup time: 1344ms [INFO]: Constructing Owicki-Gries proof for Petri program that has 68 places, 65 transitions, 134 flow. [INFO]: Computed Owicki-Gries annotation with 11 ghost variables, 12 ghost updates, and overall size 5108 [INFO]: Interfering actions: min=0, max=27, median=0 [INFO]: Computed Owicki-Gries annotation with 11 ghost variables, 12 ghost updates, and overall size 5108 Assertions: l50 : 9#(and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1| (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l39]_1|) (not |v_[l43]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l40]_1| (not |v_[l1, l53]_1|)) l52 : 18#(and (not |v_[l66, l36]_1|) |v_[l31, l9, l37, l41, l30, l22, l16]_1| (not |v_[l35, l34]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|) (not |v_[l1, l53]_1|) |v_[l64, l21, l52]_1| (or (not (and (not |v_[l66, l36]_1|) |v_[l31, l9, l37, l41, l30, l22, l16]_1| (not |v_[l35, l34]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|) (not |v_[l1, l53]_1|) |v_[l64, l21, l52]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0))))) l51 : 27#(and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (or (not (and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l51]_1| |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|))) (and (= ~y~0 ~x~0) (= |ULTIMATE.start_thr2_~l~0#1| ~x~0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)))) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l51]_1| |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|)) l10 : 35#(and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1| (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l39]_1|) (not |v_[l43]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l40]_1| (not |v_[l1, l53]_1|)) l54 : 36#false l53 : 64#(and (or (and (= ~y~0 ~x~0) (= |ULTIMATE.start_thr2_~l~0#1| ~x~0) (= ~x~0 |ULTIMATE.start_thr2_~ly~0#1|) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)) (= |ULTIMATE.start_thr2_~lx~0#1| |ULTIMATE.start_thr2_~ly~0#1|)) (not (and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) |v_[l35, l34]_1| (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|)))) (or (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)) (not (and (not |v_[l64, l21, l52]_1|) (not |v_[l35, l34]_1|) (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) |v_[l66, l36]_1| (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|)))) (or (and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) |v_[l35, l34]_1| (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|)) (and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l43]_1| |v_[l39]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|)) (and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l51]_1| |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|)) (and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) |v_[l1, l53]_1| |v_[l43]_1| |v_[l61]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|)) (and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) |v_[l31, l9, l37, l41, l30, l22, l16]_1| (not |v_[l35, l34]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|)) (and (not |v_[l64, l21, l52]_1|) (not |v_[l35, l34]_1|) (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) |v_[l66, l36]_1| (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|))) (or (not (and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l51]_1| |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|))) (and (= ~y~0 ~x~0) (= |ULTIMATE.start_thr2_~l~0#1| ~x~0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)))) (or (and (= ~y~0 ~x~0) (= |ULTIMATE.start_thr2_~l~0#1| ~x~0) (= ~x~0 |ULTIMATE.start_thr2_~ly~0#1|) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0))) (not (and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l43]_1| |v_[l39]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|)))) |v_[l1, l53]_1| (or (and (= |ULTIMATE.start_thr2_~l~0#1| ~x~0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0))) (not (and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) |v_[l1, l53]_1| |v_[l43]_1| |v_[l61]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|))))) l12 : 72#(and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1| (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l39]_1|) (not |v_[l43]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l40]_1| (not |v_[l1, l53]_1|)) l56 : 80#(and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1| (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l39]_1|) (not |v_[l43]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l40]_1| (not |v_[l1, l53]_1|)) l11 : 81#false l55 : 82#false l14 : 83#false l58 : 91#(and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1| (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l39]_1|) (not |v_[l43]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l40]_1| (not |v_[l1, l53]_1|)) l13 : 99#(and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1| (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l39]_1|) (not |v_[l43]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l40]_1| (not |v_[l1, l53]_1|)) l57 : 100#false l16 : 111#(and (or (and (not |v_[l66, l36]_1|) |v_[l31, l9, l37, l41, l30, l22, l16]_1| (not |v_[l35, l34]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|) (not |v_[l1, l53]_1|) |v_[l64, l21, l52]_1|) (and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) |v_[l31, l9, l37, l41, l30, l22, l16]_1| (not |v_[l35, l34]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|))) |v_[l31, l9, l37, l41, l30, l22, l16]_1| (or (not (and (not |v_[l66, l36]_1|) |v_[l31, l9, l37, l41, l30, l22, l16]_1| (not |v_[l35, l34]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|) (not |v_[l1, l53]_1|) |v_[l64, l21, l52]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0))))) l15 : 112#false l59 : 113#false l18 : 121#(and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1| (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l39]_1|) (not |v_[l43]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l40]_1| (not |v_[l1, l53]_1|)) l17 : 122#false l19 : 130#(and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1| (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l39]_1|) (not |v_[l43]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l40]_1| (not |v_[l1, l53]_1|)) l61 : 138#(and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) |v_[l1, l53]_1| (or (and (= |ULTIMATE.start_thr2_~l~0#1| ~x~0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0))) (not (and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) |v_[l1, l53]_1| |v_[l43]_1| |v_[l61]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|)))) |v_[l43]_1| |v_[l61]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|)) l60 : 146#(and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1| (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l39]_1|) (not |v_[l43]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l40]_1| (not |v_[l1, l53]_1|)) l63 : 154#(and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1| (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l39]_1|) (not |v_[l43]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l40]_1| (not |v_[l1, l53]_1|)) l62 : 162#(and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1| (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l39]_1|) (not |v_[l43]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l40]_1| (not |v_[l1, l53]_1|)) l21 : 170#(and (not |v_[l66, l36]_1|) |v_[l31, l9, l37, l41, l30, l22, l16]_1| (not |v_[l35, l34]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|) (not |v_[l1, l53]_1|) |v_[l64, l21, l52]_1| (or (not (and (not |v_[l66, l36]_1|) |v_[l31, l9, l37, l41, l30, l22, l16]_1| (not |v_[l35, l34]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|) (not |v_[l1, l53]_1|) |v_[l64, l21, l52]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0))))) l65 : 178#(and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1| (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l39]_1|) (not |v_[l43]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l40]_1| (not |v_[l1, l53]_1|)) l20 : 186#(and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1| (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l39]_1|) (not |v_[l43]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l40]_1| (not |v_[l1, l53]_1|)) l64 : 194#(and (not |v_[l66, l36]_1|) |v_[l31, l9, l37, l41, l30, l22, l16]_1| (not |v_[l35, l34]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|) (not |v_[l1, l53]_1|) |v_[l64, l21, l52]_1| (or (not (and (not |v_[l66, l36]_1|) |v_[l31, l9, l37, l41, l30, l22, l16]_1| (not |v_[l35, l34]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|) (not |v_[l1, l53]_1|) |v_[l64, l21, l52]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0))))) l23 : 195#false l67 : 203#(and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1| (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l39]_1|) (not |v_[l43]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l40]_1| (not |v_[l1, l53]_1|)) l22 : 214#(and (or (and (not |v_[l66, l36]_1|) |v_[l31, l9, l37, l41, l30, l22, l16]_1| (not |v_[l35, l34]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|) (not |v_[l1, l53]_1|) |v_[l64, l21, l52]_1|) (and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) |v_[l31, l9, l37, l41, l30, l22, l16]_1| (not |v_[l35, l34]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|))) |v_[l31, l9, l37, l41, l30, l22, l16]_1| (or (not (and (not |v_[l66, l36]_1|) |v_[l31, l9, l37, l41, l30, l22, l16]_1| (not |v_[l35, l34]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|) (not |v_[l1, l53]_1|) |v_[l64, l21, l52]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0))))) l66 : 222#(and (not |v_[l64, l21, l52]_1|) (not |v_[l35, l34]_1|) (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (or (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)) (not (and (not |v_[l64, l21, l52]_1|) (not |v_[l35, l34]_1|) (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) |v_[l66, l36]_1| (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|)))) (not |v_[l39]_1|) |v_[l66, l36]_1| (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|)) l25 : 223#false l24 : 224#false l27 : 225#false l26 : 233#(and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1| (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l39]_1|) (not |v_[l43]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l40]_1| (not |v_[l1, l53]_1|)) l29 : 241#(and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1| (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l39]_1|) (not |v_[l43]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l40]_1| (not |v_[l1, l53]_1|)) l28 : 249#(and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1| (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l39]_1|) (not |v_[l43]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l40]_1| (not |v_[l1, l53]_1|)) l0 : 250#false l1 : 273#(and (or (and (= ~y~0 ~x~0) (= |ULTIMATE.start_thr2_~l~0#1| ~x~0) (= ~x~0 |ULTIMATE.start_thr2_~ly~0#1|) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)) (= |ULTIMATE.start_thr2_~lx~0#1| |ULTIMATE.start_thr2_~ly~0#1|)) (not (and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) |v_[l35, l34]_1| (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|)))) (or (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)) (not (and (not |v_[l64, l21, l52]_1|) (not |v_[l35, l34]_1|) (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) |v_[l66, l36]_1| (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|)))) (or (and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) |v_[l35, l34]_1| (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|)) (and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l43]_1| |v_[l39]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|)) (and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l51]_1| |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|)) (and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) |v_[l1, l53]_1| |v_[l43]_1| |v_[l61]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|)) (and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) |v_[l31, l9, l37, l41, l30, l22, l16]_1| (not |v_[l35, l34]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|)) (and (not |v_[l64, l21, l52]_1|) (not |v_[l35, l34]_1|) (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) |v_[l66, l36]_1| (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|))) (or (not (and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l51]_1| |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|))) (and (= ~y~0 ~x~0) (= |ULTIMATE.start_thr2_~l~0#1| ~x~0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)))) (or (and (= ~y~0 ~x~0) (= |ULTIMATE.start_thr2_~l~0#1| ~x~0) (= ~x~0 |ULTIMATE.start_thr2_~ly~0#1|) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0))) (not (and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l43]_1| |v_[l39]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|)))) |v_[l1, l53]_1| (or (and (= |ULTIMATE.start_thr2_~l~0#1| ~x~0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0))) (not (and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) |v_[l1, l53]_1| |v_[l43]_1| |v_[l61]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|))))) l2 : 274#false l3 : 275#false l4 : 283#(and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1| (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l39]_1|) (not |v_[l43]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l40]_1| (not |v_[l1, l53]_1|)) l30 : 294#(and (or (and (not |v_[l66, l36]_1|) |v_[l31, l9, l37, l41, l30, l22, l16]_1| (not |v_[l35, l34]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|) (not |v_[l1, l53]_1|) |v_[l64, l21, l52]_1|) (and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) |v_[l31, l9, l37, l41, l30, l22, l16]_1| (not |v_[l35, l34]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|))) |v_[l31, l9, l37, l41, l30, l22, l16]_1| (or (not (and (not |v_[l66, l36]_1|) |v_[l31, l9, l37, l41, l30, l22, l16]_1| (not |v_[l35, l34]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|) (not |v_[l1, l53]_1|) |v_[l64, l21, l52]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0))))) l5 : 302#(and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1| (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l39]_1|) (not |v_[l43]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l40]_1| (not |v_[l1, l53]_1|)) l6 : 310#(and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1| (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l39]_1|) (not |v_[l43]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l40]_1| (not |v_[l1, l53]_1|)) l32 : 318#(and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1| (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l39]_1|) (not |v_[l43]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l40]_1| (not |v_[l1, l53]_1|)) l7 : 319#false l31 : 330#(and (or (and (not |v_[l66, l36]_1|) |v_[l31, l9, l37, l41, l30, l22, l16]_1| (not |v_[l35, l34]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|) (not |v_[l1, l53]_1|) |v_[l64, l21, l52]_1|) (and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) |v_[l31, l9, l37, l41, l30, l22, l16]_1| (not |v_[l35, l34]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|))) |v_[l31, l9, l37, l41, l30, l22, l16]_1| (or (not (and (not |v_[l66, l36]_1|) |v_[l31, l9, l37, l41, l30, l22, l16]_1| (not |v_[l35, l34]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|) (not |v_[l1, l53]_1|) |v_[l64, l21, l52]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0))))) l8 : 338#(and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1| (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l39]_1|) (not |v_[l43]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l40]_1| (not |v_[l1, l53]_1|)) l34 : 346#(and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) |v_[l35, l34]_1| (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (or (and (= ~y~0 ~x~0) (= |ULTIMATE.start_thr2_~l~0#1| ~x~0) (= ~x~0 |ULTIMATE.start_thr2_~ly~0#1|) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)) (= |ULTIMATE.start_thr2_~lx~0#1| |ULTIMATE.start_thr2_~ly~0#1|)) (not (and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) |v_[l35, l34]_1| (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|)))) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|)) l9 : 357#(and (or (and (not |v_[l66, l36]_1|) |v_[l31, l9, l37, l41, l30, l22, l16]_1| (not |v_[l35, l34]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|) (not |v_[l1, l53]_1|) |v_[l64, l21, l52]_1|) (and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) |v_[l31, l9, l37, l41, l30, l22, l16]_1| (not |v_[l35, l34]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|))) |v_[l31, l9, l37, l41, l30, l22, l16]_1| (or (not (and (not |v_[l66, l36]_1|) |v_[l31, l9, l37, l41, l30, l22, l16]_1| (not |v_[l35, l34]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|) (not |v_[l1, l53]_1|) |v_[l64, l21, l52]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0))))) l33 : 365#(and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1| (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l39]_1|) (not |v_[l43]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l40]_1| (not |v_[l1, l53]_1|)) l36 : 373#(and (not |v_[l64, l21, l52]_1|) (not |v_[l35, l34]_1|) (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (or (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)) (not (and (not |v_[l64, l21, l52]_1|) (not |v_[l35, l34]_1|) (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) |v_[l66, l36]_1| (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|)))) (not |v_[l39]_1|) |v_[l66, l36]_1| (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|)) l35 : 381#(and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) |v_[l35, l34]_1| (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (or (and (= ~y~0 ~x~0) (= |ULTIMATE.start_thr2_~l~0#1| ~x~0) (= ~x~0 |ULTIMATE.start_thr2_~ly~0#1|) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)) (= |ULTIMATE.start_thr2_~lx~0#1| |ULTIMATE.start_thr2_~ly~0#1|)) (not (and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) |v_[l35, l34]_1| (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|)))) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|)) l38 : 389#(and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1| (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l39]_1|) (not |v_[l43]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l40]_1| (not |v_[l1, l53]_1|)) l37 : 400#(and (or (and (not |v_[l66, l36]_1|) |v_[l31, l9, l37, l41, l30, l22, l16]_1| (not |v_[l35, l34]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|) (not |v_[l1, l53]_1|) |v_[l64, l21, l52]_1|) (and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) |v_[l31, l9, l37, l41, l30, l22, l16]_1| (not |v_[l35, l34]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|))) |v_[l31, l9, l37, l41, l30, l22, l16]_1| (or (not (and (not |v_[l66, l36]_1|) |v_[l31, l9, l37, l41, l30, l22, l16]_1| (not |v_[l35, l34]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|) (not |v_[l1, l53]_1|) |v_[l64, l21, l52]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0))))) l39 : 408#(and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l51]_1|) (or (and (= ~y~0 ~x~0) (= |ULTIMATE.start_thr2_~l~0#1| ~x~0) (= ~x~0 |ULTIMATE.start_thr2_~ly~0#1|) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0))) (not (and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l43]_1| |v_[l39]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|)))) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l43]_1| |v_[l39]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|)) l41 : 419#(and (or (and (not |v_[l66, l36]_1|) |v_[l31, l9, l37, l41, l30, l22, l16]_1| (not |v_[l35, l34]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|) (not |v_[l1, l53]_1|) |v_[l64, l21, l52]_1|) (and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) |v_[l31, l9, l37, l41, l30, l22, l16]_1| (not |v_[l35, l34]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|))) |v_[l31, l9, l37, l41, l30, l22, l16]_1| (or (not (and (not |v_[l66, l36]_1|) |v_[l31, l9, l37, l41, l30, l22, l16]_1| (not |v_[l35, l34]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|) (not |v_[l1, l53]_1|) |v_[l64, l21, l52]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0))))) l40 : 427#(and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1| (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l39]_1|) (not |v_[l43]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l40]_1| (not |v_[l1, l53]_1|)) l43 : 453#(and (or (and (= ~y~0 ~x~0) (= |ULTIMATE.start_thr2_~l~0#1| ~x~0) (= ~x~0 |ULTIMATE.start_thr2_~ly~0#1|) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)) (= |ULTIMATE.start_thr2_~lx~0#1| |ULTIMATE.start_thr2_~ly~0#1|)) (not (and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) |v_[l35, l34]_1| (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|)))) (or (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)) (not (and (not |v_[l64, l21, l52]_1|) (not |v_[l35, l34]_1|) (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) |v_[l66, l36]_1| (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|)))) (or (and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) |v_[l35, l34]_1| (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|)) (and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l43]_1| |v_[l39]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|)) (and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l51]_1| |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|)) (and (not |v_[l66, l36]_1|) |v_[l31, l9, l37, l41, l30, l22, l16]_1| (not |v_[l35, l34]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|) (not |v_[l1, l53]_1|) |v_[l64, l21, l52]_1|) (and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) |v_[l1, l53]_1| |v_[l43]_1| |v_[l61]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|)) (and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) |v_[l31, l9, l37, l41, l30, l22, l16]_1| (not |v_[l35, l34]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|)) (and (not |v_[l64, l21, l52]_1|) (not |v_[l35, l34]_1|) (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) |v_[l66, l36]_1| (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|))) (or (not (and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l51]_1| |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|))) (and (= ~y~0 ~x~0) (= |ULTIMATE.start_thr2_~l~0#1| ~x~0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0)))) (or (and (= ~y~0 ~x~0) (= |ULTIMATE.start_thr2_~l~0#1| ~x~0) (= ~x~0 |ULTIMATE.start_thr2_~ly~0#1|) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0))) (not (and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l1, l53]_1| |v_[l43]_1| |v_[l39]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|)))) (or (and (= |ULTIMATE.start_thr2_~l~0#1| ~x~0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0))) (not (and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) |v_[l1, l53]_1| |v_[l43]_1| |v_[l61]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|)))) |v_[l43]_1| (or (not (and (not |v_[l66, l36]_1|) |v_[l31, l9, l37, l41, l30, l22, l16]_1| (not |v_[l35, l34]_1|) (not |v_[l40]_1|) (not |v_[l39]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l43]_1| (not |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1|) (not |v_[l1, l53]_1|) |v_[l64, l21, l52]_1|)) (and (<= (+ (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 1) 0) (not (= (select (select |#pthreadsRwLock| |~#rwlock~0.base|) |~#rwlock~0.offset|) 0))))) l42 : 461#(and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1| (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l39]_1|) (not |v_[l43]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l40]_1| (not |v_[l1, l53]_1|)) l45 : 469#(and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1| (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l39]_1|) (not |v_[l43]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l40]_1| (not |v_[l1, l53]_1|)) l44 : 470#false l47 : 471#false l46 : 472#false l49 : 480#(and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1| (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l39]_1|) (not |v_[l43]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l40]_1| (not |v_[l1, l53]_1|)) l48 : 488#(and (not |v_[l64, l21, l52]_1|) (not |v_[l66, l36]_1|) (not |v_[l35, l34]_1|) |v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1| (not |v_[l31, l9, l37, l41, l30, l22, l16]_1|) (not |v_[l39]_1|) (not |v_[l43]_1|) (not |v_[l51]_1|) (not |v_[l61]_1|) |v_[l40]_1| (not |v_[l1, l53]_1|)) Ghost Variables (and initial values): v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1 : true v_[l51]_1 : false v_[l39]_1 : false v_[l31, l9, l37, l41, l30, l22, l16]_1 : false v_[l66, l36]_1 : false v_[l61]_1 : false v_[l64, l21, l52]_1 : false v_[l43]_1 : false v_[l35, l34]_1 : false v_[l1, l53]_1 : false v_[l40]_1 : true Ghost Updates: [57][32] : (v_[l39]_1, v_[l35, l34]_1) := (false, true) [46][18] : (v_[l51]_1, v_[l39]_1) := (false, true) [26][3] : (v_[l64, l21, l52]_1) := (false) [11][52] : (v_[l35, l34]_1) := (true) [61][37] : (v_[l51]_1, v_[l61]_1) := (true, false) [50][23] : (v_[l66, l36]_1, v_[l61]_1) := (false, true) [38][8] : (v_[l35, l34]_1) := (false) [65][41] : (v_[l31, l9, l37, l41, l30, l22, l16]_1, v_[l66, l36]_1) := (false, true) [23][29] : (v_[l64, l21, l52]_1, v_[l1, l53]_1) := (true, false) [30][14] : (v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1, v_[l43]_1) := (false, false) [56][30] : (v_[l35, l34]_1) := (false) [31][15] : (v_[l50, l49, l48, l10, l12, l56, l58, l13, l18, l19, l60, l63, l62, l65, l20, l67, l26, l29, l28, l4, l5, l6, l32, l8, l33, l38, l42, l45]_1, v_[l31, l9, l37, l41, l30, l22, l16]_1, v_[l43]_1, v_[l1, l53]_1, v_[l40]_1) := (false, true, true, true, false) [INFO]: EmpireComputation time [ms]: 131, EmpireComputation statistics: empire size: 8, empire law size: 145, empire annotation size: 153, number of regions: 11, Min number of regions per territory: 2, Max number of regions per territory: 3, Median number of regions per territory: 3, Min number of places per region: 1, Max number of places per region: 28, Median number of places per region: 2, Empire validity check time [ms]: 63, EmpireToOwickiGries time [ms]: 68, Owicki-Gries validity check time [ms]: 269 │ │ │ duration: 1909 ms │ │ │ status: ✔ SUCCESSFUL │ └─ GraphEmpireOG finished after 1921 ms. └─ JUnit Vintage finished after 1929 ms. ├─ JUnit Platform Suite └─ JUnit Platform Suite finished after 1 ms. Test plan execution finished. Number of all tests: 1  Test run finished after 1978 ms [ 4 containers found ] [ 0 containers skipped ] [ 4 containers started ] [ 0 containers aborted ] [ 4 containers successful ] [ 0 containers failed ] [ 1 tests found ] [ 0 tests skipped ] [ 1 tests started ] [ 0 tests aborted ] [ 1 tests successful ] [ 0 tests failed ]