java -Xmx8000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerBpl.xml --generate-csv --csv-dir csv -s ../../../trunk/examples/programs/regression/bpl/AutomizerBpl-nestedInterpolants.epf -i ../../../trunk/examples/programs/real-life/GateController.bpl -------------------------------------------------------------------------------- This is Ultimate 0.1.23-935f392 [2018-07-23 13:36:26,440 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-07-23 13:36:26,442 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-07-23 13:36:26,454 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-07-23 13:36:26,455 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-07-23 13:36:26,456 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-07-23 13:36:26,457 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-07-23 13:36:26,459 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-07-23 13:36:26,461 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-07-23 13:36:26,461 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-07-23 13:36:26,462 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... 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[2018-07-23 13:36:26,482 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-07-23 13:36:26,482 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-07-23 13:36:26,491 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-07-23 13:36:26,493 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-07-23 13:36:26,494 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-07-23 13:36:26,496 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-07-23 13:36:26,498 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-07-23 13:36:26,498 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-07-23 13:36:26,500 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... 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[2018-07-23 13:36:26,504 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/programs/regression/bpl/AutomizerBpl-nestedInterpolants.epf [2018-07-23 13:36:26,529 INFO L110 SettingsManager]: Loading preferences was successful [2018-07-23 13:36:26,529 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-07-23 13:36:26,532 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-07-23 13:36:26,532 INFO L133 SettingsManager]: * SMT solver=Internal_SMTInterpol [2018-07-23 13:36:26,532 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-07-23 13:36:26,532 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=Craig_NestedInterpolation [2018-07-23 13:36:26,533 INFO L133 SettingsManager]: * Use separate solver for trace checks=false [2018-07-23 13:36:26,533 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-07-23 13:36:26,596 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-07-23 13:36:26,610 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-07-23 13:36:26,613 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-07-23 13:36:26,615 INFO L271 PluginConnector]: Initializing Boogie PL CUP Parser... [2018-07-23 13:36:26,616 INFO L276 PluginConnector]: Boogie PL CUP Parser initialized [2018-07-23 13:36:26,617 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/programs/real-life/GateController.bpl [2018-07-23 13:36:26,617 INFO L111 BoogieParser]: Parsing: '/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/programs/real-life/GateController.bpl' [2018-07-23 13:36:26,671 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-07-23 13:36:26,672 INFO L131 ToolchainWalker]: Walking toolchain with 3 elements. [2018-07-23 13:36:26,673 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-07-23 13:36:26,673 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-07-23 13:36:26,674 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-07-23 13:36:26,703 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "GateController.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.07 01:36:26" (1/1) ... [2018-07-23 13:36:26,705 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "GateController.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.07 01:36:26" (1/1) ... [2018-07-23 13:36:26,716 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "GateController.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.07 01:36:26" (1/1) ... [2018-07-23 13:36:26,716 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "GateController.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.07 01:36:26" (1/1) ... [2018-07-23 13:36:26,719 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "GateController.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.07 01:36:26" (1/1) ... [2018-07-23 13:36:26,726 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "GateController.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.07 01:36:26" (1/1) ... [2018-07-23 13:36:26,727 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "GateController.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.07 01:36:26" (1/1) ... [2018-07-23 13:36:26,729 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-07-23 13:36:26,730 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-07-23 13:36:26,730 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-07-23 13:36:26,731 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-07-23 13:36:26,732 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "GateController.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.07 01:36:26" (1/1) ... [2018-07-23 13:36:26,824 INFO L124 BoogieDeclarations]: Specification and implementation of procedure GateController given in one single declaration [2018-07-23 13:36:26,825 INFO L130 BoogieDeclarations]: Found specification of procedure GateController [2018-07-23 13:36:26,825 INFO L138 BoogieDeclarations]: Found implementation of procedure GateController [2018-07-23 13:36:27,073 INFO L258 CfgBuilder]: Using library mode [2018-07-23 13:36:27,074 INFO L202 PluginConnector]: Adding new model GateController.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.07 01:36:27 BoogieIcfgContainer [2018-07-23 13:36:27,074 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-07-23 13:36:27,075 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-07-23 13:36:27,075 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-07-23 13:36:27,079 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-07-23 13:36:27,079 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "GateController.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 23.07 01:36:26" (1/2) ... [2018-07-23 13:36:27,080 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@56b4bb44 and model type GateController.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.07 01:36:27, skipping insertion in model container [2018-07-23 13:36:27,080 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "GateController.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.07 01:36:27" (2/2) ... [2018-07-23 13:36:27,083 INFO L112 eAbstractionObserver]: Analyzing ICFG GateController.bpl [2018-07-23 13:36:27,093 INFO L132 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:Craig_NestedInterpolation Determinization: PREDICATE_ABSTRACTION [2018-07-23 13:36:27,105 INFO L144 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-07-23 13:36:27,143 INFO L128 ementStrategyFactory]: Using default assertion order modulation [2018-07-23 13:36:27,144 INFO L373 AbstractCegarLoop]: Interprodecural is true [2018-07-23 13:36:27,144 INFO L374 AbstractCegarLoop]: Hoare is true [2018-07-23 13:36:27,145 INFO L375 AbstractCegarLoop]: Compute interpolants for Craig_NestedInterpolation [2018-07-23 13:36:27,145 INFO L376 AbstractCegarLoop]: Backedges is CANONICAL [2018-07-23 13:36:27,145 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-07-23 13:36:27,145 INFO L378 AbstractCegarLoop]: Difference is false [2018-07-23 13:36:27,145 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-07-23 13:36:27,146 INFO L384 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-07-23 13:36:27,158 INFO L276 IsEmpty]: Start isEmpty. Operand 5 states. [2018-07-23 13:36:27,168 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 4 [2018-07-23 13:36:27,169 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:27,170 INFO L357 BasicCegarLoop]: trace histogram [1, 1, 1] [2018-07-23 13:36:27,170 INFO L414 AbstractCegarLoop]: === Iteration 1 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:27,175 INFO L82 PathProgramCache]: Analyzing trace with hash 30432, now seen corresponding path program 1 times [2018-07-23 13:36:27,182 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:27,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:27,246 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:27,249 INFO L309 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-07-23 13:36:27,249 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-07-23 13:36:27,251 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:27,252 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:27,252 INFO L185 omatonBuilderFactory]: Interpolants [8#true, 9#false, 10#(<= (+ GateController_time 1000) GateController_thousand)] [2018-07-23 13:36:27,252 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:27,253 INFO L450 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-07-23 13:36:27,266 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-07-23 13:36:27,266 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-07-23 13:36:27,268 INFO L87 Difference]: Start difference. First operand 5 states. Second operand 3 states. [2018-07-23 13:36:27,294 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:27,294 INFO L93 Difference]: Finished difference Result 9 states and 9 transitions. [2018-07-23 13:36:27,295 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-07-23 13:36:27,297 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 3 [2018-07-23 13:36:27,297 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:27,308 INFO L225 Difference]: With dead ends: 9 [2018-07-23 13:36:27,308 INFO L226 Difference]: Without dead ends: 5 [2018-07-23 13:36:27,312 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-07-23 13:36:27,329 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5 states. [2018-07-23 13:36:27,344 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5 to 5. [2018-07-23 13:36:27,345 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. [2018-07-23 13:36:27,346 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 5 transitions. [2018-07-23 13:36:27,348 INFO L78 Accepts]: Start accepts. Automaton has 5 states and 5 transitions. Word has length 3 [2018-07-23 13:36:27,348 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:27,348 INFO L471 AbstractCegarLoop]: Abstraction has 5 states and 5 transitions. [2018-07-23 13:36:27,348 INFO L472 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-07-23 13:36:27,349 INFO L276 IsEmpty]: Start isEmpty. Operand 5 states and 5 transitions. [2018-07-23 13:36:27,349 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2018-07-23 13:36:27,349 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:27,349 INFO L357 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2018-07-23 13:36:27,350 INFO L414 AbstractCegarLoop]: === Iteration 2 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:27,350 INFO L82 PathProgramCache]: Analyzing trace with hash 952992, now seen corresponding path program 1 times [2018-07-23 13:36:27,350 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:27,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:27,386 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:27,387 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:27,387 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [3] total 3 [2018-07-23 13:36:27,387 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:27,388 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:27,388 INFO L185 omatonBuilderFactory]: Interpolants [39#true, 40#false, 41#(<= (+ GateController_time 1000) GateController_thousand), 42#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 43#GateController_alarm] [2018-07-23 13:36:27,388 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:27,391 INFO L450 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-07-23 13:36:27,391 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-07-23 13:36:27,392 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-07-23 13:36:27,392 INFO L87 Difference]: Start difference. First operand 5 states and 5 transitions. Second operand 5 states. [2018-07-23 13:36:27,417 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:27,417 INFO L93 Difference]: Finished difference Result 8 states and 8 transitions. [2018-07-23 13:36:27,419 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-07-23 13:36:27,419 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 4 [2018-07-23 13:36:27,420 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:27,420 INFO L225 Difference]: With dead ends: 8 [2018-07-23 13:36:27,420 INFO L226 Difference]: Without dead ends: 6 [2018-07-23 13:36:27,422 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-07-23 13:36:27,422 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6 states. [2018-07-23 13:36:27,424 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6 to 6. [2018-07-23 13:36:27,424 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6 states. [2018-07-23 13:36:27,424 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 6 transitions. [2018-07-23 13:36:27,425 INFO L78 Accepts]: Start accepts. Automaton has 6 states and 6 transitions. Word has length 4 [2018-07-23 13:36:27,425 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:27,425 INFO L471 AbstractCegarLoop]: Abstraction has 6 states and 6 transitions. [2018-07-23 13:36:27,425 INFO L472 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-07-23 13:36:27,426 INFO L276 IsEmpty]: Start isEmpty. Operand 6 states and 6 transitions. [2018-07-23 13:36:27,426 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2018-07-23 13:36:27,426 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:27,426 INFO L357 BasicCegarLoop]: trace histogram [2, 1, 1, 1] [2018-07-23 13:36:27,427 INFO L414 AbstractCegarLoop]: === Iteration 3 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:27,427 INFO L82 PathProgramCache]: Analyzing trace with hash 29552352, now seen corresponding path program 2 times [2018-07-23 13:36:27,427 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:27,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:27,498 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:27,499 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:27,499 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4] total 4 [2018-07-23 13:36:27,499 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:27,500 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:27,500 INFO L185 omatonBuilderFactory]: Interpolants [72#true, 73#false, 74#(<= (+ GateController_time 1000) GateController_thousand), 75#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 76#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 77#GateController_alarm] [2018-07-23 13:36:27,500 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:27,501 INFO L450 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-07-23 13:36:27,501 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-07-23 13:36:27,501 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=16, Unknown=0, NotChecked=0, Total=30 [2018-07-23 13:36:27,502 INFO L87 Difference]: Start difference. First operand 6 states and 6 transitions. Second operand 6 states. [2018-07-23 13:36:27,524 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:27,525 INFO L93 Difference]: Finished difference Result 9 states and 9 transitions. [2018-07-23 13:36:27,525 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-07-23 13:36:27,525 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 5 [2018-07-23 13:36:27,526 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:27,526 INFO L225 Difference]: With dead ends: 9 [2018-07-23 13:36:27,526 INFO L226 Difference]: Without dead ends: 7 [2018-07-23 13:36:27,527 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=16, Unknown=0, NotChecked=0, Total=30 [2018-07-23 13:36:27,527 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7 states. [2018-07-23 13:36:27,529 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7 to 7. [2018-07-23 13:36:27,529 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7 states. [2018-07-23 13:36:27,530 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 7 transitions. [2018-07-23 13:36:27,530 INFO L78 Accepts]: Start accepts. Automaton has 7 states and 7 transitions. Word has length 5 [2018-07-23 13:36:27,530 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:27,530 INFO L471 AbstractCegarLoop]: Abstraction has 7 states and 7 transitions. [2018-07-23 13:36:27,531 INFO L472 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-07-23 13:36:27,531 INFO L276 IsEmpty]: Start isEmpty. Operand 7 states and 7 transitions. [2018-07-23 13:36:27,531 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 7 [2018-07-23 13:36:27,531 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:27,531 INFO L357 BasicCegarLoop]: trace histogram [3, 1, 1, 1] [2018-07-23 13:36:27,532 INFO L414 AbstractCegarLoop]: === Iteration 4 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:27,532 INFO L82 PathProgramCache]: Analyzing trace with hash 916132512, now seen corresponding path program 3 times [2018-07-23 13:36:27,532 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:27,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:27,585 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:27,585 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:27,586 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5] total 5 [2018-07-23 13:36:27,586 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:27,586 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:27,587 INFO L185 omatonBuilderFactory]: Interpolants [112#(<= (+ GateController_time 1000) GateController_thousand), 113#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 114#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 115#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 116#GateController_alarm, 110#true, 111#false] [2018-07-23 13:36:27,587 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:27,587 INFO L450 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-07-23 13:36:27,588 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-07-23 13:36:27,588 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=22, Unknown=0, NotChecked=0, Total=42 [2018-07-23 13:36:27,588 INFO L87 Difference]: Start difference. First operand 7 states and 7 transitions. Second operand 7 states. [2018-07-23 13:36:27,613 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:27,613 INFO L93 Difference]: Finished difference Result 10 states and 10 transitions. [2018-07-23 13:36:27,613 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-07-23 13:36:27,614 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 6 [2018-07-23 13:36:27,614 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:27,614 INFO L225 Difference]: With dead ends: 10 [2018-07-23 13:36:27,614 INFO L226 Difference]: Without dead ends: 8 [2018-07-23 13:36:27,615 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=22, Unknown=0, NotChecked=0, Total=42 [2018-07-23 13:36:27,616 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8 states. [2018-07-23 13:36:27,618 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8 to 8. [2018-07-23 13:36:27,618 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8 states. [2018-07-23 13:36:27,619 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 8 transitions. [2018-07-23 13:36:27,619 INFO L78 Accepts]: Start accepts. Automaton has 8 states and 8 transitions. Word has length 6 [2018-07-23 13:36:27,619 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:27,619 INFO L471 AbstractCegarLoop]: Abstraction has 8 states and 8 transitions. [2018-07-23 13:36:27,620 INFO L472 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-07-23 13:36:27,620 INFO L276 IsEmpty]: Start isEmpty. Operand 8 states and 8 transitions. [2018-07-23 13:36:27,620 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2018-07-23 13:36:27,620 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:27,620 INFO L357 BasicCegarLoop]: trace histogram [4, 1, 1, 1] [2018-07-23 13:36:27,621 INFO L414 AbstractCegarLoop]: === Iteration 5 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:27,621 INFO L82 PathProgramCache]: Analyzing trace with hash -1664653600, now seen corresponding path program 4 times [2018-07-23 13:36:27,621 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:27,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:27,684 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:27,684 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:27,684 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6] total 6 [2018-07-23 13:36:27,685 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:27,685 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:27,685 INFO L185 omatonBuilderFactory]: Interpolants [160#GateController_alarm, 153#true, 154#false, 155#(<= (+ GateController_time 1000) GateController_thousand), 156#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 157#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 158#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 159#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand))] [2018-07-23 13:36:27,686 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:27,686 INFO L450 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-07-23 13:36:27,686 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-07-23 13:36:27,686 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=29, Unknown=0, NotChecked=0, Total=56 [2018-07-23 13:36:27,687 INFO L87 Difference]: Start difference. First operand 8 states and 8 transitions. Second operand 8 states. [2018-07-23 13:36:27,711 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:27,711 INFO L93 Difference]: Finished difference Result 11 states and 11 transitions. [2018-07-23 13:36:27,712 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-07-23 13:36:27,712 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 7 [2018-07-23 13:36:27,712 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:27,713 INFO L225 Difference]: With dead ends: 11 [2018-07-23 13:36:27,713 INFO L226 Difference]: Without dead ends: 9 [2018-07-23 13:36:27,714 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=29, Unknown=0, NotChecked=0, Total=56 [2018-07-23 13:36:27,714 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9 states. [2018-07-23 13:36:27,716 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9 to 9. [2018-07-23 13:36:27,717 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9 states. [2018-07-23 13:36:27,717 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 9 transitions. [2018-07-23 13:36:27,717 INFO L78 Accepts]: Start accepts. Automaton has 9 states and 9 transitions. Word has length 7 [2018-07-23 13:36:27,718 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:27,718 INFO L471 AbstractCegarLoop]: Abstraction has 9 states and 9 transitions. [2018-07-23 13:36:27,718 INFO L472 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-07-23 13:36:27,718 INFO L276 IsEmpty]: Start isEmpty. Operand 9 states and 9 transitions. [2018-07-23 13:36:27,718 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 9 [2018-07-23 13:36:27,719 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:27,719 INFO L357 BasicCegarLoop]: trace histogram [5, 1, 1, 1] [2018-07-23 13:36:27,719 INFO L414 AbstractCegarLoop]: === Iteration 6 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:27,719 INFO L82 PathProgramCache]: Analyzing trace with hash -64644448, now seen corresponding path program 5 times [2018-07-23 13:36:27,720 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:27,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:27,824 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:27,825 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:27,825 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7] total 7 [2018-07-23 13:36:27,825 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:27,825 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:27,826 INFO L185 omatonBuilderFactory]: Interpolants [208#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 209#GateController_alarm, 201#true, 202#false, 203#(<= (+ GateController_time 1000) GateController_thousand), 204#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 205#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 206#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 207#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand))] [2018-07-23 13:36:27,826 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:27,827 INFO L450 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-07-23 13:36:27,827 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-07-23 13:36:27,827 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=37, Unknown=0, NotChecked=0, Total=72 [2018-07-23 13:36:27,828 INFO L87 Difference]: Start difference. First operand 9 states and 9 transitions. Second operand 9 states. [2018-07-23 13:36:27,872 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:27,872 INFO L93 Difference]: Finished difference Result 12 states and 12 transitions. [2018-07-23 13:36:27,872 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-07-23 13:36:27,873 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 8 [2018-07-23 13:36:27,873 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:27,873 INFO L225 Difference]: With dead ends: 12 [2018-07-23 13:36:27,874 INFO L226 Difference]: Without dead ends: 10 [2018-07-23 13:36:27,874 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=35, Invalid=37, Unknown=0, NotChecked=0, Total=72 [2018-07-23 13:36:27,875 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10 states. [2018-07-23 13:36:27,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10 to 10. [2018-07-23 13:36:27,878 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10 states. [2018-07-23 13:36:27,879 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 10 transitions. [2018-07-23 13:36:27,879 INFO L78 Accepts]: Start accepts. Automaton has 10 states and 10 transitions. Word has length 8 [2018-07-23 13:36:27,879 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:27,879 INFO L471 AbstractCegarLoop]: Abstraction has 10 states and 10 transitions. [2018-07-23 13:36:27,880 INFO L472 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-07-23 13:36:27,880 INFO L276 IsEmpty]: Start isEmpty. Operand 10 states and 10 transitions. [2018-07-23 13:36:27,880 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 10 [2018-07-23 13:36:27,880 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:27,881 INFO L357 BasicCegarLoop]: trace histogram [6, 1, 1, 1] [2018-07-23 13:36:27,881 INFO L414 AbstractCegarLoop]: === Iteration 7 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:27,881 INFO L82 PathProgramCache]: Analyzing trace with hash -2003968288, now seen corresponding path program 6 times [2018-07-23 13:36:27,881 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:27,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:28,003 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:28,003 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:28,004 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8] total 8 [2018-07-23 13:36:28,004 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:28,004 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:28,005 INFO L185 omatonBuilderFactory]: Interpolants [256#(<= (+ GateController_time 1000) GateController_thousand), 257#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 258#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 259#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 260#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 261#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 262#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 263#GateController_alarm, 254#true, 255#false] [2018-07-23 13:36:28,005 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:28,005 INFO L450 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-07-23 13:36:28,008 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-07-23 13:36:28,008 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=44, Invalid=46, Unknown=0, NotChecked=0, Total=90 [2018-07-23 13:36:28,009 INFO L87 Difference]: Start difference. First operand 10 states and 10 transitions. Second operand 10 states. [2018-07-23 13:36:28,046 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:28,047 INFO L93 Difference]: Finished difference Result 13 states and 13 transitions. [2018-07-23 13:36:28,047 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-07-23 13:36:28,047 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 9 [2018-07-23 13:36:28,048 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:28,048 INFO L225 Difference]: With dead ends: 13 [2018-07-23 13:36:28,048 INFO L226 Difference]: Without dead ends: 11 [2018-07-23 13:36:28,050 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=44, Invalid=46, Unknown=0, NotChecked=0, Total=90 [2018-07-23 13:36:28,050 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11 states. [2018-07-23 13:36:28,055 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11 to 11. [2018-07-23 13:36:28,058 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11 states. [2018-07-23 13:36:28,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 11 transitions. [2018-07-23 13:36:28,059 INFO L78 Accepts]: Start accepts. Automaton has 11 states and 11 transitions. Word has length 9 [2018-07-23 13:36:28,060 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:28,060 INFO L471 AbstractCegarLoop]: Abstraction has 11 states and 11 transitions. [2018-07-23 13:36:28,060 INFO L472 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-07-23 13:36:28,060 INFO L276 IsEmpty]: Start isEmpty. Operand 11 states and 11 transitions. [2018-07-23 13:36:28,061 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 11 [2018-07-23 13:36:28,061 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:28,061 INFO L357 BasicCegarLoop]: trace histogram [7, 1, 1, 1] [2018-07-23 13:36:28,061 INFO L414 AbstractCegarLoop]: === Iteration 8 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:28,062 INFO L82 PathProgramCache]: Analyzing trace with hash -1993465184, now seen corresponding path program 7 times [2018-07-23 13:36:28,062 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:28,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:28,135 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:28,135 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:28,135 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9] total 9 [2018-07-23 13:36:28,136 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:28,136 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:28,137 INFO L185 omatonBuilderFactory]: Interpolants [320#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 321#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 322#GateController_alarm, 312#true, 313#false, 314#(<= (+ GateController_time 1000) GateController_thousand), 315#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 316#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 317#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 318#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 319#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand))] [2018-07-23 13:36:28,137 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:28,137 INFO L450 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-07-23 13:36:28,138 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-07-23 13:36:28,138 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=54, Invalid=56, Unknown=0, NotChecked=0, Total=110 [2018-07-23 13:36:28,138 INFO L87 Difference]: Start difference. First operand 11 states and 11 transitions. Second operand 11 states. [2018-07-23 13:36:28,182 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:28,182 INFO L93 Difference]: Finished difference Result 14 states and 14 transitions. [2018-07-23 13:36:28,185 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-07-23 13:36:28,186 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 10 [2018-07-23 13:36:28,186 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:28,187 INFO L225 Difference]: With dead ends: 14 [2018-07-23 13:36:28,187 INFO L226 Difference]: Without dead ends: 12 [2018-07-23 13:36:28,187 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=54, Invalid=56, Unknown=0, NotChecked=0, Total=110 [2018-07-23 13:36:28,188 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12 states. [2018-07-23 13:36:28,191 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12 to 12. [2018-07-23 13:36:28,191 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12 states. [2018-07-23 13:36:28,192 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 12 transitions. [2018-07-23 13:36:28,192 INFO L78 Accepts]: Start accepts. Automaton has 12 states and 12 transitions. Word has length 10 [2018-07-23 13:36:28,192 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:28,192 INFO L471 AbstractCegarLoop]: Abstraction has 12 states and 12 transitions. [2018-07-23 13:36:28,193 INFO L472 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-07-23 13:36:28,193 INFO L276 IsEmpty]: Start isEmpty. Operand 12 states and 12 transitions. [2018-07-23 13:36:28,193 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-07-23 13:36:28,194 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:28,194 INFO L357 BasicCegarLoop]: trace histogram [8, 1, 1, 1] [2018-07-23 13:36:28,194 INFO L414 AbstractCegarLoop]: === Iteration 9 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:28,194 INFO L82 PathProgramCache]: Analyzing trace with hash -1667868960, now seen corresponding path program 8 times [2018-07-23 13:36:28,195 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:28,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:28,275 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:28,275 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:28,276 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10] total 10 [2018-07-23 13:36:28,276 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:28,276 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:28,277 INFO L185 omatonBuilderFactory]: Interpolants [384#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 385#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 386#GateController_alarm, 375#true, 376#false, 377#(<= (+ GateController_time 1000) GateController_thousand), 378#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 379#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 380#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 381#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 382#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 383#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand))] [2018-07-23 13:36:28,277 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:28,278 INFO L450 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-07-23 13:36:28,278 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-07-23 13:36:28,278 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=65, Invalid=67, Unknown=0, NotChecked=0, Total=132 [2018-07-23 13:36:28,279 INFO L87 Difference]: Start difference. First operand 12 states and 12 transitions. Second operand 12 states. [2018-07-23 13:36:28,302 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:28,302 INFO L93 Difference]: Finished difference Result 15 states and 15 transitions. [2018-07-23 13:36:28,302 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-07-23 13:36:28,302 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 11 [2018-07-23 13:36:28,303 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:28,303 INFO L225 Difference]: With dead ends: 15 [2018-07-23 13:36:28,304 INFO L226 Difference]: Without dead ends: 13 [2018-07-23 13:36:28,304 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=65, Invalid=67, Unknown=0, NotChecked=0, Total=132 [2018-07-23 13:36:28,305 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13 states. [2018-07-23 13:36:28,310 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13 to 13. [2018-07-23 13:36:28,310 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13 states. [2018-07-23 13:36:28,311 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 13 transitions. [2018-07-23 13:36:28,311 INFO L78 Accepts]: Start accepts. Automaton has 13 states and 13 transitions. Word has length 11 [2018-07-23 13:36:28,311 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:28,314 INFO L471 AbstractCegarLoop]: Abstraction has 13 states and 13 transitions. [2018-07-23 13:36:28,314 INFO L472 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-07-23 13:36:28,314 INFO L276 IsEmpty]: Start isEmpty. Operand 13 states and 13 transitions. [2018-07-23 13:36:28,315 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-07-23 13:36:28,315 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:28,315 INFO L357 BasicCegarLoop]: trace histogram [9, 1, 1, 1] [2018-07-23 13:36:28,316 INFO L414 AbstractCegarLoop]: === Iteration 10 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:28,316 INFO L82 PathProgramCache]: Analyzing trace with hash -164320608, now seen corresponding path program 9 times [2018-07-23 13:36:28,316 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:28,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:28,413 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:28,414 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:28,414 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11] total 11 [2018-07-23 13:36:28,414 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:28,415 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:28,415 INFO L185 omatonBuilderFactory]: Interpolants [448#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 449#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 450#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 451#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 452#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 453#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 454#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 455#GateController_alarm, 443#true, 444#false, 445#(<= (+ GateController_time 1000) GateController_thousand), 446#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 447#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand))] [2018-07-23 13:36:28,416 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:28,416 INFO L450 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-07-23 13:36:28,416 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-07-23 13:36:28,417 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=77, Invalid=79, Unknown=0, NotChecked=0, Total=156 [2018-07-23 13:36:28,417 INFO L87 Difference]: Start difference. First operand 13 states and 13 transitions. Second operand 13 states. [2018-07-23 13:36:28,445 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:28,446 INFO L93 Difference]: Finished difference Result 16 states and 16 transitions. [2018-07-23 13:36:28,446 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-07-23 13:36:28,446 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 12 [2018-07-23 13:36:28,450 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:28,450 INFO L225 Difference]: With dead ends: 16 [2018-07-23 13:36:28,450 INFO L226 Difference]: Without dead ends: 14 [2018-07-23 13:36:28,451 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=77, Invalid=79, Unknown=0, NotChecked=0, Total=156 [2018-07-23 13:36:28,453 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14 states. [2018-07-23 13:36:28,463 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14 to 14. [2018-07-23 13:36:28,463 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14 states. [2018-07-23 13:36:28,464 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 14 transitions. [2018-07-23 13:36:28,464 INFO L78 Accepts]: Start accepts. Automaton has 14 states and 14 transitions. Word has length 12 [2018-07-23 13:36:28,466 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:28,466 INFO L471 AbstractCegarLoop]: Abstraction has 14 states and 14 transitions. [2018-07-23 13:36:28,466 INFO L472 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-07-23 13:36:28,467 INFO L276 IsEmpty]: Start isEmpty. Operand 14 states and 14 transitions. [2018-07-23 13:36:28,467 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2018-07-23 13:36:28,467 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:28,468 INFO L357 BasicCegarLoop]: trace histogram [10, 1, 1, 1] [2018-07-23 13:36:28,468 INFO L414 AbstractCegarLoop]: === Iteration 11 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:28,468 INFO L82 PathProgramCache]: Analyzing trace with hash -798961952, now seen corresponding path program 10 times [2018-07-23 13:36:28,469 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:28,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:28,573 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:28,573 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:28,574 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12] total 12 [2018-07-23 13:36:28,574 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:28,574 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:28,575 INFO L185 omatonBuilderFactory]: Interpolants [516#true, 517#false, 518#(<= (+ GateController_time 1000) GateController_thousand), 519#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 520#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 521#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 522#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 523#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 524#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 525#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 526#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 527#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 528#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 529#GateController_alarm] [2018-07-23 13:36:28,576 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:28,576 INFO L450 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-07-23 13:36:28,576 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-07-23 13:36:28,576 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=90, Invalid=92, Unknown=0, NotChecked=0, Total=182 [2018-07-23 13:36:28,577 INFO L87 Difference]: Start difference. First operand 14 states and 14 transitions. Second operand 14 states. [2018-07-23 13:36:28,593 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:28,594 INFO L93 Difference]: Finished difference Result 17 states and 17 transitions. [2018-07-23 13:36:28,594 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-07-23 13:36:28,594 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 13 [2018-07-23 13:36:28,594 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:28,595 INFO L225 Difference]: With dead ends: 17 [2018-07-23 13:36:28,595 INFO L226 Difference]: Without dead ends: 15 [2018-07-23 13:36:28,596 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=90, Invalid=92, Unknown=0, NotChecked=0, Total=182 [2018-07-23 13:36:28,596 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15 states. [2018-07-23 13:36:28,601 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15 to 15. [2018-07-23 13:36:28,601 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15 states. [2018-07-23 13:36:28,602 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 15 transitions. [2018-07-23 13:36:28,602 INFO L78 Accepts]: Start accepts. Automaton has 15 states and 15 transitions. Word has length 13 [2018-07-23 13:36:28,602 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:28,602 INFO L471 AbstractCegarLoop]: Abstraction has 15 states and 15 transitions. [2018-07-23 13:36:28,602 INFO L472 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-07-23 13:36:28,603 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 15 transitions. [2018-07-23 13:36:28,603 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-07-23 13:36:28,603 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:28,603 INFO L357 BasicCegarLoop]: trace histogram [11, 1, 1, 1] [2018-07-23 13:36:28,604 INFO L414 AbstractCegarLoop]: === Iteration 12 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:28,604 INFO L82 PathProgramCache]: Analyzing trace with hash 1001992864, now seen corresponding path program 11 times [2018-07-23 13:36:28,604 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:28,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:28,686 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:28,686 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:28,686 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13] total 13 [2018-07-23 13:36:28,687 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:28,687 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:28,687 INFO L185 omatonBuilderFactory]: Interpolants [608#GateController_alarm, 594#true, 595#false, 596#(<= (+ GateController_time 1000) GateController_thousand), 597#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 598#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 599#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 600#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 601#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 602#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 603#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 604#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 605#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 606#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 607#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand))] [2018-07-23 13:36:28,688 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:28,688 INFO L450 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-07-23 13:36:28,690 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-07-23 13:36:28,690 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=104, Invalid=106, Unknown=0, NotChecked=0, Total=210 [2018-07-23 13:36:28,691 INFO L87 Difference]: Start difference. First operand 15 states and 15 transitions. Second operand 15 states. [2018-07-23 13:36:28,721 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:28,721 INFO L93 Difference]: Finished difference Result 18 states and 18 transitions. [2018-07-23 13:36:28,722 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-07-23 13:36:28,722 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 14 [2018-07-23 13:36:28,723 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:28,723 INFO L225 Difference]: With dead ends: 18 [2018-07-23 13:36:28,724 INFO L226 Difference]: Without dead ends: 16 [2018-07-23 13:36:28,724 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=104, Invalid=106, Unknown=0, NotChecked=0, Total=210 [2018-07-23 13:36:28,725 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states. [2018-07-23 13:36:28,728 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 16. [2018-07-23 13:36:28,729 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16 states. [2018-07-23 13:36:28,730 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 16 transitions. [2018-07-23 13:36:28,731 INFO L78 Accepts]: Start accepts. Automaton has 16 states and 16 transitions. Word has length 14 [2018-07-23 13:36:28,731 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:28,731 INFO L471 AbstractCegarLoop]: Abstraction has 16 states and 16 transitions. [2018-07-23 13:36:28,732 INFO L472 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-07-23 13:36:28,732 INFO L276 IsEmpty]: Start isEmpty. Operand 16 states and 16 transitions. [2018-07-23 13:36:28,732 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-07-23 13:36:28,732 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:28,733 INFO L357 BasicCegarLoop]: trace histogram [12, 1, 1, 1] [2018-07-23 13:36:28,733 INFO L414 AbstractCegarLoop]: === Iteration 13 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:28,733 INFO L82 PathProgramCache]: Analyzing trace with hash 997017312, now seen corresponding path program 12 times [2018-07-23 13:36:28,733 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:28,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:28,836 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:28,837 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:28,837 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14] total 14 [2018-07-23 13:36:28,837 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:28,838 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:28,838 INFO L185 omatonBuilderFactory]: Interpolants [677#true, 678#false, 679#(<= (+ GateController_time 1000) GateController_thousand), 680#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 681#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 682#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 683#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 684#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 685#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 686#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 687#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 688#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 689#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 690#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 691#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 692#GateController_alarm] [2018-07-23 13:36:28,839 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:28,839 INFO L450 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-07-23 13:36:28,839 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-07-23 13:36:28,840 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=119, Invalid=121, Unknown=0, NotChecked=0, Total=240 [2018-07-23 13:36:28,840 INFO L87 Difference]: Start difference. First operand 16 states and 16 transitions. Second operand 16 states. [2018-07-23 13:36:28,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:28,870 INFO L93 Difference]: Finished difference Result 19 states and 19 transitions. [2018-07-23 13:36:28,870 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-07-23 13:36:28,870 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 15 [2018-07-23 13:36:28,870 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:28,871 INFO L225 Difference]: With dead ends: 19 [2018-07-23 13:36:28,871 INFO L226 Difference]: Without dead ends: 17 [2018-07-23 13:36:28,874 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=119, Invalid=121, Unknown=0, NotChecked=0, Total=240 [2018-07-23 13:36:28,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17 states. [2018-07-23 13:36:28,879 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17 to 17. [2018-07-23 13:36:28,879 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17 states. [2018-07-23 13:36:28,880 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 17 transitions. [2018-07-23 13:36:28,880 INFO L78 Accepts]: Start accepts. Automaton has 17 states and 17 transitions. Word has length 15 [2018-07-23 13:36:28,881 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:28,881 INFO L471 AbstractCegarLoop]: Abstraction has 17 states and 17 transitions. [2018-07-23 13:36:28,881 INFO L472 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-07-23 13:36:28,881 INFO L276 IsEmpty]: Start isEmpty. Operand 17 states and 17 transitions. [2018-07-23 13:36:28,882 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-07-23 13:36:28,882 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:28,882 INFO L357 BasicCegarLoop]: trace histogram [13, 1, 1, 1] [2018-07-23 13:36:28,882 INFO L414 AbstractCegarLoop]: === Iteration 14 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:28,883 INFO L82 PathProgramCache]: Analyzing trace with hash 842775200, now seen corresponding path program 13 times [2018-07-23 13:36:28,883 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:28,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:28,983 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:28,986 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:28,986 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15] total 15 [2018-07-23 13:36:28,986 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:28,987 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:28,987 INFO L185 omatonBuilderFactory]: Interpolants [768#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 769#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 770#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 771#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 772#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 773#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 774#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 775#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 776#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 777#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 778#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 779#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 780#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 781#GateController_alarm, 765#true, 766#false, 767#(<= (+ GateController_time 1000) GateController_thousand)] [2018-07-23 13:36:28,988 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:28,988 INFO L450 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-07-23 13:36:28,989 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-07-23 13:36:28,989 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=135, Invalid=137, Unknown=0, NotChecked=0, Total=272 [2018-07-23 13:36:28,990 INFO L87 Difference]: Start difference. First operand 17 states and 17 transitions. Second operand 17 states. [2018-07-23 13:36:29,010 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:29,010 INFO L93 Difference]: Finished difference Result 20 states and 20 transitions. [2018-07-23 13:36:29,011 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-07-23 13:36:29,011 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 16 [2018-07-23 13:36:29,011 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:29,011 INFO L225 Difference]: With dead ends: 20 [2018-07-23 13:36:29,012 INFO L226 Difference]: Without dead ends: 18 [2018-07-23 13:36:29,012 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=135, Invalid=137, Unknown=0, NotChecked=0, Total=272 [2018-07-23 13:36:29,013 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18 states. [2018-07-23 13:36:29,018 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18 to 18. [2018-07-23 13:36:29,019 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18 states. [2018-07-23 13:36:29,020 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 18 transitions. [2018-07-23 13:36:29,020 INFO L78 Accepts]: Start accepts. Automaton has 18 states and 18 transitions. Word has length 16 [2018-07-23 13:36:29,020 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:29,021 INFO L471 AbstractCegarLoop]: Abstraction has 18 states and 18 transitions. [2018-07-23 13:36:29,021 INFO L472 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-07-23 13:36:29,021 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states and 18 transitions. [2018-07-23 13:36:29,022 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-07-23 13:36:29,022 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:29,022 INFO L357 BasicCegarLoop]: trace histogram [14, 1, 1, 1] [2018-07-23 13:36:29,022 INFO L414 AbstractCegarLoop]: === Iteration 15 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:29,025 INFO L82 PathProgramCache]: Analyzing trace with hash 356237024, now seen corresponding path program 14 times [2018-07-23 13:36:29,025 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:29,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:29,127 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 0 proven. 105 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:29,128 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:29,128 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16] total 16 [2018-07-23 13:36:29,128 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:29,129 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:29,130 INFO L185 omatonBuilderFactory]: Interpolants [864#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 865#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 866#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 867#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 868#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 869#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 870#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 871#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 872#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 873#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 874#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 875#GateController_alarm, 858#true, 859#false, 860#(<= (+ GateController_time 1000) GateController_thousand), 861#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 862#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 863#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand))] [2018-07-23 13:36:29,130 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 0 proven. 105 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:29,130 INFO L450 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-07-23 13:36:29,131 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-07-23 13:36:29,131 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=152, Invalid=154, Unknown=0, NotChecked=0, Total=306 [2018-07-23 13:36:29,132 INFO L87 Difference]: Start difference. First operand 18 states and 18 transitions. Second operand 18 states. [2018-07-23 13:36:29,166 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:29,166 INFO L93 Difference]: Finished difference Result 21 states and 21 transitions. [2018-07-23 13:36:29,167 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-07-23 13:36:29,167 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 17 [2018-07-23 13:36:29,168 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:29,168 INFO L225 Difference]: With dead ends: 21 [2018-07-23 13:36:29,168 INFO L226 Difference]: Without dead ends: 19 [2018-07-23 13:36:29,169 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=152, Invalid=154, Unknown=0, NotChecked=0, Total=306 [2018-07-23 13:36:29,169 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19 states. [2018-07-23 13:36:29,174 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19 to 19. [2018-07-23 13:36:29,174 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19 states. [2018-07-23 13:36:29,175 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 19 transitions. [2018-07-23 13:36:29,175 INFO L78 Accepts]: Start accepts. Automaton has 19 states and 19 transitions. Word has length 17 [2018-07-23 13:36:29,175 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:29,175 INFO L471 AbstractCegarLoop]: Abstraction has 19 states and 19 transitions. [2018-07-23 13:36:29,175 INFO L472 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-07-23 13:36:29,176 INFO L276 IsEmpty]: Start isEmpty. Operand 19 states and 19 transitions. [2018-07-23 13:36:29,176 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2018-07-23 13:36:29,176 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:29,177 INFO L357 BasicCegarLoop]: trace histogram [15, 1, 1, 1] [2018-07-23 13:36:29,177 INFO L414 AbstractCegarLoop]: === Iteration 16 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:29,177 INFO L82 PathProgramCache]: Analyzing trace with hash -1841544544, now seen corresponding path program 15 times [2018-07-23 13:36:29,180 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:29,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:29,312 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:29,312 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:29,313 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17] total 17 [2018-07-23 13:36:29,313 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:29,313 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:29,314 INFO L185 omatonBuilderFactory]: Interpolants [960#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 961#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 962#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 963#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 964#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 965#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 966#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 967#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 968#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 969#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 970#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 971#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 972#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 973#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 974#GateController_alarm, 956#true, 957#false, 958#(<= (+ GateController_time 1000) GateController_thousand), 959#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand))] [2018-07-23 13:36:29,318 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:29,319 INFO L450 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-07-23 13:36:29,319 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-07-23 13:36:29,320 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=170, Invalid=172, Unknown=0, NotChecked=0, Total=342 [2018-07-23 13:36:29,320 INFO L87 Difference]: Start difference. First operand 19 states and 19 transitions. Second operand 19 states. [2018-07-23 13:36:29,351 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:29,352 INFO L93 Difference]: Finished difference Result 22 states and 22 transitions. [2018-07-23 13:36:29,352 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-07-23 13:36:29,352 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 18 [2018-07-23 13:36:29,358 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:29,358 INFO L225 Difference]: With dead ends: 22 [2018-07-23 13:36:29,360 INFO L226 Difference]: Without dead ends: 20 [2018-07-23 13:36:29,361 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 29 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=170, Invalid=172, Unknown=0, NotChecked=0, Total=342 [2018-07-23 13:36:29,362 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2018-07-23 13:36:29,368 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2018-07-23 13:36:29,368 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2018-07-23 13:36:29,369 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 20 transitions. [2018-07-23 13:36:29,369 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 20 transitions. Word has length 18 [2018-07-23 13:36:29,369 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:29,370 INFO L471 AbstractCegarLoop]: Abstraction has 20 states and 20 transitions. [2018-07-23 13:36:29,370 INFO L472 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-07-23 13:36:29,370 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 20 transitions. [2018-07-23 13:36:29,371 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-07-23 13:36:29,371 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:29,371 INFO L357 BasicCegarLoop]: trace histogram [16, 1, 1, 1] [2018-07-23 13:36:29,371 INFO L414 AbstractCegarLoop]: === Iteration 17 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:29,372 INFO L82 PathProgramCache]: Analyzing trace with hash -1253296416, now seen corresponding path program 16 times [2018-07-23 13:36:29,372 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:29,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:29,498 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 136 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:29,498 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:29,499 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18] total 18 [2018-07-23 13:36:29,499 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:29,499 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:29,500 INFO L185 omatonBuilderFactory]: Interpolants [1059#true, 1060#false, 1061#(<= (+ GateController_time 1000) GateController_thousand), 1062#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 1063#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 1064#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 1065#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 1066#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 1067#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 1068#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 1069#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 1070#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 1071#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 1072#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 1073#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 1074#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 1075#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 1076#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 1077#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 1078#GateController_alarm] [2018-07-23 13:36:29,500 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 136 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:29,500 INFO L450 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-07-23 13:36:29,501 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-07-23 13:36:29,501 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=189, Invalid=191, Unknown=0, NotChecked=0, Total=380 [2018-07-23 13:36:29,501 INFO L87 Difference]: Start difference. First operand 20 states and 20 transitions. Second operand 20 states. [2018-07-23 13:36:29,525 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:29,526 INFO L93 Difference]: Finished difference Result 23 states and 23 transitions. [2018-07-23 13:36:29,526 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-07-23 13:36:29,526 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 19 [2018-07-23 13:36:29,526 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:29,527 INFO L225 Difference]: With dead ends: 23 [2018-07-23 13:36:29,527 INFO L226 Difference]: Without dead ends: 21 [2018-07-23 13:36:29,528 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 31 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=189, Invalid=191, Unknown=0, NotChecked=0, Total=380 [2018-07-23 13:36:29,528 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states. [2018-07-23 13:36:29,531 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2018-07-23 13:36:29,532 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2018-07-23 13:36:29,532 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 21 transitions. [2018-07-23 13:36:29,532 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 21 transitions. Word has length 19 [2018-07-23 13:36:29,533 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:29,533 INFO L471 AbstractCegarLoop]: Abstraction has 21 states and 21 transitions. [2018-07-23 13:36:29,533 INFO L472 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-07-23 13:36:29,533 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 21 transitions. [2018-07-23 13:36:29,534 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-07-23 13:36:29,534 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:29,534 INFO L357 BasicCegarLoop]: trace histogram [17, 1, 1, 1] [2018-07-23 13:36:29,534 INFO L414 AbstractCegarLoop]: === Iteration 18 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:29,534 INFO L82 PathProgramCache]: Analyzing trace with hash -197473632, now seen corresponding path program 17 times [2018-07-23 13:36:29,535 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:29,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:29,663 INFO L134 CoverageAnalysis]: Checked inductivity of 153 backedges. 0 proven. 153 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:29,664 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:29,665 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19] total 19 [2018-07-23 13:36:29,665 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:29,665 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:29,666 INFO L185 omatonBuilderFactory]: Interpolants [1184#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 1185#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 1186#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 1187#GateController_alarm, 1167#true, 1168#false, 1169#(<= (+ GateController_time 1000) GateController_thousand), 1170#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 1171#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 1172#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 1173#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 1174#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 1175#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 1176#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 1177#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 1178#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 1179#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 1180#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 1181#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 1182#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 1183#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand))] [2018-07-23 13:36:29,666 INFO L134 CoverageAnalysis]: Checked inductivity of 153 backedges. 0 proven. 153 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:29,666 INFO L450 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-07-23 13:36:29,667 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-07-23 13:36:29,667 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=209, Invalid=211, Unknown=0, NotChecked=0, Total=420 [2018-07-23 13:36:29,667 INFO L87 Difference]: Start difference. First operand 21 states and 21 transitions. Second operand 21 states. [2018-07-23 13:36:29,709 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:29,709 INFO L93 Difference]: Finished difference Result 24 states and 24 transitions. [2018-07-23 13:36:29,709 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-07-23 13:36:29,710 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 20 [2018-07-23 13:36:29,710 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:29,710 INFO L225 Difference]: With dead ends: 24 [2018-07-23 13:36:29,711 INFO L226 Difference]: Without dead ends: 22 [2018-07-23 13:36:29,711 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 33 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=209, Invalid=211, Unknown=0, NotChecked=0, Total=420 [2018-07-23 13:36:29,712 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2018-07-23 13:36:29,720 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2018-07-23 13:36:29,721 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22 states. [2018-07-23 13:36:29,721 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 22 transitions. [2018-07-23 13:36:29,724 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 22 transitions. Word has length 20 [2018-07-23 13:36:29,725 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:29,725 INFO L471 AbstractCegarLoop]: Abstraction has 22 states and 22 transitions. [2018-07-23 13:36:29,725 INFO L472 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-07-23 13:36:29,725 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 22 transitions. [2018-07-23 13:36:29,726 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-07-23 13:36:29,726 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:29,726 INFO L357 BasicCegarLoop]: trace histogram [18, 1, 1, 1] [2018-07-23 13:36:29,726 INFO L414 AbstractCegarLoop]: === Iteration 19 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:29,727 INFO L82 PathProgramCache]: Analyzing trace with hash -1826705696, now seen corresponding path program 18 times [2018-07-23 13:36:29,728 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:29,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:29,898 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 0 proven. 171 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:29,898 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:29,898 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20] total 20 [2018-07-23 13:36:29,899 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:29,899 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:29,900 INFO L185 omatonBuilderFactory]: Interpolants [1280#true, 1281#false, 1282#(<= (+ GateController_time 1000) GateController_thousand), 1283#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 1284#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 1285#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 1286#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 1287#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 1288#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 1289#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 1290#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 1291#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 1292#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 1293#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 1294#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 1295#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 1296#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 1297#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 1298#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 1299#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 1300#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 1301#GateController_alarm] [2018-07-23 13:36:29,900 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 0 proven. 171 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:29,900 INFO L450 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-07-23 13:36:29,901 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-07-23 13:36:29,901 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=230, Invalid=232, Unknown=0, NotChecked=0, Total=462 [2018-07-23 13:36:29,902 INFO L87 Difference]: Start difference. First operand 22 states and 22 transitions. Second operand 22 states. [2018-07-23 13:36:29,928 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:29,929 INFO L93 Difference]: Finished difference Result 25 states and 25 transitions. [2018-07-23 13:36:29,929 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-07-23 13:36:29,929 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 21 [2018-07-23 13:36:29,930 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:29,930 INFO L225 Difference]: With dead ends: 25 [2018-07-23 13:36:29,930 INFO L226 Difference]: Without dead ends: 23 [2018-07-23 13:36:29,931 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 35 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=230, Invalid=232, Unknown=0, NotChecked=0, Total=462 [2018-07-23 13:36:29,931 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23 states. [2018-07-23 13:36:29,938 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23 to 23. [2018-07-23 13:36:29,938 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23 states. [2018-07-23 13:36:29,939 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23 states to 23 states and 23 transitions. [2018-07-23 13:36:29,939 INFO L78 Accepts]: Start accepts. Automaton has 23 states and 23 transitions. Word has length 21 [2018-07-23 13:36:29,940 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:29,941 INFO L471 AbstractCegarLoop]: Abstraction has 23 states and 23 transitions. [2018-07-23 13:36:29,941 INFO L472 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-07-23 13:36:29,941 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states and 23 transitions. [2018-07-23 13:36:29,941 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-07-23 13:36:29,942 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:29,942 INFO L357 BasicCegarLoop]: trace histogram [19, 1, 1, 1] [2018-07-23 13:36:29,942 INFO L414 AbstractCegarLoop]: === Iteration 20 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:29,942 INFO L82 PathProgramCache]: Analyzing trace with hash -793292128, now seen corresponding path program 19 times [2018-07-23 13:36:29,942 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:29,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:30,093 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:30,094 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:30,094 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21] total 21 [2018-07-23 13:36:30,094 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:30,094 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:30,095 INFO L185 omatonBuilderFactory]: Interpolants [1408#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 1409#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 1410#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 1411#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 1412#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 1413#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 1414#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 1415#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 1416#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 1417#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 1418#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 1419#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 1420#GateController_alarm, 1398#true, 1399#false, 1400#(<= (+ GateController_time 1000) GateController_thousand), 1401#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 1402#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 1403#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 1404#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 1405#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 1406#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 1407#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand))] [2018-07-23 13:36:30,097 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:30,097 INFO L450 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-07-23 13:36:30,098 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-07-23 13:36:30,098 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=252, Invalid=254, Unknown=0, NotChecked=0, Total=506 [2018-07-23 13:36:30,098 INFO L87 Difference]: Start difference. First operand 23 states and 23 transitions. Second operand 23 states. [2018-07-23 13:36:30,128 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:30,128 INFO L93 Difference]: Finished difference Result 26 states and 26 transitions. [2018-07-23 13:36:30,128 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-07-23 13:36:30,129 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 22 [2018-07-23 13:36:30,129 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:30,129 INFO L225 Difference]: With dead ends: 26 [2018-07-23 13:36:30,129 INFO L226 Difference]: Without dead ends: 24 [2018-07-23 13:36:30,130 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 37 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=252, Invalid=254, Unknown=0, NotChecked=0, Total=506 [2018-07-23 13:36:30,132 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24 states. [2018-07-23 13:36:30,136 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24 to 24. [2018-07-23 13:36:30,136 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24 states. [2018-07-23 13:36:30,137 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 24 transitions. [2018-07-23 13:36:30,137 INFO L78 Accepts]: Start accepts. Automaton has 24 states and 24 transitions. Word has length 22 [2018-07-23 13:36:30,138 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:30,138 INFO L471 AbstractCegarLoop]: Abstraction has 24 states and 24 transitions. [2018-07-23 13:36:30,139 INFO L472 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-07-23 13:36:30,139 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 24 transitions. [2018-07-23 13:36:30,139 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-07-23 13:36:30,140 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:30,140 INFO L357 BasicCegarLoop]: trace histogram [20, 1, 1, 1] [2018-07-23 13:36:30,140 INFO L414 AbstractCegarLoop]: === Iteration 21 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:30,142 INFO L82 PathProgramCache]: Analyzing trace with hash 1177757408, now seen corresponding path program 20 times [2018-07-23 13:36:30,142 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:30,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:30,311 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 0 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:30,311 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:30,311 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22] total 22 [2018-07-23 13:36:30,312 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:30,312 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:30,313 INFO L185 omatonBuilderFactory]: Interpolants [1536#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 1537#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 1538#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 1539#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 1540#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 1541#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 1542#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 1543#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 1544#GateController_alarm, 1521#true, 1522#false, 1523#(<= (+ GateController_time 1000) GateController_thousand), 1524#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 1525#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 1526#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 1527#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 1528#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 1529#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 1530#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 1531#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 1532#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 1533#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 1534#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 1535#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand))] [2018-07-23 13:36:30,313 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 0 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:30,313 INFO L450 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-07-23 13:36:30,314 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-07-23 13:36:30,314 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=275, Invalid=277, Unknown=0, NotChecked=0, Total=552 [2018-07-23 13:36:30,318 INFO L87 Difference]: Start difference. First operand 24 states and 24 transitions. Second operand 24 states. [2018-07-23 13:36:30,358 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:30,358 INFO L93 Difference]: Finished difference Result 27 states and 27 transitions. [2018-07-23 13:36:30,359 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-07-23 13:36:30,359 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 23 [2018-07-23 13:36:30,359 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:30,360 INFO L225 Difference]: With dead ends: 27 [2018-07-23 13:36:30,360 INFO L226 Difference]: Without dead ends: 25 [2018-07-23 13:36:30,361 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 39 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=275, Invalid=277, Unknown=0, NotChecked=0, Total=552 [2018-07-23 13:36:30,361 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2018-07-23 13:36:30,367 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2018-07-23 13:36:30,368 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2018-07-23 13:36:30,368 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 25 transitions. [2018-07-23 13:36:30,369 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 25 transitions. Word has length 23 [2018-07-23 13:36:30,369 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:30,369 INFO L471 AbstractCegarLoop]: Abstraction has 25 states and 25 transitions. [2018-07-23 13:36:30,369 INFO L472 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-07-23 13:36:30,369 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 25 transitions. [2018-07-23 13:36:30,370 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-07-23 13:36:30,373 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:30,373 INFO L357 BasicCegarLoop]: trace histogram [21, 1, 1, 1] [2018-07-23 13:36:30,374 INFO L414 AbstractCegarLoop]: === Iteration 22 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:30,374 INFO L82 PathProgramCache]: Analyzing trace with hash -2144216416, now seen corresponding path program 21 times [2018-07-23 13:36:30,374 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:30,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:30,548 INFO L134 CoverageAnalysis]: Checked inductivity of 231 backedges. 0 proven. 231 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:30,548 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:30,548 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23] total 23 [2018-07-23 13:36:30,549 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:30,549 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:30,550 INFO L185 omatonBuilderFactory]: Interpolants [1664#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 1665#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 1666#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 1667#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 1668#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 1669#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 1670#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 1671#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 1672#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 1673#GateController_alarm, 1649#true, 1650#false, 1651#(<= (+ GateController_time 1000) GateController_thousand), 1652#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 1653#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 1654#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 1655#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 1656#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 1657#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 1658#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 1659#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 1660#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 1661#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 1662#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 1663#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand))] [2018-07-23 13:36:30,550 INFO L134 CoverageAnalysis]: Checked inductivity of 231 backedges. 0 proven. 231 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:30,550 INFO L450 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-07-23 13:36:30,551 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-07-23 13:36:30,551 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=299, Invalid=301, Unknown=0, NotChecked=0, Total=600 [2018-07-23 13:36:30,552 INFO L87 Difference]: Start difference. First operand 25 states and 25 transitions. Second operand 25 states. [2018-07-23 13:36:30,584 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:30,584 INFO L93 Difference]: Finished difference Result 28 states and 28 transitions. [2018-07-23 13:36:30,585 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-07-23 13:36:30,585 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 24 [2018-07-23 13:36:30,585 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:30,587 INFO L225 Difference]: With dead ends: 28 [2018-07-23 13:36:30,587 INFO L226 Difference]: Without dead ends: 26 [2018-07-23 13:36:30,588 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 41 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=299, Invalid=301, Unknown=0, NotChecked=0, Total=600 [2018-07-23 13:36:30,588 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26 states. [2018-07-23 13:36:30,597 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26 to 26. [2018-07-23 13:36:30,598 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26 states. [2018-07-23 13:36:30,598 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 26 transitions. [2018-07-23 13:36:30,598 INFO L78 Accepts]: Start accepts. Automaton has 26 states and 26 transitions. Word has length 24 [2018-07-23 13:36:30,599 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:30,599 INFO L471 AbstractCegarLoop]: Abstraction has 26 states and 26 transitions. [2018-07-23 13:36:30,599 INFO L472 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-07-23 13:36:30,599 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 26 transitions. [2018-07-23 13:36:30,600 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-07-23 13:36:30,600 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:30,600 INFO L357 BasicCegarLoop]: trace histogram [22, 1, 1, 1] [2018-07-23 13:36:30,600 INFO L414 AbstractCegarLoop]: === Iteration 23 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:30,601 INFO L82 PathProgramCache]: Analyzing trace with hash -2046189856, now seen corresponding path program 22 times [2018-07-23 13:36:30,601 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:30,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:30,787 INFO L134 CoverageAnalysis]: Checked inductivity of 253 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:30,788 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:30,788 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24] total 24 [2018-07-23 13:36:30,788 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:30,788 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:30,789 INFO L185 omatonBuilderFactory]: Interpolants [1792#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 1793#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 1794#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 1795#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 1796#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 1797#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 1798#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 1799#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 1800#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 1801#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 1802#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 1803#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 1804#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 1805#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 1806#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 1807#GateController_alarm, 1782#true, 1783#false, 1784#(<= (+ GateController_time 1000) GateController_thousand), 1785#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 1786#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 1787#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 1788#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 1789#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 1790#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 1791#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand))] [2018-07-23 13:36:30,789 INFO L134 CoverageAnalysis]: Checked inductivity of 253 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:30,790 INFO L450 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-07-23 13:36:30,790 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-07-23 13:36:30,791 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=324, Invalid=326, Unknown=0, NotChecked=0, Total=650 [2018-07-23 13:36:30,791 INFO L87 Difference]: Start difference. First operand 26 states and 26 transitions. Second operand 26 states. [2018-07-23 13:36:30,820 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:30,820 INFO L93 Difference]: Finished difference Result 29 states and 29 transitions. [2018-07-23 13:36:30,820 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-07-23 13:36:30,821 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 25 [2018-07-23 13:36:30,821 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:30,821 INFO L225 Difference]: With dead ends: 29 [2018-07-23 13:36:30,821 INFO L226 Difference]: Without dead ends: 27 [2018-07-23 13:36:30,822 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 43 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=324, Invalid=326, Unknown=0, NotChecked=0, Total=650 [2018-07-23 13:36:30,822 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states. [2018-07-23 13:36:30,828 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 27. [2018-07-23 13:36:30,828 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27 states. [2018-07-23 13:36:30,829 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 27 transitions. [2018-07-23 13:36:30,830 INFO L78 Accepts]: Start accepts. Automaton has 27 states and 27 transitions. Word has length 25 [2018-07-23 13:36:30,830 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:30,830 INFO L471 AbstractCegarLoop]: Abstraction has 27 states and 27 transitions. [2018-07-23 13:36:30,830 INFO L472 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-07-23 13:36:30,830 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states and 27 transitions. [2018-07-23 13:36:30,831 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-07-23 13:36:30,831 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:30,831 INFO L357 BasicCegarLoop]: trace histogram [23, 1, 1, 1] [2018-07-23 13:36:30,832 INFO L414 AbstractCegarLoop]: === Iteration 24 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:30,833 INFO L82 PathProgramCache]: Analyzing trace with hash 992633504, now seen corresponding path program 23 times [2018-07-23 13:36:30,833 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:30,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:31,005 INFO L134 CoverageAnalysis]: Checked inductivity of 276 backedges. 0 proven. 276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:31,005 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:31,005 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25] total 25 [2018-07-23 13:36:31,006 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:31,006 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:31,006 INFO L185 omatonBuilderFactory]: Interpolants [1920#true, 1921#false, 1922#(<= (+ GateController_time 1000) GateController_thousand), 1923#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 1924#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 1925#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 1926#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 1927#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 1928#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 1929#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 1930#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 1931#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 1932#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 1933#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 1934#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 1935#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 1936#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 1937#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 1938#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 1939#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 1940#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 1941#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 1942#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 1943#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 1944#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 1945#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 1946#GateController_alarm] [2018-07-23 13:36:31,007 INFO L134 CoverageAnalysis]: Checked inductivity of 276 backedges. 0 proven. 276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:31,007 INFO L450 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-07-23 13:36:31,008 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-07-23 13:36:31,008 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=350, Invalid=352, Unknown=0, NotChecked=0, Total=702 [2018-07-23 13:36:31,008 INFO L87 Difference]: Start difference. First operand 27 states and 27 transitions. Second operand 27 states. [2018-07-23 13:36:31,042 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:31,043 INFO L93 Difference]: Finished difference Result 30 states and 30 transitions. [2018-07-23 13:36:31,043 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-07-23 13:36:31,043 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 26 [2018-07-23 13:36:31,043 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:31,044 INFO L225 Difference]: With dead ends: 30 [2018-07-23 13:36:31,044 INFO L226 Difference]: Without dead ends: 28 [2018-07-23 13:36:31,048 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 45 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=350, Invalid=352, Unknown=0, NotChecked=0, Total=702 [2018-07-23 13:36:31,048 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states. [2018-07-23 13:36:31,053 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 28. [2018-07-23 13:36:31,053 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28 states. [2018-07-23 13:36:31,054 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 28 transitions. [2018-07-23 13:36:31,054 INFO L78 Accepts]: Start accepts. Automaton has 28 states and 28 transitions. Word has length 26 [2018-07-23 13:36:31,054 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:31,057 INFO L471 AbstractCegarLoop]: Abstraction has 28 states and 28 transitions. [2018-07-23 13:36:31,057 INFO L472 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-07-23 13:36:31,058 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 28 transitions. [2018-07-23 13:36:31,058 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-07-23 13:36:31,058 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:31,058 INFO L357 BasicCegarLoop]: trace histogram [24, 1, 1, 1] [2018-07-23 13:36:31,059 INFO L414 AbstractCegarLoop]: === Iteration 25 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:31,059 INFO L82 PathProgramCache]: Analyzing trace with hash 706877152, now seen corresponding path program 24 times [2018-07-23 13:36:31,061 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:31,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:31,334 INFO L134 CoverageAnalysis]: Checked inductivity of 300 backedges. 0 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:31,335 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:31,335 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26] total 26 [2018-07-23 13:36:31,335 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:31,335 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:31,336 INFO L185 omatonBuilderFactory]: Interpolants [2063#true, 2064#false, 2065#(<= (+ GateController_time 1000) GateController_thousand), 2066#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 2067#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 2068#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 2069#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 2070#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 2071#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 2072#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 2073#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 2074#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 2075#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 2076#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 2077#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 2078#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 2079#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 2080#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 2081#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 2082#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 2083#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 2084#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 2085#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 2086#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 2087#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 2088#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 2089#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 2090#GateController_alarm] [2018-07-23 13:36:31,336 INFO L134 CoverageAnalysis]: Checked inductivity of 300 backedges. 0 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:31,337 INFO L450 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-07-23 13:36:31,337 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-07-23 13:36:31,337 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=377, Invalid=379, Unknown=0, NotChecked=0, Total=756 [2018-07-23 13:36:31,338 INFO L87 Difference]: Start difference. First operand 28 states and 28 transitions. Second operand 28 states. [2018-07-23 13:36:31,368 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:31,368 INFO L93 Difference]: Finished difference Result 31 states and 31 transitions. [2018-07-23 13:36:31,368 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-07-23 13:36:31,368 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 27 [2018-07-23 13:36:31,369 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:31,369 INFO L225 Difference]: With dead ends: 31 [2018-07-23 13:36:31,369 INFO L226 Difference]: Without dead ends: 29 [2018-07-23 13:36:31,370 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 26 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 47 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=377, Invalid=379, Unknown=0, NotChecked=0, Total=756 [2018-07-23 13:36:31,370 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states. [2018-07-23 13:36:31,376 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 29. [2018-07-23 13:36:31,377 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2018-07-23 13:36:31,377 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 29 transitions. [2018-07-23 13:36:31,377 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 29 transitions. Word has length 27 [2018-07-23 13:36:31,377 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:31,378 INFO L471 AbstractCegarLoop]: Abstraction has 29 states and 29 transitions. [2018-07-23 13:36:31,378 INFO L472 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-07-23 13:36:31,378 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 29 transitions. [2018-07-23 13:36:31,381 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-07-23 13:36:31,381 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:31,382 INFO L357 BasicCegarLoop]: trace histogram [25, 1, 1, 1] [2018-07-23 13:36:31,382 INFO L414 AbstractCegarLoop]: === Iteration 26 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:31,382 INFO L82 PathProgramCache]: Analyzing trace with hash 438364832, now seen corresponding path program 25 times [2018-07-23 13:36:31,382 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:31,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:31,569 INFO L134 CoverageAnalysis]: Checked inductivity of 325 backedges. 0 proven. 325 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:31,570 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:31,570 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27] total 27 [2018-07-23 13:36:31,570 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:31,570 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:31,571 INFO L185 omatonBuilderFactory]: Interpolants [2211#true, 2212#false, 2213#(<= (+ GateController_time 1000) GateController_thousand), 2214#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 2215#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 2216#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 2217#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 2218#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 2219#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 2220#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 2221#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 2222#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 2223#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 2224#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 2225#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 2226#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 2227#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 2228#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 2229#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 2230#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 2231#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 2232#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 2233#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 2234#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 2235#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 2236#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 2237#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 2238#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 2239#GateController_alarm] [2018-07-23 13:36:31,571 INFO L134 CoverageAnalysis]: Checked inductivity of 325 backedges. 0 proven. 325 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:31,572 INFO L450 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-07-23 13:36:31,572 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-07-23 13:36:31,572 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=405, Invalid=407, Unknown=0, NotChecked=0, Total=812 [2018-07-23 13:36:31,573 INFO L87 Difference]: Start difference. First operand 29 states and 29 transitions. Second operand 29 states. [2018-07-23 13:36:31,605 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:31,606 INFO L93 Difference]: Finished difference Result 32 states and 32 transitions. [2018-07-23 13:36:31,606 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-07-23 13:36:31,606 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 28 [2018-07-23 13:36:31,606 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:31,607 INFO L225 Difference]: With dead ends: 32 [2018-07-23 13:36:31,607 INFO L226 Difference]: Without dead ends: 30 [2018-07-23 13:36:31,608 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 49 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=405, Invalid=407, Unknown=0, NotChecked=0, Total=812 [2018-07-23 13:36:31,608 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30 states. [2018-07-23 13:36:31,611 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30 to 30. [2018-07-23 13:36:31,612 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30 states. [2018-07-23 13:36:31,612 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 30 transitions. [2018-07-23 13:36:31,612 INFO L78 Accepts]: Start accepts. Automaton has 30 states and 30 transitions. Word has length 28 [2018-07-23 13:36:31,612 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:31,613 INFO L471 AbstractCegarLoop]: Abstraction has 30 states and 30 transitions. [2018-07-23 13:36:31,613 INFO L472 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-07-23 13:36:31,613 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 30 transitions. [2018-07-23 13:36:31,613 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-07-23 13:36:31,614 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:31,614 INFO L357 BasicCegarLoop]: trace histogram [26, 1, 1, 1] [2018-07-23 13:36:31,614 INFO L414 AbstractCegarLoop]: === Iteration 27 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:31,614 INFO L82 PathProgramCache]: Analyzing trace with hash 704417504, now seen corresponding path program 26 times [2018-07-23 13:36:31,614 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:31,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:31,828 INFO L134 CoverageAnalysis]: Checked inductivity of 351 backedges. 0 proven. 351 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:31,829 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:31,829 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28] total 28 [2018-07-23 13:36:31,829 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:31,829 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:31,830 INFO L185 omatonBuilderFactory]: Interpolants [2368#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 2369#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 2370#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 2371#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 2372#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 2373#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 2374#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 2375#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 2376#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 2377#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 2378#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 2379#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 2380#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 2381#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 2382#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 2383#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 2384#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 2385#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 2386#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 2387#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 2388#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 2389#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 2390#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 2391#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 2392#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 2393#GateController_alarm, 2364#true, 2365#false, 2366#(<= (+ GateController_time 1000) GateController_thousand), 2367#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand))] [2018-07-23 13:36:31,830 INFO L134 CoverageAnalysis]: Checked inductivity of 351 backedges. 0 proven. 351 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:31,831 INFO L450 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-07-23 13:36:31,831 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-07-23 13:36:31,831 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=434, Invalid=436, Unknown=0, NotChecked=0, Total=870 [2018-07-23 13:36:31,832 INFO L87 Difference]: Start difference. First operand 30 states and 30 transitions. Second operand 30 states. [2018-07-23 13:36:31,871 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:31,871 INFO L93 Difference]: Finished difference Result 33 states and 33 transitions. [2018-07-23 13:36:31,871 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-07-23 13:36:31,871 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 29 [2018-07-23 13:36:31,872 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:31,872 INFO L225 Difference]: With dead ends: 33 [2018-07-23 13:36:31,872 INFO L226 Difference]: Without dead ends: 31 [2018-07-23 13:36:31,873 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 28 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 51 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=434, Invalid=436, Unknown=0, NotChecked=0, Total=870 [2018-07-23 13:36:31,873 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31 states. [2018-07-23 13:36:31,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31 to 31. [2018-07-23 13:36:31,878 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31 states. [2018-07-23 13:36:31,879 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 31 transitions. [2018-07-23 13:36:31,879 INFO L78 Accepts]: Start accepts. Automaton has 31 states and 31 transitions. Word has length 29 [2018-07-23 13:36:31,879 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:31,879 INFO L471 AbstractCegarLoop]: Abstraction has 31 states and 31 transitions. [2018-07-23 13:36:31,879 INFO L472 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-07-23 13:36:31,880 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states and 31 transitions. [2018-07-23 13:36:31,880 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2018-07-23 13:36:31,880 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:31,880 INFO L357 BasicCegarLoop]: trace histogram [27, 1, 1, 1] [2018-07-23 13:36:31,880 INFO L414 AbstractCegarLoop]: === Iteration 28 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:31,881 INFO L82 PathProgramCache]: Analyzing trace with hash 362115744, now seen corresponding path program 27 times [2018-07-23 13:36:31,881 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:31,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:32,100 INFO L134 CoverageAnalysis]: Checked inductivity of 378 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:32,100 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:32,101 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29] total 29 [2018-07-23 13:36:32,101 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:32,101 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:32,102 INFO L185 omatonBuilderFactory]: Interpolants [2522#true, 2523#false, 2524#(<= (+ GateController_time 1000) GateController_thousand), 2525#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 2526#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 2527#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 2528#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 2529#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 2530#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 2531#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 2532#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 2533#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 2534#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 2535#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 2536#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 2537#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 2538#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 2539#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 2540#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 2541#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 2542#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 2543#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 2544#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 2545#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 2546#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 2547#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 2548#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 2549#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 2550#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 2551#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 2552#GateController_alarm] [2018-07-23 13:36:32,102 INFO L134 CoverageAnalysis]: Checked inductivity of 378 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:32,103 INFO L450 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-07-23 13:36:32,103 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-07-23 13:36:32,108 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=464, Invalid=466, Unknown=0, NotChecked=0, Total=930 [2018-07-23 13:36:32,108 INFO L87 Difference]: Start difference. First operand 31 states and 31 transitions. Second operand 31 states. [2018-07-23 13:36:32,138 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:32,138 INFO L93 Difference]: Finished difference Result 34 states and 34 transitions. [2018-07-23 13:36:32,138 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-07-23 13:36:32,139 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 30 [2018-07-23 13:36:32,139 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:32,139 INFO L225 Difference]: With dead ends: 34 [2018-07-23 13:36:32,139 INFO L226 Difference]: Without dead ends: 32 [2018-07-23 13:36:32,140 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 29 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 53 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=464, Invalid=466, Unknown=0, NotChecked=0, Total=930 [2018-07-23 13:36:32,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states. [2018-07-23 13:36:32,148 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 32. [2018-07-23 13:36:32,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 32 states. [2018-07-23 13:36:32,149 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 32 transitions. [2018-07-23 13:36:32,149 INFO L78 Accepts]: Start accepts. Automaton has 32 states and 32 transitions. Word has length 30 [2018-07-23 13:36:32,152 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:32,152 INFO L471 AbstractCegarLoop]: Abstraction has 32 states and 32 transitions. [2018-07-23 13:36:32,152 INFO L472 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-07-23 13:36:32,152 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 32 transitions. [2018-07-23 13:36:32,152 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2018-07-23 13:36:32,153 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:32,153 INFO L357 BasicCegarLoop]: trace histogram [28, 1, 1, 1] [2018-07-23 13:36:32,153 INFO L414 AbstractCegarLoop]: === Iteration 29 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:32,153 INFO L82 PathProgramCache]: Analyzing trace with hash -1659304224, now seen corresponding path program 28 times [2018-07-23 13:36:32,153 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:32,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:32,392 INFO L134 CoverageAnalysis]: Checked inductivity of 406 backedges. 0 proven. 406 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:32,392 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:32,393 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30] total 30 [2018-07-23 13:36:32,393 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:32,393 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:32,393 INFO L185 omatonBuilderFactory]: Interpolants [2688#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 2689#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 2690#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 2691#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 2692#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 2693#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 2694#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 2695#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 2696#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 2697#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 2698#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 2699#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 2700#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 2701#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 2702#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 2703#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 2704#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 2705#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 2706#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 2707#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 2708#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 2709#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 2710#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 2711#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 2712#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 2713#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 2714#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 2715#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 2716#GateController_alarm, 2685#true, 2686#false, 2687#(<= (+ GateController_time 1000) GateController_thousand)] [2018-07-23 13:36:32,394 INFO L134 CoverageAnalysis]: Checked inductivity of 406 backedges. 0 proven. 406 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:32,394 INFO L450 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-07-23 13:36:32,395 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-07-23 13:36:32,395 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=495, Invalid=497, Unknown=0, NotChecked=0, Total=992 [2018-07-23 13:36:32,395 INFO L87 Difference]: Start difference. First operand 32 states and 32 transitions. Second operand 32 states. [2018-07-23 13:36:32,427 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:32,427 INFO L93 Difference]: Finished difference Result 35 states and 35 transitions. [2018-07-23 13:36:32,427 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-07-23 13:36:32,427 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 31 [2018-07-23 13:36:32,427 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:32,428 INFO L225 Difference]: With dead ends: 35 [2018-07-23 13:36:32,428 INFO L226 Difference]: Without dead ends: 33 [2018-07-23 13:36:32,429 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 55 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=495, Invalid=497, Unknown=0, NotChecked=0, Total=992 [2018-07-23 13:36:32,429 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33 states. [2018-07-23 13:36:32,438 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33 to 33. [2018-07-23 13:36:32,438 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33 states. [2018-07-23 13:36:32,438 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 33 transitions. [2018-07-23 13:36:32,439 INFO L78 Accepts]: Start accepts. Automaton has 33 states and 33 transitions. Word has length 31 [2018-07-23 13:36:32,439 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:32,439 INFO L471 AbstractCegarLoop]: Abstraction has 33 states and 33 transitions. [2018-07-23 13:36:32,439 INFO L472 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-07-23 13:36:32,439 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 33 transitions. [2018-07-23 13:36:32,440 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-07-23 13:36:32,440 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:32,440 INFO L357 BasicCegarLoop]: trace histogram [29, 1, 1, 1] [2018-07-23 13:36:32,440 INFO L414 AbstractCegarLoop]: === Iteration 30 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:32,440 INFO L82 PathProgramCache]: Analyzing trace with hash 101186208, now seen corresponding path program 29 times [2018-07-23 13:36:32,440 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:32,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:32,696 INFO L134 CoverageAnalysis]: Checked inductivity of 435 backedges. 0 proven. 435 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:32,696 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:32,696 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31] total 31 [2018-07-23 13:36:32,696 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:32,697 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:32,697 INFO L185 omatonBuilderFactory]: Interpolants [2880#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 2881#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 2882#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 2883#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 2884#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 2885#GateController_alarm, 2853#true, 2854#false, 2855#(<= (+ GateController_time 1000) GateController_thousand), 2856#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 2857#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 2858#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 2859#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 2860#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 2861#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 2862#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 2863#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 2864#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 2865#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 2866#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 2867#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 2868#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 2869#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 2870#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 2871#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 2872#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 2873#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 2874#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 2875#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 2876#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 2877#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 2878#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 2879#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand))] [2018-07-23 13:36:32,698 INFO L134 CoverageAnalysis]: Checked inductivity of 435 backedges. 0 proven. 435 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:32,698 INFO L450 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-07-23 13:36:32,698 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-07-23 13:36:32,699 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=527, Invalid=529, Unknown=0, NotChecked=0, Total=1056 [2018-07-23 13:36:32,699 INFO L87 Difference]: Start difference. First operand 33 states and 33 transitions. Second operand 33 states. [2018-07-23 13:36:32,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:32,724 INFO L93 Difference]: Finished difference Result 36 states and 36 transitions. [2018-07-23 13:36:32,724 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-07-23 13:36:32,724 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 32 [2018-07-23 13:36:32,725 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:32,725 INFO L225 Difference]: With dead ends: 36 [2018-07-23 13:36:32,725 INFO L226 Difference]: Without dead ends: 34 [2018-07-23 13:36:32,726 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 31 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 57 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=527, Invalid=529, Unknown=0, NotChecked=0, Total=1056 [2018-07-23 13:36:32,726 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states. [2018-07-23 13:36:32,733 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 34. [2018-07-23 13:36:32,733 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 34 states. [2018-07-23 13:36:32,734 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 34 transitions. [2018-07-23 13:36:32,734 INFO L78 Accepts]: Start accepts. Automaton has 34 states and 34 transitions. Word has length 32 [2018-07-23 13:36:32,734 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:32,734 INFO L471 AbstractCegarLoop]: Abstraction has 34 states and 34 transitions. [2018-07-23 13:36:32,734 INFO L472 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-07-23 13:36:32,735 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 34 transitions. [2018-07-23 13:36:32,735 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-07-23 13:36:32,735 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:32,735 INFO L357 BasicCegarLoop]: trace histogram [30, 1, 1, 1] [2018-07-23 13:36:32,735 INFO L414 AbstractCegarLoop]: === Iteration 31 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:32,736 INFO L82 PathProgramCache]: Analyzing trace with hash -1158185248, now seen corresponding path program 30 times [2018-07-23 13:36:32,736 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:32,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:32,984 INFO L134 CoverageAnalysis]: Checked inductivity of 465 backedges. 0 proven. 465 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:32,985 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:32,985 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32] total 32 [2018-07-23 13:36:32,985 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:32,985 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:32,986 INFO L185 omatonBuilderFactory]: Interpolants [3026#true, 3027#false, 3028#(<= (+ GateController_time 1000) GateController_thousand), 3029#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 3030#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 3031#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 3032#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 3033#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 3034#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 3035#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 3036#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 3037#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 3038#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 3039#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 3040#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 3041#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 3042#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 3043#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 3044#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 3045#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 3046#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 3047#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 3048#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 3049#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 3050#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 3051#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 3052#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 3053#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 3054#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 3055#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 3056#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 3057#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 3058#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 3059#GateController_alarm] [2018-07-23 13:36:32,986 INFO L134 CoverageAnalysis]: Checked inductivity of 465 backedges. 0 proven. 465 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:32,987 INFO L450 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-07-23 13:36:32,987 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-07-23 13:36:32,988 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=560, Invalid=562, Unknown=0, NotChecked=0, Total=1122 [2018-07-23 13:36:32,988 INFO L87 Difference]: Start difference. First operand 34 states and 34 transitions. Second operand 34 states. [2018-07-23 13:36:33,020 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:33,020 INFO L93 Difference]: Finished difference Result 37 states and 37 transitions. [2018-07-23 13:36:33,021 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-07-23 13:36:33,021 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 33 [2018-07-23 13:36:33,021 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:33,021 INFO L225 Difference]: With dead ends: 37 [2018-07-23 13:36:33,022 INFO L226 Difference]: Without dead ends: 35 [2018-07-23 13:36:33,023 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 59 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=560, Invalid=562, Unknown=0, NotChecked=0, Total=1122 [2018-07-23 13:36:33,023 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35 states. [2018-07-23 13:36:33,027 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35 to 35. [2018-07-23 13:36:33,027 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 35 states. [2018-07-23 13:36:33,028 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35 states to 35 states and 35 transitions. [2018-07-23 13:36:33,028 INFO L78 Accepts]: Start accepts. Automaton has 35 states and 35 transitions. Word has length 33 [2018-07-23 13:36:33,028 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:33,028 INFO L471 AbstractCegarLoop]: Abstraction has 35 states and 35 transitions. [2018-07-23 13:36:33,028 INFO L472 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-07-23 13:36:33,028 INFO L276 IsEmpty]: Start isEmpty. Operand 35 states and 35 transitions. [2018-07-23 13:36:33,029 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-07-23 13:36:33,029 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:33,029 INFO L357 BasicCegarLoop]: trace histogram [31, 1, 1, 1] [2018-07-23 13:36:33,029 INFO L414 AbstractCegarLoop]: === Iteration 32 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:33,029 INFO L82 PathProgramCache]: Analyzing trace with hash -1543994720, now seen corresponding path program 31 times [2018-07-23 13:36:33,030 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:33,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:33,298 INFO L134 CoverageAnalysis]: Checked inductivity of 496 backedges. 0 proven. 496 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:33,298 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:33,298 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33] total 33 [2018-07-23 13:36:33,298 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:33,299 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:33,299 INFO L185 omatonBuilderFactory]: Interpolants [3204#true, 3205#false, 3206#(<= (+ GateController_time 1000) GateController_thousand), 3207#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 3208#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 3209#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 3210#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 3211#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 3212#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 3213#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 3214#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 3215#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 3216#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 3217#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 3218#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 3219#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 3220#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 3221#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 3222#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 3223#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 3224#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 3225#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 3226#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 3227#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 3228#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 3229#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 3230#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 3231#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 3232#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 3233#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 3234#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 3235#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 3236#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 3237#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 3238#GateController_alarm] [2018-07-23 13:36:33,300 INFO L134 CoverageAnalysis]: Checked inductivity of 496 backedges. 0 proven. 496 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:33,300 INFO L450 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-07-23 13:36:33,300 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-07-23 13:36:33,301 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=594, Invalid=596, Unknown=0, NotChecked=0, Total=1190 [2018-07-23 13:36:33,302 INFO L87 Difference]: Start difference. First operand 35 states and 35 transitions. Second operand 35 states. [2018-07-23 13:36:33,335 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:33,336 INFO L93 Difference]: Finished difference Result 38 states and 38 transitions. [2018-07-23 13:36:33,336 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-07-23 13:36:33,336 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 34 [2018-07-23 13:36:33,336 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:33,337 INFO L225 Difference]: With dead ends: 38 [2018-07-23 13:36:33,337 INFO L226 Difference]: Without dead ends: 36 [2018-07-23 13:36:33,338 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 61 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=594, Invalid=596, Unknown=0, NotChecked=0, Total=1190 [2018-07-23 13:36:33,338 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2018-07-23 13:36:33,347 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 36. [2018-07-23 13:36:33,347 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2018-07-23 13:36:33,347 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 36 transitions. [2018-07-23 13:36:33,348 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 36 transitions. Word has length 34 [2018-07-23 13:36:33,348 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:33,348 INFO L471 AbstractCegarLoop]: Abstraction has 36 states and 36 transitions. [2018-07-23 13:36:33,348 INFO L472 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-07-23 13:36:33,355 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 36 transitions. [2018-07-23 13:36:33,355 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-07-23 13:36:33,356 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:33,356 INFO L357 BasicCegarLoop]: trace histogram [32, 1, 1, 1] [2018-07-23 13:36:33,356 INFO L414 AbstractCegarLoop]: === Iteration 33 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:33,356 INFO L82 PathProgramCache]: Analyzing trace with hash -619186464, now seen corresponding path program 32 times [2018-07-23 13:36:33,356 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:33,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:33,643 INFO L134 CoverageAnalysis]: Checked inductivity of 528 backedges. 0 proven. 528 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:33,643 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:33,643 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34] total 34 [2018-07-23 13:36:33,644 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:33,644 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:33,644 INFO L185 omatonBuilderFactory]: Interpolants [3392#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 3393#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 3394#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 3395#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 3396#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 3397#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 3398#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 3399#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 3400#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 3401#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 3402#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 3403#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 3404#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 3405#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 3406#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 3407#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 3408#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 3409#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 3410#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 3411#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 3412#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 3413#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 3414#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 3415#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 3416#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 3417#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 3418#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 3419#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 3420#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 3421#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 3422#GateController_alarm, 3387#true, 3388#false, 3389#(<= (+ GateController_time 1000) GateController_thousand), 3390#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 3391#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand))] [2018-07-23 13:36:33,645 INFO L134 CoverageAnalysis]: Checked inductivity of 528 backedges. 0 proven. 528 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:33,645 INFO L450 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-07-23 13:36:33,648 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-07-23 13:36:33,649 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=629, Invalid=631, Unknown=0, NotChecked=0, Total=1260 [2018-07-23 13:36:33,649 INFO L87 Difference]: Start difference. First operand 36 states and 36 transitions. Second operand 36 states. [2018-07-23 13:36:33,684 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:33,684 INFO L93 Difference]: Finished difference Result 39 states and 39 transitions. [2018-07-23 13:36:33,685 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-07-23 13:36:33,685 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 35 [2018-07-23 13:36:33,685 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:33,685 INFO L225 Difference]: With dead ends: 39 [2018-07-23 13:36:33,685 INFO L226 Difference]: Without dead ends: 37 [2018-07-23 13:36:33,687 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 34 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 63 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=629, Invalid=631, Unknown=0, NotChecked=0, Total=1260 [2018-07-23 13:36:33,687 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states. [2018-07-23 13:36:33,691 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 37. [2018-07-23 13:36:33,691 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37 states. [2018-07-23 13:36:33,692 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 37 transitions. [2018-07-23 13:36:33,692 INFO L78 Accepts]: Start accepts. Automaton has 37 states and 37 transitions. Word has length 35 [2018-07-23 13:36:33,692 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:33,692 INFO L471 AbstractCegarLoop]: Abstraction has 37 states and 37 transitions. [2018-07-23 13:36:33,692 INFO L472 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-07-23 13:36:33,692 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 37 transitions. [2018-07-23 13:36:33,693 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-07-23 13:36:33,693 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:33,693 INFO L357 BasicCegarLoop]: trace histogram [33, 1, 1, 1] [2018-07-23 13:36:33,693 INFO L414 AbstractCegarLoop]: === Iteration 34 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:33,693 INFO L82 PathProgramCache]: Analyzing trace with hash -2014901600, now seen corresponding path program 33 times [2018-07-23 13:36:33,694 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:33,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:33,989 INFO L134 CoverageAnalysis]: Checked inductivity of 561 backedges. 0 proven. 561 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:33,990 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:33,990 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35] total 35 [2018-07-23 13:36:33,990 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:33,990 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:33,991 INFO L185 omatonBuilderFactory]: Interpolants [3584#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 3585#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 3586#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 3587#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 3588#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 3589#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 3590#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 3591#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 3592#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 3593#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 3594#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 3595#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 3596#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 3597#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 3598#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 3599#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 3600#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 3601#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 3602#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 3603#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 3604#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 3605#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 3606#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 3607#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 3608#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 3609#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 3610#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 3611#GateController_alarm, 3575#true, 3576#false, 3577#(<= (+ GateController_time 1000) GateController_thousand), 3578#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 3579#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 3580#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 3581#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 3582#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 3583#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand))] [2018-07-23 13:36:33,992 INFO L134 CoverageAnalysis]: Checked inductivity of 561 backedges. 0 proven. 561 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:33,992 INFO L450 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-07-23 13:36:33,992 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-07-23 13:36:33,993 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=665, Invalid=667, Unknown=0, NotChecked=0, Total=1332 [2018-07-23 13:36:33,993 INFO L87 Difference]: Start difference. First operand 37 states and 37 transitions. Second operand 37 states. [2018-07-23 13:36:34,028 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:34,028 INFO L93 Difference]: Finished difference Result 40 states and 40 transitions. [2018-07-23 13:36:34,028 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2018-07-23 13:36:34,028 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 36 [2018-07-23 13:36:34,028 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:34,029 INFO L225 Difference]: With dead ends: 40 [2018-07-23 13:36:34,029 INFO L226 Difference]: Without dead ends: 38 [2018-07-23 13:36:34,030 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 35 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 65 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=665, Invalid=667, Unknown=0, NotChecked=0, Total=1332 [2018-07-23 13:36:34,031 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38 states. [2018-07-23 13:36:34,035 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38 to 38. [2018-07-23 13:36:34,035 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38 states. [2018-07-23 13:36:34,035 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 38 transitions. [2018-07-23 13:36:34,036 INFO L78 Accepts]: Start accepts. Automaton has 38 states and 38 transitions. Word has length 36 [2018-07-23 13:36:34,036 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:34,036 INFO L471 AbstractCegarLoop]: Abstraction has 38 states and 38 transitions. [2018-07-23 13:36:34,036 INFO L472 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-07-23 13:36:34,036 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 38 transitions. [2018-07-23 13:36:34,037 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-07-23 13:36:34,037 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:34,037 INFO L357 BasicCegarLoop]: trace histogram [34, 1, 1, 1] [2018-07-23 13:36:34,037 INFO L414 AbstractCegarLoop]: === Iteration 35 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:34,037 INFO L82 PathProgramCache]: Analyzing trace with hash 1962569440, now seen corresponding path program 34 times [2018-07-23 13:36:34,038 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:34,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:34,352 INFO L134 CoverageAnalysis]: Checked inductivity of 595 backedges. 0 proven. 595 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:34,353 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:34,353 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36] total 36 [2018-07-23 13:36:34,353 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:34,354 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:34,355 INFO L185 omatonBuilderFactory]: Interpolants [3776#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 3777#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 3778#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 3779#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 3780#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 3781#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 3782#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 3783#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 3784#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 3785#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 3786#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 3787#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 3788#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 3789#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 3790#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 3791#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 3792#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 3793#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 3794#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 3795#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 3796#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 3797#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 3798#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 3799#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 3800#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 3801#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 3802#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 3803#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 3804#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 3805#GateController_alarm, 3768#true, 3769#false, 3770#(<= (+ GateController_time 1000) GateController_thousand), 3771#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 3772#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 3773#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 3774#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 3775#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand))] [2018-07-23 13:36:34,356 INFO L134 CoverageAnalysis]: Checked inductivity of 595 backedges. 0 proven. 595 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:34,356 INFO L450 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-07-23 13:36:34,357 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-07-23 13:36:34,357 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=702, Invalid=704, Unknown=0, NotChecked=0, Total=1406 [2018-07-23 13:36:34,358 INFO L87 Difference]: Start difference. First operand 38 states and 38 transitions. Second operand 38 states. [2018-07-23 13:36:34,394 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:34,395 INFO L93 Difference]: Finished difference Result 41 states and 41 transitions. [2018-07-23 13:36:34,395 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-07-23 13:36:34,395 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 37 [2018-07-23 13:36:34,395 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:34,396 INFO L225 Difference]: With dead ends: 41 [2018-07-23 13:36:34,396 INFO L226 Difference]: Without dead ends: 39 [2018-07-23 13:36:34,397 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 67 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=702, Invalid=704, Unknown=0, NotChecked=0, Total=1406 [2018-07-23 13:36:34,397 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states. [2018-07-23 13:36:34,408 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 39. [2018-07-23 13:36:34,409 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39 states. [2018-07-23 13:36:34,409 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 39 transitions. [2018-07-23 13:36:34,409 INFO L78 Accepts]: Start accepts. Automaton has 39 states and 39 transitions. Word has length 37 [2018-07-23 13:36:34,410 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:34,410 INFO L471 AbstractCegarLoop]: Abstraction has 39 states and 39 transitions. [2018-07-23 13:36:34,410 INFO L472 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-07-23 13:36:34,410 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 39 transitions. [2018-07-23 13:36:34,410 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-07-23 13:36:34,411 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:34,411 INFO L357 BasicCegarLoop]: trace histogram [35, 1, 1, 1] [2018-07-23 13:36:34,411 INFO L414 AbstractCegarLoop]: === Iteration 36 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:34,415 INFO L82 PathProgramCache]: Analyzing trace with hash 710120096, now seen corresponding path program 35 times [2018-07-23 13:36:34,416 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:34,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:34,794 INFO L134 CoverageAnalysis]: Checked inductivity of 630 backedges. 0 proven. 630 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:34,794 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:34,797 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37] total 37 [2018-07-23 13:36:34,797 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:34,798 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:34,798 INFO L185 omatonBuilderFactory]: Interpolants [3968#(<= (+ GateController_time 1000) GateController_thousand), 3969#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 3970#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 3971#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 3972#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 3973#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 3974#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 3975#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 3976#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 3977#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 3978#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 3979#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 3980#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 3981#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 3982#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 3983#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 3984#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 3985#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 3986#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 3987#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 3988#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 3989#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 3990#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 3991#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 3992#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 3993#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 3994#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 3995#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 3996#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 3997#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 3998#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 3999#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 4000#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 4001#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 4002#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 4003#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 4004#GateController_alarm, 3966#true, 3967#false] [2018-07-23 13:36:34,799 INFO L134 CoverageAnalysis]: Checked inductivity of 630 backedges. 0 proven. 630 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:34,799 INFO L450 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-07-23 13:36:34,799 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-07-23 13:36:34,800 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=740, Invalid=742, Unknown=0, NotChecked=0, Total=1482 [2018-07-23 13:36:34,801 INFO L87 Difference]: Start difference. First operand 39 states and 39 transitions. Second operand 39 states. [2018-07-23 13:36:34,844 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:34,844 INFO L93 Difference]: Finished difference Result 42 states and 42 transitions. [2018-07-23 13:36:34,844 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-07-23 13:36:34,844 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 38 [2018-07-23 13:36:34,845 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:34,845 INFO L225 Difference]: With dead ends: 42 [2018-07-23 13:36:34,845 INFO L226 Difference]: Without dead ends: 40 [2018-07-23 13:36:34,846 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 69 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=740, Invalid=742, Unknown=0, NotChecked=0, Total=1482 [2018-07-23 13:36:34,846 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states. [2018-07-23 13:36:34,850 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 40. [2018-07-23 13:36:34,850 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40 states. [2018-07-23 13:36:34,850 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 40 transitions. [2018-07-23 13:36:34,851 INFO L78 Accepts]: Start accepts. Automaton has 40 states and 40 transitions. Word has length 38 [2018-07-23 13:36:34,851 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:34,851 INFO L471 AbstractCegarLoop]: Abstraction has 40 states and 40 transitions. [2018-07-23 13:36:34,851 INFO L472 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-07-23 13:36:34,851 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states and 40 transitions. [2018-07-23 13:36:34,851 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-07-23 13:36:34,852 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:34,852 INFO L357 BasicCegarLoop]: trace histogram [36, 1, 1, 1] [2018-07-23 13:36:34,852 INFO L414 AbstractCegarLoop]: === Iteration 37 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:34,852 INFO L82 PathProgramCache]: Analyzing trace with hash 538896096, now seen corresponding path program 36 times [2018-07-23 13:36:34,852 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:34,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:35,132 INFO L134 CoverageAnalysis]: Checked inductivity of 666 backedges. 0 proven. 666 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:35,132 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:35,132 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38] total 38 [2018-07-23 13:36:35,132 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:35,133 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:35,133 INFO L185 omatonBuilderFactory]: Interpolants [4169#true, 4170#false, 4171#(<= (+ GateController_time 1000) GateController_thousand), 4172#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 4173#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 4174#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 4175#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 4176#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 4177#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 4178#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 4179#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 4180#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 4181#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 4182#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 4183#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 4184#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 4185#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 4186#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 4187#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 4188#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 4189#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 4190#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 4191#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 4192#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 4193#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 4194#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 4195#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 4196#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 4197#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 4198#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 4199#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 4200#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 4201#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 4202#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 4203#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 4204#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 4205#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 4206#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 4207#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 4208#GateController_alarm] [2018-07-23 13:36:35,133 INFO L134 CoverageAnalysis]: Checked inductivity of 666 backedges. 0 proven. 666 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:35,134 INFO L450 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-07-23 13:36:35,134 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-07-23 13:36:35,135 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=779, Invalid=781, Unknown=0, NotChecked=0, Total=1560 [2018-07-23 13:36:35,135 INFO L87 Difference]: Start difference. First operand 40 states and 40 transitions. Second operand 40 states. [2018-07-23 13:36:35,180 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:35,180 INFO L93 Difference]: Finished difference Result 43 states and 43 transitions. [2018-07-23 13:36:35,180 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2018-07-23 13:36:35,180 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 39 [2018-07-23 13:36:35,181 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:35,181 INFO L225 Difference]: With dead ends: 43 [2018-07-23 13:36:35,181 INFO L226 Difference]: Without dead ends: 41 [2018-07-23 13:36:35,182 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 71 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=779, Invalid=781, Unknown=0, NotChecked=0, Total=1560 [2018-07-23 13:36:35,182 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41 states. [2018-07-23 13:36:35,186 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41 to 41. [2018-07-23 13:36:35,186 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41 states. [2018-07-23 13:36:35,186 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 41 transitions. [2018-07-23 13:36:35,186 INFO L78 Accepts]: Start accepts. Automaton has 41 states and 41 transitions. Word has length 39 [2018-07-23 13:36:35,187 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:35,187 INFO L471 AbstractCegarLoop]: Abstraction has 41 states and 41 transitions. [2018-07-23 13:36:35,187 INFO L472 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-07-23 13:36:35,187 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 41 transitions. [2018-07-23 13:36:35,187 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-07-23 13:36:35,187 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:35,188 INFO L357 BasicCegarLoop]: trace histogram [37, 1, 1, 1] [2018-07-23 13:36:35,188 INFO L414 AbstractCegarLoop]: === Iteration 38 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:35,188 INFO L82 PathProgramCache]: Analyzing trace with hash -474080608, now seen corresponding path program 37 times [2018-07-23 13:36:35,188 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:35,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:35,478 INFO L134 CoverageAnalysis]: Checked inductivity of 703 backedges. 0 proven. 703 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:35,478 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:35,478 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [39] total 39 [2018-07-23 13:36:35,479 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:35,479 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:35,479 INFO L185 omatonBuilderFactory]: Interpolants [4416#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 4417#GateController_alarm, 4377#true, 4378#false, 4379#(<= (+ GateController_time 1000) GateController_thousand), 4380#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 4381#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 4382#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 4383#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 4384#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 4385#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 4386#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 4387#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 4388#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 4389#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 4390#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 4391#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 4392#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 4393#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 4394#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 4395#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 4396#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 4397#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 4398#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 4399#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 4400#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 4401#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 4402#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 4403#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 4404#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 4405#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 4406#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 4407#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 4408#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 4409#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 4410#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 4411#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 4412#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 4413#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 4414#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 4415#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand))] [2018-07-23 13:36:35,480 INFO L134 CoverageAnalysis]: Checked inductivity of 703 backedges. 0 proven. 703 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:35,480 INFO L450 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-07-23 13:36:35,480 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-07-23 13:36:35,481 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=819, Invalid=821, Unknown=0, NotChecked=0, Total=1640 [2018-07-23 13:36:35,481 INFO L87 Difference]: Start difference. First operand 41 states and 41 transitions. Second operand 41 states. [2018-07-23 13:36:35,511 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:35,511 INFO L93 Difference]: Finished difference Result 44 states and 44 transitions. [2018-07-23 13:36:35,511 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-07-23 13:36:35,512 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 40 [2018-07-23 13:36:35,512 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:35,512 INFO L225 Difference]: With dead ends: 44 [2018-07-23 13:36:35,512 INFO L226 Difference]: Without dead ends: 42 [2018-07-23 13:36:35,513 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 73 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=819, Invalid=821, Unknown=0, NotChecked=0, Total=1640 [2018-07-23 13:36:35,514 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42 states. [2018-07-23 13:36:35,518 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42 to 42. [2018-07-23 13:36:35,518 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42 states. [2018-07-23 13:36:35,521 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 42 transitions. [2018-07-23 13:36:35,522 INFO L78 Accepts]: Start accepts. Automaton has 42 states and 42 transitions. Word has length 40 [2018-07-23 13:36:35,522 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:35,522 INFO L471 AbstractCegarLoop]: Abstraction has 42 states and 42 transitions. [2018-07-23 13:36:35,522 INFO L472 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-07-23 13:36:35,522 INFO L276 IsEmpty]: Start isEmpty. Operand 42 states and 42 transitions. [2018-07-23 13:36:35,522 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-07-23 13:36:35,523 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:35,523 INFO L357 BasicCegarLoop]: trace histogram [38, 1, 1, 1] [2018-07-23 13:36:35,523 INFO L414 AbstractCegarLoop]: === Iteration 39 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:35,523 INFO L82 PathProgramCache]: Analyzing trace with hash -1811587360, now seen corresponding path program 38 times [2018-07-23 13:36:35,523 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:35,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:35,814 INFO L134 CoverageAnalysis]: Checked inductivity of 741 backedges. 0 proven. 741 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:35,814 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:35,814 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40] total 40 [2018-07-23 13:36:35,814 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:35,815 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:35,815 INFO L185 omatonBuilderFactory]: Interpolants [4608#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 4609#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 4610#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 4611#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 4612#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 4613#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 4614#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 4615#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 4616#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 4617#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 4618#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 4619#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 4620#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 4621#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 4622#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 4623#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 4624#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 4625#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 4626#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 4627#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 4628#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 4629#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 4630#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 4631#GateController_alarm, 4590#true, 4591#false, 4592#(<= (+ GateController_time 1000) GateController_thousand), 4593#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 4594#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 4595#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 4596#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 4597#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 4598#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 4599#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 4600#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 4601#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 4602#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 4603#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 4604#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 4605#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 4606#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 4607#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand))] [2018-07-23 13:36:35,815 INFO L134 CoverageAnalysis]: Checked inductivity of 741 backedges. 0 proven. 741 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:35,816 INFO L450 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-07-23 13:36:35,816 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-07-23 13:36:35,817 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=860, Invalid=862, Unknown=0, NotChecked=0, Total=1722 [2018-07-23 13:36:35,817 INFO L87 Difference]: Start difference. First operand 42 states and 42 transitions. Second operand 42 states. [2018-07-23 13:36:35,850 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:35,850 INFO L93 Difference]: Finished difference Result 45 states and 45 transitions. [2018-07-23 13:36:35,850 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2018-07-23 13:36:35,850 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 41 [2018-07-23 13:36:35,851 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:35,851 INFO L225 Difference]: With dead ends: 45 [2018-07-23 13:36:35,851 INFO L226 Difference]: Without dead ends: 43 [2018-07-23 13:36:35,852 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 40 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 75 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=860, Invalid=862, Unknown=0, NotChecked=0, Total=1722 [2018-07-23 13:36:35,852 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states. [2018-07-23 13:36:35,857 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 43. [2018-07-23 13:36:35,857 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 43 states. [2018-07-23 13:36:35,858 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 43 transitions. [2018-07-23 13:36:35,858 INFO L78 Accepts]: Start accepts. Automaton has 43 states and 43 transitions. Word has length 41 [2018-07-23 13:36:35,858 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:35,858 INFO L471 AbstractCegarLoop]: Abstraction has 43 states and 43 transitions. [2018-07-23 13:36:35,858 INFO L472 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-07-23 13:36:35,858 INFO L276 IsEmpty]: Start isEmpty. Operand 43 states and 43 transitions. [2018-07-23 13:36:35,859 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-07-23 13:36:35,859 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:35,859 INFO L357 BasicCegarLoop]: trace histogram [39, 1, 1, 1] [2018-07-23 13:36:35,859 INFO L414 AbstractCegarLoop]: === Iteration 40 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:35,859 INFO L82 PathProgramCache]: Analyzing trace with hash -324623712, now seen corresponding path program 39 times [2018-07-23 13:36:35,860 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:35,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:36,181 INFO L134 CoverageAnalysis]: Checked inductivity of 780 backedges. 0 proven. 780 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:36,181 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:36,181 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [41] total 41 [2018-07-23 13:36:36,182 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:36,182 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:36,182 INFO L185 omatonBuilderFactory]: Interpolants [4808#true, 4809#false, 4810#(<= (+ GateController_time 1000) GateController_thousand), 4811#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 4812#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 4813#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 4814#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 4815#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 4816#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 4817#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 4818#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 4819#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 4820#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 4821#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 4822#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 4823#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 4824#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 4825#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 4826#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 4827#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 4828#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 4829#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 4830#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 4831#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 4832#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 4833#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 4834#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 4835#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 4836#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 4837#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 4838#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 4839#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 4840#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 4841#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 4842#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 4843#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 4844#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 4845#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 4846#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 4847#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 4848#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 4849#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 4850#GateController_alarm] [2018-07-23 13:36:36,183 INFO L134 CoverageAnalysis]: Checked inductivity of 780 backedges. 0 proven. 780 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:36,183 INFO L450 AbstractCegarLoop]: Interpolant automaton has 43 states [2018-07-23 13:36:36,183 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2018-07-23 13:36:36,184 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=902, Invalid=904, Unknown=0, NotChecked=0, Total=1806 [2018-07-23 13:36:36,184 INFO L87 Difference]: Start difference. First operand 43 states and 43 transitions. Second operand 43 states. [2018-07-23 13:36:36,223 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:36,224 INFO L93 Difference]: Finished difference Result 46 states and 46 transitions. [2018-07-23 13:36:36,224 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2018-07-23 13:36:36,224 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 42 [2018-07-23 13:36:36,224 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:36,225 INFO L225 Difference]: With dead ends: 46 [2018-07-23 13:36:36,225 INFO L226 Difference]: Without dead ends: 44 [2018-07-23 13:36:36,226 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 41 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 77 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=902, Invalid=904, Unknown=0, NotChecked=0, Total=1806 [2018-07-23 13:36:36,226 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states. [2018-07-23 13:36:36,230 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 44. [2018-07-23 13:36:36,230 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 44 states. [2018-07-23 13:36:36,231 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 44 transitions. [2018-07-23 13:36:36,231 INFO L78 Accepts]: Start accepts. Automaton has 44 states and 44 transitions. Word has length 42 [2018-07-23 13:36:36,231 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:36,231 INFO L471 AbstractCegarLoop]: Abstraction has 44 states and 44 transitions. [2018-07-23 13:36:36,231 INFO L472 AbstractCegarLoop]: Interpolant automaton has 43 states. [2018-07-23 13:36:36,231 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 44 transitions. [2018-07-23 13:36:36,232 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-07-23 13:36:36,232 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:36,232 INFO L357 BasicCegarLoop]: trace histogram [40, 1, 1, 1] [2018-07-23 13:36:36,232 INFO L414 AbstractCegarLoop]: === Iteration 41 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:36,232 INFO L82 PathProgramCache]: Analyzing trace with hash -1473390880, now seen corresponding path program 40 times [2018-07-23 13:36:36,232 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:36,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:36,530 INFO L134 CoverageAnalysis]: Checked inductivity of 820 backedges. 0 proven. 820 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:36,531 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:36,531 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42] total 42 [2018-07-23 13:36:36,531 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:36,531 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:36,532 INFO L185 omatonBuilderFactory]: Interpolants [5056#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 5057#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 5058#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 5059#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 5060#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 5061#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 5062#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 5063#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 5064#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 5065#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 5066#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 5067#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 5068#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 5069#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 5070#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 5071#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 5072#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 5073#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 5074#GateController_alarm, 5031#true, 5032#false, 5033#(<= (+ GateController_time 1000) GateController_thousand), 5034#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 5035#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 5036#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 5037#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 5038#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 5039#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 5040#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 5041#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 5042#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 5043#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 5044#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 5045#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 5046#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 5047#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 5048#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 5049#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 5050#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 5051#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 5052#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 5053#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 5054#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 5055#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand))] [2018-07-23 13:36:36,532 INFO L134 CoverageAnalysis]: Checked inductivity of 820 backedges. 0 proven. 820 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:36,532 INFO L450 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-07-23 13:36:36,533 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-07-23 13:36:36,534 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=945, Invalid=947, Unknown=0, NotChecked=0, Total=1892 [2018-07-23 13:36:36,534 INFO L87 Difference]: Start difference. First operand 44 states and 44 transitions. Second operand 44 states. [2018-07-23 13:36:36,566 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:36,566 INFO L93 Difference]: Finished difference Result 47 states and 47 transitions. [2018-07-23 13:36:36,566 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2018-07-23 13:36:36,566 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 43 [2018-07-23 13:36:36,567 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:36,567 INFO L225 Difference]: With dead ends: 47 [2018-07-23 13:36:36,567 INFO L226 Difference]: Without dead ends: 45 [2018-07-23 13:36:36,568 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 42 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 79 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=945, Invalid=947, Unknown=0, NotChecked=0, Total=1892 [2018-07-23 13:36:36,569 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45 states. [2018-07-23 13:36:36,573 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45 to 45. [2018-07-23 13:36:36,573 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45 states. [2018-07-23 13:36:36,573 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 45 transitions. [2018-07-23 13:36:36,573 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 45 transitions. Word has length 43 [2018-07-23 13:36:36,574 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:36,574 INFO L471 AbstractCegarLoop]: Abstraction has 45 states and 45 transitions. [2018-07-23 13:36:36,574 INFO L472 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-07-23 13:36:36,574 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 45 transitions. [2018-07-23 13:36:36,574 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-07-23 13:36:36,574 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:36,575 INFO L357 BasicCegarLoop]: trace histogram [41, 1, 1, 1] [2018-07-23 13:36:36,575 INFO L414 AbstractCegarLoop]: === Iteration 42 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:36,575 INFO L82 PathProgramCache]: Analyzing trace with hash 1569532576, now seen corresponding path program 41 times [2018-07-23 13:36:36,575 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:36,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:36,885 INFO L134 CoverageAnalysis]: Checked inductivity of 861 backedges. 0 proven. 861 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:36,886 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:36,886 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [43] total 43 [2018-07-23 13:36:36,886 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:36,886 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:36,887 INFO L185 omatonBuilderFactory]: Interpolants [5259#true, 5260#false, 5261#(<= (+ GateController_time 1000) GateController_thousand), 5262#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 5263#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 5264#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 5265#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 5266#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 5267#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 5268#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 5269#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 5270#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 5271#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 5272#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 5273#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 5274#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 5275#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 5276#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 5277#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 5278#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 5279#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 5280#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 5281#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 5282#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 5283#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 5284#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 5285#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 5286#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 5287#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 5288#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 5289#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 5290#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 5291#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 5292#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 5293#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 5294#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 5295#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 5296#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 5297#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 5298#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 5299#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 5300#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 5301#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 5302#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 5303#GateController_alarm] [2018-07-23 13:36:36,887 INFO L134 CoverageAnalysis]: Checked inductivity of 861 backedges. 0 proven. 861 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:36,888 INFO L450 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-07-23 13:36:36,888 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-07-23 13:36:36,889 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=989, Invalid=991, Unknown=0, NotChecked=0, Total=1980 [2018-07-23 13:36:36,889 INFO L87 Difference]: Start difference. First operand 45 states and 45 transitions. Second operand 45 states. [2018-07-23 13:36:36,931 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:36,932 INFO L93 Difference]: Finished difference Result 48 states and 48 transitions. [2018-07-23 13:36:36,932 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-07-23 13:36:36,932 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 44 [2018-07-23 13:36:36,932 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:36,933 INFO L225 Difference]: With dead ends: 48 [2018-07-23 13:36:36,933 INFO L226 Difference]: Without dead ends: 46 [2018-07-23 13:36:36,934 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 81 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=989, Invalid=991, Unknown=0, NotChecked=0, Total=1980 [2018-07-23 13:36:36,934 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46 states. [2018-07-23 13:36:36,938 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46 to 46. [2018-07-23 13:36:36,939 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46 states. [2018-07-23 13:36:36,939 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 46 transitions. [2018-07-23 13:36:36,939 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 46 transitions. Word has length 44 [2018-07-23 13:36:36,940 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:36,940 INFO L471 AbstractCegarLoop]: Abstraction has 46 states and 46 transitions. [2018-07-23 13:36:36,940 INFO L472 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-07-23 13:36:36,940 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 46 transitions. [2018-07-23 13:36:36,940 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-07-23 13:36:36,940 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:36,941 INFO L357 BasicCegarLoop]: trace histogram [42, 1, 1, 1] [2018-07-23 13:36:36,941 INFO L414 AbstractCegarLoop]: === Iteration 43 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:36,941 INFO L82 PathProgramCache]: Analyzing trace with hash 1410879200, now seen corresponding path program 42 times [2018-07-23 13:36:36,941 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:36,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:37,265 INFO L134 CoverageAnalysis]: Checked inductivity of 903 backedges. 0 proven. 903 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:37,266 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:37,266 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44] total 44 [2018-07-23 13:36:37,266 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:37,267 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:37,268 INFO L185 omatonBuilderFactory]: Interpolants [5504#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 5505#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 5506#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 5507#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 5508#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 5509#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 5510#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 5511#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 5512#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 5513#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 5514#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 5515#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 5516#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 5517#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 5518#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 5519#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 5520#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 5521#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 5522#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 5523#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 5524#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 5525#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 5526#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 5527#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 5528#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 5529#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 5530#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 5531#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 5532#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 5533#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 5534#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 5535#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 5536#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 5537#GateController_alarm, 5492#true, 5493#false, 5494#(<= (+ GateController_time 1000) GateController_thousand), 5495#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 5496#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 5497#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 5498#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 5499#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 5500#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 5501#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 5502#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 5503#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand))] [2018-07-23 13:36:37,268 INFO L134 CoverageAnalysis]: Checked inductivity of 903 backedges. 0 proven. 903 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:37,268 INFO L450 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-07-23 13:36:37,269 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-07-23 13:36:37,270 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1034, Invalid=1036, Unknown=0, NotChecked=0, Total=2070 [2018-07-23 13:36:37,270 INFO L87 Difference]: Start difference. First operand 46 states and 46 transitions. Second operand 46 states. [2018-07-23 13:36:37,315 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:37,315 INFO L93 Difference]: Finished difference Result 49 states and 49 transitions. [2018-07-23 13:36:37,315 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2018-07-23 13:36:37,315 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 45 [2018-07-23 13:36:37,316 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:37,316 INFO L225 Difference]: With dead ends: 49 [2018-07-23 13:36:37,316 INFO L226 Difference]: Without dead ends: 47 [2018-07-23 13:36:37,318 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 83 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=1034, Invalid=1036, Unknown=0, NotChecked=0, Total=2070 [2018-07-23 13:36:37,318 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states. [2018-07-23 13:36:37,323 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 47. [2018-07-23 13:36:37,324 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 47 states. [2018-07-23 13:36:37,324 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 47 transitions. [2018-07-23 13:36:37,324 INFO L78 Accepts]: Start accepts. Automaton has 47 states and 47 transitions. Word has length 45 [2018-07-23 13:36:37,324 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:37,325 INFO L471 AbstractCegarLoop]: Abstraction has 47 states and 47 transitions. [2018-07-23 13:36:37,325 INFO L472 AbstractCegarLoop]: Interpolant automaton has 46 states. [2018-07-23 13:36:37,325 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 47 transitions. [2018-07-23 13:36:37,325 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-07-23 13:36:37,326 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:37,326 INFO L357 BasicCegarLoop]: trace histogram [43, 1, 1, 1] [2018-07-23 13:36:37,326 INFO L414 AbstractCegarLoop]: === Iteration 44 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:37,326 INFO L82 PathProgramCache]: Analyzing trace with hash 787591840, now seen corresponding path program 43 times [2018-07-23 13:36:37,326 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:37,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:37,722 INFO L134 CoverageAnalysis]: Checked inductivity of 946 backedges. 0 proven. 946 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:37,722 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:37,723 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [45] total 45 [2018-07-23 13:36:37,723 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:37,723 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:37,724 INFO L185 omatonBuilderFactory]: Interpolants [5760#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 5761#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 5762#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 5763#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 5764#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 5765#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 5766#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 5767#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 5768#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 5769#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 5770#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 5771#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 5772#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 5773#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 5774#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 5775#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 5776#GateController_alarm, 5730#true, 5731#false, 5732#(<= (+ GateController_time 1000) GateController_thousand), 5733#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 5734#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 5735#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 5736#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 5737#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 5738#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 5739#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 5740#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 5741#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 5742#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 5743#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 5744#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 5745#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 5746#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 5747#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 5748#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 5749#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 5750#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 5751#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 5752#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 5753#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 5754#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 5755#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 5756#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 5757#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 5758#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 5759#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand))] [2018-07-23 13:36:37,724 INFO L134 CoverageAnalysis]: Checked inductivity of 946 backedges. 0 proven. 946 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:37,725 INFO L450 AbstractCegarLoop]: Interpolant automaton has 47 states [2018-07-23 13:36:37,725 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2018-07-23 13:36:37,726 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1080, Invalid=1082, Unknown=0, NotChecked=0, Total=2162 [2018-07-23 13:36:37,726 INFO L87 Difference]: Start difference. First operand 47 states and 47 transitions. Second operand 47 states. [2018-07-23 13:36:37,764 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:37,764 INFO L93 Difference]: Finished difference Result 50 states and 50 transitions. [2018-07-23 13:36:37,765 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-07-23 13:36:37,765 INFO L78 Accepts]: Start accepts. Automaton has 47 states. Word has length 46 [2018-07-23 13:36:37,765 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:37,765 INFO L225 Difference]: With dead ends: 50 [2018-07-23 13:36:37,766 INFO L226 Difference]: Without dead ends: 48 [2018-07-23 13:36:37,767 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 85 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=1080, Invalid=1082, Unknown=0, NotChecked=0, Total=2162 [2018-07-23 13:36:37,767 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48 states. [2018-07-23 13:36:37,772 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48 to 48. [2018-07-23 13:36:37,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48 states. [2018-07-23 13:36:37,772 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 48 transitions. [2018-07-23 13:36:37,772 INFO L78 Accepts]: Start accepts. Automaton has 48 states and 48 transitions. Word has length 46 [2018-07-23 13:36:37,773 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:37,773 INFO L471 AbstractCegarLoop]: Abstraction has 48 states and 48 transitions. [2018-07-23 13:36:37,773 INFO L472 AbstractCegarLoop]: Interpolant automaton has 47 states. [2018-07-23 13:36:37,773 INFO L276 IsEmpty]: Start isEmpty. Operand 48 states and 48 transitions. [2018-07-23 13:36:37,774 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-07-23 13:36:37,774 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:37,774 INFO L357 BasicCegarLoop]: trace histogram [44, 1, 1, 1] [2018-07-23 13:36:37,774 INFO L414 AbstractCegarLoop]: === Iteration 45 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:37,774 INFO L82 PathProgramCache]: Analyzing trace with hash -1354447136, now seen corresponding path program 44 times [2018-07-23 13:36:37,775 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:37,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:38,185 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:38,185 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:38,185 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46] total 46 [2018-07-23 13:36:38,185 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:38,186 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:38,186 INFO L185 omatonBuilderFactory]: Interpolants [6016#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 6017#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 6018#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 6019#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 6020#GateController_alarm, 5973#true, 5974#false, 5975#(<= (+ GateController_time 1000) GateController_thousand), 5976#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 5977#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 5978#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 5979#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 5980#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 5981#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 5982#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 5983#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 5984#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 5985#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 5986#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 5987#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 5988#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 5989#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 5990#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 5991#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 5992#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 5993#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 5994#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 5995#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 5996#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 5997#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 5998#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 5999#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 6000#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 6001#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 6002#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 6003#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 6004#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 6005#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 6006#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 6007#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 6008#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 6009#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 6010#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 6011#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 6012#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 6013#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 6014#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 6015#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand))] [2018-07-23 13:36:38,186 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:38,187 INFO L450 AbstractCegarLoop]: Interpolant automaton has 48 states [2018-07-23 13:36:38,187 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2018-07-23 13:36:38,188 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1127, Invalid=1129, Unknown=0, NotChecked=0, Total=2256 [2018-07-23 13:36:38,188 INFO L87 Difference]: Start difference. First operand 48 states and 48 transitions. Second operand 48 states. [2018-07-23 13:36:38,223 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:38,223 INFO L93 Difference]: Finished difference Result 51 states and 51 transitions. [2018-07-23 13:36:38,223 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2018-07-23 13:36:38,223 INFO L78 Accepts]: Start accepts. Automaton has 48 states. Word has length 47 [2018-07-23 13:36:38,224 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:38,224 INFO L225 Difference]: With dead ends: 51 [2018-07-23 13:36:38,224 INFO L226 Difference]: Without dead ends: 49 [2018-07-23 13:36:38,225 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 46 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 87 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=1127, Invalid=1129, Unknown=0, NotChecked=0, Total=2256 [2018-07-23 13:36:38,225 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2018-07-23 13:36:38,230 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 49. [2018-07-23 13:36:38,230 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 49 states. [2018-07-23 13:36:38,230 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 49 transitions. [2018-07-23 13:36:38,230 INFO L78 Accepts]: Start accepts. Automaton has 49 states and 49 transitions. Word has length 47 [2018-07-23 13:36:38,231 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:38,231 INFO L471 AbstractCegarLoop]: Abstraction has 49 states and 49 transitions. [2018-07-23 13:36:38,231 INFO L472 AbstractCegarLoop]: Interpolant automaton has 48 states. [2018-07-23 13:36:38,231 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 49 transitions. [2018-07-23 13:36:38,231 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-07-23 13:36:38,232 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:38,232 INFO L357 BasicCegarLoop]: trace histogram [45, 1, 1, 1] [2018-07-23 13:36:38,232 INFO L414 AbstractCegarLoop]: === Iteration 46 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:38,232 INFO L82 PathProgramCache]: Analyzing trace with hash 961821344, now seen corresponding path program 45 times [2018-07-23 13:36:38,232 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:38,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:38,541 INFO L134 CoverageAnalysis]: Checked inductivity of 1035 backedges. 0 proven. 1035 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:38,542 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:38,542 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [47] total 47 [2018-07-23 13:36:38,542 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:38,542 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:38,543 INFO L185 omatonBuilderFactory]: Interpolants [6221#true, 6222#false, 6223#(<= (+ GateController_time 1000) GateController_thousand), 6224#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 6225#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 6226#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 6227#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 6228#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 6229#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 6230#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 6231#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 6232#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 6233#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 6234#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 6235#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 6236#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 6237#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 6238#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 6239#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 6240#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 6241#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 6242#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 6243#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 6244#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 6245#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 6246#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 6247#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 6248#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 6249#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 6250#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 6251#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 6252#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 6253#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 6254#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 6255#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 6256#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 6257#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 6258#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 6259#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 6260#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 6261#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 6262#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 6263#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 6264#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 6265#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 6266#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 6267#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 6268#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 6269#GateController_alarm] [2018-07-23 13:36:38,543 INFO L134 CoverageAnalysis]: Checked inductivity of 1035 backedges. 0 proven. 1035 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:38,544 INFO L450 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-07-23 13:36:38,544 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-07-23 13:36:38,545 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1175, Invalid=1177, Unknown=0, NotChecked=0, Total=2352 [2018-07-23 13:36:38,545 INFO L87 Difference]: Start difference. First operand 49 states and 49 transitions. Second operand 49 states. [2018-07-23 13:36:38,589 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:38,590 INFO L93 Difference]: Finished difference Result 52 states and 52 transitions. [2018-07-23 13:36:38,590 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2018-07-23 13:36:38,590 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 48 [2018-07-23 13:36:38,590 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:38,591 INFO L225 Difference]: With dead ends: 52 [2018-07-23 13:36:38,591 INFO L226 Difference]: Without dead ends: 50 [2018-07-23 13:36:38,592 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 47 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 47 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 89 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=1175, Invalid=1177, Unknown=0, NotChecked=0, Total=2352 [2018-07-23 13:36:38,592 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2018-07-23 13:36:38,596 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 50. [2018-07-23 13:36:38,596 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2018-07-23 13:36:38,597 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 50 transitions. [2018-07-23 13:36:38,597 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 50 transitions. Word has length 48 [2018-07-23 13:36:38,597 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:38,597 INFO L471 AbstractCegarLoop]: Abstraction has 50 states and 50 transitions. [2018-07-23 13:36:38,597 INFO L472 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-07-23 13:36:38,598 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 50 transitions. [2018-07-23 13:36:38,598 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-07-23 13:36:38,598 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:38,598 INFO L357 BasicCegarLoop]: trace histogram [46, 1, 1, 1] [2018-07-23 13:36:38,598 INFO L414 AbstractCegarLoop]: === Iteration 47 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:38,599 INFO L82 PathProgramCache]: Analyzing trace with hash -248299808, now seen corresponding path program 46 times [2018-07-23 13:36:38,599 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:38,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:38,924 INFO L134 CoverageAnalysis]: Checked inductivity of 1081 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:38,924 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:38,924 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48] total 48 [2018-07-23 13:36:38,924 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:38,925 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:38,925 INFO L185 omatonBuilderFactory]: Interpolants [6474#true, 6475#false, 6476#(<= (+ GateController_time 1000) GateController_thousand), 6477#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 6478#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 6479#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 6480#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 6481#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 6482#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 6483#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 6484#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 6485#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 6486#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 6487#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 6488#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 6489#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 6490#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 6491#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 6492#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 6493#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 6494#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 6495#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 6496#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 6497#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 6498#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 6499#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 6500#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 6501#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 6502#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 6503#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 6504#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 6505#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 6506#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 6507#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 6508#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 6509#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 6510#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 6511#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 6512#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 6513#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 6514#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 6515#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 6516#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 6517#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 6518#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 6519#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 6520#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 6521#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 6522#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 6523#GateController_alarm] [2018-07-23 13:36:38,926 INFO L134 CoverageAnalysis]: Checked inductivity of 1081 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:38,926 INFO L450 AbstractCegarLoop]: Interpolant automaton has 50 states [2018-07-23 13:36:38,926 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2018-07-23 13:36:38,927 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1224, Invalid=1226, Unknown=0, NotChecked=0, Total=2450 [2018-07-23 13:36:38,927 INFO L87 Difference]: Start difference. First operand 50 states and 50 transitions. Second operand 50 states. [2018-07-23 13:36:38,977 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:38,977 INFO L93 Difference]: Finished difference Result 53 states and 53 transitions. [2018-07-23 13:36:38,977 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2018-07-23 13:36:38,977 INFO L78 Accepts]: Start accepts. Automaton has 50 states. Word has length 49 [2018-07-23 13:36:38,978 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:38,978 INFO L225 Difference]: With dead ends: 53 [2018-07-23 13:36:38,978 INFO L226 Difference]: Without dead ends: 51 [2018-07-23 13:36:38,979 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 91 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=1224, Invalid=1226, Unknown=0, NotChecked=0, Total=2450 [2018-07-23 13:36:38,979 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51 states. [2018-07-23 13:36:38,984 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51 to 51. [2018-07-23 13:36:38,984 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51 states. [2018-07-23 13:36:38,984 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 51 transitions. [2018-07-23 13:36:38,984 INFO L78 Accepts]: Start accepts. Automaton has 51 states and 51 transitions. Word has length 49 [2018-07-23 13:36:38,985 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:38,985 INFO L471 AbstractCegarLoop]: Abstraction has 51 states and 51 transitions. [2018-07-23 13:36:38,985 INFO L472 AbstractCegarLoop]: Interpolant automaton has 50 states. [2018-07-23 13:36:38,985 INFO L276 IsEmpty]: Start isEmpty. Operand 51 states and 51 transitions. [2018-07-23 13:36:38,985 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-07-23 13:36:38,986 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:38,986 INFO L357 BasicCegarLoop]: trace histogram [47, 1, 1, 1] [2018-07-23 13:36:38,986 INFO L414 AbstractCegarLoop]: === Iteration 48 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:38,986 INFO L82 PathProgramCache]: Analyzing trace with hash 892650144, now seen corresponding path program 47 times [2018-07-23 13:36:38,986 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:39,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:39,315 INFO L134 CoverageAnalysis]: Checked inductivity of 1128 backedges. 0 proven. 1128 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:39,315 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:39,316 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [49] total 49 [2018-07-23 13:36:39,316 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:39,316 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:39,316 INFO L185 omatonBuilderFactory]: Interpolants [6732#true, 6733#false, 6734#(<= (+ GateController_time 1000) GateController_thousand), 6735#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 6736#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 6737#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 6738#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 6739#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 6740#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 6741#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 6742#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 6743#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 6744#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 6745#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 6746#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 6747#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 6748#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 6749#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 6750#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 6751#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 6752#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 6753#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 6754#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 6755#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 6756#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 6757#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 6758#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 6759#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 6760#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 6761#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 6762#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 6763#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 6764#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 6765#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 6766#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 6767#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 6768#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 6769#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 6770#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 6771#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 6772#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 6773#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 6774#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 6775#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 6776#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 6777#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 6778#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 6779#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 6780#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 6781#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 6782#GateController_alarm] [2018-07-23 13:36:39,317 INFO L134 CoverageAnalysis]: Checked inductivity of 1128 backedges. 0 proven. 1128 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:39,317 INFO L450 AbstractCegarLoop]: Interpolant automaton has 51 states [2018-07-23 13:36:39,318 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2018-07-23 13:36:39,318 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1274, Invalid=1276, Unknown=0, NotChecked=0, Total=2550 [2018-07-23 13:36:39,319 INFO L87 Difference]: Start difference. First operand 51 states and 51 transitions. Second operand 51 states. [2018-07-23 13:36:39,364 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:39,365 INFO L93 Difference]: Finished difference Result 54 states and 54 transitions. [2018-07-23 13:36:39,365 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-07-23 13:36:39,365 INFO L78 Accepts]: Start accepts. Automaton has 51 states. Word has length 50 [2018-07-23 13:36:39,365 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:39,366 INFO L225 Difference]: With dead ends: 54 [2018-07-23 13:36:39,366 INFO L226 Difference]: Without dead ends: 52 [2018-07-23 13:36:39,367 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 93 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=1274, Invalid=1276, Unknown=0, NotChecked=0, Total=2550 [2018-07-23 13:36:39,367 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states. [2018-07-23 13:36:39,371 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 52. [2018-07-23 13:36:39,372 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 52 states. [2018-07-23 13:36:39,372 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 52 transitions. [2018-07-23 13:36:39,372 INFO L78 Accepts]: Start accepts. Automaton has 52 states and 52 transitions. Word has length 50 [2018-07-23 13:36:39,372 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:39,373 INFO L471 AbstractCegarLoop]: Abstraction has 52 states and 52 transitions. [2018-07-23 13:36:39,373 INFO L472 AbstractCegarLoop]: Interpolant automaton has 51 states. [2018-07-23 13:36:39,373 INFO L276 IsEmpty]: Start isEmpty. Operand 52 states and 52 transitions. [2018-07-23 13:36:39,373 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-07-23 13:36:39,373 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:39,373 INFO L357 BasicCegarLoop]: trace histogram [48, 1, 1, 1] [2018-07-23 13:36:39,374 INFO L414 AbstractCegarLoop]: === Iteration 49 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:39,374 INFO L82 PathProgramCache]: Analyzing trace with hash 1902360288, now seen corresponding path program 48 times [2018-07-23 13:36:39,374 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:39,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:39,690 INFO L134 CoverageAnalysis]: Checked inductivity of 1176 backedges. 0 proven. 1176 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:39,690 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:39,690 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50] total 50 [2018-07-23 13:36:39,691 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:39,691 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:39,691 INFO L185 omatonBuilderFactory]: Interpolants [7040#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 7041#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 7042#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 7043#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 7044#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 7045#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 7046#GateController_alarm, 6995#true, 6996#false, 6997#(<= (+ GateController_time 1000) GateController_thousand), 6998#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 6999#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 7000#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 7001#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 7002#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 7003#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 7004#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 7005#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 7006#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 7007#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 7008#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 7009#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 7010#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 7011#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 7012#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 7013#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 7014#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 7015#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 7016#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 7017#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 7018#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 7019#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 7020#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 7021#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 7022#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 7023#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 7024#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 7025#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 7026#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 7027#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 7028#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 7029#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 7030#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 7031#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 7032#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 7033#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 7034#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 7035#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 7036#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 7037#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 7038#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 7039#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand))] [2018-07-23 13:36:39,692 INFO L134 CoverageAnalysis]: Checked inductivity of 1176 backedges. 0 proven. 1176 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:39,692 INFO L450 AbstractCegarLoop]: Interpolant automaton has 52 states [2018-07-23 13:36:39,693 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2018-07-23 13:36:39,693 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1325, Invalid=1327, Unknown=0, NotChecked=0, Total=2652 [2018-07-23 13:36:39,693 INFO L87 Difference]: Start difference. First operand 52 states and 52 transitions. Second operand 52 states. [2018-07-23 13:36:39,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:39,728 INFO L93 Difference]: Finished difference Result 55 states and 55 transitions. [2018-07-23 13:36:39,728 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2018-07-23 13:36:39,728 INFO L78 Accepts]: Start accepts. Automaton has 52 states. Word has length 51 [2018-07-23 13:36:39,728 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:39,729 INFO L225 Difference]: With dead ends: 55 [2018-07-23 13:36:39,729 INFO L226 Difference]: Without dead ends: 53 [2018-07-23 13:36:39,730 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 95 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=1325, Invalid=1327, Unknown=0, NotChecked=0, Total=2652 [2018-07-23 13:36:39,730 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states. [2018-07-23 13:36:39,734 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 53. [2018-07-23 13:36:39,735 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 53 states. [2018-07-23 13:36:39,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 53 transitions. [2018-07-23 13:36:39,735 INFO L78 Accepts]: Start accepts. Automaton has 53 states and 53 transitions. Word has length 51 [2018-07-23 13:36:39,735 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:39,735 INFO L471 AbstractCegarLoop]: Abstraction has 53 states and 53 transitions. [2018-07-23 13:36:39,736 INFO L472 AbstractCegarLoop]: Interpolant automaton has 52 states. [2018-07-23 13:36:39,736 INFO L276 IsEmpty]: Start isEmpty. Operand 53 states and 53 transitions. [2018-07-23 13:36:39,736 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-07-23 13:36:39,736 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:39,736 INFO L357 BasicCegarLoop]: trace histogram [49, 1, 1, 1] [2018-07-23 13:36:39,736 INFO L414 AbstractCegarLoop]: === Iteration 50 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:39,737 INFO L82 PathProgramCache]: Analyzing trace with hash -1156363616, now seen corresponding path program 49 times [2018-07-23 13:36:39,737 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:39,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:40,072 INFO L134 CoverageAnalysis]: Checked inductivity of 1225 backedges. 0 proven. 1225 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:40,072 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:40,072 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [51] total 51 [2018-07-23 13:36:40,072 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:40,073 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:40,073 INFO L185 omatonBuilderFactory]: Interpolants [7296#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 7297#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 7298#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 7299#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 7300#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 7301#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 7302#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 7303#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 7304#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 7305#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 7306#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 7307#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 7308#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 7309#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 7310#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 7311#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 7312#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 7313#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 7314#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 7315#GateController_alarm, 7263#true, 7264#false, 7265#(<= (+ GateController_time 1000) GateController_thousand), 7266#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 7267#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 7268#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 7269#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 7270#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 7271#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 7272#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 7273#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 7274#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 7275#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 7276#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 7277#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 7278#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 7279#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 7280#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 7281#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 7282#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 7283#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 7284#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 7285#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 7286#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 7287#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 7288#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 7289#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 7290#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 7291#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 7292#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 7293#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 7294#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 7295#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand))] [2018-07-23 13:36:40,074 INFO L134 CoverageAnalysis]: Checked inductivity of 1225 backedges. 0 proven. 1225 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:40,074 INFO L450 AbstractCegarLoop]: Interpolant automaton has 53 states [2018-07-23 13:36:40,075 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2018-07-23 13:36:40,075 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1377, Invalid=1379, Unknown=0, NotChecked=0, Total=2756 [2018-07-23 13:36:40,075 INFO L87 Difference]: Start difference. First operand 53 states and 53 transitions. Second operand 53 states. [2018-07-23 13:36:40,110 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:40,111 INFO L93 Difference]: Finished difference Result 56 states and 56 transitions. [2018-07-23 13:36:40,111 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2018-07-23 13:36:40,111 INFO L78 Accepts]: Start accepts. Automaton has 53 states. Word has length 52 [2018-07-23 13:36:40,111 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:40,112 INFO L225 Difference]: With dead ends: 56 [2018-07-23 13:36:40,112 INFO L226 Difference]: Without dead ends: 54 [2018-07-23 13:36:40,113 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 51 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 97 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=1377, Invalid=1379, Unknown=0, NotChecked=0, Total=2756 [2018-07-23 13:36:40,113 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2018-07-23 13:36:40,117 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 54. [2018-07-23 13:36:40,118 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2018-07-23 13:36:40,118 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 54 transitions. [2018-07-23 13:36:40,118 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 54 transitions. Word has length 52 [2018-07-23 13:36:40,118 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:40,119 INFO L471 AbstractCegarLoop]: Abstraction has 54 states and 54 transitions. [2018-07-23 13:36:40,119 INFO L472 AbstractCegarLoop]: Interpolant automaton has 53 states. [2018-07-23 13:36:40,119 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 54 transitions. [2018-07-23 13:36:40,119 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-07-23 13:36:40,119 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:40,119 INFO L357 BasicCegarLoop]: trace histogram [50, 1, 1, 1] [2018-07-23 13:36:40,120 INFO L414 AbstractCegarLoop]: === Iteration 51 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:40,120 INFO L82 PathProgramCache]: Analyzing trace with hash -1487524128, now seen corresponding path program 50 times [2018-07-23 13:36:40,120 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:40,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:40,448 INFO L134 CoverageAnalysis]: Checked inductivity of 1275 backedges. 0 proven. 1275 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:40,448 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:40,449 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [52] total 52 [2018-07-23 13:36:40,449 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:40,449 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:40,450 INFO L185 omatonBuilderFactory]: Interpolants [7552#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 7553#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 7554#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 7555#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 7556#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 7557#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 7558#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 7559#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 7560#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 7561#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 7562#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 7563#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 7564#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 7565#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 7566#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 7567#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 7568#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 7569#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 7570#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 7571#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 7572#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 7573#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 7574#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 7575#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 7576#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 7577#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 7578#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 7579#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 7580#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 7581#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 7582#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 7583#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 7584#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 7585#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 7586#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 7587#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 7588#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 7589#GateController_alarm, 7536#true, 7537#false, 7538#(<= (+ GateController_time 1000) GateController_thousand), 7539#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 7540#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 7541#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 7542#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 7543#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 7544#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 7545#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 7546#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 7547#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 7548#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 7549#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 7550#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 7551#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand))] [2018-07-23 13:36:40,451 INFO L134 CoverageAnalysis]: Checked inductivity of 1275 backedges. 0 proven. 1275 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:40,451 INFO L450 AbstractCegarLoop]: Interpolant automaton has 54 states [2018-07-23 13:36:40,451 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2018-07-23 13:36:40,452 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1430, Invalid=1432, Unknown=0, NotChecked=0, Total=2862 [2018-07-23 13:36:40,453 INFO L87 Difference]: Start difference. First operand 54 states and 54 transitions. Second operand 54 states. [2018-07-23 13:36:40,495 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:40,496 INFO L93 Difference]: Finished difference Result 57 states and 57 transitions. [2018-07-23 13:36:40,496 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2018-07-23 13:36:40,496 INFO L78 Accepts]: Start accepts. Automaton has 54 states. Word has length 53 [2018-07-23 13:36:40,496 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:40,497 INFO L225 Difference]: With dead ends: 57 [2018-07-23 13:36:40,497 INFO L226 Difference]: Without dead ends: 55 [2018-07-23 13:36:40,498 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 99 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=1430, Invalid=1432, Unknown=0, NotChecked=0, Total=2862 [2018-07-23 13:36:40,498 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55 states. [2018-07-23 13:36:40,503 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55 to 55. [2018-07-23 13:36:40,503 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 55 states. [2018-07-23 13:36:40,504 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 55 transitions. [2018-07-23 13:36:40,504 INFO L78 Accepts]: Start accepts. Automaton has 55 states and 55 transitions. Word has length 53 [2018-07-23 13:36:40,504 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:40,505 INFO L471 AbstractCegarLoop]: Abstraction has 55 states and 55 transitions. [2018-07-23 13:36:40,505 INFO L472 AbstractCegarLoop]: Interpolant automaton has 54 states. [2018-07-23 13:36:40,505 INFO L276 IsEmpty]: Start isEmpty. Operand 55 states and 55 transitions. [2018-07-23 13:36:40,505 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-07-23 13:36:40,505 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:40,506 INFO L357 BasicCegarLoop]: trace histogram [51, 1, 1, 1] [2018-07-23 13:36:40,506 INFO L414 AbstractCegarLoop]: === Iteration 52 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:40,506 INFO L82 PathProgramCache]: Analyzing trace with hash 1131401888, now seen corresponding path program 51 times [2018-07-23 13:36:40,506 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:40,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:40,906 INFO L134 CoverageAnalysis]: Checked inductivity of 1326 backedges. 0 proven. 1326 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:40,906 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:40,906 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [53] total 53 [2018-07-23 13:36:40,907 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:40,907 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:40,908 INFO L185 omatonBuilderFactory]: Interpolants [7814#true, 7815#false, 7816#(<= (+ GateController_time 1000) GateController_thousand), 7817#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 7818#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 7819#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 7820#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 7821#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 7822#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 7823#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 7824#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 7825#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 7826#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 7827#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 7828#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 7829#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 7830#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 7831#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 7832#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 7833#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 7834#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 7835#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 7836#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 7837#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 7838#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 7839#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 7840#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 7841#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 7842#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 7843#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 7844#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 7845#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 7846#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 7847#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 7848#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 7849#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 7850#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 7851#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 7852#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 7853#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 7854#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 7855#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 7856#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 7857#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 7858#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 7859#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 7860#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 7861#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 7862#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 7863#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 7864#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 7865#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 7866#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 7867#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 7868#GateController_alarm] [2018-07-23 13:36:40,908 INFO L134 CoverageAnalysis]: Checked inductivity of 1326 backedges. 0 proven. 1326 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:40,909 INFO L450 AbstractCegarLoop]: Interpolant automaton has 55 states [2018-07-23 13:36:40,909 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2018-07-23 13:36:40,910 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1484, Invalid=1486, Unknown=0, NotChecked=0, Total=2970 [2018-07-23 13:36:40,911 INFO L87 Difference]: Start difference. First operand 55 states and 55 transitions. Second operand 55 states. [2018-07-23 13:36:40,972 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:40,972 INFO L93 Difference]: Finished difference Result 58 states and 58 transitions. [2018-07-23 13:36:40,972 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 55 states. [2018-07-23 13:36:40,973 INFO L78 Accepts]: Start accepts. Automaton has 55 states. Word has length 54 [2018-07-23 13:36:40,973 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:40,973 INFO L225 Difference]: With dead ends: 58 [2018-07-23 13:36:40,974 INFO L226 Difference]: Without dead ends: 56 [2018-07-23 13:36:40,975 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 101 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=1484, Invalid=1486, Unknown=0, NotChecked=0, Total=2970 [2018-07-23 13:36:40,975 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56 states. [2018-07-23 13:36:40,981 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56 to 56. [2018-07-23 13:36:40,981 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 56 states. [2018-07-23 13:36:40,981 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56 states to 56 states and 56 transitions. [2018-07-23 13:36:40,982 INFO L78 Accepts]: Start accepts. Automaton has 56 states and 56 transitions. Word has length 54 [2018-07-23 13:36:40,982 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:40,982 INFO L471 AbstractCegarLoop]: Abstraction has 56 states and 56 transitions. [2018-07-23 13:36:40,982 INFO L472 AbstractCegarLoop]: Interpolant automaton has 55 states. [2018-07-23 13:36:40,982 INFO L276 IsEmpty]: Start isEmpty. Operand 56 states and 56 transitions. [2018-07-23 13:36:40,983 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2018-07-23 13:36:40,983 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:40,983 INFO L357 BasicCegarLoop]: trace histogram [52, 1, 1, 1] [2018-07-23 13:36:40,984 INFO L414 AbstractCegarLoop]: === Iteration 53 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:40,984 INFO L82 PathProgramCache]: Analyzing trace with hash 713729760, now seen corresponding path program 52 times [2018-07-23 13:36:40,984 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:41,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:41,464 INFO L134 CoverageAnalysis]: Checked inductivity of 1378 backedges. 0 proven. 1378 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:41,464 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:41,464 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54] total 54 [2018-07-23 13:36:41,465 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:41,465 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:41,465 INFO L185 omatonBuilderFactory]: Interpolants [8097#true, 8098#false, 8099#(<= (+ GateController_time 1000) GateController_thousand), 8100#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 8101#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 8102#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 8103#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 8104#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 8105#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 8106#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 8107#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 8108#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 8109#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 8110#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 8111#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 8112#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 8113#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 8114#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 8115#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 8116#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 8117#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 8118#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 8119#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 8120#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 8121#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 8122#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 8123#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 8124#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 8125#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 8126#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 8127#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 8128#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 8129#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 8130#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 8131#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 8132#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 8133#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 8134#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 8135#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 8136#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 8137#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 8138#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 8139#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 8140#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 8141#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 8142#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 8143#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 8144#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 8145#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 8146#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 8147#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 8148#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 8149#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 8150#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 8151#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 8152#GateController_alarm] [2018-07-23 13:36:41,466 INFO L134 CoverageAnalysis]: Checked inductivity of 1378 backedges. 0 proven. 1378 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:41,466 INFO L450 AbstractCegarLoop]: Interpolant automaton has 56 states [2018-07-23 13:36:41,467 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 56 interpolants. [2018-07-23 13:36:41,467 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1539, Invalid=1541, Unknown=0, NotChecked=0, Total=3080 [2018-07-23 13:36:41,467 INFO L87 Difference]: Start difference. First operand 56 states and 56 transitions. Second operand 56 states. [2018-07-23 13:36:41,512 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:41,512 INFO L93 Difference]: Finished difference Result 59 states and 59 transitions. [2018-07-23 13:36:41,513 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2018-07-23 13:36:41,513 INFO L78 Accepts]: Start accepts. Automaton has 56 states. Word has length 55 [2018-07-23 13:36:41,513 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:41,513 INFO L225 Difference]: With dead ends: 59 [2018-07-23 13:36:41,513 INFO L226 Difference]: Without dead ends: 57 [2018-07-23 13:36:41,514 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 54 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 103 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=1539, Invalid=1541, Unknown=0, NotChecked=0, Total=3080 [2018-07-23 13:36:41,515 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57 states. [2018-07-23 13:36:41,519 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57 to 57. [2018-07-23 13:36:41,519 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 57 states. [2018-07-23 13:36:41,520 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 57 transitions. [2018-07-23 13:36:41,520 INFO L78 Accepts]: Start accepts. Automaton has 57 states and 57 transitions. Word has length 55 [2018-07-23 13:36:41,520 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:41,520 INFO L471 AbstractCegarLoop]: Abstraction has 57 states and 57 transitions. [2018-07-23 13:36:41,520 INFO L472 AbstractCegarLoop]: Interpolant automaton has 56 states. [2018-07-23 13:36:41,521 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 57 transitions. [2018-07-23 13:36:41,521 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-07-23 13:36:41,521 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:41,521 INFO L357 BasicCegarLoop]: trace histogram [53, 1, 1, 1] [2018-07-23 13:36:41,522 INFO L414 AbstractCegarLoop]: === Iteration 54 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:41,522 INFO L82 PathProgramCache]: Analyzing trace with hash 650795680, now seen corresponding path program 53 times [2018-07-23 13:36:41,522 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:41,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:41,861 INFO L134 CoverageAnalysis]: Checked inductivity of 1431 backedges. 0 proven. 1431 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:41,861 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:41,862 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [55] total 55 [2018-07-23 13:36:41,862 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:41,862 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:41,863 INFO L185 omatonBuilderFactory]: Interpolants [8385#true, 8386#false, 8387#(<= (+ GateController_time 1000) GateController_thousand), 8388#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 8389#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 8390#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 8391#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 8392#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 8393#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 8394#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 8395#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 8396#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 8397#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 8398#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 8399#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 8400#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 8401#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 8402#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 8403#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 8404#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 8405#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 8406#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 8407#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 8408#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 8409#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 8410#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 8411#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 8412#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 8413#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 8414#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 8415#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 8416#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 8417#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 8418#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 8419#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 8420#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 8421#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 8422#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 8423#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 8424#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 8425#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 8426#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 8427#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 8428#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 8429#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 8430#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 8431#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 8432#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 8433#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 8434#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 8435#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 8436#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 8437#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 8438#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 8439#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 8440#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 8441#GateController_alarm] [2018-07-23 13:36:41,863 INFO L134 CoverageAnalysis]: Checked inductivity of 1431 backedges. 0 proven. 1431 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:41,863 INFO L450 AbstractCegarLoop]: Interpolant automaton has 57 states [2018-07-23 13:36:41,864 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2018-07-23 13:36:41,865 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1595, Invalid=1597, Unknown=0, NotChecked=0, Total=3192 [2018-07-23 13:36:41,865 INFO L87 Difference]: Start difference. First operand 57 states and 57 transitions. Second operand 57 states. [2018-07-23 13:36:41,922 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:41,923 INFO L93 Difference]: Finished difference Result 60 states and 60 transitions. [2018-07-23 13:36:41,923 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2018-07-23 13:36:41,923 INFO L78 Accepts]: Start accepts. Automaton has 57 states. Word has length 56 [2018-07-23 13:36:41,923 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:41,924 INFO L225 Difference]: With dead ends: 60 [2018-07-23 13:36:41,924 INFO L226 Difference]: Without dead ends: 58 [2018-07-23 13:36:41,925 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 55 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 55 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 105 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=1595, Invalid=1597, Unknown=0, NotChecked=0, Total=3192 [2018-07-23 13:36:41,925 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58 states. [2018-07-23 13:36:41,930 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58 to 58. [2018-07-23 13:36:41,931 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 58 states. [2018-07-23 13:36:41,931 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 58 transitions. [2018-07-23 13:36:41,931 INFO L78 Accepts]: Start accepts. Automaton has 58 states and 58 transitions. Word has length 56 [2018-07-23 13:36:41,931 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:41,932 INFO L471 AbstractCegarLoop]: Abstraction has 58 states and 58 transitions. [2018-07-23 13:36:41,932 INFO L472 AbstractCegarLoop]: Interpolant automaton has 57 states. [2018-07-23 13:36:41,932 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states and 58 transitions. [2018-07-23 13:36:41,933 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-07-23 13:36:41,933 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:41,933 INFO L357 BasicCegarLoop]: trace histogram [54, 1, 1, 1] [2018-07-23 13:36:41,933 INFO L414 AbstractCegarLoop]: === Iteration 55 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:41,933 INFO L82 PathProgramCache]: Analyzing trace with hash -1300160800, now seen corresponding path program 54 times [2018-07-23 13:36:41,934 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:41,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:42,305 INFO L134 CoverageAnalysis]: Checked inductivity of 1485 backedges. 0 proven. 1485 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:42,306 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:42,306 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [56] total 56 [2018-07-23 13:36:42,306 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:42,307 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:42,307 INFO L185 omatonBuilderFactory]: Interpolants [8704#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 8705#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 8706#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 8707#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 8708#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 8709#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 8710#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 8711#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 8712#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 8713#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 8714#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 8715#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 8716#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 8717#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 8718#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 8719#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 8720#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 8721#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 8722#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 8723#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 8724#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 8725#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 8726#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 8727#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 8728#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 8729#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 8730#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 8731#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 8732#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 8733#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 8734#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 8735#GateController_alarm, 8678#true, 8679#false, 8680#(<= (+ GateController_time 1000) GateController_thousand), 8681#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 8682#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 8683#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 8684#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 8685#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 8686#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 8687#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 8688#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 8689#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 8690#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 8691#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 8692#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 8693#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 8694#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 8695#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 8696#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 8697#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 8698#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 8699#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 8700#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 8701#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 8702#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 8703#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand))] [2018-07-23 13:36:42,308 INFO L134 CoverageAnalysis]: Checked inductivity of 1485 backedges. 0 proven. 1485 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:42,308 INFO L450 AbstractCegarLoop]: Interpolant automaton has 58 states [2018-07-23 13:36:42,308 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2018-07-23 13:36:42,309 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1652, Invalid=1654, Unknown=0, NotChecked=0, Total=3306 [2018-07-23 13:36:42,309 INFO L87 Difference]: Start difference. First operand 58 states and 58 transitions. Second operand 58 states. [2018-07-23 13:36:42,356 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:42,356 INFO L93 Difference]: Finished difference Result 61 states and 61 transitions. [2018-07-23 13:36:42,357 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2018-07-23 13:36:42,357 INFO L78 Accepts]: Start accepts. Automaton has 58 states. Word has length 57 [2018-07-23 13:36:42,357 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:42,358 INFO L225 Difference]: With dead ends: 61 [2018-07-23 13:36:42,358 INFO L226 Difference]: Without dead ends: 59 [2018-07-23 13:36:42,359 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 56 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 107 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=1652, Invalid=1654, Unknown=0, NotChecked=0, Total=3306 [2018-07-23 13:36:42,359 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2018-07-23 13:36:42,370 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 59. [2018-07-23 13:36:42,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 59 states. [2018-07-23 13:36:42,371 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 59 transitions. [2018-07-23 13:36:42,371 INFO L78 Accepts]: Start accepts. Automaton has 59 states and 59 transitions. Word has length 57 [2018-07-23 13:36:42,371 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:42,371 INFO L471 AbstractCegarLoop]: Abstraction has 59 states and 59 transitions. [2018-07-23 13:36:42,372 INFO L472 AbstractCegarLoop]: Interpolant automaton has 58 states. [2018-07-23 13:36:42,372 INFO L276 IsEmpty]: Start isEmpty. Operand 59 states and 59 transitions. [2018-07-23 13:36:42,372 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-07-23 13:36:42,372 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:42,373 INFO L357 BasicCegarLoop]: trace histogram [55, 1, 1, 1] [2018-07-23 13:36:42,373 INFO L414 AbstractCegarLoop]: === Iteration 56 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:42,373 INFO L82 PathProgramCache]: Analyzing trace with hash -1650269536, now seen corresponding path program 55 times [2018-07-23 13:36:42,373 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:42,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:42,766 INFO L134 CoverageAnalysis]: Checked inductivity of 1540 backedges. 0 proven. 1540 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:42,766 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:42,767 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [57] total 57 [2018-07-23 13:36:42,767 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:42,767 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:42,768 INFO L185 omatonBuilderFactory]: Interpolants [8976#true, 8977#false, 8978#(<= (+ GateController_time 1000) GateController_thousand), 8979#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 8980#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 8981#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 8982#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 8983#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 8984#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 8985#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 8986#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 8987#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 8988#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 8989#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 8990#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 8991#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 8992#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 8993#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 8994#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 8995#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 8996#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 8997#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 8998#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 8999#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 9000#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 9001#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 9002#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 9003#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 9004#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 9005#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 9006#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 9007#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 9008#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 9009#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 9010#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 9011#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 9012#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 9013#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 9014#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 9015#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 9016#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 9017#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 9018#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 9019#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 9020#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 9021#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 9022#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 9023#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 9024#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 9025#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 9026#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 9027#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 9028#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 9029#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 9030#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 9031#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 9032#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 9033#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 9034#GateController_alarm] [2018-07-23 13:36:42,768 INFO L134 CoverageAnalysis]: Checked inductivity of 1540 backedges. 0 proven. 1540 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:42,769 INFO L450 AbstractCegarLoop]: Interpolant automaton has 59 states [2018-07-23 13:36:42,769 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2018-07-23 13:36:42,770 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1710, Invalid=1712, Unknown=0, NotChecked=0, Total=3422 [2018-07-23 13:36:42,770 INFO L87 Difference]: Start difference. First operand 59 states and 59 transitions. Second operand 59 states. [2018-07-23 13:36:42,834 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:42,834 INFO L93 Difference]: Finished difference Result 62 states and 62 transitions. [2018-07-23 13:36:42,835 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2018-07-23 13:36:42,835 INFO L78 Accepts]: Start accepts. Automaton has 59 states. Word has length 58 [2018-07-23 13:36:42,835 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:42,836 INFO L225 Difference]: With dead ends: 62 [2018-07-23 13:36:42,836 INFO L226 Difference]: Without dead ends: 60 [2018-07-23 13:36:42,838 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 57 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 57 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 109 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=1710, Invalid=1712, Unknown=0, NotChecked=0, Total=3422 [2018-07-23 13:36:42,838 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states. [2018-07-23 13:36:42,844 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 60. [2018-07-23 13:36:42,844 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2018-07-23 13:36:42,844 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 60 transitions. [2018-07-23 13:36:42,845 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 60 transitions. Word has length 58 [2018-07-23 13:36:42,845 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:42,845 INFO L471 AbstractCegarLoop]: Abstraction has 60 states and 60 transitions. [2018-07-23 13:36:42,845 INFO L472 AbstractCegarLoop]: Interpolant automaton has 59 states. [2018-07-23 13:36:42,845 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 60 transitions. [2018-07-23 13:36:42,846 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-07-23 13:36:42,846 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:42,846 INFO L357 BasicCegarLoop]: trace histogram [56, 1, 1, 1] [2018-07-23 13:36:42,846 INFO L414 AbstractCegarLoop]: === Iteration 57 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:42,846 INFO L82 PathProgramCache]: Analyzing trace with hash 381261536, now seen corresponding path program 56 times [2018-07-23 13:36:42,846 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:42,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:43,331 INFO L134 CoverageAnalysis]: Checked inductivity of 1596 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:43,331 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:43,332 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58] total 58 [2018-07-23 13:36:43,332 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:43,332 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:43,333 INFO L185 omatonBuilderFactory]: Interpolants [9279#true, 9280#false, 9281#(<= (+ GateController_time 1000) GateController_thousand), 9282#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 9283#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 9284#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 9285#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 9286#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 9287#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 9288#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 9289#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 9290#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 9291#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 9292#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 9293#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 9294#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 9295#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 9296#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 9297#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 9298#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 9299#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 9300#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 9301#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 9302#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 9303#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 9304#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 9305#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 9306#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 9307#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 9308#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 9309#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 9310#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 9311#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 9312#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 9313#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 9314#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 9315#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 9316#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 9317#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 9318#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 9319#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 9320#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 9321#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 9322#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 9323#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 9324#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 9325#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 9326#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 9327#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 9328#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 9329#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 9330#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 9331#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 9332#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 9333#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 9334#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 9335#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 9336#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 9337#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 9338#GateController_alarm] [2018-07-23 13:36:43,333 INFO L134 CoverageAnalysis]: Checked inductivity of 1596 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:43,334 INFO L450 AbstractCegarLoop]: Interpolant automaton has 60 states [2018-07-23 13:36:43,335 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 60 interpolants. [2018-07-23 13:36:43,335 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1769, Invalid=1771, Unknown=0, NotChecked=0, Total=3540 [2018-07-23 13:36:43,335 INFO L87 Difference]: Start difference. First operand 60 states and 60 transitions. Second operand 60 states. [2018-07-23 13:36:43,407 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:43,407 INFO L93 Difference]: Finished difference Result 63 states and 63 transitions. [2018-07-23 13:36:43,408 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2018-07-23 13:36:43,408 INFO L78 Accepts]: Start accepts. Automaton has 60 states. Word has length 59 [2018-07-23 13:36:43,408 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:43,409 INFO L225 Difference]: With dead ends: 63 [2018-07-23 13:36:43,409 INFO L226 Difference]: Without dead ends: 61 [2018-07-23 13:36:43,410 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 58 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 111 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=1769, Invalid=1771, Unknown=0, NotChecked=0, Total=3540 [2018-07-23 13:36:43,410 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states. [2018-07-23 13:36:43,416 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 61. [2018-07-23 13:36:43,416 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 61 states. [2018-07-23 13:36:43,417 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 61 transitions. [2018-07-23 13:36:43,417 INFO L78 Accepts]: Start accepts. Automaton has 61 states and 61 transitions. Word has length 59 [2018-07-23 13:36:43,417 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:43,417 INFO L471 AbstractCegarLoop]: Abstraction has 61 states and 61 transitions. [2018-07-23 13:36:43,417 INFO L472 AbstractCegarLoop]: Interpolant automaton has 60 states. [2018-07-23 13:36:43,417 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 61 transitions. [2018-07-23 13:36:43,418 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2018-07-23 13:36:43,418 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:43,418 INFO L357 BasicCegarLoop]: trace histogram [57, 1, 1, 1] [2018-07-23 13:36:43,419 INFO L414 AbstractCegarLoop]: === Iteration 58 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:43,419 INFO L82 PathProgramCache]: Analyzing trace with hash -1065784672, now seen corresponding path program 57 times [2018-07-23 13:36:43,419 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:43,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:43,860 INFO L134 CoverageAnalysis]: Checked inductivity of 1653 backedges. 0 proven. 1653 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:43,860 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:43,860 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [59] total 59 [2018-07-23 13:36:43,861 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:43,861 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:43,861 INFO L185 omatonBuilderFactory]: Interpolants [9600#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 9601#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 9602#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 9603#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 9604#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 9605#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 9606#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 9607#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 9608#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 9609#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 9610#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 9611#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 9612#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 9613#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 9614#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 9615#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 9616#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 9617#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 9618#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 9619#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 9620#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 9621#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 9622#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 9623#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 9624#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 9625#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 9626#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 9627#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 9628#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 9629#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 9630#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 9631#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 9632#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 9633#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 9634#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 9635#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 9636#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 9637#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 9638#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 9639#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 9640#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 9641#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 9642#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 9643#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 9644#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 9645#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 9646#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 9647#GateController_alarm, 9587#true, 9588#false, 9589#(<= (+ GateController_time 1000) GateController_thousand), 9590#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 9591#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 9592#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 9593#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 9594#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 9595#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 9596#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 9597#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 9598#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 9599#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand))] [2018-07-23 13:36:43,862 INFO L134 CoverageAnalysis]: Checked inductivity of 1653 backedges. 0 proven. 1653 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:43,862 INFO L450 AbstractCegarLoop]: Interpolant automaton has 61 states [2018-07-23 13:36:43,863 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 61 interpolants. [2018-07-23 13:36:43,863 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1829, Invalid=1831, Unknown=0, NotChecked=0, Total=3660 [2018-07-23 13:36:43,864 INFO L87 Difference]: Start difference. First operand 61 states and 61 transitions. Second operand 61 states. [2018-07-23 13:36:43,930 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:43,930 INFO L93 Difference]: Finished difference Result 64 states and 64 transitions. [2018-07-23 13:36:43,930 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 61 states. [2018-07-23 13:36:43,930 INFO L78 Accepts]: Start accepts. Automaton has 61 states. Word has length 60 [2018-07-23 13:36:43,931 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:43,931 INFO L225 Difference]: With dead ends: 64 [2018-07-23 13:36:43,931 INFO L226 Difference]: Without dead ends: 62 [2018-07-23 13:36:43,932 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 59 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 59 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 113 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=1829, Invalid=1831, Unknown=0, NotChecked=0, Total=3660 [2018-07-23 13:36:43,932 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62 states. [2018-07-23 13:36:43,938 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62 to 62. [2018-07-23 13:36:43,938 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 62 states. [2018-07-23 13:36:43,938 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62 states to 62 states and 62 transitions. [2018-07-23 13:36:43,938 INFO L78 Accepts]: Start accepts. Automaton has 62 states and 62 transitions. Word has length 60 [2018-07-23 13:36:43,939 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:43,939 INFO L471 AbstractCegarLoop]: Abstraction has 62 states and 62 transitions. [2018-07-23 13:36:43,939 INFO L472 AbstractCegarLoop]: Interpolant automaton has 61 states. [2018-07-23 13:36:43,939 INFO L276 IsEmpty]: Start isEmpty. Operand 62 states and 62 transitions. [2018-07-23 13:36:43,939 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2018-07-23 13:36:43,940 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:43,940 INFO L357 BasicCegarLoop]: trace histogram [58, 1, 1, 1] [2018-07-23 13:36:43,940 INFO L414 AbstractCegarLoop]: === Iteration 59 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:43,940 INFO L82 PathProgramCache]: Analyzing trace with hash 1320423136, now seen corresponding path program 58 times [2018-07-23 13:36:43,940 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:43,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:44,370 INFO L134 CoverageAnalysis]: Checked inductivity of 1711 backedges. 0 proven. 1711 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:44,370 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:44,370 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [60] total 60 [2018-07-23 13:36:44,371 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:44,371 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:44,371 INFO L185 omatonBuilderFactory]: Interpolants [9900#true, 9901#false, 9902#(<= (+ GateController_time 1000) GateController_thousand), 9903#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 9904#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 9905#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 9906#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 9907#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 9908#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 9909#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 9910#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 9911#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 9912#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 9913#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 9914#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 9915#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 9916#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 9917#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 9918#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 9919#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 9920#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 9921#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 9922#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 9923#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 9924#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 9925#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 9926#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 9927#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 9928#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 9929#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 9930#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 9931#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 9932#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 9933#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 9934#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 9935#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 9936#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 9937#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 9938#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 9939#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 9940#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 9941#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 9942#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 9943#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 9944#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 9945#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 9946#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 9947#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 9948#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 9949#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 9950#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 9951#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 9952#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 9953#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 9954#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 9955#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 9956#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 9957#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 9958#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 9959#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 9960#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 9961#GateController_alarm] [2018-07-23 13:36:44,372 INFO L134 CoverageAnalysis]: Checked inductivity of 1711 backedges. 0 proven. 1711 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:44,372 INFO L450 AbstractCegarLoop]: Interpolant automaton has 62 states [2018-07-23 13:36:44,373 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2018-07-23 13:36:44,374 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1890, Invalid=1892, Unknown=0, NotChecked=0, Total=3782 [2018-07-23 13:36:44,374 INFO L87 Difference]: Start difference. First operand 62 states and 62 transitions. Second operand 62 states. [2018-07-23 13:36:44,435 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:44,435 INFO L93 Difference]: Finished difference Result 65 states and 65 transitions. [2018-07-23 13:36:44,436 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 62 states. [2018-07-23 13:36:44,436 INFO L78 Accepts]: Start accepts. Automaton has 62 states. Word has length 61 [2018-07-23 13:36:44,436 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:44,436 INFO L225 Difference]: With dead ends: 65 [2018-07-23 13:36:44,437 INFO L226 Difference]: Without dead ends: 63 [2018-07-23 13:36:44,439 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 60 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 115 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=1890, Invalid=1892, Unknown=0, NotChecked=0, Total=3782 [2018-07-23 13:36:44,439 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63 states. [2018-07-23 13:36:44,444 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63 to 63. [2018-07-23 13:36:44,445 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2018-07-23 13:36:44,445 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 63 transitions. [2018-07-23 13:36:44,445 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 63 transitions. Word has length 61 [2018-07-23 13:36:44,445 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:44,446 INFO L471 AbstractCegarLoop]: Abstraction has 63 states and 63 transitions. [2018-07-23 13:36:44,446 INFO L472 AbstractCegarLoop]: Interpolant automaton has 62 states. [2018-07-23 13:36:44,446 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 63 transitions. [2018-07-23 13:36:44,446 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-07-23 13:36:44,446 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:44,447 INFO L357 BasicCegarLoop]: trace histogram [59, 1, 1, 1] [2018-07-23 13:36:44,447 INFO L414 AbstractCegarLoop]: === Iteration 60 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:44,447 INFO L82 PathProgramCache]: Analyzing trace with hash -2016546144, now seen corresponding path program 59 times [2018-07-23 13:36:44,447 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:44,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:44,885 INFO L134 CoverageAnalysis]: Checked inductivity of 1770 backedges. 0 proven. 1770 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:44,885 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:44,885 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [61] total 61 [2018-07-23 13:36:44,886 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:44,886 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:44,886 INFO L185 omatonBuilderFactory]: Interpolants [10240#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 10241#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 10242#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 10243#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 10244#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 10245#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 10246#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 10247#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 10248#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 10249#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 10250#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 10251#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 10252#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 10253#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 10254#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 10255#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 10256#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 10257#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 10258#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 10259#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 10260#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 10261#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 10262#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 10263#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 10264#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 10265#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 10266#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 10267#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 10268#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 10269#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 10270#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 10271#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 10272#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 10273#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 10274#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 10275#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 10276#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 10277#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 10278#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 10279#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 10280#GateController_alarm, 10218#true, 10219#false, 10220#(<= (+ GateController_time 1000) GateController_thousand), 10221#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 10222#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 10223#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 10224#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 10225#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 10226#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 10227#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 10228#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 10229#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 10230#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 10231#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 10232#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 10233#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 10234#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 10235#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 10236#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 10237#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 10238#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 10239#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand))] [2018-07-23 13:36:44,887 INFO L134 CoverageAnalysis]: Checked inductivity of 1770 backedges. 0 proven. 1770 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:44,887 INFO L450 AbstractCegarLoop]: Interpolant automaton has 63 states [2018-07-23 13:36:44,888 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 63 interpolants. [2018-07-23 13:36:44,888 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1952, Invalid=1954, Unknown=0, NotChecked=0, Total=3906 [2018-07-23 13:36:44,889 INFO L87 Difference]: Start difference. First operand 63 states and 63 transitions. Second operand 63 states. [2018-07-23 13:36:44,937 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:44,937 INFO L93 Difference]: Finished difference Result 66 states and 66 transitions. [2018-07-23 13:36:44,937 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2018-07-23 13:36:44,938 INFO L78 Accepts]: Start accepts. Automaton has 63 states. Word has length 62 [2018-07-23 13:36:44,938 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:44,938 INFO L225 Difference]: With dead ends: 66 [2018-07-23 13:36:44,938 INFO L226 Difference]: Without dead ends: 64 [2018-07-23 13:36:44,939 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 61 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 61 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 117 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=1952, Invalid=1954, Unknown=0, NotChecked=0, Total=3906 [2018-07-23 13:36:44,940 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states. [2018-07-23 13:36:44,945 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 64. [2018-07-23 13:36:44,946 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 64 states. [2018-07-23 13:36:44,946 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 64 transitions. [2018-07-23 13:36:44,946 INFO L78 Accepts]: Start accepts. Automaton has 64 states and 64 transitions. Word has length 62 [2018-07-23 13:36:44,946 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:44,946 INFO L471 AbstractCegarLoop]: Abstraction has 64 states and 64 transitions. [2018-07-23 13:36:44,946 INFO L472 AbstractCegarLoop]: Interpolant automaton has 63 states. [2018-07-23 13:36:44,947 INFO L276 IsEmpty]: Start isEmpty. Operand 64 states and 64 transitions. [2018-07-23 13:36:44,947 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2018-07-23 13:36:44,947 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:44,947 INFO L357 BasicCegarLoop]: trace histogram [60, 1, 1, 1] [2018-07-23 13:36:44,948 INFO L414 AbstractCegarLoop]: === Iteration 61 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:44,948 INFO L82 PathProgramCache]: Analyzing trace with hash 1911588576, now seen corresponding path program 60 times [2018-07-23 13:36:44,948 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:44,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:45,336 INFO L134 CoverageAnalysis]: Checked inductivity of 1830 backedges. 0 proven. 1830 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:45,336 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:45,336 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [62] total 62 [2018-07-23 13:36:45,336 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:45,337 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:45,337 INFO L185 omatonBuilderFactory]: Interpolants [10541#true, 10542#false, 10543#(<= (+ GateController_time 1000) GateController_thousand), 10544#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 10545#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 10546#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 10547#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 10548#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 10549#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 10550#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 10551#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 10552#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 10553#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 10554#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 10555#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 10556#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 10557#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 10558#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 10559#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 10560#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 10561#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 10562#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 10563#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 10564#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 10565#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 10566#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 10567#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 10568#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 10569#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 10570#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 10571#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 10572#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 10573#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 10574#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 10575#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 10576#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 10577#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 10578#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 10579#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 10580#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 10581#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 10582#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 10583#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 10584#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 10585#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 10586#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 10587#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 10588#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 10589#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 10590#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 10591#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 10592#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 10593#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 10594#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 10595#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 10596#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 10597#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 10598#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 10599#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 10600#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 10601#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 10602#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 10603#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 10604#GateController_alarm] [2018-07-23 13:36:45,338 INFO L134 CoverageAnalysis]: Checked inductivity of 1830 backedges. 0 proven. 1830 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:45,338 INFO L450 AbstractCegarLoop]: Interpolant automaton has 64 states [2018-07-23 13:36:45,339 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 64 interpolants. [2018-07-23 13:36:45,339 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2015, Invalid=2017, Unknown=0, NotChecked=0, Total=4032 [2018-07-23 13:36:45,340 INFO L87 Difference]: Start difference. First operand 64 states and 64 transitions. Second operand 64 states. [2018-07-23 13:36:45,396 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:45,396 INFO L93 Difference]: Finished difference Result 67 states and 67 transitions. [2018-07-23 13:36:45,396 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 64 states. [2018-07-23 13:36:45,396 INFO L78 Accepts]: Start accepts. Automaton has 64 states. Word has length 63 [2018-07-23 13:36:45,396 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:45,397 INFO L225 Difference]: With dead ends: 67 [2018-07-23 13:36:45,397 INFO L226 Difference]: Without dead ends: 65 [2018-07-23 13:36:45,398 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 62 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 119 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=2015, Invalid=2017, Unknown=0, NotChecked=0, Total=4032 [2018-07-23 13:36:45,398 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65 states. [2018-07-23 13:36:45,404 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65 to 65. [2018-07-23 13:36:45,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 65 states. [2018-07-23 13:36:45,404 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 65 transitions. [2018-07-23 13:36:45,405 INFO L78 Accepts]: Start accepts. Automaton has 65 states and 65 transitions. Word has length 63 [2018-07-23 13:36:45,405 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:45,405 INFO L471 AbstractCegarLoop]: Abstraction has 65 states and 65 transitions. [2018-07-23 13:36:45,405 INFO L472 AbstractCegarLoop]: Interpolant automaton has 64 states. [2018-07-23 13:36:45,405 INFO L276 IsEmpty]: Start isEmpty. Operand 65 states and 65 transitions. [2018-07-23 13:36:45,406 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-07-23 13:36:45,406 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:45,406 INFO L357 BasicCegarLoop]: trace histogram [61, 1, 1, 1] [2018-07-23 13:36:45,406 INFO L414 AbstractCegarLoop]: === Iteration 62 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:45,406 INFO L82 PathProgramCache]: Analyzing trace with hash -870286688, now seen corresponding path program 61 times [2018-07-23 13:36:45,406 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:45,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:45,806 INFO L134 CoverageAnalysis]: Checked inductivity of 1891 backedges. 0 proven. 1891 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:45,806 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:45,807 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [63] total 63 [2018-07-23 13:36:45,807 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:45,807 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:45,808 INFO L185 omatonBuilderFactory]: Interpolants [10880#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 10881#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 10882#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 10883#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 10884#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 10885#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 10886#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 10887#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 10888#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 10889#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 10890#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 10891#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 10892#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 10893#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 10894#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 10895#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 10896#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 10897#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 10898#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 10899#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 10900#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 10901#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 10902#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 10903#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 10904#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 10905#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 10906#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 10907#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 10908#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 10909#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 10910#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 10911#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 10912#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 10913#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 10914#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 10915#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 10916#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 10917#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 10918#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 10919#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 10920#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 10921#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 10922#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 10923#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 10924#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 10925#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 10926#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 10927#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 10928#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 10929#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 10930#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 10931#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 10932#(or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)), 10933#GateController_alarm, 10869#true, 10870#false, 10871#(<= (+ GateController_time 1000) GateController_thousand), 10872#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 10873#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 10874#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 10875#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 10876#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 10877#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 10878#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 10879#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand))] [2018-07-23 13:36:45,808 INFO L134 CoverageAnalysis]: Checked inductivity of 1891 backedges. 0 proven. 1891 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:45,808 INFO L450 AbstractCegarLoop]: Interpolant automaton has 65 states [2018-07-23 13:36:45,809 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2018-07-23 13:36:45,810 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2079, Invalid=2081, Unknown=0, NotChecked=0, Total=4160 [2018-07-23 13:36:45,810 INFO L87 Difference]: Start difference. First operand 65 states and 65 transitions. Second operand 65 states. [2018-07-23 13:36:45,868 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:45,868 INFO L93 Difference]: Finished difference Result 68 states and 68 transitions. [2018-07-23 13:36:45,868 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2018-07-23 13:36:45,868 INFO L78 Accepts]: Start accepts. Automaton has 65 states. Word has length 64 [2018-07-23 13:36:45,869 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:45,869 INFO L225 Difference]: With dead ends: 68 [2018-07-23 13:36:45,869 INFO L226 Difference]: Without dead ends: 66 [2018-07-23 13:36:45,870 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 63 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 121 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=2079, Invalid=2081, Unknown=0, NotChecked=0, Total=4160 [2018-07-23 13:36:45,870 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66 states. [2018-07-23 13:36:45,876 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66 to 66. [2018-07-23 13:36:45,876 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 66 states. [2018-07-23 13:36:45,876 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 66 transitions. [2018-07-23 13:36:45,876 INFO L78 Accepts]: Start accepts. Automaton has 66 states and 66 transitions. Word has length 64 [2018-07-23 13:36:45,877 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:45,877 INFO L471 AbstractCegarLoop]: Abstraction has 66 states and 66 transitions. [2018-07-23 13:36:45,877 INFO L472 AbstractCegarLoop]: Interpolant automaton has 65 states. [2018-07-23 13:36:45,877 INFO L276 IsEmpty]: Start isEmpty. Operand 66 states and 66 transitions. [2018-07-23 13:36:45,877 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2018-07-23 13:36:45,877 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:45,878 INFO L357 BasicCegarLoop]: trace histogram [62, 1, 1, 1] [2018-07-23 13:36:45,878 INFO L414 AbstractCegarLoop]: === Iteration 63 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:45,878 INFO L82 PathProgramCache]: Analyzing trace with hash -1209073952, now seen corresponding path program 62 times [2018-07-23 13:36:45,878 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:45,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:46,279 INFO L134 CoverageAnalysis]: Checked inductivity of 1953 backedges. 0 proven. 1953 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:46,280 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:46,280 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64] total 64 [2018-07-23 13:36:46,280 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:46,280 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:46,281 INFO L185 omatonBuilderFactory]: Interpolants [11264#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 11265#(or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)), 11266#(or GateController_alarm (<= (+ GateController_time 380) GateController_thousand)), 11267#GateController_alarm, 11202#true, 11203#false, 11204#(<= (+ GateController_time 1000) GateController_thousand), 11205#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 11206#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 11207#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 11208#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 11209#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 11210#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 11211#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 11212#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 11213#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 11214#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 11215#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 11216#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 11217#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 11218#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 11219#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 11220#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 11221#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 11222#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 11223#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 11224#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 11225#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 11226#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 11227#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 11228#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 11229#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 11230#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 11231#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 11232#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 11233#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 11234#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 11235#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 11236#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 11237#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 11238#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 11239#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 11240#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 11241#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 11242#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 11243#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 11244#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 11245#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 11246#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 11247#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 11248#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 11249#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 11250#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 11251#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 11252#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 11253#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 11254#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 11255#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 11256#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 11257#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 11258#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 11259#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 11260#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 11261#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 11262#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 11263#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand))] [2018-07-23 13:36:46,282 INFO L134 CoverageAnalysis]: Checked inductivity of 1953 backedges. 0 proven. 1953 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:46,282 INFO L450 AbstractCegarLoop]: Interpolant automaton has 66 states [2018-07-23 13:36:46,283 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 66 interpolants. [2018-07-23 13:36:46,283 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2144, Invalid=2146, Unknown=0, NotChecked=0, Total=4290 [2018-07-23 13:36:46,284 INFO L87 Difference]: Start difference. First operand 66 states and 66 transitions. Second operand 66 states. [2018-07-23 13:36:46,336 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:46,337 INFO L93 Difference]: Finished difference Result 69 states and 69 transitions. [2018-07-23 13:36:46,337 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 66 states. [2018-07-23 13:36:46,337 INFO L78 Accepts]: Start accepts. Automaton has 66 states. Word has length 65 [2018-07-23 13:36:46,337 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:46,338 INFO L225 Difference]: With dead ends: 69 [2018-07-23 13:36:46,338 INFO L226 Difference]: Without dead ends: 67 [2018-07-23 13:36:46,339 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 64 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 123 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=2144, Invalid=2146, Unknown=0, NotChecked=0, Total=4290 [2018-07-23 13:36:46,339 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states. [2018-07-23 13:36:46,345 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 67. [2018-07-23 13:36:46,345 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 67 states. [2018-07-23 13:36:46,346 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 67 transitions. [2018-07-23 13:36:46,346 INFO L78 Accepts]: Start accepts. Automaton has 67 states and 67 transitions. Word has length 65 [2018-07-23 13:36:46,346 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:46,346 INFO L471 AbstractCegarLoop]: Abstraction has 67 states and 67 transitions. [2018-07-23 13:36:46,346 INFO L472 AbstractCegarLoop]: Interpolant automaton has 66 states. [2018-07-23 13:36:46,346 INFO L276 IsEmpty]: Start isEmpty. Operand 67 states and 67 transitions. [2018-07-23 13:36:46,347 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-07-23 13:36:46,347 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:46,347 INFO L357 BasicCegarLoop]: trace histogram [63, 1, 1, 1] [2018-07-23 13:36:46,347 INFO L414 AbstractCegarLoop]: === Iteration 64 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:46,348 INFO L82 PathProgramCache]: Analyzing trace with hash 1173422752, now seen corresponding path program 63 times [2018-07-23 13:36:46,348 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:46,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:46,788 INFO L134 CoverageAnalysis]: Checked inductivity of 2016 backedges. 0 proven. 2016 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:46,788 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:46,789 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [65] total 65 [2018-07-23 13:36:46,789 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:46,789 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:46,790 INFO L185 omatonBuilderFactory]: Interpolants [11540#true, 11541#false, 11542#(<= (+ GateController_time 1000) GateController_thousand), 11543#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 11544#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 11545#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 11546#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 11547#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 11548#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 11549#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 11550#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 11551#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 11552#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 11553#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 11554#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 11555#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 11556#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 11557#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 11558#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 11559#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 11560#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 11561#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 11562#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 11563#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 11564#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 11565#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 11566#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 11567#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 11568#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 11569#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 11570#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 11571#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 11572#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 11573#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 11574#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 11575#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 11576#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 11577#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 11578#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 11579#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 11580#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 11581#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 11582#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 11583#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 11584#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 11585#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 11586#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 11587#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 11588#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 11589#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 11590#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 11591#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 11592#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 11593#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 11594#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 11595#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 11596#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 11597#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 11598#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 11599#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 11600#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 11601#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 11602#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 11603#(or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)), 11604#(or GateController_alarm (<= (+ GateController_time 380) GateController_thousand)), 11605#(or GateController_alarm (<= (+ GateController_time 370) GateController_thousand)), 11606#GateController_alarm] [2018-07-23 13:36:46,790 INFO L134 CoverageAnalysis]: Checked inductivity of 2016 backedges. 0 proven. 2016 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:46,790 INFO L450 AbstractCegarLoop]: Interpolant automaton has 67 states [2018-07-23 13:36:46,791 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 67 interpolants. [2018-07-23 13:36:46,792 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2210, Invalid=2212, Unknown=0, NotChecked=0, Total=4422 [2018-07-23 13:36:46,792 INFO L87 Difference]: Start difference. First operand 67 states and 67 transitions. Second operand 67 states. [2018-07-23 13:36:46,857 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:46,857 INFO L93 Difference]: Finished difference Result 70 states and 70 transitions. [2018-07-23 13:36:46,858 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 67 states. [2018-07-23 13:36:46,858 INFO L78 Accepts]: Start accepts. Automaton has 67 states. Word has length 66 [2018-07-23 13:36:46,858 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:46,858 INFO L225 Difference]: With dead ends: 70 [2018-07-23 13:36:46,859 INFO L226 Difference]: Without dead ends: 68 [2018-07-23 13:36:46,860 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 65 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 65 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 125 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=2210, Invalid=2212, Unknown=0, NotChecked=0, Total=4422 [2018-07-23 13:36:46,860 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68 states. [2018-07-23 13:36:46,866 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68 to 68. [2018-07-23 13:36:46,866 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 68 states. [2018-07-23 13:36:46,866 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68 states to 68 states and 68 transitions. [2018-07-23 13:36:46,866 INFO L78 Accepts]: Start accepts. Automaton has 68 states and 68 transitions. Word has length 66 [2018-07-23 13:36:46,867 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:46,867 INFO L471 AbstractCegarLoop]: Abstraction has 68 states and 68 transitions. [2018-07-23 13:36:46,867 INFO L472 AbstractCegarLoop]: Interpolant automaton has 67 states. [2018-07-23 13:36:46,867 INFO L276 IsEmpty]: Start isEmpty. Operand 68 states and 68 transitions. [2018-07-23 13:36:46,867 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2018-07-23 13:36:46,868 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:46,868 INFO L357 BasicCegarLoop]: trace histogram [64, 1, 1, 1] [2018-07-23 13:36:46,868 INFO L414 AbstractCegarLoop]: === Iteration 65 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:46,868 INFO L82 PathProgramCache]: Analyzing trace with hash 2016376544, now seen corresponding path program 64 times [2018-07-23 13:36:46,868 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:46,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:47,353 INFO L134 CoverageAnalysis]: Checked inductivity of 2080 backedges. 0 proven. 2080 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:47,353 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:47,354 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [66] total 66 [2018-07-23 13:36:47,354 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:47,354 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:47,355 INFO L185 omatonBuilderFactory]: Interpolants [11904#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 11905#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 11906#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 11907#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 11908#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 11909#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 11910#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 11911#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 11912#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 11913#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 11914#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 11915#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 11916#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 11917#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 11918#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 11919#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 11920#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 11921#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 11922#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 11923#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 11924#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 11925#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 11926#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 11927#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 11928#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 11929#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 11930#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 11931#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 11932#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 11933#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 11934#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 11935#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 11936#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 11937#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 11938#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 11939#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 11940#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 11941#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 11942#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 11943#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 11944#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 11945#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 11946#(or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)), 11947#(or GateController_alarm (<= (+ GateController_time 380) GateController_thousand)), 11948#(or GateController_alarm (<= (+ GateController_time 370) GateController_thousand)), 11949#(or (<= (+ GateController_time 360) GateController_thousand) GateController_alarm), 11950#GateController_alarm, 11883#true, 11884#false, 11885#(<= (+ GateController_time 1000) GateController_thousand), 11886#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 11887#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 11888#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 11889#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 11890#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 11891#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 11892#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 11893#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 11894#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 11895#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 11896#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 11897#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 11898#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 11899#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 11900#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 11901#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 11902#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 11903#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand))] [2018-07-23 13:36:47,355 INFO L134 CoverageAnalysis]: Checked inductivity of 2080 backedges. 0 proven. 2080 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:47,356 INFO L450 AbstractCegarLoop]: Interpolant automaton has 68 states [2018-07-23 13:36:47,357 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 68 interpolants. [2018-07-23 13:36:47,357 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2277, Invalid=2279, Unknown=0, NotChecked=0, Total=4556 [2018-07-23 13:36:47,358 INFO L87 Difference]: Start difference. First operand 68 states and 68 transitions. Second operand 68 states. [2018-07-23 13:36:47,422 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:47,422 INFO L93 Difference]: Finished difference Result 71 states and 71 transitions. [2018-07-23 13:36:47,422 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2018-07-23 13:36:47,422 INFO L78 Accepts]: Start accepts. Automaton has 68 states. Word has length 67 [2018-07-23 13:36:47,423 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:47,423 INFO L225 Difference]: With dead ends: 71 [2018-07-23 13:36:47,423 INFO L226 Difference]: Without dead ends: 69 [2018-07-23 13:36:47,424 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 66 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 127 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=2277, Invalid=2279, Unknown=0, NotChecked=0, Total=4556 [2018-07-23 13:36:47,424 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states. [2018-07-23 13:36:47,431 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 69. [2018-07-23 13:36:47,432 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 69 states. [2018-07-23 13:36:47,432 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 69 transitions. [2018-07-23 13:36:47,432 INFO L78 Accepts]: Start accepts. Automaton has 69 states and 69 transitions. Word has length 67 [2018-07-23 13:36:47,432 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:47,433 INFO L471 AbstractCegarLoop]: Abstraction has 69 states and 69 transitions. [2018-07-23 13:36:47,433 INFO L472 AbstractCegarLoop]: Interpolant automaton has 68 states. [2018-07-23 13:36:47,433 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 69 transitions. [2018-07-23 13:36:47,434 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-07-23 13:36:47,434 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:47,434 INFO L357 BasicCegarLoop]: trace histogram [65, 1, 1, 1] [2018-07-23 13:36:47,434 INFO L414 AbstractCegarLoop]: === Iteration 66 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:47,435 INFO L82 PathProgramCache]: Analyzing trace with hash -1916826976, now seen corresponding path program 65 times [2018-07-23 13:36:47,435 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:47,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:48,014 INFO L134 CoverageAnalysis]: Checked inductivity of 2145 backedges. 0 proven. 2145 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:48,014 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:48,014 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [67] total 67 [2018-07-23 13:36:48,015 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:48,015 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:48,015 INFO L185 omatonBuilderFactory]: Interpolants [12288#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 12289#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 12290#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 12291#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 12292#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 12293#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 12294#(or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)), 12295#(or GateController_alarm (<= (+ GateController_time 380) GateController_thousand)), 12296#(or GateController_alarm (<= (+ GateController_time 370) GateController_thousand)), 12297#(or (<= (+ GateController_time 360) GateController_thousand) GateController_alarm), 12298#(or (<= (+ GateController_time 350) GateController_thousand) GateController_alarm), 12299#GateController_alarm, 12231#true, 12232#false, 12233#(<= (+ GateController_time 1000) GateController_thousand), 12234#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 12235#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 12236#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 12237#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 12238#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 12239#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 12240#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 12241#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 12242#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 12243#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 12244#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 12245#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 12246#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 12247#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 12248#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 12249#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 12250#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 12251#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 12252#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 12253#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 12254#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 12255#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 12256#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 12257#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 12258#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 12259#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 12260#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 12261#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 12262#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 12263#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 12264#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 12265#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 12266#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 12267#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 12268#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 12269#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 12270#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 12271#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 12272#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 12273#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 12274#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 12275#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 12276#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 12277#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 12278#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 12279#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 12280#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 12281#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 12282#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 12283#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 12284#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 12285#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 12286#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 12287#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand))] [2018-07-23 13:36:48,016 INFO L134 CoverageAnalysis]: Checked inductivity of 2145 backedges. 0 proven. 2145 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:48,016 INFO L450 AbstractCegarLoop]: Interpolant automaton has 69 states [2018-07-23 13:36:48,016 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2018-07-23 13:36:48,017 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2345, Invalid=2347, Unknown=0, NotChecked=0, Total=4692 [2018-07-23 13:36:48,017 INFO L87 Difference]: Start difference. First operand 69 states and 69 transitions. Second operand 69 states. [2018-07-23 13:36:48,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:48,066 INFO L93 Difference]: Finished difference Result 72 states and 72 transitions. [2018-07-23 13:36:48,066 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2018-07-23 13:36:48,066 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 68 [2018-07-23 13:36:48,066 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:48,067 INFO L225 Difference]: With dead ends: 72 [2018-07-23 13:36:48,067 INFO L226 Difference]: Without dead ends: 70 [2018-07-23 13:36:48,068 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 67 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 129 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=2345, Invalid=2347, Unknown=0, NotChecked=0, Total=4692 [2018-07-23 13:36:48,069 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70 states. [2018-07-23 13:36:48,074 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70 to 70. [2018-07-23 13:36:48,074 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 70 states. [2018-07-23 13:36:48,074 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70 states to 70 states and 70 transitions. [2018-07-23 13:36:48,075 INFO L78 Accepts]: Start accepts. Automaton has 70 states and 70 transitions. Word has length 68 [2018-07-23 13:36:48,075 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:48,075 INFO L471 AbstractCegarLoop]: Abstraction has 70 states and 70 transitions. [2018-07-23 13:36:48,075 INFO L472 AbstractCegarLoop]: Interpolant automaton has 69 states. [2018-07-23 13:36:48,075 INFO L276 IsEmpty]: Start isEmpty. Operand 70 states and 70 transitions. [2018-07-23 13:36:48,076 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-07-23 13:36:48,076 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:48,076 INFO L357 BasicCegarLoop]: trace histogram [66, 1, 1, 1] [2018-07-23 13:36:48,076 INFO L414 AbstractCegarLoop]: === Iteration 67 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:48,076 INFO L82 PathProgramCache]: Analyzing trace with hash 707915488, now seen corresponding path program 66 times [2018-07-23 13:36:48,076 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:48,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:48,467 INFO L134 CoverageAnalysis]: Checked inductivity of 2211 backedges. 0 proven. 2211 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:48,468 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:48,468 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [68] total 68 [2018-07-23 13:36:48,468 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:48,468 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:48,469 INFO L185 omatonBuilderFactory]: Interpolants [12584#true, 12585#false, 12586#(<= (+ GateController_time 1000) GateController_thousand), 12587#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 12588#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 12589#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 12590#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 12591#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 12592#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 12593#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 12594#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 12595#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 12596#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 12597#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 12598#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 12599#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 12600#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 12601#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 12602#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 12603#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 12604#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 12605#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 12606#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 12607#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 12608#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 12609#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 12610#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 12611#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 12612#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 12613#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 12614#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 12615#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 12616#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 12617#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 12618#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 12619#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 12620#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 12621#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 12622#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 12623#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 12624#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 12625#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 12626#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 12627#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 12628#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 12629#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 12630#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 12631#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 12632#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 12633#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 12634#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 12635#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 12636#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 12637#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 12638#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 12639#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 12640#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 12641#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 12642#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 12643#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 12644#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 12645#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 12646#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 12647#(or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)), 12648#(or GateController_alarm (<= (+ GateController_time 380) GateController_thousand)), 12649#(or GateController_alarm (<= (+ GateController_time 370) GateController_thousand)), 12650#(or (<= (+ GateController_time 360) GateController_thousand) GateController_alarm), 12651#(or (<= (+ GateController_time 350) GateController_thousand) GateController_alarm), 12652#(or GateController_alarm (<= (+ GateController_time 340) GateController_thousand)), 12653#GateController_alarm] [2018-07-23 13:36:48,469 INFO L134 CoverageAnalysis]: Checked inductivity of 2211 backedges. 0 proven. 2211 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:48,470 INFO L450 AbstractCegarLoop]: Interpolant automaton has 70 states [2018-07-23 13:36:48,470 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2018-07-23 13:36:48,471 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2414, Invalid=2416, Unknown=0, NotChecked=0, Total=4830 [2018-07-23 13:36:48,471 INFO L87 Difference]: Start difference. First operand 70 states and 70 transitions. Second operand 70 states. [2018-07-23 13:36:48,537 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:48,538 INFO L93 Difference]: Finished difference Result 73 states and 73 transitions. [2018-07-23 13:36:48,538 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 70 states. [2018-07-23 13:36:48,538 INFO L78 Accepts]: Start accepts. Automaton has 70 states. Word has length 69 [2018-07-23 13:36:48,538 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:48,539 INFO L225 Difference]: With dead ends: 73 [2018-07-23 13:36:48,539 INFO L226 Difference]: Without dead ends: 71 [2018-07-23 13:36:48,540 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 68 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 68 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 131 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=2414, Invalid=2416, Unknown=0, NotChecked=0, Total=4830 [2018-07-23 13:36:48,540 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71 states. [2018-07-23 13:36:48,545 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71 to 71. [2018-07-23 13:36:48,545 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 71 states. [2018-07-23 13:36:48,546 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71 states to 71 states and 71 transitions. [2018-07-23 13:36:48,546 INFO L78 Accepts]: Start accepts. Automaton has 71 states and 71 transitions. Word has length 69 [2018-07-23 13:36:48,546 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:48,546 INFO L471 AbstractCegarLoop]: Abstraction has 71 states and 71 transitions. [2018-07-23 13:36:48,546 INFO L472 AbstractCegarLoop]: Interpolant automaton has 70 states. [2018-07-23 13:36:48,546 INFO L276 IsEmpty]: Start isEmpty. Operand 71 states and 71 transitions. [2018-07-23 13:36:48,547 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-07-23 13:36:48,547 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:48,547 INFO L357 BasicCegarLoop]: trace histogram [67, 1, 1, 1] [2018-07-23 13:36:48,547 INFO L414 AbstractCegarLoop]: === Iteration 68 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:48,547 INFO L82 PathProgramCache]: Analyzing trace with hash 470553248, now seen corresponding path program 67 times [2018-07-23 13:36:48,547 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:48,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:48,897 INFO L134 CoverageAnalysis]: Checked inductivity of 2278 backedges. 0 proven. 2278 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:48,897 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:48,898 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [69] total 69 [2018-07-23 13:36:48,898 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:48,898 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:48,898 INFO L185 omatonBuilderFactory]: Interpolants [12942#true, 12943#false, 12944#(<= (+ GateController_time 1000) GateController_thousand), 12945#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 12946#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 12947#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 12948#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 12949#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 12950#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 12951#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 12952#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 12953#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 12954#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 12955#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 12956#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 12957#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 12958#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 12959#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 12960#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 12961#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 12962#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 12963#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 12964#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 12965#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 12966#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 12967#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 12968#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 12969#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 12970#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 12971#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 12972#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 12973#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 12974#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 12975#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 12976#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 12977#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 12978#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 12979#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 12980#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 12981#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 12982#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 12983#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 12984#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 12985#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 12986#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 12987#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 12988#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 12989#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 12990#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 12991#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 12992#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 12993#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 12994#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 12995#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 12996#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 12997#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 12998#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 12999#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 13000#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 13001#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 13002#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 13003#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 13004#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 13005#(or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)), 13006#(or GateController_alarm (<= (+ GateController_time 380) GateController_thousand)), 13007#(or GateController_alarm (<= (+ GateController_time 370) GateController_thousand)), 13008#(or (<= (+ GateController_time 360) GateController_thousand) GateController_alarm), 13009#(or (<= (+ GateController_time 350) GateController_thousand) GateController_alarm), 13010#(or GateController_alarm (<= (+ GateController_time 340) GateController_thousand)), 13011#(or (<= (+ GateController_time 330) GateController_thousand) GateController_alarm), 13012#GateController_alarm] [2018-07-23 13:36:48,899 INFO L134 CoverageAnalysis]: Checked inductivity of 2278 backedges. 0 proven. 2278 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:48,899 INFO L450 AbstractCegarLoop]: Interpolant automaton has 71 states [2018-07-23 13:36:48,900 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 71 interpolants. [2018-07-23 13:36:48,900 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2484, Invalid=2486, Unknown=0, NotChecked=0, Total=4970 [2018-07-23 13:36:48,901 INFO L87 Difference]: Start difference. First operand 71 states and 71 transitions. Second operand 71 states. [2018-07-23 13:36:48,976 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:48,976 INFO L93 Difference]: Finished difference Result 74 states and 74 transitions. [2018-07-23 13:36:48,977 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 71 states. [2018-07-23 13:36:48,977 INFO L78 Accepts]: Start accepts. Automaton has 71 states. Word has length 70 [2018-07-23 13:36:48,977 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:48,978 INFO L225 Difference]: With dead ends: 74 [2018-07-23 13:36:48,978 INFO L226 Difference]: Without dead ends: 72 [2018-07-23 13:36:48,979 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 69 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 69 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 133 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=2484, Invalid=2486, Unknown=0, NotChecked=0, Total=4970 [2018-07-23 13:36:48,980 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72 states. [2018-07-23 13:36:48,984 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72 to 72. [2018-07-23 13:36:48,985 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 72 states. [2018-07-23 13:36:48,985 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 72 transitions. [2018-07-23 13:36:48,985 INFO L78 Accepts]: Start accepts. Automaton has 72 states and 72 transitions. Word has length 70 [2018-07-23 13:36:48,985 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:48,985 INFO L471 AbstractCegarLoop]: Abstraction has 72 states and 72 transitions. [2018-07-23 13:36:48,985 INFO L472 AbstractCegarLoop]: Interpolant automaton has 71 states. [2018-07-23 13:36:48,986 INFO L276 IsEmpty]: Start isEmpty. Operand 72 states and 72 transitions. [2018-07-23 13:36:48,986 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2018-07-23 13:36:48,986 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:48,986 INFO L357 BasicCegarLoop]: trace histogram [68, 1, 1, 1] [2018-07-23 13:36:48,986 INFO L414 AbstractCegarLoop]: === Iteration 69 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:48,987 INFO L82 PathProgramCache]: Analyzing trace with hash 1702258400, now seen corresponding path program 68 times [2018-07-23 13:36:48,987 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:49,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:49,375 INFO L134 CoverageAnalysis]: Checked inductivity of 2346 backedges. 0 proven. 2346 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:49,375 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:49,375 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [70] total 70 [2018-07-23 13:36:49,375 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:49,375 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:49,376 INFO L185 omatonBuilderFactory]: Interpolants [13312#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 13313#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 13314#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 13315#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 13316#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 13317#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 13318#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 13319#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 13320#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 13321#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 13322#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 13323#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 13324#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 13325#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 13326#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 13327#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 13328#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 13329#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 13330#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 13331#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 13332#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 13333#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 13334#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 13335#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 13336#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 13337#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 13338#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 13339#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 13340#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 13341#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 13342#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 13343#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 13344#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 13345#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 13346#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 13347#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 13348#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 13349#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 13350#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 13351#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 13352#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 13353#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 13354#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 13355#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 13356#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 13357#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 13358#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 13359#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 13360#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 13361#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 13362#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 13363#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 13364#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 13365#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 13366#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 13367#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 13368#(or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)), 13369#(or GateController_alarm (<= (+ GateController_time 380) GateController_thousand)), 13370#(or GateController_alarm (<= (+ GateController_time 370) GateController_thousand)), 13371#(or (<= (+ GateController_time 360) GateController_thousand) GateController_alarm), 13372#(or (<= (+ GateController_time 350) GateController_thousand) GateController_alarm), 13373#(or GateController_alarm (<= (+ GateController_time 340) GateController_thousand)), 13374#(or (<= (+ GateController_time 330) GateController_thousand) GateController_alarm), 13375#(or GateController_alarm (<= (+ GateController_time 320) GateController_thousand)), 13376#GateController_alarm, 13305#true, 13306#false, 13307#(<= (+ GateController_time 1000) GateController_thousand), 13308#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 13309#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 13310#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 13311#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand))] [2018-07-23 13:36:49,376 INFO L134 CoverageAnalysis]: Checked inductivity of 2346 backedges. 0 proven. 2346 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:49,376 INFO L450 AbstractCegarLoop]: Interpolant automaton has 72 states [2018-07-23 13:36:49,377 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 72 interpolants. [2018-07-23 13:36:49,378 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2555, Invalid=2557, Unknown=0, NotChecked=0, Total=5112 [2018-07-23 13:36:49,378 INFO L87 Difference]: Start difference. First operand 72 states and 72 transitions. Second operand 72 states. [2018-07-23 13:36:49,448 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:49,448 INFO L93 Difference]: Finished difference Result 75 states and 75 transitions. [2018-07-23 13:36:49,449 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2018-07-23 13:36:49,449 INFO L78 Accepts]: Start accepts. Automaton has 72 states. Word has length 71 [2018-07-23 13:36:49,449 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:49,449 INFO L225 Difference]: With dead ends: 75 [2018-07-23 13:36:49,450 INFO L226 Difference]: Without dead ends: 73 [2018-07-23 13:36:49,450 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 70 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 70 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 135 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=2555, Invalid=2557, Unknown=0, NotChecked=0, Total=5112 [2018-07-23 13:36:49,451 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states. [2018-07-23 13:36:49,455 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 73. [2018-07-23 13:36:49,456 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 73 states. [2018-07-23 13:36:49,456 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 73 transitions. [2018-07-23 13:36:49,456 INFO L78 Accepts]: Start accepts. Automaton has 73 states and 73 transitions. Word has length 71 [2018-07-23 13:36:49,456 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:49,457 INFO L471 AbstractCegarLoop]: Abstraction has 73 states and 73 transitions. [2018-07-23 13:36:49,457 INFO L472 AbstractCegarLoop]: Interpolant automaton has 72 states. [2018-07-23 13:36:49,457 INFO L276 IsEmpty]: Start isEmpty. Operand 73 states and 73 transitions. [2018-07-23 13:36:49,457 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-07-23 13:36:49,457 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:49,458 INFO L357 BasicCegarLoop]: trace histogram [69, 1, 1, 1] [2018-07-23 13:36:49,458 INFO L414 AbstractCegarLoop]: === Iteration 70 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:49,458 INFO L82 PathProgramCache]: Analyzing trace with hash 1230412448, now seen corresponding path program 69 times [2018-07-23 13:36:49,458 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:49,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:49,921 INFO L134 CoverageAnalysis]: Checked inductivity of 2415 backedges. 0 proven. 2415 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:49,921 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:49,921 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [71] total 71 [2018-07-23 13:36:49,922 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:49,922 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:49,922 INFO L185 omatonBuilderFactory]: Interpolants [13696#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 13697#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 13698#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 13699#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 13700#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 13701#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 13702#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 13703#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 13704#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 13705#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 13706#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 13707#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 13708#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 13709#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 13710#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 13711#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 13712#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 13713#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 13714#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 13715#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 13716#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 13717#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 13718#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 13719#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 13720#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 13721#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 13722#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 13723#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 13724#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 13725#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 13726#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 13727#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 13728#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 13729#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 13730#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 13731#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 13732#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 13733#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 13734#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 13735#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 13736#(or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)), 13737#(or GateController_alarm (<= (+ GateController_time 380) GateController_thousand)), 13738#(or GateController_alarm (<= (+ GateController_time 370) GateController_thousand)), 13739#(or (<= (+ GateController_time 360) GateController_thousand) GateController_alarm), 13740#(or (<= (+ GateController_time 350) GateController_thousand) GateController_alarm), 13741#(or GateController_alarm (<= (+ GateController_time 340) GateController_thousand)), 13742#(or (<= (+ GateController_time 330) GateController_thousand) GateController_alarm), 13743#(or GateController_alarm (<= (+ GateController_time 320) GateController_thousand)), 13744#(or GateController_alarm (<= (+ GateController_time 310) GateController_thousand)), 13745#GateController_alarm, 13673#true, 13674#false, 13675#(<= (+ GateController_time 1000) GateController_thousand), 13676#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 13677#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 13678#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 13679#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 13680#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 13681#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 13682#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 13683#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 13684#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 13685#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 13686#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 13687#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 13688#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 13689#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 13690#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 13691#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 13692#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 13693#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 13694#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 13695#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand))] [2018-07-23 13:36:49,923 INFO L134 CoverageAnalysis]: Checked inductivity of 2415 backedges. 0 proven. 2415 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:49,923 INFO L450 AbstractCegarLoop]: Interpolant automaton has 73 states [2018-07-23 13:36:49,924 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 73 interpolants. [2018-07-23 13:36:49,924 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2627, Invalid=2629, Unknown=0, NotChecked=0, Total=5256 [2018-07-23 13:36:49,925 INFO L87 Difference]: Start difference. First operand 73 states and 73 transitions. Second operand 73 states. [2018-07-23 13:36:49,991 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:49,991 INFO L93 Difference]: Finished difference Result 76 states and 76 transitions. [2018-07-23 13:36:49,991 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 73 states. [2018-07-23 13:36:49,991 INFO L78 Accepts]: Start accepts. Automaton has 73 states. Word has length 72 [2018-07-23 13:36:49,991 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:49,992 INFO L225 Difference]: With dead ends: 76 [2018-07-23 13:36:49,992 INFO L226 Difference]: Without dead ends: 74 [2018-07-23 13:36:49,993 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 71 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 71 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 137 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=2627, Invalid=2629, Unknown=0, NotChecked=0, Total=5256 [2018-07-23 13:36:49,993 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states. [2018-07-23 13:36:49,999 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 74. [2018-07-23 13:36:49,999 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74 states. [2018-07-23 13:36:49,999 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 74 transitions. [2018-07-23 13:36:50,000 INFO L78 Accepts]: Start accepts. Automaton has 74 states and 74 transitions. Word has length 72 [2018-07-23 13:36:50,000 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:50,000 INFO L471 AbstractCegarLoop]: Abstraction has 74 states and 74 transitions. [2018-07-23 13:36:50,000 INFO L472 AbstractCegarLoop]: Interpolant automaton has 73 states. [2018-07-23 13:36:50,000 INFO L276 IsEmpty]: Start isEmpty. Operand 74 states and 74 transitions. [2018-07-23 13:36:50,001 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-07-23 13:36:50,001 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:50,001 INFO L357 BasicCegarLoop]: trace histogram [70, 1, 1, 1] [2018-07-23 13:36:50,001 INFO L414 AbstractCegarLoop]: === Iteration 71 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:50,001 INFO L82 PathProgramCache]: Analyzing trace with hash -511910176, now seen corresponding path program 70 times [2018-07-23 13:36:50,002 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:50,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:50,508 INFO L134 CoverageAnalysis]: Checked inductivity of 2485 backedges. 0 proven. 2485 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:50,508 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:50,509 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [72] total 72 [2018-07-23 13:36:50,509 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:50,509 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:50,510 INFO L185 omatonBuilderFactory]: Interpolants [14080#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 14081#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 14082#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 14083#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 14084#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 14085#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 14086#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 14087#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 14088#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 14089#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 14090#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 14091#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 14092#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 14093#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 14094#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 14095#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 14096#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 14097#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 14098#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 14099#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 14100#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 14101#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 14102#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 14103#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 14104#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 14105#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 14106#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 14107#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 14108#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 14109#(or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)), 14110#(or GateController_alarm (<= (+ GateController_time 380) GateController_thousand)), 14111#(or GateController_alarm (<= (+ GateController_time 370) GateController_thousand)), 14112#(or (<= (+ GateController_time 360) GateController_thousand) GateController_alarm), 14113#(or (<= (+ GateController_time 350) GateController_thousand) GateController_alarm), 14114#(or GateController_alarm (<= (+ GateController_time 340) GateController_thousand)), 14115#(or (<= (+ GateController_time 330) GateController_thousand) GateController_alarm), 14116#(or GateController_alarm (<= (+ GateController_time 320) GateController_thousand)), 14117#(or GateController_alarm (<= (+ GateController_time 310) GateController_thousand)), 14118#(or GateController_alarm (<= (+ GateController_time 300) GateController_thousand)), 14119#GateController_alarm, 14046#true, 14047#false, 14048#(<= (+ GateController_time 1000) GateController_thousand), 14049#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 14050#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 14051#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 14052#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 14053#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 14054#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 14055#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 14056#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 14057#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 14058#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 14059#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 14060#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 14061#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 14062#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 14063#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 14064#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 14065#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 14066#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 14067#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 14068#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 14069#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 14070#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 14071#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 14072#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 14073#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 14074#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 14075#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 14076#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 14077#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 14078#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 14079#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm)] [2018-07-23 13:36:50,510 INFO L134 CoverageAnalysis]: Checked inductivity of 2485 backedges. 0 proven. 2485 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:50,511 INFO L450 AbstractCegarLoop]: Interpolant automaton has 74 states [2018-07-23 13:36:50,511 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 74 interpolants. [2018-07-23 13:36:50,512 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2700, Invalid=2702, Unknown=0, NotChecked=0, Total=5402 [2018-07-23 13:36:50,512 INFO L87 Difference]: Start difference. First operand 74 states and 74 transitions. Second operand 74 states. [2018-07-23 13:36:50,569 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:50,570 INFO L93 Difference]: Finished difference Result 77 states and 77 transitions. [2018-07-23 13:36:50,570 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 74 states. [2018-07-23 13:36:50,570 INFO L78 Accepts]: Start accepts. Automaton has 74 states. Word has length 73 [2018-07-23 13:36:50,570 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:50,571 INFO L225 Difference]: With dead ends: 77 [2018-07-23 13:36:50,571 INFO L226 Difference]: Without dead ends: 75 [2018-07-23 13:36:50,571 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 72 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 139 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=2700, Invalid=2702, Unknown=0, NotChecked=0, Total=5402 [2018-07-23 13:36:50,572 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75 states. [2018-07-23 13:36:50,577 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75 to 75. [2018-07-23 13:36:50,578 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 75 states. [2018-07-23 13:36:50,578 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 75 transitions. [2018-07-23 13:36:50,578 INFO L78 Accepts]: Start accepts. Automaton has 75 states and 75 transitions. Word has length 73 [2018-07-23 13:36:50,578 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:50,579 INFO L471 AbstractCegarLoop]: Abstraction has 75 states and 75 transitions. [2018-07-23 13:36:50,579 INFO L472 AbstractCegarLoop]: Interpolant automaton has 74 states. [2018-07-23 13:36:50,579 INFO L276 IsEmpty]: Start isEmpty. Operand 75 states and 75 transitions. [2018-07-23 13:36:50,579 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-07-23 13:36:50,579 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:50,580 INFO L357 BasicCegarLoop]: trace histogram [71, 1, 1, 1] [2018-07-23 13:36:50,580 INFO L414 AbstractCegarLoop]: === Iteration 72 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:50,580 INFO L82 PathProgramCache]: Analyzing trace with hash 1310663328, now seen corresponding path program 71 times [2018-07-23 13:36:50,580 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:50,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:51,142 INFO L134 CoverageAnalysis]: Checked inductivity of 2556 backedges. 0 proven. 2556 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:51,143 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:51,143 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [73] total 73 [2018-07-23 13:36:51,145 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:51,145 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:51,146 INFO L185 omatonBuilderFactory]: Interpolants [14464#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 14465#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 14466#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 14467#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 14468#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 14469#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 14470#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 14471#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 14472#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 14473#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 14474#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 14475#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 14476#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 14477#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 14478#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 14479#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 14480#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 14481#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 14482#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 14483#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 14484#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 14485#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 14486#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 14487#(or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)), 14488#(or GateController_alarm (<= (+ GateController_time 380) GateController_thousand)), 14489#(or GateController_alarm (<= (+ GateController_time 370) GateController_thousand)), 14490#(or (<= (+ GateController_time 360) GateController_thousand) GateController_alarm), 14491#(or (<= (+ GateController_time 350) GateController_thousand) GateController_alarm), 14492#(or GateController_alarm (<= (+ GateController_time 340) GateController_thousand)), 14493#(or (<= (+ GateController_time 330) GateController_thousand) GateController_alarm), 14494#(or GateController_alarm (<= (+ GateController_time 320) GateController_thousand)), 14495#(or GateController_alarm (<= (+ GateController_time 310) GateController_thousand)), 14496#(or GateController_alarm (<= (+ GateController_time 300) GateController_thousand)), 14497#(or GateController_alarm (<= (+ GateController_time 290) GateController_thousand)), 14498#GateController_alarm, 14424#true, 14425#false, 14426#(<= (+ GateController_time 1000) GateController_thousand), 14427#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 14428#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 14429#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 14430#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 14431#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 14432#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 14433#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 14434#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 14435#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 14436#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 14437#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 14438#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 14439#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 14440#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 14441#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 14442#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 14443#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 14444#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 14445#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 14446#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 14447#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 14448#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 14449#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 14450#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 14451#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 14452#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 14453#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 14454#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 14455#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 14456#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 14457#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 14458#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 14459#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 14460#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 14461#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 14462#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 14463#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand))] [2018-07-23 13:36:51,146 INFO L134 CoverageAnalysis]: Checked inductivity of 2556 backedges. 0 proven. 2556 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:51,147 INFO L450 AbstractCegarLoop]: Interpolant automaton has 75 states [2018-07-23 13:36:51,147 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 75 interpolants. [2018-07-23 13:36:51,148 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2774, Invalid=2776, Unknown=0, NotChecked=0, Total=5550 [2018-07-23 13:36:51,148 INFO L87 Difference]: Start difference. First operand 75 states and 75 transitions. Second operand 75 states. [2018-07-23 13:36:51,197 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:51,197 INFO L93 Difference]: Finished difference Result 78 states and 78 transitions. [2018-07-23 13:36:51,197 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 75 states. [2018-07-23 13:36:51,198 INFO L78 Accepts]: Start accepts. Automaton has 75 states. Word has length 74 [2018-07-23 13:36:51,198 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:51,198 INFO L225 Difference]: With dead ends: 78 [2018-07-23 13:36:51,198 INFO L226 Difference]: Without dead ends: 76 [2018-07-23 13:36:51,199 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 73 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 73 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 141 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=2774, Invalid=2776, Unknown=0, NotChecked=0, Total=5550 [2018-07-23 13:36:51,199 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76 states. [2018-07-23 13:36:51,205 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76 to 76. [2018-07-23 13:36:51,205 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 76 states. [2018-07-23 13:36:51,205 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 76 transitions. [2018-07-23 13:36:51,205 INFO L78 Accepts]: Start accepts. Automaton has 76 states and 76 transitions. Word has length 74 [2018-07-23 13:36:51,206 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:51,206 INFO L471 AbstractCegarLoop]: Abstraction has 76 states and 76 transitions. [2018-07-23 13:36:51,206 INFO L472 AbstractCegarLoop]: Interpolant automaton has 75 states. [2018-07-23 13:36:51,206 INFO L276 IsEmpty]: Start isEmpty. Operand 76 states and 76 transitions. [2018-07-23 13:36:51,206 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2018-07-23 13:36:51,206 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:51,207 INFO L357 BasicCegarLoop]: trace histogram [72, 1, 1, 1] [2018-07-23 13:36:51,207 INFO L414 AbstractCegarLoop]: === Iteration 73 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:51,207 INFO L82 PathProgramCache]: Analyzing trace with hash 1975867104, now seen corresponding path program 72 times [2018-07-23 13:36:51,207 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:51,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:51,632 INFO L134 CoverageAnalysis]: Checked inductivity of 2628 backedges. 0 proven. 2628 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:51,633 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:51,633 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [74] total 74 [2018-07-23 13:36:51,633 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:51,633 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:51,634 INFO L185 omatonBuilderFactory]: Interpolants [14848#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 14849#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 14850#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 14851#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 14852#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 14853#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 14854#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 14855#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 14856#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 14857#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 14858#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 14859#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 14860#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 14861#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 14862#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 14863#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 14864#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 14865#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 14866#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 14867#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 14868#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 14869#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 14870#(or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)), 14871#(or GateController_alarm (<= (+ GateController_time 380) GateController_thousand)), 14872#(or GateController_alarm (<= (+ GateController_time 370) GateController_thousand)), 14873#(or (<= (+ GateController_time 360) GateController_thousand) GateController_alarm), 14874#(or (<= (+ GateController_time 350) GateController_thousand) GateController_alarm), 14875#(or GateController_alarm (<= (+ GateController_time 340) GateController_thousand)), 14876#(or (<= (+ GateController_time 330) GateController_thousand) GateController_alarm), 14877#(or GateController_alarm (<= (+ GateController_time 320) GateController_thousand)), 14878#(or GateController_alarm (<= (+ GateController_time 310) GateController_thousand)), 14879#(or GateController_alarm (<= (+ GateController_time 300) GateController_thousand)), 14880#(or GateController_alarm (<= (+ GateController_time 290) GateController_thousand)), 14881#(or GateController_alarm (<= (+ GateController_time 280) GateController_thousand)), 14882#GateController_alarm, 14807#true, 14808#false, 14809#(<= (+ GateController_time 1000) GateController_thousand), 14810#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 14811#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 14812#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 14813#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 14814#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 14815#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 14816#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 14817#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 14818#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 14819#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 14820#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 14821#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 14822#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 14823#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 14824#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 14825#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 14826#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 14827#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 14828#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 14829#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 14830#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 14831#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 14832#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 14833#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 14834#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 14835#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 14836#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 14837#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 14838#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 14839#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 14840#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 14841#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 14842#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 14843#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 14844#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 14845#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 14846#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 14847#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand))] [2018-07-23 13:36:51,634 INFO L134 CoverageAnalysis]: Checked inductivity of 2628 backedges. 0 proven. 2628 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:51,635 INFO L450 AbstractCegarLoop]: Interpolant automaton has 76 states [2018-07-23 13:36:51,635 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 76 interpolants. [2018-07-23 13:36:51,636 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2849, Invalid=2851, Unknown=0, NotChecked=0, Total=5700 [2018-07-23 13:36:51,636 INFO L87 Difference]: Start difference. First operand 76 states and 76 transitions. Second operand 76 states. [2018-07-23 13:36:51,685 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:51,686 INFO L93 Difference]: Finished difference Result 79 states and 79 transitions. [2018-07-23 13:36:51,686 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 76 states. [2018-07-23 13:36:51,686 INFO L78 Accepts]: Start accepts. Automaton has 76 states. Word has length 75 [2018-07-23 13:36:51,686 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:51,687 INFO L225 Difference]: With dead ends: 79 [2018-07-23 13:36:51,687 INFO L226 Difference]: Without dead ends: 77 [2018-07-23 13:36:51,687 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 74 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 74 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 143 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=2849, Invalid=2851, Unknown=0, NotChecked=0, Total=5700 [2018-07-23 13:36:51,688 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77 states. [2018-07-23 13:36:51,693 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77 to 77. [2018-07-23 13:36:51,693 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 77 states. [2018-07-23 13:36:51,693 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 77 transitions. [2018-07-23 13:36:51,693 INFO L78 Accepts]: Start accepts. Automaton has 77 states and 77 transitions. Word has length 75 [2018-07-23 13:36:51,694 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:51,694 INFO L471 AbstractCegarLoop]: Abstraction has 77 states and 77 transitions. [2018-07-23 13:36:51,694 INFO L472 AbstractCegarLoop]: Interpolant automaton has 76 states. [2018-07-23 13:36:51,694 INFO L276 IsEmpty]: Start isEmpty. Operand 77 states and 77 transitions. [2018-07-23 13:36:51,694 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2018-07-23 13:36:51,694 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:51,695 INFO L357 BasicCegarLoop]: trace histogram [73, 1, 1, 1] [2018-07-23 13:36:51,695 INFO L414 AbstractCegarLoop]: === Iteration 74 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:51,695 INFO L82 PathProgramCache]: Analyzing trace with hash 1122347680, now seen corresponding path program 73 times [2018-07-23 13:36:51,695 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:51,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:52,189 INFO L134 CoverageAnalysis]: Checked inductivity of 2701 backedges. 0 proven. 2701 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:52,189 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:52,189 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [75] total 75 [2018-07-23 13:36:52,190 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:52,190 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:52,191 INFO L185 omatonBuilderFactory]: Interpolants [15232#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 15233#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 15234#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 15235#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 15236#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 15237#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 15238#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 15239#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 15240#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 15241#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 15242#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 15243#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 15244#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 15245#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 15246#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 15247#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 15248#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 15249#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 15250#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 15251#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 15252#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 15253#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 15254#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 15255#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 15256#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 15257#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 15258#(or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)), 15259#(or GateController_alarm (<= (+ GateController_time 380) GateController_thousand)), 15260#(or GateController_alarm (<= (+ GateController_time 370) GateController_thousand)), 15261#(or (<= (+ GateController_time 360) GateController_thousand) GateController_alarm), 15262#(or (<= (+ GateController_time 350) GateController_thousand) GateController_alarm), 15263#(or GateController_alarm (<= (+ GateController_time 340) GateController_thousand)), 15264#(or (<= (+ GateController_time 330) GateController_thousand) GateController_alarm), 15265#(or GateController_alarm (<= (+ GateController_time 320) GateController_thousand)), 15266#(or GateController_alarm (<= (+ GateController_time 310) GateController_thousand)), 15267#(or GateController_alarm (<= (+ GateController_time 300) GateController_thousand)), 15268#(or GateController_alarm (<= (+ GateController_time 290) GateController_thousand)), 15269#(or GateController_alarm (<= (+ GateController_time 280) GateController_thousand)), 15270#(or (<= (+ GateController_time 270) GateController_thousand) GateController_alarm), 15271#GateController_alarm, 15195#true, 15196#false, 15197#(<= (+ GateController_time 1000) GateController_thousand), 15198#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 15199#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 15200#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 15201#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 15202#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 15203#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 15204#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 15205#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 15206#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 15207#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 15208#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 15209#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 15210#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 15211#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 15212#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 15213#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 15214#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 15215#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 15216#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 15217#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 15218#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 15219#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 15220#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 15221#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 15222#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 15223#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 15224#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 15225#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 15226#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 15227#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 15228#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 15229#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 15230#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 15231#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand))] [2018-07-23 13:36:52,191 INFO L134 CoverageAnalysis]: Checked inductivity of 2701 backedges. 0 proven. 2701 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:52,192 INFO L450 AbstractCegarLoop]: Interpolant automaton has 77 states [2018-07-23 13:36:52,192 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 77 interpolants. [2018-07-23 13:36:52,193 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2925, Invalid=2927, Unknown=0, NotChecked=0, Total=5852 [2018-07-23 13:36:52,193 INFO L87 Difference]: Start difference. First operand 77 states and 77 transitions. Second operand 77 states. [2018-07-23 13:36:52,251 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:52,252 INFO L93 Difference]: Finished difference Result 80 states and 80 transitions. [2018-07-23 13:36:52,252 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 77 states. [2018-07-23 13:36:52,252 INFO L78 Accepts]: Start accepts. Automaton has 77 states. Word has length 76 [2018-07-23 13:36:52,252 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:52,253 INFO L225 Difference]: With dead ends: 80 [2018-07-23 13:36:52,253 INFO L226 Difference]: Without dead ends: 78 [2018-07-23 13:36:52,253 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 75 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 75 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 145 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=2925, Invalid=2927, Unknown=0, NotChecked=0, Total=5852 [2018-07-23 13:36:52,254 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78 states. [2018-07-23 13:36:52,259 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78 to 78. [2018-07-23 13:36:52,259 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 78 states. [2018-07-23 13:36:52,259 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 78 transitions. [2018-07-23 13:36:52,259 INFO L78 Accepts]: Start accepts. Automaton has 78 states and 78 transitions. Word has length 76 [2018-07-23 13:36:52,260 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:52,260 INFO L471 AbstractCegarLoop]: Abstraction has 78 states and 78 transitions. [2018-07-23 13:36:52,260 INFO L472 AbstractCegarLoop]: Interpolant automaton has 77 states. [2018-07-23 13:36:52,260 INFO L276 IsEmpty]: Start isEmpty. Operand 78 states and 78 transitions. [2018-07-23 13:36:52,260 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-07-23 13:36:52,261 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:52,261 INFO L357 BasicCegarLoop]: trace histogram [74, 1, 1, 1] [2018-07-23 13:36:52,261 INFO L414 AbstractCegarLoop]: === Iteration 75 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:52,261 INFO L82 PathProgramCache]: Analyzing trace with hash 433049312, now seen corresponding path program 74 times [2018-07-23 13:36:52,261 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:52,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:52,714 INFO L134 CoverageAnalysis]: Checked inductivity of 2775 backedges. 0 proven. 2775 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:52,715 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:52,715 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [76] total 76 [2018-07-23 13:36:52,715 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:52,715 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:52,716 INFO L185 omatonBuilderFactory]: Interpolants [15616#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 15617#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 15618#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 15619#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 15620#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 15621#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 15622#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 15623#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 15624#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 15625#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 15626#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 15627#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 15628#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 15629#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 15630#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 15631#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 15632#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 15633#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 15634#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 15635#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 15636#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 15637#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 15638#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 15639#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 15640#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 15641#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 15642#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 15643#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 15644#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 15645#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 15646#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 15647#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 15648#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 15649#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 15650#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 15651#(or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)), 15652#(or GateController_alarm (<= (+ GateController_time 380) GateController_thousand)), 15653#(or GateController_alarm (<= (+ GateController_time 370) GateController_thousand)), 15654#(or (<= (+ GateController_time 360) GateController_thousand) GateController_alarm), 15655#(or (<= (+ GateController_time 350) GateController_thousand) GateController_alarm), 15656#(or GateController_alarm (<= (+ GateController_time 340) GateController_thousand)), 15657#(or (<= (+ GateController_time 330) GateController_thousand) GateController_alarm), 15658#(or GateController_alarm (<= (+ GateController_time 320) GateController_thousand)), 15659#(or GateController_alarm (<= (+ GateController_time 310) GateController_thousand)), 15660#(or GateController_alarm (<= (+ GateController_time 300) GateController_thousand)), 15661#(or GateController_alarm (<= (+ GateController_time 290) GateController_thousand)), 15662#(or GateController_alarm (<= (+ GateController_time 280) GateController_thousand)), 15663#(or (<= (+ GateController_time 270) GateController_thousand) GateController_alarm), 15664#(or GateController_alarm (<= (+ GateController_time 260) GateController_thousand)), 15665#GateController_alarm, 15588#true, 15589#false, 15590#(<= (+ GateController_time 1000) GateController_thousand), 15591#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 15592#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 15593#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 15594#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 15595#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 15596#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 15597#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 15598#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 15599#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 15600#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 15601#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 15602#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 15603#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 15604#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 15605#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 15606#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 15607#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 15608#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 15609#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 15610#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 15611#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 15612#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 15613#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 15614#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 15615#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand))] [2018-07-23 13:36:52,716 INFO L134 CoverageAnalysis]: Checked inductivity of 2775 backedges. 0 proven. 2775 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:52,716 INFO L450 AbstractCegarLoop]: Interpolant automaton has 78 states [2018-07-23 13:36:52,717 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 78 interpolants. [2018-07-23 13:36:52,718 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3002, Invalid=3004, Unknown=0, NotChecked=0, Total=6006 [2018-07-23 13:36:52,718 INFO L87 Difference]: Start difference. First operand 78 states and 78 transitions. Second operand 78 states. [2018-07-23 13:36:52,792 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:52,793 INFO L93 Difference]: Finished difference Result 81 states and 81 transitions. [2018-07-23 13:36:52,793 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 78 states. [2018-07-23 13:36:52,793 INFO L78 Accepts]: Start accepts. Automaton has 78 states. Word has length 77 [2018-07-23 13:36:52,793 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:52,794 INFO L225 Difference]: With dead ends: 81 [2018-07-23 13:36:52,794 INFO L226 Difference]: Without dead ends: 79 [2018-07-23 13:36:52,795 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 76 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 76 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 147 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=3002, Invalid=3004, Unknown=0, NotChecked=0, Total=6006 [2018-07-23 13:36:52,795 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79 states. [2018-07-23 13:36:52,800 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79 to 79. [2018-07-23 13:36:52,801 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 79 states. [2018-07-23 13:36:52,801 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79 states to 79 states and 79 transitions. [2018-07-23 13:36:52,801 INFO L78 Accepts]: Start accepts. Automaton has 79 states and 79 transitions. Word has length 77 [2018-07-23 13:36:52,801 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:52,802 INFO L471 AbstractCegarLoop]: Abstraction has 79 states and 79 transitions. [2018-07-23 13:36:52,802 INFO L472 AbstractCegarLoop]: Interpolant automaton has 78 states. [2018-07-23 13:36:52,802 INFO L276 IsEmpty]: Start isEmpty. Operand 79 states and 79 transitions. [2018-07-23 13:36:52,802 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2018-07-23 13:36:52,803 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:52,803 INFO L357 BasicCegarLoop]: trace histogram [75, 1, 1, 1] [2018-07-23 13:36:52,803 INFO L414 AbstractCegarLoop]: === Iteration 76 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:52,803 INFO L82 PathProgramCache]: Analyzing trace with hash 539636384, now seen corresponding path program 75 times [2018-07-23 13:36:52,803 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:52,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:53,306 INFO L134 CoverageAnalysis]: Checked inductivity of 2850 backedges. 0 proven. 2850 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:53,306 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:53,307 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [77] total 77 [2018-07-23 13:36:53,307 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:53,307 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:53,307 INFO L185 omatonBuilderFactory]: Interpolants [16000#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 16001#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 16002#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 16003#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 16004#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 16005#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 16006#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 16007#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 16008#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 16009#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 16010#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 16011#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 16012#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 16013#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 16014#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 16015#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 16016#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 16017#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 16018#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 16019#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 16020#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 16021#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 16022#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 16023#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 16024#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 16025#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 16026#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 16027#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 16028#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 16029#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 16030#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 16031#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 16032#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 16033#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 16034#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 16035#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 16036#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 16037#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 16038#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 16039#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 16040#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 16041#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 16042#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 16043#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 16044#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 16045#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 16046#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 16047#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 16048#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 16049#(or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)), 16050#(or GateController_alarm (<= (+ GateController_time 380) GateController_thousand)), 16051#(or GateController_alarm (<= (+ GateController_time 370) GateController_thousand)), 16052#(or (<= (+ GateController_time 360) GateController_thousand) GateController_alarm), 16053#(or (<= (+ GateController_time 350) GateController_thousand) GateController_alarm), 16054#(or GateController_alarm (<= (+ GateController_time 340) GateController_thousand)), 16055#(or (<= (+ GateController_time 330) GateController_thousand) GateController_alarm), 16056#(or GateController_alarm (<= (+ GateController_time 320) GateController_thousand)), 16057#(or GateController_alarm (<= (+ GateController_time 310) GateController_thousand)), 16058#(or GateController_alarm (<= (+ GateController_time 300) GateController_thousand)), 16059#(or GateController_alarm (<= (+ GateController_time 290) GateController_thousand)), 16060#(or GateController_alarm (<= (+ GateController_time 280) GateController_thousand)), 16061#(or (<= (+ GateController_time 270) GateController_thousand) GateController_alarm), 16062#(or GateController_alarm (<= (+ GateController_time 260) GateController_thousand)), 16063#(or GateController_alarm (<= (+ GateController_time 250) GateController_thousand)), 16064#GateController_alarm, 15986#true, 15987#false, 15988#(<= (+ GateController_time 1000) GateController_thousand), 15989#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 15990#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 15991#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 15992#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 15993#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 15994#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 15995#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 15996#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 15997#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 15998#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 15999#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand))] [2018-07-23 13:36:53,308 INFO L134 CoverageAnalysis]: Checked inductivity of 2850 backedges. 0 proven. 2850 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:53,308 INFO L450 AbstractCegarLoop]: Interpolant automaton has 79 states [2018-07-23 13:36:53,308 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 79 interpolants. [2018-07-23 13:36:53,308 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3080, Invalid=3082, Unknown=0, NotChecked=0, Total=6162 [2018-07-23 13:36:53,309 INFO L87 Difference]: Start difference. First operand 79 states and 79 transitions. Second operand 79 states. [2018-07-23 13:36:53,384 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:53,384 INFO L93 Difference]: Finished difference Result 82 states and 82 transitions. [2018-07-23 13:36:53,384 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 79 states. [2018-07-23 13:36:53,385 INFO L78 Accepts]: Start accepts. Automaton has 79 states. Word has length 78 [2018-07-23 13:36:53,385 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:53,385 INFO L225 Difference]: With dead ends: 82 [2018-07-23 13:36:53,385 INFO L226 Difference]: Without dead ends: 80 [2018-07-23 13:36:53,386 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 77 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 77 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 149 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=3080, Invalid=3082, Unknown=0, NotChecked=0, Total=6162 [2018-07-23 13:36:53,386 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states. [2018-07-23 13:36:53,391 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 80. [2018-07-23 13:36:53,392 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 80 states. [2018-07-23 13:36:53,392 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 80 transitions. [2018-07-23 13:36:53,392 INFO L78 Accepts]: Start accepts. Automaton has 80 states and 80 transitions. Word has length 78 [2018-07-23 13:36:53,392 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:53,392 INFO L471 AbstractCegarLoop]: Abstraction has 80 states and 80 transitions. [2018-07-23 13:36:53,393 INFO L472 AbstractCegarLoop]: Interpolant automaton has 79 states. [2018-07-23 13:36:53,393 INFO L276 IsEmpty]: Start isEmpty. Operand 80 states and 80 transitions. [2018-07-23 13:36:53,393 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2018-07-23 13:36:53,393 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:53,393 INFO L357 BasicCegarLoop]: trace histogram [76, 1, 1, 1] [2018-07-23 13:36:53,394 INFO L414 AbstractCegarLoop]: === Iteration 77 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:53,394 INFO L82 PathProgramCache]: Analyzing trace with hash -451131680, now seen corresponding path program 76 times [2018-07-23 13:36:53,394 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:53,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:53,828 INFO L134 CoverageAnalysis]: Checked inductivity of 2926 backedges. 0 proven. 2926 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:53,828 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:53,828 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [78] total 78 [2018-07-23 13:36:53,828 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:53,829 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:53,829 INFO L185 omatonBuilderFactory]: Interpolants [16389#true, 16390#false, 16391#(<= (+ GateController_time 1000) GateController_thousand), 16392#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 16393#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 16394#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 16395#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 16396#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 16397#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 16398#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 16399#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 16400#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 16401#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 16402#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 16403#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 16404#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 16405#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 16406#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 16407#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 16408#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 16409#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 16410#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 16411#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 16412#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 16413#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 16414#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 16415#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 16416#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 16417#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 16418#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 16419#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 16420#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 16421#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 16422#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 16423#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 16424#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 16425#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 16426#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 16427#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 16428#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 16429#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 16430#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 16431#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 16432#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 16433#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 16434#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 16435#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 16436#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 16437#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 16438#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 16439#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 16440#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 16441#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 16442#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 16443#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 16444#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 16445#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 16446#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 16447#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 16448#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 16449#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 16450#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 16451#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 16452#(or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)), 16453#(or GateController_alarm (<= (+ GateController_time 380) GateController_thousand)), 16454#(or GateController_alarm (<= (+ GateController_time 370) GateController_thousand)), 16455#(or (<= (+ GateController_time 360) GateController_thousand) GateController_alarm), 16456#(or (<= (+ GateController_time 350) GateController_thousand) GateController_alarm), 16457#(or GateController_alarm (<= (+ GateController_time 340) GateController_thousand)), 16458#(or (<= (+ GateController_time 330) GateController_thousand) GateController_alarm), 16459#(or GateController_alarm (<= (+ GateController_time 320) GateController_thousand)), 16460#(or GateController_alarm (<= (+ GateController_time 310) GateController_thousand)), 16461#(or GateController_alarm (<= (+ GateController_time 300) GateController_thousand)), 16462#(or GateController_alarm (<= (+ GateController_time 290) GateController_thousand)), 16463#(or GateController_alarm (<= (+ GateController_time 280) GateController_thousand)), 16464#(or (<= (+ GateController_time 270) GateController_thousand) GateController_alarm), 16465#(or GateController_alarm (<= (+ GateController_time 260) GateController_thousand)), 16466#(or GateController_alarm (<= (+ GateController_time 250) GateController_thousand)), 16467#(or GateController_alarm (<= (+ GateController_time 240) GateController_thousand)), 16468#GateController_alarm] [2018-07-23 13:36:53,830 INFO L134 CoverageAnalysis]: Checked inductivity of 2926 backedges. 0 proven. 2926 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:53,830 INFO L450 AbstractCegarLoop]: Interpolant automaton has 80 states [2018-07-23 13:36:53,831 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 80 interpolants. [2018-07-23 13:36:53,831 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3159, Invalid=3161, Unknown=0, NotChecked=0, Total=6320 [2018-07-23 13:36:53,831 INFO L87 Difference]: Start difference. First operand 80 states and 80 transitions. Second operand 80 states. [2018-07-23 13:36:53,931 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:53,931 INFO L93 Difference]: Finished difference Result 83 states and 83 transitions. [2018-07-23 13:36:53,931 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 80 states. [2018-07-23 13:36:53,931 INFO L78 Accepts]: Start accepts. Automaton has 80 states. Word has length 79 [2018-07-23 13:36:53,932 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:53,932 INFO L225 Difference]: With dead ends: 83 [2018-07-23 13:36:53,932 INFO L226 Difference]: Without dead ends: 81 [2018-07-23 13:36:53,933 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 78 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 78 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 151 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=3159, Invalid=3161, Unknown=0, NotChecked=0, Total=6320 [2018-07-23 13:36:53,933 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81 states. [2018-07-23 13:36:53,940 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81 to 81. [2018-07-23 13:36:53,940 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 81 states. [2018-07-23 13:36:53,940 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 81 transitions. [2018-07-23 13:36:53,941 INFO L78 Accepts]: Start accepts. Automaton has 81 states and 81 transitions. Word has length 79 [2018-07-23 13:36:53,941 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:53,941 INFO L471 AbstractCegarLoop]: Abstraction has 81 states and 81 transitions. [2018-07-23 13:36:53,941 INFO L472 AbstractCegarLoop]: Interpolant automaton has 80 states. [2018-07-23 13:36:53,941 INFO L276 IsEmpty]: Start isEmpty. Operand 81 states and 81 transitions. [2018-07-23 13:36:53,942 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2018-07-23 13:36:53,942 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:53,942 INFO L357 BasicCegarLoop]: trace histogram [77, 1, 1, 1] [2018-07-23 13:36:53,942 INFO L414 AbstractCegarLoop]: === Iteration 78 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:53,943 INFO L82 PathProgramCache]: Analyzing trace with hash -1100170592, now seen corresponding path program 77 times [2018-07-23 13:36:53,943 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:53,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:54,553 INFO L134 CoverageAnalysis]: Checked inductivity of 3003 backedges. 0 proven. 3003 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:54,553 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:54,553 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [79] total 79 [2018-07-23 13:36:54,554 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:54,554 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:54,554 INFO L185 omatonBuilderFactory]: Interpolants [16797#true, 16798#false, 16799#(<= (+ GateController_time 1000) GateController_thousand), 16800#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 16801#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 16802#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 16803#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 16804#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 16805#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 16806#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 16807#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 16808#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 16809#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 16810#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 16811#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 16812#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 16813#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 16814#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 16815#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 16816#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 16817#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 16818#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 16819#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 16820#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 16821#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 16822#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 16823#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 16824#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 16825#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 16826#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 16827#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 16828#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 16829#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 16830#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 16831#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 16832#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 16833#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 16834#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 16835#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 16836#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 16837#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 16838#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 16839#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 16840#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 16841#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 16842#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 16843#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 16844#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 16845#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 16846#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 16847#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 16848#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 16849#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 16850#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 16851#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 16852#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 16853#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 16854#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 16855#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 16856#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 16857#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 16858#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 16859#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 16860#(or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)), 16861#(or GateController_alarm (<= (+ GateController_time 380) GateController_thousand)), 16862#(or GateController_alarm (<= (+ GateController_time 370) GateController_thousand)), 16863#(or (<= (+ GateController_time 360) GateController_thousand) GateController_alarm), 16864#(or (<= (+ GateController_time 350) GateController_thousand) GateController_alarm), 16865#(or GateController_alarm (<= (+ GateController_time 340) GateController_thousand)), 16866#(or (<= (+ GateController_time 330) GateController_thousand) GateController_alarm), 16867#(or GateController_alarm (<= (+ GateController_time 320) GateController_thousand)), 16868#(or GateController_alarm (<= (+ GateController_time 310) GateController_thousand)), 16869#(or GateController_alarm (<= (+ GateController_time 300) GateController_thousand)), 16870#(or GateController_alarm (<= (+ GateController_time 290) GateController_thousand)), 16871#(or GateController_alarm (<= (+ GateController_time 280) GateController_thousand)), 16872#(or (<= (+ GateController_time 270) GateController_thousand) GateController_alarm), 16873#(or GateController_alarm (<= (+ GateController_time 260) GateController_thousand)), 16874#(or GateController_alarm (<= (+ GateController_time 250) GateController_thousand)), 16875#(or GateController_alarm (<= (+ GateController_time 240) GateController_thousand)), 16876#(or GateController_alarm (<= (+ GateController_time 230) GateController_thousand)), 16877#GateController_alarm] [2018-07-23 13:36:54,554 INFO L134 CoverageAnalysis]: Checked inductivity of 3003 backedges. 0 proven. 3003 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:54,555 INFO L450 AbstractCegarLoop]: Interpolant automaton has 81 states [2018-07-23 13:36:54,555 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 81 interpolants. [2018-07-23 13:36:54,555 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3239, Invalid=3241, Unknown=0, NotChecked=0, Total=6480 [2018-07-23 13:36:54,556 INFO L87 Difference]: Start difference. First operand 81 states and 81 transitions. Second operand 81 states. [2018-07-23 13:36:54,639 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:54,639 INFO L93 Difference]: Finished difference Result 84 states and 84 transitions. [2018-07-23 13:36:54,639 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 81 states. [2018-07-23 13:36:54,639 INFO L78 Accepts]: Start accepts. Automaton has 81 states. Word has length 80 [2018-07-23 13:36:54,640 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:54,640 INFO L225 Difference]: With dead ends: 84 [2018-07-23 13:36:54,640 INFO L226 Difference]: Without dead ends: 82 [2018-07-23 13:36:54,641 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 79 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 79 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 153 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=3239, Invalid=3241, Unknown=0, NotChecked=0, Total=6480 [2018-07-23 13:36:54,641 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states. [2018-07-23 13:36:54,650 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 82. [2018-07-23 13:36:54,650 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 82 states. [2018-07-23 13:36:54,650 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 82 transitions. [2018-07-23 13:36:54,651 INFO L78 Accepts]: Start accepts. Automaton has 82 states and 82 transitions. Word has length 80 [2018-07-23 13:36:54,652 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:54,652 INFO L471 AbstractCegarLoop]: Abstraction has 82 states and 82 transitions. [2018-07-23 13:36:54,652 INFO L472 AbstractCegarLoop]: Interpolant automaton has 81 states. [2018-07-23 13:36:54,652 INFO L276 IsEmpty]: Start isEmpty. Operand 82 states and 82 transitions. [2018-07-23 13:36:54,652 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2018-07-23 13:36:54,652 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:54,653 INFO L357 BasicCegarLoop]: trace histogram [78, 1, 1, 1] [2018-07-23 13:36:54,653 INFO L414 AbstractCegarLoop]: === Iteration 79 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:54,653 INFO L82 PathProgramCache]: Analyzing trace with hash 254459616, now seen corresponding path program 78 times [2018-07-23 13:36:54,653 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:54,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:55,106 INFO L134 CoverageAnalysis]: Checked inductivity of 3081 backedges. 0 proven. 3081 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:55,107 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:55,107 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [80] total 80 [2018-07-23 13:36:55,107 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:55,107 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:55,107 INFO L185 omatonBuilderFactory]: Interpolants [17280#(or GateController_alarm (<= (+ GateController_time 320) GateController_thousand)), 17281#(or GateController_alarm (<= (+ GateController_time 310) GateController_thousand)), 17282#(or GateController_alarm (<= (+ GateController_time 300) GateController_thousand)), 17283#(or GateController_alarm (<= (+ GateController_time 290) GateController_thousand)), 17284#(or GateController_alarm (<= (+ GateController_time 280) GateController_thousand)), 17285#(or (<= (+ GateController_time 270) GateController_thousand) GateController_alarm), 17286#(or GateController_alarm (<= (+ GateController_time 260) GateController_thousand)), 17287#(or GateController_alarm (<= (+ GateController_time 250) GateController_thousand)), 17288#(or GateController_alarm (<= (+ GateController_time 240) GateController_thousand)), 17289#(or GateController_alarm (<= (+ GateController_time 230) GateController_thousand)), 17290#(or GateController_alarm (<= (+ GateController_time 220) GateController_thousand)), 17291#GateController_alarm, 17210#true, 17211#false, 17212#(<= (+ GateController_time 1000) GateController_thousand), 17213#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 17214#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 17215#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 17216#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 17217#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 17218#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 17219#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 17220#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 17221#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 17222#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 17223#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 17224#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 17225#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 17226#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 17227#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 17228#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 17229#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 17230#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 17231#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 17232#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 17233#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 17234#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 17235#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 17236#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 17237#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 17238#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 17239#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 17240#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 17241#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 17242#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 17243#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 17244#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 17245#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 17246#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 17247#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 17248#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 17249#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 17250#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 17251#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 17252#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 17253#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 17254#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 17255#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 17256#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 17257#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 17258#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 17259#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 17260#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 17261#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 17262#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 17263#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 17264#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 17265#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 17266#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 17267#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 17268#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 17269#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 17270#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 17271#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 17272#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 17273#(or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)), 17274#(or GateController_alarm (<= (+ GateController_time 380) GateController_thousand)), 17275#(or GateController_alarm (<= (+ GateController_time 370) GateController_thousand)), 17276#(or (<= (+ GateController_time 360) GateController_thousand) GateController_alarm), 17277#(or (<= (+ GateController_time 350) GateController_thousand) GateController_alarm), 17278#(or GateController_alarm (<= (+ GateController_time 340) GateController_thousand)), 17279#(or (<= (+ GateController_time 330) GateController_thousand) GateController_alarm)] [2018-07-23 13:36:55,108 INFO L134 CoverageAnalysis]: Checked inductivity of 3081 backedges. 0 proven. 3081 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:55,108 INFO L450 AbstractCegarLoop]: Interpolant automaton has 82 states [2018-07-23 13:36:55,108 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 82 interpolants. [2018-07-23 13:36:55,109 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3320, Invalid=3322, Unknown=0, NotChecked=0, Total=6642 [2018-07-23 13:36:55,109 INFO L87 Difference]: Start difference. First operand 82 states and 82 transitions. Second operand 82 states. [2018-07-23 13:36:55,179 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:55,179 INFO L93 Difference]: Finished difference Result 85 states and 85 transitions. [2018-07-23 13:36:55,179 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 82 states. [2018-07-23 13:36:55,179 INFO L78 Accepts]: Start accepts. Automaton has 82 states. Word has length 81 [2018-07-23 13:36:55,179 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:55,180 INFO L225 Difference]: With dead ends: 85 [2018-07-23 13:36:55,180 INFO L226 Difference]: Without dead ends: 83 [2018-07-23 13:36:55,181 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 80 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 80 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 155 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=3320, Invalid=3322, Unknown=0, NotChecked=0, Total=6642 [2018-07-23 13:36:55,181 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states. [2018-07-23 13:36:55,189 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 83. [2018-07-23 13:36:55,190 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 83 states. [2018-07-23 13:36:55,190 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 83 transitions. [2018-07-23 13:36:55,190 INFO L78 Accepts]: Start accepts. Automaton has 83 states and 83 transitions. Word has length 81 [2018-07-23 13:36:55,191 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:55,191 INFO L471 AbstractCegarLoop]: Abstraction has 83 states and 83 transitions. [2018-07-23 13:36:55,191 INFO L472 AbstractCegarLoop]: Interpolant automaton has 82 states. [2018-07-23 13:36:55,191 INFO L276 IsEmpty]: Start isEmpty. Operand 83 states and 83 transitions. [2018-07-23 13:36:55,191 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2018-07-23 13:36:55,191 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:55,192 INFO L357 BasicCegarLoop]: trace histogram [79, 1, 1, 1] [2018-07-23 13:36:55,192 INFO L414 AbstractCegarLoop]: === Iteration 80 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:55,192 INFO L82 PathProgramCache]: Analyzing trace with hash -701676896, now seen corresponding path program 79 times [2018-07-23 13:36:55,192 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:55,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:55,724 INFO L134 CoverageAnalysis]: Checked inductivity of 3160 backedges. 0 proven. 3160 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:55,724 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:55,724 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [81] total 81 [2018-07-23 13:36:55,725 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:55,725 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:55,725 INFO L185 omatonBuilderFactory]: Interpolants [17664#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 17665#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 17666#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 17667#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 17668#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 17669#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 17670#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 17671#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 17672#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 17673#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 17674#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 17675#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 17676#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 17677#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 17678#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 17679#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 17680#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 17681#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 17682#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 17683#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 17684#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 17685#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 17686#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 17687#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 17688#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 17689#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 17690#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 17691#(or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)), 17692#(or GateController_alarm (<= (+ GateController_time 380) GateController_thousand)), 17693#(or GateController_alarm (<= (+ GateController_time 370) GateController_thousand)), 17694#(or (<= (+ GateController_time 360) GateController_thousand) GateController_alarm), 17695#(or (<= (+ GateController_time 350) GateController_thousand) GateController_alarm), 17696#(or GateController_alarm (<= (+ GateController_time 340) GateController_thousand)), 17697#(or (<= (+ GateController_time 330) GateController_thousand) GateController_alarm), 17698#(or GateController_alarm (<= (+ GateController_time 320) GateController_thousand)), 17699#(or GateController_alarm (<= (+ GateController_time 310) GateController_thousand)), 17700#(or GateController_alarm (<= (+ GateController_time 300) GateController_thousand)), 17701#(or GateController_alarm (<= (+ GateController_time 290) GateController_thousand)), 17702#(or GateController_alarm (<= (+ GateController_time 280) GateController_thousand)), 17703#(or (<= (+ GateController_time 270) GateController_thousand) GateController_alarm), 17704#(or GateController_alarm (<= (+ GateController_time 260) GateController_thousand)), 17705#(or GateController_alarm (<= (+ GateController_time 250) GateController_thousand)), 17706#(or GateController_alarm (<= (+ GateController_time 240) GateController_thousand)), 17707#(or GateController_alarm (<= (+ GateController_time 230) GateController_thousand)), 17708#(or GateController_alarm (<= (+ GateController_time 220) GateController_thousand)), 17709#(or GateController_alarm (<= (+ GateController_time 210) GateController_thousand)), 17710#GateController_alarm, 17628#true, 17629#false, 17630#(<= (+ GateController_time 1000) GateController_thousand), 17631#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 17632#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 17633#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 17634#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 17635#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 17636#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 17637#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 17638#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 17639#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 17640#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 17641#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 17642#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 17643#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 17644#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 17645#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 17646#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 17647#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 17648#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 17649#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 17650#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 17651#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 17652#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 17653#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 17654#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 17655#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 17656#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 17657#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 17658#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 17659#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 17660#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 17661#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 17662#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 17663#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand))] [2018-07-23 13:36:55,726 INFO L134 CoverageAnalysis]: Checked inductivity of 3160 backedges. 0 proven. 3160 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:55,726 INFO L450 AbstractCegarLoop]: Interpolant automaton has 83 states [2018-07-23 13:36:55,727 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 83 interpolants. [2018-07-23 13:36:55,727 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3402, Invalid=3404, Unknown=0, NotChecked=0, Total=6806 [2018-07-23 13:36:55,727 INFO L87 Difference]: Start difference. First operand 83 states and 83 transitions. Second operand 83 states. [2018-07-23 13:36:55,789 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:55,790 INFO L93 Difference]: Finished difference Result 86 states and 86 transitions. [2018-07-23 13:36:55,790 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 83 states. [2018-07-23 13:36:55,790 INFO L78 Accepts]: Start accepts. Automaton has 83 states. Word has length 82 [2018-07-23 13:36:55,790 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:55,791 INFO L225 Difference]: With dead ends: 86 [2018-07-23 13:36:55,791 INFO L226 Difference]: Without dead ends: 84 [2018-07-23 13:36:55,792 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 81 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 81 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 157 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=3402, Invalid=3404, Unknown=0, NotChecked=0, Total=6806 [2018-07-23 13:36:55,792 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84 states. [2018-07-23 13:36:55,797 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84 to 84. [2018-07-23 13:36:55,797 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 84 states. [2018-07-23 13:36:55,798 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 84 transitions. [2018-07-23 13:36:55,798 INFO L78 Accepts]: Start accepts. Automaton has 84 states and 84 transitions. Word has length 82 [2018-07-23 13:36:55,798 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:55,798 INFO L471 AbstractCegarLoop]: Abstraction has 84 states and 84 transitions. [2018-07-23 13:36:55,798 INFO L472 AbstractCegarLoop]: Interpolant automaton has 83 states. [2018-07-23 13:36:55,798 INFO L276 IsEmpty]: Start isEmpty. Operand 84 states and 84 transitions. [2018-07-23 13:36:55,799 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-07-23 13:36:55,799 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:55,799 INFO L357 BasicCegarLoop]: trace histogram [80, 1, 1, 1] [2018-07-23 13:36:55,799 INFO L414 AbstractCegarLoop]: === Iteration 81 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:55,800 INFO L82 PathProgramCache]: Analyzing trace with hash -277137696, now seen corresponding path program 80 times [2018-07-23 13:36:55,800 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:55,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:56,233 INFO L134 CoverageAnalysis]: Checked inductivity of 3240 backedges. 0 proven. 3240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:56,234 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:56,234 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [82] total 82 [2018-07-23 13:36:56,234 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:56,234 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:56,235 INFO L185 omatonBuilderFactory]: Interpolants [18051#true, 18052#false, 18053#(<= (+ GateController_time 1000) GateController_thousand), 18054#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 18055#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 18056#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 18057#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 18058#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 18059#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 18060#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 18061#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 18062#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 18063#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 18064#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 18065#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 18066#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 18067#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 18068#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 18069#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 18070#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 18071#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 18072#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 18073#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 18074#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 18075#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 18076#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 18077#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 18078#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 18079#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 18080#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 18081#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 18082#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 18083#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 18084#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 18085#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 18086#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 18087#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 18088#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 18089#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 18090#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 18091#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 18092#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 18093#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 18094#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 18095#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 18096#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 18097#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 18098#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 18099#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 18100#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 18101#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 18102#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 18103#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 18104#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 18105#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 18106#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 18107#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 18108#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 18109#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 18110#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 18111#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 18112#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 18113#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 18114#(or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)), 18115#(or GateController_alarm (<= (+ GateController_time 380) GateController_thousand)), 18116#(or GateController_alarm (<= (+ GateController_time 370) GateController_thousand)), 18117#(or (<= (+ GateController_time 360) GateController_thousand) GateController_alarm), 18118#(or (<= (+ GateController_time 350) GateController_thousand) GateController_alarm), 18119#(or GateController_alarm (<= (+ GateController_time 340) GateController_thousand)), 18120#(or (<= (+ GateController_time 330) GateController_thousand) GateController_alarm), 18121#(or GateController_alarm (<= (+ GateController_time 320) GateController_thousand)), 18122#(or GateController_alarm (<= (+ GateController_time 310) GateController_thousand)), 18123#(or GateController_alarm (<= (+ GateController_time 300) GateController_thousand)), 18124#(or GateController_alarm (<= (+ GateController_time 290) GateController_thousand)), 18125#(or GateController_alarm (<= (+ GateController_time 280) GateController_thousand)), 18126#(or (<= (+ GateController_time 270) GateController_thousand) GateController_alarm), 18127#(or GateController_alarm (<= (+ GateController_time 260) GateController_thousand)), 18128#(or GateController_alarm (<= (+ GateController_time 250) GateController_thousand)), 18129#(or GateController_alarm (<= (+ GateController_time 240) GateController_thousand)), 18130#(or GateController_alarm (<= (+ GateController_time 230) GateController_thousand)), 18131#(or GateController_alarm (<= (+ GateController_time 220) GateController_thousand)), 18132#(or GateController_alarm (<= (+ GateController_time 210) GateController_thousand)), 18133#(or GateController_alarm (<= (+ GateController_time 200) GateController_thousand)), 18134#GateController_alarm] [2018-07-23 13:36:56,235 INFO L134 CoverageAnalysis]: Checked inductivity of 3240 backedges. 0 proven. 3240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:56,235 INFO L450 AbstractCegarLoop]: Interpolant automaton has 84 states [2018-07-23 13:36:56,236 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 84 interpolants. [2018-07-23 13:36:56,236 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3485, Invalid=3487, Unknown=0, NotChecked=0, Total=6972 [2018-07-23 13:36:56,236 INFO L87 Difference]: Start difference. First operand 84 states and 84 transitions. Second operand 84 states. [2018-07-23 13:36:56,308 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:56,308 INFO L93 Difference]: Finished difference Result 87 states and 87 transitions. [2018-07-23 13:36:56,308 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 84 states. [2018-07-23 13:36:56,308 INFO L78 Accepts]: Start accepts. Automaton has 84 states. Word has length 83 [2018-07-23 13:36:56,309 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:56,309 INFO L225 Difference]: With dead ends: 87 [2018-07-23 13:36:56,309 INFO L226 Difference]: Without dead ends: 85 [2018-07-23 13:36:56,310 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 82 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 82 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 159 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=3485, Invalid=3487, Unknown=0, NotChecked=0, Total=6972 [2018-07-23 13:36:56,310 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states. [2018-07-23 13:36:56,316 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 85. [2018-07-23 13:36:56,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 85 states. [2018-07-23 13:36:56,316 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85 states to 85 states and 85 transitions. [2018-07-23 13:36:56,316 INFO L78 Accepts]: Start accepts. Automaton has 85 states and 85 transitions. Word has length 83 [2018-07-23 13:36:56,317 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:56,317 INFO L471 AbstractCegarLoop]: Abstraction has 85 states and 85 transitions. [2018-07-23 13:36:56,317 INFO L472 AbstractCegarLoop]: Interpolant automaton has 84 states. [2018-07-23 13:36:56,317 INFO L276 IsEmpty]: Start isEmpty. Operand 85 states and 85 transitions. [2018-07-23 13:36:56,317 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-07-23 13:36:56,317 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:56,318 INFO L357 BasicCegarLoop]: trace histogram [81, 1, 1, 1] [2018-07-23 13:36:56,318 INFO L414 AbstractCegarLoop]: === Iteration 82 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:56,318 INFO L82 PathProgramCache]: Analyzing trace with hash -1324384, now seen corresponding path program 81 times [2018-07-23 13:36:56,318 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:56,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:56,756 INFO L134 CoverageAnalysis]: Checked inductivity of 3321 backedges. 0 proven. 3321 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:56,756 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:56,757 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [83] total 83 [2018-07-23 13:36:56,757 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:56,757 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:56,757 INFO L185 omatonBuilderFactory]: Interpolants [18560#(or GateController_alarm (<= (+ GateController_time 210) GateController_thousand)), 18561#(or GateController_alarm (<= (+ GateController_time 200) GateController_thousand)), 18562#(or (<= (+ GateController_time 190) GateController_thousand) GateController_alarm), 18563#GateController_alarm, 18479#true, 18480#false, 18481#(<= (+ GateController_time 1000) GateController_thousand), 18482#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 18483#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 18484#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 18485#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 18486#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 18487#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 18488#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 18489#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 18490#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 18491#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 18492#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 18493#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 18494#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 18495#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 18496#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 18497#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 18498#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 18499#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 18500#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 18501#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 18502#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 18503#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 18504#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 18505#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 18506#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 18507#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 18508#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 18509#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 18510#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 18511#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 18512#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 18513#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 18514#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 18515#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 18516#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 18517#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 18518#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 18519#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 18520#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 18521#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 18522#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 18523#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 18524#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 18525#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 18526#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 18527#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 18528#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 18529#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 18530#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 18531#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 18532#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 18533#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 18534#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 18535#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 18536#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 18537#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 18538#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 18539#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 18540#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 18541#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 18542#(or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)), 18543#(or GateController_alarm (<= (+ GateController_time 380) GateController_thousand)), 18544#(or GateController_alarm (<= (+ GateController_time 370) GateController_thousand)), 18545#(or (<= (+ GateController_time 360) GateController_thousand) GateController_alarm), 18546#(or (<= (+ GateController_time 350) GateController_thousand) GateController_alarm), 18547#(or GateController_alarm (<= (+ GateController_time 340) GateController_thousand)), 18548#(or (<= (+ GateController_time 330) GateController_thousand) GateController_alarm), 18549#(or GateController_alarm (<= (+ GateController_time 320) GateController_thousand)), 18550#(or GateController_alarm (<= (+ GateController_time 310) GateController_thousand)), 18551#(or GateController_alarm (<= (+ GateController_time 300) GateController_thousand)), 18552#(or GateController_alarm (<= (+ GateController_time 290) GateController_thousand)), 18553#(or GateController_alarm (<= (+ GateController_time 280) GateController_thousand)), 18554#(or (<= (+ GateController_time 270) GateController_thousand) GateController_alarm), 18555#(or GateController_alarm (<= (+ GateController_time 260) GateController_thousand)), 18556#(or GateController_alarm (<= (+ GateController_time 250) GateController_thousand)), 18557#(or GateController_alarm (<= (+ GateController_time 240) GateController_thousand)), 18558#(or GateController_alarm (<= (+ GateController_time 230) GateController_thousand)), 18559#(or GateController_alarm (<= (+ GateController_time 220) GateController_thousand))] [2018-07-23 13:36:56,758 INFO L134 CoverageAnalysis]: Checked inductivity of 3321 backedges. 0 proven. 3321 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:56,758 INFO L450 AbstractCegarLoop]: Interpolant automaton has 85 states [2018-07-23 13:36:56,759 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 85 interpolants. [2018-07-23 13:36:56,759 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3569, Invalid=3571, Unknown=0, NotChecked=0, Total=7140 [2018-07-23 13:36:56,759 INFO L87 Difference]: Start difference. First operand 85 states and 85 transitions. Second operand 85 states. [2018-07-23 13:36:56,815 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:56,815 INFO L93 Difference]: Finished difference Result 88 states and 88 transitions. [2018-07-23 13:36:56,816 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 85 states. [2018-07-23 13:36:56,816 INFO L78 Accepts]: Start accepts. Automaton has 85 states. Word has length 84 [2018-07-23 13:36:56,816 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:56,816 INFO L225 Difference]: With dead ends: 88 [2018-07-23 13:36:56,816 INFO L226 Difference]: Without dead ends: 86 [2018-07-23 13:36:56,817 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 83 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 83 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 161 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=3569, Invalid=3571, Unknown=0, NotChecked=0, Total=7140 [2018-07-23 13:36:56,817 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 86 states. [2018-07-23 13:36:56,822 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 86 to 86. [2018-07-23 13:36:56,822 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 86 states. [2018-07-23 13:36:56,822 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 86 transitions. [2018-07-23 13:36:56,822 INFO L78 Accepts]: Start accepts. Automaton has 86 states and 86 transitions. Word has length 84 [2018-07-23 13:36:56,822 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:56,822 INFO L471 AbstractCegarLoop]: Abstraction has 86 states and 86 transitions. [2018-07-23 13:36:56,822 INFO L472 AbstractCegarLoop]: Interpolant automaton has 85 states. [2018-07-23 13:36:56,823 INFO L276 IsEmpty]: Start isEmpty. Operand 86 states and 86 transitions. [2018-07-23 13:36:56,823 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2018-07-23 13:36:56,823 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:56,823 INFO L357 BasicCegarLoop]: trace histogram [82, 1, 1, 1] [2018-07-23 13:36:56,823 INFO L414 AbstractCegarLoop]: === Iteration 83 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:56,823 INFO L82 PathProgramCache]: Analyzing trace with hash -41046304, now seen corresponding path program 82 times [2018-07-23 13:36:56,824 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:56,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:57,252 INFO L134 CoverageAnalysis]: Checked inductivity of 3403 backedges. 0 proven. 3403 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:57,252 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:57,253 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [84] total 84 [2018-07-23 13:36:57,253 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:57,253 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:57,253 INFO L185 omatonBuilderFactory]: Interpolants [18944#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 18945#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 18946#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 18947#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 18948#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 18949#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 18950#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 18951#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 18952#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 18953#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 18954#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 18955#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 18956#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 18957#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 18958#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 18959#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 18960#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 18961#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 18962#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 18963#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 18964#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 18965#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 18966#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 18967#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 18968#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 18969#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 18970#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 18971#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 18972#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 18973#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 18974#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 18975#(or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)), 18976#(or GateController_alarm (<= (+ GateController_time 380) GateController_thousand)), 18977#(or GateController_alarm (<= (+ GateController_time 370) GateController_thousand)), 18978#(or (<= (+ GateController_time 360) GateController_thousand) GateController_alarm), 18979#(or (<= (+ GateController_time 350) GateController_thousand) GateController_alarm), 18980#(or GateController_alarm (<= (+ GateController_time 340) GateController_thousand)), 18981#(or (<= (+ GateController_time 330) GateController_thousand) GateController_alarm), 18982#(or GateController_alarm (<= (+ GateController_time 320) GateController_thousand)), 18983#(or GateController_alarm (<= (+ GateController_time 310) GateController_thousand)), 18984#(or GateController_alarm (<= (+ GateController_time 300) GateController_thousand)), 18985#(or GateController_alarm (<= (+ GateController_time 290) GateController_thousand)), 18986#(or GateController_alarm (<= (+ GateController_time 280) GateController_thousand)), 18987#(or (<= (+ GateController_time 270) GateController_thousand) GateController_alarm), 18988#(or GateController_alarm (<= (+ GateController_time 260) GateController_thousand)), 18989#(or GateController_alarm (<= (+ GateController_time 250) GateController_thousand)), 18990#(or GateController_alarm (<= (+ GateController_time 240) GateController_thousand)), 18991#(or GateController_alarm (<= (+ GateController_time 230) GateController_thousand)), 18992#(or GateController_alarm (<= (+ GateController_time 220) GateController_thousand)), 18993#(or GateController_alarm (<= (+ GateController_time 210) GateController_thousand)), 18994#(or GateController_alarm (<= (+ GateController_time 200) GateController_thousand)), 18995#(or (<= (+ GateController_time 190) GateController_thousand) GateController_alarm), 18996#(or GateController_alarm (<= (+ GateController_time 180) GateController_thousand)), 18997#GateController_alarm, 18912#true, 18913#false, 18914#(<= (+ GateController_time 1000) GateController_thousand), 18915#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 18916#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 18917#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 18918#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 18919#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 18920#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 18921#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 18922#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 18923#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 18924#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 18925#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 18926#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 18927#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 18928#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 18929#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 18930#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 18931#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 18932#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 18933#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 18934#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 18935#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 18936#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 18937#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 18938#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 18939#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 18940#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 18941#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 18942#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 18943#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand))] [2018-07-23 13:36:57,254 INFO L134 CoverageAnalysis]: Checked inductivity of 3403 backedges. 0 proven. 3403 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:57,254 INFO L450 AbstractCegarLoop]: Interpolant automaton has 86 states [2018-07-23 13:36:57,255 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 86 interpolants. [2018-07-23 13:36:57,255 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3654, Invalid=3656, Unknown=0, NotChecked=0, Total=7310 [2018-07-23 13:36:57,256 INFO L87 Difference]: Start difference. First operand 86 states and 86 transitions. Second operand 86 states. [2018-07-23 13:36:57,312 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:57,312 INFO L93 Difference]: Finished difference Result 89 states and 89 transitions. [2018-07-23 13:36:57,312 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 86 states. [2018-07-23 13:36:57,313 INFO L78 Accepts]: Start accepts. Automaton has 86 states. Word has length 85 [2018-07-23 13:36:57,313 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:57,313 INFO L225 Difference]: With dead ends: 89 [2018-07-23 13:36:57,313 INFO L226 Difference]: Without dead ends: 87 [2018-07-23 13:36:57,314 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 84 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 84 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 163 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=3654, Invalid=3656, Unknown=0, NotChecked=0, Total=7310 [2018-07-23 13:36:57,314 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states. [2018-07-23 13:36:57,319 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 87. [2018-07-23 13:36:57,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 87 states. [2018-07-23 13:36:57,320 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 87 transitions. [2018-07-23 13:36:57,320 INFO L78 Accepts]: Start accepts. Automaton has 87 states and 87 transitions. Word has length 85 [2018-07-23 13:36:57,320 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:57,320 INFO L471 AbstractCegarLoop]: Abstraction has 87 states and 87 transitions. [2018-07-23 13:36:57,320 INFO L472 AbstractCegarLoop]: Interpolant automaton has 86 states. [2018-07-23 13:36:57,320 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 87 transitions. [2018-07-23 13:36:57,321 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-07-23 13:36:57,321 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:57,321 INFO L357 BasicCegarLoop]: trace histogram [83, 1, 1, 1] [2018-07-23 13:36:57,321 INFO L414 AbstractCegarLoop]: === Iteration 84 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:57,321 INFO L82 PathProgramCache]: Analyzing trace with hash -1272425824, now seen corresponding path program 83 times [2018-07-23 13:36:57,321 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:57,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:57,792 INFO L134 CoverageAnalysis]: Checked inductivity of 3486 backedges. 0 proven. 3486 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:57,792 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:57,792 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [85] total 85 [2018-07-23 13:36:57,793 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:57,793 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:57,793 INFO L185 omatonBuilderFactory]: Interpolants [19350#true, 19351#false, 19352#(<= (+ GateController_time 1000) GateController_thousand), 19353#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 19354#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 19355#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 19356#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 19357#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 19358#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 19359#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 19360#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 19361#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 19362#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 19363#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 19364#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 19365#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 19366#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 19367#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 19368#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 19369#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 19370#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 19371#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 19372#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 19373#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 19374#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 19375#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 19376#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 19377#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 19378#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 19379#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 19380#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 19381#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 19382#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 19383#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 19384#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 19385#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 19386#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 19387#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 19388#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 19389#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 19390#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 19391#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 19392#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 19393#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 19394#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 19395#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 19396#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 19397#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 19398#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 19399#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 19400#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 19401#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 19402#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 19403#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 19404#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 19405#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 19406#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 19407#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 19408#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 19409#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 19410#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 19411#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 19412#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 19413#(or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)), 19414#(or GateController_alarm (<= (+ GateController_time 380) GateController_thousand)), 19415#(or GateController_alarm (<= (+ GateController_time 370) GateController_thousand)), 19416#(or (<= (+ GateController_time 360) GateController_thousand) GateController_alarm), 19417#(or (<= (+ GateController_time 350) GateController_thousand) GateController_alarm), 19418#(or GateController_alarm (<= (+ GateController_time 340) GateController_thousand)), 19419#(or (<= (+ GateController_time 330) GateController_thousand) GateController_alarm), 19420#(or GateController_alarm (<= (+ GateController_time 320) GateController_thousand)), 19421#(or GateController_alarm (<= (+ GateController_time 310) GateController_thousand)), 19422#(or GateController_alarm (<= (+ GateController_time 300) GateController_thousand)), 19423#(or GateController_alarm (<= (+ GateController_time 290) GateController_thousand)), 19424#(or GateController_alarm (<= (+ GateController_time 280) GateController_thousand)), 19425#(or (<= (+ GateController_time 270) GateController_thousand) GateController_alarm), 19426#(or GateController_alarm (<= (+ GateController_time 260) GateController_thousand)), 19427#(or GateController_alarm (<= (+ GateController_time 250) GateController_thousand)), 19428#(or GateController_alarm (<= (+ GateController_time 240) GateController_thousand)), 19429#(or GateController_alarm (<= (+ GateController_time 230) GateController_thousand)), 19430#(or GateController_alarm (<= (+ GateController_time 220) GateController_thousand)), 19431#(or GateController_alarm (<= (+ GateController_time 210) GateController_thousand)), 19432#(or GateController_alarm (<= (+ GateController_time 200) GateController_thousand)), 19433#(or (<= (+ GateController_time 190) GateController_thousand) GateController_alarm), 19434#(or GateController_alarm (<= (+ GateController_time 180) GateController_thousand)), 19435#(or GateController_alarm (<= (+ GateController_time 170) GateController_thousand)), 19436#GateController_alarm] [2018-07-23 13:36:57,794 INFO L134 CoverageAnalysis]: Checked inductivity of 3486 backedges. 0 proven. 3486 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:57,794 INFO L450 AbstractCegarLoop]: Interpolant automaton has 87 states [2018-07-23 13:36:57,795 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 87 interpolants. [2018-07-23 13:36:57,795 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3740, Invalid=3742, Unknown=0, NotChecked=0, Total=7482 [2018-07-23 13:36:57,795 INFO L87 Difference]: Start difference. First operand 87 states and 87 transitions. Second operand 87 states. [2018-07-23 13:36:57,879 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:57,880 INFO L93 Difference]: Finished difference Result 90 states and 90 transitions. [2018-07-23 13:36:57,880 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 87 states. [2018-07-23 13:36:57,880 INFO L78 Accepts]: Start accepts. Automaton has 87 states. Word has length 86 [2018-07-23 13:36:57,880 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:57,881 INFO L225 Difference]: With dead ends: 90 [2018-07-23 13:36:57,881 INFO L226 Difference]: Without dead ends: 88 [2018-07-23 13:36:57,882 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 85 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 85 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 165 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=3740, Invalid=3742, Unknown=0, NotChecked=0, Total=7482 [2018-07-23 13:36:57,882 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88 states. [2018-07-23 13:36:57,887 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88 to 88. [2018-07-23 13:36:57,888 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 88 states. [2018-07-23 13:36:57,888 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 88 transitions. [2018-07-23 13:36:57,888 INFO L78 Accepts]: Start accepts. Automaton has 88 states and 88 transitions. Word has length 86 [2018-07-23 13:36:57,888 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:57,888 INFO L471 AbstractCegarLoop]: Abstraction has 88 states and 88 transitions. [2018-07-23 13:36:57,888 INFO L472 AbstractCegarLoop]: Interpolant automaton has 87 states. [2018-07-23 13:36:57,889 INFO L276 IsEmpty]: Start isEmpty. Operand 88 states and 88 transitions. [2018-07-23 13:36:57,889 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-07-23 13:36:57,889 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:57,889 INFO L357 BasicCegarLoop]: trace histogram [84, 1, 1, 1] [2018-07-23 13:36:57,889 INFO L414 AbstractCegarLoop]: === Iteration 85 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:57,890 INFO L82 PathProgramCache]: Analyzing trace with hash -790485280, now seen corresponding path program 84 times [2018-07-23 13:36:57,890 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:57,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:58,328 INFO L134 CoverageAnalysis]: Checked inductivity of 3570 backedges. 0 proven. 3570 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:58,329 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:58,329 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [86] total 86 [2018-07-23 13:36:58,329 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:58,329 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:58,329 INFO L185 omatonBuilderFactory]: Interpolants [19840#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 19841#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 19842#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 19843#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 19844#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 19845#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 19846#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 19847#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 19848#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 19849#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 19850#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 19851#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 19852#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 19853#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 19854#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 19855#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 19856#(or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)), 19857#(or GateController_alarm (<= (+ GateController_time 380) GateController_thousand)), 19858#(or GateController_alarm (<= (+ GateController_time 370) GateController_thousand)), 19859#(or (<= (+ GateController_time 360) GateController_thousand) GateController_alarm), 19860#(or (<= (+ GateController_time 350) GateController_thousand) GateController_alarm), 19861#(or GateController_alarm (<= (+ GateController_time 340) GateController_thousand)), 19862#(or (<= (+ GateController_time 330) GateController_thousand) GateController_alarm), 19863#(or GateController_alarm (<= (+ GateController_time 320) GateController_thousand)), 19864#(or GateController_alarm (<= (+ GateController_time 310) GateController_thousand)), 19865#(or GateController_alarm (<= (+ GateController_time 300) GateController_thousand)), 19866#(or GateController_alarm (<= (+ GateController_time 290) GateController_thousand)), 19867#(or GateController_alarm (<= (+ GateController_time 280) GateController_thousand)), 19868#(or (<= (+ GateController_time 270) GateController_thousand) GateController_alarm), 19869#(or GateController_alarm (<= (+ GateController_time 260) GateController_thousand)), 19870#(or GateController_alarm (<= (+ GateController_time 250) GateController_thousand)), 19871#(or GateController_alarm (<= (+ GateController_time 240) GateController_thousand)), 19872#(or GateController_alarm (<= (+ GateController_time 230) GateController_thousand)), 19873#(or GateController_alarm (<= (+ GateController_time 220) GateController_thousand)), 19874#(or GateController_alarm (<= (+ GateController_time 210) GateController_thousand)), 19875#(or GateController_alarm (<= (+ GateController_time 200) GateController_thousand)), 19876#(or (<= (+ GateController_time 190) GateController_thousand) GateController_alarm), 19877#(or GateController_alarm (<= (+ GateController_time 180) GateController_thousand)), 19878#(or GateController_alarm (<= (+ GateController_time 170) GateController_thousand)), 19879#(or GateController_alarm (<= (+ GateController_time 160) GateController_thousand)), 19880#GateController_alarm, 19793#true, 19794#false, 19795#(<= (+ GateController_time 1000) GateController_thousand), 19796#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 19797#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 19798#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 19799#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 19800#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 19801#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 19802#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 19803#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 19804#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 19805#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 19806#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 19807#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 19808#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 19809#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 19810#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 19811#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 19812#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 19813#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 19814#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 19815#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 19816#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 19817#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 19818#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 19819#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 19820#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 19821#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 19822#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 19823#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 19824#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 19825#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 19826#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 19827#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 19828#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 19829#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 19830#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 19831#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 19832#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 19833#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 19834#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 19835#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 19836#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 19837#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 19838#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 19839#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm)] [2018-07-23 13:36:58,330 INFO L134 CoverageAnalysis]: Checked inductivity of 3570 backedges. 0 proven. 3570 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:58,330 INFO L450 AbstractCegarLoop]: Interpolant automaton has 88 states [2018-07-23 13:36:58,331 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 88 interpolants. [2018-07-23 13:36:58,331 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3827, Invalid=3829, Unknown=0, NotChecked=0, Total=7656 [2018-07-23 13:36:58,331 INFO L87 Difference]: Start difference. First operand 88 states and 88 transitions. Second operand 88 states. [2018-07-23 13:36:58,378 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:58,378 INFO L93 Difference]: Finished difference Result 91 states and 91 transitions. [2018-07-23 13:36:58,378 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 88 states. [2018-07-23 13:36:58,378 INFO L78 Accepts]: Start accepts. Automaton has 88 states. Word has length 87 [2018-07-23 13:36:58,378 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:58,379 INFO L225 Difference]: With dead ends: 91 [2018-07-23 13:36:58,379 INFO L226 Difference]: Without dead ends: 89 [2018-07-23 13:36:58,380 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 86 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 86 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 167 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=3827, Invalid=3829, Unknown=0, NotChecked=0, Total=7656 [2018-07-23 13:36:58,380 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 89 states. [2018-07-23 13:36:58,385 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 89 to 89. [2018-07-23 13:36:58,385 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 89 states. [2018-07-23 13:36:58,385 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 89 transitions. [2018-07-23 13:36:58,385 INFO L78 Accepts]: Start accepts. Automaton has 89 states and 89 transitions. Word has length 87 [2018-07-23 13:36:58,385 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:58,386 INFO L471 AbstractCegarLoop]: Abstraction has 89 states and 89 transitions. [2018-07-23 13:36:58,386 INFO L472 AbstractCegarLoop]: Interpolant automaton has 88 states. [2018-07-23 13:36:58,386 INFO L276 IsEmpty]: Start isEmpty. Operand 89 states and 89 transitions. [2018-07-23 13:36:58,386 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2018-07-23 13:36:58,386 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:58,386 INFO L357 BasicCegarLoop]: trace histogram [85, 1, 1, 1] [2018-07-23 13:36:58,387 INFO L414 AbstractCegarLoop]: === Iteration 86 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:58,387 INFO L82 PathProgramCache]: Analyzing trace with hash 1264769696, now seen corresponding path program 85 times [2018-07-23 13:36:58,387 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:58,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:58,831 INFO L134 CoverageAnalysis]: Checked inductivity of 3655 backedges. 0 proven. 3655 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:58,831 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:58,831 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [87] total 87 [2018-07-23 13:36:58,831 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:58,832 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:58,832 INFO L185 omatonBuilderFactory]: Interpolants [20241#true, 20242#false, 20243#(<= (+ GateController_time 1000) GateController_thousand), 20244#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 20245#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 20246#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 20247#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 20248#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 20249#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 20250#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 20251#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 20252#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 20253#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 20254#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 20255#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 20256#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 20257#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 20258#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 20259#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 20260#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 20261#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 20262#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 20263#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 20264#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 20265#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 20266#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 20267#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 20268#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 20269#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 20270#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 20271#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 20272#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 20273#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 20274#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 20275#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 20276#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 20277#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 20278#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 20279#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 20280#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 20281#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 20282#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 20283#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 20284#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 20285#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 20286#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 20287#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 20288#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 20289#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 20290#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 20291#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 20292#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 20293#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 20294#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 20295#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 20296#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 20297#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 20298#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 20299#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 20300#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 20301#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 20302#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 20303#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 20304#(or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)), 20305#(or GateController_alarm (<= (+ GateController_time 380) GateController_thousand)), 20306#(or GateController_alarm (<= (+ GateController_time 370) GateController_thousand)), 20307#(or (<= (+ GateController_time 360) GateController_thousand) GateController_alarm), 20308#(or (<= (+ GateController_time 350) GateController_thousand) GateController_alarm), 20309#(or GateController_alarm (<= (+ GateController_time 340) GateController_thousand)), 20310#(or (<= (+ GateController_time 330) GateController_thousand) GateController_alarm), 20311#(or GateController_alarm (<= (+ GateController_time 320) GateController_thousand)), 20312#(or GateController_alarm (<= (+ GateController_time 310) GateController_thousand)), 20313#(or GateController_alarm (<= (+ GateController_time 300) GateController_thousand)), 20314#(or GateController_alarm (<= (+ GateController_time 290) GateController_thousand)), 20315#(or GateController_alarm (<= (+ GateController_time 280) GateController_thousand)), 20316#(or (<= (+ GateController_time 270) GateController_thousand) GateController_alarm), 20317#(or GateController_alarm (<= (+ GateController_time 260) GateController_thousand)), 20318#(or GateController_alarm (<= (+ GateController_time 250) GateController_thousand)), 20319#(or GateController_alarm (<= (+ GateController_time 240) GateController_thousand)), 20320#(or GateController_alarm (<= (+ GateController_time 230) GateController_thousand)), 20321#(or GateController_alarm (<= (+ GateController_time 220) GateController_thousand)), 20322#(or GateController_alarm (<= (+ GateController_time 210) GateController_thousand)), 20323#(or GateController_alarm (<= (+ GateController_time 200) GateController_thousand)), 20324#(or (<= (+ GateController_time 190) GateController_thousand) GateController_alarm), 20325#(or GateController_alarm (<= (+ GateController_time 180) GateController_thousand)), 20326#(or GateController_alarm (<= (+ GateController_time 170) GateController_thousand)), 20327#(or GateController_alarm (<= (+ GateController_time 160) GateController_thousand)), 20328#(or GateController_alarm (<= (+ GateController_time 150) GateController_thousand)), 20329#GateController_alarm] [2018-07-23 13:36:58,832 INFO L134 CoverageAnalysis]: Checked inductivity of 3655 backedges. 0 proven. 3655 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:58,833 INFO L450 AbstractCegarLoop]: Interpolant automaton has 89 states [2018-07-23 13:36:58,833 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 89 interpolants. [2018-07-23 13:36:58,834 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3915, Invalid=3917, Unknown=0, NotChecked=0, Total=7832 [2018-07-23 13:36:58,834 INFO L87 Difference]: Start difference. First operand 89 states and 89 transitions. Second operand 89 states. [2018-07-23 13:36:58,921 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:58,921 INFO L93 Difference]: Finished difference Result 92 states and 92 transitions. [2018-07-23 13:36:58,922 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 89 states. [2018-07-23 13:36:58,922 INFO L78 Accepts]: Start accepts. Automaton has 89 states. Word has length 88 [2018-07-23 13:36:58,922 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:58,923 INFO L225 Difference]: With dead ends: 92 [2018-07-23 13:36:58,923 INFO L226 Difference]: Without dead ends: 90 [2018-07-23 13:36:58,923 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 87 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 87 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 169 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=3915, Invalid=3917, Unknown=0, NotChecked=0, Total=7832 [2018-07-23 13:36:58,924 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90 states. [2018-07-23 13:36:58,929 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90 to 90. [2018-07-23 13:36:58,929 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 90 states. [2018-07-23 13:36:58,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90 states to 90 states and 90 transitions. [2018-07-23 13:36:58,930 INFO L78 Accepts]: Start accepts. Automaton has 90 states and 90 transitions. Word has length 88 [2018-07-23 13:36:58,930 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:58,930 INFO L471 AbstractCegarLoop]: Abstraction has 90 states and 90 transitions. [2018-07-23 13:36:58,930 INFO L472 AbstractCegarLoop]: Interpolant automaton has 89 states. [2018-07-23 13:36:58,931 INFO L276 IsEmpty]: Start isEmpty. Operand 90 states and 90 transitions. [2018-07-23 13:36:58,931 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-07-23 13:36:58,931 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:58,931 INFO L357 BasicCegarLoop]: trace histogram [86, 1, 1, 1] [2018-07-23 13:36:58,931 INFO L414 AbstractCegarLoop]: === Iteration 87 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:58,931 INFO L82 PathProgramCache]: Analyzing trace with hash 553164512, now seen corresponding path program 86 times [2018-07-23 13:36:58,932 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:58,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:59,389 INFO L134 CoverageAnalysis]: Checked inductivity of 3741 backedges. 0 proven. 3741 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:59,390 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:59,390 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [88] total 88 [2018-07-23 13:36:59,390 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:59,390 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:59,391 INFO L185 omatonBuilderFactory]: Interpolants [20736#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 20737#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 20738#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 20739#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 20740#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 20741#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 20742#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 20743#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 20744#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 20745#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 20746#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 20747#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 20748#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 20749#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 20750#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 20751#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 20752#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 20753#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 20754#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 20755#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 20756#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 20757#(or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)), 20758#(or GateController_alarm (<= (+ GateController_time 380) GateController_thousand)), 20759#(or GateController_alarm (<= (+ GateController_time 370) GateController_thousand)), 20760#(or (<= (+ GateController_time 360) GateController_thousand) GateController_alarm), 20761#(or (<= (+ GateController_time 350) GateController_thousand) GateController_alarm), 20762#(or GateController_alarm (<= (+ GateController_time 340) GateController_thousand)), 20763#(or (<= (+ GateController_time 330) GateController_thousand) GateController_alarm), 20764#(or GateController_alarm (<= (+ GateController_time 320) GateController_thousand)), 20765#(or GateController_alarm (<= (+ GateController_time 310) GateController_thousand)), 20766#(or GateController_alarm (<= (+ GateController_time 300) GateController_thousand)), 20767#(or GateController_alarm (<= (+ GateController_time 290) GateController_thousand)), 20768#(or GateController_alarm (<= (+ GateController_time 280) GateController_thousand)), 20769#(or (<= (+ GateController_time 270) GateController_thousand) GateController_alarm), 20770#(or GateController_alarm (<= (+ GateController_time 260) GateController_thousand)), 20771#(or GateController_alarm (<= (+ GateController_time 250) GateController_thousand)), 20772#(or GateController_alarm (<= (+ GateController_time 240) GateController_thousand)), 20773#(or GateController_alarm (<= (+ GateController_time 230) GateController_thousand)), 20774#(or GateController_alarm (<= (+ GateController_time 220) GateController_thousand)), 20775#(or GateController_alarm (<= (+ GateController_time 210) GateController_thousand)), 20776#(or GateController_alarm (<= (+ GateController_time 200) GateController_thousand)), 20777#(or (<= (+ GateController_time 190) GateController_thousand) GateController_alarm), 20778#(or GateController_alarm (<= (+ GateController_time 180) GateController_thousand)), 20779#(or GateController_alarm (<= (+ GateController_time 170) GateController_thousand)), 20780#(or GateController_alarm (<= (+ GateController_time 160) GateController_thousand)), 20781#(or GateController_alarm (<= (+ GateController_time 150) GateController_thousand)), 20782#(or (<= (+ GateController_time 140) GateController_thousand) GateController_alarm), 20783#GateController_alarm, 20694#true, 20695#false, 20696#(<= (+ GateController_time 1000) GateController_thousand), 20697#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 20698#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 20699#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 20700#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 20701#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 20702#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 20703#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 20704#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 20705#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 20706#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 20707#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 20708#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 20709#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 20710#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 20711#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 20712#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 20713#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 20714#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 20715#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 20716#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 20717#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 20718#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 20719#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 20720#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 20721#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 20722#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 20723#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 20724#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 20725#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 20726#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 20727#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 20728#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 20729#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 20730#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 20731#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 20732#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 20733#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 20734#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 20735#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand))] [2018-07-23 13:36:59,391 INFO L134 CoverageAnalysis]: Checked inductivity of 3741 backedges. 0 proven. 3741 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:59,391 INFO L450 AbstractCegarLoop]: Interpolant automaton has 90 states [2018-07-23 13:36:59,392 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 90 interpolants. [2018-07-23 13:36:59,393 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=4004, Invalid=4006, Unknown=0, NotChecked=0, Total=8010 [2018-07-23 13:36:59,393 INFO L87 Difference]: Start difference. First operand 90 states and 90 transitions. Second operand 90 states. [2018-07-23 13:36:59,442 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:36:59,443 INFO L93 Difference]: Finished difference Result 93 states and 93 transitions. [2018-07-23 13:36:59,443 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 90 states. [2018-07-23 13:36:59,443 INFO L78 Accepts]: Start accepts. Automaton has 90 states. Word has length 89 [2018-07-23 13:36:59,443 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:36:59,444 INFO L225 Difference]: With dead ends: 93 [2018-07-23 13:36:59,444 INFO L226 Difference]: Without dead ends: 91 [2018-07-23 13:36:59,445 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 88 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 88 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 171 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=4004, Invalid=4006, Unknown=0, NotChecked=0, Total=8010 [2018-07-23 13:36:59,445 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91 states. [2018-07-23 13:36:59,458 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91 to 91. [2018-07-23 13:36:59,458 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 91 states. [2018-07-23 13:36:59,459 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91 states to 91 states and 91 transitions. [2018-07-23 13:36:59,459 INFO L78 Accepts]: Start accepts. Automaton has 91 states and 91 transitions. Word has length 89 [2018-07-23 13:36:59,459 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:36:59,459 INFO L471 AbstractCegarLoop]: Abstraction has 91 states and 91 transitions. [2018-07-23 13:36:59,459 INFO L472 AbstractCegarLoop]: Interpolant automaton has 90 states. [2018-07-23 13:36:59,459 INFO L276 IsEmpty]: Start isEmpty. Operand 91 states and 91 transitions. [2018-07-23 13:36:59,460 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-07-23 13:36:59,460 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:36:59,460 INFO L357 BasicCegarLoop]: trace histogram [87, 1, 1, 1] [2018-07-23 13:36:59,460 INFO L414 AbstractCegarLoop]: === Iteration 88 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:36:59,460 INFO L82 PathProgramCache]: Analyzing trace with hash -31759712, now seen corresponding path program 87 times [2018-07-23 13:36:59,461 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:36:59,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:36:59,926 INFO L134 CoverageAnalysis]: Checked inductivity of 3828 backedges. 0 proven. 3828 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:59,927 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:36:59,927 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [89] total 89 [2018-07-23 13:36:59,927 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:36:59,927 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:59,928 INFO L185 omatonBuilderFactory]: Interpolants [21152#true, 21153#false, 21154#(<= (+ GateController_time 1000) GateController_thousand), 21155#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 21156#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 21157#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 21158#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 21159#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 21160#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 21161#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 21162#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 21163#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 21164#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 21165#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 21166#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 21167#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 21168#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 21169#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 21170#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 21171#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 21172#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 21173#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 21174#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 21175#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 21176#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 21177#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 21178#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 21179#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 21180#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 21181#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 21182#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 21183#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 21184#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 21185#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 21186#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 21187#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 21188#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 21189#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 21190#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 21191#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 21192#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 21193#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 21194#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 21195#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 21196#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 21197#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 21198#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 21199#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 21200#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 21201#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 21202#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 21203#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 21204#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 21205#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 21206#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 21207#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 21208#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 21209#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 21210#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 21211#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 21212#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 21213#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 21214#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 21215#(or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)), 21216#(or GateController_alarm (<= (+ GateController_time 380) GateController_thousand)), 21217#(or GateController_alarm (<= (+ GateController_time 370) GateController_thousand)), 21218#(or (<= (+ GateController_time 360) GateController_thousand) GateController_alarm), 21219#(or (<= (+ GateController_time 350) GateController_thousand) GateController_alarm), 21220#(or GateController_alarm (<= (+ GateController_time 340) GateController_thousand)), 21221#(or (<= (+ GateController_time 330) GateController_thousand) GateController_alarm), 21222#(or GateController_alarm (<= (+ GateController_time 320) GateController_thousand)), 21223#(or GateController_alarm (<= (+ GateController_time 310) GateController_thousand)), 21224#(or GateController_alarm (<= (+ GateController_time 300) GateController_thousand)), 21225#(or GateController_alarm (<= (+ GateController_time 290) GateController_thousand)), 21226#(or GateController_alarm (<= (+ GateController_time 280) GateController_thousand)), 21227#(or (<= (+ GateController_time 270) GateController_thousand) GateController_alarm), 21228#(or GateController_alarm (<= (+ GateController_time 260) GateController_thousand)), 21229#(or GateController_alarm (<= (+ GateController_time 250) GateController_thousand)), 21230#(or GateController_alarm (<= (+ GateController_time 240) GateController_thousand)), 21231#(or GateController_alarm (<= (+ GateController_time 230) GateController_thousand)), 21232#(or GateController_alarm (<= (+ GateController_time 220) GateController_thousand)), 21233#(or GateController_alarm (<= (+ GateController_time 210) GateController_thousand)), 21234#(or GateController_alarm (<= (+ GateController_time 200) GateController_thousand)), 21235#(or (<= (+ GateController_time 190) GateController_thousand) GateController_alarm), 21236#(or GateController_alarm (<= (+ GateController_time 180) GateController_thousand)), 21237#(or GateController_alarm (<= (+ GateController_time 170) GateController_thousand)), 21238#(or GateController_alarm (<= (+ GateController_time 160) GateController_thousand)), 21239#(or GateController_alarm (<= (+ GateController_time 150) GateController_thousand)), 21240#(or (<= (+ GateController_time 140) GateController_thousand) GateController_alarm), 21241#(or GateController_alarm (<= (+ GateController_time 130) GateController_thousand)), 21242#GateController_alarm] [2018-07-23 13:36:59,928 INFO L134 CoverageAnalysis]: Checked inductivity of 3828 backedges. 0 proven. 3828 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:36:59,928 INFO L450 AbstractCegarLoop]: Interpolant automaton has 91 states [2018-07-23 13:36:59,929 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 91 interpolants. [2018-07-23 13:36:59,929 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=4094, Invalid=4096, Unknown=0, NotChecked=0, Total=8190 [2018-07-23 13:36:59,930 INFO L87 Difference]: Start difference. First operand 91 states and 91 transitions. Second operand 91 states. [2018-07-23 13:37:00,013 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:37:00,013 INFO L93 Difference]: Finished difference Result 94 states and 94 transitions. [2018-07-23 13:37:00,013 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 91 states. [2018-07-23 13:37:00,013 INFO L78 Accepts]: Start accepts. Automaton has 91 states. Word has length 90 [2018-07-23 13:37:00,014 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:37:00,014 INFO L225 Difference]: With dead ends: 94 [2018-07-23 13:37:00,015 INFO L226 Difference]: Without dead ends: 92 [2018-07-23 13:37:00,015 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 89 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 89 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 173 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=4094, Invalid=4096, Unknown=0, NotChecked=0, Total=8190 [2018-07-23 13:37:00,015 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 92 states. [2018-07-23 13:37:00,022 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 92 to 92. [2018-07-23 13:37:00,022 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 92 states. [2018-07-23 13:37:00,023 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92 states to 92 states and 92 transitions. [2018-07-23 13:37:00,023 INFO L78 Accepts]: Start accepts. Automaton has 92 states and 92 transitions. Word has length 90 [2018-07-23 13:37:00,023 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:37:00,023 INFO L471 AbstractCegarLoop]: Abstraction has 92 states and 92 transitions. [2018-07-23 13:37:00,023 INFO L472 AbstractCegarLoop]: Interpolant automaton has 91 states. [2018-07-23 13:37:00,024 INFO L276 IsEmpty]: Start isEmpty. Operand 92 states and 92 transitions. [2018-07-23 13:37:00,024 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2018-07-23 13:37:00,024 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:37:00,024 INFO L357 BasicCegarLoop]: trace histogram [88, 1, 1, 1] [2018-07-23 13:37:00,024 INFO L414 AbstractCegarLoop]: === Iteration 89 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:37:00,025 INFO L82 PathProgramCache]: Analyzing trace with hash -984541472, now seen corresponding path program 88 times [2018-07-23 13:37:00,025 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:37:00,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:37:00,696 INFO L134 CoverageAnalysis]: Checked inductivity of 3916 backedges. 0 proven. 3916 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:37:00,697 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:37:00,697 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [90] total 90 [2018-07-23 13:37:00,697 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:37:00,697 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:37:00,698 INFO L185 omatonBuilderFactory]: Interpolants [21632#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 21633#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 21634#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 21635#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 21636#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 21637#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 21638#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 21639#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 21640#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 21641#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 21642#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 21643#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 21644#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 21645#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 21646#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 21647#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 21648#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 21649#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 21650#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 21651#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 21652#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 21653#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 21654#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 21655#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 21656#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 21657#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 21658#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 21659#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 21660#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 21661#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 21662#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 21663#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 21664#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 21665#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 21666#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 21667#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 21668#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 21669#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 21670#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 21671#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 21672#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 21673#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 21674#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 21675#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 21676#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 21677#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 21678#(or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)), 21679#(or GateController_alarm (<= (+ GateController_time 380) GateController_thousand)), 21680#(or GateController_alarm (<= (+ GateController_time 370) GateController_thousand)), 21681#(or (<= (+ GateController_time 360) GateController_thousand) GateController_alarm), 21682#(or (<= (+ GateController_time 350) GateController_thousand) GateController_alarm), 21683#(or GateController_alarm (<= (+ GateController_time 340) GateController_thousand)), 21684#(or (<= (+ GateController_time 330) GateController_thousand) GateController_alarm), 21685#(or GateController_alarm (<= (+ GateController_time 320) GateController_thousand)), 21686#(or GateController_alarm (<= (+ GateController_time 310) GateController_thousand)), 21687#(or GateController_alarm (<= (+ GateController_time 300) GateController_thousand)), 21688#(or GateController_alarm (<= (+ GateController_time 290) GateController_thousand)), 21689#(or GateController_alarm (<= (+ GateController_time 280) GateController_thousand)), 21690#(or (<= (+ GateController_time 270) GateController_thousand) GateController_alarm), 21691#(or GateController_alarm (<= (+ GateController_time 260) GateController_thousand)), 21692#(or GateController_alarm (<= (+ GateController_time 250) GateController_thousand)), 21693#(or GateController_alarm (<= (+ GateController_time 240) GateController_thousand)), 21694#(or GateController_alarm (<= (+ GateController_time 230) GateController_thousand)), 21695#(or GateController_alarm (<= (+ GateController_time 220) GateController_thousand)), 21696#(or GateController_alarm (<= (+ GateController_time 210) GateController_thousand)), 21697#(or GateController_alarm (<= (+ GateController_time 200) GateController_thousand)), 21698#(or (<= (+ GateController_time 190) GateController_thousand) GateController_alarm), 21699#(or GateController_alarm (<= (+ GateController_time 180) GateController_thousand)), 21700#(or GateController_alarm (<= (+ GateController_time 170) GateController_thousand)), 21701#(or GateController_alarm (<= (+ GateController_time 160) GateController_thousand)), 21702#(or GateController_alarm (<= (+ GateController_time 150) GateController_thousand)), 21703#(or (<= (+ GateController_time 140) GateController_thousand) GateController_alarm), 21704#(or GateController_alarm (<= (+ GateController_time 130) GateController_thousand)), 21705#(or GateController_alarm (<= (+ GateController_time 120) GateController_thousand)), 21706#GateController_alarm, 21615#true, 21616#false, 21617#(<= (+ GateController_time 1000) GateController_thousand), 21618#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 21619#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 21620#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 21621#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 21622#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 21623#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 21624#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 21625#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 21626#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 21627#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 21628#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 21629#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 21630#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 21631#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand))] [2018-07-23 13:37:00,698 INFO L134 CoverageAnalysis]: Checked inductivity of 3916 backedges. 0 proven. 3916 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:37:00,698 INFO L450 AbstractCegarLoop]: Interpolant automaton has 92 states [2018-07-23 13:37:00,699 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 92 interpolants. [2018-07-23 13:37:00,699 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=4185, Invalid=4187, Unknown=0, NotChecked=0, Total=8372 [2018-07-23 13:37:00,699 INFO L87 Difference]: Start difference. First operand 92 states and 92 transitions. Second operand 92 states. [2018-07-23 13:37:00,797 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:37:00,797 INFO L93 Difference]: Finished difference Result 95 states and 95 transitions. [2018-07-23 13:37:00,798 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 92 states. [2018-07-23 13:37:00,798 INFO L78 Accepts]: Start accepts. Automaton has 92 states. Word has length 91 [2018-07-23 13:37:00,798 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:37:00,799 INFO L225 Difference]: With dead ends: 95 [2018-07-23 13:37:00,799 INFO L226 Difference]: Without dead ends: 93 [2018-07-23 13:37:00,799 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 90 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 90 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 175 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=4185, Invalid=4187, Unknown=0, NotChecked=0, Total=8372 [2018-07-23 13:37:00,800 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states. [2018-07-23 13:37:00,806 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 93. [2018-07-23 13:37:00,806 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 93 states. [2018-07-23 13:37:00,807 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 93 transitions. [2018-07-23 13:37:00,807 INFO L78 Accepts]: Start accepts. Automaton has 93 states and 93 transitions. Word has length 91 [2018-07-23 13:37:00,807 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:37:00,807 INFO L471 AbstractCegarLoop]: Abstraction has 93 states and 93 transitions. [2018-07-23 13:37:00,808 INFO L472 AbstractCegarLoop]: Interpolant automaton has 92 states. [2018-07-23 13:37:00,808 INFO L276 IsEmpty]: Start isEmpty. Operand 93 states and 93 transitions. [2018-07-23 13:37:00,808 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-07-23 13:37:00,808 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:37:00,809 INFO L357 BasicCegarLoop]: trace histogram [89, 1, 1, 1] [2018-07-23 13:37:00,809 INFO L414 AbstractCegarLoop]: === Iteration 90 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:37:00,809 INFO L82 PathProgramCache]: Analyzing trace with hash -456004960, now seen corresponding path program 89 times [2018-07-23 13:37:00,809 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:37:00,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:37:01,262 INFO L134 CoverageAnalysis]: Checked inductivity of 4005 backedges. 0 proven. 4005 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:37:01,262 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:37:01,262 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [91] total 91 [2018-07-23 13:37:01,263 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:37:01,263 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:37:01,263 INFO L185 omatonBuilderFactory]: Interpolants [22144#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 22145#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 22146#(or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)), 22147#(or GateController_alarm (<= (+ GateController_time 380) GateController_thousand)), 22148#(or GateController_alarm (<= (+ GateController_time 370) GateController_thousand)), 22149#(or (<= (+ GateController_time 360) GateController_thousand) GateController_alarm), 22150#(or (<= (+ GateController_time 350) GateController_thousand) GateController_alarm), 22151#(or GateController_alarm (<= (+ GateController_time 340) GateController_thousand)), 22152#(or (<= (+ GateController_time 330) GateController_thousand) GateController_alarm), 22153#(or GateController_alarm (<= (+ GateController_time 320) GateController_thousand)), 22154#(or GateController_alarm (<= (+ GateController_time 310) GateController_thousand)), 22155#(or GateController_alarm (<= (+ GateController_time 300) GateController_thousand)), 22156#(or GateController_alarm (<= (+ GateController_time 290) GateController_thousand)), 22157#(or GateController_alarm (<= (+ GateController_time 280) GateController_thousand)), 22158#(or (<= (+ GateController_time 270) GateController_thousand) GateController_alarm), 22159#(or GateController_alarm (<= (+ GateController_time 260) GateController_thousand)), 22160#(or GateController_alarm (<= (+ GateController_time 250) GateController_thousand)), 22161#(or GateController_alarm (<= (+ GateController_time 240) GateController_thousand)), 22162#(or GateController_alarm (<= (+ GateController_time 230) GateController_thousand)), 22163#(or GateController_alarm (<= (+ GateController_time 220) GateController_thousand)), 22164#(or GateController_alarm (<= (+ GateController_time 210) GateController_thousand)), 22165#(or GateController_alarm (<= (+ GateController_time 200) GateController_thousand)), 22166#(or (<= (+ GateController_time 190) GateController_thousand) GateController_alarm), 22167#(or GateController_alarm (<= (+ GateController_time 180) GateController_thousand)), 22168#(or GateController_alarm (<= (+ GateController_time 170) GateController_thousand)), 22169#(or GateController_alarm (<= (+ GateController_time 160) GateController_thousand)), 22170#(or GateController_alarm (<= (+ GateController_time 150) GateController_thousand)), 22171#(or (<= (+ GateController_time 140) GateController_thousand) GateController_alarm), 22172#(or GateController_alarm (<= (+ GateController_time 130) GateController_thousand)), 22173#(or GateController_alarm (<= (+ GateController_time 120) GateController_thousand)), 22174#(or GateController_alarm (<= (+ GateController_time 110) GateController_thousand)), 22175#GateController_alarm, 22083#true, 22084#false, 22085#(<= (+ GateController_time 1000) GateController_thousand), 22086#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 22087#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 22088#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 22089#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 22090#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 22091#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 22092#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 22093#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 22094#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 22095#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 22096#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 22097#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 22098#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 22099#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 22100#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 22101#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 22102#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 22103#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 22104#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 22105#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 22106#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 22107#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 22108#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 22109#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 22110#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 22111#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 22112#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 22113#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 22114#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 22115#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 22116#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 22117#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 22118#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 22119#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 22120#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 22121#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 22122#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 22123#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 22124#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 22125#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 22126#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 22127#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 22128#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 22129#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 22130#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 22131#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 22132#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 22133#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 22134#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 22135#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 22136#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 22137#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 22138#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 22139#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 22140#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 22141#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 22142#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 22143#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm)] [2018-07-23 13:37:01,264 INFO L134 CoverageAnalysis]: Checked inductivity of 4005 backedges. 0 proven. 4005 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:37:01,264 INFO L450 AbstractCegarLoop]: Interpolant automaton has 93 states [2018-07-23 13:37:01,264 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 93 interpolants. [2018-07-23 13:37:01,265 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=4277, Invalid=4279, Unknown=0, NotChecked=0, Total=8556 [2018-07-23 13:37:01,265 INFO L87 Difference]: Start difference. First operand 93 states and 93 transitions. Second operand 93 states. [2018-07-23 13:37:01,314 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:37:01,314 INFO L93 Difference]: Finished difference Result 96 states and 96 transitions. [2018-07-23 13:37:01,314 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 93 states. [2018-07-23 13:37:01,314 INFO L78 Accepts]: Start accepts. Automaton has 93 states. Word has length 92 [2018-07-23 13:37:01,314 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:37:01,315 INFO L225 Difference]: With dead ends: 96 [2018-07-23 13:37:01,315 INFO L226 Difference]: Without dead ends: 94 [2018-07-23 13:37:01,316 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 91 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 91 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 177 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=4277, Invalid=4279, Unknown=0, NotChecked=0, Total=8556 [2018-07-23 13:37:01,316 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94 states. [2018-07-23 13:37:01,321 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94 to 94. [2018-07-23 13:37:01,321 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 94 states. [2018-07-23 13:37:01,321 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94 states to 94 states and 94 transitions. [2018-07-23 13:37:01,321 INFO L78 Accepts]: Start accepts. Automaton has 94 states and 94 transitions. Word has length 92 [2018-07-23 13:37:01,322 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:37:01,322 INFO L471 AbstractCegarLoop]: Abstraction has 94 states and 94 transitions. [2018-07-23 13:37:01,322 INFO L472 AbstractCegarLoop]: Interpolant automaton has 93 states. [2018-07-23 13:37:01,322 INFO L276 IsEmpty]: Start isEmpty. Operand 94 states and 94 transitions. [2018-07-23 13:37:01,322 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-07-23 13:37:01,323 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:37:01,323 INFO L357 BasicCegarLoop]: trace histogram [90, 1, 1, 1] [2018-07-23 13:37:01,323 INFO L414 AbstractCegarLoop]: === Iteration 91 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:37:01,323 INFO L82 PathProgramCache]: Analyzing trace with hash -1251242272, now seen corresponding path program 90 times [2018-07-23 13:37:01,323 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:37:01,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:37:01,774 INFO L134 CoverageAnalysis]: Checked inductivity of 4095 backedges. 0 proven. 4095 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:37:01,774 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:37:01,775 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [92] total 92 [2018-07-23 13:37:01,775 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:37:01,775 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:37:01,775 INFO L185 omatonBuilderFactory]: Interpolants [22556#true, 22557#false, 22558#(<= (+ GateController_time 1000) GateController_thousand), 22559#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 22560#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 22561#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 22562#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 22563#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 22564#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 22565#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 22566#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 22567#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 22568#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 22569#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 22570#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 22571#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 22572#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 22573#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 22574#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 22575#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 22576#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 22577#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 22578#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 22579#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 22580#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 22581#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 22582#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 22583#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 22584#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 22585#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 22586#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 22587#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 22588#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 22589#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 22590#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 22591#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 22592#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 22593#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 22594#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 22595#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 22596#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 22597#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 22598#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 22599#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 22600#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 22601#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 22602#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 22603#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 22604#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 22605#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 22606#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 22607#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 22608#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 22609#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 22610#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 22611#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 22612#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 22613#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 22614#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 22615#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 22616#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 22617#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 22618#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 22619#(or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)), 22620#(or GateController_alarm (<= (+ GateController_time 380) GateController_thousand)), 22621#(or GateController_alarm (<= (+ GateController_time 370) GateController_thousand)), 22622#(or (<= (+ GateController_time 360) GateController_thousand) GateController_alarm), 22623#(or (<= (+ GateController_time 350) GateController_thousand) GateController_alarm), 22624#(or GateController_alarm (<= (+ GateController_time 340) GateController_thousand)), 22625#(or (<= (+ GateController_time 330) GateController_thousand) GateController_alarm), 22626#(or GateController_alarm (<= (+ GateController_time 320) GateController_thousand)), 22627#(or GateController_alarm (<= (+ GateController_time 310) GateController_thousand)), 22628#(or GateController_alarm (<= (+ GateController_time 300) GateController_thousand)), 22629#(or GateController_alarm (<= (+ GateController_time 290) GateController_thousand)), 22630#(or GateController_alarm (<= (+ GateController_time 280) GateController_thousand)), 22631#(or (<= (+ GateController_time 270) GateController_thousand) GateController_alarm), 22632#(or GateController_alarm (<= (+ GateController_time 260) GateController_thousand)), 22633#(or GateController_alarm (<= (+ GateController_time 250) GateController_thousand)), 22634#(or GateController_alarm (<= (+ GateController_time 240) GateController_thousand)), 22635#(or GateController_alarm (<= (+ GateController_time 230) GateController_thousand)), 22636#(or GateController_alarm (<= (+ GateController_time 220) GateController_thousand)), 22637#(or GateController_alarm (<= (+ GateController_time 210) GateController_thousand)), 22638#(or GateController_alarm (<= (+ GateController_time 200) GateController_thousand)), 22639#(or (<= (+ GateController_time 190) GateController_thousand) GateController_alarm), 22640#(or GateController_alarm (<= (+ GateController_time 180) GateController_thousand)), 22641#(or GateController_alarm (<= (+ GateController_time 170) GateController_thousand)), 22642#(or GateController_alarm (<= (+ GateController_time 160) GateController_thousand)), 22643#(or GateController_alarm (<= (+ GateController_time 150) GateController_thousand)), 22644#(or (<= (+ GateController_time 140) GateController_thousand) GateController_alarm), 22645#(or GateController_alarm (<= (+ GateController_time 130) GateController_thousand)), 22646#(or GateController_alarm (<= (+ GateController_time 120) GateController_thousand)), 22647#(or GateController_alarm (<= (+ GateController_time 110) GateController_thousand)), 22648#(or GateController_alarm (<= (+ GateController_time 100) GateController_thousand)), 22649#GateController_alarm] [2018-07-23 13:37:01,776 INFO L134 CoverageAnalysis]: Checked inductivity of 4095 backedges. 0 proven. 4095 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:37:01,776 INFO L450 AbstractCegarLoop]: Interpolant automaton has 94 states [2018-07-23 13:37:01,777 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 94 interpolants. [2018-07-23 13:37:01,778 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=4370, Invalid=4372, Unknown=0, NotChecked=0, Total=8742 [2018-07-23 13:37:01,778 INFO L87 Difference]: Start difference. First operand 94 states and 94 transitions. Second operand 94 states. [2018-07-23 13:37:01,864 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:37:01,864 INFO L93 Difference]: Finished difference Result 97 states and 97 transitions. [2018-07-23 13:37:01,864 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 94 states. [2018-07-23 13:37:01,864 INFO L78 Accepts]: Start accepts. Automaton has 94 states. Word has length 93 [2018-07-23 13:37:01,865 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:37:01,865 INFO L225 Difference]: With dead ends: 97 [2018-07-23 13:37:01,865 INFO L226 Difference]: Without dead ends: 95 [2018-07-23 13:37:01,866 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 92 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 92 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 179 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=4370, Invalid=4372, Unknown=0, NotChecked=0, Total=8742 [2018-07-23 13:37:01,866 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95 states. [2018-07-23 13:37:01,872 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95 to 95. [2018-07-23 13:37:01,872 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 95 states. [2018-07-23 13:37:01,872 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 95 transitions. [2018-07-23 13:37:01,873 INFO L78 Accepts]: Start accepts. Automaton has 95 states and 95 transitions. Word has length 93 [2018-07-23 13:37:01,873 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:37:01,873 INFO L471 AbstractCegarLoop]: Abstraction has 95 states and 95 transitions. [2018-07-23 13:37:01,873 INFO L472 AbstractCegarLoop]: Interpolant automaton has 94 states. [2018-07-23 13:37:01,873 INFO L276 IsEmpty]: Start isEmpty. Operand 95 states and 95 transitions. [2018-07-23 13:37:01,873 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-07-23 13:37:01,873 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:37:01,874 INFO L357 BasicCegarLoop]: trace histogram [91, 1, 1, 1] [2018-07-23 13:37:01,874 INFO L414 AbstractCegarLoop]: === Iteration 92 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:37:01,874 INFO L82 PathProgramCache]: Analyzing trace with hash -133795168, now seen corresponding path program 91 times [2018-07-23 13:37:01,874 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:37:01,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:37:02,351 INFO L134 CoverageAnalysis]: Checked inductivity of 4186 backedges. 0 proven. 4186 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:37:02,351 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:37:02,351 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [93] total 93 [2018-07-23 13:37:02,351 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:37:02,351 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:37:02,352 INFO L185 omatonBuilderFactory]: Interpolants [23040#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 23041#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 23042#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 23043#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 23044#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 23045#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 23046#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 23047#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 23048#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 23049#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 23050#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 23051#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 23052#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 23053#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 23054#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 23055#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 23056#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 23057#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 23058#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 23059#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 23060#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 23061#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 23062#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 23063#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 23064#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 23065#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 23066#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 23067#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 23068#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 23069#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 23070#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 23071#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 23072#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 23073#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 23074#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 23075#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 23076#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 23077#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 23078#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 23079#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 23080#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 23081#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 23082#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 23083#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 23084#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 23085#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 23086#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 23087#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 23088#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 23089#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 23090#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 23091#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 23092#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 23093#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 23094#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 23095#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 23096#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 23097#(or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)), 23098#(or GateController_alarm (<= (+ GateController_time 380) GateController_thousand)), 23099#(or GateController_alarm (<= (+ GateController_time 370) GateController_thousand)), 23100#(or (<= (+ GateController_time 360) GateController_thousand) GateController_alarm), 23101#(or (<= (+ GateController_time 350) GateController_thousand) GateController_alarm), 23102#(or GateController_alarm (<= (+ GateController_time 340) GateController_thousand)), 23103#(or (<= (+ GateController_time 330) GateController_thousand) GateController_alarm), 23104#(or GateController_alarm (<= (+ GateController_time 320) GateController_thousand)), 23105#(or GateController_alarm (<= (+ GateController_time 310) GateController_thousand)), 23106#(or GateController_alarm (<= (+ GateController_time 300) GateController_thousand)), 23107#(or GateController_alarm (<= (+ GateController_time 290) GateController_thousand)), 23108#(or GateController_alarm (<= (+ GateController_time 280) GateController_thousand)), 23109#(or (<= (+ GateController_time 270) GateController_thousand) GateController_alarm), 23110#(or GateController_alarm (<= (+ GateController_time 260) GateController_thousand)), 23111#(or GateController_alarm (<= (+ GateController_time 250) GateController_thousand)), 23112#(or GateController_alarm (<= (+ GateController_time 240) GateController_thousand)), 23113#(or GateController_alarm (<= (+ GateController_time 230) GateController_thousand)), 23114#(or GateController_alarm (<= (+ GateController_time 220) GateController_thousand)), 23115#(or GateController_alarm (<= (+ GateController_time 210) GateController_thousand)), 23116#(or GateController_alarm (<= (+ GateController_time 200) GateController_thousand)), 23117#(or (<= (+ GateController_time 190) GateController_thousand) GateController_alarm), 23118#(or GateController_alarm (<= (+ GateController_time 180) GateController_thousand)), 23119#(or GateController_alarm (<= (+ GateController_time 170) GateController_thousand)), 23120#(or GateController_alarm (<= (+ GateController_time 160) GateController_thousand)), 23121#(or GateController_alarm (<= (+ GateController_time 150) GateController_thousand)), 23122#(or (<= (+ GateController_time 140) GateController_thousand) GateController_alarm), 23123#(or GateController_alarm (<= (+ GateController_time 130) GateController_thousand)), 23124#(or GateController_alarm (<= (+ GateController_time 120) GateController_thousand)), 23125#(or GateController_alarm (<= (+ GateController_time 110) GateController_thousand)), 23126#(or GateController_alarm (<= (+ GateController_time 100) GateController_thousand)), 23127#(or GateController_alarm (<= (+ GateController_time 90) GateController_thousand)), 23128#GateController_alarm, 23034#true, 23035#false, 23036#(<= (+ GateController_time 1000) GateController_thousand), 23037#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 23038#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 23039#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand))] [2018-07-23 13:37:02,352 INFO L134 CoverageAnalysis]: Checked inductivity of 4186 backedges. 0 proven. 4186 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:37:02,353 INFO L450 AbstractCegarLoop]: Interpolant automaton has 95 states [2018-07-23 13:37:02,353 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 95 interpolants. [2018-07-23 13:37:02,354 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=4464, Invalid=4466, Unknown=0, NotChecked=0, Total=8930 [2018-07-23 13:37:02,354 INFO L87 Difference]: Start difference. First operand 95 states and 95 transitions. Second operand 95 states. [2018-07-23 13:37:02,459 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:37:02,459 INFO L93 Difference]: Finished difference Result 98 states and 98 transitions. [2018-07-23 13:37:02,459 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 95 states. [2018-07-23 13:37:02,459 INFO L78 Accepts]: Start accepts. Automaton has 95 states. Word has length 94 [2018-07-23 13:37:02,460 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:37:02,460 INFO L225 Difference]: With dead ends: 98 [2018-07-23 13:37:02,460 INFO L226 Difference]: Without dead ends: 96 [2018-07-23 13:37:02,461 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 93 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 93 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 181 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=4464, Invalid=4466, Unknown=0, NotChecked=0, Total=8930 [2018-07-23 13:37:02,461 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96 states. [2018-07-23 13:37:02,465 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96 to 96. [2018-07-23 13:37:02,465 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 96 states. [2018-07-23 13:37:02,466 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 96 states to 96 states and 96 transitions. [2018-07-23 13:37:02,466 INFO L78 Accepts]: Start accepts. Automaton has 96 states and 96 transitions. Word has length 94 [2018-07-23 13:37:02,466 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:37:02,466 INFO L471 AbstractCegarLoop]: Abstraction has 96 states and 96 transitions. [2018-07-23 13:37:02,466 INFO L472 AbstractCegarLoop]: Interpolant automaton has 95 states. [2018-07-23 13:37:02,466 INFO L276 IsEmpty]: Start isEmpty. Operand 96 states and 96 transitions. [2018-07-23 13:37:02,467 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2018-07-23 13:37:02,467 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:37:02,467 INFO L357 BasicCegarLoop]: trace histogram [92, 1, 1, 1] [2018-07-23 13:37:02,467 INFO L414 AbstractCegarLoop]: === Iteration 93 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:37:02,467 INFO L82 PathProgramCache]: Analyzing trace with hash 147326688, now seen corresponding path program 92 times [2018-07-23 13:37:02,467 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:37:02,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:37:02,970 INFO L134 CoverageAnalysis]: Checked inductivity of 4278 backedges. 0 proven. 4278 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:37:02,970 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:37:02,970 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [94] total 94 [2018-07-23 13:37:02,970 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:37:02,971 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:37:02,971 INFO L185 omatonBuilderFactory]: Interpolants [23552#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 23553#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 23554#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 23555#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 23556#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 23557#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 23558#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 23559#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 23560#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 23561#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 23562#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 23563#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 23564#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 23565#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 23566#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 23567#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 23568#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 23569#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 23570#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 23571#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 23572#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 23573#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 23574#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 23575#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 23576#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 23577#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 23578#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 23579#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 23580#(or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)), 23581#(or GateController_alarm (<= (+ GateController_time 380) GateController_thousand)), 23582#(or GateController_alarm (<= (+ GateController_time 370) GateController_thousand)), 23583#(or (<= (+ GateController_time 360) GateController_thousand) GateController_alarm), 23584#(or (<= (+ GateController_time 350) GateController_thousand) GateController_alarm), 23585#(or GateController_alarm (<= (+ GateController_time 340) GateController_thousand)), 23586#(or (<= (+ GateController_time 330) GateController_thousand) GateController_alarm), 23587#(or GateController_alarm (<= (+ GateController_time 320) GateController_thousand)), 23588#(or GateController_alarm (<= (+ GateController_time 310) GateController_thousand)), 23589#(or GateController_alarm (<= (+ GateController_time 300) GateController_thousand)), 23590#(or GateController_alarm (<= (+ GateController_time 290) GateController_thousand)), 23591#(or GateController_alarm (<= (+ GateController_time 280) GateController_thousand)), 23592#(or (<= (+ GateController_time 270) GateController_thousand) GateController_alarm), 23593#(or GateController_alarm (<= (+ GateController_time 260) GateController_thousand)), 23594#(or GateController_alarm (<= (+ GateController_time 250) GateController_thousand)), 23595#(or GateController_alarm (<= (+ GateController_time 240) GateController_thousand)), 23596#(or GateController_alarm (<= (+ GateController_time 230) GateController_thousand)), 23597#(or GateController_alarm (<= (+ GateController_time 220) GateController_thousand)), 23598#(or GateController_alarm (<= (+ GateController_time 210) GateController_thousand)), 23599#(or GateController_alarm (<= (+ GateController_time 200) GateController_thousand)), 23600#(or (<= (+ GateController_time 190) GateController_thousand) GateController_alarm), 23601#(or GateController_alarm (<= (+ GateController_time 180) GateController_thousand)), 23602#(or GateController_alarm (<= (+ GateController_time 170) GateController_thousand)), 23603#(or GateController_alarm (<= (+ GateController_time 160) GateController_thousand)), 23604#(or GateController_alarm (<= (+ GateController_time 150) GateController_thousand)), 23605#(or (<= (+ GateController_time 140) GateController_thousand) GateController_alarm), 23606#(or GateController_alarm (<= (+ GateController_time 130) GateController_thousand)), 23607#(or GateController_alarm (<= (+ GateController_time 120) GateController_thousand)), 23608#(or GateController_alarm (<= (+ GateController_time 110) GateController_thousand)), 23609#(or GateController_alarm (<= (+ GateController_time 100) GateController_thousand)), 23610#(or GateController_alarm (<= (+ GateController_time 90) GateController_thousand)), 23611#(or GateController_alarm (<= (+ GateController_time 80) GateController_thousand)), 23612#GateController_alarm, 23517#true, 23518#false, 23519#(<= (+ GateController_time 1000) GateController_thousand), 23520#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 23521#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 23522#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 23523#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 23524#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 23525#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 23526#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 23527#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 23528#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 23529#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 23530#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 23531#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 23532#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 23533#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 23534#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 23535#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 23536#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 23537#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 23538#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 23539#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 23540#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 23541#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 23542#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 23543#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 23544#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 23545#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 23546#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 23547#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 23548#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 23549#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 23550#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 23551#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm)] [2018-07-23 13:37:02,971 INFO L134 CoverageAnalysis]: Checked inductivity of 4278 backedges. 0 proven. 4278 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:37:02,972 INFO L450 AbstractCegarLoop]: Interpolant automaton has 96 states [2018-07-23 13:37:02,972 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 96 interpolants. [2018-07-23 13:37:02,973 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=4559, Invalid=4561, Unknown=0, NotChecked=0, Total=9120 [2018-07-23 13:37:02,973 INFO L87 Difference]: Start difference. First operand 96 states and 96 transitions. Second operand 96 states. [2018-07-23 13:37:03,044 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:37:03,044 INFO L93 Difference]: Finished difference Result 99 states and 99 transitions. [2018-07-23 13:37:03,044 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2018-07-23 13:37:03,044 INFO L78 Accepts]: Start accepts. Automaton has 96 states. Word has length 95 [2018-07-23 13:37:03,045 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:37:03,045 INFO L225 Difference]: With dead ends: 99 [2018-07-23 13:37:03,046 INFO L226 Difference]: Without dead ends: 97 [2018-07-23 13:37:03,046 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 94 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 94 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 183 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=4559, Invalid=4561, Unknown=0, NotChecked=0, Total=9120 [2018-07-23 13:37:03,047 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states. [2018-07-23 13:37:03,053 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 97. [2018-07-23 13:37:03,053 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 97 states. [2018-07-23 13:37:03,053 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 97 transitions. [2018-07-23 13:37:03,054 INFO L78 Accepts]: Start accepts. Automaton has 97 states and 97 transitions. Word has length 95 [2018-07-23 13:37:03,054 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:37:03,054 INFO L471 AbstractCegarLoop]: Abstraction has 97 states and 97 transitions. [2018-07-23 13:37:03,054 INFO L472 AbstractCegarLoop]: Interpolant automaton has 96 states. [2018-07-23 13:37:03,054 INFO L276 IsEmpty]: Start isEmpty. Operand 97 states and 97 transitions. [2018-07-23 13:37:03,055 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-07-23 13:37:03,055 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:37:03,055 INFO L357 BasicCegarLoop]: trace histogram [93, 1, 1, 1] [2018-07-23 13:37:03,055 INFO L414 AbstractCegarLoop]: === Iteration 94 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:37:03,055 INFO L82 PathProgramCache]: Analyzing trace with hash 272169632, now seen corresponding path program 93 times [2018-07-23 13:37:03,056 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:37:03,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:37:03,621 INFO L134 CoverageAnalysis]: Checked inductivity of 4371 backedges. 0 proven. 4371 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:37:03,622 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:37:03,622 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [95] total 95 [2018-07-23 13:37:03,622 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:37:03,622 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:37:03,622 INFO L185 omatonBuilderFactory]: Interpolants [24064#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 24065#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 24066#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 24067#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 24068#(or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)), 24069#(or GateController_alarm (<= (+ GateController_time 380) GateController_thousand)), 24070#(or GateController_alarm (<= (+ GateController_time 370) GateController_thousand)), 24071#(or (<= (+ GateController_time 360) GateController_thousand) GateController_alarm), 24072#(or (<= (+ GateController_time 350) GateController_thousand) GateController_alarm), 24073#(or GateController_alarm (<= (+ GateController_time 340) GateController_thousand)), 24074#(or (<= (+ GateController_time 330) GateController_thousand) GateController_alarm), 24075#(or GateController_alarm (<= (+ GateController_time 320) GateController_thousand)), 24076#(or GateController_alarm (<= (+ GateController_time 310) GateController_thousand)), 24077#(or GateController_alarm (<= (+ GateController_time 300) GateController_thousand)), 24078#(or GateController_alarm (<= (+ GateController_time 290) GateController_thousand)), 24079#(or GateController_alarm (<= (+ GateController_time 280) GateController_thousand)), 24080#(or (<= (+ GateController_time 270) GateController_thousand) GateController_alarm), 24081#(or GateController_alarm (<= (+ GateController_time 260) GateController_thousand)), 24082#(or GateController_alarm (<= (+ GateController_time 250) GateController_thousand)), 24083#(or GateController_alarm (<= (+ GateController_time 240) GateController_thousand)), 24084#(or GateController_alarm (<= (+ GateController_time 230) GateController_thousand)), 24085#(or GateController_alarm (<= (+ GateController_time 220) GateController_thousand)), 24086#(or GateController_alarm (<= (+ GateController_time 210) GateController_thousand)), 24087#(or GateController_alarm (<= (+ GateController_time 200) GateController_thousand)), 24088#(or (<= (+ GateController_time 190) GateController_thousand) GateController_alarm), 24089#(or GateController_alarm (<= (+ GateController_time 180) GateController_thousand)), 24090#(or GateController_alarm (<= (+ GateController_time 170) GateController_thousand)), 24091#(or GateController_alarm (<= (+ GateController_time 160) GateController_thousand)), 24092#(or GateController_alarm (<= (+ GateController_time 150) GateController_thousand)), 24093#(or (<= (+ GateController_time 140) GateController_thousand) GateController_alarm), 24094#(or GateController_alarm (<= (+ GateController_time 130) GateController_thousand)), 24095#(or GateController_alarm (<= (+ GateController_time 120) GateController_thousand)), 24096#(or GateController_alarm (<= (+ GateController_time 110) GateController_thousand)), 24097#(or GateController_alarm (<= (+ GateController_time 100) GateController_thousand)), 24098#(or GateController_alarm (<= (+ GateController_time 90) GateController_thousand)), 24099#(or GateController_alarm (<= (+ GateController_time 80) GateController_thousand)), 24100#(or GateController_alarm (<= (+ GateController_time 70) GateController_thousand)), 24101#GateController_alarm, 24005#true, 24006#false, 24007#(<= (+ GateController_time 1000) GateController_thousand), 24008#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 24009#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 24010#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 24011#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 24012#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 24013#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 24014#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 24015#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 24016#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 24017#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 24018#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 24019#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 24020#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 24021#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 24022#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 24023#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 24024#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 24025#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 24026#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 24027#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 24028#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 24029#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 24030#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 24031#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 24032#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 24033#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 24034#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 24035#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 24036#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 24037#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 24038#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 24039#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 24040#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 24041#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 24042#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 24043#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 24044#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 24045#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 24046#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 24047#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 24048#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 24049#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 24050#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 24051#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 24052#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 24053#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 24054#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 24055#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 24056#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 24057#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 24058#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 24059#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 24060#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 24061#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 24062#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 24063#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand))] [2018-07-23 13:37:03,623 INFO L134 CoverageAnalysis]: Checked inductivity of 4371 backedges. 0 proven. 4371 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:37:03,623 INFO L450 AbstractCegarLoop]: Interpolant automaton has 97 states [2018-07-23 13:37:03,623 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2018-07-23 13:37:03,624 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=4655, Invalid=4657, Unknown=0, NotChecked=0, Total=9312 [2018-07-23 13:37:03,624 INFO L87 Difference]: Start difference. First operand 97 states and 97 transitions. Second operand 97 states. [2018-07-23 13:37:03,676 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:37:03,676 INFO L93 Difference]: Finished difference Result 100 states and 100 transitions. [2018-07-23 13:37:03,676 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 97 states. [2018-07-23 13:37:03,676 INFO L78 Accepts]: Start accepts. Automaton has 97 states. Word has length 96 [2018-07-23 13:37:03,676 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:37:03,677 INFO L225 Difference]: With dead ends: 100 [2018-07-23 13:37:03,677 INFO L226 Difference]: Without dead ends: 98 [2018-07-23 13:37:03,677 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 95 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 95 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 185 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=4655, Invalid=4657, Unknown=0, NotChecked=0, Total=9312 [2018-07-23 13:37:03,678 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98 states. [2018-07-23 13:37:03,683 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98 to 98. [2018-07-23 13:37:03,683 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 98 states. [2018-07-23 13:37:03,683 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98 states to 98 states and 98 transitions. [2018-07-23 13:37:03,683 INFO L78 Accepts]: Start accepts. Automaton has 98 states and 98 transitions. Word has length 96 [2018-07-23 13:37:03,683 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:37:03,684 INFO L471 AbstractCegarLoop]: Abstraction has 98 states and 98 transitions. [2018-07-23 13:37:03,684 INFO L472 AbstractCegarLoop]: Interpolant automaton has 97 states. [2018-07-23 13:37:03,684 INFO L276 IsEmpty]: Start isEmpty. Operand 98 states and 98 transitions. [2018-07-23 13:37:03,684 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2018-07-23 13:37:03,684 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:37:03,684 INFO L357 BasicCegarLoop]: trace histogram [94, 1, 1, 1] [2018-07-23 13:37:03,684 INFO L414 AbstractCegarLoop]: === Iteration 95 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:37:03,685 INFO L82 PathProgramCache]: Analyzing trace with hash -152666400, now seen corresponding path program 94 times [2018-07-23 13:37:03,685 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:37:03,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:37:04,194 INFO L134 CoverageAnalysis]: Checked inductivity of 4465 backedges. 0 proven. 4465 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:37:04,195 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:37:04,195 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [96] total 96 [2018-07-23 13:37:04,195 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:37:04,195 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:37:04,195 INFO L185 omatonBuilderFactory]: Interpolants [24576#(or GateController_alarm (<= (+ GateController_time 240) GateController_thousand)), 24577#(or GateController_alarm (<= (+ GateController_time 230) GateController_thousand)), 24578#(or GateController_alarm (<= (+ GateController_time 220) GateController_thousand)), 24579#(or GateController_alarm (<= (+ GateController_time 210) GateController_thousand)), 24580#(or GateController_alarm (<= (+ GateController_time 200) GateController_thousand)), 24581#(or (<= (+ GateController_time 190) GateController_thousand) GateController_alarm), 24582#(or GateController_alarm (<= (+ GateController_time 180) GateController_thousand)), 24583#(or GateController_alarm (<= (+ GateController_time 170) GateController_thousand)), 24584#(or GateController_alarm (<= (+ GateController_time 160) GateController_thousand)), 24585#(or GateController_alarm (<= (+ GateController_time 150) GateController_thousand)), 24586#(or (<= (+ GateController_time 140) GateController_thousand) GateController_alarm), 24587#(or GateController_alarm (<= (+ GateController_time 130) GateController_thousand)), 24588#(or GateController_alarm (<= (+ GateController_time 120) GateController_thousand)), 24589#(or GateController_alarm (<= (+ GateController_time 110) GateController_thousand)), 24590#(or GateController_alarm (<= (+ GateController_time 100) GateController_thousand)), 24591#(or GateController_alarm (<= (+ GateController_time 90) GateController_thousand)), 24592#(or GateController_alarm (<= (+ GateController_time 80) GateController_thousand)), 24593#(or GateController_alarm (<= (+ GateController_time 70) GateController_thousand)), 24594#(or GateController_alarm (<= (+ GateController_time 60) GateController_thousand)), 24595#GateController_alarm, 24498#true, 24499#false, 24500#(<= (+ GateController_time 1000) GateController_thousand), 24501#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 24502#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 24503#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 24504#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 24505#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 24506#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 24507#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 24508#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 24509#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 24510#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 24511#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 24512#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 24513#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 24514#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 24515#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 24516#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 24517#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 24518#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 24519#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 24520#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 24521#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 24522#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 24523#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 24524#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 24525#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 24526#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 24527#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 24528#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 24529#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 24530#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 24531#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 24532#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 24533#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 24534#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 24535#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 24536#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 24537#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 24538#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 24539#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 24540#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 24541#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 24542#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 24543#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 24544#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 24545#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 24546#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 24547#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 24548#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 24549#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 24550#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 24551#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 24552#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 24553#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 24554#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 24555#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 24556#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 24557#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 24558#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 24559#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 24560#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 24561#(or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)), 24562#(or GateController_alarm (<= (+ GateController_time 380) GateController_thousand)), 24563#(or GateController_alarm (<= (+ GateController_time 370) GateController_thousand)), 24564#(or (<= (+ GateController_time 360) GateController_thousand) GateController_alarm), 24565#(or (<= (+ GateController_time 350) GateController_thousand) GateController_alarm), 24566#(or GateController_alarm (<= (+ GateController_time 340) GateController_thousand)), 24567#(or (<= (+ GateController_time 330) GateController_thousand) GateController_alarm), 24568#(or GateController_alarm (<= (+ GateController_time 320) GateController_thousand)), 24569#(or GateController_alarm (<= (+ GateController_time 310) GateController_thousand)), 24570#(or GateController_alarm (<= (+ GateController_time 300) GateController_thousand)), 24571#(or GateController_alarm (<= (+ GateController_time 290) GateController_thousand)), 24572#(or GateController_alarm (<= (+ GateController_time 280) GateController_thousand)), 24573#(or (<= (+ GateController_time 270) GateController_thousand) GateController_alarm), 24574#(or GateController_alarm (<= (+ GateController_time 260) GateController_thousand)), 24575#(or GateController_alarm (<= (+ GateController_time 250) GateController_thousand))] [2018-07-23 13:37:04,196 INFO L134 CoverageAnalysis]: Checked inductivity of 4465 backedges. 0 proven. 4465 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:37:04,196 INFO L450 AbstractCegarLoop]: Interpolant automaton has 98 states [2018-07-23 13:37:04,197 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 98 interpolants. [2018-07-23 13:37:04,198 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=4752, Invalid=4754, Unknown=0, NotChecked=0, Total=9506 [2018-07-23 13:37:04,198 INFO L87 Difference]: Start difference. First operand 98 states and 98 transitions. Second operand 98 states. [2018-07-23 13:37:04,269 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:37:04,269 INFO L93 Difference]: Finished difference Result 101 states and 101 transitions. [2018-07-23 13:37:04,269 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 98 states. [2018-07-23 13:37:04,270 INFO L78 Accepts]: Start accepts. Automaton has 98 states. Word has length 97 [2018-07-23 13:37:04,270 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:37:04,270 INFO L225 Difference]: With dead ends: 101 [2018-07-23 13:37:04,270 INFO L226 Difference]: Without dead ends: 99 [2018-07-23 13:37:04,271 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 96 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 96 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 187 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=4752, Invalid=4754, Unknown=0, NotChecked=0, Total=9506 [2018-07-23 13:37:04,271 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states. [2018-07-23 13:37:04,277 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 99. [2018-07-23 13:37:04,277 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 99 states. [2018-07-23 13:37:04,278 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 99 transitions. [2018-07-23 13:37:04,278 INFO L78 Accepts]: Start accepts. Automaton has 99 states and 99 transitions. Word has length 97 [2018-07-23 13:37:04,278 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:37:04,278 INFO L471 AbstractCegarLoop]: Abstraction has 99 states and 99 transitions. [2018-07-23 13:37:04,278 INFO L472 AbstractCegarLoop]: Interpolant automaton has 98 states. [2018-07-23 13:37:04,278 INFO L276 IsEmpty]: Start isEmpty. Operand 99 states and 99 transitions. [2018-07-23 13:37:04,279 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2018-07-23 13:37:04,279 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:37:04,279 INFO L357 BasicCegarLoop]: trace histogram [95, 1, 1, 1] [2018-07-23 13:37:04,279 INFO L414 AbstractCegarLoop]: === Iteration 96 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:37:04,279 INFO L82 PathProgramCache]: Analyzing trace with hash -437681504, now seen corresponding path program 95 times [2018-07-23 13:37:04,279 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:37:04,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:37:04,757 INFO L134 CoverageAnalysis]: Checked inductivity of 4560 backedges. 0 proven. 4560 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:37:04,757 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:37:04,757 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [97] total 97 [2018-07-23 13:37:04,758 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:37:04,758 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:37:04,758 INFO L185 omatonBuilderFactory]: Interpolants [25088#(or GateController_alarm (<= (+ GateController_time 100) GateController_thousand)), 25089#(or GateController_alarm (<= (+ GateController_time 90) GateController_thousand)), 25090#(or GateController_alarm (<= (+ GateController_time 80) GateController_thousand)), 25091#(or GateController_alarm (<= (+ GateController_time 70) GateController_thousand)), 25092#(or GateController_alarm (<= (+ GateController_time 60) GateController_thousand)), 25093#(or GateController_alarm (<= (+ GateController_time 50) GateController_thousand)), 25094#GateController_alarm, 24996#true, 24997#false, 24998#(<= (+ GateController_time 1000) GateController_thousand), 24999#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 25000#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 25001#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 25002#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 25003#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 25004#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 25005#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 25006#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 25007#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 25008#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 25009#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 25010#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 25011#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 25012#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 25013#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 25014#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 25015#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 25016#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 25017#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 25018#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 25019#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 25020#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 25021#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 25022#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 25023#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 25024#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 25025#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 25026#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 25027#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 25028#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 25029#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 25030#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 25031#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 25032#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 25033#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 25034#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 25035#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 25036#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 25037#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 25038#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 25039#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 25040#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 25041#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 25042#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 25043#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 25044#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 25045#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 25046#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 25047#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 25048#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 25049#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 25050#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 25051#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 25052#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 25053#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 25054#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 25055#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 25056#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 25057#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 25058#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 25059#(or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)), 25060#(or GateController_alarm (<= (+ GateController_time 380) GateController_thousand)), 25061#(or GateController_alarm (<= (+ GateController_time 370) GateController_thousand)), 25062#(or (<= (+ GateController_time 360) GateController_thousand) GateController_alarm), 25063#(or (<= (+ GateController_time 350) GateController_thousand) GateController_alarm), 25064#(or GateController_alarm (<= (+ GateController_time 340) GateController_thousand)), 25065#(or (<= (+ GateController_time 330) GateController_thousand) GateController_alarm), 25066#(or GateController_alarm (<= (+ GateController_time 320) GateController_thousand)), 25067#(or GateController_alarm (<= (+ GateController_time 310) GateController_thousand)), 25068#(or GateController_alarm (<= (+ GateController_time 300) GateController_thousand)), 25069#(or GateController_alarm (<= (+ GateController_time 290) GateController_thousand)), 25070#(or GateController_alarm (<= (+ GateController_time 280) GateController_thousand)), 25071#(or (<= (+ GateController_time 270) GateController_thousand) GateController_alarm), 25072#(or GateController_alarm (<= (+ GateController_time 260) GateController_thousand)), 25073#(or GateController_alarm (<= (+ GateController_time 250) GateController_thousand)), 25074#(or GateController_alarm (<= (+ GateController_time 240) GateController_thousand)), 25075#(or GateController_alarm (<= (+ GateController_time 230) GateController_thousand)), 25076#(or GateController_alarm (<= (+ GateController_time 220) GateController_thousand)), 25077#(or GateController_alarm (<= (+ GateController_time 210) GateController_thousand)), 25078#(or GateController_alarm (<= (+ GateController_time 200) GateController_thousand)), 25079#(or (<= (+ GateController_time 190) GateController_thousand) GateController_alarm), 25080#(or GateController_alarm (<= (+ GateController_time 180) GateController_thousand)), 25081#(or GateController_alarm (<= (+ GateController_time 170) GateController_thousand)), 25082#(or GateController_alarm (<= (+ GateController_time 160) GateController_thousand)), 25083#(or GateController_alarm (<= (+ GateController_time 150) GateController_thousand)), 25084#(or (<= (+ GateController_time 140) GateController_thousand) GateController_alarm), 25085#(or GateController_alarm (<= (+ GateController_time 130) GateController_thousand)), 25086#(or GateController_alarm (<= (+ GateController_time 120) GateController_thousand)), 25087#(or GateController_alarm (<= (+ GateController_time 110) GateController_thousand))] [2018-07-23 13:37:04,759 INFO L134 CoverageAnalysis]: Checked inductivity of 4560 backedges. 0 proven. 4560 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:37:04,759 INFO L450 AbstractCegarLoop]: Interpolant automaton has 99 states [2018-07-23 13:37:04,760 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 99 interpolants. [2018-07-23 13:37:04,761 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=4850, Invalid=4852, Unknown=0, NotChecked=0, Total=9702 [2018-07-23 13:37:04,761 INFO L87 Difference]: Start difference. First operand 99 states and 99 transitions. Second operand 99 states. [2018-07-23 13:37:04,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:37:04,849 INFO L93 Difference]: Finished difference Result 102 states and 102 transitions. [2018-07-23 13:37:04,849 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 99 states. [2018-07-23 13:37:04,849 INFO L78 Accepts]: Start accepts. Automaton has 99 states. Word has length 98 [2018-07-23 13:37:04,849 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:37:04,850 INFO L225 Difference]: With dead ends: 102 [2018-07-23 13:37:04,850 INFO L226 Difference]: Without dead ends: 100 [2018-07-23 13:37:04,851 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 97 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 97 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 189 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=4850, Invalid=4852, Unknown=0, NotChecked=0, Total=9702 [2018-07-23 13:37:04,851 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states. [2018-07-23 13:37:04,855 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 100. [2018-07-23 13:37:04,855 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 100 states. [2018-07-23 13:37:04,856 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100 states to 100 states and 100 transitions. [2018-07-23 13:37:04,856 INFO L78 Accepts]: Start accepts. Automaton has 100 states and 100 transitions. Word has length 98 [2018-07-23 13:37:04,856 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:37:04,856 INFO L471 AbstractCegarLoop]: Abstraction has 100 states and 100 transitions. [2018-07-23 13:37:04,856 INFO L472 AbstractCegarLoop]: Interpolant automaton has 99 states. [2018-07-23 13:37:04,856 INFO L276 IsEmpty]: Start isEmpty. Operand 100 states and 100 transitions. [2018-07-23 13:37:04,857 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-07-23 13:37:04,857 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:37:04,857 INFO L357 BasicCegarLoop]: trace histogram [96, 1, 1, 1] [2018-07-23 13:37:04,857 INFO L414 AbstractCegarLoop]: === Iteration 97 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:37:04,857 INFO L82 PathProgramCache]: Analyzing trace with hash -683215136, now seen corresponding path program 96 times [2018-07-23 13:37:04,857 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:37:04,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:37:05,341 INFO L134 CoverageAnalysis]: Checked inductivity of 4656 backedges. 0 proven. 4656 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:37:05,341 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:37:05,341 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [98] total 98 [2018-07-23 13:37:05,341 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:37:05,341 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:37:05,342 INFO L185 omatonBuilderFactory]: Interpolants [25499#true, 25500#false, 25501#(<= (+ GateController_time 1000) GateController_thousand), 25502#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 25503#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 25504#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 25505#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 25506#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 25507#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 25508#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 25509#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 25510#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 25511#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 25512#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 25513#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 25514#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 25515#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 25516#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 25517#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 25518#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 25519#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 25520#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 25521#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 25522#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 25523#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 25524#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 25525#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 25526#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 25527#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 25528#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 25529#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 25530#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 25531#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 25532#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 25533#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 25534#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 25535#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 25536#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 25537#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 25538#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 25539#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 25540#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 25541#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 25542#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 25543#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 25544#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 25545#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 25546#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 25547#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 25548#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 25549#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 25550#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 25551#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 25552#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 25553#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 25554#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 25555#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 25556#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 25557#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 25558#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 25559#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 25560#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 25561#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 25562#(or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)), 25563#(or GateController_alarm (<= (+ GateController_time 380) GateController_thousand)), 25564#(or GateController_alarm (<= (+ GateController_time 370) GateController_thousand)), 25565#(or (<= (+ GateController_time 360) GateController_thousand) GateController_alarm), 25566#(or (<= (+ GateController_time 350) GateController_thousand) GateController_alarm), 25567#(or GateController_alarm (<= (+ GateController_time 340) GateController_thousand)), 25568#(or (<= (+ GateController_time 330) GateController_thousand) GateController_alarm), 25569#(or GateController_alarm (<= (+ GateController_time 320) GateController_thousand)), 25570#(or GateController_alarm (<= (+ GateController_time 310) GateController_thousand)), 25571#(or GateController_alarm (<= (+ GateController_time 300) GateController_thousand)), 25572#(or GateController_alarm (<= (+ GateController_time 290) GateController_thousand)), 25573#(or GateController_alarm (<= (+ GateController_time 280) GateController_thousand)), 25574#(or (<= (+ GateController_time 270) GateController_thousand) GateController_alarm), 25575#(or GateController_alarm (<= (+ GateController_time 260) GateController_thousand)), 25576#(or GateController_alarm (<= (+ GateController_time 250) GateController_thousand)), 25577#(or GateController_alarm (<= (+ GateController_time 240) GateController_thousand)), 25578#(or GateController_alarm (<= (+ GateController_time 230) GateController_thousand)), 25579#(or GateController_alarm (<= (+ GateController_time 220) GateController_thousand)), 25580#(or GateController_alarm (<= (+ GateController_time 210) GateController_thousand)), 25581#(or GateController_alarm (<= (+ GateController_time 200) GateController_thousand)), 25582#(or (<= (+ GateController_time 190) GateController_thousand) GateController_alarm), 25583#(or GateController_alarm (<= (+ GateController_time 180) GateController_thousand)), 25584#(or GateController_alarm (<= (+ GateController_time 170) GateController_thousand)), 25585#(or GateController_alarm (<= (+ GateController_time 160) GateController_thousand)), 25586#(or GateController_alarm (<= (+ GateController_time 150) GateController_thousand)), 25587#(or (<= (+ GateController_time 140) GateController_thousand) GateController_alarm), 25588#(or GateController_alarm (<= (+ GateController_time 130) GateController_thousand)), 25589#(or GateController_alarm (<= (+ GateController_time 120) GateController_thousand)), 25590#(or GateController_alarm (<= (+ GateController_time 110) GateController_thousand)), 25591#(or GateController_alarm (<= (+ GateController_time 100) GateController_thousand)), 25592#(or GateController_alarm (<= (+ GateController_time 90) GateController_thousand)), 25593#(or GateController_alarm (<= (+ GateController_time 80) GateController_thousand)), 25594#(or GateController_alarm (<= (+ GateController_time 70) GateController_thousand)), 25595#(or GateController_alarm (<= (+ GateController_time 60) GateController_thousand)), 25596#(or GateController_alarm (<= (+ GateController_time 50) GateController_thousand)), 25597#(or (<= (+ GateController_time 40) GateController_thousand) GateController_alarm), 25598#GateController_alarm] [2018-07-23 13:37:05,342 INFO L134 CoverageAnalysis]: Checked inductivity of 4656 backedges. 0 proven. 4656 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:37:05,342 INFO L450 AbstractCegarLoop]: Interpolant automaton has 100 states [2018-07-23 13:37:05,343 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 100 interpolants. [2018-07-23 13:37:05,343 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=4949, Invalid=4951, Unknown=0, NotChecked=0, Total=9900 [2018-07-23 13:37:05,343 INFO L87 Difference]: Start difference. First operand 100 states and 100 transitions. Second operand 100 states. [2018-07-23 13:37:05,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:37:05,439 INFO L93 Difference]: Finished difference Result 103 states and 103 transitions. [2018-07-23 13:37:05,439 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 100 states. [2018-07-23 13:37:05,439 INFO L78 Accepts]: Start accepts. Automaton has 100 states. Word has length 99 [2018-07-23 13:37:05,439 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:37:05,440 INFO L225 Difference]: With dead ends: 103 [2018-07-23 13:37:05,440 INFO L226 Difference]: Without dead ends: 101 [2018-07-23 13:37:05,441 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 98 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 98 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 191 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=4949, Invalid=4951, Unknown=0, NotChecked=0, Total=9900 [2018-07-23 13:37:05,441 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101 states. [2018-07-23 13:37:05,446 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101 to 101. [2018-07-23 13:37:05,446 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 101 states. [2018-07-23 13:37:05,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101 states to 101 states and 101 transitions. [2018-07-23 13:37:05,447 INFO L78 Accepts]: Start accepts. Automaton has 101 states and 101 transitions. Word has length 99 [2018-07-23 13:37:05,447 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:37:05,447 INFO L471 AbstractCegarLoop]: Abstraction has 101 states and 101 transitions. [2018-07-23 13:37:05,447 INFO L472 AbstractCegarLoop]: Interpolant automaton has 100 states. [2018-07-23 13:37:05,447 INFO L276 IsEmpty]: Start isEmpty. Operand 101 states and 101 transitions. [2018-07-23 13:37:05,447 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 101 [2018-07-23 13:37:05,447 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:37:05,448 INFO L357 BasicCegarLoop]: trace histogram [97, 1, 1, 1] [2018-07-23 13:37:05,448 INFO L414 AbstractCegarLoop]: === Iteration 98 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:37:05,448 INFO L82 PathProgramCache]: Analyzing trace with hash 295176864, now seen corresponding path program 97 times [2018-07-23 13:37:05,448 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:37:05,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:37:05,974 INFO L134 CoverageAnalysis]: Checked inductivity of 4753 backedges. 0 proven. 4753 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:37:05,975 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:37:05,975 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [99] total 99 [2018-07-23 13:37:05,975 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:37:05,975 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:37:05,976 INFO L185 omatonBuilderFactory]: Interpolants [26007#true, 26008#false, 26009#(<= (+ GateController_time 1000) GateController_thousand), 26010#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 26011#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 26012#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 26013#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 26014#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 26015#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 26016#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 26017#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 26018#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 26019#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 26020#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 26021#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 26022#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 26023#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 26024#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 26025#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 26026#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 26027#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 26028#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 26029#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 26030#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 26031#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 26032#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 26033#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 26034#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 26035#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 26036#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 26037#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 26038#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 26039#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 26040#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 26041#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 26042#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 26043#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 26044#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 26045#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 26046#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 26047#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 26048#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 26049#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 26050#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 26051#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 26052#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 26053#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 26054#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 26055#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 26056#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 26057#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 26058#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 26059#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 26060#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 26061#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 26062#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 26063#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 26064#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 26065#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 26066#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 26067#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 26068#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 26069#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 26070#(or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)), 26071#(or GateController_alarm (<= (+ GateController_time 380) GateController_thousand)), 26072#(or GateController_alarm (<= (+ GateController_time 370) GateController_thousand)), 26073#(or (<= (+ GateController_time 360) GateController_thousand) GateController_alarm), 26074#(or (<= (+ GateController_time 350) GateController_thousand) GateController_alarm), 26075#(or GateController_alarm (<= (+ GateController_time 340) GateController_thousand)), 26076#(or (<= (+ GateController_time 330) GateController_thousand) GateController_alarm), 26077#(or GateController_alarm (<= (+ GateController_time 320) GateController_thousand)), 26078#(or GateController_alarm (<= (+ GateController_time 310) GateController_thousand)), 26079#(or GateController_alarm (<= (+ GateController_time 300) GateController_thousand)), 26080#(or GateController_alarm (<= (+ GateController_time 290) GateController_thousand)), 26081#(or GateController_alarm (<= (+ GateController_time 280) GateController_thousand)), 26082#(or (<= (+ GateController_time 270) GateController_thousand) GateController_alarm), 26083#(or GateController_alarm (<= (+ GateController_time 260) GateController_thousand)), 26084#(or GateController_alarm (<= (+ GateController_time 250) GateController_thousand)), 26085#(or GateController_alarm (<= (+ GateController_time 240) GateController_thousand)), 26086#(or GateController_alarm (<= (+ GateController_time 230) GateController_thousand)), 26087#(or GateController_alarm (<= (+ GateController_time 220) GateController_thousand)), 26088#(or GateController_alarm (<= (+ GateController_time 210) GateController_thousand)), 26089#(or GateController_alarm (<= (+ GateController_time 200) GateController_thousand)), 26090#(or (<= (+ GateController_time 190) GateController_thousand) GateController_alarm), 26091#(or GateController_alarm (<= (+ GateController_time 180) GateController_thousand)), 26092#(or GateController_alarm (<= (+ GateController_time 170) GateController_thousand)), 26093#(or GateController_alarm (<= (+ GateController_time 160) GateController_thousand)), 26094#(or GateController_alarm (<= (+ GateController_time 150) GateController_thousand)), 26095#(or (<= (+ GateController_time 140) GateController_thousand) GateController_alarm), 26096#(or GateController_alarm (<= (+ GateController_time 130) GateController_thousand)), 26097#(or GateController_alarm (<= (+ GateController_time 120) GateController_thousand)), 26098#(or GateController_alarm (<= (+ GateController_time 110) GateController_thousand)), 26099#(or GateController_alarm (<= (+ GateController_time 100) GateController_thousand)), 26100#(or GateController_alarm (<= (+ GateController_time 90) GateController_thousand)), 26101#(or GateController_alarm (<= (+ GateController_time 80) GateController_thousand)), 26102#(or GateController_alarm (<= (+ GateController_time 70) GateController_thousand)), 26103#(or GateController_alarm (<= (+ GateController_time 60) GateController_thousand)), 26104#(or GateController_alarm (<= (+ GateController_time 50) GateController_thousand)), 26105#(or (<= (+ GateController_time 40) GateController_thousand) GateController_alarm), 26106#(or GateController_alarm (<= (+ GateController_time 30) GateController_thousand)), 26107#GateController_alarm] [2018-07-23 13:37:05,976 INFO L134 CoverageAnalysis]: Checked inductivity of 4753 backedges. 0 proven. 4753 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:37:05,976 INFO L450 AbstractCegarLoop]: Interpolant automaton has 101 states [2018-07-23 13:37:05,977 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 101 interpolants. [2018-07-23 13:37:05,977 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5049, Invalid=5051, Unknown=0, NotChecked=0, Total=10100 [2018-07-23 13:37:05,977 INFO L87 Difference]: Start difference. First operand 101 states and 101 transitions. Second operand 101 states. [2018-07-23 13:37:06,082 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:37:06,082 INFO L93 Difference]: Finished difference Result 104 states and 104 transitions. [2018-07-23 13:37:06,082 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 101 states. [2018-07-23 13:37:06,082 INFO L78 Accepts]: Start accepts. Automaton has 101 states. Word has length 100 [2018-07-23 13:37:06,082 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:37:06,083 INFO L225 Difference]: With dead ends: 104 [2018-07-23 13:37:06,083 INFO L226 Difference]: Without dead ends: 102 [2018-07-23 13:37:06,084 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 99 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 99 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 193 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=5049, Invalid=5051, Unknown=0, NotChecked=0, Total=10100 [2018-07-23 13:37:06,084 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102 states. [2018-07-23 13:37:06,090 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102 to 102. [2018-07-23 13:37:06,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102 states. [2018-07-23 13:37:06,091 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 102 transitions. [2018-07-23 13:37:06,091 INFO L78 Accepts]: Start accepts. Automaton has 102 states and 102 transitions. Word has length 100 [2018-07-23 13:37:06,091 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:37:06,091 INFO L471 AbstractCegarLoop]: Abstraction has 102 states and 102 transitions. [2018-07-23 13:37:06,091 INFO L472 AbstractCegarLoop]: Interpolant automaton has 101 states. [2018-07-23 13:37:06,091 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 102 transitions. [2018-07-23 13:37:06,092 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 102 [2018-07-23 13:37:06,092 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:37:06,092 INFO L357 BasicCegarLoop]: trace histogram [98, 1, 1, 1] [2018-07-23 13:37:06,092 INFO L414 AbstractCegarLoop]: === Iteration 99 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:37:06,092 INFO L82 PathProgramCache]: Analyzing trace with hash 560557792, now seen corresponding path program 98 times [2018-07-23 13:37:06,093 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:37:06,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:37:06,708 INFO L134 CoverageAnalysis]: Checked inductivity of 4851 backedges. 0 proven. 4851 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:37:06,708 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:37:06,708 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [100] total 100 [2018-07-23 13:37:06,709 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:37:06,709 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:37:06,709 INFO L185 omatonBuilderFactory]: Interpolants [26520#true, 26521#false, 26522#(<= (+ GateController_time 1000) GateController_thousand), 26523#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 26524#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 26525#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 26526#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 26527#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 26528#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 26529#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 26530#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 26531#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 26532#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 26533#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 26534#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 26535#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 26536#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 26537#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 26538#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 26539#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 26540#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 26541#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 26542#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 26543#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 26544#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 26545#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 26546#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 26547#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 26548#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 26549#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 26550#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 26551#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 26552#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 26553#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 26554#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 26555#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 26556#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 26557#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 26558#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 26559#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 26560#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 26561#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 26562#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 26563#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 26564#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 26565#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 26566#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 26567#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 26568#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 26569#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 26570#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 26571#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 26572#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 26573#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 26574#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 26575#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 26576#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 26577#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 26578#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 26579#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 26580#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 26581#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 26582#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 26583#(or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)), 26584#(or GateController_alarm (<= (+ GateController_time 380) GateController_thousand)), 26585#(or GateController_alarm (<= (+ GateController_time 370) GateController_thousand)), 26586#(or (<= (+ GateController_time 360) GateController_thousand) GateController_alarm), 26587#(or (<= (+ GateController_time 350) GateController_thousand) GateController_alarm), 26588#(or GateController_alarm (<= (+ GateController_time 340) GateController_thousand)), 26589#(or (<= (+ GateController_time 330) GateController_thousand) GateController_alarm), 26590#(or GateController_alarm (<= (+ GateController_time 320) GateController_thousand)), 26591#(or GateController_alarm (<= (+ GateController_time 310) GateController_thousand)), 26592#(or GateController_alarm (<= (+ GateController_time 300) GateController_thousand)), 26593#(or GateController_alarm (<= (+ GateController_time 290) GateController_thousand)), 26594#(or GateController_alarm (<= (+ GateController_time 280) GateController_thousand)), 26595#(or (<= (+ GateController_time 270) GateController_thousand) GateController_alarm), 26596#(or GateController_alarm (<= (+ GateController_time 260) GateController_thousand)), 26597#(or GateController_alarm (<= (+ GateController_time 250) GateController_thousand)), 26598#(or GateController_alarm (<= (+ GateController_time 240) GateController_thousand)), 26599#(or GateController_alarm (<= (+ GateController_time 230) GateController_thousand)), 26600#(or GateController_alarm (<= (+ GateController_time 220) GateController_thousand)), 26601#(or GateController_alarm (<= (+ GateController_time 210) GateController_thousand)), 26602#(or GateController_alarm (<= (+ GateController_time 200) GateController_thousand)), 26603#(or (<= (+ GateController_time 190) GateController_thousand) GateController_alarm), 26604#(or GateController_alarm (<= (+ GateController_time 180) GateController_thousand)), 26605#(or GateController_alarm (<= (+ GateController_time 170) GateController_thousand)), 26606#(or GateController_alarm (<= (+ GateController_time 160) GateController_thousand)), 26607#(or GateController_alarm (<= (+ GateController_time 150) GateController_thousand)), 26608#(or (<= (+ GateController_time 140) GateController_thousand) GateController_alarm), 26609#(or GateController_alarm (<= (+ GateController_time 130) GateController_thousand)), 26610#(or GateController_alarm (<= (+ GateController_time 120) GateController_thousand)), 26611#(or GateController_alarm (<= (+ GateController_time 110) GateController_thousand)), 26612#(or GateController_alarm (<= (+ GateController_time 100) GateController_thousand)), 26613#(or GateController_alarm (<= (+ GateController_time 90) GateController_thousand)), 26614#(or GateController_alarm (<= (+ GateController_time 80) GateController_thousand)), 26615#(or GateController_alarm (<= (+ GateController_time 70) GateController_thousand)), 26616#(or GateController_alarm (<= (+ GateController_time 60) GateController_thousand)), 26617#(or GateController_alarm (<= (+ GateController_time 50) GateController_thousand)), 26618#(or (<= (+ GateController_time 40) GateController_thousand) GateController_alarm), 26619#(or GateController_alarm (<= (+ GateController_time 30) GateController_thousand)), 26620#(or GateController_alarm (<= (+ GateController_time 20) GateController_thousand)), 26621#GateController_alarm] [2018-07-23 13:37:06,710 INFO L134 CoverageAnalysis]: Checked inductivity of 4851 backedges. 0 proven. 4851 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:37:06,710 INFO L450 AbstractCegarLoop]: Interpolant automaton has 102 states [2018-07-23 13:37:06,711 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 102 interpolants. [2018-07-23 13:37:06,711 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5150, Invalid=5152, Unknown=0, NotChecked=0, Total=10302 [2018-07-23 13:37:06,711 INFO L87 Difference]: Start difference. First operand 102 states and 102 transitions. Second operand 102 states. [2018-07-23 13:37:06,822 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:37:06,822 INFO L93 Difference]: Finished difference Result 105 states and 105 transitions. [2018-07-23 13:37:06,822 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 102 states. [2018-07-23 13:37:06,823 INFO L78 Accepts]: Start accepts. Automaton has 102 states. Word has length 101 [2018-07-23 13:37:06,823 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:37:06,823 INFO L225 Difference]: With dead ends: 105 [2018-07-23 13:37:06,823 INFO L226 Difference]: Without dead ends: 103 [2018-07-23 13:37:06,824 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 100 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 100 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 195 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=5150, Invalid=5152, Unknown=0, NotChecked=0, Total=10302 [2018-07-23 13:37:06,824 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 103 states. [2018-07-23 13:37:06,829 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 103 to 103. [2018-07-23 13:37:06,829 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 103 states. [2018-07-23 13:37:06,830 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103 states to 103 states and 103 transitions. [2018-07-23 13:37:06,830 INFO L78 Accepts]: Start accepts. Automaton has 103 states and 103 transitions. Word has length 101 [2018-07-23 13:37:06,830 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:37:06,830 INFO L471 AbstractCegarLoop]: Abstraction has 103 states and 103 transitions. [2018-07-23 13:37:06,830 INFO L472 AbstractCegarLoop]: Interpolant automaton has 102 states. [2018-07-23 13:37:06,830 INFO L276 IsEmpty]: Start isEmpty. Operand 103 states and 103 transitions. [2018-07-23 13:37:06,831 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-07-23 13:37:06,831 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:37:06,831 INFO L357 BasicCegarLoop]: trace histogram [99, 1, 1, 1] [2018-07-23 13:37:06,831 INFO L414 AbstractCegarLoop]: === Iteration 100 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:37:06,831 INFO L82 PathProgramCache]: Analyzing trace with hash 197431968, now seen corresponding path program 99 times [2018-07-23 13:37:06,831 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:37:06,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:37:07,378 INFO L134 CoverageAnalysis]: Checked inductivity of 4950 backedges. 0 proven. 4950 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:37:07,379 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:37:07,379 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [101] total 101 [2018-07-23 13:37:07,379 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:37:07,379 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:37:07,380 INFO L185 omatonBuilderFactory]: Interpolants [27136#(or (<= (+ GateController_time 40) GateController_thousand) GateController_alarm), 27137#(or GateController_alarm (<= (+ GateController_time 30) GateController_thousand)), 27138#(or GateController_alarm (<= (+ GateController_time 20) GateController_thousand)), 27139#(or GateController_alarm (<= (+ GateController_time 10) GateController_thousand)), 27140#GateController_alarm, 27038#true, 27039#false, 27040#(<= (+ GateController_time 1000) GateController_thousand), 27041#(or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)), 27042#(or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)), 27043#(or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)), 27044#(or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)), 27045#(or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)), 27046#(or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)), 27047#(or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)), 27048#(or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)), 27049#(or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)), 27050#(or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)), 27051#(or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)), 27052#(or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)), 27053#(or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)), 27054#(or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)), 27055#(or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)), 27056#(or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)), 27057#(or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)), 27058#(or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)), 27059#(or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)), 27060#(or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)), 27061#(or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)), 27062#(or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)), 27063#(or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)), 27064#(or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)), 27065#(or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)), 27066#(or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)), 27067#(or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)), 27068#(or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)), 27069#(or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)), 27070#(or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)), 27071#(or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm), 27072#(or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm), 27073#(or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)), 27074#(or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)), 27075#(or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)), 27076#(or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)), 27077#(or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)), 27078#(or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)), 27079#(or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)), 27080#(or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)), 27081#(or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)), 27082#(or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)), 27083#(or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)), 27084#(or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm), 27085#(or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)), 27086#(or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)), 27087#(or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)), 27088#(or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)), 27089#(or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)), 27090#(or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm), 27091#(or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm), 27092#(or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)), 27093#(or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)), 27094#(or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)), 27095#(or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)), 27096#(or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)), 27097#(or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)), 27098#(or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm), 27099#(or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)), 27100#(or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)), 27101#(or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)), 27102#(or GateController_alarm (<= (+ GateController_time 380) GateController_thousand)), 27103#(or GateController_alarm (<= (+ GateController_time 370) GateController_thousand)), 27104#(or (<= (+ GateController_time 360) GateController_thousand) GateController_alarm), 27105#(or (<= (+ GateController_time 350) GateController_thousand) GateController_alarm), 27106#(or GateController_alarm (<= (+ GateController_time 340) GateController_thousand)), 27107#(or (<= (+ GateController_time 330) GateController_thousand) GateController_alarm), 27108#(or GateController_alarm (<= (+ GateController_time 320) GateController_thousand)), 27109#(or GateController_alarm (<= (+ GateController_time 310) GateController_thousand)), 27110#(or GateController_alarm (<= (+ GateController_time 300) GateController_thousand)), 27111#(or GateController_alarm (<= (+ GateController_time 290) GateController_thousand)), 27112#(or GateController_alarm (<= (+ GateController_time 280) GateController_thousand)), 27113#(or (<= (+ GateController_time 270) GateController_thousand) GateController_alarm), 27114#(or GateController_alarm (<= (+ GateController_time 260) GateController_thousand)), 27115#(or GateController_alarm (<= (+ GateController_time 250) GateController_thousand)), 27116#(or GateController_alarm (<= (+ GateController_time 240) GateController_thousand)), 27117#(or GateController_alarm (<= (+ GateController_time 230) GateController_thousand)), 27118#(or GateController_alarm (<= (+ GateController_time 220) GateController_thousand)), 27119#(or GateController_alarm (<= (+ GateController_time 210) GateController_thousand)), 27120#(or GateController_alarm (<= (+ GateController_time 200) GateController_thousand)), 27121#(or (<= (+ GateController_time 190) GateController_thousand) GateController_alarm), 27122#(or GateController_alarm (<= (+ GateController_time 180) GateController_thousand)), 27123#(or GateController_alarm (<= (+ GateController_time 170) GateController_thousand)), 27124#(or GateController_alarm (<= (+ GateController_time 160) GateController_thousand)), 27125#(or GateController_alarm (<= (+ GateController_time 150) GateController_thousand)), 27126#(or (<= (+ GateController_time 140) GateController_thousand) GateController_alarm), 27127#(or GateController_alarm (<= (+ GateController_time 130) GateController_thousand)), 27128#(or GateController_alarm (<= (+ GateController_time 120) GateController_thousand)), 27129#(or GateController_alarm (<= (+ GateController_time 110) GateController_thousand)), 27130#(or GateController_alarm (<= (+ GateController_time 100) GateController_thousand)), 27131#(or GateController_alarm (<= (+ GateController_time 90) GateController_thousand)), 27132#(or GateController_alarm (<= (+ GateController_time 80) GateController_thousand)), 27133#(or GateController_alarm (<= (+ GateController_time 70) GateController_thousand)), 27134#(or GateController_alarm (<= (+ GateController_time 60) GateController_thousand)), 27135#(or GateController_alarm (<= (+ GateController_time 50) GateController_thousand))] [2018-07-23 13:37:07,380 INFO L134 CoverageAnalysis]: Checked inductivity of 4950 backedges. 0 proven. 4950 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:37:07,380 INFO L450 AbstractCegarLoop]: Interpolant automaton has 103 states [2018-07-23 13:37:07,381 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 103 interpolants. [2018-07-23 13:37:07,381 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5252, Invalid=5254, Unknown=0, NotChecked=0, Total=10506 [2018-07-23 13:37:07,381 INFO L87 Difference]: Start difference. First operand 103 states and 103 transitions. Second operand 103 states. [2018-07-23 13:37:07,463 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:37:07,464 INFO L93 Difference]: Finished difference Result 106 states and 106 transitions. [2018-07-23 13:37:07,464 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 103 states. [2018-07-23 13:37:07,464 INFO L78 Accepts]: Start accepts. Automaton has 103 states. Word has length 102 [2018-07-23 13:37:07,464 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:37:07,464 INFO L225 Difference]: With dead ends: 106 [2018-07-23 13:37:07,465 INFO L226 Difference]: Without dead ends: 104 [2018-07-23 13:37:07,465 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 101 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 101 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 197 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=5252, Invalid=5254, Unknown=0, NotChecked=0, Total=10506 [2018-07-23 13:37:07,466 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104 states. [2018-07-23 13:37:07,469 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104 to 104. [2018-07-23 13:37:07,469 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 104 states. [2018-07-23 13:37:07,470 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 104 states to 104 states and 104 transitions. [2018-07-23 13:37:07,470 INFO L78 Accepts]: Start accepts. Automaton has 104 states and 104 transitions. Word has length 102 [2018-07-23 13:37:07,470 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:37:07,470 INFO L471 AbstractCegarLoop]: Abstraction has 104 states and 104 transitions. [2018-07-23 13:37:07,470 INFO L472 AbstractCegarLoop]: Interpolant automaton has 103 states. [2018-07-23 13:37:07,470 INFO L276 IsEmpty]: Start isEmpty. Operand 104 states and 104 transitions. [2018-07-23 13:37:07,470 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 104 [2018-07-23 13:37:07,471 INFO L349 BasicCegarLoop]: Found error trace [2018-07-23 13:37:07,471 INFO L357 BasicCegarLoop]: trace histogram [100, 1, 1, 1] [2018-07-23 13:37:07,471 INFO L414 AbstractCegarLoop]: === Iteration 101 === [GateControllerErr0AssertViolationASSERT]=== [2018-07-23 13:37:07,471 INFO L82 PathProgramCache]: Analyzing trace with hash 1825433312, now seen corresponding path program 100 times [2018-07-23 13:37:07,471 INFO L69 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-07-23 13:37:07,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-23 13:37:08,940 INFO L134 CoverageAnalysis]: Checked inductivity of 5050 backedges. 0 proven. 5050 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:37:08,941 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-07-23 13:37:08,941 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [101] total 101 [2018-07-23 13:37:08,941 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-07-23 13:37:08,941 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:37:08,942 INFO L185 omatonBuilderFactory]: Interpolants [27648#(and (<= GateController_maxGatePosition (+ GateController_gate 15)) (<= (+ GateController_gate 15) GateController_maxGatePosition)), 27649#(and (<= (+ GateController_gate 14) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 14))), 27650#(and (<= GateController_maxGatePosition (+ GateController_gate 13)) (<= (+ GateController_gate 13) GateController_maxGatePosition)), 27651#(and (<= (+ GateController_gate 12) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 12))), 27652#(and (<= GateController_maxGatePosition (+ GateController_gate 11)) (<= (+ GateController_gate 11) GateController_maxGatePosition)), 27653#(and (<= GateController_maxGatePosition (+ GateController_gate 10)) (<= (+ GateController_gate 10) GateController_maxGatePosition)), 27654#(and (<= (+ GateController_gate 9) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 9))), 27655#(and (<= (+ GateController_gate 8) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 8))), 27656#(and (<= (+ GateController_gate 7) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 7))), 27657#(and (<= (+ GateController_gate 6) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 6))), 27658#(and (<= GateController_maxGatePosition (+ GateController_gate 5)) (<= (+ GateController_gate 5) GateController_maxGatePosition)), 27659#(and (<= GateController_maxGatePosition (+ GateController_gate 4)) (<= (+ GateController_gate 4) GateController_maxGatePosition)), 27660#(and (<= (+ GateController_gate 3) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 3))), 27661#(and (<= GateController_maxGatePosition (+ GateController_gate 2)) (<= (+ GateController_gate 2) GateController_maxGatePosition)), 27662#(and (<= (+ GateController_gate 1) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 1))), 27663#(and (<= GateController_maxGatePosition GateController_gate) (<= GateController_gate GateController_maxGatePosition)), 27561#true, 27562#false, 27563#(and (<= (+ GateController_gate 100) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 100))), 27564#(and (<= GateController_maxGatePosition (+ GateController_gate 99)) (<= (+ GateController_gate 99) GateController_maxGatePosition)), 27565#(and (<= (+ GateController_gate 98) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 98))), 27566#(and (<= (+ GateController_gate 97) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 97))), 27567#(and (<= GateController_maxGatePosition (+ GateController_gate 96)) (<= (+ GateController_gate 96) GateController_maxGatePosition)), 27568#(and (<= GateController_maxGatePosition (+ GateController_gate 95)) (<= (+ GateController_gate 95) GateController_maxGatePosition)), 27569#(and (<= (+ GateController_gate 94) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 94))), 27570#(and (<= GateController_maxGatePosition (+ GateController_gate 93)) (<= (+ GateController_gate 93) GateController_maxGatePosition)), 27571#(and (<= (+ GateController_gate 92) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 92))), 27572#(and (<= (+ GateController_gate 91) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 91))), 27573#(and (<= GateController_maxGatePosition (+ GateController_gate 90)) (<= (+ GateController_gate 90) GateController_maxGatePosition)), 27574#(and (<= (+ GateController_gate 89) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 89))), 27575#(and (<= (+ GateController_gate 88) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 88))), 27576#(and (<= (+ GateController_gate 87) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 87))), 27577#(and (<= (+ GateController_gate 86) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 86))), 27578#(and (<= GateController_maxGatePosition (+ GateController_gate 85)) (<= (+ GateController_gate 85) GateController_maxGatePosition)), 27579#(and (<= (+ GateController_gate 84) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 84))), 27580#(and (<= (+ GateController_gate 83) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 83))), 27581#(and (<= GateController_maxGatePosition (+ GateController_gate 82)) (<= (+ GateController_gate 82) GateController_maxGatePosition)), 27582#(and (<= (+ GateController_gate 81) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 81))), 27583#(and (<= GateController_maxGatePosition (+ GateController_gate 80)) (<= (+ GateController_gate 80) GateController_maxGatePosition)), 27584#(and (<= (+ GateController_gate 79) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 79))), 27585#(and (<= (+ GateController_gate 78) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 78))), 27586#(and (<= (+ GateController_gate 77) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 77))), 27587#(and (<= GateController_maxGatePosition (+ GateController_gate 76)) (<= (+ GateController_gate 76) GateController_maxGatePosition)), 27588#(and (<= GateController_maxGatePosition (+ GateController_gate 75)) (<= (+ GateController_gate 75) GateController_maxGatePosition)), 27589#(and (<= GateController_maxGatePosition (+ GateController_gate 74)) (<= (+ GateController_gate 74) GateController_maxGatePosition)), 27590#(and (<= GateController_maxGatePosition (+ GateController_gate 73)) (<= (+ GateController_gate 73) GateController_maxGatePosition)), 27591#(and (<= GateController_maxGatePosition (+ GateController_gate 72)) (<= (+ GateController_gate 72) GateController_maxGatePosition)), 27592#(and (<= (+ GateController_gate 71) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 71))), 27593#(and (<= GateController_maxGatePosition (+ GateController_gate 70)) (<= (+ GateController_gate 70) GateController_maxGatePosition)), 27594#(and (<= (+ GateController_gate 69) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 69))), 27595#(and (<= GateController_maxGatePosition (+ GateController_gate 68)) (<= (+ GateController_gate 68) GateController_maxGatePosition)), 27596#(and (<= GateController_maxGatePosition (+ GateController_gate 67)) (<= (+ GateController_gate 67) GateController_maxGatePosition)), 27597#(and (<= (+ GateController_gate 66) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 66))), 27598#(and (<= (+ GateController_gate 65) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 65))), 27599#(and (<= GateController_maxGatePosition (+ GateController_gate 64)) (<= (+ GateController_gate 64) GateController_maxGatePosition)), 27600#(and (<= GateController_maxGatePosition (+ GateController_gate 63)) (<= (+ GateController_gate 63) GateController_maxGatePosition)), 27601#(and (<= GateController_maxGatePosition (+ GateController_gate 62)) (<= (+ GateController_gate 62) GateController_maxGatePosition)), 27602#(and (<= (+ GateController_gate 61) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 61))), 27603#(and (<= GateController_maxGatePosition (+ GateController_gate 60)) (<= (+ GateController_gate 60) GateController_maxGatePosition)), 27604#(and (<= (+ GateController_gate 59) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 59))), 27605#(and (<= GateController_maxGatePosition (+ GateController_gate 58)) (<= (+ GateController_gate 58) GateController_maxGatePosition)), 27606#(and (<= GateController_maxGatePosition (+ GateController_gate 57)) (<= (+ GateController_gate 57) GateController_maxGatePosition)), 27607#(and (<= GateController_maxGatePosition (+ GateController_gate 56)) (<= (+ GateController_gate 56) GateController_maxGatePosition)), 27608#(and (<= GateController_maxGatePosition (+ GateController_gate 55)) (<= (+ GateController_gate 55) GateController_maxGatePosition)), 27609#(and (<= GateController_maxGatePosition (+ GateController_gate 54)) (<= (+ GateController_gate 54) GateController_maxGatePosition)), 27610#(and (<= (+ GateController_gate 53) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 53))), 27611#(and (<= GateController_maxGatePosition (+ GateController_gate 52)) (<= (+ GateController_gate 52) GateController_maxGatePosition)), 27612#(and (<= GateController_maxGatePosition (+ GateController_gate 51)) (<= (+ GateController_gate 51) GateController_maxGatePosition)), 27613#(and (<= (+ GateController_gate 50) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 50))), 27614#(and (<= (+ GateController_gate 49) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 49))), 27615#(and (<= (+ GateController_gate 48) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 48))), 27616#(and (<= (+ GateController_gate 47) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 47))), 27617#(and (<= GateController_maxGatePosition (+ GateController_gate 46)) (<= (+ GateController_gate 46) GateController_maxGatePosition)), 27618#(and (<= GateController_maxGatePosition (+ GateController_gate 45)) (<= (+ GateController_gate 45) GateController_maxGatePosition)), 27619#(and (<= (+ GateController_gate 44) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 44))), 27620#(and (<= (+ GateController_gate 43) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 43))), 27621#(and (<= (+ GateController_gate 42) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 42))), 27622#(and (<= (+ GateController_gate 41) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 41))), 27623#(and (<= (+ GateController_gate 40) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 40))), 27624#(and (<= (+ GateController_gate 39) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 39))), 27625#(and (<= (+ GateController_gate 38) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 38))), 27626#(and (<= (+ GateController_gate 37) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 37))), 27627#(and (<= GateController_maxGatePosition (+ GateController_gate 36)) (<= (+ GateController_gate 36) GateController_maxGatePosition)), 27628#(and (<= GateController_maxGatePosition (+ GateController_gate 35)) (<= (+ GateController_gate 35) GateController_maxGatePosition)), 27629#(and (<= (+ GateController_gate 34) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 34))), 27630#(and (<= (+ GateController_gate 33) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 33))), 27631#(and (<= GateController_maxGatePosition (+ GateController_gate 32)) (<= (+ GateController_gate 32) GateController_maxGatePosition)), 27632#(and (<= (+ GateController_gate 31) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 31))), 27633#(and (<= (+ GateController_gate 30) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 30))), 27634#(and (<= (+ GateController_gate 29) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 29))), 27635#(and (<= GateController_maxGatePosition (+ GateController_gate 28)) (<= (+ GateController_gate 28) GateController_maxGatePosition)), 27636#(and (<= (+ GateController_gate 27) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 27))), 27637#(and (<= (+ GateController_gate 26) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 26))), 27638#(and (<= GateController_maxGatePosition (+ GateController_gate 25)) (<= (+ GateController_gate 25) GateController_maxGatePosition)), 27639#(and (<= (+ GateController_gate 24) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 24))), 27640#(and (<= (+ GateController_gate 23) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 23))), 27641#(and (<= GateController_maxGatePosition (+ GateController_gate 22)) (<= (+ GateController_gate 22) GateController_maxGatePosition)), 27642#(and (<= (+ GateController_gate 21) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 21))), 27643#(and (<= GateController_maxGatePosition (+ GateController_gate 20)) (<= (+ GateController_gate 20) GateController_maxGatePosition)), 27644#(and (<= (+ GateController_gate 19) GateController_maxGatePosition) (<= GateController_maxGatePosition (+ GateController_gate 19))), 27645#(and (<= GateController_maxGatePosition (+ GateController_gate 18)) (<= (+ GateController_gate 18) GateController_maxGatePosition)), 27646#(and (<= GateController_maxGatePosition (+ GateController_gate 17)) (<= (+ GateController_gate 17) GateController_maxGatePosition)), 27647#(and (<= GateController_maxGatePosition (+ GateController_gate 16)) (<= (+ GateController_gate 16) GateController_maxGatePosition))] [2018-07-23 13:37:08,943 INFO L134 CoverageAnalysis]: Checked inductivity of 5050 backedges. 0 proven. 5050 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-23 13:37:08,943 INFO L450 AbstractCegarLoop]: Interpolant automaton has 103 states [2018-07-23 13:37:08,943 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 103 interpolants. [2018-07-23 13:37:08,944 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=203, Invalid=10303, Unknown=0, NotChecked=0, Total=10506 [2018-07-23 13:37:08,944 INFO L87 Difference]: Start difference. First operand 104 states and 104 transitions. Second operand 103 states. [2018-07-23 13:37:10,389 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-23 13:37:10,389 INFO L93 Difference]: Finished difference Result 104 states and 104 transitions. [2018-07-23 13:37:10,389 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 103 states. [2018-07-23 13:37:10,389 INFO L78 Accepts]: Start accepts. Automaton has 103 states. Word has length 103 [2018-07-23 13:37:10,390 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-23 13:37:10,390 INFO L225 Difference]: With dead ends: 104 [2018-07-23 13:37:10,390 INFO L226 Difference]: Without dead ends: 0 [2018-07-23 13:37:10,391 INFO L575 BasicCegarLoop]: 0 DeclaredPredicates, 101 GetRequests, 0 SyntacticMatches, 0 SemanticMatches, 101 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=203, Invalid=10303, Unknown=0, NotChecked=0, Total=10506 [2018-07-23 13:37:10,391 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 0 states. [2018-07-23 13:37:10,392 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 0 to 0. [2018-07-23 13:37:10,392 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 0 states. [2018-07-23 13:37:10,392 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 0 states to 0 states and 0 transitions. [2018-07-23 13:37:10,392 INFO L78 Accepts]: Start accepts. Automaton has 0 states and 0 transitions. Word has length 103 [2018-07-23 13:37:10,392 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-23 13:37:10,392 INFO L471 AbstractCegarLoop]: Abstraction has 0 states and 0 transitions. [2018-07-23 13:37:10,392 INFO L472 AbstractCegarLoop]: Interpolant automaton has 103 states. [2018-07-23 13:37:10,392 INFO L276 IsEmpty]: Start isEmpty. Operand 0 states and 0 transitions. [2018-07-23 13:37:10,393 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-07-23 13:37:10,398 INFO L343 DoubleDeckerVisitor]: Before removal of dead ends 0 states and 0 transitions. [2018-07-23 13:37:10,583 WARN L169 SmtUtils]: Spent 172.00 ms on a formula simplification that was a NOOP. DAG size: 898 [2018-07-23 13:37:11,795 WARN L169 SmtUtils]: Spent 1.20 s on a formula simplification that was a NOOP. DAG size: 898 [2018-07-23 13:37:11,805 INFO L424 ceAbstractionStarter]: At program point GateControllerENTRY(lines 18 45) the Hoare annotation is: true [2018-07-23 13:37:11,806 INFO L421 ceAbstractionStarter]: For program point L34''(lines 34 36) no Hoare annotation was computed. [2018-07-23 13:37:11,806 INFO L424 ceAbstractionStarter]: At program point GateControllerEXIT(lines 18 45) the Hoare annotation is: true [2018-07-23 13:37:11,806 INFO L421 ceAbstractionStarter]: For program point L34(lines 34 36) no Hoare annotation was computed. [2018-07-23 13:37:11,821 INFO L417 ceAbstractionStarter]: At program point L33(lines 33 42) the Hoare annotation is: (or (let ((.cse0 (+ GateController_gate 45))) (and (or GateController_alarm (<= (+ GateController_time 450) GateController_thousand)) (<= GateController_maxGatePosition .cse0) (<= .cse0 GateController_maxGatePosition))) (let ((.cse1 (+ GateController_gate 61))) (and (or GateController_alarm (<= (+ GateController_time 610) GateController_thousand)) (<= .cse1 GateController_maxGatePosition) (<= GateController_maxGatePosition .cse1))) (let ((.cse2 (+ GateController_gate 66))) (and (<= .cse2 GateController_maxGatePosition) (or GateController_alarm (<= (+ GateController_time 660) GateController_thousand)) (<= GateController_maxGatePosition .cse2))) (let ((.cse3 (+ GateController_gate 12))) (and (or GateController_alarm (<= (+ GateController_time 120) GateController_thousand)) (<= .cse3 GateController_maxGatePosition) (<= GateController_maxGatePosition .cse3))) (let ((.cse4 (+ GateController_gate 39))) (and (or GateController_alarm (<= (+ GateController_time 390) GateController_thousand)) (<= .cse4 GateController_maxGatePosition) (<= GateController_maxGatePosition .cse4))) (let ((.cse5 (+ GateController_gate 86))) (and (<= .cse5 GateController_maxGatePosition) (<= GateController_maxGatePosition .cse5) (or GateController_alarm (<= (+ GateController_time 860) GateController_thousand)))) (let ((.cse6 (+ GateController_gate 95))) (and (<= GateController_maxGatePosition .cse6) (<= .cse6 GateController_maxGatePosition) (or GateController_alarm (<= (+ GateController_time 950) GateController_thousand)))) (let ((.cse7 (+ GateController_gate 51))) (and (<= GateController_maxGatePosition .cse7) (or GateController_alarm (<= (+ GateController_time 510) GateController_thousand)) (<= .cse7 GateController_maxGatePosition))) (let ((.cse8 (+ GateController_gate 27))) (and (<= .cse8 GateController_maxGatePosition) (or (<= (+ GateController_time 270) GateController_thousand) GateController_alarm) (<= GateController_maxGatePosition .cse8))) (let ((.cse9 (+ GateController_gate 44))) (and (<= .cse9 GateController_maxGatePosition) (<= GateController_maxGatePosition .cse9) (or GateController_alarm (<= (+ GateController_time 440) GateController_thousand)))) (let ((.cse10 (+ GateController_gate 58))) (and (<= GateController_maxGatePosition .cse10) (<= .cse10 GateController_maxGatePosition) (or GateController_alarm (<= (+ GateController_time 580) GateController_thousand)))) (let ((.cse11 (+ GateController_gate 19))) (and (or (<= (+ GateController_time 190) GateController_thousand) GateController_alarm) (<= .cse11 GateController_maxGatePosition) (<= GateController_maxGatePosition .cse11))) (and (<= GateController_maxGatePosition GateController_gate) (<= GateController_gate GateController_maxGatePosition)) (let ((.cse12 (+ GateController_gate 91))) (and (<= .cse12 GateController_maxGatePosition) (<= GateController_maxGatePosition .cse12) (or GateController_alarm (<= (+ GateController_time 910) GateController_thousand)))) (let ((.cse13 (+ GateController_gate 67))) (and (or GateController_alarm (<= (+ GateController_time 670) GateController_thousand)) (<= GateController_maxGatePosition .cse13) (<= .cse13 GateController_maxGatePosition))) (let ((.cse14 (+ GateController_gate 1))) (and (<= .cse14 GateController_maxGatePosition) (or GateController_alarm (<= (+ GateController_time 10) GateController_thousand)) (<= GateController_maxGatePosition .cse14))) (let ((.cse15 (+ GateController_gate 71))) (and (or GateController_alarm (<= (+ GateController_time 710) GateController_thousand)) (<= .cse15 GateController_maxGatePosition) (<= GateController_maxGatePosition .cse15))) (let ((.cse16 (+ GateController_gate 20))) (and (<= GateController_maxGatePosition .cse16) (or GateController_alarm (<= (+ GateController_time 200) GateController_thousand)) (<= .cse16 GateController_maxGatePosition))) (let ((.cse17 (+ GateController_gate 2))) (and (or GateController_alarm (<= (+ GateController_time 20) GateController_thousand)) (<= GateController_maxGatePosition .cse17) (<= .cse17 GateController_maxGatePosition))) (let ((.cse18 (+ GateController_gate 57))) (and (<= GateController_maxGatePosition .cse18) (<= .cse18 GateController_maxGatePosition) (or GateController_alarm (<= (+ GateController_time 570) GateController_thousand)))) (let ((.cse19 (+ GateController_gate 54))) (and (<= GateController_maxGatePosition .cse19) (or GateController_alarm (<= (+ GateController_time 540) GateController_thousand)) (<= .cse19 GateController_maxGatePosition))) (let ((.cse20 (+ GateController_gate 48))) (and (<= .cse20 GateController_maxGatePosition) (or GateController_alarm (<= (+ GateController_time 480) GateController_thousand)) (<= GateController_maxGatePosition .cse20))) (let ((.cse21 (+ GateController_gate 25))) (and (or GateController_alarm (<= (+ GateController_time 250) GateController_thousand)) (<= GateController_maxGatePosition .cse21) (<= .cse21 GateController_maxGatePosition))) (let ((.cse22 (+ GateController_gate 90))) (and (or GateController_alarm (<= (+ GateController_time 900) GateController_thousand)) (<= GateController_maxGatePosition .cse22) (<= .cse22 GateController_maxGatePosition))) (let ((.cse23 (+ GateController_gate 5))) (and (<= GateController_maxGatePosition .cse23) (or GateController_alarm (<= (+ GateController_time 50) GateController_thousand)) (<= .cse23 GateController_maxGatePosition))) (let ((.cse24 (+ GateController_gate 49))) (and (<= .cse24 GateController_maxGatePosition) (or (<= (+ GateController_time 490) GateController_thousand) GateController_alarm) (<= GateController_maxGatePosition .cse24))) (let ((.cse25 (+ GateController_gate 68))) (and (<= GateController_maxGatePosition .cse25) (<= .cse25 GateController_maxGatePosition) (or (<= (+ GateController_time 680) GateController_thousand) GateController_alarm))) (let ((.cse26 (+ GateController_gate 35))) (and (<= GateController_maxGatePosition .cse26) (or (<= (+ GateController_time 350) GateController_thousand) GateController_alarm) (<= .cse26 GateController_maxGatePosition))) (let ((.cse27 (+ GateController_gate 60))) (and (<= GateController_maxGatePosition .cse27) (or GateController_alarm (<= (+ GateController_time 600) GateController_thousand)) (<= .cse27 GateController_maxGatePosition))) (let ((.cse28 (+ GateController_gate 42))) (and (or (<= (+ GateController_time 420) GateController_thousand) GateController_alarm) (<= .cse28 GateController_maxGatePosition) (<= GateController_maxGatePosition .cse28))) (let ((.cse29 (+ GateController_gate 88))) (and (<= .cse29 GateController_maxGatePosition) (or GateController_alarm (<= (+ GateController_time 880) GateController_thousand)) (<= GateController_maxGatePosition .cse29))) (let ((.cse30 (+ GateController_gate 63))) (and (or GateController_alarm (<= (+ GateController_time 630) GateController_thousand)) (<= GateController_maxGatePosition .cse30) (<= .cse30 GateController_maxGatePosition))) (let ((.cse31 (+ GateController_gate 7))) (and (<= .cse31 GateController_maxGatePosition) (<= GateController_maxGatePosition .cse31) (or GateController_alarm (<= (+ GateController_time 70) GateController_thousand)))) (let ((.cse32 (+ GateController_gate 40))) (and (<= .cse32 GateController_maxGatePosition) (<= GateController_maxGatePosition .cse32) (or GateController_alarm (<= (+ GateController_time 400) GateController_thousand)))) (let ((.cse33 (+ GateController_gate 79))) (and (or GateController_alarm (<= (+ GateController_time 790) GateController_thousand)) (<= .cse33 GateController_maxGatePosition) (<= GateController_maxGatePosition .cse33))) (let ((.cse34 (+ GateController_gate 93))) (and (or GateController_alarm (<= (+ GateController_time 930) GateController_thousand)) (<= GateController_maxGatePosition .cse34) (<= .cse34 GateController_maxGatePosition))) (let ((.cse35 (+ GateController_gate 89))) (and (<= .cse35 GateController_maxGatePosition) (<= GateController_maxGatePosition .cse35) (or GateController_alarm (<= (+ GateController_time 890) GateController_thousand)))) (let ((.cse36 (+ GateController_gate 65))) (and (or GateController_alarm (<= (+ GateController_time 650) GateController_thousand)) (<= .cse36 GateController_maxGatePosition) (<= GateController_maxGatePosition .cse36))) (let ((.cse37 (+ GateController_gate 87))) (and (<= .cse37 GateController_maxGatePosition) (or GateController_alarm (<= (+ GateController_time 870) GateController_thousand)) (<= GateController_maxGatePosition .cse37))) (let ((.cse38 (+ GateController_gate 38))) (and (<= .cse38 GateController_maxGatePosition) (or GateController_alarm (<= (+ GateController_time 380) GateController_thousand)) (<= GateController_maxGatePosition .cse38))) (let ((.cse39 (+ GateController_gate 4))) (and (or (<= (+ GateController_time 40) GateController_thousand) GateController_alarm) (<= GateController_maxGatePosition .cse39) (<= .cse39 GateController_maxGatePosition))) (let ((.cse40 (+ GateController_gate 36))) (and (<= GateController_maxGatePosition .cse40) (<= .cse40 GateController_maxGatePosition) (or (<= (+ GateController_time 360) GateController_thousand) GateController_alarm))) (let ((.cse41 (+ GateController_gate 64))) (and (<= GateController_maxGatePosition .cse41) (or GateController_alarm (<= (+ GateController_time 640) GateController_thousand)) (<= .cse41 GateController_maxGatePosition))) (let ((.cse42 (+ GateController_gate 56))) (and (or (<= (+ GateController_time 560) GateController_thousand) GateController_alarm) (<= GateController_maxGatePosition .cse42) (<= .cse42 GateController_maxGatePosition))) (let ((.cse43 (+ GateController_gate 8))) (and (<= .cse43 GateController_maxGatePosition) (or GateController_alarm (<= (+ GateController_time 80) GateController_thousand)) (<= GateController_maxGatePosition .cse43))) (let ((.cse44 (+ GateController_gate 9))) (and (<= .cse44 GateController_maxGatePosition) (<= GateController_maxGatePosition .cse44) (or GateController_alarm (<= (+ GateController_time 90) GateController_thousand)))) (let ((.cse45 (+ GateController_gate 15))) (and (<= GateController_maxGatePosition .cse45) (<= .cse45 GateController_maxGatePosition) (or GateController_alarm (<= (+ GateController_time 150) GateController_thousand)))) (let ((.cse46 (+ GateController_gate 85))) (and (or GateController_alarm (<= (+ GateController_time 850) GateController_thousand)) (<= GateController_maxGatePosition .cse46) (<= .cse46 GateController_maxGatePosition))) (let ((.cse47 (+ GateController_gate 77))) (and (<= .cse47 GateController_maxGatePosition) (or GateController_alarm (<= (+ GateController_time 770) GateController_thousand)) (<= GateController_maxGatePosition .cse47))) (let ((.cse48 (+ GateController_gate 53))) (and (<= .cse48 GateController_maxGatePosition) (or GateController_alarm (<= (+ GateController_time 530) GateController_thousand)) (<= GateController_maxGatePosition .cse48))) (let ((.cse49 (+ GateController_gate 43))) (and (or GateController_alarm (<= (+ GateController_time 430) GateController_thousand)) (<= .cse49 GateController_maxGatePosition) (<= GateController_maxGatePosition .cse49))) (let ((.cse50 (+ GateController_gate 11))) (and (<= GateController_maxGatePosition .cse50) (or GateController_alarm (<= (+ GateController_time 110) GateController_thousand)) (<= .cse50 GateController_maxGatePosition))) (let ((.cse51 (+ GateController_gate 47))) (and (<= .cse51 GateController_maxGatePosition) (or GateController_alarm (<= (+ GateController_time 470) GateController_thousand)) (<= GateController_maxGatePosition .cse51))) (let ((.cse52 (+ GateController_gate 96))) (and (<= GateController_maxGatePosition .cse52) (<= .cse52 GateController_maxGatePosition) (or GateController_alarm (<= (+ GateController_time 960) GateController_thousand)))) (let ((.cse53 (+ GateController_gate 17))) (and (or GateController_alarm (<= (+ GateController_time 170) GateController_thousand)) (<= GateController_maxGatePosition .cse53) (<= .cse53 GateController_maxGatePosition))) (let ((.cse54 (+ GateController_gate 76))) (and (<= GateController_maxGatePosition .cse54) (<= .cse54 GateController_maxGatePosition) (or GateController_alarm (<= (+ GateController_time 760) GateController_thousand)))) (let ((.cse55 (+ GateController_gate 70))) (and (<= GateController_maxGatePosition .cse55) (<= .cse55 GateController_maxGatePosition) (or GateController_alarm (<= (+ GateController_time 700) GateController_thousand)))) (let ((.cse56 (+ GateController_gate 26))) (and (<= .cse56 GateController_maxGatePosition) (or GateController_alarm (<= (+ GateController_time 260) GateController_thousand)) (<= GateController_maxGatePosition .cse56))) (let ((.cse57 (+ GateController_gate 23))) (and (or GateController_alarm (<= (+ GateController_time 230) GateController_thousand)) (<= .cse57 GateController_maxGatePosition) (<= GateController_maxGatePosition .cse57))) (let ((.cse58 (+ GateController_gate 32))) (and (<= GateController_maxGatePosition .cse58) (or GateController_alarm (<= (+ GateController_time 320) GateController_thousand)) (<= .cse58 GateController_maxGatePosition))) (let ((.cse59 (+ GateController_gate 22))) (and (<= GateController_maxGatePosition .cse59) (or GateController_alarm (<= (+ GateController_time 220) GateController_thousand)) (<= .cse59 GateController_maxGatePosition))) (let ((.cse60 (+ GateController_gate 73))) (and (or GateController_alarm (<= (+ GateController_time 730) GateController_thousand)) (<= GateController_maxGatePosition .cse60) (<= .cse60 GateController_maxGatePosition))) (let ((.cse61 (+ GateController_gate 14))) (and (<= .cse61 GateController_maxGatePosition) (<= GateController_maxGatePosition .cse61) (or (<= (+ GateController_time 140) GateController_thousand) GateController_alarm))) (let ((.cse62 (+ GateController_gate 16))) (and (or GateController_alarm (<= (+ GateController_time 160) GateController_thousand)) (<= GateController_maxGatePosition .cse62) (<= .cse62 GateController_maxGatePosition))) (let ((.cse63 (+ GateController_gate 33))) (and (or (<= (+ GateController_time 330) GateController_thousand) GateController_alarm) (<= .cse63 GateController_maxGatePosition) (<= GateController_maxGatePosition .cse63))) (let ((.cse64 (+ GateController_gate 18))) (and (<= GateController_maxGatePosition .cse64) (or GateController_alarm (<= (+ GateController_time 180) GateController_thousand)) (<= .cse64 GateController_maxGatePosition))) (let ((.cse65 (+ GateController_gate 13))) (and (<= GateController_maxGatePosition .cse65) (<= .cse65 GateController_maxGatePosition) (or GateController_alarm (<= (+ GateController_time 130) GateController_thousand)))) (let ((.cse66 (+ GateController_gate 62))) (and (<= GateController_maxGatePosition .cse66) (or GateController_alarm (<= (+ GateController_time 620) GateController_thousand)) (<= .cse66 GateController_maxGatePosition))) (let ((.cse67 (+ GateController_gate 72))) (and (<= GateController_maxGatePosition .cse67) (<= .cse67 GateController_maxGatePosition) (or GateController_alarm (<= (+ GateController_time 720) GateController_thousand)))) (let ((.cse68 (+ GateController_gate 24))) (and (<= .cse68 GateController_maxGatePosition) (<= GateController_maxGatePosition .cse68) (or GateController_alarm (<= (+ GateController_time 240) GateController_thousand)))) (let ((.cse69 (+ GateController_gate 52))) (and (or GateController_alarm (<= (+ GateController_time 520) GateController_thousand)) (<= GateController_maxGatePosition .cse69) (<= .cse69 GateController_maxGatePosition))) (let ((.cse70 (+ GateController_gate 94))) (and (or GateController_alarm (<= (+ GateController_time 940) GateController_thousand)) (<= .cse70 GateController_maxGatePosition) (<= GateController_maxGatePosition .cse70))) (let ((.cse71 (+ GateController_gate 83))) (and (or GateController_alarm (<= (+ GateController_time 830) GateController_thousand)) (<= .cse71 GateController_maxGatePosition) (<= GateController_maxGatePosition .cse71))) (let ((.cse72 (+ GateController_gate 82))) (and (<= GateController_maxGatePosition .cse72) (or GateController_alarm (<= (+ GateController_time 820) GateController_thousand)) (<= .cse72 GateController_maxGatePosition))) (let ((.cse73 (+ GateController_gate 98))) (and (<= .cse73 GateController_maxGatePosition) (<= GateController_maxGatePosition .cse73) (or GateController_alarm (<= (+ GateController_time 980) GateController_thousand)))) (let ((.cse74 (+ GateController_gate 37))) (and (<= .cse74 GateController_maxGatePosition) (<= GateController_maxGatePosition .cse74) (or GateController_alarm (<= (+ GateController_time 370) GateController_thousand)))) (let ((.cse75 (+ GateController_gate 50))) (and (<= .cse75 GateController_maxGatePosition) (<= GateController_maxGatePosition .cse75) (or (<= (+ GateController_time 500) GateController_thousand) GateController_alarm))) (let ((.cse76 (+ GateController_gate 41))) (and (<= .cse76 GateController_maxGatePosition) (<= GateController_maxGatePosition .cse76) (or GateController_alarm (<= (+ GateController_time 410) GateController_thousand)))) (let ((.cse77 (+ GateController_gate 81))) (and (<= .cse77 GateController_maxGatePosition) (<= GateController_maxGatePosition .cse77) (or GateController_alarm (<= (+ GateController_time 810) GateController_thousand)))) (let ((.cse78 (+ GateController_gate 75))) (and (or GateController_alarm (<= (+ GateController_time 750) GateController_thousand)) (<= GateController_maxGatePosition .cse78) (<= .cse78 GateController_maxGatePosition))) (let ((.cse79 (+ GateController_gate 29))) (and (<= .cse79 GateController_maxGatePosition) (or GateController_alarm (<= (+ GateController_time 290) GateController_thousand)) (<= GateController_maxGatePosition .cse79))) (let ((.cse80 (+ GateController_gate 46))) (and (<= GateController_maxGatePosition .cse80) (or GateController_alarm (<= (+ GateController_time 460) GateController_thousand)) (<= .cse80 GateController_maxGatePosition))) (let ((.cse81 (+ GateController_gate 34))) (and (<= .cse81 GateController_maxGatePosition) (or GateController_alarm (<= (+ GateController_time 340) GateController_thousand)) (<= GateController_maxGatePosition .cse81))) (let ((.cse82 (+ GateController_gate 69))) (and (<= .cse82 GateController_maxGatePosition) (or (<= (+ GateController_time 690) GateController_thousand) GateController_alarm) (<= GateController_maxGatePosition .cse82))) (let ((.cse83 (+ GateController_gate 84))) (and (<= .cse83 GateController_maxGatePosition) (<= GateController_maxGatePosition .cse83) (or GateController_alarm (<= (+ GateController_time 840) GateController_thousand)))) (let ((.cse84 (+ GateController_gate 80))) (and (<= GateController_maxGatePosition .cse84) (or GateController_alarm (<= (+ GateController_time 800) GateController_thousand)) (<= .cse84 GateController_maxGatePosition))) (let ((.cse85 (+ GateController_gate 92))) (and (<= .cse85 GateController_maxGatePosition) (<= GateController_maxGatePosition .cse85) (or GateController_alarm (<= (+ GateController_time 920) GateController_thousand)))) (let ((.cse86 (+ GateController_gate 10))) (and (or GateController_alarm (<= (+ GateController_time 100) GateController_thousand)) (<= GateController_maxGatePosition .cse86) (<= .cse86 GateController_maxGatePosition))) (let ((.cse87 (+ GateController_gate 28))) (and (or GateController_alarm (<= (+ GateController_time 280) GateController_thousand)) (<= GateController_maxGatePosition .cse87) (<= .cse87 GateController_maxGatePosition))) (let ((.cse88 (+ GateController_gate 100))) (and (<= .cse88 GateController_maxGatePosition) (<= (+ GateController_time 1000) GateController_thousand) (<= GateController_maxGatePosition .cse88))) (let ((.cse89 (+ GateController_gate 30))) (and (<= .cse89 GateController_maxGatePosition) (<= GateController_maxGatePosition .cse89) (or GateController_alarm (<= (+ GateController_time 300) GateController_thousand)))) (let ((.cse90 (+ GateController_gate 21))) (and (<= .cse90 GateController_maxGatePosition) (<= GateController_maxGatePosition .cse90) (or GateController_alarm (<= (+ GateController_time 210) GateController_thousand)))) (let ((.cse91 (+ GateController_gate 55))) (and (<= GateController_maxGatePosition .cse91) (<= .cse91 GateController_maxGatePosition) (or GateController_alarm (<= (+ GateController_time 550) GateController_thousand)))) (let ((.cse92 (+ GateController_gate 74))) (and (<= GateController_maxGatePosition .cse92) (or GateController_alarm (<= (+ GateController_time 740) GateController_thousand)) (<= .cse92 GateController_maxGatePosition))) (let ((.cse93 (+ GateController_gate 99))) (and (or GateController_alarm (<= (+ GateController_time 990) GateController_thousand)) (<= GateController_maxGatePosition .cse93) (<= .cse93 GateController_maxGatePosition))) (let ((.cse94 (+ GateController_gate 6))) (and (<= .cse94 GateController_maxGatePosition) (<= GateController_maxGatePosition .cse94) (or GateController_alarm (<= (+ GateController_time 60) GateController_thousand)))) (let ((.cse95 (+ GateController_gate 78))) (and (<= .cse95 GateController_maxGatePosition) (or GateController_alarm (<= (+ GateController_time 780) GateController_thousand)) (<= GateController_maxGatePosition .cse95))) (let ((.cse96 (+ GateController_gate 97))) (and (or GateController_alarm (<= (+ GateController_time 970) GateController_thousand)) (<= .cse96 GateController_maxGatePosition) (<= GateController_maxGatePosition .cse96))) (let ((.cse97 (+ GateController_gate 3))) (and (<= .cse97 GateController_maxGatePosition) (<= GateController_maxGatePosition .cse97) (or GateController_alarm (<= (+ GateController_time 30) GateController_thousand)))) (let ((.cse98 (+ GateController_gate 59))) (and (<= .cse98 GateController_maxGatePosition) (or GateController_alarm (<= (+ GateController_time 590) GateController_thousand)) (<= GateController_maxGatePosition .cse98))) (let ((.cse99 (+ GateController_gate 31))) (and (or GateController_alarm (<= (+ GateController_time 310) GateController_thousand)) (<= .cse99 GateController_maxGatePosition) (<= GateController_maxGatePosition .cse99)))) [2018-07-23 13:37:11,822 INFO L417 ceAbstractionStarter]: At program point L44(line 44) the Hoare annotation is: (or GateController_alarm (and (<= GateController_maxGatePosition GateController_gate) (<= GateController_gate GateController_maxGatePosition))) [2018-07-23 13:37:11,822 INFO L421 ceAbstractionStarter]: For program point L38(lines 38 40) no Hoare annotation was computed. [2018-07-23 13:37:11,822 INFO L421 ceAbstractionStarter]: For program point L38''(lines 38 40) no Hoare annotation was computed. [2018-07-23 13:37:11,822 INFO L421 ceAbstractionStarter]: For program point GateControllerFINAL(lines 18 45) no Hoare annotation was computed. [2018-07-23 13:37:11,822 INFO L417 ceAbstractionStarter]: At program point GateControllerErr0AssertViolationASSERT(line 44) the Hoare annotation is: false [2018-07-23 13:37:11,875 INFO L202 PluginConnector]: Adding new model GateController.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 23.07 01:37:11 BoogieIcfgContainer [2018-07-23 13:37:11,875 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-07-23 13:37:11,876 INFO L168 Benchmark]: Toolchain (without parser) took 45204.31 ms. Allocated memory was 1.5 GB in the beginning and 3.0 GB in the end (delta: 1.5 GB). Free memory was 1.5 GB in the beginning and 1.1 GB in the end (delta: 401.3 MB). Peak memory consumption was 1.9 GB. Max. memory is 7.1 GB. [2018-07-23 13:37:11,880 INFO L168 Benchmark]: Boogie PL CUP Parser took 0.21 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-07-23 13:37:11,880 INFO L168 Benchmark]: Boogie Preprocessor took 56.20 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-07-23 13:37:11,881 INFO L168 Benchmark]: RCFGBuilder took 344.29 ms. Allocated memory is still 1.5 GB. Free memory was 1.5 GB in the beginning and 1.5 GB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 7.1 GB. [2018-07-23 13:37:11,881 INFO L168 Benchmark]: TraceAbstraction took 44799.75 ms. Allocated memory was 1.5 GB in the beginning and 3.0 GB in the end (delta: 1.5 GB). Free memory was 1.5 GB in the beginning and 1.1 GB in the end (delta: 390.7 MB). Peak memory consumption was 1.8 GB. Max. memory is 7.1 GB. [2018-07-23 13:37:11,884 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * Boogie PL CUP Parser took 0.21 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. * Boogie Preprocessor took 56.20 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. * RCFGBuilder took 344.29 ms. Allocated memory is still 1.5 GB. Free memory was 1.5 GB in the beginning and 1.5 GB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 7.1 GB. * TraceAbstraction took 44799.75 ms. Allocated memory was 1.5 GB in the beginning and 3.0 GB in the end (delta: 1.5 GB). Free memory was 1.5 GB in the beginning and 1.1 GB in the end (delta: 390.7 MB). Peak memory consumption was 1.8 GB. Max. memory is 7.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - PositiveResult [Line: 44]: assertion always holds For all program executions holds that assertion always holds at this location - AllSpecificationsHoldResult: All specifications hold 1 specifications checked. All of them hold - InvariantResult [Line: 33]: Loop Invariant Derived loop invariant: ((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((alarm || time + 450 <= thousand) && maxGatePosition <= gate + 45) && gate + 45 <= maxGatePosition) || (((alarm || time + 610 <= thousand) && gate + 61 <= maxGatePosition) && maxGatePosition <= gate + 61)) || ((gate + 66 <= maxGatePosition && (alarm || time + 660 <= thousand)) && maxGatePosition <= gate + 66)) || (((alarm || time + 120 <= thousand) && gate + 12 <= maxGatePosition) && maxGatePosition <= gate + 12)) || (((alarm || time + 390 <= thousand) && gate + 39 <= maxGatePosition) && maxGatePosition <= gate + 39)) || ((gate + 86 <= maxGatePosition && maxGatePosition <= gate + 86) && (alarm || time + 860 <= thousand))) || ((maxGatePosition <= gate + 95 && gate + 95 <= maxGatePosition) && (alarm || time + 950 <= thousand))) || ((maxGatePosition <= gate + 51 && (alarm || time + 510 <= thousand)) && gate + 51 <= maxGatePosition)) || ((gate + 27 <= maxGatePosition && (time + 270 <= thousand || alarm)) && maxGatePosition <= gate + 27)) || ((gate + 44 <= maxGatePosition && maxGatePosition <= gate + 44) && (alarm || time + 440 <= thousand))) || ((maxGatePosition <= gate + 58 && gate + 58 <= maxGatePosition) && (alarm || time + 580 <= thousand))) || (((time + 190 <= thousand || alarm) && gate + 19 <= maxGatePosition) && maxGatePosition <= gate + 19)) || (maxGatePosition <= gate && gate <= maxGatePosition)) || ((gate + 91 <= maxGatePosition && maxGatePosition <= gate + 91) && (alarm || time + 910 <= thousand))) || (((alarm || time + 670 <= thousand) && maxGatePosition <= gate + 67) && gate + 67 <= maxGatePosition)) || ((gate + 1 <= maxGatePosition && (alarm || time + 10 <= thousand)) && maxGatePosition <= gate + 1)) || (((alarm || time + 710 <= thousand) && gate + 71 <= maxGatePosition) && maxGatePosition <= gate + 71)) || ((maxGatePosition <= gate + 20 && (alarm || time + 200 <= thousand)) && gate + 20 <= maxGatePosition)) || (((alarm || time + 20 <= thousand) && maxGatePosition <= gate + 2) && gate + 2 <= maxGatePosition)) || ((maxGatePosition <= gate + 57 && gate + 57 <= maxGatePosition) && (alarm || time + 570 <= thousand))) || ((maxGatePosition <= gate + 54 && (alarm || time + 540 <= thousand)) && gate + 54 <= maxGatePosition)) || ((gate + 48 <= maxGatePosition && (alarm || time + 480 <= thousand)) && maxGatePosition <= gate + 48)) || (((alarm || time + 250 <= thousand) && maxGatePosition <= gate + 25) && gate + 25 <= maxGatePosition)) || (((alarm || time + 900 <= thousand) && maxGatePosition <= gate + 90) && gate + 90 <= maxGatePosition)) || ((maxGatePosition <= gate + 5 && (alarm || time + 50 <= thousand)) && gate + 5 <= maxGatePosition)) || ((gate + 49 <= maxGatePosition && (time + 490 <= thousand || alarm)) && maxGatePosition <= gate + 49)) || ((maxGatePosition <= gate + 68 && gate + 68 <= maxGatePosition) && (time + 680 <= thousand || alarm))) || ((maxGatePosition <= gate + 35 && (time + 350 <= thousand || alarm)) && gate + 35 <= maxGatePosition)) || ((maxGatePosition <= gate + 60 && (alarm || time + 600 <= thousand)) && gate + 60 <= maxGatePosition)) || (((time + 420 <= thousand || alarm) && gate + 42 <= maxGatePosition) && maxGatePosition <= gate + 42)) || ((gate + 88 <= maxGatePosition && (alarm || time + 880 <= thousand)) && maxGatePosition <= gate + 88)) || (((alarm || time + 630 <= thousand) && maxGatePosition <= gate + 63) && gate + 63 <= maxGatePosition)) || ((gate + 7 <= maxGatePosition && maxGatePosition <= gate + 7) && (alarm || time + 70 <= thousand))) || ((gate + 40 <= maxGatePosition && maxGatePosition <= gate + 40) && (alarm || time + 400 <= thousand))) || (((alarm || time + 790 <= thousand) && gate + 79 <= maxGatePosition) && maxGatePosition <= gate + 79)) || (((alarm || time + 930 <= thousand) && maxGatePosition <= gate + 93) && gate + 93 <= maxGatePosition)) || ((gate + 89 <= maxGatePosition && maxGatePosition <= gate + 89) && (alarm || time + 890 <= thousand))) || (((alarm || time + 650 <= thousand) && gate + 65 <= maxGatePosition) && maxGatePosition <= gate + 65)) || ((gate + 87 <= maxGatePosition && (alarm || time + 870 <= thousand)) && maxGatePosition <= gate + 87)) || ((gate + 38 <= maxGatePosition && (alarm || time + 380 <= thousand)) && maxGatePosition <= gate + 38)) || (((time + 40 <= thousand || alarm) && maxGatePosition <= gate + 4) && gate + 4 <= maxGatePosition)) || ((maxGatePosition <= gate + 36 && gate + 36 <= maxGatePosition) && (time + 360 <= thousand || alarm))) || ((maxGatePosition <= gate + 64 && (alarm || time + 640 <= thousand)) && gate + 64 <= maxGatePosition)) || (((time + 560 <= thousand || alarm) && maxGatePosition <= gate + 56) && gate + 56 <= maxGatePosition)) || ((gate + 8 <= maxGatePosition && (alarm || time + 80 <= thousand)) && maxGatePosition <= gate + 8)) || ((gate + 9 <= maxGatePosition && maxGatePosition <= gate + 9) && (alarm || time + 90 <= thousand))) || ((maxGatePosition <= gate + 15 && gate + 15 <= maxGatePosition) && (alarm || time + 150 <= thousand))) || (((alarm || time + 850 <= thousand) && maxGatePosition <= gate + 85) && gate + 85 <= maxGatePosition)) || ((gate + 77 <= maxGatePosition && (alarm || time + 770 <= thousand)) && maxGatePosition <= gate + 77)) || ((gate + 53 <= maxGatePosition && (alarm || time + 530 <= thousand)) && maxGatePosition <= gate + 53)) || (((alarm || time + 430 <= thousand) && gate + 43 <= maxGatePosition) && maxGatePosition <= gate + 43)) || ((maxGatePosition <= gate + 11 && (alarm || time + 110 <= thousand)) && gate + 11 <= maxGatePosition)) || ((gate + 47 <= maxGatePosition && (alarm || time + 470 <= thousand)) && maxGatePosition <= gate + 47)) || ((maxGatePosition <= gate + 96 && gate + 96 <= maxGatePosition) && (alarm || time + 960 <= thousand))) || (((alarm || time + 170 <= thousand) && maxGatePosition <= gate + 17) && gate + 17 <= maxGatePosition)) || ((maxGatePosition <= gate + 76 && gate + 76 <= maxGatePosition) && (alarm || time + 760 <= thousand))) || ((maxGatePosition <= gate + 70 && gate + 70 <= maxGatePosition) && (alarm || time + 700 <= thousand))) || ((gate + 26 <= maxGatePosition && (alarm || time + 260 <= thousand)) && maxGatePosition <= gate + 26)) || (((alarm || time + 230 <= thousand) && gate + 23 <= maxGatePosition) && maxGatePosition <= gate + 23)) || ((maxGatePosition <= gate + 32 && (alarm || time + 320 <= thousand)) && gate + 32 <= maxGatePosition)) || ((maxGatePosition <= gate + 22 && (alarm || time + 220 <= thousand)) && gate + 22 <= maxGatePosition)) || (((alarm || time + 730 <= thousand) && maxGatePosition <= gate + 73) && gate + 73 <= maxGatePosition)) || ((gate + 14 <= maxGatePosition && maxGatePosition <= gate + 14) && (time + 140 <= thousand || alarm))) || (((alarm || time + 160 <= thousand) && maxGatePosition <= gate + 16) && gate + 16 <= maxGatePosition)) || (((time + 330 <= thousand || alarm) && gate + 33 <= maxGatePosition) && maxGatePosition <= gate + 33)) || ((maxGatePosition <= gate + 18 && (alarm || time + 180 <= thousand)) && gate + 18 <= maxGatePosition)) || ((maxGatePosition <= gate + 13 && gate + 13 <= maxGatePosition) && (alarm || time + 130 <= thousand))) || ((maxGatePosition <= gate + 62 && (alarm || time + 620 <= thousand)) && gate + 62 <= maxGatePosition)) || ((maxGatePosition <= gate + 72 && gate + 72 <= maxGatePosition) && (alarm || time + 720 <= thousand))) || ((gate + 24 <= maxGatePosition && maxGatePosition <= gate + 24) && (alarm || time + 240 <= thousand))) || (((alarm || time + 520 <= thousand) && maxGatePosition <= gate + 52) && gate + 52 <= maxGatePosition)) || (((alarm || time + 940 <= thousand) && gate + 94 <= maxGatePosition) && maxGatePosition <= gate + 94)) || (((alarm || time + 830 <= thousand) && gate + 83 <= maxGatePosition) && maxGatePosition <= gate + 83)) || ((maxGatePosition <= gate + 82 && (alarm || time + 820 <= thousand)) && gate + 82 <= maxGatePosition)) || ((gate + 98 <= maxGatePosition && maxGatePosition <= gate + 98) && (alarm || time + 980 <= thousand))) || ((gate + 37 <= maxGatePosition && maxGatePosition <= gate + 37) && (alarm || time + 370 <= thousand))) || ((gate + 50 <= maxGatePosition && maxGatePosition <= gate + 50) && (time + 500 <= thousand || alarm))) || ((gate + 41 <= maxGatePosition && maxGatePosition <= gate + 41) && (alarm || time + 410 <= thousand))) || ((gate + 81 <= maxGatePosition && maxGatePosition <= gate + 81) && (alarm || time + 810 <= thousand))) || (((alarm || time + 750 <= thousand) && maxGatePosition <= gate + 75) && gate + 75 <= maxGatePosition)) || ((gate + 29 <= maxGatePosition && (alarm || time + 290 <= thousand)) && maxGatePosition <= gate + 29)) || ((maxGatePosition <= gate + 46 && (alarm || time + 460 <= thousand)) && gate + 46 <= maxGatePosition)) || ((gate + 34 <= maxGatePosition && (alarm || time + 340 <= thousand)) && maxGatePosition <= gate + 34)) || ((gate + 69 <= maxGatePosition && (time + 690 <= thousand || alarm)) && maxGatePosition <= gate + 69)) || ((gate + 84 <= maxGatePosition && maxGatePosition <= gate + 84) && (alarm || time + 840 <= thousand))) || ((maxGatePosition <= gate + 80 && (alarm || time + 800 <= thousand)) && gate + 80 <= maxGatePosition)) || ((gate + 92 <= maxGatePosition && maxGatePosition <= gate + 92) && (alarm || time + 920 <= thousand))) || (((alarm || time + 100 <= thousand) && maxGatePosition <= gate + 10) && gate + 10 <= maxGatePosition)) || (((alarm || time + 280 <= thousand) && maxGatePosition <= gate + 28) && gate + 28 <= maxGatePosition)) || ((gate + 100 <= maxGatePosition && time + 1000 <= thousand) && maxGatePosition <= gate + 100)) || ((gate + 30 <= maxGatePosition && maxGatePosition <= gate + 30) && (alarm || time + 300 <= thousand))) || ((gate + 21 <= maxGatePosition && maxGatePosition <= gate + 21) && (alarm || time + 210 <= thousand))) || ((maxGatePosition <= gate + 55 && gate + 55 <= maxGatePosition) && (alarm || time + 550 <= thousand))) || ((maxGatePosition <= gate + 74 && (alarm || time + 740 <= thousand)) && gate + 74 <= maxGatePosition)) || (((alarm || time + 990 <= thousand) && maxGatePosition <= gate + 99) && gate + 99 <= maxGatePosition)) || ((gate + 6 <= maxGatePosition && maxGatePosition <= gate + 6) && (alarm || time + 60 <= thousand))) || ((gate + 78 <= maxGatePosition && (alarm || time + 780 <= thousand)) && maxGatePosition <= gate + 78)) || (((alarm || time + 970 <= thousand) && gate + 97 <= maxGatePosition) && maxGatePosition <= gate + 97)) || ((gate + 3 <= maxGatePosition && maxGatePosition <= gate + 3) && (alarm || time + 30 <= thousand))) || ((gate + 59 <= maxGatePosition && (alarm || time + 590 <= thousand)) && maxGatePosition <= gate + 59)) || (((alarm || time + 310 <= thousand) && gate + 31 <= maxGatePosition) && maxGatePosition <= gate + 31) - ProcedureContractResult [Line: 18]: Procedure Contract for GateController Derived contract for procedure GateController: true - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 10 locations, 1 error locations. SAFE Result, 44.6s OverallTime, 101 OverallIterations, 100 TraceHistogramMax, 6.8s AutomataDifference, 0.0s DeadEndRemovalTime, 1.4s HoareAnnotationTime, HoareTripleCheckerStatistics: 204 SDtfs, 4 SDslu, 146 SDs, 0 SdLazy, 22836 SolverSat, 305 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 2.6s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 5251 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5250 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9801 ImplicationChecksByTransitivity, 25.4s Time, 0.1s BasicInterpolantAutomatonTime, BiggestAbstraction: size=104occurred in iteration=100, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/171700 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.6s AutomataMinimizationTime, 101 MinimizatonAttempts, 0 StatesRemovedByMinimization, 0 NontrivialMinimizations, HoareAnnotationStatistics: 0.0s HoareAnnotationTime, 5 LocationsWithAnnotation, 5 PreInvPairs, 108 NumberOfFragments, 1818 HoareAnnotationTreeSize, 5 FomulaSimplifications, 0 FormulaSimplificationTreeSizeReduction, 0.1s HoareSimplificationTime, 5 FomulaSimplificationsInter, 0 FormulaSimplificationTreeSizeReductionInter, 1.2s HoareSimplificationTimeInter, RefinementEngineStatistics: TraceCheckStatistics: 0.2s SsaConstructionTime, 1.7s SatisfiabilityAnalysisTime, 32.2s InterpolantComputationTime, 5353 NumberOfCodeBlocks, 5353 NumberOfCodeBlocksAsserted, 101 NumberOfCheckSat, 5252 ConstructedInterpolants, 0 QuantifiedInterpolants, 2512278 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 101 InterpolantComputations, 1 PerfectInterpolantSequences, 0/171700 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be correct! Written .csv to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/csv/GateController.bpl_AutomizerBpl-nestedInterpolants.epf_AutomizerBpl.xml/Csv-Benchmark-0-2018-07-23_13-37-11-897.csv Written .csv to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/csv/GateController.bpl_AutomizerBpl-nestedInterpolants.epf_AutomizerBpl.xml/Csv-TraceAbstractionBenchmarks-0-2018-07-23_13-37-11-897.csv Received shutdown request...