java -Xmx8000000000 -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data --generate-csv --csv-dir csv -tc ../../../trunk/examples/toolchains/KojakBplInline.xml -s ../../../trunk/examples/settings/pu-bench/svcomp-Reach-32bit-Kojak_Default_PUPT.epf -i ../../../trunk/examples/programs/20170304-DifficultPathPrograms/diamond1.i_3.bpl -------------------------------------------------------------------------------- This is Ultimate 0.1.23-1cc990c [2018-10-01 03:32:13,461 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-10-01 03:32:13,463 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-10-01 03:32:13,476 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-10-01 03:32:13,476 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-10-01 03:32:13,477 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-10-01 03:32:13,478 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-10-01 03:32:13,480 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-10-01 03:32:13,482 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-10-01 03:32:13,483 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-10-01 03:32:13,484 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-10-01 03:32:13,484 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-10-01 03:32:13,485 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-10-01 03:32:13,486 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-10-01 03:32:13,487 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-10-01 03:32:13,488 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-10-01 03:32:13,489 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-10-01 03:32:13,491 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-10-01 03:32:13,493 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-10-01 03:32:13,495 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-10-01 03:32:13,496 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-10-01 03:32:13,497 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-10-01 03:32:13,500 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-10-01 03:32:13,500 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-10-01 03:32:13,500 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-10-01 03:32:13,501 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-10-01 03:32:13,502 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-10-01 03:32:13,503 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-10-01 03:32:13,504 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-10-01 03:32:13,505 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-10-01 03:32:13,505 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-10-01 03:32:13,506 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-10-01 03:32:13,506 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-10-01 03:32:13,506 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-10-01 03:32:13,508 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-10-01 03:32:13,508 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-10-01 03:32:13,509 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/pu-bench/svcomp-Reach-32bit-Kojak_Default_PUPT.epf [2018-10-01 03:32:13,532 INFO L110 SettingsManager]: Loading preferences was successful [2018-10-01 03:32:13,532 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-10-01 03:32:13,533 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-10-01 03:32:13,533 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-10-01 03:32:13,534 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-10-01 03:32:13,534 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-10-01 03:32:13,535 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-10-01 03:32:13,535 INFO L133 SettingsManager]: * sizeof long=4 [2018-10-01 03:32:13,535 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-10-01 03:32:13,535 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-10-01 03:32:13,535 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-10-01 03:32:13,536 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-10-01 03:32:13,537 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-10-01 03:32:13,537 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-10-01 03:32:13,537 INFO L133 SettingsManager]: * sizeof long double=12 [2018-10-01 03:32:13,537 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-10-01 03:32:13,537 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-10-01 03:32:13,538 INFO L131 SettingsManager]: Preferences of CodeCheck differ from their defaults: [2018-10-01 03:32:13,538 INFO L133 SettingsManager]: * Timeout in seconds=1000000 [2018-10-01 03:32:13,538 INFO L133 SettingsManager]: * Use predicate trie based predicate unification=true [2018-10-01 03:32:13,538 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-10-01 03:32:13,539 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-10-01 03:32:13,540 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 [2018-10-01 03:32:13,540 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-10-01 03:32:13,540 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-10-01 03:32:13,540 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-10-01 03:32:13,540 INFO L133 SettingsManager]: * Trace refinement strategy=PENGUIN [2018-10-01 03:32:13,541 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-10-01 03:32:13,541 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-10-01 03:32:13,541 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-10-01 03:32:13,605 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-10-01 03:32:13,619 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-10-01 03:32:13,625 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-10-01 03:32:13,627 INFO L271 PluginConnector]: Initializing Boogie PL CUP Parser... [2018-10-01 03:32:13,628 INFO L276 PluginConnector]: Boogie PL CUP Parser initialized [2018-10-01 03:32:13,629 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/programs/20170304-DifficultPathPrograms/diamond1.i_3.bpl [2018-10-01 03:32:13,629 INFO L111 BoogieParser]: Parsing: '/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/programs/20170304-DifficultPathPrograms/diamond1.i_3.bpl' [2018-10-01 03:32:13,684 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-10-01 03:32:13,687 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-10-01 03:32:13,688 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-10-01 03:32:13,688 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-10-01 03:32:13,688 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-10-01 03:32:13,708 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "diamond1.i_3.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 01.10 03:32:13" (1/1) ... [2018-10-01 03:32:13,721 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "diamond1.i_3.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 01.10 03:32:13" (1/1) ... [2018-10-01 03:32:13,728 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-10-01 03:32:13,729 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-10-01 03:32:13,729 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-10-01 03:32:13,729 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-10-01 03:32:13,741 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "diamond1.i_3.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 01.10 03:32:13" (1/1) ... [2018-10-01 03:32:13,741 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "diamond1.i_3.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 01.10 03:32:13" (1/1) ... [2018-10-01 03:32:13,742 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "diamond1.i_3.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 01.10 03:32:13" (1/1) ... [2018-10-01 03:32:13,742 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "diamond1.i_3.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 01.10 03:32:13" (1/1) ... [2018-10-01 03:32:13,746 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "diamond1.i_3.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 01.10 03:32:13" (1/1) ... [2018-10-01 03:32:13,748 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "diamond1.i_3.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 01.10 03:32:13" (1/1) ... [2018-10-01 03:32:13,749 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "diamond1.i_3.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 01.10 03:32:13" (1/1) ... [2018-10-01 03:32:13,750 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-10-01 03:32:13,751 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-10-01 03:32:13,751 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-10-01 03:32:13,751 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-10-01 03:32:13,752 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "diamond1.i_3.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 01.10 03:32:13" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 [2018-10-01 03:32:13,818 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-10-01 03:32:13,818 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-10-01 03:32:14,068 INFO L348 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-10-01 03:32:14,068 INFO L202 PluginConnector]: Adding new model diamond1.i_3.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 01.10 03:32:14 BoogieIcfgContainer [2018-10-01 03:32:14,069 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-10-01 03:32:14,069 INFO L113 PluginConnector]: ------------------------CodeCheck---------------------------- [2018-10-01 03:32:14,069 INFO L271 PluginConnector]: Initializing CodeCheck... [2018-10-01 03:32:14,081 INFO L276 PluginConnector]: CodeCheck initialized [2018-10-01 03:32:14,081 INFO L185 PluginConnector]: Executing the observer CodeCheckObserver from plugin CodeCheck for "diamond1.i_3.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 01.10 03:32:14" (1/1) ... [2018-10-01 03:32:14,095 INFO L99 BPredicateUnifier]: Initialized predicate-trie based predicate unifier [2018-10-01 03:32:14,130 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:14,139 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 6 transitions. [2018-10-01 03:32:14,140 INFO L276 IsEmpty]: Start isEmpty. Operand 6 states and 6 transitions. [2018-10-01 03:32:14,143 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2018-10-01 03:32:14,143 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:14,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:14,356 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:14,698 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:14,699 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 7 transitions. [2018-10-01 03:32:14,699 INFO L276 IsEmpty]: Start isEmpty. Operand 7 states and 7 transitions. [2018-10-01 03:32:14,699 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 7 [2018-10-01 03:32:14,699 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:14,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:14,776 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:15,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:15,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 9 transitions. [2018-10-01 03:32:15,406 INFO L276 IsEmpty]: Start isEmpty. Operand 9 states and 9 transitions. [2018-10-01 03:32:15,406 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 9 [2018-10-01 03:32:15,406 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:15,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:15,486 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:15,952 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:15,953 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 11 transitions. [2018-10-01 03:32:15,953 INFO L276 IsEmpty]: Start isEmpty. Operand 11 states and 11 transitions. [2018-10-01 03:32:15,953 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 11 [2018-10-01 03:32:15,953 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:15,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:16,098 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:16,831 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:16,831 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 13 transitions. [2018-10-01 03:32:16,832 INFO L276 IsEmpty]: Start isEmpty. Operand 13 states and 13 transitions. [2018-10-01 03:32:16,832 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-10-01 03:32:16,833 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:16,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:17,004 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:17,325 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:17,326 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 15 transitions. [2018-10-01 03:32:17,326 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 15 transitions. [2018-10-01 03:32:17,327 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-10-01 03:32:17,328 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:17,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:17,517 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:18,320 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:18,321 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 17 transitions. [2018-10-01 03:32:18,321 INFO L276 IsEmpty]: Start isEmpty. Operand 17 states and 17 transitions. [2018-10-01 03:32:18,322 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-10-01 03:32:18,322 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:18,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:18,548 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:19,222 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:19,222 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 19 transitions. [2018-10-01 03:32:19,223 INFO L276 IsEmpty]: Start isEmpty. Operand 19 states and 19 transitions. [2018-10-01 03:32:19,224 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2018-10-01 03:32:19,224 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:19,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:19,356 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 0 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:19,670 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:19,671 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 21 transitions. [2018-10-01 03:32:19,671 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 21 transitions. [2018-10-01 03:32:19,671 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-10-01 03:32:19,672 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:19,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:19,920 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:20,267 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:20,268 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23 states to 23 states and 23 transitions. [2018-10-01 03:32:20,268 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states and 23 transitions. [2018-10-01 03:32:20,269 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-10-01 03:32:20,269 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:20,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:20,430 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:20,866 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:20,866 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 25 transitions. [2018-10-01 03:32:20,867 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 25 transitions. [2018-10-01 03:32:20,867 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-10-01 03:32:20,867 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:20,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:21,055 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:21,413 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:21,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 27 transitions. [2018-10-01 03:32:21,414 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states and 27 transitions. [2018-10-01 03:32:21,415 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-10-01 03:32:21,416 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:21,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:21,615 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 132 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:22,106 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:22,107 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 29 transitions. [2018-10-01 03:32:22,107 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 29 transitions. [2018-10-01 03:32:22,108 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-10-01 03:32:22,108 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:22,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:22,322 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:22,697 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:22,698 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 31 transitions. [2018-10-01 03:32:22,698 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states and 31 transitions. [2018-10-01 03:32:22,699 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2018-10-01 03:32:22,699 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:22,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:22,884 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 182 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:23,275 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:23,276 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 33 transitions. [2018-10-01 03:32:23,277 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 33 transitions. [2018-10-01 03:32:23,277 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-10-01 03:32:23,278 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:23,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:23,691 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 0 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:24,297 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:24,298 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35 states to 35 states and 35 transitions. [2018-10-01 03:32:24,298 INFO L276 IsEmpty]: Start isEmpty. Operand 35 states and 35 transitions. [2018-10-01 03:32:24,299 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-10-01 03:32:24,299 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:24,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:24,641 INFO L134 CoverageAnalysis]: Checked inductivity of 240 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:25,365 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:25,365 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 37 transitions. [2018-10-01 03:32:25,366 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 37 transitions. [2018-10-01 03:32:25,366 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-10-01 03:32:25,367 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:25,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:25,563 INFO L134 CoverageAnalysis]: Checked inductivity of 272 backedges. 0 proven. 272 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:26,193 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:26,194 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 39 transitions. [2018-10-01 03:32:26,194 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 39 transitions. [2018-10-01 03:32:26,195 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-10-01 03:32:26,195 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:26,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:26,406 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 0 proven. 306 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:26,903 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:26,904 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 41 transitions. [2018-10-01 03:32:26,904 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 41 transitions. [2018-10-01 03:32:26,905 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-10-01 03:32:26,905 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:26,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:27,050 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 0 proven. 342 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:28,136 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:28,137 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 43 transitions. [2018-10-01 03:32:28,138 INFO L276 IsEmpty]: Start isEmpty. Operand 43 states and 43 transitions. [2018-10-01 03:32:28,139 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-10-01 03:32:28,139 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:28,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:28,902 INFO L134 CoverageAnalysis]: Checked inductivity of 380 backedges. 0 proven. 380 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:29,417 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:29,419 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 45 transitions. [2018-10-01 03:32:29,419 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 45 transitions. [2018-10-01 03:32:29,420 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-10-01 03:32:29,420 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:29,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:29,604 INFO L134 CoverageAnalysis]: Checked inductivity of 420 backedges. 0 proven. 420 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:30,184 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:30,184 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 47 transitions. [2018-10-01 03:32:30,185 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 47 transitions. [2018-10-01 03:32:30,185 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-10-01 03:32:30,185 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:30,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:30,840 INFO L134 CoverageAnalysis]: Checked inductivity of 462 backedges. 0 proven. 462 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:31,414 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:31,415 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 49 transitions. [2018-10-01 03:32:31,415 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 49 transitions. [2018-10-01 03:32:31,416 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-10-01 03:32:31,416 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:31,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:32,258 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:32,849 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:32,850 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 51 transitions. [2018-10-01 03:32:32,850 INFO L276 IsEmpty]: Start isEmpty. Operand 51 states and 51 transitions. [2018-10-01 03:32:32,851 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-10-01 03:32:32,851 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:32,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:33,053 INFO L134 CoverageAnalysis]: Checked inductivity of 552 backedges. 0 proven. 552 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:33,690 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:33,691 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 53 transitions. [2018-10-01 03:32:33,691 INFO L276 IsEmpty]: Start isEmpty. Operand 53 states and 53 transitions. [2018-10-01 03:32:33,691 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-10-01 03:32:33,691 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:33,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:34,303 INFO L134 CoverageAnalysis]: Checked inductivity of 600 backedges. 0 proven. 600 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:35,044 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:35,044 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 55 transitions. [2018-10-01 03:32:35,044 INFO L276 IsEmpty]: Start isEmpty. Operand 55 states and 55 transitions. [2018-10-01 03:32:35,045 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-10-01 03:32:35,045 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:35,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:35,900 INFO L134 CoverageAnalysis]: Checked inductivity of 650 backedges. 0 proven. 650 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:36,799 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:36,800 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 57 transitions. [2018-10-01 03:32:36,800 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 57 transitions. [2018-10-01 03:32:36,801 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-10-01 03:32:36,801 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:36,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:37,006 INFO L134 CoverageAnalysis]: Checked inductivity of 702 backedges. 0 proven. 702 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:37,694 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:37,694 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 59 transitions. [2018-10-01 03:32:37,695 INFO L276 IsEmpty]: Start isEmpty. Operand 59 states and 59 transitions. [2018-10-01 03:32:37,696 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-10-01 03:32:37,696 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:37,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:38,209 INFO L134 CoverageAnalysis]: Checked inductivity of 756 backedges. 0 proven. 756 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:39,018 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:39,018 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 61 transitions. [2018-10-01 03:32:39,019 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 61 transitions. [2018-10-01 03:32:39,019 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2018-10-01 03:32:39,019 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:39,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:39,311 INFO L134 CoverageAnalysis]: Checked inductivity of 812 backedges. 0 proven. 812 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:40,053 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:40,053 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 63 transitions. [2018-10-01 03:32:40,053 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 63 transitions. [2018-10-01 03:32:40,054 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-10-01 03:32:40,054 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:40,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:40,793 INFO L134 CoverageAnalysis]: Checked inductivity of 870 backedges. 0 proven. 870 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:41,741 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:41,741 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 65 transitions. [2018-10-01 03:32:41,741 INFO L276 IsEmpty]: Start isEmpty. Operand 65 states and 65 transitions. [2018-10-01 03:32:41,742 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-10-01 03:32:41,742 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:41,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:41,976 INFO L134 CoverageAnalysis]: Checked inductivity of 930 backedges. 0 proven. 930 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:42,726 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:42,727 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 67 transitions. [2018-10-01 03:32:42,727 INFO L276 IsEmpty]: Start isEmpty. Operand 67 states and 67 transitions. [2018-10-01 03:32:42,727 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-10-01 03:32:42,727 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:42,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:43,099 INFO L134 CoverageAnalysis]: Checked inductivity of 992 backedges. 0 proven. 992 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:43,916 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:43,916 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 69 transitions. [2018-10-01 03:32:43,916 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 69 transitions. [2018-10-01 03:32:43,916 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-10-01 03:32:43,916 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:43,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:44,250 INFO L134 CoverageAnalysis]: Checked inductivity of 1056 backedges. 0 proven. 1056 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:45,060 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:45,060 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71 states to 71 states and 71 transitions. [2018-10-01 03:32:45,060 INFO L276 IsEmpty]: Start isEmpty. Operand 71 states and 71 transitions. [2018-10-01 03:32:45,061 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-10-01 03:32:45,061 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:45,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:45,344 INFO L134 CoverageAnalysis]: Checked inductivity of 1122 backedges. 0 proven. 1122 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:46,256 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:46,256 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 73 transitions. [2018-10-01 03:32:46,256 INFO L276 IsEmpty]: Start isEmpty. Operand 73 states and 73 transitions. [2018-10-01 03:32:46,257 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-10-01 03:32:46,257 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:46,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:46,518 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 0 proven. 1190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:47,599 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:47,600 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 75 transitions. [2018-10-01 03:32:47,600 INFO L276 IsEmpty]: Start isEmpty. Operand 75 states and 75 transitions. [2018-10-01 03:32:47,601 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-10-01 03:32:47,601 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:47,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:48,000 INFO L134 CoverageAnalysis]: Checked inductivity of 1260 backedges. 0 proven. 1260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:48,934 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:48,935 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 77 transitions. [2018-10-01 03:32:48,935 INFO L276 IsEmpty]: Start isEmpty. Operand 77 states and 77 transitions. [2018-10-01 03:32:48,936 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2018-10-01 03:32:48,936 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:48,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:49,313 INFO L134 CoverageAnalysis]: Checked inductivity of 1332 backedges. 0 proven. 1332 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:50,217 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:50,217 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79 states to 79 states and 79 transitions. [2018-10-01 03:32:50,218 INFO L276 IsEmpty]: Start isEmpty. Operand 79 states and 79 transitions. [2018-10-01 03:32:50,218 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2018-10-01 03:32:50,218 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:50,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:51,056 INFO L134 CoverageAnalysis]: Checked inductivity of 1406 backedges. 0 proven. 1406 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:52,277 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:52,277 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 81 transitions. [2018-10-01 03:32:52,277 INFO L276 IsEmpty]: Start isEmpty. Operand 81 states and 81 transitions. [2018-10-01 03:32:52,278 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2018-10-01 03:32:52,278 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:52,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:52,916 INFO L134 CoverageAnalysis]: Checked inductivity of 1482 backedges. 0 proven. 1482 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:53,986 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:53,987 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 83 transitions. [2018-10-01 03:32:53,987 INFO L276 IsEmpty]: Start isEmpty. Operand 83 states and 83 transitions. [2018-10-01 03:32:53,988 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2018-10-01 03:32:53,988 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:54,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:54,450 INFO L134 CoverageAnalysis]: Checked inductivity of 1560 backedges. 0 proven. 1560 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:55,452 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:55,453 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85 states to 85 states and 85 transitions. [2018-10-01 03:32:55,453 INFO L276 IsEmpty]: Start isEmpty. Operand 85 states and 85 transitions. [2018-10-01 03:32:55,454 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-10-01 03:32:55,454 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:55,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:55,712 INFO L134 CoverageAnalysis]: Checked inductivity of 1640 backedges. 0 proven. 1640 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:56,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:56,894 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 87 transitions. [2018-10-01 03:32:56,894 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 87 transitions. [2018-10-01 03:32:56,894 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-10-01 03:32:56,895 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:56,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:57,262 INFO L134 CoverageAnalysis]: Checked inductivity of 1722 backedges. 0 proven. 1722 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:58,342 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:58,342 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 89 transitions. [2018-10-01 03:32:58,342 INFO L276 IsEmpty]: Start isEmpty. Operand 89 states and 89 transitions. [2018-10-01 03:32:58,343 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2018-10-01 03:32:58,343 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:58,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:58,604 INFO L134 CoverageAnalysis]: Checked inductivity of 1806 backedges. 0 proven. 1806 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:32:59,691 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:32:59,692 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91 states to 91 states and 91 transitions. [2018-10-01 03:32:59,692 INFO L276 IsEmpty]: Start isEmpty. Operand 91 states and 91 transitions. [2018-10-01 03:32:59,693 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-10-01 03:32:59,693 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:32:59,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:32:59,951 INFO L134 CoverageAnalysis]: Checked inductivity of 1892 backedges. 0 proven. 1892 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:33:01,084 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:33:01,085 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 93 transitions. [2018-10-01 03:33:01,085 INFO L276 IsEmpty]: Start isEmpty. Operand 93 states and 93 transitions. [2018-10-01 03:33:01,086 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-10-01 03:33:01,086 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:33:01,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:33:01,363 INFO L134 CoverageAnalysis]: Checked inductivity of 1980 backedges. 0 proven. 1980 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:33:02,637 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:33:02,638 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 95 transitions. [2018-10-01 03:33:02,638 INFO L276 IsEmpty]: Start isEmpty. Operand 95 states and 95 transitions. [2018-10-01 03:33:02,638 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-10-01 03:33:02,639 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:33:02,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:33:02,976 INFO L134 CoverageAnalysis]: Checked inductivity of 2070 backedges. 0 proven. 2070 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:33:04,140 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:33:04,141 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 97 transitions. [2018-10-01 03:33:04,141 INFO L276 IsEmpty]: Start isEmpty. Operand 97 states and 97 transitions. [2018-10-01 03:33:04,141 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-10-01 03:33:04,141 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:33:04,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:33:04,399 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:33:05,633 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:33:05,633 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 99 transitions. [2018-10-01 03:33:05,634 INFO L276 IsEmpty]: Start isEmpty. Operand 99 states and 99 transitions. [2018-10-01 03:33:05,634 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2018-10-01 03:33:05,634 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:33:05,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:33:05,919 INFO L134 CoverageAnalysis]: Checked inductivity of 2256 backedges. 0 proven. 2256 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:33:11,065 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:33:11,066 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101 states to 101 states and 101 transitions. [2018-10-01 03:33:11,066 INFO L276 IsEmpty]: Start isEmpty. Operand 101 states and 101 transitions. [2018-10-01 03:33:11,066 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 101 [2018-10-01 03:33:11,067 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:33:11,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:33:11,305 INFO L134 CoverageAnalysis]: Checked inductivity of 2352 backedges. 0 proven. 2352 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:33:12,700 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:33:12,701 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103 states to 103 states and 103 transitions. [2018-10-01 03:33:12,701 INFO L276 IsEmpty]: Start isEmpty. Operand 103 states and 103 transitions. [2018-10-01 03:33:12,702 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-10-01 03:33:12,702 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:33:12,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:33:12,981 INFO L134 CoverageAnalysis]: Checked inductivity of 2450 backedges. 0 proven. 2450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:33:14,262 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:33:14,263 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 105 transitions. [2018-10-01 03:33:14,263 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 105 transitions. [2018-10-01 03:33:14,264 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2018-10-01 03:33:14,264 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:33:14,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:33:14,517 INFO L134 CoverageAnalysis]: Checked inductivity of 2550 backedges. 0 proven. 2550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:33:15,869 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:33:15,870 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 107 states to 107 states and 107 transitions. [2018-10-01 03:33:15,870 INFO L276 IsEmpty]: Start isEmpty. Operand 107 states and 107 transitions. [2018-10-01 03:33:15,871 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 107 [2018-10-01 03:33:15,871 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:33:15,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:33:16,362 INFO L134 CoverageAnalysis]: Checked inductivity of 2652 backedges. 0 proven. 2652 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:33:17,994 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:33:17,994 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 109 states to 109 states and 109 transitions. [2018-10-01 03:33:17,994 INFO L276 IsEmpty]: Start isEmpty. Operand 109 states and 109 transitions. [2018-10-01 03:33:17,994 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 109 [2018-10-01 03:33:17,995 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:33:18,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:33:18,253 INFO L134 CoverageAnalysis]: Checked inductivity of 2756 backedges. 0 proven. 2756 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:33:19,641 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:33:19,642 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111 states to 111 states and 111 transitions. [2018-10-01 03:33:19,642 INFO L276 IsEmpty]: Start isEmpty. Operand 111 states and 111 transitions. [2018-10-01 03:33:19,642 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2018-10-01 03:33:19,643 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:33:19,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:33:19,911 INFO L134 CoverageAnalysis]: Checked inductivity of 2862 backedges. 0 proven. 2862 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:33:21,331 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:33:21,331 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 113 transitions. [2018-10-01 03:33:21,331 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 113 transitions. [2018-10-01 03:33:21,332 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 113 [2018-10-01 03:33:21,332 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:33:21,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:33:21,691 INFO L134 CoverageAnalysis]: Checked inductivity of 2970 backedges. 0 proven. 2970 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:33:23,451 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:33:23,451 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 115 transitions. [2018-10-01 03:33:23,451 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 115 transitions. [2018-10-01 03:33:23,452 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 115 [2018-10-01 03:33:23,452 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:33:23,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:33:23,905 INFO L134 CoverageAnalysis]: Checked inductivity of 3080 backedges. 0 proven. 3080 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:33:25,424 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:33:25,424 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 117 transitions. [2018-10-01 03:33:25,424 INFO L276 IsEmpty]: Start isEmpty. Operand 117 states and 117 transitions. [2018-10-01 03:33:25,425 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 117 [2018-10-01 03:33:25,425 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:33:25,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:33:26,833 INFO L134 CoverageAnalysis]: Checked inductivity of 3192 backedges. 0 proven. 3192 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:33:28,592 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:33:28,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 119 states to 119 states and 119 transitions. [2018-10-01 03:33:28,592 INFO L276 IsEmpty]: Start isEmpty. Operand 119 states and 119 transitions. [2018-10-01 03:33:28,593 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 119 [2018-10-01 03:33:28,593 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:33:28,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:33:29,513 INFO L134 CoverageAnalysis]: Checked inductivity of 3306 backedges. 0 proven. 3306 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:33:31,117 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:33:31,118 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 121 states to 121 states and 121 transitions. [2018-10-01 03:33:31,118 INFO L276 IsEmpty]: Start isEmpty. Operand 121 states and 121 transitions. [2018-10-01 03:33:31,118 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-10-01 03:33:31,118 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:33:31,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:33:31,606 INFO L134 CoverageAnalysis]: Checked inductivity of 3422 backedges. 0 proven. 3422 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:33:33,400 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:33:33,400 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 123 states to 123 states and 123 transitions. [2018-10-01 03:33:33,400 INFO L276 IsEmpty]: Start isEmpty. Operand 123 states and 123 transitions. [2018-10-01 03:33:33,401 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-10-01 03:33:33,401 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:33:33,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:33:33,739 INFO L134 CoverageAnalysis]: Checked inductivity of 3540 backedges. 0 proven. 3540 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:33:35,407 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:33:35,407 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125 states to 125 states and 125 transitions. [2018-10-01 03:33:35,407 INFO L276 IsEmpty]: Start isEmpty. Operand 125 states and 125 transitions. [2018-10-01 03:33:35,408 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 125 [2018-10-01 03:33:35,408 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:33:35,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:33:35,829 INFO L134 CoverageAnalysis]: Checked inductivity of 3660 backedges. 0 proven. 3660 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:33:37,499 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:33:37,500 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 127 states to 127 states and 127 transitions. [2018-10-01 03:33:37,500 INFO L276 IsEmpty]: Start isEmpty. Operand 127 states and 127 transitions. [2018-10-01 03:33:37,500 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 127 [2018-10-01 03:33:37,501 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:33:37,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:33:37,848 INFO L134 CoverageAnalysis]: Checked inductivity of 3782 backedges. 0 proven. 3782 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:33:39,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:33:39,534 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 129 states to 129 states and 129 transitions. [2018-10-01 03:33:39,534 INFO L276 IsEmpty]: Start isEmpty. Operand 129 states and 129 transitions. [2018-10-01 03:33:39,534 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2018-10-01 03:33:39,534 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:33:39,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:33:39,868 INFO L134 CoverageAnalysis]: Checked inductivity of 3906 backedges. 0 proven. 3906 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:33:41,588 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:33:41,589 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 131 states to 131 states and 131 transitions. [2018-10-01 03:33:41,589 INFO L276 IsEmpty]: Start isEmpty. Operand 131 states and 131 transitions. [2018-10-01 03:33:41,590 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 131 [2018-10-01 03:33:41,590 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:33:41,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:33:41,917 INFO L134 CoverageAnalysis]: Checked inductivity of 4032 backedges. 0 proven. 4032 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:33:43,894 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:33:43,894 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 133 states to 133 states and 133 transitions. [2018-10-01 03:33:43,894 INFO L276 IsEmpty]: Start isEmpty. Operand 133 states and 133 transitions. [2018-10-01 03:33:43,895 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2018-10-01 03:33:43,895 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:33:43,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:33:44,251 INFO L134 CoverageAnalysis]: Checked inductivity of 4160 backedges. 0 proven. 4160 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:33:46,186 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:33:46,187 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135 states to 135 states and 135 transitions. [2018-10-01 03:33:46,187 INFO L276 IsEmpty]: Start isEmpty. Operand 135 states and 135 transitions. [2018-10-01 03:33:46,188 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2018-10-01 03:33:46,188 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:33:46,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:33:46,562 INFO L134 CoverageAnalysis]: Checked inductivity of 4290 backedges. 0 proven. 4290 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:33:48,577 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:33:48,577 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 137 states to 137 states and 137 transitions. [2018-10-01 03:33:48,578 INFO L276 IsEmpty]: Start isEmpty. Operand 137 states and 137 transitions. [2018-10-01 03:33:48,579 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 137 [2018-10-01 03:33:48,579 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:33:48,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:33:48,941 INFO L134 CoverageAnalysis]: Checked inductivity of 4422 backedges. 0 proven. 4422 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:33:50,854 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:33:50,855 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 139 transitions. [2018-10-01 03:33:50,855 INFO L276 IsEmpty]: Start isEmpty. Operand 139 states and 139 transitions. [2018-10-01 03:33:50,856 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 139 [2018-10-01 03:33:50,856 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:33:50,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:33:51,369 INFO L134 CoverageAnalysis]: Checked inductivity of 4556 backedges. 0 proven. 4556 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:33:53,352 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:33:53,352 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 141 transitions. [2018-10-01 03:33:53,352 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 141 transitions. [2018-10-01 03:33:53,353 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 141 [2018-10-01 03:33:53,353 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:33:53,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:33:53,815 INFO L134 CoverageAnalysis]: Checked inductivity of 4692 backedges. 0 proven. 4692 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:33:55,726 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:33:55,727 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 143 states to 143 states and 143 transitions. [2018-10-01 03:33:55,727 INFO L276 IsEmpty]: Start isEmpty. Operand 143 states and 143 transitions. [2018-10-01 03:33:55,728 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 143 [2018-10-01 03:33:55,728 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:33:55,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:33:56,096 INFO L134 CoverageAnalysis]: Checked inductivity of 4830 backedges. 0 proven. 4830 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:33:58,036 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:33:58,036 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 145 states to 145 states and 145 transitions. [2018-10-01 03:33:58,037 INFO L276 IsEmpty]: Start isEmpty. Operand 145 states and 145 transitions. [2018-10-01 03:33:58,037 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 145 [2018-10-01 03:33:58,037 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:33:58,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:33:58,515 INFO L134 CoverageAnalysis]: Checked inductivity of 4970 backedges. 0 proven. 4970 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:34:00,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:34:00,512 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147 states to 147 states and 147 transitions. [2018-10-01 03:34:00,512 INFO L276 IsEmpty]: Start isEmpty. Operand 147 states and 147 transitions. [2018-10-01 03:34:00,513 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 147 [2018-10-01 03:34:00,513 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:34:00,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:34:00,913 INFO L134 CoverageAnalysis]: Checked inductivity of 5112 backedges. 0 proven. 5112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:34:02,962 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:34:02,963 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 149 transitions. [2018-10-01 03:34:02,963 INFO L276 IsEmpty]: Start isEmpty. Operand 149 states and 149 transitions. [2018-10-01 03:34:02,964 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 149 [2018-10-01 03:34:02,964 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:34:03,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:34:03,447 INFO L134 CoverageAnalysis]: Checked inductivity of 5256 backedges. 0 proven. 5256 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:34:05,570 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:34:05,571 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 151 states to 151 states and 151 transitions. [2018-10-01 03:34:05,571 INFO L276 IsEmpty]: Start isEmpty. Operand 151 states and 151 transitions. [2018-10-01 03:34:05,572 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-10-01 03:34:05,572 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:34:05,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:34:06,012 INFO L134 CoverageAnalysis]: Checked inductivity of 5402 backedges. 0 proven. 5402 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:34:08,167 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:34:08,168 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 153 states to 153 states and 153 transitions. [2018-10-01 03:34:08,168 INFO L276 IsEmpty]: Start isEmpty. Operand 153 states and 153 transitions. [2018-10-01 03:34:08,168 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 153 [2018-10-01 03:34:08,169 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:34:08,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:34:08,576 INFO L134 CoverageAnalysis]: Checked inductivity of 5550 backedges. 0 proven. 5550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:34:10,758 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:34:10,758 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 155 states to 155 states and 155 transitions. [2018-10-01 03:34:10,758 INFO L276 IsEmpty]: Start isEmpty. Operand 155 states and 155 transitions. [2018-10-01 03:34:10,759 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 155 [2018-10-01 03:34:10,759 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:34:10,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:34:11,279 INFO L134 CoverageAnalysis]: Checked inductivity of 5700 backedges. 0 proven. 5700 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:34:13,455 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:34:13,455 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 157 states to 157 states and 157 transitions. [2018-10-01 03:34:13,456 INFO L276 IsEmpty]: Start isEmpty. Operand 157 states and 157 transitions. [2018-10-01 03:34:13,456 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 157 [2018-10-01 03:34:13,456 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:34:13,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:34:13,880 INFO L134 CoverageAnalysis]: Checked inductivity of 5852 backedges. 0 proven. 5852 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:34:16,117 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:34:16,117 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 159 states to 159 states and 159 transitions. [2018-10-01 03:34:16,117 INFO L276 IsEmpty]: Start isEmpty. Operand 159 states and 159 transitions. [2018-10-01 03:34:16,118 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 159 [2018-10-01 03:34:16,118 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:34:16,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:34:16,591 INFO L134 CoverageAnalysis]: Checked inductivity of 6006 backedges. 0 proven. 6006 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:34:18,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:34:18,893 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 161 states to 161 states and 161 transitions. [2018-10-01 03:34:18,894 INFO L276 IsEmpty]: Start isEmpty. Operand 161 states and 161 transitions. [2018-10-01 03:34:18,894 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 161 [2018-10-01 03:34:18,894 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:34:18,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:34:19,353 INFO L134 CoverageAnalysis]: Checked inductivity of 6162 backedges. 0 proven. 6162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:34:21,729 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:34:21,729 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 163 states to 163 states and 163 transitions. [2018-10-01 03:34:21,729 INFO L276 IsEmpty]: Start isEmpty. Operand 163 states and 163 transitions. [2018-10-01 03:34:21,730 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2018-10-01 03:34:21,730 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:34:21,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:34:22,185 INFO L134 CoverageAnalysis]: Checked inductivity of 6320 backedges. 0 proven. 6320 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:34:24,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:34:24,772 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165 states to 165 states and 165 transitions. [2018-10-01 03:34:24,773 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states and 165 transitions. [2018-10-01 03:34:24,773 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 165 [2018-10-01 03:34:24,773 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:34:24,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:34:25,222 INFO L134 CoverageAnalysis]: Checked inductivity of 6480 backedges. 0 proven. 6480 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:34:27,682 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:34:27,683 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 167 states to 167 states and 167 transitions. [2018-10-01 03:34:27,683 INFO L276 IsEmpty]: Start isEmpty. Operand 167 states and 167 transitions. [2018-10-01 03:34:27,683 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 167 [2018-10-01 03:34:27,684 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:34:27,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:34:28,213 INFO L134 CoverageAnalysis]: Checked inductivity of 6642 backedges. 0 proven. 6642 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:34:30,840 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:34:30,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 169 states to 169 states and 169 transitions. [2018-10-01 03:34:30,841 INFO L276 IsEmpty]: Start isEmpty. Operand 169 states and 169 transitions. [2018-10-01 03:34:30,841 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2018-10-01 03:34:30,841 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:34:30,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:34:31,563 INFO L134 CoverageAnalysis]: Checked inductivity of 6806 backedges. 0 proven. 6806 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:34:34,080 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:34:34,081 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 171 states to 171 states and 171 transitions. [2018-10-01 03:34:34,081 INFO L276 IsEmpty]: Start isEmpty. Operand 171 states and 171 transitions. [2018-10-01 03:34:34,082 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 171 [2018-10-01 03:34:34,082 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:34:34,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:34:34,569 INFO L134 CoverageAnalysis]: Checked inductivity of 6972 backedges. 0 proven. 6972 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:34:37,061 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:34:37,061 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 173 states to 173 states and 173 transitions. [2018-10-01 03:34:37,061 INFO L276 IsEmpty]: Start isEmpty. Operand 173 states and 173 transitions. [2018-10-01 03:34:37,062 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 173 [2018-10-01 03:34:37,062 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:34:37,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:34:37,541 INFO L134 CoverageAnalysis]: Checked inductivity of 7140 backedges. 0 proven. 7140 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:34:40,286 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:34:40,287 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 175 states to 175 states and 175 transitions. [2018-10-01 03:34:40,287 INFO L276 IsEmpty]: Start isEmpty. Operand 175 states and 175 transitions. [2018-10-01 03:34:40,287 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 175 [2018-10-01 03:34:40,288 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:34:40,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:34:40,791 INFO L134 CoverageAnalysis]: Checked inductivity of 7310 backedges. 0 proven. 7310 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:34:43,422 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:34:43,422 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 177 states to 177 states and 177 transitions. [2018-10-01 03:34:43,423 INFO L276 IsEmpty]: Start isEmpty. Operand 177 states and 177 transitions. [2018-10-01 03:34:43,423 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 177 [2018-10-01 03:34:43,423 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:34:43,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:34:44,028 INFO L134 CoverageAnalysis]: Checked inductivity of 7482 backedges. 0 proven. 7482 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:34:46,701 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:34:46,701 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 179 states to 179 states and 179 transitions. [2018-10-01 03:34:46,701 INFO L276 IsEmpty]: Start isEmpty. Operand 179 states and 179 transitions. [2018-10-01 03:34:46,702 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2018-10-01 03:34:46,702 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:34:46,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:34:47,199 INFO L134 CoverageAnalysis]: Checked inductivity of 7656 backedges. 0 proven. 7656 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:34:49,916 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:34:49,916 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 181 states to 181 states and 181 transitions. [2018-10-01 03:34:49,916 INFO L276 IsEmpty]: Start isEmpty. Operand 181 states and 181 transitions. [2018-10-01 03:34:49,917 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 181 [2018-10-01 03:34:49,917 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:34:49,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:34:50,410 INFO L134 CoverageAnalysis]: Checked inductivity of 7832 backedges. 0 proven. 7832 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:34:53,069 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:34:53,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 183 states to 183 states and 183 transitions. [2018-10-01 03:34:53,070 INFO L276 IsEmpty]: Start isEmpty. Operand 183 states and 183 transitions. [2018-10-01 03:34:53,070 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 183 [2018-10-01 03:34:53,070 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:34:53,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:34:53,562 INFO L134 CoverageAnalysis]: Checked inductivity of 8010 backedges. 0 proven. 8010 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:34:56,461 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:34:56,461 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 185 states to 185 states and 185 transitions. [2018-10-01 03:34:56,461 INFO L276 IsEmpty]: Start isEmpty. Operand 185 states and 185 transitions. [2018-10-01 03:34:56,462 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 185 [2018-10-01 03:34:56,462 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:34:56,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:34:56,949 INFO L134 CoverageAnalysis]: Checked inductivity of 8190 backedges. 0 proven. 8190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:34:59,691 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:34:59,692 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 187 states to 187 states and 187 transitions. [2018-10-01 03:34:59,692 INFO L276 IsEmpty]: Start isEmpty. Operand 187 states and 187 transitions. [2018-10-01 03:34:59,693 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 187 [2018-10-01 03:34:59,693 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:34:59,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:35:00,238 INFO L134 CoverageAnalysis]: Checked inductivity of 8372 backedges. 0 proven. 8372 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:35:02,996 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:35:02,997 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 189 states to 189 states and 189 transitions. [2018-10-01 03:35:02,997 INFO L276 IsEmpty]: Start isEmpty. Operand 189 states and 189 transitions. [2018-10-01 03:35:02,998 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 189 [2018-10-01 03:35:02,998 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:35:03,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:35:03,598 INFO L134 CoverageAnalysis]: Checked inductivity of 8556 backedges. 0 proven. 8556 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:35:06,594 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:35:06,595 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 191 states to 191 states and 191 transitions. [2018-10-01 03:35:06,595 INFO L276 IsEmpty]: Start isEmpty. Operand 191 states and 191 transitions. [2018-10-01 03:35:06,595 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 191 [2018-10-01 03:35:06,596 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:35:06,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:35:07,155 INFO L134 CoverageAnalysis]: Checked inductivity of 8742 backedges. 0 proven. 8742 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:35:10,011 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:35:10,011 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 193 states to 193 states and 193 transitions. [2018-10-01 03:35:10,011 INFO L276 IsEmpty]: Start isEmpty. Operand 193 states and 193 transitions. [2018-10-01 03:35:10,012 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 193 [2018-10-01 03:35:10,012 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:35:10,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:35:10,577 INFO L134 CoverageAnalysis]: Checked inductivity of 8930 backedges. 0 proven. 8930 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:35:13,499 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:35:13,499 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195 states to 195 states and 195 transitions. [2018-10-01 03:35:13,499 INFO L276 IsEmpty]: Start isEmpty. Operand 195 states and 195 transitions. [2018-10-01 03:35:13,500 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 195 [2018-10-01 03:35:13,500 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:35:13,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:35:14,053 INFO L134 CoverageAnalysis]: Checked inductivity of 9120 backedges. 0 proven. 9120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:35:17,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:35:17,149 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 197 states to 197 states and 197 transitions. [2018-10-01 03:35:17,149 INFO L276 IsEmpty]: Start isEmpty. Operand 197 states and 197 transitions. [2018-10-01 03:35:17,150 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 197 [2018-10-01 03:35:17,150 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:35:17,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:35:17,738 INFO L134 CoverageAnalysis]: Checked inductivity of 9312 backedges. 0 proven. 9312 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:35:20,648 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:35:20,649 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 199 states to 199 states and 199 transitions. [2018-10-01 03:35:20,649 INFO L276 IsEmpty]: Start isEmpty. Operand 199 states and 199 transitions. [2018-10-01 03:35:20,649 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 199 [2018-10-01 03:35:20,649 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:35:20,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:35:21,283 INFO L134 CoverageAnalysis]: Checked inductivity of 9506 backedges. 0 proven. 9506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:35:24,236 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:35:24,237 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 201 states to 201 states and 201 transitions. [2018-10-01 03:35:24,237 INFO L276 IsEmpty]: Start isEmpty. Operand 201 states and 201 transitions. [2018-10-01 03:35:24,237 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 201 [2018-10-01 03:35:24,237 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:35:24,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-01 03:35:24,944 INFO L134 CoverageAnalysis]: Checked inductivity of 9702 backedges. 0 proven. 9702 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-01 03:35:28,037 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-01 03:35:28,037 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 203 states to 203 states and 203 transitions. [2018-10-01 03:35:28,038 INFO L276 IsEmpty]: Start isEmpty. Operand 203 states and 203 transitions. [2018-10-01 03:35:28,038 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 203 [2018-10-01 03:35:28,038 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-01 03:35:29,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-01 03:35:30,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-01 03:35:30,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-01 03:35:31,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-01 03:35:31,316 WARN L491 CodeCheckObserver]: This program is UNSAFE, Check terminated with 0 iterations. [2018-10-01 03:35:31,369 INFO L202 PluginConnector]: Adding new model diamond1.i_3.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck CFG 01.10 03:35:31 ImpRootNode [2018-10-01 03:35:31,370 INFO L132 PluginConnector]: ------------------------ END CodeCheck---------------------------- [2018-10-01 03:35:31,371 INFO L168 Benchmark]: Toolchain (without parser) took 197685.65 ms. Allocated memory was 1.5 GB in the beginning and 1.7 GB in the end (delta: 129.5 MB). Free memory was 1.5 GB in the beginning and 1.5 GB in the end (delta: 19.8 MB). Peak memory consumption was 149.3 MB. Max. memory is 7.1 GB. [2018-10-01 03:35:31,373 INFO L168 Benchmark]: Boogie PL CUP Parser took 0.18 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-10-01 03:35:31,373 INFO L168 Benchmark]: Boogie Procedure Inliner took 40.27 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-10-01 03:35:31,373 INFO L168 Benchmark]: Boogie Preprocessor took 21.68 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-10-01 03:35:31,374 INFO L168 Benchmark]: RCFGBuilder took 317.98 ms. Allocated memory is still 1.5 GB. Free memory was 1.5 GB in the beginning and 1.5 GB in the end (delta: 21.1 MB). Peak memory consumption was 21.1 MB. Max. memory is 7.1 GB. [2018-10-01 03:35:31,375 INFO L168 Benchmark]: CodeCheck took 197300.37 ms. Allocated memory was 1.5 GB in the beginning and 1.7 GB in the end (delta: 129.5 MB). Free memory was 1.5 GB in the beginning and 1.5 GB in the end (delta: -1.4 MB). Peak memory consumption was 128.1 MB. Max. memory is 7.1 GB. [2018-10-01 03:35:31,378 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck: - StatisticsResult: Ultimate CodeCheck benchmark data CFG has 1 procedures, 7 locations, 1 error locations. UNSAFE Result, 197.2s OverallTime, 100 OverallIterations, 0 TraceHistogramMax, 0.0s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 0 SDtfs, -4 SDslu, -8 SDs, 0 SdLazy, -10 SolverSat, -6 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 163.9s Time, PredicateUnifierStatistics: No data available, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=-1occurred in iteration=-1, traceCheckStatistics: 0.1s SsaConstructionTime, 3.6s SatisfiabilityAnalysisTime, 35.0s InterpolantComputationTime, 10300 NumberOfCodeBlocks, 10300 NumberOfCodeBlocksAsserted, 100 NumberOfCheckSat, 9999 ConstructedInterpolants, 0 QuantifiedInterpolants, 9273099 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 99 InterpolantComputations, 1 PerfectInterpolantSequences, 0/323400 InterpolantCoveringCapability, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: No data available, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: No data available, ReuseStatistics: No data available - CounterExampleResult [Line: 38]: assertion can be violated assertion can be violated We found a FailurePath: [L11] havoc main_#res; [L12] havoc main_#t~nondet0, main_#t~post1, main_~x~5, main_~y~5; [L13] main_~x~5 := 0; [L14] main_~y~5 := main_#t~nondet0; [L15] havoc main_#t~nondet0; VAL [main_~x~5=0] [L18] assume true; VAL [main_~x~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=1, main_~y~5=0] [L18] assume true; VAL [main_~x~5=1, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=2, main_~y~5=0] [L18] assume true; VAL [main_~x~5=2, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=3, main_~y~5=0] [L18] assume true; VAL [main_~x~5=3, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=4, main_~y~5=0] [L18] assume true; VAL [main_~x~5=4, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=5, main_~y~5=0] [L18] assume true; VAL [main_~x~5=5, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=6, main_~y~5=0] [L18] assume true; VAL [main_~x~5=6, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=7, main_~y~5=0] [L18] assume true; VAL [main_~x~5=7, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=8, main_~y~5=0] [L18] assume true; VAL [main_~x~5=8, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=9, main_~y~5=0] [L18] assume true; VAL [main_~x~5=9, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=10, main_~y~5=0] [L18] assume true; VAL [main_~x~5=10, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=11, main_~y~5=0] [L18] assume true; VAL [main_~x~5=11, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=12, main_~y~5=0] [L18] assume true; VAL [main_~x~5=12, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=13, main_~y~5=0] [L18] assume true; VAL [main_~x~5=13, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=14, main_~y~5=0] [L18] assume true; VAL [main_~x~5=14, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=15, main_~y~5=0] [L18] assume true; VAL [main_~x~5=15, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=16, main_~y~5=0] [L18] assume true; VAL [main_~x~5=16, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=17, main_~y~5=0] [L18] assume true; VAL [main_~x~5=17, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=18, main_~y~5=0] [L18] assume true; VAL [main_~x~5=18, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=19, main_~y~5=0] [L18] assume true; VAL [main_~x~5=19, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=20, main_~y~5=0] [L18] assume true; VAL [main_~x~5=20, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=21, main_~y~5=0] [L18] assume true; VAL [main_~x~5=21, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=22, main_~y~5=0] [L18] assume true; VAL [main_~x~5=22, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=23, main_~y~5=0] [L18] assume true; VAL [main_~x~5=23, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=24, main_~y~5=0] [L18] assume true; VAL [main_~x~5=24, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=25, main_~y~5=0] [L18] assume true; VAL [main_~x~5=25, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=26, main_~y~5=0] [L18] assume true; VAL [main_~x~5=26, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=27, main_~y~5=0] [L18] assume true; VAL [main_~x~5=27, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=28, main_~y~5=0] [L18] assume true; VAL [main_~x~5=28, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=29, main_~y~5=0] [L18] assume true; VAL [main_~x~5=29, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=30, main_~y~5=0] [L18] assume true; VAL [main_~x~5=30, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=31, main_~y~5=0] [L18] assume true; VAL [main_~x~5=31, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=32, main_~y~5=0] [L18] assume true; VAL [main_~x~5=32, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=33, main_~y~5=0] [L18] assume true; VAL [main_~x~5=33, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=34, main_~y~5=0] [L18] assume true; VAL [main_~x~5=34, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=35, main_~y~5=0] [L18] assume true; VAL [main_~x~5=35, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=36, main_~y~5=0] [L18] assume true; VAL [main_~x~5=36, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=37, main_~y~5=0] [L18] assume true; VAL [main_~x~5=37, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=38, main_~y~5=0] [L18] assume true; VAL [main_~x~5=38, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=39, main_~y~5=0] [L18] assume true; VAL [main_~x~5=39, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=40, main_~y~5=0] [L18] assume true; VAL [main_~x~5=40, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=41, main_~y~5=0] [L18] assume true; VAL [main_~x~5=41, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=42, main_~y~5=0] [L18] assume true; VAL [main_~x~5=42, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=43, main_~y~5=0] [L18] assume true; VAL [main_~x~5=43, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=44, main_~y~5=0] [L18] assume true; VAL [main_~x~5=44, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=45, main_~y~5=0] [L18] assume true; VAL [main_~x~5=45, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=46, main_~y~5=0] [L18] assume true; VAL [main_~x~5=46, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=47, main_~y~5=0] [L18] assume true; VAL [main_~x~5=47, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=48, main_~y~5=0] [L18] assume true; VAL [main_~x~5=48, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=49, main_~y~5=0] [L18] assume true; VAL [main_~x~5=49, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=50, main_~y~5=0] [L18] assume true; VAL [main_~x~5=50, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=51, main_~y~5=0] [L18] assume true; VAL [main_~x~5=51, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=52, main_~y~5=0] [L18] assume true; VAL [main_~x~5=52, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=53, main_~y~5=0] [L18] assume true; VAL [main_~x~5=53, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=54, main_~y~5=0] [L18] assume true; VAL [main_~x~5=54, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=55, main_~y~5=0] [L18] assume true; VAL [main_~x~5=55, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=56, main_~y~5=0] [L18] assume true; VAL [main_~x~5=56, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=57, main_~y~5=0] [L18] assume true; VAL [main_~x~5=57, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=58, main_~y~5=0] [L18] assume true; VAL [main_~x~5=58, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=59, main_~y~5=0] [L18] assume true; VAL [main_~x~5=59, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=60, main_~y~5=0] [L18] assume true; VAL [main_~x~5=60, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=61, main_~y~5=0] [L18] assume true; VAL [main_~x~5=61, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=62, main_~y~5=0] [L18] assume true; VAL [main_~x~5=62, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=63, main_~y~5=0] [L18] assume true; VAL [main_~x~5=63, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=64, main_~y~5=0] [L18] assume true; VAL [main_~x~5=64, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=65, main_~y~5=0] [L18] assume true; VAL [main_~x~5=65, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=66, main_~y~5=0] [L18] assume true; VAL [main_~x~5=66, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=67, main_~y~5=0] [L18] assume true; VAL [main_~x~5=67, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=68, main_~y~5=0] [L18] assume true; VAL [main_~x~5=68, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=69, main_~y~5=0] [L18] assume true; VAL [main_~x~5=69, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=70, main_~y~5=0] [L18] assume true; VAL [main_~x~5=70, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=71, main_~y~5=0] [L18] assume true; VAL [main_~x~5=71, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=72, main_~y~5=0] [L18] assume true; VAL [main_~x~5=72, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=73, main_~y~5=0] [L18] assume true; VAL [main_~x~5=73, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=74, main_~y~5=0] [L18] assume true; VAL [main_~x~5=74, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=75, main_~y~5=0] [L18] assume true; VAL [main_~x~5=75, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=76, main_~y~5=0] [L18] assume true; VAL [main_~x~5=76, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=77, main_~y~5=0] [L18] assume true; VAL [main_~x~5=77, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=78, main_~y~5=0] [L18] assume true; VAL [main_~x~5=78, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=79, main_~y~5=0] [L18] assume true; VAL [main_~x~5=79, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=80, main_~y~5=0] [L18] assume true; VAL [main_~x~5=80, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=81, main_~y~5=0] [L18] assume true; VAL [main_~x~5=81, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=82, main_~y~5=0] [L18] assume true; VAL [main_~x~5=82, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=83, main_~y~5=0] [L18] assume true; VAL [main_~x~5=83, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=84, main_~y~5=0] [L18] assume true; VAL [main_~x~5=84, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=85, main_~y~5=0] [L18] assume true; VAL [main_~x~5=85, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=86, main_~y~5=0] [L18] assume true; VAL [main_~x~5=86, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=87, main_~y~5=0] [L18] assume true; VAL [main_~x~5=87, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=88, main_~y~5=0] [L18] assume true; VAL [main_~x~5=88, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=89, main_~y~5=0] [L18] assume true; VAL [main_~x~5=89, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=90, main_~y~5=0] [L18] assume true; VAL [main_~x~5=90, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=91, main_~y~5=0] [L18] assume true; VAL [main_~x~5=91, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=92, main_~y~5=0] [L18] assume true; VAL [main_~x~5=92, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=93, main_~y~5=0] [L18] assume true; VAL [main_~x~5=93, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=94, main_~y~5=0] [L18] assume true; VAL [main_~x~5=94, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=95, main_~y~5=0] [L18] assume true; VAL [main_~x~5=95, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=96, main_~y~5=0] [L18] assume true; VAL [main_~x~5=96, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=97, main_~y~5=0] [L18] assume true; VAL [main_~x~5=97, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=98, main_~y~5=0] [L18] assume true; VAL [main_~x~5=98, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=99, main_~y~5=0] [L18] assume true; VAL [main_~x~5=99, main_~y~5=0] [L23] assume !(main_~x~5 % 4294967296 < 99); [L24] __VERIFIER_assert_#in~cond := (if (if main_~x~5 % 4294967296 < 0 && main_~x~5 % 4294967296 % 2 != 0 then main_~x~5 % 4294967296 % 2 - 2 else main_~x~5 % 4294967296 % 2) % 4294967296 == (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 then 1 else 0); [L25] havoc __VERIFIER_assert_~cond; [L26] __VERIFIER_assert_~cond := __VERIFIER_assert_#in~cond; [L27] assume __VERIFIER_assert_~cond == 0; [L28] assume !false; VAL [__VERIFIER_assert_#in~cond=0, __VERIFIER_assert_~cond=0, main_~x~5=99, main_~y~5=0] [L38] assert false; VAL [__VERIFIER_assert_#in~cond=0, __VERIFIER_assert_~cond=0, main_~x~5=99, main_~y~5=0] * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * Boogie PL CUP Parser took 0.18 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. * Boogie Procedure Inliner took 40.27 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. * Boogie Preprocessor took 21.68 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. * RCFGBuilder took 317.98 ms. Allocated memory is still 1.5 GB. Free memory was 1.5 GB in the beginning and 1.5 GB in the end (delta: 21.1 MB). Peak memory consumption was 21.1 MB. Max. memory is 7.1 GB. * CodeCheck took 197300.37 ms. Allocated memory was 1.5 GB in the beginning and 1.7 GB in the end (delta: 129.5 MB). Free memory was 1.5 GB in the beginning and 1.5 GB in the end (delta: -1.4 MB). Peak memory consumption was 128.1 MB. Max. memory is 7.1 GB. RESULT: Ultimate proved your program to be incorrect! Written .csv to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/csv/diamond1.i_3.bpl_svcomp-Reach-32bit-Kojak_Default_PUPT.epf_KojakBplInline.xml/Csv-CodeCheckBenchmarks-0-2018-10-01_03-35-31-390.csv Written .csv to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/csv/diamond1.i_3.bpl_svcomp-Reach-32bit-Kojak_Default_PUPT.epf_KojakBplInline.xml/Csv-Benchmark-0-2018-10-01_03-35-31-390.csv Received shutdown request...