java -Xmx8000000000 -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data --generate-csv --csv-dir csv -tc ../../../trunk/examples/toolchains/KojakBplInline.xml -s ../../../trunk/examples/settings/pu-bench/svcomp-Reach-32bit-Kojak_Default_PUPT.epf -i ../../../trunk/examples/programs/20170304-DifficultPathPrograms/diamond1.i_3.bpl -------------------------------------------------------------------------------- This is Ultimate 0.1.23-2eb0a67 [2018-10-03 10:10:14,574 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-10-03 10:10:14,576 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-10-03 10:10:14,588 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-10-03 10:10:14,588 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-10-03 10:10:14,590 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-10-03 10:10:14,591 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-10-03 10:10:14,593 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-10-03 10:10:14,594 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-10-03 10:10:14,595 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-10-03 10:10:14,596 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-10-03 10:10:14,596 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-10-03 10:10:14,597 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-10-03 10:10:14,598 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-10-03 10:10:14,599 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-10-03 10:10:14,600 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-10-03 10:10:14,601 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-10-03 10:10:14,603 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-10-03 10:10:14,605 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-10-03 10:10:14,607 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-10-03 10:10:14,608 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-10-03 10:10:14,609 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-10-03 10:10:14,612 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-10-03 10:10:14,612 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-10-03 10:10:14,612 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-10-03 10:10:14,613 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-10-03 10:10:14,614 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-10-03 10:10:14,615 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-10-03 10:10:14,616 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-10-03 10:10:14,617 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-10-03 10:10:14,617 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-10-03 10:10:14,618 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-10-03 10:10:14,618 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-10-03 10:10:14,619 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-10-03 10:10:14,620 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-10-03 10:10:14,621 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-10-03 10:10:14,621 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/pu-bench/svcomp-Reach-32bit-Kojak_Default_PUPT.epf [2018-10-03 10:10:14,640 INFO L110 SettingsManager]: Loading preferences was successful [2018-10-03 10:10:14,640 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-10-03 10:10:14,641 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-10-03 10:10:14,641 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-10-03 10:10:14,642 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-10-03 10:10:14,642 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-10-03 10:10:14,642 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-10-03 10:10:14,642 INFO L133 SettingsManager]: * sizeof long=4 [2018-10-03 10:10:14,643 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-10-03 10:10:14,643 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-10-03 10:10:14,643 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-10-03 10:10:14,643 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-10-03 10:10:14,643 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-10-03 10:10:14,644 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-10-03 10:10:14,644 INFO L133 SettingsManager]: * sizeof long double=12 [2018-10-03 10:10:14,644 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-10-03 10:10:14,644 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-10-03 10:10:14,644 INFO L131 SettingsManager]: Preferences of CodeCheck differ from their defaults: [2018-10-03 10:10:14,645 INFO L133 SettingsManager]: * Timeout in seconds=1000000 [2018-10-03 10:10:14,645 INFO L133 SettingsManager]: * Use predicate trie based predicate unification=true [2018-10-03 10:10:14,645 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-10-03 10:10:14,645 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-10-03 10:10:14,645 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 [2018-10-03 10:10:14,646 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-10-03 10:10:14,646 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-10-03 10:10:14,646 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-10-03 10:10:14,646 INFO L133 SettingsManager]: * Trace refinement strategy=PENGUIN [2018-10-03 10:10:14,646 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-10-03 10:10:14,646 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-10-03 10:10:14,647 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-10-03 10:10:14,703 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-10-03 10:10:14,717 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-10-03 10:10:14,726 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-10-03 10:10:14,728 INFO L271 PluginConnector]: Initializing Boogie PL CUP Parser... [2018-10-03 10:10:14,729 INFO L276 PluginConnector]: Boogie PL CUP Parser initialized [2018-10-03 10:10:14,730 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/programs/20170304-DifficultPathPrograms/diamond1.i_3.bpl [2018-10-03 10:10:14,731 INFO L111 BoogieParser]: Parsing: '/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/programs/20170304-DifficultPathPrograms/diamond1.i_3.bpl' [2018-10-03 10:10:14,801 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-10-03 10:10:14,804 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-10-03 10:10:14,805 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-10-03 10:10:14,805 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-10-03 10:10:14,806 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-10-03 10:10:14,828 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "diamond1.i_3.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 03.10 10:10:14" (1/1) ... [2018-10-03 10:10:14,841 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "diamond1.i_3.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 03.10 10:10:14" (1/1) ... [2018-10-03 10:10:14,848 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-10-03 10:10:14,850 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-10-03 10:10:14,850 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-10-03 10:10:14,850 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-10-03 10:10:14,862 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "diamond1.i_3.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 03.10 10:10:14" (1/1) ... [2018-10-03 10:10:14,862 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "diamond1.i_3.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 03.10 10:10:14" (1/1) ... [2018-10-03 10:10:14,863 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "diamond1.i_3.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 03.10 10:10:14" (1/1) ... [2018-10-03 10:10:14,863 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "diamond1.i_3.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 03.10 10:10:14" (1/1) ... [2018-10-03 10:10:14,866 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "diamond1.i_3.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 03.10 10:10:14" (1/1) ... [2018-10-03 10:10:14,869 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "diamond1.i_3.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 03.10 10:10:14" (1/1) ... [2018-10-03 10:10:14,870 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "diamond1.i_3.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 03.10 10:10:14" (1/1) ... [2018-10-03 10:10:14,871 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-10-03 10:10:14,872 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-10-03 10:10:14,872 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-10-03 10:10:14,872 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-10-03 10:10:14,873 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "diamond1.i_3.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 03.10 10:10:14" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 [2018-10-03 10:10:14,942 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-10-03 10:10:14,942 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-10-03 10:10:15,184 INFO L340 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-10-03 10:10:15,185 INFO L202 PluginConnector]: Adding new model diamond1.i_3.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.10 10:10:15 BoogieIcfgContainer [2018-10-03 10:10:15,185 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-10-03 10:10:15,186 INFO L113 PluginConnector]: ------------------------CodeCheck---------------------------- [2018-10-03 10:10:15,186 INFO L271 PluginConnector]: Initializing CodeCheck... [2018-10-03 10:10:15,197 INFO L276 PluginConnector]: CodeCheck initialized [2018-10-03 10:10:15,198 INFO L185 PluginConnector]: Executing the observer CodeCheckObserver from plugin CodeCheck for "diamond1.i_3.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.10 10:10:15" (1/1) ... [2018-10-03 10:10:15,210 INFO L106 BPredicateUnifier]: Initialized predicate-trie based predicate unifier [2018-10-03 10:10:15,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:15,244 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 6 transitions. [2018-10-03 10:10:15,245 INFO L276 IsEmpty]: Start isEmpty. Operand 6 states and 6 transitions. [2018-10-03 10:10:15,248 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2018-10-03 10:10:15,248 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:15,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:15,430 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:15,732 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:15,733 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 7 transitions. [2018-10-03 10:10:15,733 INFO L276 IsEmpty]: Start isEmpty. Operand 7 states and 7 transitions. [2018-10-03 10:10:15,733 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 7 [2018-10-03 10:10:15,733 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:15,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:15,814 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:16,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:16,216 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 9 transitions. [2018-10-03 10:10:16,216 INFO L276 IsEmpty]: Start isEmpty. Operand 9 states and 9 transitions. [2018-10-03 10:10:16,216 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 9 [2018-10-03 10:10:16,216 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:16,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:16,511 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:16,941 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:16,942 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 11 transitions. [2018-10-03 10:10:16,942 INFO L276 IsEmpty]: Start isEmpty. Operand 11 states and 11 transitions. [2018-10-03 10:10:16,942 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 11 [2018-10-03 10:10:16,943 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:16,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:17,101 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:17,402 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:17,402 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 13 transitions. [2018-10-03 10:10:17,403 INFO L276 IsEmpty]: Start isEmpty. Operand 13 states and 13 transitions. [2018-10-03 10:10:17,403 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-10-03 10:10:17,403 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:17,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:17,754 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:18,144 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:18,145 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 15 transitions. [2018-10-03 10:10:18,145 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 15 transitions. [2018-10-03 10:10:18,146 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-10-03 10:10:18,146 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:18,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:18,311 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:19,018 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:19,019 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 17 transitions. [2018-10-03 10:10:19,019 INFO L276 IsEmpty]: Start isEmpty. Operand 17 states and 17 transitions. [2018-10-03 10:10:19,020 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-10-03 10:10:19,021 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:19,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:19,172 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:19,794 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:19,795 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 19 transitions. [2018-10-03 10:10:19,795 INFO L276 IsEmpty]: Start isEmpty. Operand 19 states and 19 transitions. [2018-10-03 10:10:19,796 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2018-10-03 10:10:19,796 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:19,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:20,074 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 0 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:20,370 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:20,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 21 transitions. [2018-10-03 10:10:20,370 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 21 transitions. [2018-10-03 10:10:20,371 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-10-03 10:10:20,372 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:20,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:20,908 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:21,224 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:21,225 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23 states to 23 states and 23 transitions. [2018-10-03 10:10:21,226 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states and 23 transitions. [2018-10-03 10:10:21,227 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-10-03 10:10:21,227 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:21,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:21,359 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:21,690 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:21,691 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 25 transitions. [2018-10-03 10:10:21,691 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 25 transitions. [2018-10-03 10:10:21,692 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-10-03 10:10:21,692 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:21,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:21,878 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:22,269 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:22,270 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 27 transitions. [2018-10-03 10:10:22,270 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states and 27 transitions. [2018-10-03 10:10:22,271 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-10-03 10:10:22,272 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:22,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:22,448 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 132 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:22,844 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:22,844 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 29 transitions. [2018-10-03 10:10:22,845 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 29 transitions. [2018-10-03 10:10:22,846 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-10-03 10:10:22,846 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:22,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:23,027 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:23,514 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:23,515 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 31 transitions. [2018-10-03 10:10:23,515 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states and 31 transitions. [2018-10-03 10:10:23,517 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2018-10-03 10:10:23,517 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:23,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:23,638 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 182 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:23,976 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:23,977 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 33 transitions. [2018-10-03 10:10:23,977 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 33 transitions. [2018-10-03 10:10:23,979 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-10-03 10:10:23,979 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:23,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:24,348 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 0 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:24,920 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:24,921 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35 states to 35 states and 35 transitions. [2018-10-03 10:10:24,921 INFO L276 IsEmpty]: Start isEmpty. Operand 35 states and 35 transitions. [2018-10-03 10:10:24,922 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-10-03 10:10:24,922 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:24,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:25,028 INFO L134 CoverageAnalysis]: Checked inductivity of 240 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:25,486 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:25,487 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 37 transitions. [2018-10-03 10:10:25,487 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 37 transitions. [2018-10-03 10:10:25,487 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-10-03 10:10:25,487 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:25,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:25,638 INFO L134 CoverageAnalysis]: Checked inductivity of 272 backedges. 0 proven. 272 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:26,085 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:26,086 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 39 transitions. [2018-10-03 10:10:26,086 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 39 transitions. [2018-10-03 10:10:26,087 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-10-03 10:10:26,087 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:26,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:26,328 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 0 proven. 306 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:27,006 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:27,007 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 41 transitions. [2018-10-03 10:10:27,007 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 41 transitions. [2018-10-03 10:10:27,008 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-10-03 10:10:27,008 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:27,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:27,828 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 0 proven. 342 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:29,087 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:29,087 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 43 transitions. [2018-10-03 10:10:29,087 INFO L276 IsEmpty]: Start isEmpty. Operand 43 states and 43 transitions. [2018-10-03 10:10:29,088 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-10-03 10:10:29,088 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:29,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:29,898 INFO L134 CoverageAnalysis]: Checked inductivity of 380 backedges. 0 proven. 380 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:30,392 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:30,393 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 45 transitions. [2018-10-03 10:10:30,393 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 45 transitions. [2018-10-03 10:10:30,394 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-10-03 10:10:30,394 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:30,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:30,635 INFO L134 CoverageAnalysis]: Checked inductivity of 420 backedges. 0 proven. 420 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:31,109 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:31,109 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 47 transitions. [2018-10-03 10:10:31,110 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 47 transitions. [2018-10-03 10:10:31,111 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-10-03 10:10:31,111 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:31,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:31,258 INFO L134 CoverageAnalysis]: Checked inductivity of 462 backedges. 0 proven. 462 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:31,779 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:31,779 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 49 transitions. [2018-10-03 10:10:31,779 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 49 transitions. [2018-10-03 10:10:31,780 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-10-03 10:10:31,780 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:31,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:32,782 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:33,907 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:33,908 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 51 transitions. [2018-10-03 10:10:33,908 INFO L276 IsEmpty]: Start isEmpty. Operand 51 states and 51 transitions. [2018-10-03 10:10:33,909 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-10-03 10:10:33,909 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:33,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:34,080 INFO L134 CoverageAnalysis]: Checked inductivity of 552 backedges. 0 proven. 552 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:34,770 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:34,770 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 53 transitions. [2018-10-03 10:10:34,770 INFO L276 IsEmpty]: Start isEmpty. Operand 53 states and 53 transitions. [2018-10-03 10:10:34,771 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-10-03 10:10:34,771 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:34,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:35,123 INFO L134 CoverageAnalysis]: Checked inductivity of 600 backedges. 0 proven. 600 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:35,792 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:35,792 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 55 transitions. [2018-10-03 10:10:35,792 INFO L276 IsEmpty]: Start isEmpty. Operand 55 states and 55 transitions. [2018-10-03 10:10:35,793 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-10-03 10:10:35,793 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:35,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:36,897 INFO L134 CoverageAnalysis]: Checked inductivity of 650 backedges. 0 proven. 650 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:37,680 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:37,680 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 57 transitions. [2018-10-03 10:10:37,681 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 57 transitions. [2018-10-03 10:10:37,681 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-10-03 10:10:37,681 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:37,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:38,032 INFO L134 CoverageAnalysis]: Checked inductivity of 702 backedges. 0 proven. 702 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:38,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:38,654 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 59 transitions. [2018-10-03 10:10:38,655 INFO L276 IsEmpty]: Start isEmpty. Operand 59 states and 59 transitions. [2018-10-03 10:10:38,655 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-10-03 10:10:38,655 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:38,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:38,884 INFO L134 CoverageAnalysis]: Checked inductivity of 756 backedges. 0 proven. 756 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:39,595 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:39,596 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 61 transitions. [2018-10-03 10:10:39,596 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 61 transitions. [2018-10-03 10:10:39,597 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2018-10-03 10:10:39,597 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:39,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:39,890 INFO L134 CoverageAnalysis]: Checked inductivity of 812 backedges. 0 proven. 812 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:40,726 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:40,726 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 63 transitions. [2018-10-03 10:10:40,727 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 63 transitions. [2018-10-03 10:10:40,728 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-10-03 10:10:40,728 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:40,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:41,122 INFO L134 CoverageAnalysis]: Checked inductivity of 870 backedges. 0 proven. 870 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:41,857 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:41,858 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 65 transitions. [2018-10-03 10:10:41,858 INFO L276 IsEmpty]: Start isEmpty. Operand 65 states and 65 transitions. [2018-10-03 10:10:41,858 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-10-03 10:10:41,859 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:41,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:42,771 INFO L134 CoverageAnalysis]: Checked inductivity of 930 backedges. 0 proven. 930 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:43,567 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:43,567 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 67 transitions. [2018-10-03 10:10:43,567 INFO L276 IsEmpty]: Start isEmpty. Operand 67 states and 67 transitions. [2018-10-03 10:10:43,567 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-10-03 10:10:43,567 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:43,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:44,579 INFO L134 CoverageAnalysis]: Checked inductivity of 992 backedges. 0 proven. 992 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:45,323 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:45,324 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 69 transitions. [2018-10-03 10:10:45,324 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 69 transitions. [2018-10-03 10:10:45,324 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-10-03 10:10:45,324 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:45,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:45,535 INFO L134 CoverageAnalysis]: Checked inductivity of 1056 backedges. 0 proven. 1056 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:46,299 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:46,300 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71 states to 71 states and 71 transitions. [2018-10-03 10:10:46,300 INFO L276 IsEmpty]: Start isEmpty. Operand 71 states and 71 transitions. [2018-10-03 10:10:46,300 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-10-03 10:10:46,300 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:46,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:46,744 INFO L134 CoverageAnalysis]: Checked inductivity of 1122 backedges. 0 proven. 1122 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:47,544 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:47,544 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 73 transitions. [2018-10-03 10:10:47,545 INFO L276 IsEmpty]: Start isEmpty. Operand 73 states and 73 transitions. [2018-10-03 10:10:47,545 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-10-03 10:10:47,545 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:47,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:48,180 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 0 proven. 1190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:49,171 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:49,172 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 75 transitions. [2018-10-03 10:10:49,172 INFO L276 IsEmpty]: Start isEmpty. Operand 75 states and 75 transitions. [2018-10-03 10:10:49,173 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-10-03 10:10:49,173 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:49,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:49,422 INFO L134 CoverageAnalysis]: Checked inductivity of 1260 backedges. 0 proven. 1260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:50,337 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:50,338 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 77 transitions. [2018-10-03 10:10:50,338 INFO L276 IsEmpty]: Start isEmpty. Operand 77 states and 77 transitions. [2018-10-03 10:10:50,338 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2018-10-03 10:10:50,338 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:50,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:50,613 INFO L134 CoverageAnalysis]: Checked inductivity of 1332 backedges. 0 proven. 1332 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:51,502 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:51,503 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79 states to 79 states and 79 transitions. [2018-10-03 10:10:51,503 INFO L276 IsEmpty]: Start isEmpty. Operand 79 states and 79 transitions. [2018-10-03 10:10:51,503 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2018-10-03 10:10:51,503 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:51,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:52,563 INFO L134 CoverageAnalysis]: Checked inductivity of 1406 backedges. 0 proven. 1406 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:54,911 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:54,912 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 81 transitions. [2018-10-03 10:10:54,912 INFO L276 IsEmpty]: Start isEmpty. Operand 81 states and 81 transitions. [2018-10-03 10:10:54,913 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2018-10-03 10:10:54,913 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:54,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:55,393 INFO L134 CoverageAnalysis]: Checked inductivity of 1482 backedges. 0 proven. 1482 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:56,414 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:56,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 83 transitions. [2018-10-03 10:10:56,414 INFO L276 IsEmpty]: Start isEmpty. Operand 83 states and 83 transitions. [2018-10-03 10:10:56,415 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2018-10-03 10:10:56,415 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:56,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:56,716 INFO L134 CoverageAnalysis]: Checked inductivity of 1560 backedges. 0 proven. 1560 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:57,703 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:57,703 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85 states to 85 states and 85 transitions. [2018-10-03 10:10:57,704 INFO L276 IsEmpty]: Start isEmpty. Operand 85 states and 85 transitions. [2018-10-03 10:10:57,704 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-10-03 10:10:57,704 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:57,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:57,949 INFO L134 CoverageAnalysis]: Checked inductivity of 1640 backedges. 0 proven. 1640 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:10:59,136 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:10:59,137 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 87 transitions. [2018-10-03 10:10:59,137 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 87 transitions. [2018-10-03 10:10:59,138 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-10-03 10:10:59,138 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:10:59,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:10:59,462 INFO L134 CoverageAnalysis]: Checked inductivity of 1722 backedges. 0 proven. 1722 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:11:01,241 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:11:01,241 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 89 transitions. [2018-10-03 10:11:01,242 INFO L276 IsEmpty]: Start isEmpty. Operand 89 states and 89 transitions. [2018-10-03 10:11:01,242 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2018-10-03 10:11:01,242 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:11:01,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:11:01,652 INFO L134 CoverageAnalysis]: Checked inductivity of 1806 backedges. 0 proven. 1806 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:11:02,639 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:11:02,640 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91 states to 91 states and 91 transitions. [2018-10-03 10:11:02,640 INFO L276 IsEmpty]: Start isEmpty. Operand 91 states and 91 transitions. [2018-10-03 10:11:02,640 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-10-03 10:11:02,640 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:11:02,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:11:02,909 INFO L134 CoverageAnalysis]: Checked inductivity of 1892 backedges. 0 proven. 1892 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:11:03,991 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:11:03,992 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 93 transitions. [2018-10-03 10:11:03,992 INFO L276 IsEmpty]: Start isEmpty. Operand 93 states and 93 transitions. [2018-10-03 10:11:03,992 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-10-03 10:11:03,994 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:11:04,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:11:04,274 INFO L134 CoverageAnalysis]: Checked inductivity of 1980 backedges. 0 proven. 1980 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:11:05,377 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:11:05,378 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 95 transitions. [2018-10-03 10:11:05,378 INFO L276 IsEmpty]: Start isEmpty. Operand 95 states and 95 transitions. [2018-10-03 10:11:05,378 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-10-03 10:11:05,378 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:11:05,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:11:05,632 INFO L134 CoverageAnalysis]: Checked inductivity of 2070 backedges. 0 proven. 2070 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:11:06,726 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:11:06,726 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 97 transitions. [2018-10-03 10:11:06,726 INFO L276 IsEmpty]: Start isEmpty. Operand 97 states and 97 transitions. [2018-10-03 10:11:06,727 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-10-03 10:11:06,727 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:11:06,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:11:06,931 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:11:08,054 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:11:08,055 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 99 transitions. [2018-10-03 10:11:08,055 INFO L276 IsEmpty]: Start isEmpty. Operand 99 states and 99 transitions. [2018-10-03 10:11:08,055 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2018-10-03 10:11:08,056 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:11:08,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:11:08,368 INFO L134 CoverageAnalysis]: Checked inductivity of 2256 backedges. 0 proven. 2256 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:11:13,515 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:11:13,516 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101 states to 101 states and 101 transitions. [2018-10-03 10:11:13,516 INFO L276 IsEmpty]: Start isEmpty. Operand 101 states and 101 transitions. [2018-10-03 10:11:13,516 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 101 [2018-10-03 10:11:13,516 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:11:13,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:11:13,746 INFO L134 CoverageAnalysis]: Checked inductivity of 2352 backedges. 0 proven. 2352 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:11:15,002 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:11:15,002 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103 states to 103 states and 103 transitions. [2018-10-03 10:11:15,003 INFO L276 IsEmpty]: Start isEmpty. Operand 103 states and 103 transitions. [2018-10-03 10:11:15,003 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-10-03 10:11:15,003 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:11:15,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:11:15,258 INFO L134 CoverageAnalysis]: Checked inductivity of 2450 backedges. 0 proven. 2450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:11:16,551 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:11:16,551 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 105 transitions. [2018-10-03 10:11:16,552 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 105 transitions. [2018-10-03 10:11:16,552 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2018-10-03 10:11:16,552 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:11:16,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:11:16,780 INFO L134 CoverageAnalysis]: Checked inductivity of 2550 backedges. 0 proven. 2550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:11:18,121 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:11:18,121 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 107 states to 107 states and 107 transitions. [2018-10-03 10:11:18,122 INFO L276 IsEmpty]: Start isEmpty. Operand 107 states and 107 transitions. [2018-10-03 10:11:18,122 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 107 [2018-10-03 10:11:18,122 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:11:18,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:11:18,555 INFO L134 CoverageAnalysis]: Checked inductivity of 2652 backedges. 0 proven. 2652 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:11:19,997 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:11:19,998 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 109 states to 109 states and 109 transitions. [2018-10-03 10:11:19,998 INFO L276 IsEmpty]: Start isEmpty. Operand 109 states and 109 transitions. [2018-10-03 10:11:19,999 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 109 [2018-10-03 10:11:19,999 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:11:20,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:11:20,226 INFO L134 CoverageAnalysis]: Checked inductivity of 2756 backedges. 0 proven. 2756 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:11:21,541 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:11:21,542 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111 states to 111 states and 111 transitions. [2018-10-03 10:11:21,542 INFO L276 IsEmpty]: Start isEmpty. Operand 111 states and 111 transitions. [2018-10-03 10:11:21,543 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2018-10-03 10:11:21,543 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:11:21,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:11:21,758 INFO L134 CoverageAnalysis]: Checked inductivity of 2862 backedges. 0 proven. 2862 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:11:23,118 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:11:23,118 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 113 transitions. [2018-10-03 10:11:23,118 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 113 transitions. [2018-10-03 10:11:23,119 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 113 [2018-10-03 10:11:23,119 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:11:23,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:11:24,128 INFO L134 CoverageAnalysis]: Checked inductivity of 2970 backedges. 0 proven. 2970 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:11:25,553 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:11:25,553 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 115 transitions. [2018-10-03 10:11:25,554 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 115 transitions. [2018-10-03 10:11:25,554 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 115 [2018-10-03 10:11:25,554 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:11:25,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:11:25,928 INFO L134 CoverageAnalysis]: Checked inductivity of 3080 backedges. 0 proven. 3080 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:11:27,343 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:11:27,343 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 117 transitions. [2018-10-03 10:11:27,343 INFO L276 IsEmpty]: Start isEmpty. Operand 117 states and 117 transitions. [2018-10-03 10:11:27,344 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 117 [2018-10-03 10:11:27,344 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:11:27,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:11:27,609 INFO L134 CoverageAnalysis]: Checked inductivity of 3192 backedges. 0 proven. 3192 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:11:29,216 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:11:29,217 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 119 states to 119 states and 119 transitions. [2018-10-03 10:11:29,217 INFO L276 IsEmpty]: Start isEmpty. Operand 119 states and 119 transitions. [2018-10-03 10:11:29,217 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 119 [2018-10-03 10:11:29,217 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:11:29,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:11:29,752 INFO L134 CoverageAnalysis]: Checked inductivity of 3306 backedges. 0 proven. 3306 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:11:31,323 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:11:31,323 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 121 states to 121 states and 121 transitions. [2018-10-03 10:11:31,323 INFO L276 IsEmpty]: Start isEmpty. Operand 121 states and 121 transitions. [2018-10-03 10:11:31,324 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-10-03 10:11:31,324 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:11:31,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:11:32,256 INFO L134 CoverageAnalysis]: Checked inductivity of 3422 backedges. 0 proven. 3422 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:11:33,830 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:11:33,831 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 123 states to 123 states and 123 transitions. [2018-10-03 10:11:33,831 INFO L276 IsEmpty]: Start isEmpty. Operand 123 states and 123 transitions. [2018-10-03 10:11:33,831 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-10-03 10:11:33,831 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:11:33,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:11:34,263 INFO L134 CoverageAnalysis]: Checked inductivity of 3540 backedges. 0 proven. 3540 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:11:35,837 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:11:35,838 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125 states to 125 states and 125 transitions. [2018-10-03 10:11:35,838 INFO L276 IsEmpty]: Start isEmpty. Operand 125 states and 125 transitions. [2018-10-03 10:11:35,839 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 125 [2018-10-03 10:11:35,839 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:11:35,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:11:36,082 INFO L134 CoverageAnalysis]: Checked inductivity of 3660 backedges. 0 proven. 3660 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:11:37,741 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:11:37,742 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 127 states to 127 states and 127 transitions. [2018-10-03 10:11:37,742 INFO L276 IsEmpty]: Start isEmpty. Operand 127 states and 127 transitions. [2018-10-03 10:11:37,742 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 127 [2018-10-03 10:11:37,743 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:11:37,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:11:38,030 INFO L134 CoverageAnalysis]: Checked inductivity of 3782 backedges. 0 proven. 3782 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:11:39,829 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:11:39,829 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 129 states to 129 states and 129 transitions. [2018-10-03 10:11:39,829 INFO L276 IsEmpty]: Start isEmpty. Operand 129 states and 129 transitions. [2018-10-03 10:11:39,830 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2018-10-03 10:11:39,830 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:11:39,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:11:40,121 INFO L134 CoverageAnalysis]: Checked inductivity of 3906 backedges. 0 proven. 3906 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:11:41,860 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:11:41,861 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 131 states to 131 states and 131 transitions. [2018-10-03 10:11:41,861 INFO L276 IsEmpty]: Start isEmpty. Operand 131 states and 131 transitions. [2018-10-03 10:11:41,861 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 131 [2018-10-03 10:11:41,861 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:11:41,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:11:42,119 INFO L134 CoverageAnalysis]: Checked inductivity of 4032 backedges. 0 proven. 4032 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:11:43,854 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:11:43,854 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 133 states to 133 states and 133 transitions. [2018-10-03 10:11:43,855 INFO L276 IsEmpty]: Start isEmpty. Operand 133 states and 133 transitions. [2018-10-03 10:11:43,855 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2018-10-03 10:11:43,855 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:11:43,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:11:44,369 INFO L134 CoverageAnalysis]: Checked inductivity of 4160 backedges. 0 proven. 4160 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:11:46,152 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:11:46,153 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135 states to 135 states and 135 transitions. [2018-10-03 10:11:46,153 INFO L276 IsEmpty]: Start isEmpty. Operand 135 states and 135 transitions. [2018-10-03 10:11:46,154 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2018-10-03 10:11:46,154 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:11:46,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:11:46,423 INFO L134 CoverageAnalysis]: Checked inductivity of 4290 backedges. 0 proven. 4290 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:11:48,259 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:11:48,259 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 137 states to 137 states and 137 transitions. [2018-10-03 10:11:48,259 INFO L276 IsEmpty]: Start isEmpty. Operand 137 states and 137 transitions. [2018-10-03 10:11:48,260 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 137 [2018-10-03 10:11:48,260 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:11:48,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:11:48,554 INFO L134 CoverageAnalysis]: Checked inductivity of 4422 backedges. 0 proven. 4422 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:11:50,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:11:50,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 139 transitions. [2018-10-03 10:11:50,655 INFO L276 IsEmpty]: Start isEmpty. Operand 139 states and 139 transitions. [2018-10-03 10:11:50,655 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 139 [2018-10-03 10:11:50,655 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:11:50,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:11:51,130 INFO L134 CoverageAnalysis]: Checked inductivity of 4556 backedges. 0 proven. 4556 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:11:53,056 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:11:53,056 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 141 transitions. [2018-10-03 10:11:53,056 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 141 transitions. [2018-10-03 10:11:53,057 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 141 [2018-10-03 10:11:53,057 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:11:53,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:11:53,375 INFO L134 CoverageAnalysis]: Checked inductivity of 4692 backedges. 0 proven. 4692 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:11:55,495 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:11:55,496 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 143 states to 143 states and 143 transitions. [2018-10-03 10:11:55,496 INFO L276 IsEmpty]: Start isEmpty. Operand 143 states and 143 transitions. [2018-10-03 10:11:55,497 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 143 [2018-10-03 10:11:55,497 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:11:55,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:11:55,859 INFO L134 CoverageAnalysis]: Checked inductivity of 4830 backedges. 0 proven. 4830 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:11:57,850 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:11:57,851 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 145 states to 145 states and 145 transitions. [2018-10-03 10:11:57,851 INFO L276 IsEmpty]: Start isEmpty. Operand 145 states and 145 transitions. [2018-10-03 10:11:57,851 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 145 [2018-10-03 10:11:57,851 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:11:57,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:11:58,211 INFO L134 CoverageAnalysis]: Checked inductivity of 4970 backedges. 0 proven. 4970 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:12:00,282 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:12:00,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147 states to 147 states and 147 transitions. [2018-10-03 10:12:00,283 INFO L276 IsEmpty]: Start isEmpty. Operand 147 states and 147 transitions. [2018-10-03 10:12:00,284 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 147 [2018-10-03 10:12:00,284 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:12:00,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:12:00,605 INFO L134 CoverageAnalysis]: Checked inductivity of 5112 backedges. 0 proven. 5112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:12:02,591 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:12:02,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 149 transitions. [2018-10-03 10:12:02,592 INFO L276 IsEmpty]: Start isEmpty. Operand 149 states and 149 transitions. [2018-10-03 10:12:02,592 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 149 [2018-10-03 10:12:02,592 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:12:02,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:12:02,961 INFO L134 CoverageAnalysis]: Checked inductivity of 5256 backedges. 0 proven. 5256 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:12:05,031 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:12:05,031 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 151 states to 151 states and 151 transitions. [2018-10-03 10:12:05,031 INFO L276 IsEmpty]: Start isEmpty. Operand 151 states and 151 transitions. [2018-10-03 10:12:05,032 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-10-03 10:12:05,032 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:12:05,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:12:05,439 INFO L134 CoverageAnalysis]: Checked inductivity of 5402 backedges. 0 proven. 5402 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:12:07,541 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:12:07,542 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 153 states to 153 states and 153 transitions. [2018-10-03 10:12:07,542 INFO L276 IsEmpty]: Start isEmpty. Operand 153 states and 153 transitions. [2018-10-03 10:12:07,543 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 153 [2018-10-03 10:12:07,543 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:12:07,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:12:07,897 INFO L134 CoverageAnalysis]: Checked inductivity of 5550 backedges. 0 proven. 5550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:12:10,114 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:12:10,114 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 155 states to 155 states and 155 transitions. [2018-10-03 10:12:10,114 INFO L276 IsEmpty]: Start isEmpty. Operand 155 states and 155 transitions. [2018-10-03 10:12:10,115 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 155 [2018-10-03 10:12:10,115 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:12:10,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:12:10,467 INFO L134 CoverageAnalysis]: Checked inductivity of 5700 backedges. 0 proven. 5700 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:12:12,701 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:12:12,701 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 157 states to 157 states and 157 transitions. [2018-10-03 10:12:12,701 INFO L276 IsEmpty]: Start isEmpty. Operand 157 states and 157 transitions. [2018-10-03 10:12:12,702 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 157 [2018-10-03 10:12:12,702 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:12:12,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:12:13,075 INFO L134 CoverageAnalysis]: Checked inductivity of 5852 backedges. 0 proven. 5852 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:12:15,416 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:12:15,416 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 159 states to 159 states and 159 transitions. [2018-10-03 10:12:15,416 INFO L276 IsEmpty]: Start isEmpty. Operand 159 states and 159 transitions. [2018-10-03 10:12:15,417 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 159 [2018-10-03 10:12:15,417 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:12:15,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:12:15,897 INFO L134 CoverageAnalysis]: Checked inductivity of 6006 backedges. 0 proven. 6006 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:12:18,245 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:12:18,245 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 161 states to 161 states and 161 transitions. [2018-10-03 10:12:18,246 INFO L276 IsEmpty]: Start isEmpty. Operand 161 states and 161 transitions. [2018-10-03 10:12:18,246 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 161 [2018-10-03 10:12:18,247 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:12:18,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:12:18,635 INFO L134 CoverageAnalysis]: Checked inductivity of 6162 backedges. 0 proven. 6162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:12:21,049 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:12:21,050 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 163 states to 163 states and 163 transitions. [2018-10-03 10:12:21,050 INFO L276 IsEmpty]: Start isEmpty. Operand 163 states and 163 transitions. [2018-10-03 10:12:21,051 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2018-10-03 10:12:21,051 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:12:21,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:12:21,521 INFO L134 CoverageAnalysis]: Checked inductivity of 6320 backedges. 0 proven. 6320 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:12:23,995 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:12:23,995 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165 states to 165 states and 165 transitions. [2018-10-03 10:12:23,995 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states and 165 transitions. [2018-10-03 10:12:23,996 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 165 [2018-10-03 10:12:23,996 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:12:24,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:12:24,500 INFO L134 CoverageAnalysis]: Checked inductivity of 6480 backedges. 0 proven. 6480 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:12:27,269 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:12:27,269 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 167 states to 167 states and 167 transitions. [2018-10-03 10:12:27,269 INFO L276 IsEmpty]: Start isEmpty. Operand 167 states and 167 transitions. [2018-10-03 10:12:27,270 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 167 [2018-10-03 10:12:27,270 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:12:27,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:12:27,691 INFO L134 CoverageAnalysis]: Checked inductivity of 6642 backedges. 0 proven. 6642 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:12:30,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:12:30,211 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 169 states to 169 states and 169 transitions. [2018-10-03 10:12:30,212 INFO L276 IsEmpty]: Start isEmpty. Operand 169 states and 169 transitions. [2018-10-03 10:12:30,212 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2018-10-03 10:12:30,212 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:12:30,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:12:30,690 INFO L134 CoverageAnalysis]: Checked inductivity of 6806 backedges. 0 proven. 6806 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:12:33,203 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:12:33,203 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 171 states to 171 states and 171 transitions. [2018-10-03 10:12:33,203 INFO L276 IsEmpty]: Start isEmpty. Operand 171 states and 171 transitions. [2018-10-03 10:12:33,204 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 171 [2018-10-03 10:12:33,204 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:12:33,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:12:33,627 INFO L134 CoverageAnalysis]: Checked inductivity of 6972 backedges. 0 proven. 6972 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:12:36,278 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:12:36,279 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 173 states to 173 states and 173 transitions. [2018-10-03 10:12:36,279 INFO L276 IsEmpty]: Start isEmpty. Operand 173 states and 173 transitions. [2018-10-03 10:12:36,279 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 173 [2018-10-03 10:12:36,280 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:12:36,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:12:36,703 INFO L134 CoverageAnalysis]: Checked inductivity of 7140 backedges. 0 proven. 7140 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:12:39,323 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:12:39,323 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 175 states to 175 states and 175 transitions. [2018-10-03 10:12:39,323 INFO L276 IsEmpty]: Start isEmpty. Operand 175 states and 175 transitions. [2018-10-03 10:12:39,324 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 175 [2018-10-03 10:12:39,324 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:12:39,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:12:39,786 INFO L134 CoverageAnalysis]: Checked inductivity of 7310 backedges. 0 proven. 7310 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:12:42,755 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:12:42,756 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 177 states to 177 states and 177 transitions. [2018-10-03 10:12:42,756 INFO L276 IsEmpty]: Start isEmpty. Operand 177 states and 177 transitions. [2018-10-03 10:12:42,756 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 177 [2018-10-03 10:12:42,756 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:12:42,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:12:43,226 INFO L134 CoverageAnalysis]: Checked inductivity of 7482 backedges. 0 proven. 7482 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:12:45,974 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:12:45,975 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 179 states to 179 states and 179 transitions. [2018-10-03 10:12:45,975 INFO L276 IsEmpty]: Start isEmpty. Operand 179 states and 179 transitions. [2018-10-03 10:12:45,975 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2018-10-03 10:12:45,976 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:12:46,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:12:46,453 INFO L134 CoverageAnalysis]: Checked inductivity of 7656 backedges. 0 proven. 7656 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:12:49,279 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:12:49,280 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 181 states to 181 states and 181 transitions. [2018-10-03 10:12:49,280 INFO L276 IsEmpty]: Start isEmpty. Operand 181 states and 181 transitions. [2018-10-03 10:12:49,280 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 181 [2018-10-03 10:12:49,280 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:12:49,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:12:49,760 INFO L134 CoverageAnalysis]: Checked inductivity of 7832 backedges. 0 proven. 7832 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:12:52,956 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:12:52,956 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 183 states to 183 states and 183 transitions. [2018-10-03 10:12:52,956 INFO L276 IsEmpty]: Start isEmpty. Operand 183 states and 183 transitions. [2018-10-03 10:12:52,957 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 183 [2018-10-03 10:12:52,957 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:12:53,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:12:53,439 INFO L134 CoverageAnalysis]: Checked inductivity of 8010 backedges. 0 proven. 8010 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:12:56,306 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:12:56,306 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 185 states to 185 states and 185 transitions. [2018-10-03 10:12:56,306 INFO L276 IsEmpty]: Start isEmpty. Operand 185 states and 185 transitions. [2018-10-03 10:12:56,307 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 185 [2018-10-03 10:12:56,307 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:12:56,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:12:56,781 INFO L134 CoverageAnalysis]: Checked inductivity of 8190 backedges. 0 proven. 8190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:12:59,593 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:12:59,593 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 187 states to 187 states and 187 transitions. [2018-10-03 10:12:59,593 INFO L276 IsEmpty]: Start isEmpty. Operand 187 states and 187 transitions. [2018-10-03 10:12:59,594 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 187 [2018-10-03 10:12:59,594 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:12:59,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:13:00,116 INFO L134 CoverageAnalysis]: Checked inductivity of 8372 backedges. 0 proven. 8372 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:13:03,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:13:03,216 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 189 states to 189 states and 189 transitions. [2018-10-03 10:13:03,216 INFO L276 IsEmpty]: Start isEmpty. Operand 189 states and 189 transitions. [2018-10-03 10:13:03,216 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 189 [2018-10-03 10:13:03,216 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:13:03,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:13:03,751 INFO L134 CoverageAnalysis]: Checked inductivity of 8556 backedges. 0 proven. 8556 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:13:06,748 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:13:06,748 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 191 states to 191 states and 191 transitions. [2018-10-03 10:13:06,748 INFO L276 IsEmpty]: Start isEmpty. Operand 191 states and 191 transitions. [2018-10-03 10:13:06,749 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 191 [2018-10-03 10:13:06,749 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:13:06,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:13:07,275 INFO L134 CoverageAnalysis]: Checked inductivity of 8742 backedges. 0 proven. 8742 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:13:10,237 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:13:10,238 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 193 states to 193 states and 193 transitions. [2018-10-03 10:13:10,238 INFO L276 IsEmpty]: Start isEmpty. Operand 193 states and 193 transitions. [2018-10-03 10:13:10,238 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 193 [2018-10-03 10:13:10,238 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:13:10,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:13:10,786 INFO L134 CoverageAnalysis]: Checked inductivity of 8930 backedges. 0 proven. 8930 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:13:14,147 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:13:14,147 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195 states to 195 states and 195 transitions. [2018-10-03 10:13:14,148 INFO L276 IsEmpty]: Start isEmpty. Operand 195 states and 195 transitions. [2018-10-03 10:13:14,148 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 195 [2018-10-03 10:13:14,148 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:13:14,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:13:14,721 INFO L134 CoverageAnalysis]: Checked inductivity of 9120 backedges. 0 proven. 9120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:13:18,165 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:13:18,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 197 states to 197 states and 197 transitions. [2018-10-03 10:13:18,165 INFO L276 IsEmpty]: Start isEmpty. Operand 197 states and 197 transitions. [2018-10-03 10:13:18,166 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 197 [2018-10-03 10:13:18,166 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:13:18,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:13:18,747 INFO L134 CoverageAnalysis]: Checked inductivity of 9312 backedges. 0 proven. 9312 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:13:21,967 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:13:21,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 199 states to 199 states and 199 transitions. [2018-10-03 10:13:21,967 INFO L276 IsEmpty]: Start isEmpty. Operand 199 states and 199 transitions. [2018-10-03 10:13:21,968 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 199 [2018-10-03 10:13:21,968 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:13:22,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:13:22,534 INFO L134 CoverageAnalysis]: Checked inductivity of 9506 backedges. 0 proven. 9506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:13:25,712 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:13:25,712 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 201 states to 201 states and 201 transitions. [2018-10-03 10:13:25,713 INFO L276 IsEmpty]: Start isEmpty. Operand 201 states and 201 transitions. [2018-10-03 10:13:25,713 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 201 [2018-10-03 10:13:25,713 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:13:25,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-03 10:13:26,320 INFO L134 CoverageAnalysis]: Checked inductivity of 9702 backedges. 0 proven. 9702 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-03 10:13:29,655 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-03 10:13:29,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 203 states to 203 states and 203 transitions. [2018-10-03 10:13:29,655 INFO L276 IsEmpty]: Start isEmpty. Operand 203 states and 203 transitions. [2018-10-03 10:13:29,656 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 203 [2018-10-03 10:13:29,656 INFO L423 CodeCheckObserver]: Error Path is FOUND. [2018-10-03 10:13:30,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-03 10:13:31,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-03 10:13:32,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-03 10:13:32,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-03 10:13:32,625 WARN L491 CodeCheckObserver]: This program is UNSAFE, Check terminated with 0 iterations. [2018-10-03 10:13:32,632 INFO L760 CodeCheckObserver]: 0 DeclaredPredicates, 65458 GetRequests, 55362 SyntacticMatches, 9702 SemanticMatches, 394 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 176.1s Time 42.4s impTime 100 [2018-10-03 10:13:32,680 INFO L202 PluginConnector]: Adding new model diamond1.i_3.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck CFG 03.10 10:13:32 ImpRootNode [2018-10-03 10:13:32,681 INFO L132 PluginConnector]: ------------------------ END CodeCheck---------------------------- [2018-10-03 10:13:32,682 INFO L168 Benchmark]: Toolchain (without parser) took 197880.14 ms. Allocated memory was 1.5 GB in the beginning and 1.6 GB in the end (delta: 24.1 MB). Free memory was 1.5 GB in the beginning and 896.8 MB in the end (delta: 564.1 MB). Peak memory consumption was 588.2 MB. Max. memory is 7.1 GB. [2018-10-03 10:13:32,684 INFO L168 Benchmark]: Boogie PL CUP Parser took 0.24 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-10-03 10:13:32,684 INFO L168 Benchmark]: Boogie Procedure Inliner took 43.97 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-10-03 10:13:32,685 INFO L168 Benchmark]: Boogie Preprocessor took 21.83 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-10-03 10:13:32,685 INFO L168 Benchmark]: RCFGBuilder took 313.13 ms. Allocated memory is still 1.5 GB. Free memory was 1.5 GB in the beginning and 1.4 GB in the end (delta: 21.1 MB). Peak memory consumption was 21.1 MB. Max. memory is 7.1 GB. [2018-10-03 10:13:32,686 INFO L168 Benchmark]: CodeCheck took 197495.26 ms. Allocated memory was 1.5 GB in the beginning and 1.6 GB in the end (delta: 24.1 MB). Free memory was 1.4 GB in the beginning and 896.8 MB in the end (delta: 542.9 MB). Peak memory consumption was 567.1 MB. Max. memory is 7.1 GB. [2018-10-03 10:13:32,690 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck: - StatisticsResult: Ultimate CodeCheck benchmark data CFG has 1 procedures, 7 locations, 1 error locations. UNSAFE Result, 197.4s OverallTime, 100 OverallIterations, 0 TraceHistogramMax, 0.0s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 0 SDtfs, -4 SDslu, -8 SDs, 0 SdLazy, -10 SolverSat, -6 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 155.6s Time, PredicateUnifierStatistics: No data available, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=-1occurred in iteration=-1, traceCheckStatistics: 0.1s SsaConstructionTime, 3.6s SatisfiabilityAnalysisTime, 31.9s InterpolantComputationTime, 10300 NumberOfCodeBlocks, 10300 NumberOfCodeBlocksAsserted, 100 NumberOfCheckSat, 9999 ConstructedInterpolants, 0 QuantifiedInterpolants, 9273099 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 99 InterpolantComputations, 1 PerfectInterpolantSequences, 0/323400 InterpolantCoveringCapability, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: No data available, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: No data available, ReuseStatistics: No data available - CounterExampleResult [Line: 38]: assertion can be violated assertion can be violated We found a FailurePath: [L11] havoc main_#res; [L12] havoc main_#t~nondet0, main_#t~post1, main_~x~5, main_~y~5; [L13] main_~x~5 := 0; [L14] main_~y~5 := main_#t~nondet0; [L15] havoc main_#t~nondet0; VAL [main_~x~5=0] [L18] assume true; VAL [main_~x~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=1, main_~y~5=0] [L18] assume true; VAL [main_~x~5=1, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=2, main_~y~5=0] [L18] assume true; VAL [main_~x~5=2, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=3, main_~y~5=0] [L18] assume true; VAL [main_~x~5=3, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=4, main_~y~5=0] [L18] assume true; VAL [main_~x~5=4, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=5, main_~y~5=0] [L18] assume true; VAL [main_~x~5=5, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=6, main_~y~5=0] [L18] assume true; VAL [main_~x~5=6, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=7, main_~y~5=0] [L18] assume true; VAL [main_~x~5=7, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=8, main_~y~5=0] [L18] assume true; VAL [main_~x~5=8, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=9, main_~y~5=0] [L18] assume true; VAL [main_~x~5=9, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=10, main_~y~5=0] [L18] assume true; VAL [main_~x~5=10, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=11, main_~y~5=0] [L18] assume true; VAL [main_~x~5=11, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=12, main_~y~5=0] [L18] assume true; VAL [main_~x~5=12, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=13, main_~y~5=0] [L18] assume true; VAL [main_~x~5=13, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=14, main_~y~5=0] [L18] assume true; VAL [main_~x~5=14, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=15, main_~y~5=0] [L18] assume true; VAL [main_~x~5=15, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=16, main_~y~5=0] [L18] assume true; VAL [main_~x~5=16, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=17, main_~y~5=0] [L18] assume true; VAL [main_~x~5=17, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=18, main_~y~5=0] [L18] assume true; VAL [main_~x~5=18, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=19, main_~y~5=0] [L18] assume true; VAL [main_~x~5=19, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=20, main_~y~5=0] [L18] assume true; VAL [main_~x~5=20, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=21, main_~y~5=0] [L18] assume true; VAL [main_~x~5=21, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=22, main_~y~5=0] [L18] assume true; VAL [main_~x~5=22, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=23, main_~y~5=0] [L18] assume true; VAL [main_~x~5=23, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=24, main_~y~5=0] [L18] assume true; VAL [main_~x~5=24, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=25, main_~y~5=0] [L18] assume true; VAL [main_~x~5=25, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=26, main_~y~5=0] [L18] assume true; VAL [main_~x~5=26, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=27, main_~y~5=0] [L18] assume true; VAL [main_~x~5=27, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=28, main_~y~5=0] [L18] assume true; VAL [main_~x~5=28, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=29, main_~y~5=0] [L18] assume true; VAL [main_~x~5=29, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=30, main_~y~5=0] [L18] assume true; VAL [main_~x~5=30, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=31, main_~y~5=0] [L18] assume true; VAL [main_~x~5=31, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=32, main_~y~5=0] [L18] assume true; VAL [main_~x~5=32, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=33, main_~y~5=0] [L18] assume true; VAL [main_~x~5=33, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=34, main_~y~5=0] [L18] assume true; VAL [main_~x~5=34, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=35, main_~y~5=0] [L18] assume true; VAL [main_~x~5=35, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=36, main_~y~5=0] [L18] assume true; VAL [main_~x~5=36, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=37, main_~y~5=0] [L18] assume true; VAL [main_~x~5=37, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=38, main_~y~5=0] [L18] assume true; VAL [main_~x~5=38, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=39, main_~y~5=0] [L18] assume true; VAL [main_~x~5=39, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=40, main_~y~5=0] [L18] assume true; VAL [main_~x~5=40, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=41, main_~y~5=0] [L18] assume true; VAL [main_~x~5=41, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=42, main_~y~5=0] [L18] assume true; VAL [main_~x~5=42, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=43, main_~y~5=0] [L18] assume true; VAL [main_~x~5=43, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=44, main_~y~5=0] [L18] assume true; VAL [main_~x~5=44, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=45, main_~y~5=0] [L18] assume true; VAL [main_~x~5=45, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=46, main_~y~5=0] [L18] assume true; VAL [main_~x~5=46, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=47, main_~y~5=0] [L18] assume true; VAL [main_~x~5=47, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=48, main_~y~5=0] [L18] assume true; VAL [main_~x~5=48, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=49, main_~y~5=0] [L18] assume true; VAL [main_~x~5=49, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=50, main_~y~5=0] [L18] assume true; VAL [main_~x~5=50, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=51, main_~y~5=0] [L18] assume true; VAL [main_~x~5=51, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=52, main_~y~5=0] [L18] assume true; VAL [main_~x~5=52, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=53, main_~y~5=0] [L18] assume true; VAL [main_~x~5=53, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=54, main_~y~5=0] [L18] assume true; VAL [main_~x~5=54, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=55, main_~y~5=0] [L18] assume true; VAL [main_~x~5=55, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=56, main_~y~5=0] [L18] assume true; VAL [main_~x~5=56, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=57, main_~y~5=0] [L18] assume true; VAL [main_~x~5=57, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=58, main_~y~5=0] [L18] assume true; VAL [main_~x~5=58, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=59, main_~y~5=0] [L18] assume true; VAL [main_~x~5=59, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=60, main_~y~5=0] [L18] assume true; VAL [main_~x~5=60, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=61, main_~y~5=0] [L18] assume true; VAL [main_~x~5=61, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=62, main_~y~5=0] [L18] assume true; VAL [main_~x~5=62, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=63, main_~y~5=0] [L18] assume true; VAL [main_~x~5=63, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=64, main_~y~5=0] [L18] assume true; VAL [main_~x~5=64, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=65, main_~y~5=0] [L18] assume true; VAL [main_~x~5=65, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=66, main_~y~5=0] [L18] assume true; VAL [main_~x~5=66, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=67, main_~y~5=0] [L18] assume true; VAL [main_~x~5=67, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=68, main_~y~5=0] [L18] assume true; VAL [main_~x~5=68, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=69, main_~y~5=0] [L18] assume true; VAL [main_~x~5=69, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=70, main_~y~5=0] [L18] assume true; VAL [main_~x~5=70, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=71, main_~y~5=0] [L18] assume true; VAL [main_~x~5=71, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=72, main_~y~5=0] [L18] assume true; VAL [main_~x~5=72, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=73, main_~y~5=0] [L18] assume true; VAL [main_~x~5=73, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=74, main_~y~5=0] [L18] assume true; VAL [main_~x~5=74, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=75, main_~y~5=0] [L18] assume true; VAL [main_~x~5=75, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=76, main_~y~5=0] [L18] assume true; VAL [main_~x~5=76, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=77, main_~y~5=0] [L18] assume true; VAL [main_~x~5=77, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=78, main_~y~5=0] [L18] assume true; VAL [main_~x~5=78, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=79, main_~y~5=0] [L18] assume true; VAL [main_~x~5=79, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=80, main_~y~5=0] [L18] assume true; VAL [main_~x~5=80, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=81, main_~y~5=0] [L18] assume true; VAL [main_~x~5=81, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=82, main_~y~5=0] [L18] assume true; VAL [main_~x~5=82, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=83, main_~y~5=0] [L18] assume true; VAL [main_~x~5=83, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=84, main_~y~5=0] [L18] assume true; VAL [main_~x~5=84, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=85, main_~y~5=0] [L18] assume true; VAL [main_~x~5=85, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=86, main_~y~5=0] [L18] assume true; VAL [main_~x~5=86, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=87, main_~y~5=0] [L18] assume true; VAL [main_~x~5=87, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=88, main_~y~5=0] [L18] assume true; VAL [main_~x~5=88, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=89, main_~y~5=0] [L18] assume true; VAL [main_~x~5=89, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=90, main_~y~5=0] [L18] assume true; VAL [main_~x~5=90, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=91, main_~y~5=0] [L18] assume true; VAL [main_~x~5=91, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=92, main_~y~5=0] [L18] assume true; VAL [main_~x~5=92, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=93, main_~y~5=0] [L18] assume true; VAL [main_~x~5=93, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=94, main_~y~5=0] [L18] assume true; VAL [main_~x~5=94, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=95, main_~y~5=0] [L18] assume true; VAL [main_~x~5=95, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=96, main_~y~5=0] [L18] assume true; VAL [main_~x~5=96, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=97, main_~y~5=0] [L18] assume true; VAL [main_~x~5=97, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=98, main_~y~5=0] [L18] assume true; VAL [main_~x~5=98, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=99, main_~y~5=0] [L18] assume true; VAL [main_~x~5=99, main_~y~5=0] [L23] assume !(main_~x~5 % 4294967296 < 99); [L24] __VERIFIER_assert_#in~cond := (if (if main_~x~5 % 4294967296 < 0 && main_~x~5 % 4294967296 % 2 != 0 then main_~x~5 % 4294967296 % 2 - 2 else main_~x~5 % 4294967296 % 2) % 4294967296 == (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 then 1 else 0); [L25] havoc __VERIFIER_assert_~cond; [L26] __VERIFIER_assert_~cond := __VERIFIER_assert_#in~cond; [L27] assume __VERIFIER_assert_~cond == 0; [L28] assume !false; VAL [__VERIFIER_assert_#in~cond=0, __VERIFIER_assert_~cond=0, main_~x~5=99, main_~y~5=0] [L38] assert false; VAL [__VERIFIER_assert_#in~cond=0, __VERIFIER_assert_~cond=0, main_~x~5=99, main_~y~5=0] * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * Boogie PL CUP Parser took 0.24 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. * Boogie Procedure Inliner took 43.97 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. * Boogie Preprocessor took 21.83 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. * RCFGBuilder took 313.13 ms. Allocated memory is still 1.5 GB. Free memory was 1.5 GB in the beginning and 1.4 GB in the end (delta: 21.1 MB). Peak memory consumption was 21.1 MB. Max. memory is 7.1 GB. * CodeCheck took 197495.26 ms. Allocated memory was 1.5 GB in the beginning and 1.6 GB in the end (delta: 24.1 MB). Free memory was 1.4 GB in the beginning and 896.8 MB in the end (delta: 542.9 MB). Peak memory consumption was 567.1 MB. Max. memory is 7.1 GB. RESULT: Ultimate proved your program to be incorrect! Written .csv to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/csv/diamond1.i_3.bpl_svcomp-Reach-32bit-Kojak_Default_PUPT.epf_KojakBplInline.xml/Csv-CodeCheckBenchmarks-0-2018-10-03_10-13-32-702.csv Written .csv to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/csv/diamond1.i_3.bpl_svcomp-Reach-32bit-Kojak_Default_PUPT.epf_KojakBplInline.xml/Csv-Benchmark-0-2018-10-03_10-13-32-702.csv Received shutdown request...