java -Xmx8000000000 -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data --generate-csv --csv-dir csv -tc ../../../trunk/examples/toolchains/KojakBplInline.xml -s ../../../trunk/examples/settings/pu-bench/svcomp-Reach-32bit-Kojak_Default_PUPT.epf -i ../../../trunk/examples/programs/20170304-DifficultPathPrograms/diamond1.i_3.bpl -------------------------------------------------------------------------------- This is Ultimate 0.1.23-9f4048f [2018-10-04 13:46:50,044 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-10-04 13:46:50,046 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-10-04 13:46:50,066 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-10-04 13:46:50,067 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-10-04 13:46:50,068 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-10-04 13:46:50,069 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-10-04 13:46:50,071 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-10-04 13:46:50,072 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-10-04 13:46:50,073 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-10-04 13:46:50,074 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-10-04 13:46:50,074 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-10-04 13:46:50,075 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-10-04 13:46:50,076 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-10-04 13:46:50,077 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-10-04 13:46:50,078 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-10-04 13:46:50,079 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-10-04 13:46:50,083 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-10-04 13:46:50,085 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-10-04 13:46:50,087 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-10-04 13:46:50,088 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-10-04 13:46:50,089 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-10-04 13:46:50,092 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-10-04 13:46:50,092 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-10-04 13:46:50,092 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-10-04 13:46:50,093 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-10-04 13:46:50,094 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-10-04 13:46:50,095 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-10-04 13:46:50,096 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-10-04 13:46:50,097 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-10-04 13:46:50,097 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-10-04 13:46:50,098 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-10-04 13:46:50,098 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-10-04 13:46:50,098 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-10-04 13:46:50,100 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-10-04 13:46:50,100 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-10-04 13:46:50,101 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/pu-bench/svcomp-Reach-32bit-Kojak_Default_PUPT.epf [2018-10-04 13:46:50,130 INFO L110 SettingsManager]: Loading preferences was successful [2018-10-04 13:46:50,132 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-10-04 13:46:50,133 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-10-04 13:46:50,133 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-10-04 13:46:50,134 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-10-04 13:46:50,134 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-10-04 13:46:50,135 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-10-04 13:46:50,135 INFO L133 SettingsManager]: * sizeof long=4 [2018-10-04 13:46:50,135 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-10-04 13:46:50,135 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-10-04 13:46:50,135 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-10-04 13:46:50,136 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-10-04 13:46:50,136 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-10-04 13:46:50,136 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-10-04 13:46:50,136 INFO L133 SettingsManager]: * sizeof long double=12 [2018-10-04 13:46:50,136 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-10-04 13:46:50,136 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-10-04 13:46:50,138 INFO L131 SettingsManager]: Preferences of CodeCheck differ from their defaults: [2018-10-04 13:46:50,138 INFO L133 SettingsManager]: * Timeout in seconds=1000000 [2018-10-04 13:46:50,138 INFO L133 SettingsManager]: * Use predicate trie based predicate unification=true [2018-10-04 13:46:50,138 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-10-04 13:46:50,139 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-10-04 13:46:50,139 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 [2018-10-04 13:46:50,139 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-10-04 13:46:50,139 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-10-04 13:46:50,140 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-10-04 13:46:50,140 INFO L133 SettingsManager]: * Trace refinement strategy=PENGUIN [2018-10-04 13:46:50,140 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-10-04 13:46:50,140 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-10-04 13:46:50,140 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-10-04 13:46:50,205 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-10-04 13:46:50,222 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-10-04 13:46:50,230 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-10-04 13:46:50,232 INFO L271 PluginConnector]: Initializing Boogie PL CUP Parser... [2018-10-04 13:46:50,232 INFO L276 PluginConnector]: Boogie PL CUP Parser initialized [2018-10-04 13:46:50,233 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/programs/20170304-DifficultPathPrograms/diamond1.i_3.bpl [2018-10-04 13:46:50,234 INFO L111 BoogieParser]: Parsing: '/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/programs/20170304-DifficultPathPrograms/diamond1.i_3.bpl' [2018-10-04 13:46:50,282 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-10-04 13:46:50,284 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-10-04 13:46:50,284 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-10-04 13:46:50,285 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-10-04 13:46:50,285 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-10-04 13:46:50,305 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "diamond1.i_3.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.10 01:46:50" (1/1) ... [2018-10-04 13:46:50,315 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "diamond1.i_3.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.10 01:46:50" (1/1) ... [2018-10-04 13:46:50,320 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-10-04 13:46:50,321 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-10-04 13:46:50,322 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-10-04 13:46:50,322 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-10-04 13:46:50,332 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "diamond1.i_3.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.10 01:46:50" (1/1) ... [2018-10-04 13:46:50,333 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "diamond1.i_3.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.10 01:46:50" (1/1) ... [2018-10-04 13:46:50,334 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "diamond1.i_3.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.10 01:46:50" (1/1) ... [2018-10-04 13:46:50,334 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "diamond1.i_3.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.10 01:46:50" (1/1) ... [2018-10-04 13:46:50,337 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "diamond1.i_3.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.10 01:46:50" (1/1) ... [2018-10-04 13:46:50,338 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "diamond1.i_3.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.10 01:46:50" (1/1) ... [2018-10-04 13:46:50,339 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "diamond1.i_3.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.10 01:46:50" (1/1) ... [2018-10-04 13:46:50,341 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-10-04 13:46:50,341 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-10-04 13:46:50,342 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-10-04 13:46:50,342 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-10-04 13:46:50,343 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "diamond1.i_3.bpl de.uni_freiburg.informatik.ultimate.boogie.parser AST 04.10 01:46:50" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 [2018-10-04 13:46:50,406 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-10-04 13:46:50,407 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-10-04 13:46:50,648 INFO L341 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-10-04 13:46:50,649 INFO L202 PluginConnector]: Adding new model diamond1.i_3.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 04.10 01:46:50 BoogieIcfgContainer [2018-10-04 13:46:50,649 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-10-04 13:46:50,649 INFO L113 PluginConnector]: ------------------------CodeCheck---------------------------- [2018-10-04 13:46:50,649 INFO L271 PluginConnector]: Initializing CodeCheck... [2018-10-04 13:46:50,658 INFO L276 PluginConnector]: CodeCheck initialized [2018-10-04 13:46:50,659 INFO L185 PluginConnector]: Executing the observer CodeCheckObserver from plugin CodeCheck for "diamond1.i_3.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 04.10 01:46:50" (1/1) ... [2018-10-04 13:46:50,672 INFO L108 BPredicateUnifier]: Initialized predicate-trie based predicate unifier [2018-10-04 13:46:50,702 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:46:50,708 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 6 transitions. [2018-10-04 13:46:50,709 INFO L276 IsEmpty]: Start isEmpty. Operand 6 states and 6 transitions. [2018-10-04 13:46:50,711 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2018-10-04 13:46:50,711 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:46:50,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:46:50,881 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:46:51,161 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:46:51,162 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 7 transitions. [2018-10-04 13:46:51,162 INFO L276 IsEmpty]: Start isEmpty. Operand 7 states and 7 transitions. [2018-10-04 13:46:51,162 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 7 [2018-10-04 13:46:51,162 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:46:51,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:46:51,244 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:46:51,674 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:46:51,675 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 9 transitions. [2018-10-04 13:46:51,675 INFO L276 IsEmpty]: Start isEmpty. Operand 9 states and 9 transitions. [2018-10-04 13:46:51,675 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 9 [2018-10-04 13:46:51,676 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:46:51,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:46:51,811 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:46:52,518 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:46:52,519 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 11 transitions. [2018-10-04 13:46:52,520 INFO L276 IsEmpty]: Start isEmpty. Operand 11 states and 11 transitions. [2018-10-04 13:46:52,520 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 11 [2018-10-04 13:46:52,520 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:46:52,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:46:52,634 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:46:52,875 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:46:52,875 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 13 transitions. [2018-10-04 13:46:52,875 INFO L276 IsEmpty]: Start isEmpty. Operand 13 states and 13 transitions. [2018-10-04 13:46:52,876 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-10-04 13:46:52,876 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:46:52,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:46:53,242 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:46:53,686 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:46:53,687 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 15 transitions. [2018-10-04 13:46:53,687 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 15 transitions. [2018-10-04 13:46:53,688 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-10-04 13:46:53,688 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:46:53,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:46:53,839 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:46:54,636 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:46:54,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 17 transitions. [2018-10-04 13:46:54,637 INFO L276 IsEmpty]: Start isEmpty. Operand 17 states and 17 transitions. [2018-10-04 13:46:54,638 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-10-04 13:46:54,638 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:46:54,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:46:54,790 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:46:55,403 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:46:55,404 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 19 transitions. [2018-10-04 13:46:55,404 INFO L276 IsEmpty]: Start isEmpty. Operand 19 states and 19 transitions. [2018-10-04 13:46:55,405 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2018-10-04 13:46:55,405 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:46:55,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:46:55,571 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 0 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:46:55,965 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:46:55,965 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 21 transitions. [2018-10-04 13:46:55,966 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 21 transitions. [2018-10-04 13:46:55,966 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-10-04 13:46:55,966 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:46:55,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:46:56,079 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:46:56,476 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:46:56,477 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23 states to 23 states and 23 transitions. [2018-10-04 13:46:56,477 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states and 23 transitions. [2018-10-04 13:46:56,478 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-10-04 13:46:56,479 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:46:56,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:46:56,732 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:46:57,040 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:46:57,041 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 25 transitions. [2018-10-04 13:46:57,042 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 25 transitions. [2018-10-04 13:46:57,042 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-10-04 13:46:57,043 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:46:57,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:46:57,277 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:46:57,603 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:46:57,604 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 27 transitions. [2018-10-04 13:46:57,605 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states and 27 transitions. [2018-10-04 13:46:57,606 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-10-04 13:46:57,606 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:46:57,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:46:57,752 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 132 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:46:58,153 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:46:58,154 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 29 transitions. [2018-10-04 13:46:58,154 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 29 transitions. [2018-10-04 13:46:58,155 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-10-04 13:46:58,155 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:46:58,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:46:58,305 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:46:58,872 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:46:58,873 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 31 transitions. [2018-10-04 13:46:58,873 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states and 31 transitions. [2018-10-04 13:46:58,874 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2018-10-04 13:46:58,874 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:46:58,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:46:59,424 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 182 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:46:59,846 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:46:59,847 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 33 transitions. [2018-10-04 13:46:59,847 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 33 transitions. [2018-10-04 13:46:59,848 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-10-04 13:46:59,848 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:46:59,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:46:59,984 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 0 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:00,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:00,585 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35 states to 35 states and 35 transitions. [2018-10-04 13:47:00,585 INFO L276 IsEmpty]: Start isEmpty. Operand 35 states and 35 transitions. [2018-10-04 13:47:00,585 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-10-04 13:47:00,586 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:00,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:00,735 INFO L134 CoverageAnalysis]: Checked inductivity of 240 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:01,276 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:01,277 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 37 transitions. [2018-10-04 13:47:01,277 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 37 transitions. [2018-10-04 13:47:01,278 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-10-04 13:47:01,278 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:01,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:01,423 INFO L134 CoverageAnalysis]: Checked inductivity of 272 backedges. 0 proven. 272 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:01,858 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:01,858 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 39 transitions. [2018-10-04 13:47:01,858 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 39 transitions. [2018-10-04 13:47:01,859 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-10-04 13:47:01,859 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:01,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:02,073 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 0 proven. 306 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:02,738 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:02,739 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 41 transitions. [2018-10-04 13:47:02,739 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 41 transitions. [2018-10-04 13:47:02,740 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-10-04 13:47:02,740 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:02,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:03,041 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 0 proven. 342 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:04,123 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:04,124 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 43 transitions. [2018-10-04 13:47:04,124 INFO L276 IsEmpty]: Start isEmpty. Operand 43 states and 43 transitions. [2018-10-04 13:47:04,125 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-10-04 13:47:04,126 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:04,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:04,868 INFO L134 CoverageAnalysis]: Checked inductivity of 380 backedges. 0 proven. 380 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:05,344 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:05,345 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 45 transitions. [2018-10-04 13:47:05,345 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 45 transitions. [2018-10-04 13:47:05,346 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-10-04 13:47:05,346 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:05,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:05,867 INFO L134 CoverageAnalysis]: Checked inductivity of 420 backedges. 0 proven. 420 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:06,419 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:06,420 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 47 transitions. [2018-10-04 13:47:06,420 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 47 transitions. [2018-10-04 13:47:06,421 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-10-04 13:47:06,421 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:06,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:06,815 INFO L134 CoverageAnalysis]: Checked inductivity of 462 backedges. 0 proven. 462 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:07,337 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:07,338 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 49 transitions. [2018-10-04 13:47:07,338 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 49 transitions. [2018-10-04 13:47:07,339 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-10-04 13:47:07,339 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:07,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:08,115 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:08,645 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:08,646 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 51 transitions. [2018-10-04 13:47:08,646 INFO L276 IsEmpty]: Start isEmpty. Operand 51 states and 51 transitions. [2018-10-04 13:47:08,646 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-10-04 13:47:08,647 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:08,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:09,245 INFO L252 BPredicateUnifier]: --------PredicateTrie is restructured: old depths: 25 new depth: 24 [2018-10-04 13:47:09,253 INFO L134 CoverageAnalysis]: Checked inductivity of 552 backedges. 0 proven. 552 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:09,866 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:09,867 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 53 transitions. [2018-10-04 13:47:09,867 INFO L276 IsEmpty]: Start isEmpty. Operand 53 states and 53 transitions. [2018-10-04 13:47:09,868 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-10-04 13:47:09,868 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:09,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:10,092 INFO L134 CoverageAnalysis]: Checked inductivity of 600 backedges. 0 proven. 600 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:10,767 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:10,767 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 55 transitions. [2018-10-04 13:47:10,767 INFO L276 IsEmpty]: Start isEmpty. Operand 55 states and 55 transitions. [2018-10-04 13:47:10,768 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-10-04 13:47:10,768 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:10,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:11,073 INFO L134 CoverageAnalysis]: Checked inductivity of 650 backedges. 0 proven. 650 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:11,730 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:11,730 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 57 transitions. [2018-10-04 13:47:11,730 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 57 transitions. [2018-10-04 13:47:11,731 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-10-04 13:47:11,731 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:11,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:11,935 INFO L134 CoverageAnalysis]: Checked inductivity of 702 backedges. 0 proven. 702 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:12,593 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:12,593 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 59 transitions. [2018-10-04 13:47:12,593 INFO L276 IsEmpty]: Start isEmpty. Operand 59 states and 59 transitions. [2018-10-04 13:47:12,594 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-10-04 13:47:12,594 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:12,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:12,811 INFO L134 CoverageAnalysis]: Checked inductivity of 756 backedges. 0 proven. 756 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:13,582 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:13,582 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 61 transitions. [2018-10-04 13:47:13,583 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 61 transitions. [2018-10-04 13:47:13,583 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2018-10-04 13:47:13,584 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:13,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:14,770 INFO L134 CoverageAnalysis]: Checked inductivity of 812 backedges. 0 proven. 812 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:15,580 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:15,580 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 63 transitions. [2018-10-04 13:47:15,580 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 63 transitions. [2018-10-04 13:47:15,581 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-10-04 13:47:15,581 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:15,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:15,999 INFO L134 CoverageAnalysis]: Checked inductivity of 870 backedges. 0 proven. 870 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:16,936 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:16,936 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 65 transitions. [2018-10-04 13:47:16,937 INFO L276 IsEmpty]: Start isEmpty. Operand 65 states and 65 transitions. [2018-10-04 13:47:16,937 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-10-04 13:47:16,937 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:16,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:17,189 INFO L134 CoverageAnalysis]: Checked inductivity of 930 backedges. 0 proven. 930 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:17,934 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:17,934 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 67 transitions. [2018-10-04 13:47:17,935 INFO L276 IsEmpty]: Start isEmpty. Operand 67 states and 67 transitions. [2018-10-04 13:47:17,935 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-10-04 13:47:17,935 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:17,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:18,387 INFO L134 CoverageAnalysis]: Checked inductivity of 992 backedges. 0 proven. 992 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:19,204 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:19,205 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 69 transitions. [2018-10-04 13:47:19,205 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 69 transitions. [2018-10-04 13:47:19,205 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-10-04 13:47:19,205 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:19,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:19,734 INFO L134 CoverageAnalysis]: Checked inductivity of 1056 backedges. 0 proven. 1056 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:20,520 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:20,520 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71 states to 71 states and 71 transitions. [2018-10-04 13:47:20,520 INFO L276 IsEmpty]: Start isEmpty. Operand 71 states and 71 transitions. [2018-10-04 13:47:20,521 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-10-04 13:47:20,521 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:20,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:20,833 INFO L134 CoverageAnalysis]: Checked inductivity of 1122 backedges. 0 proven. 1122 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:21,875 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:21,875 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 73 transitions. [2018-10-04 13:47:21,876 INFO L276 IsEmpty]: Start isEmpty. Operand 73 states and 73 transitions. [2018-10-04 13:47:21,876 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-10-04 13:47:21,876 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:21,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:22,094 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 0 proven. 1190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:23,093 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:23,094 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 75 transitions. [2018-10-04 13:47:23,094 INFO L276 IsEmpty]: Start isEmpty. Operand 75 states and 75 transitions. [2018-10-04 13:47:23,094 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-10-04 13:47:23,094 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:23,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:23,464 INFO L134 CoverageAnalysis]: Checked inductivity of 1260 backedges. 0 proven. 1260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:24,386 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:24,386 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 77 transitions. [2018-10-04 13:47:24,387 INFO L276 IsEmpty]: Start isEmpty. Operand 77 states and 77 transitions. [2018-10-04 13:47:24,387 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2018-10-04 13:47:24,387 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:24,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:24,593 INFO L134 CoverageAnalysis]: Checked inductivity of 1332 backedges. 0 proven. 1332 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:25,515 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:25,516 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79 states to 79 states and 79 transitions. [2018-10-04 13:47:25,516 INFO L276 IsEmpty]: Start isEmpty. Operand 79 states and 79 transitions. [2018-10-04 13:47:25,516 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2018-10-04 13:47:25,516 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:25,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:26,098 INFO L134 CoverageAnalysis]: Checked inductivity of 1406 backedges. 0 proven. 1406 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:28,573 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:28,574 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 81 transitions. [2018-10-04 13:47:28,574 INFO L276 IsEmpty]: Start isEmpty. Operand 81 states and 81 transitions. [2018-10-04 13:47:28,575 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2018-10-04 13:47:28,575 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:28,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:29,165 INFO L134 CoverageAnalysis]: Checked inductivity of 1482 backedges. 0 proven. 1482 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:30,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:30,210 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 83 transitions. [2018-10-04 13:47:30,210 INFO L276 IsEmpty]: Start isEmpty. Operand 83 states and 83 transitions. [2018-10-04 13:47:30,210 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2018-10-04 13:47:30,210 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:30,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:30,482 INFO L134 CoverageAnalysis]: Checked inductivity of 1560 backedges. 0 proven. 1560 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:31,530 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:31,531 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85 states to 85 states and 85 transitions. [2018-10-04 13:47:31,531 INFO L276 IsEmpty]: Start isEmpty. Operand 85 states and 85 transitions. [2018-10-04 13:47:31,532 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-10-04 13:47:31,532 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:31,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:31,728 INFO L134 CoverageAnalysis]: Checked inductivity of 1640 backedges. 0 proven. 1640 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:32,728 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:32,729 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 87 transitions. [2018-10-04 13:47:32,729 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 87 transitions. [2018-10-04 13:47:32,729 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-10-04 13:47:32,729 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:32,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:33,129 INFO L134 CoverageAnalysis]: Checked inductivity of 1722 backedges. 0 proven. 1722 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:34,886 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:34,886 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 89 transitions. [2018-10-04 13:47:34,886 INFO L276 IsEmpty]: Start isEmpty. Operand 89 states and 89 transitions. [2018-10-04 13:47:34,887 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2018-10-04 13:47:34,887 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:34,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:35,607 INFO L252 BPredicateUnifier]: --------PredicateTrie is restructured: old depths: 44 new depth: 43 [2018-10-04 13:47:35,622 INFO L134 CoverageAnalysis]: Checked inductivity of 1806 backedges. 0 proven. 1806 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:36,691 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:36,691 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91 states to 91 states and 91 transitions. [2018-10-04 13:47:36,691 INFO L276 IsEmpty]: Start isEmpty. Operand 91 states and 91 transitions. [2018-10-04 13:47:36,692 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-10-04 13:47:36,692 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:36,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:37,019 INFO L134 CoverageAnalysis]: Checked inductivity of 1892 backedges. 0 proven. 1892 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:38,056 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:38,057 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 93 transitions. [2018-10-04 13:47:38,057 INFO L276 IsEmpty]: Start isEmpty. Operand 93 states and 93 transitions. [2018-10-04 13:47:38,058 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-10-04 13:47:38,058 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:38,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:38,278 INFO L134 CoverageAnalysis]: Checked inductivity of 1980 backedges. 0 proven. 1980 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:39,403 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:39,404 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 95 transitions. [2018-10-04 13:47:39,404 INFO L276 IsEmpty]: Start isEmpty. Operand 95 states and 95 transitions. [2018-10-04 13:47:39,405 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-10-04 13:47:39,405 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:39,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:39,665 INFO L134 CoverageAnalysis]: Checked inductivity of 2070 backedges. 0 proven. 2070 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:40,753 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:40,753 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 97 transitions. [2018-10-04 13:47:40,754 INFO L276 IsEmpty]: Start isEmpty. Operand 97 states and 97 transitions. [2018-10-04 13:47:40,754 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-10-04 13:47:40,754 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:40,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:40,931 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:42,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:42,282 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 99 transitions. [2018-10-04 13:47:42,282 INFO L276 IsEmpty]: Start isEmpty. Operand 99 states and 99 transitions. [2018-10-04 13:47:42,283 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2018-10-04 13:47:42,283 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:42,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:42,550 INFO L134 CoverageAnalysis]: Checked inductivity of 2256 backedges. 0 proven. 2256 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:47,848 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:47,849 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101 states to 101 states and 101 transitions. [2018-10-04 13:47:47,849 INFO L276 IsEmpty]: Start isEmpty. Operand 101 states and 101 transitions. [2018-10-04 13:47:47,849 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 101 [2018-10-04 13:47:47,849 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:47,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:48,191 INFO L134 CoverageAnalysis]: Checked inductivity of 2352 backedges. 0 proven. 2352 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:49,448 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:49,449 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103 states to 103 states and 103 transitions. [2018-10-04 13:47:49,449 INFO L276 IsEmpty]: Start isEmpty. Operand 103 states and 103 transitions. [2018-10-04 13:47:49,450 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-10-04 13:47:49,450 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:49,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:49,651 INFO L134 CoverageAnalysis]: Checked inductivity of 2450 backedges. 0 proven. 2450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:50,926 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:50,927 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 105 transitions. [2018-10-04 13:47:50,927 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 105 transitions. [2018-10-04 13:47:50,927 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2018-10-04 13:47:50,928 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:50,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:51,138 INFO L134 CoverageAnalysis]: Checked inductivity of 2550 backedges. 0 proven. 2550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:52,652 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:52,652 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 107 states to 107 states and 107 transitions. [2018-10-04 13:47:52,652 INFO L276 IsEmpty]: Start isEmpty. Operand 107 states and 107 transitions. [2018-10-04 13:47:52,653 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 107 [2018-10-04 13:47:52,653 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:52,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:52,939 INFO L134 CoverageAnalysis]: Checked inductivity of 2652 backedges. 0 proven. 2652 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:54,292 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:54,293 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 109 states to 109 states and 109 transitions. [2018-10-04 13:47:54,293 INFO L276 IsEmpty]: Start isEmpty. Operand 109 states and 109 transitions. [2018-10-04 13:47:54,293 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 109 [2018-10-04 13:47:54,293 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:54,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:54,484 INFO L134 CoverageAnalysis]: Checked inductivity of 2756 backedges. 0 proven. 2756 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:55,821 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:55,822 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111 states to 111 states and 111 transitions. [2018-10-04 13:47:55,822 INFO L276 IsEmpty]: Start isEmpty. Operand 111 states and 111 transitions. [2018-10-04 13:47:55,822 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2018-10-04 13:47:55,822 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:55,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:56,029 INFO L134 CoverageAnalysis]: Checked inductivity of 2862 backedges. 0 proven. 2862 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:57,468 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:57,468 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 113 transitions. [2018-10-04 13:47:57,468 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 113 transitions. [2018-10-04 13:47:57,468 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 113 [2018-10-04 13:47:57,469 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:57,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:47:57,770 INFO L134 CoverageAnalysis]: Checked inductivity of 2970 backedges. 0 proven. 2970 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:47:59,162 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:47:59,162 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 115 transitions. [2018-10-04 13:47:59,162 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 115 transitions. [2018-10-04 13:47:59,163 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 115 [2018-10-04 13:47:59,163 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:47:59,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:48:01,432 INFO L134 CoverageAnalysis]: Checked inductivity of 3080 backedges. 0 proven. 3080 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:48:03,838 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:48:03,839 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 117 transitions. [2018-10-04 13:48:03,839 INFO L276 IsEmpty]: Start isEmpty. Operand 117 states and 117 transitions. [2018-10-04 13:48:03,839 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 117 [2018-10-04 13:48:03,840 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:48:03,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:48:05,737 INFO L134 CoverageAnalysis]: Checked inductivity of 3192 backedges. 0 proven. 3192 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:48:07,240 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:48:07,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 119 states to 119 states and 119 transitions. [2018-10-04 13:48:07,240 INFO L276 IsEmpty]: Start isEmpty. Operand 119 states and 119 transitions. [2018-10-04 13:48:07,241 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 119 [2018-10-04 13:48:07,241 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:48:07,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:48:07,593 INFO L134 CoverageAnalysis]: Checked inductivity of 3306 backedges. 0 proven. 3306 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:48:09,171 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:48:09,171 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 121 states to 121 states and 121 transitions. [2018-10-04 13:48:09,172 INFO L276 IsEmpty]: Start isEmpty. Operand 121 states and 121 transitions. [2018-10-04 13:48:09,172 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-10-04 13:48:09,172 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:48:09,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:48:09,956 INFO L134 CoverageAnalysis]: Checked inductivity of 3422 backedges. 0 proven. 3422 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:48:11,493 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:48:11,494 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 123 states to 123 states and 123 transitions. [2018-10-04 13:48:11,494 INFO L276 IsEmpty]: Start isEmpty. Operand 123 states and 123 transitions. [2018-10-04 13:48:11,494 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-10-04 13:48:11,494 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:48:11,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:48:11,761 INFO L134 CoverageAnalysis]: Checked inductivity of 3540 backedges. 0 proven. 3540 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:48:13,610 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:48:13,610 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125 states to 125 states and 125 transitions. [2018-10-04 13:48:13,610 INFO L276 IsEmpty]: Start isEmpty. Operand 125 states and 125 transitions. [2018-10-04 13:48:13,610 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 125 [2018-10-04 13:48:13,611 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:48:13,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:48:14,921 INFO L252 BPredicateUnifier]: --------PredicateTrie is restructured: old depths: 62 new depth: 61 [2018-10-04 13:48:14,977 INFO L134 CoverageAnalysis]: Checked inductivity of 3660 backedges. 0 proven. 3660 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:48:16,687 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:48:16,687 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 127 states to 127 states and 127 transitions. [2018-10-04 13:48:16,687 INFO L276 IsEmpty]: Start isEmpty. Operand 127 states and 127 transitions. [2018-10-04 13:48:16,688 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 127 [2018-10-04 13:48:16,688 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:48:16,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:48:16,971 INFO L134 CoverageAnalysis]: Checked inductivity of 3782 backedges. 0 proven. 3782 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:48:18,912 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:48:18,913 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 129 states to 129 states and 129 transitions. [2018-10-04 13:48:18,913 INFO L276 IsEmpty]: Start isEmpty. Operand 129 states and 129 transitions. [2018-10-04 13:48:18,913 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2018-10-04 13:48:18,913 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:48:18,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:48:19,200 INFO L134 CoverageAnalysis]: Checked inductivity of 3906 backedges. 0 proven. 3906 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:48:20,969 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:48:20,970 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 131 states to 131 states and 131 transitions. [2018-10-04 13:48:20,970 INFO L276 IsEmpty]: Start isEmpty. Operand 131 states and 131 transitions. [2018-10-04 13:48:20,970 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 131 [2018-10-04 13:48:20,970 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:48:21,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:48:21,240 INFO L134 CoverageAnalysis]: Checked inductivity of 4032 backedges. 0 proven. 4032 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:48:22,982 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:48:22,982 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 133 states to 133 states and 133 transitions. [2018-10-04 13:48:22,983 INFO L276 IsEmpty]: Start isEmpty. Operand 133 states and 133 transitions. [2018-10-04 13:48:22,983 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2018-10-04 13:48:22,983 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:48:23,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:48:23,255 INFO L134 CoverageAnalysis]: Checked inductivity of 4160 backedges. 0 proven. 4160 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:48:25,035 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:48:25,036 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135 states to 135 states and 135 transitions. [2018-10-04 13:48:25,036 INFO L276 IsEmpty]: Start isEmpty. Operand 135 states and 135 transitions. [2018-10-04 13:48:25,037 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2018-10-04 13:48:25,037 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:48:25,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:48:25,317 INFO L134 CoverageAnalysis]: Checked inductivity of 4290 backedges. 0 proven. 4290 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:48:27,122 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:48:27,122 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 137 states to 137 states and 137 transitions. [2018-10-04 13:48:27,122 INFO L276 IsEmpty]: Start isEmpty. Operand 137 states and 137 transitions. [2018-10-04 13:48:27,123 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 137 [2018-10-04 13:48:27,123 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:48:27,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:48:27,440 INFO L134 CoverageAnalysis]: Checked inductivity of 4422 backedges. 0 proven. 4422 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:48:29,602 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:48:29,603 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 139 transitions. [2018-10-04 13:48:29,603 INFO L276 IsEmpty]: Start isEmpty. Operand 139 states and 139 transitions. [2018-10-04 13:48:29,604 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 139 [2018-10-04 13:48:29,604 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:48:29,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:48:30,043 INFO L134 CoverageAnalysis]: Checked inductivity of 4556 backedges. 0 proven. 4556 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:48:31,981 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:48:31,981 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 141 transitions. [2018-10-04 13:48:31,982 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 141 transitions. [2018-10-04 13:48:31,982 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 141 [2018-10-04 13:48:31,982 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:48:32,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:48:32,366 INFO L134 CoverageAnalysis]: Checked inductivity of 4692 backedges. 0 proven. 4692 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:48:34,431 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:48:34,431 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 143 states to 143 states and 143 transitions. [2018-10-04 13:48:34,432 INFO L276 IsEmpty]: Start isEmpty. Operand 143 states and 143 transitions. [2018-10-04 13:48:34,432 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 143 [2018-10-04 13:48:34,432 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:48:34,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:48:34,834 INFO L134 CoverageAnalysis]: Checked inductivity of 4830 backedges. 0 proven. 4830 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:48:36,813 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:48:36,814 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 145 states to 145 states and 145 transitions. [2018-10-04 13:48:36,814 INFO L276 IsEmpty]: Start isEmpty. Operand 145 states and 145 transitions. [2018-10-04 13:48:36,814 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 145 [2018-10-04 13:48:36,814 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:48:36,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:48:37,186 INFO L134 CoverageAnalysis]: Checked inductivity of 4970 backedges. 0 proven. 4970 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:48:39,409 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:48:39,410 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147 states to 147 states and 147 transitions. [2018-10-04 13:48:39,410 INFO L276 IsEmpty]: Start isEmpty. Operand 147 states and 147 transitions. [2018-10-04 13:48:39,411 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 147 [2018-10-04 13:48:39,411 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:48:39,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:48:39,770 INFO L134 CoverageAnalysis]: Checked inductivity of 5112 backedges. 0 proven. 5112 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:48:41,763 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:48:41,764 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 149 transitions. [2018-10-04 13:48:41,764 INFO L276 IsEmpty]: Start isEmpty. Operand 149 states and 149 transitions. [2018-10-04 13:48:41,765 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 149 [2018-10-04 13:48:41,765 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:48:41,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:48:42,121 INFO L134 CoverageAnalysis]: Checked inductivity of 5256 backedges. 0 proven. 5256 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:48:44,423 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:48:44,424 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 151 states to 151 states and 151 transitions. [2018-10-04 13:48:44,424 INFO L276 IsEmpty]: Start isEmpty. Operand 151 states and 151 transitions. [2018-10-04 13:48:44,425 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-10-04 13:48:44,425 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:48:44,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:48:44,801 INFO L134 CoverageAnalysis]: Checked inductivity of 5402 backedges. 0 proven. 5402 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:48:46,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:48:46,894 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 153 states to 153 states and 153 transitions. [2018-10-04 13:48:46,894 INFO L276 IsEmpty]: Start isEmpty. Operand 153 states and 153 transitions. [2018-10-04 13:48:46,894 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 153 [2018-10-04 13:48:46,894 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:48:46,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:48:47,212 INFO L134 CoverageAnalysis]: Checked inductivity of 5550 backedges. 0 proven. 5550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:48:49,565 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:48:49,565 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 155 states to 155 states and 155 transitions. [2018-10-04 13:48:49,565 INFO L276 IsEmpty]: Start isEmpty. Operand 155 states and 155 transitions. [2018-10-04 13:48:49,566 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 155 [2018-10-04 13:48:49,566 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:48:49,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:48:49,893 INFO L134 CoverageAnalysis]: Checked inductivity of 5700 backedges. 0 proven. 5700 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:48:52,061 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:48:52,061 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 157 states to 157 states and 157 transitions. [2018-10-04 13:48:52,061 INFO L276 IsEmpty]: Start isEmpty. Operand 157 states and 157 transitions. [2018-10-04 13:48:52,062 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 157 [2018-10-04 13:48:52,062 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:48:52,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:48:52,621 INFO L134 CoverageAnalysis]: Checked inductivity of 5852 backedges. 0 proven. 5852 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:48:55,163 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:48:55,163 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 159 states to 159 states and 159 transitions. [2018-10-04 13:48:55,164 INFO L276 IsEmpty]: Start isEmpty. Operand 159 states and 159 transitions. [2018-10-04 13:48:55,164 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 159 [2018-10-04 13:48:55,164 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:48:55,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:48:55,603 INFO L134 CoverageAnalysis]: Checked inductivity of 6006 backedges. 0 proven. 6006 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:48:57,876 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:48:57,876 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 161 states to 161 states and 161 transitions. [2018-10-04 13:48:57,877 INFO L276 IsEmpty]: Start isEmpty. Operand 161 states and 161 transitions. [2018-10-04 13:48:57,877 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 161 [2018-10-04 13:48:57,878 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:48:57,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:48:58,236 INFO L134 CoverageAnalysis]: Checked inductivity of 6162 backedges. 0 proven. 6162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:49:00,672 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:49:00,672 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 163 states to 163 states and 163 transitions. [2018-10-04 13:49:00,672 INFO L276 IsEmpty]: Start isEmpty. Operand 163 states and 163 transitions. [2018-10-04 13:49:00,673 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2018-10-04 13:49:00,673 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:49:00,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:49:01,050 INFO L134 CoverageAnalysis]: Checked inductivity of 6320 backedges. 0 proven. 6320 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:49:03,470 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:49:03,470 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165 states to 165 states and 165 transitions. [2018-10-04 13:49:03,470 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states and 165 transitions. [2018-10-04 13:49:03,471 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 165 [2018-10-04 13:49:03,471 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:49:03,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:49:03,906 INFO L134 CoverageAnalysis]: Checked inductivity of 6480 backedges. 0 proven. 6480 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:49:06,398 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:49:06,398 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 167 states to 167 states and 167 transitions. [2018-10-04 13:49:06,398 INFO L276 IsEmpty]: Start isEmpty. Operand 167 states and 167 transitions. [2018-10-04 13:49:06,399 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 167 [2018-10-04 13:49:06,399 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:49:06,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:49:07,935 INFO L252 BPredicateUnifier]: --------PredicateTrie is restructured: old depths: 83 new depth: 82 [2018-10-04 13:49:07,998 INFO L134 CoverageAnalysis]: Checked inductivity of 6642 backedges. 0 proven. 6642 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:49:10,663 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:49:10,663 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 169 states to 169 states and 169 transitions. [2018-10-04 13:49:10,663 INFO L276 IsEmpty]: Start isEmpty. Operand 169 states and 169 transitions. [2018-10-04 13:49:10,664 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2018-10-04 13:49:10,664 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:49:10,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:49:11,108 INFO L134 CoverageAnalysis]: Checked inductivity of 6806 backedges. 0 proven. 6806 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:49:13,551 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:49:13,551 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 171 states to 171 states and 171 transitions. [2018-10-04 13:49:13,551 INFO L276 IsEmpty]: Start isEmpty. Operand 171 states and 171 transitions. [2018-10-04 13:49:13,552 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 171 [2018-10-04 13:49:13,552 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:49:13,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:49:13,988 INFO L134 CoverageAnalysis]: Checked inductivity of 6972 backedges. 0 proven. 6972 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:49:16,564 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:49:16,564 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 173 states to 173 states and 173 transitions. [2018-10-04 13:49:16,564 INFO L276 IsEmpty]: Start isEmpty. Operand 173 states and 173 transitions. [2018-10-04 13:49:16,565 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 173 [2018-10-04 13:49:16,565 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:49:16,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:49:16,967 INFO L134 CoverageAnalysis]: Checked inductivity of 7140 backedges. 0 proven. 7140 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:49:19,536 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:49:19,537 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 175 states to 175 states and 175 transitions. [2018-10-04 13:49:19,537 INFO L276 IsEmpty]: Start isEmpty. Operand 175 states and 175 transitions. [2018-10-04 13:49:19,537 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 175 [2018-10-04 13:49:19,538 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:49:19,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:49:19,995 INFO L134 CoverageAnalysis]: Checked inductivity of 7310 backedges. 0 proven. 7310 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:49:22,673 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:49:22,673 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 177 states to 177 states and 177 transitions. [2018-10-04 13:49:22,673 INFO L276 IsEmpty]: Start isEmpty. Operand 177 states and 177 transitions. [2018-10-04 13:49:22,674 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 177 [2018-10-04 13:49:22,674 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:49:22,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:49:23,116 INFO L134 CoverageAnalysis]: Checked inductivity of 7482 backedges. 0 proven. 7482 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:49:26,082 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:49:26,082 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 179 states to 179 states and 179 transitions. [2018-10-04 13:49:26,082 INFO L276 IsEmpty]: Start isEmpty. Operand 179 states and 179 transitions. [2018-10-04 13:49:26,083 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2018-10-04 13:49:26,083 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:49:26,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:49:26,516 INFO L134 CoverageAnalysis]: Checked inductivity of 7656 backedges. 0 proven. 7656 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:49:29,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:49:29,256 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 181 states to 181 states and 181 transitions. [2018-10-04 13:49:29,256 INFO L276 IsEmpty]: Start isEmpty. Operand 181 states and 181 transitions. [2018-10-04 13:49:29,256 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 181 [2018-10-04 13:49:29,256 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:49:29,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:49:29,718 INFO L134 CoverageAnalysis]: Checked inductivity of 7832 backedges. 0 proven. 7832 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:49:32,502 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:49:32,503 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 183 states to 183 states and 183 transitions. [2018-10-04 13:49:32,503 INFO L276 IsEmpty]: Start isEmpty. Operand 183 states and 183 transitions. [2018-10-04 13:49:32,503 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 183 [2018-10-04 13:49:32,503 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:49:32,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:49:32,945 INFO L134 CoverageAnalysis]: Checked inductivity of 8010 backedges. 0 proven. 8010 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:49:36,007 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:49:36,007 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 185 states to 185 states and 185 transitions. [2018-10-04 13:49:36,007 INFO L276 IsEmpty]: Start isEmpty. Operand 185 states and 185 transitions. [2018-10-04 13:49:36,008 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 185 [2018-10-04 13:49:36,008 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:49:36,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:49:36,462 INFO L134 CoverageAnalysis]: Checked inductivity of 8190 backedges. 0 proven. 8190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:49:39,216 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:49:39,217 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 187 states to 187 states and 187 transitions. [2018-10-04 13:49:39,217 INFO L276 IsEmpty]: Start isEmpty. Operand 187 states and 187 transitions. [2018-10-04 13:49:39,217 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 187 [2018-10-04 13:49:39,218 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:49:39,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:49:39,799 INFO L134 CoverageAnalysis]: Checked inductivity of 8372 backedges. 0 proven. 8372 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:49:42,621 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:49:42,621 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 189 states to 189 states and 189 transitions. [2018-10-04 13:49:42,621 INFO L276 IsEmpty]: Start isEmpty. Operand 189 states and 189 transitions. [2018-10-04 13:49:42,622 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 189 [2018-10-04 13:49:42,622 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:49:42,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:49:43,089 INFO L134 CoverageAnalysis]: Checked inductivity of 8556 backedges. 0 proven. 8556 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:49:46,178 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:49:46,179 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 191 states to 191 states and 191 transitions. [2018-10-04 13:49:46,179 INFO L276 IsEmpty]: Start isEmpty. Operand 191 states and 191 transitions. [2018-10-04 13:49:46,180 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 191 [2018-10-04 13:49:46,180 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:49:46,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:49:46,644 INFO L134 CoverageAnalysis]: Checked inductivity of 8742 backedges. 0 proven. 8742 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:49:49,576 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:49:49,577 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 193 states to 193 states and 193 transitions. [2018-10-04 13:49:49,577 INFO L276 IsEmpty]: Start isEmpty. Operand 193 states and 193 transitions. [2018-10-04 13:49:49,577 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 193 [2018-10-04 13:49:49,577 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:49:49,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:49:50,151 INFO L134 CoverageAnalysis]: Checked inductivity of 8930 backedges. 0 proven. 8930 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:49:53,134 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:49:53,134 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195 states to 195 states and 195 transitions. [2018-10-04 13:49:53,134 INFO L276 IsEmpty]: Start isEmpty. Operand 195 states and 195 transitions. [2018-10-04 13:49:53,135 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 195 [2018-10-04 13:49:53,135 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:49:53,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:49:53,648 INFO L134 CoverageAnalysis]: Checked inductivity of 9120 backedges. 0 proven. 9120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:49:56,972 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:49:56,973 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 197 states to 197 states and 197 transitions. [2018-10-04 13:49:56,973 INFO L276 IsEmpty]: Start isEmpty. Operand 197 states and 197 transitions. [2018-10-04 13:49:56,973 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 197 [2018-10-04 13:49:56,974 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:49:57,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:49:57,471 INFO L134 CoverageAnalysis]: Checked inductivity of 9312 backedges. 0 proven. 9312 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:50:00,542 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:50:00,543 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 199 states to 199 states and 199 transitions. [2018-10-04 13:50:00,543 INFO L276 IsEmpty]: Start isEmpty. Operand 199 states and 199 transitions. [2018-10-04 13:50:00,543 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 199 [2018-10-04 13:50:00,543 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:50:00,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:50:01,103 INFO L134 CoverageAnalysis]: Checked inductivity of 9506 backedges. 0 proven. 9506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:50:04,157 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:50:04,157 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 201 states to 201 states and 201 transitions. [2018-10-04 13:50:04,157 INFO L276 IsEmpty]: Start isEmpty. Operand 201 states and 201 transitions. [2018-10-04 13:50:04,158 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 201 [2018-10-04 13:50:04,158 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:50:04,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-10-04 13:50:04,707 INFO L134 CoverageAnalysis]: Checked inductivity of 9702 backedges. 0 proven. 9702 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-10-04 13:50:08,005 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2018-10-04 13:50:08,006 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 203 states to 203 states and 203 transitions. [2018-10-04 13:50:08,006 INFO L276 IsEmpty]: Start isEmpty. Operand 203 states and 203 transitions. [2018-10-04 13:50:08,006 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 203 [2018-10-04 13:50:08,007 INFO L428 CodeCheckObserver]: Error Path is FOUND. [2018-10-04 13:50:09,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-04 13:50:10,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-04 13:50:11,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-04 13:50:11,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-10-04 13:50:11,532 WARN L496 CodeCheckObserver]: This program is UNSAFE, Check terminated with 100 iterations. [2018-10-04 13:50:11,632 INFO L202 PluginConnector]: Adding new model diamond1.i_3.bpl de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck CFG 04.10 01:50:11 ImpRootNode [2018-10-04 13:50:11,632 INFO L132 PluginConnector]: ------------------------ END CodeCheck---------------------------- [2018-10-04 13:50:11,633 INFO L168 Benchmark]: Toolchain (without parser) took 201350.65 ms. Allocated memory was 1.5 GB in the beginning and 1.5 GB in the end (delta: -30.9 MB). Free memory was 1.5 GB in the beginning and 1.2 GB in the end (delta: 262.6 MB). Peak memory consumption was 231.7 MB. Max. memory is 7.1 GB. [2018-10-04 13:50:11,639 INFO L168 Benchmark]: Boogie PL CUP Parser took 0.19 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-10-04 13:50:11,640 INFO L168 Benchmark]: Boogie Procedure Inliner took 36.58 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-10-04 13:50:11,640 INFO L168 Benchmark]: Boogie Preprocessor took 19.63 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-10-04 13:50:11,641 INFO L168 Benchmark]: RCFGBuilder took 307.33 ms. Allocated memory is still 1.5 GB. Free memory was 1.5 GB in the beginning and 1.4 GB in the end (delta: 21.1 MB). Peak memory consumption was 21.1 MB. Max. memory is 7.1 GB. [2018-10-04 13:50:11,642 INFO L168 Benchmark]: CodeCheck took 200983.13 ms. Allocated memory was 1.5 GB in the beginning and 1.5 GB in the end (delta: -30.9 MB). Free memory was 1.4 GB in the beginning and 1.2 GB in the end (delta: 241.5 MB). Peak memory consumption was 210.5 MB. Max. memory is 7.1 GB. [2018-10-04 13:50:11,645 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck: - StatisticsResult: Ultimate CodeCheck benchmark data CFG has 1 procedures, 7 locations, 1 error locations. UNSAFE Result, 200.8s OverallTime, 100 OverallIterations, 0 TraceHistogramMax, 0.0s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 0 SDtfs, -4 SDslu, -8 SDs, 0 SdLazy, -10 SolverSat, -6 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 153.8s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 65458 GetRequests, 55362 SyntacticMatches, 9702 SemanticMatches, 394 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 180.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=-1occurred in iteration=-1, traceCheckStatistics: 0.1s SsaConstructionTime, 3.6s SatisfiabilityAnalysisTime, 34.6s InterpolantComputationTime, 10300 NumberOfCodeBlocks, 10300 NumberOfCodeBlocksAsserted, 100 NumberOfCheckSat, 9999 ConstructedInterpolants, 0 QuantifiedInterpolants, 9273099 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 99 InterpolantComputations, 1 PerfectInterpolantSequences, 0/323400 InterpolantCoveringCapability, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: No data available, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: No data available, ReuseStatistics: No data available - CounterExampleResult [Line: 38]: assertion can be violated assertion can be violated We found a FailurePath: [L11] havoc main_#res; [L12] havoc main_#t~nondet0, main_#t~post1, main_~x~5, main_~y~5; [L13] main_~x~5 := 0; [L14] main_~y~5 := main_#t~nondet0; [L15] havoc main_#t~nondet0; VAL [main_~x~5=0] [L18] assume true; VAL [main_~x~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=1, main_~y~5=0] [L18] assume true; VAL [main_~x~5=1, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=2, main_~y~5=0] [L18] assume true; VAL [main_~x~5=2, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=3, main_~y~5=0] [L18] assume true; VAL [main_~x~5=3, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=4, main_~y~5=0] [L18] assume true; VAL [main_~x~5=4, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=5, main_~y~5=0] [L18] assume true; VAL [main_~x~5=5, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=6, main_~y~5=0] [L18] assume true; VAL [main_~x~5=6, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=7, main_~y~5=0] [L18] assume true; VAL [main_~x~5=7, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=8, main_~y~5=0] [L18] assume true; VAL [main_~x~5=8, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=9, main_~y~5=0] [L18] assume true; VAL [main_~x~5=9, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=10, main_~y~5=0] [L18] assume true; VAL [main_~x~5=10, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=11, main_~y~5=0] [L18] assume true; VAL [main_~x~5=11, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=12, main_~y~5=0] [L18] assume true; VAL [main_~x~5=12, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=13, main_~y~5=0] [L18] assume true; VAL [main_~x~5=13, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=14, main_~y~5=0] [L18] assume true; VAL [main_~x~5=14, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=15, main_~y~5=0] [L18] assume true; VAL [main_~x~5=15, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=16, main_~y~5=0] [L18] assume true; VAL [main_~x~5=16, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=17, main_~y~5=0] [L18] assume true; VAL [main_~x~5=17, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=18, main_~y~5=0] [L18] assume true; VAL [main_~x~5=18, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=19, main_~y~5=0] [L18] assume true; VAL [main_~x~5=19, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=20, main_~y~5=0] [L18] assume true; VAL [main_~x~5=20, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=21, main_~y~5=0] [L18] assume true; VAL [main_~x~5=21, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=22, main_~y~5=0] [L18] assume true; VAL [main_~x~5=22, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=23, main_~y~5=0] [L18] assume true; VAL [main_~x~5=23, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=24, main_~y~5=0] [L18] assume true; VAL [main_~x~5=24, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=25, main_~y~5=0] [L18] assume true; VAL [main_~x~5=25, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=26, main_~y~5=0] [L18] assume true; VAL [main_~x~5=26, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=27, main_~y~5=0] [L18] assume true; VAL [main_~x~5=27, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=28, main_~y~5=0] [L18] assume true; VAL [main_~x~5=28, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=29, main_~y~5=0] [L18] assume true; VAL [main_~x~5=29, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=30, main_~y~5=0] [L18] assume true; VAL [main_~x~5=30, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=31, main_~y~5=0] [L18] assume true; VAL [main_~x~5=31, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=32, main_~y~5=0] [L18] assume true; VAL [main_~x~5=32, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=33, main_~y~5=0] [L18] assume true; VAL [main_~x~5=33, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=34, main_~y~5=0] [L18] assume true; VAL [main_~x~5=34, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=35, main_~y~5=0] [L18] assume true; VAL [main_~x~5=35, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=36, main_~y~5=0] [L18] assume true; VAL [main_~x~5=36, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=37, main_~y~5=0] [L18] assume true; VAL [main_~x~5=37, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=38, main_~y~5=0] [L18] assume true; VAL [main_~x~5=38, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=39, main_~y~5=0] [L18] assume true; VAL [main_~x~5=39, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=40, main_~y~5=0] [L18] assume true; VAL [main_~x~5=40, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=41, main_~y~5=0] [L18] assume true; VAL [main_~x~5=41, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=42, main_~y~5=0] [L18] assume true; VAL [main_~x~5=42, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=43, main_~y~5=0] [L18] assume true; VAL [main_~x~5=43, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=44, main_~y~5=0] [L18] assume true; VAL [main_~x~5=44, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=45, main_~y~5=0] [L18] assume true; VAL [main_~x~5=45, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=46, main_~y~5=0] [L18] assume true; VAL [main_~x~5=46, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=47, main_~y~5=0] [L18] assume true; VAL [main_~x~5=47, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=48, main_~y~5=0] [L18] assume true; VAL [main_~x~5=48, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=49, main_~y~5=0] [L18] assume true; VAL [main_~x~5=49, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=50, main_~y~5=0] [L18] assume true; VAL [main_~x~5=50, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=51, main_~y~5=0] [L18] assume true; VAL [main_~x~5=51, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=52, main_~y~5=0] [L18] assume true; VAL [main_~x~5=52, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=53, main_~y~5=0] [L18] assume true; VAL [main_~x~5=53, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=54, main_~y~5=0] [L18] assume true; VAL [main_~x~5=54, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=55, main_~y~5=0] [L18] assume true; VAL [main_~x~5=55, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=56, main_~y~5=0] [L18] assume true; VAL [main_~x~5=56, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=57, main_~y~5=0] [L18] assume true; VAL [main_~x~5=57, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=58, main_~y~5=0] [L18] assume true; VAL [main_~x~5=58, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=59, main_~y~5=0] [L18] assume true; VAL [main_~x~5=59, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=60, main_~y~5=0] [L18] assume true; VAL [main_~x~5=60, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=61, main_~y~5=0] [L18] assume true; VAL [main_~x~5=61, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=62, main_~y~5=0] [L18] assume true; VAL [main_~x~5=62, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=63, main_~y~5=0] [L18] assume true; VAL [main_~x~5=63, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=64, main_~y~5=0] [L18] assume true; VAL [main_~x~5=64, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=65, main_~y~5=0] [L18] assume true; VAL [main_~x~5=65, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=66, main_~y~5=0] [L18] assume true; VAL [main_~x~5=66, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=67, main_~y~5=0] [L18] assume true; VAL [main_~x~5=67, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=68, main_~y~5=0] [L18] assume true; VAL [main_~x~5=68, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=69, main_~y~5=0] [L18] assume true; VAL [main_~x~5=69, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=70, main_~y~5=0] [L18] assume true; VAL [main_~x~5=70, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=71, main_~y~5=0] [L18] assume true; VAL [main_~x~5=71, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=72, main_~y~5=0] [L18] assume true; VAL [main_~x~5=72, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=73, main_~y~5=0] [L18] assume true; VAL [main_~x~5=73, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=74, main_~y~5=0] [L18] assume true; VAL [main_~x~5=74, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=75, main_~y~5=0] [L18] assume true; VAL [main_~x~5=75, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=76, main_~y~5=0] [L18] assume true; VAL [main_~x~5=76, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=77, main_~y~5=0] [L18] assume true; VAL [main_~x~5=77, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=78, main_~y~5=0] [L18] assume true; VAL [main_~x~5=78, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=79, main_~y~5=0] [L18] assume true; VAL [main_~x~5=79, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=80, main_~y~5=0] [L18] assume true; VAL [main_~x~5=80, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=81, main_~y~5=0] [L18] assume true; VAL [main_~x~5=81, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=82, main_~y~5=0] [L18] assume true; VAL [main_~x~5=82, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=83, main_~y~5=0] [L18] assume true; VAL [main_~x~5=83, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=84, main_~y~5=0] [L18] assume true; VAL [main_~x~5=84, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=85, main_~y~5=0] [L18] assume true; VAL [main_~x~5=85, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=86, main_~y~5=0] [L18] assume true; VAL [main_~x~5=86, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=87, main_~y~5=0] [L18] assume true; VAL [main_~x~5=87, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=88, main_~y~5=0] [L18] assume true; VAL [main_~x~5=88, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=89, main_~y~5=0] [L18] assume true; VAL [main_~x~5=89, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=90, main_~y~5=0] [L18] assume true; VAL [main_~x~5=90, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=91, main_~y~5=0] [L18] assume true; VAL [main_~x~5=91, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=92, main_~y~5=0] [L18] assume true; VAL [main_~x~5=92, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=93, main_~y~5=0] [L18] assume true; VAL [main_~x~5=93, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=94, main_~y~5=0] [L18] assume true; VAL [main_~x~5=94, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=95, main_~y~5=0] [L18] assume true; VAL [main_~x~5=95, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=96, main_~y~5=0] [L18] assume true; VAL [main_~x~5=96, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=97, main_~y~5=0] [L18] assume true; VAL [main_~x~5=97, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=98, main_~y~5=0] [L18] assume true; VAL [main_~x~5=98, main_~y~5=0] [L31] assume !!(main_~x~5 % 4294967296 < 99); [L32] assume (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 == 0; [L33] main_#t~post1 := main_~x~5; [L34] main_~x~5 := main_#t~post1 + 1; [L35] havoc main_#t~post1; VAL [main_~x~5=99, main_~y~5=0] [L18] assume true; VAL [main_~x~5=99, main_~y~5=0] [L23] assume !(main_~x~5 % 4294967296 < 99); [L24] __VERIFIER_assert_#in~cond := (if (if main_~x~5 % 4294967296 < 0 && main_~x~5 % 4294967296 % 2 != 0 then main_~x~5 % 4294967296 % 2 - 2 else main_~x~5 % 4294967296 % 2) % 4294967296 == (if main_~y~5 % 4294967296 < 0 && main_~y~5 % 4294967296 % 2 != 0 then main_~y~5 % 4294967296 % 2 - 2 else main_~y~5 % 4294967296 % 2) % 4294967296 then 1 else 0); [L25] havoc __VERIFIER_assert_~cond; [L26] __VERIFIER_assert_~cond := __VERIFIER_assert_#in~cond; [L27] assume __VERIFIER_assert_~cond == 0; [L28] assume !false; VAL [__VERIFIER_assert_#in~cond=0, __VERIFIER_assert_~cond=0, main_~x~5=99, main_~y~5=0] [L38] assert false; VAL [__VERIFIER_assert_#in~cond=0, __VERIFIER_assert_~cond=0, main_~x~5=99, main_~y~5=0] * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * Boogie PL CUP Parser took 0.19 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. * Boogie Procedure Inliner took 36.58 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. * Boogie Preprocessor took 19.63 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. * RCFGBuilder took 307.33 ms. Allocated memory is still 1.5 GB. Free memory was 1.5 GB in the beginning and 1.4 GB in the end (delta: 21.1 MB). Peak memory consumption was 21.1 MB. Max. memory is 7.1 GB. * CodeCheck took 200983.13 ms. Allocated memory was 1.5 GB in the beginning and 1.5 GB in the end (delta: -30.9 MB). Free memory was 1.4 GB in the beginning and 1.2 GB in the end (delta: 241.5 MB). Peak memory consumption was 210.5 MB. Max. memory is 7.1 GB. RESULT: Ultimate proved your program to be incorrect! Written .csv to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/csv/diamond1.i_3.bpl_svcomp-Reach-32bit-Kojak_Default_PUPT.epf_KojakBplInline.xml/Csv-CodeCheckBenchmarks-0-2018-10-04_13-50-11-657.csv Written .csv to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/csv/diamond1.i_3.bpl_svcomp-Reach-32bit-Kojak_Default_PUPT.epf_KojakBplInline.xml/Csv-Benchmark-0-2018-10-04_13-50-11-657.csv Received shutdown request...