/usr/bin/java -ea -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data --core.log.level.for.class de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=WARN -tc ../../../trunk/examples/toolchains/AutomizerCTransformed.xml -s ../../../trunk/examples/settings/automizer/LoopAccelerationJordanC.epf -i ../../../trunk/examples/svcomp/loops-crafted-1/in-de41.c -------------------------------------------------------------------------------- This is Ultimate 0.2.2-dev-34549b5 [2022-04-07 17:24:55,966 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-04-07 17:24:55,968 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-04-07 17:24:56,004 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-04-07 17:24:56,004 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-04-07 17:24:56,005 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-04-07 17:24:56,007 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-04-07 17:24:56,009 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-04-07 17:24:56,010 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-04-07 17:24:56,013 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-04-07 17:24:56,014 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-04-07 17:24:56,015 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-04-07 17:24:56,015 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-04-07 17:24:56,018 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-04-07 17:24:56,019 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-04-07 17:24:56,021 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-04-07 17:24:56,021 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-04-07 17:24:56,022 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-04-07 17:24:56,023 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-04-07 17:24:56,027 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-04-07 17:24:56,028 INFO L181 SettingsManager]: Resetting HornVerifier preferences to default values [2022-04-07 17:24:56,029 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-04-07 17:24:56,030 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-04-07 17:24:56,030 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-04-07 17:24:56,031 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-04-07 17:24:56,036 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-04-07 17:24:56,036 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-04-07 17:24:56,036 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-04-07 17:24:56,036 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-04-07 17:24:56,037 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-04-07 17:24:56,038 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-04-07 17:24:56,038 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-04-07 17:24:56,039 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-04-07 17:24:56,039 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-04-07 17:24:56,040 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-04-07 17:24:56,040 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-04-07 17:24:56,041 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-04-07 17:24:56,041 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-04-07 17:24:56,041 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-04-07 17:24:56,041 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-04-07 17:24:56,042 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-04-07 17:24:56,043 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-04-07 17:24:56,043 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/automizer/LoopAccelerationJordanC.epf [2022-04-07 17:24:56,050 INFO L113 SettingsManager]: Loading preferences was successful [2022-04-07 17:24:56,050 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-04-07 17:24:56,051 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-04-07 17:24:56,051 INFO L138 SettingsManager]: * sizeof long=4 [2022-04-07 17:24:56,052 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-04-07 17:24:56,052 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-04-07 17:24:56,052 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-04-07 17:24:56,052 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-04-07 17:24:56,052 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-04-07 17:24:56,052 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-04-07 17:24:56,053 INFO L138 SettingsManager]: * sizeof long double=12 [2022-04-07 17:24:56,053 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-04-07 17:24:56,053 INFO L138 SettingsManager]: * Use constant arrays=true [2022-04-07 17:24:56,053 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-04-07 17:24:56,053 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-04-07 17:24:56,053 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-04-07 17:24:56,053 INFO L138 SettingsManager]: * To the following directory=./dump/ [2022-04-07 17:24:56,053 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-04-07 17:24:56,053 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-04-07 17:24:56,054 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-04-07 17:24:56,054 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-04-07 17:24:56,055 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-04-07 17:24:56,055 INFO L138 SettingsManager]: * TransformationType=LOOP_ACCELERATION_JORDAN WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.core: Log level for class -> de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=WARN; [2022-04-07 17:24:56,233 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-04-07 17:24:56,249 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-04-07 17:24:56,251 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-04-07 17:24:56,252 INFO L271 PluginConnector]: Initializing CDTParser... [2022-04-07 17:24:56,252 INFO L275 PluginConnector]: CDTParser initialized [2022-04-07 17:24:56,253 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loops-crafted-1/in-de41.c [2022-04-07 17:24:56,288 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/733d30655/72fe1b03d2d34947be89922417beaa9b/FLAG77cd58479 [2022-04-07 17:24:56,611 INFO L306 CDTParser]: Found 1 translation units. [2022-04-07 17:24:56,611 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/loops-crafted-1/in-de41.c [2022-04-07 17:24:56,616 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/733d30655/72fe1b03d2d34947be89922417beaa9b/FLAG77cd58479 [2022-04-07 17:24:56,624 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/733d30655/72fe1b03d2d34947be89922417beaa9b [2022-04-07 17:24:56,626 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-04-07 17:24:56,627 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2022-04-07 17:24:56,627 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-04-07 17:24:56,627 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-04-07 17:24:56,629 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-04-07 17:24:56,630 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.04 05:24:56" (1/1) ... [2022-04-07 17:24:56,631 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4b99fbf4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 05:24:56, skipping insertion in model container [2022-04-07 17:24:56,631 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.04 05:24:56" (1/1) ... [2022-04-07 17:24:56,635 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-04-07 17:24:56,642 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-04-07 17:24:56,741 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loops-crafted-1/in-de41.c[368,381] [2022-04-07 17:24:56,753 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-04-07 17:24:56,758 INFO L203 MainTranslator]: Completed pre-run [2022-04-07 17:24:56,773 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loops-crafted-1/in-de41.c[368,381] [2022-04-07 17:24:56,780 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-04-07 17:24:56,788 INFO L208 MainTranslator]: Completed translation [2022-04-07 17:24:56,788 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 05:24:56 WrapperNode [2022-04-07 17:24:56,788 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-04-07 17:24:56,789 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-04-07 17:24:56,789 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-04-07 17:24:56,789 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-04-07 17:24:56,797 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 05:24:56" (1/1) ... [2022-04-07 17:24:56,797 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 05:24:56" (1/1) ... [2022-04-07 17:24:56,801 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 05:24:56" (1/1) ... [2022-04-07 17:24:56,801 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 05:24:56" (1/1) ... [2022-04-07 17:24:56,805 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 05:24:56" (1/1) ... [2022-04-07 17:24:56,807 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 05:24:56" (1/1) ... [2022-04-07 17:24:56,808 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 05:24:56" (1/1) ... [2022-04-07 17:24:56,809 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-04-07 17:24:56,810 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-04-07 17:24:56,810 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-04-07 17:24:56,810 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-04-07 17:24:56,810 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 05:24:56" (1/1) ... [2022-04-07 17:24:56,815 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-04-07 17:24:56,821 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 17:24:56,829 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-04-07 17:24:56,833 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-04-07 17:24:56,851 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2022-04-07 17:24:56,851 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-04-07 17:24:56,851 INFO L138 BoogieDeclarations]: Found implementation of procedure reach_error [2022-04-07 17:24:56,851 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2022-04-07 17:24:56,852 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2022-04-07 17:24:56,852 INFO L130 BoogieDeclarations]: Found specification of procedure abort [2022-04-07 17:24:56,852 INFO L130 BoogieDeclarations]: Found specification of procedure __assert_fail [2022-04-07 17:24:56,852 INFO L130 BoogieDeclarations]: Found specification of procedure reach_error [2022-04-07 17:24:56,852 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-04-07 17:24:56,852 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_uint [2022-04-07 17:24:56,852 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2022-04-07 17:24:56,852 INFO L130 BoogieDeclarations]: Found specification of procedure main [2022-04-07 17:24:56,852 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2022-04-07 17:24:56,852 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-04-07 17:24:56,852 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-04-07 17:24:56,852 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-04-07 17:24:56,853 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-04-07 17:24:56,853 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-04-07 17:24:56,895 INFO L234 CfgBuilder]: Building ICFG [2022-04-07 17:24:56,896 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-04-07 17:24:57,029 INFO L275 CfgBuilder]: Performing block encoding [2022-04-07 17:24:57,033 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-04-07 17:24:57,033 INFO L299 CfgBuilder]: Removed 4 assume(true) statements. [2022-04-07 17:24:57,034 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.04 05:24:57 BoogieIcfgContainer [2022-04-07 17:24:57,034 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-04-07 17:24:57,035 INFO L113 PluginConnector]: ------------------------IcfgTransformer---------------------------- [2022-04-07 17:24:57,035 INFO L271 PluginConnector]: Initializing IcfgTransformer... [2022-04-07 17:24:57,035 INFO L275 PluginConnector]: IcfgTransformer initialized [2022-04-07 17:24:57,037 INFO L185 PluginConnector]: Executing the observer IcfgTransformationObserver from plugin IcfgTransformer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.04 05:24:57" (1/1) ... [2022-04-07 17:24:57,039 INFO L168 ansformationObserver]: Applying ICFG transformation LOOP_ACCELERATION_JORDAN [2022-04-07 17:24:57,492 INFO L89 elerationTransformer]: Jordan loop acceleration statistics: 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult [2022-04-07 17:24:57,493 INFO L91 elerationTransformer]: Accelerated Formula: (and (= (+ v_main_~x~0_3 1) v_main_~x~0_4) (= v_main_~y~0_5 (+ v_main_~y~0_6 1)) (< 0 (mod v_main_~x~0_4 4294967296))) InVars {main_~x~0=v_main_~x~0_4, main_~y~0=v_main_~y~0_6} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] to Formula: (let ((.cse0 (mod v_main_~x~0_4 4294967296))) (or (and (= |v_main_#t~post5_3| |v_main_#t~post5_1|) (= v_main_~x~0_4 v_main_~x~0_3) (= |v_main_#t~post6_3| |v_main_#t~post6_1|) (<= .cse0 0) (= v_main_~y~0_6 v_main_~y~0_5)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ v_main_~x~0_4 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)) (not (<= (+ v_main_~y~0_6 v_it_1 1) v_main_~y~0_5)))) (< v_main_~y~0_6 v_main_~y~0_5) (< 0 .cse0) (= v_main_~x~0_3 (+ v_main_~x~0_4 v_main_~y~0_6 (* (- 1) v_main_~y~0_5)))))) InVars {main_~y~0=v_main_~y~0_6, main_#t~post5=|v_main_#t~post5_3|, main_~x~0=v_main_~x~0_4, main_#t~post6=|v_main_#t~post6_3|} OutVars{main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_~x~0=v_main_~x~0_3, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] [2022-04-07 17:24:57,762 INFO L89 elerationTransformer]: Jordan loop acceleration statistics: 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult [2022-04-07 17:24:57,763 INFO L91 elerationTransformer]: Accelerated Formula: (and (= v_main_~z~0_7 (+ v_main_~z~0_6 1)) (= v_main_~x~0_8 (+ v_main_~x~0_9 1)) (< 0 (mod v_main_~z~0_7 4294967296))) InVars {main_~x~0=v_main_~x~0_9, main_~z~0=v_main_~z~0_7} OutVars{main_~x~0=v_main_~x~0_8, main_~z~0=v_main_~z~0_6, main_#t~post8=|v_main_#t~post8_1|, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] to Formula: (let ((.cse0 (mod v_main_~z~0_7 4294967296))) (or (and (= v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_7 v_main_~z~0_6) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|) (<= .cse0 0)) (and (< v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_6 (+ (* (- 1) v_main_~x~0_8) v_main_~x~0_9 v_main_~z~0_7)) (forall ((v_it_2 Int)) (or (not (<= 1 v_it_2)) (not (<= (+ v_main_~x~0_9 v_it_2 1) v_main_~x~0_8)) (< 0 (mod (+ v_main_~z~0_7 (* v_it_2 4294967295)) 4294967296)))) (< 0 .cse0)))) InVars {main_~x~0=v_main_~x~0_9, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_8, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_6, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] [2022-04-07 17:24:58,007 INFO L89 elerationTransformer]: Jordan loop acceleration statistics: 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult [2022-04-07 17:24:58,007 INFO L91 elerationTransformer]: Accelerated Formula: (and (< 0 (mod v_main_~y~0_4 4294967296)) (= (+ v_main_~z~0_3 1) v_main_~z~0_2) (= v_main_~y~0_4 (+ v_main_~y~0_3 1))) InVars {main_~z~0=v_main_~z~0_3, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post10=|v_main_#t~post10_1|, main_~z~0=v_main_~z~0_2, main_~y~0=v_main_~y~0_3, main_#t~post9=|v_main_#t~post9_1|} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] to Formula: (let ((.cse0 (mod v_main_~y~0_4 4294967296))) (or (and (= (+ (* (- 1) v_main_~y~0_3) v_main_~y~0_4 v_main_~z~0_3) v_main_~z~0_2) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_4 (* v_it_3 4294967295)) 4294967296)) (not (<= (+ v_main_~y~0_3 v_it_3 1) v_main_~y~0_4)))) (< v_main_~y~0_3 v_main_~y~0_4)) (and (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= v_main_~y~0_4 v_main_~y~0_3) (<= .cse0 0) (= |v_main_#t~post9_3| |v_main_#t~post9_1|)))) InVars {main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_3, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] [2022-04-07 17:24:58,225 INFO L89 elerationTransformer]: Jordan loop acceleration statistics: 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult [2022-04-07 17:24:58,226 INFO L91 elerationTransformer]: Accelerated Formula: (and (= v_main_~x~0_7 (+ v_main_~x~0_6 1)) (< 0 (mod v_main_~x~0_7 4294967296)) (= (+ v_main_~y~0_8 1) v_main_~y~0_7)) InVars {main_~x~0=v_main_~x~0_7, main_~y~0=v_main_~y~0_8} OutVars{main_~x~0=v_main_~x~0_6, main_~y~0=v_main_~y~0_7, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] to Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] [2022-04-07 17:24:58,229 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 07.04 05:24:58 BasicIcfg [2022-04-07 17:24:58,229 INFO L132 PluginConnector]: ------------------------ END IcfgTransformer---------------------------- [2022-04-07 17:24:58,231 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-04-07 17:24:58,231 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-04-07 17:24:58,233 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-04-07 17:24:58,233 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.04 05:24:56" (1/4) ... [2022-04-07 17:24:58,243 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@579a394d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.04 05:24:58, skipping insertion in model container [2022-04-07 17:24:58,243 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 05:24:56" (2/4) ... [2022-04-07 17:24:58,243 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@579a394d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.04 05:24:58, skipping insertion in model container [2022-04-07 17:24:58,244 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.04 05:24:57" (3/4) ... [2022-04-07 17:24:58,244 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@579a394d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.04 05:24:58, skipping insertion in model container [2022-04-07 17:24:58,244 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 07.04 05:24:58" (4/4) ... [2022-04-07 17:24:58,245 INFO L111 eAbstractionObserver]: Analyzing ICFG in-de41.cJordan [2022-04-07 17:24:58,248 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:ForwardPredicates Determinization: PREDICATE_ABSTRACTION [2022-04-07 17:24:58,248 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-04-07 17:24:58,271 INFO L339 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-04-07 17:24:58,275 INFO L340 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=ForwardPredicates, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=false, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=All, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP [2022-04-07 17:24:58,275 INFO L341 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-04-07 17:24:58,286 INFO L276 IsEmpty]: Start isEmpty. Operand has 23 states, 15 states have (on average 1.6666666666666667) internal successors, (25), 16 states have internal predecessors, (25), 3 states have call successors, (3), 3 states have call predecessors, (3), 3 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 17:24:58,289 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2022-04-07 17:24:58,289 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 17:24:58,290 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 17:24:58,290 INFO L403 AbstractCegarLoop]: === Iteration 1 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 17:24:58,293 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 17:24:58,293 INFO L85 PathProgramCache]: Analyzing trace with hash -2015447748, now seen corresponding path program 1 times [2022-04-07 17:24:58,299 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 17:24:58,299 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2003884750] [2022-04-07 17:24:58,299 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:24:58,300 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 17:24:58,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:24:58,387 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 17:24:58,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:24:58,406 INFO L290 TraceCheckUtils]: 0: Hoare triple {31#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {26#true} is VALID [2022-04-07 17:24:58,406 INFO L290 TraceCheckUtils]: 1: Hoare triple {26#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {26#true} is VALID [2022-04-07 17:24:58,407 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {26#true} {26#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {26#true} is VALID [2022-04-07 17:24:58,408 INFO L272 TraceCheckUtils]: 0: Hoare triple {26#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {31#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 17:24:58,409 INFO L290 TraceCheckUtils]: 1: Hoare triple {31#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {26#true} is VALID [2022-04-07 17:24:58,409 INFO L290 TraceCheckUtils]: 2: Hoare triple {26#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {26#true} is VALID [2022-04-07 17:24:58,409 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {26#true} {26#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {26#true} is VALID [2022-04-07 17:24:58,409 INFO L272 TraceCheckUtils]: 4: Hoare triple {26#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {26#true} is VALID [2022-04-07 17:24:58,410 INFO L290 TraceCheckUtils]: 5: Hoare triple {26#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {26#true} is VALID [2022-04-07 17:24:58,410 INFO L290 TraceCheckUtils]: 6: Hoare triple {26#true} [81] L16-2-->L16-3: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {27#false} is VALID [2022-04-07 17:24:58,411 INFO L290 TraceCheckUtils]: 7: Hoare triple {27#false} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {27#false} is VALID [2022-04-07 17:24:58,411 INFO L290 TraceCheckUtils]: 8: Hoare triple {27#false} [85] L23-2-->L29-1: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {27#false} is VALID [2022-04-07 17:24:58,411 INFO L290 TraceCheckUtils]: 9: Hoare triple {27#false} [88] L29-1-->L35-1: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {27#false} is VALID [2022-04-07 17:24:58,411 INFO L290 TraceCheckUtils]: 10: Hoare triple {27#false} [91] L35-1-->L35-2: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {27#false} is VALID [2022-04-07 17:24:58,411 INFO L272 TraceCheckUtils]: 11: Hoare triple {27#false} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {27#false} is VALID [2022-04-07 17:24:58,411 INFO L290 TraceCheckUtils]: 12: Hoare triple {27#false} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {27#false} is VALID [2022-04-07 17:24:58,412 INFO L290 TraceCheckUtils]: 13: Hoare triple {27#false} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {27#false} is VALID [2022-04-07 17:24:58,413 INFO L290 TraceCheckUtils]: 14: Hoare triple {27#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {27#false} is VALID [2022-04-07 17:24:58,413 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 17:24:58,413 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 17:24:58,413 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2003884750] [2022-04-07 17:24:58,414 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2003884750] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-07 17:24:58,414 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-07 17:24:58,414 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-04-07 17:24:58,416 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1383895116] [2022-04-07 17:24:58,416 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-07 17:24:58,422 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 15 [2022-04-07 17:24:58,423 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 17:24:58,425 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:24:58,439 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 15 edges. 15 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 17:24:58,439 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-04-07 17:24:58,440 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 17:24:58,465 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-04-07 17:24:58,465 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-04-07 17:24:58,467 INFO L87 Difference]: Start difference. First operand has 23 states, 15 states have (on average 1.6666666666666667) internal successors, (25), 16 states have internal predecessors, (25), 3 states have call successors, (3), 3 states have call predecessors, (3), 3 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:24:58,510 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:24:58,511 INFO L93 Difference]: Finished difference Result 23 states and 26 transitions. [2022-04-07 17:24:58,511 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-04-07 17:24:58,511 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 15 [2022-04-07 17:24:58,511 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 17:24:58,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:24:58,524 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 31 transitions. [2022-04-07 17:24:58,524 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:24:58,528 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 31 transitions. [2022-04-07 17:24:58,528 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 3 states and 31 transitions. [2022-04-07 17:24:58,554 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 31 edges. 31 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 17:24:58,560 INFO L225 Difference]: With dead ends: 23 [2022-04-07 17:24:58,560 INFO L226 Difference]: Without dead ends: 16 [2022-04-07 17:24:58,561 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-04-07 17:24:58,564 INFO L913 BasicCegarLoop]: 25 mSDtfsCounter, 17 mSDsluCounter, 3 mSDsCounter, 0 mSdLazyCounter, 3 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 18 SdHoareTripleChecker+Valid, 28 SdHoareTripleChecker+Invalid, 5 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 3 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-07 17:24:58,565 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [18 Valid, 28 Invalid, 5 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 3 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-07 17:24:58,575 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states. [2022-04-07 17:24:58,582 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 16. [2022-04-07 17:24:58,582 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 17:24:58,582 INFO L82 GeneralOperation]: Start isEquivalent. First operand 16 states. Second operand has 16 states, 11 states have (on average 1.3636363636363635) internal successors, (15), 11 states have internal predecessors, (15), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:24:58,583 INFO L74 IsIncluded]: Start isIncluded. First operand 16 states. Second operand has 16 states, 11 states have (on average 1.3636363636363635) internal successors, (15), 11 states have internal predecessors, (15), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:24:58,583 INFO L87 Difference]: Start difference. First operand 16 states. Second operand has 16 states, 11 states have (on average 1.3636363636363635) internal successors, (15), 11 states have internal predecessors, (15), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:24:58,588 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:24:58,589 INFO L93 Difference]: Finished difference Result 16 states and 19 transitions. [2022-04-07 17:24:58,589 INFO L276 IsEmpty]: Start isEmpty. Operand 16 states and 19 transitions. [2022-04-07 17:24:58,589 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:24:58,589 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:24:58,589 INFO L74 IsIncluded]: Start isIncluded. First operand has 16 states, 11 states have (on average 1.3636363636363635) internal successors, (15), 11 states have internal predecessors, (15), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 16 states. [2022-04-07 17:24:58,590 INFO L87 Difference]: Start difference. First operand has 16 states, 11 states have (on average 1.3636363636363635) internal successors, (15), 11 states have internal predecessors, (15), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 16 states. [2022-04-07 17:24:58,591 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:24:58,592 INFO L93 Difference]: Finished difference Result 16 states and 19 transitions. [2022-04-07 17:24:58,592 INFO L276 IsEmpty]: Start isEmpty. Operand 16 states and 19 transitions. [2022-04-07 17:24:58,592 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:24:58,592 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:24:58,593 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 17:24:58,593 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 17:24:58,595 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 11 states have (on average 1.3636363636363635) internal successors, (15), 11 states have internal predecessors, (15), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:24:58,597 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 19 transitions. [2022-04-07 17:24:58,601 INFO L78 Accepts]: Start accepts. Automaton has 16 states and 19 transitions. Word has length 15 [2022-04-07 17:24:58,601 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 17:24:58,601 INFO L478 AbstractCegarLoop]: Abstraction has 16 states and 19 transitions. [2022-04-07 17:24:58,601 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:24:58,601 INFO L276 IsEmpty]: Start isEmpty. Operand 16 states and 19 transitions. [2022-04-07 17:24:58,602 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2022-04-07 17:24:58,602 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 17:24:58,602 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 17:24:58,602 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-04-07 17:24:58,602 INFO L403 AbstractCegarLoop]: === Iteration 2 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 17:24:58,604 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 17:24:58,604 INFO L85 PathProgramCache]: Analyzing trace with hash 1389121438, now seen corresponding path program 1 times [2022-04-07 17:24:58,604 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 17:24:58,605 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [219373727] [2022-04-07 17:24:58,605 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:24:58,605 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 17:24:58,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:24:58,793 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 17:24:58,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:24:58,803 INFO L290 TraceCheckUtils]: 0: Hoare triple {115#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {105#true} is VALID [2022-04-07 17:24:58,803 INFO L290 TraceCheckUtils]: 1: Hoare triple {105#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {105#true} is VALID [2022-04-07 17:24:58,803 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {105#true} {105#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {105#true} is VALID [2022-04-07 17:24:58,804 INFO L272 TraceCheckUtils]: 0: Hoare triple {105#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {115#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 17:24:58,804 INFO L290 TraceCheckUtils]: 1: Hoare triple {115#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {105#true} is VALID [2022-04-07 17:24:58,804 INFO L290 TraceCheckUtils]: 2: Hoare triple {105#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {105#true} is VALID [2022-04-07 17:24:58,804 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {105#true} {105#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {105#true} is VALID [2022-04-07 17:24:58,804 INFO L272 TraceCheckUtils]: 4: Hoare triple {105#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {105#true} is VALID [2022-04-07 17:24:58,805 INFO L290 TraceCheckUtils]: 5: Hoare triple {105#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {110#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} is VALID [2022-04-07 17:24:58,806 INFO L290 TraceCheckUtils]: 6: Hoare triple {110#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {111#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:24:58,806 INFO L290 TraceCheckUtils]: 7: Hoare triple {111#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {111#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:24:58,807 INFO L290 TraceCheckUtils]: 8: Hoare triple {111#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {111#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:24:58,807 INFO L290 TraceCheckUtils]: 9: Hoare triple {111#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {111#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:24:58,808 INFO L290 TraceCheckUtils]: 10: Hoare triple {111#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {112#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0))} is VALID [2022-04-07 17:24:58,809 INFO L272 TraceCheckUtils]: 11: Hoare triple {112#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {113#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-07 17:24:58,809 INFO L290 TraceCheckUtils]: 12: Hoare triple {113#(not (= |__VERIFIER_assert_#in~cond| 0))} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {114#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-07 17:24:58,810 INFO L290 TraceCheckUtils]: 13: Hoare triple {114#(not (= __VERIFIER_assert_~cond 0))} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {106#false} is VALID [2022-04-07 17:24:58,810 INFO L290 TraceCheckUtils]: 14: Hoare triple {106#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {106#false} is VALID [2022-04-07 17:24:58,810 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 17:24:58,810 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 17:24:58,810 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [219373727] [2022-04-07 17:24:58,810 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [219373727] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-07 17:24:58,811 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-07 17:24:58,811 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2022-04-07 17:24:58,811 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1116715881] [2022-04-07 17:24:58,811 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-07 17:24:58,812 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 7 states have (on average 1.5714285714285714) internal successors, (11), 6 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 15 [2022-04-07 17:24:58,813 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 17:24:58,813 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 8 states, 7 states have (on average 1.5714285714285714) internal successors, (11), 6 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:24:58,824 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 15 edges. 15 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 17:24:58,824 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-04-07 17:24:58,827 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 17:24:58,828 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-04-07 17:24:58,829 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2022-04-07 17:24:58,829 INFO L87 Difference]: Start difference. First operand 16 states and 19 transitions. Second operand has 8 states, 7 states have (on average 1.5714285714285714) internal successors, (11), 6 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:24:59,012 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:24:59,012 INFO L93 Difference]: Finished difference Result 27 states and 36 transitions. [2022-04-07 17:24:59,012 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-04-07 17:24:59,012 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 7 states have (on average 1.5714285714285714) internal successors, (11), 6 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 15 [2022-04-07 17:24:59,012 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 17:24:59,012 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 7 states have (on average 1.5714285714285714) internal successors, (11), 6 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:24:59,014 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 37 transitions. [2022-04-07 17:24:59,014 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 7 states have (on average 1.5714285714285714) internal successors, (11), 6 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:24:59,015 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 37 transitions. [2022-04-07 17:24:59,015 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 7 states and 37 transitions. [2022-04-07 17:24:59,048 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 37 edges. 37 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 17:24:59,049 INFO L225 Difference]: With dead ends: 27 [2022-04-07 17:24:59,049 INFO L226 Difference]: Without dead ends: 24 [2022-04-07 17:24:59,049 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=36, Invalid=96, Unknown=0, NotChecked=0, Total=132 [2022-04-07 17:24:59,050 INFO L913 BasicCegarLoop]: 10 mSDtfsCounter, 20 mSDsluCounter, 32 mSDsCounter, 0 mSdLazyCounter, 59 mSolverCounterSat, 8 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 20 SdHoareTripleChecker+Valid, 42 SdHoareTripleChecker+Invalid, 71 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 8 IncrementalHoareTripleChecker+Valid, 59 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 4 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-07 17:24:59,050 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [20 Valid, 42 Invalid, 71 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [8 Valid, 59 Invalid, 0 Unknown, 4 Unchecked, 0.1s Time] [2022-04-07 17:24:59,051 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24 states. [2022-04-07 17:24:59,052 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24 to 21. [2022-04-07 17:24:59,052 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 17:24:59,052 INFO L82 GeneralOperation]: Start isEquivalent. First operand 24 states. Second operand has 21 states, 16 states have (on average 1.4375) internal successors, (23), 16 states have internal predecessors, (23), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:24:59,053 INFO L74 IsIncluded]: Start isIncluded. First operand 24 states. Second operand has 21 states, 16 states have (on average 1.4375) internal successors, (23), 16 states have internal predecessors, (23), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:24:59,053 INFO L87 Difference]: Start difference. First operand 24 states. Second operand has 21 states, 16 states have (on average 1.4375) internal successors, (23), 16 states have internal predecessors, (23), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:24:59,054 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:24:59,054 INFO L93 Difference]: Finished difference Result 24 states and 33 transitions. [2022-04-07 17:24:59,054 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 33 transitions. [2022-04-07 17:24:59,054 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:24:59,055 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:24:59,055 INFO L74 IsIncluded]: Start isIncluded. First operand has 21 states, 16 states have (on average 1.4375) internal successors, (23), 16 states have internal predecessors, (23), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 24 states. [2022-04-07 17:24:59,055 INFO L87 Difference]: Start difference. First operand has 21 states, 16 states have (on average 1.4375) internal successors, (23), 16 states have internal predecessors, (23), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 24 states. [2022-04-07 17:24:59,056 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:24:59,056 INFO L93 Difference]: Finished difference Result 24 states and 33 transitions. [2022-04-07 17:24:59,056 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 33 transitions. [2022-04-07 17:24:59,056 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:24:59,056 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:24:59,056 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 17:24:59,056 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 17:24:59,057 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21 states, 16 states have (on average 1.4375) internal successors, (23), 16 states have internal predecessors, (23), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:24:59,057 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 27 transitions. [2022-04-07 17:24:59,057 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 27 transitions. Word has length 15 [2022-04-07 17:24:59,058 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 17:24:59,058 INFO L478 AbstractCegarLoop]: Abstraction has 21 states and 27 transitions. [2022-04-07 17:24:59,058 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 7 states have (on average 1.5714285714285714) internal successors, (11), 6 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:24:59,058 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 27 transitions. [2022-04-07 17:24:59,058 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2022-04-07 17:24:59,058 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 17:24:59,058 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 17:24:59,058 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-04-07 17:24:59,059 INFO L403 AbstractCegarLoop]: === Iteration 3 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 17:24:59,059 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 17:24:59,059 INFO L85 PathProgramCache]: Analyzing trace with hash 139812261, now seen corresponding path program 1 times [2022-04-07 17:24:59,059 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 17:24:59,059 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [142945769] [2022-04-07 17:24:59,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:24:59,059 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 17:24:59,070 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.0))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-07 17:24:59,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:24:59,090 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.1))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-07 17:24:59,176 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 17:24:59,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:24:59,195 INFO L290 TraceCheckUtils]: 0: Hoare triple {232#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {222#true} is VALID [2022-04-07 17:24:59,195 INFO L290 TraceCheckUtils]: 1: Hoare triple {222#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {222#true} is VALID [2022-04-07 17:24:59,195 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {222#true} {222#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {222#true} is VALID [2022-04-07 17:24:59,196 INFO L272 TraceCheckUtils]: 0: Hoare triple {222#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {232#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 17:24:59,196 INFO L290 TraceCheckUtils]: 1: Hoare triple {232#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {222#true} is VALID [2022-04-07 17:24:59,196 INFO L290 TraceCheckUtils]: 2: Hoare triple {222#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {222#true} is VALID [2022-04-07 17:24:59,196 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {222#true} {222#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {222#true} is VALID [2022-04-07 17:24:59,197 INFO L272 TraceCheckUtils]: 4: Hoare triple {222#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {222#true} is VALID [2022-04-07 17:24:59,201 INFO L290 TraceCheckUtils]: 5: Hoare triple {222#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {227#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} is VALID [2022-04-07 17:24:59,202 INFO L290 TraceCheckUtils]: 6: Hoare triple {227#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {228#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:24:59,203 INFO L290 TraceCheckUtils]: 7: Hoare triple {228#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {228#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:24:59,203 INFO L290 TraceCheckUtils]: 8: Hoare triple {228#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {228#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:24:59,204 INFO L290 TraceCheckUtils]: 9: Hoare triple {228#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {228#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:24:59,205 INFO L290 TraceCheckUtils]: 10: Hoare triple {228#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [93] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {229#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is VALID [2022-04-07 17:24:59,206 INFO L290 TraceCheckUtils]: 11: Hoare triple {229#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {229#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is VALID [2022-04-07 17:24:59,207 INFO L272 TraceCheckUtils]: 12: Hoare triple {229#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {230#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-07 17:24:59,207 INFO L290 TraceCheckUtils]: 13: Hoare triple {230#(not (= |__VERIFIER_assert_#in~cond| 0))} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {231#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-07 17:24:59,207 INFO L290 TraceCheckUtils]: 14: Hoare triple {231#(not (= __VERIFIER_assert_~cond 0))} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {223#false} is VALID [2022-04-07 17:24:59,208 INFO L290 TraceCheckUtils]: 15: Hoare triple {223#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {223#false} is VALID [2022-04-07 17:24:59,208 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 17:24:59,208 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 17:24:59,208 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [142945769] [2022-04-07 17:24:59,208 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [142945769] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 17:24:59,208 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1770025322] [2022-04-07 17:24:59,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:24:59,209 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 17:24:59,209 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 17:24:59,216 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 17:24:59,244 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-04-07 17:24:59,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:24:59,264 INFO L263 TraceCheckSpWp]: Trace formula consists of 61 conjuncts, 9 conjunts are in the unsatisfiable core [2022-04-07 17:24:59,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:24:59,288 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 17:24:59,936 INFO L272 TraceCheckUtils]: 0: Hoare triple {222#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {222#true} is VALID [2022-04-07 17:24:59,936 INFO L290 TraceCheckUtils]: 1: Hoare triple {222#true} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {222#true} is VALID [2022-04-07 17:24:59,936 INFO L290 TraceCheckUtils]: 2: Hoare triple {222#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {222#true} is VALID [2022-04-07 17:24:59,937 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {222#true} {222#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {222#true} is VALID [2022-04-07 17:24:59,937 INFO L272 TraceCheckUtils]: 4: Hoare triple {222#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {222#true} is VALID [2022-04-07 17:24:59,937 INFO L290 TraceCheckUtils]: 5: Hoare triple {222#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {251#(= main_~n~0 main_~x~0)} is VALID [2022-04-07 17:24:59,938 INFO L290 TraceCheckUtils]: 6: Hoare triple {251#(= main_~n~0 main_~x~0)} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {255#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-07 17:24:59,938 INFO L290 TraceCheckUtils]: 7: Hoare triple {255#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {255#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-07 17:24:59,938 INFO L290 TraceCheckUtils]: 8: Hoare triple {255#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {255#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-07 17:24:59,939 INFO L290 TraceCheckUtils]: 9: Hoare triple {255#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {265#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-07 17:24:59,940 INFO L290 TraceCheckUtils]: 10: Hoare triple {265#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} [93] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {265#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-07 17:24:59,940 INFO L290 TraceCheckUtils]: 11: Hoare triple {265#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {272#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~n~0 4294967296))))} is VALID [2022-04-07 17:24:59,941 INFO L272 TraceCheckUtils]: 12: Hoare triple {272#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~n~0 4294967296))))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {276#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 17:24:59,942 INFO L290 TraceCheckUtils]: 13: Hoare triple {276#(<= 1 |__VERIFIER_assert_#in~cond|)} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {280#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 17:24:59,942 INFO L290 TraceCheckUtils]: 14: Hoare triple {280#(<= 1 __VERIFIER_assert_~cond)} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {223#false} is VALID [2022-04-07 17:24:59,942 INFO L290 TraceCheckUtils]: 15: Hoare triple {223#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {223#false} is VALID [2022-04-07 17:24:59,942 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-07 17:24:59,943 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-04-07 17:24:59,943 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1770025322] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-07 17:24:59,943 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-04-07 17:24:59,943 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [8] total 14 [2022-04-07 17:24:59,943 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1983395912] [2022-04-07 17:24:59,943 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-07 17:24:59,944 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 7 states have (on average 1.7142857142857142) internal successors, (12), 7 states have internal predecessors, (12), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 16 [2022-04-07 17:24:59,944 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 17:24:59,944 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 8 states, 7 states have (on average 1.7142857142857142) internal successors, (12), 7 states have internal predecessors, (12), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:24:59,956 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 16 edges. 16 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 17:24:59,956 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-04-07 17:24:59,956 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 17:24:59,957 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-04-07 17:24:59,957 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=142, Unknown=0, NotChecked=0, Total=182 [2022-04-07 17:24:59,957 INFO L87 Difference]: Start difference. First operand 21 states and 27 transitions. Second operand has 8 states, 7 states have (on average 1.7142857142857142) internal successors, (12), 7 states have internal predecessors, (12), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:25:00,044 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:25:00,044 INFO L93 Difference]: Finished difference Result 26 states and 33 transitions. [2022-04-07 17:25:00,044 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-04-07 17:25:00,045 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 7 states have (on average 1.7142857142857142) internal successors, (12), 7 states have internal predecessors, (12), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 16 [2022-04-07 17:25:00,045 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 17:25:00,045 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 7 states have (on average 1.7142857142857142) internal successors, (12), 7 states have internal predecessors, (12), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:25:00,046 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 31 transitions. [2022-04-07 17:25:00,046 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 7 states have (on average 1.7142857142857142) internal successors, (12), 7 states have internal predecessors, (12), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:25:00,047 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 31 transitions. [2022-04-07 17:25:00,047 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 7 states and 31 transitions. [2022-04-07 17:25:00,070 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 31 edges. 31 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 17:25:00,070 INFO L225 Difference]: With dead ends: 26 [2022-04-07 17:25:00,070 INFO L226 Difference]: Without dead ends: 19 [2022-04-07 17:25:00,071 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 11 SyntacticMatches, 1 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 42 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=46, Invalid=164, Unknown=0, NotChecked=0, Total=210 [2022-04-07 17:25:00,071 INFO L913 BasicCegarLoop]: 13 mSDtfsCounter, 9 mSDsluCounter, 51 mSDsCounter, 0 mSdLazyCounter, 30 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 9 SdHoareTripleChecker+Valid, 64 SdHoareTripleChecker+Invalid, 38 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 30 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 7 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-07 17:25:00,072 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [9 Valid, 64 Invalid, 38 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 30 Invalid, 0 Unknown, 7 Unchecked, 0.0s Time] [2022-04-07 17:25:00,072 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19 states. [2022-04-07 17:25:00,073 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19 to 19. [2022-04-07 17:25:00,073 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 17:25:00,073 INFO L82 GeneralOperation]: Start isEquivalent. First operand 19 states. Second operand has 19 states, 14 states have (on average 1.3571428571428572) internal successors, (19), 14 states have internal predecessors, (19), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:25:00,073 INFO L74 IsIncluded]: Start isIncluded. First operand 19 states. Second operand has 19 states, 14 states have (on average 1.3571428571428572) internal successors, (19), 14 states have internal predecessors, (19), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:25:00,074 INFO L87 Difference]: Start difference. First operand 19 states. Second operand has 19 states, 14 states have (on average 1.3571428571428572) internal successors, (19), 14 states have internal predecessors, (19), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:25:00,074 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:25:00,074 INFO L93 Difference]: Finished difference Result 19 states and 23 transitions. [2022-04-07 17:25:00,074 INFO L276 IsEmpty]: Start isEmpty. Operand 19 states and 23 transitions. [2022-04-07 17:25:00,075 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:25:00,075 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:25:00,075 INFO L74 IsIncluded]: Start isIncluded. First operand has 19 states, 14 states have (on average 1.3571428571428572) internal successors, (19), 14 states have internal predecessors, (19), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 19 states. [2022-04-07 17:25:00,075 INFO L87 Difference]: Start difference. First operand has 19 states, 14 states have (on average 1.3571428571428572) internal successors, (19), 14 states have internal predecessors, (19), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 19 states. [2022-04-07 17:25:00,076 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:25:00,076 INFO L93 Difference]: Finished difference Result 19 states and 23 transitions. [2022-04-07 17:25:00,076 INFO L276 IsEmpty]: Start isEmpty. Operand 19 states and 23 transitions. [2022-04-07 17:25:00,076 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:25:00,076 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:25:00,076 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 17:25:00,076 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 17:25:00,076 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19 states, 14 states have (on average 1.3571428571428572) internal successors, (19), 14 states have internal predecessors, (19), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:25:00,077 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 23 transitions. [2022-04-07 17:25:00,077 INFO L78 Accepts]: Start accepts. Automaton has 19 states and 23 transitions. Word has length 16 [2022-04-07 17:25:00,077 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 17:25:00,077 INFO L478 AbstractCegarLoop]: Abstraction has 19 states and 23 transitions. [2022-04-07 17:25:00,077 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 7 states have (on average 1.7142857142857142) internal successors, (12), 7 states have internal predecessors, (12), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:25:00,077 INFO L276 IsEmpty]: Start isEmpty. Operand 19 states and 23 transitions. [2022-04-07 17:25:00,078 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2022-04-07 17:25:00,078 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 17:25:00,078 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 17:25:00,099 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Forceful destruction successful, exit code 0 [2022-04-07 17:25:00,299 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2,2 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 17:25:00,299 INFO L403 AbstractCegarLoop]: === Iteration 4 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 17:25:00,300 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 17:25:00,300 INFO L85 PathProgramCache]: Analyzing trace with hash -894405051, now seen corresponding path program 1 times [2022-04-07 17:25:00,300 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 17:25:00,300 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [319694155] [2022-04-07 17:25:00,300 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:25:00,300 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 17:25:00,309 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_2.0))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-07 17:25:00,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:25:00,327 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_2.1))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-07 17:25:00,413 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 17:25:00,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:25:00,420 INFO L290 TraceCheckUtils]: 0: Hoare triple {381#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {371#true} is VALID [2022-04-07 17:25:00,420 INFO L290 TraceCheckUtils]: 1: Hoare triple {371#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {371#true} is VALID [2022-04-07 17:25:00,420 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {371#true} {371#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {371#true} is VALID [2022-04-07 17:25:00,423 INFO L272 TraceCheckUtils]: 0: Hoare triple {371#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {381#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 17:25:00,423 INFO L290 TraceCheckUtils]: 1: Hoare triple {381#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {371#true} is VALID [2022-04-07 17:25:00,423 INFO L290 TraceCheckUtils]: 2: Hoare triple {371#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {371#true} is VALID [2022-04-07 17:25:00,423 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {371#true} {371#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {371#true} is VALID [2022-04-07 17:25:00,424 INFO L272 TraceCheckUtils]: 4: Hoare triple {371#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {371#true} is VALID [2022-04-07 17:25:00,424 INFO L290 TraceCheckUtils]: 5: Hoare triple {371#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {376#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} is VALID [2022-04-07 17:25:00,425 INFO L290 TraceCheckUtils]: 6: Hoare triple {376#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {377#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} is VALID [2022-04-07 17:25:00,425 INFO L290 TraceCheckUtils]: 7: Hoare triple {377#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {377#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} is VALID [2022-04-07 17:25:00,426 INFO L290 TraceCheckUtils]: 8: Hoare triple {377#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} [87] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_7 4294967296))) (or (and (= v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_7 v_main_~z~0_6) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|) (<= .cse0 0)) (and (< v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_6 (+ (* (- 1) v_main_~x~0_8) v_main_~x~0_9 v_main_~z~0_7)) (forall ((v_it_2 Int)) (or (not (<= 1 v_it_2)) (not (<= (+ v_main_~x~0_9 v_it_2 1) v_main_~x~0_8)) (< 0 (mod (+ v_main_~z~0_7 (* v_it_2 4294967295)) 4294967296)))) (< 0 .cse0)))) InVars {main_~x~0=v_main_~x~0_9, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_8, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_6, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {378#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0))} is VALID [2022-04-07 17:25:00,427 INFO L290 TraceCheckUtils]: 9: Hoare triple {378#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {378#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0))} is VALID [2022-04-07 17:25:00,427 INFO L290 TraceCheckUtils]: 10: Hoare triple {378#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {378#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0))} is VALID [2022-04-07 17:25:00,428 INFO L290 TraceCheckUtils]: 11: Hoare triple {378#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {378#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0))} is VALID [2022-04-07 17:25:00,429 INFO L272 TraceCheckUtils]: 12: Hoare triple {378#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {379#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-07 17:25:00,431 INFO L290 TraceCheckUtils]: 13: Hoare triple {379#(not (= |__VERIFIER_assert_#in~cond| 0))} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {380#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-07 17:25:00,433 INFO L290 TraceCheckUtils]: 14: Hoare triple {380#(not (= __VERIFIER_assert_~cond 0))} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {372#false} is VALID [2022-04-07 17:25:00,433 INFO L290 TraceCheckUtils]: 15: Hoare triple {372#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {372#false} is VALID [2022-04-07 17:25:00,433 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 17:25:00,433 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 17:25:00,433 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [319694155] [2022-04-07 17:25:00,433 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [319694155] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 17:25:00,433 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [471051447] [2022-04-07 17:25:00,433 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:25:00,434 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 17:25:00,434 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 17:25:00,434 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 17:25:00,456 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-04-07 17:25:00,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:25:00,473 INFO L263 TraceCheckSpWp]: Trace formula consists of 61 conjuncts, 7 conjunts are in the unsatisfiable core [2022-04-07 17:25:00,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:25:00,478 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 17:25:00,946 INFO L272 TraceCheckUtils]: 0: Hoare triple {371#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {371#true} is VALID [2022-04-07 17:25:00,947 INFO L290 TraceCheckUtils]: 1: Hoare triple {371#true} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {371#true} is VALID [2022-04-07 17:25:00,947 INFO L290 TraceCheckUtils]: 2: Hoare triple {371#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {371#true} is VALID [2022-04-07 17:25:00,947 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {371#true} {371#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {371#true} is VALID [2022-04-07 17:25:00,947 INFO L272 TraceCheckUtils]: 4: Hoare triple {371#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {371#true} is VALID [2022-04-07 17:25:00,947 INFO L290 TraceCheckUtils]: 5: Hoare triple {371#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {400#(= main_~n~0 main_~x~0)} is VALID [2022-04-07 17:25:00,948 INFO L290 TraceCheckUtils]: 6: Hoare triple {400#(= main_~n~0 main_~x~0)} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {404#(not (< 0 (mod main_~n~0 4294967296)))} is VALID [2022-04-07 17:25:00,949 INFO L290 TraceCheckUtils]: 7: Hoare triple {404#(not (< 0 (mod main_~n~0 4294967296)))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {404#(not (< 0 (mod main_~n~0 4294967296)))} is VALID [2022-04-07 17:25:00,949 INFO L290 TraceCheckUtils]: 8: Hoare triple {404#(not (< 0 (mod main_~n~0 4294967296)))} [87] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_7 4294967296))) (or (and (= v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_7 v_main_~z~0_6) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|) (<= .cse0 0)) (and (< v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_6 (+ (* (- 1) v_main_~x~0_8) v_main_~x~0_9 v_main_~z~0_7)) (forall ((v_it_2 Int)) (or (not (<= 1 v_it_2)) (not (<= (+ v_main_~x~0_9 v_it_2 1) v_main_~x~0_8)) (< 0 (mod (+ v_main_~z~0_7 (* v_it_2 4294967295)) 4294967296)))) (< 0 .cse0)))) InVars {main_~x~0=v_main_~x~0_9, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_8, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_6, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {404#(not (< 0 (mod main_~n~0 4294967296)))} is VALID [2022-04-07 17:25:00,949 INFO L290 TraceCheckUtils]: 9: Hoare triple {404#(not (< 0 (mod main_~n~0 4294967296)))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {404#(not (< 0 (mod main_~n~0 4294967296)))} is VALID [2022-04-07 17:25:00,950 INFO L290 TraceCheckUtils]: 10: Hoare triple {404#(not (< 0 (mod main_~n~0 4294967296)))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {417#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~n~0 4294967296))))} is VALID [2022-04-07 17:25:00,951 INFO L290 TraceCheckUtils]: 11: Hoare triple {417#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~n~0 4294967296))))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {417#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~n~0 4294967296))))} is VALID [2022-04-07 17:25:00,951 INFO L272 TraceCheckUtils]: 12: Hoare triple {417#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~n~0 4294967296))))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {424#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 17:25:00,952 INFO L290 TraceCheckUtils]: 13: Hoare triple {424#(<= 1 |__VERIFIER_assert_#in~cond|)} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {428#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 17:25:00,953 INFO L290 TraceCheckUtils]: 14: Hoare triple {428#(<= 1 __VERIFIER_assert_~cond)} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {372#false} is VALID [2022-04-07 17:25:00,954 INFO L290 TraceCheckUtils]: 15: Hoare triple {372#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {372#false} is VALID [2022-04-07 17:25:00,954 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-07 17:25:00,954 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-04-07 17:25:00,954 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [471051447] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-07 17:25:00,954 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-04-07 17:25:00,954 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [8] total 13 [2022-04-07 17:25:00,954 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1551960537] [2022-04-07 17:25:00,954 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-07 17:25:00,955 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 1.7142857142857142) internal successors, (12), 6 states have internal predecessors, (12), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 16 [2022-04-07 17:25:00,955 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 17:25:00,955 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 7 states, 7 states have (on average 1.7142857142857142) internal successors, (12), 6 states have internal predecessors, (12), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:25:00,970 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 16 edges. 16 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 17:25:00,970 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-04-07 17:25:00,971 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 17:25:00,971 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-04-07 17:25:00,971 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=122, Unknown=0, NotChecked=0, Total=156 [2022-04-07 17:25:00,971 INFO L87 Difference]: Start difference. First operand 19 states and 23 transitions. Second operand has 7 states, 7 states have (on average 1.7142857142857142) internal successors, (12), 6 states have internal predecessors, (12), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:25:01,051 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:25:01,051 INFO L93 Difference]: Finished difference Result 25 states and 31 transitions. [2022-04-07 17:25:01,051 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-04-07 17:25:01,051 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 1.7142857142857142) internal successors, (12), 6 states have internal predecessors, (12), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 16 [2022-04-07 17:25:01,051 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 17:25:01,051 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7 states, 7 states have (on average 1.7142857142857142) internal successors, (12), 6 states have internal predecessors, (12), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:25:01,052 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 32 transitions. [2022-04-07 17:25:01,052 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7 states, 7 states have (on average 1.7142857142857142) internal successors, (12), 6 states have internal predecessors, (12), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:25:01,053 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 32 transitions. [2022-04-07 17:25:01,053 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 8 states and 32 transitions. [2022-04-07 17:25:01,077 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 32 edges. 32 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 17:25:01,078 INFO L225 Difference]: With dead ends: 25 [2022-04-07 17:25:01,078 INFO L226 Difference]: Without dead ends: 22 [2022-04-07 17:25:01,078 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 14 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=45, Invalid=165, Unknown=0, NotChecked=0, Total=210 [2022-04-07 17:25:01,079 INFO L913 BasicCegarLoop]: 14 mSDtfsCounter, 6 mSDsluCounter, 58 mSDsCounter, 0 mSdLazyCounter, 22 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 6 SdHoareTripleChecker+Valid, 72 SdHoareTripleChecker+Invalid, 27 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 22 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 5 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-07 17:25:01,079 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [6 Valid, 72 Invalid, 27 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 22 Invalid, 0 Unknown, 5 Unchecked, 0.0s Time] [2022-04-07 17:25:01,079 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2022-04-07 17:25:01,080 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2022-04-07 17:25:01,080 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 17:25:01,081 INFO L82 GeneralOperation]: Start isEquivalent. First operand 22 states. Second operand has 22 states, 17 states have (on average 1.411764705882353) internal successors, (24), 17 states have internal predecessors, (24), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:25:01,081 INFO L74 IsIncluded]: Start isIncluded. First operand 22 states. Second operand has 22 states, 17 states have (on average 1.411764705882353) internal successors, (24), 17 states have internal predecessors, (24), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:25:01,081 INFO L87 Difference]: Start difference. First operand 22 states. Second operand has 22 states, 17 states have (on average 1.411764705882353) internal successors, (24), 17 states have internal predecessors, (24), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:25:01,082 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:25:01,082 INFO L93 Difference]: Finished difference Result 22 states and 28 transitions. [2022-04-07 17:25:01,082 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 28 transitions. [2022-04-07 17:25:01,082 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:25:01,082 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:25:01,082 INFO L74 IsIncluded]: Start isIncluded. First operand has 22 states, 17 states have (on average 1.411764705882353) internal successors, (24), 17 states have internal predecessors, (24), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 22 states. [2022-04-07 17:25:01,082 INFO L87 Difference]: Start difference. First operand has 22 states, 17 states have (on average 1.411764705882353) internal successors, (24), 17 states have internal predecessors, (24), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 22 states. [2022-04-07 17:25:01,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:25:01,083 INFO L93 Difference]: Finished difference Result 22 states and 28 transitions. [2022-04-07 17:25:01,083 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 28 transitions. [2022-04-07 17:25:01,083 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:25:01,083 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:25:01,084 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 17:25:01,084 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 17:25:01,084 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22 states, 17 states have (on average 1.411764705882353) internal successors, (24), 17 states have internal predecessors, (24), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:25:01,084 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 28 transitions. [2022-04-07 17:25:01,084 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 28 transitions. Word has length 16 [2022-04-07 17:25:01,084 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 17:25:01,084 INFO L478 AbstractCegarLoop]: Abstraction has 22 states and 28 transitions. [2022-04-07 17:25:01,085 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 1.7142857142857142) internal successors, (12), 6 states have internal predecessors, (12), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:25:01,085 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 28 transitions. [2022-04-07 17:25:01,085 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2022-04-07 17:25:01,085 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 17:25:01,085 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 17:25:01,103 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2022-04-07 17:25:01,299 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable3 [2022-04-07 17:25:01,299 INFO L403 AbstractCegarLoop]: === Iteration 5 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 17:25:01,300 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 17:25:01,300 INFO L85 PathProgramCache]: Analyzing trace with hash 1590526661, now seen corresponding path program 1 times [2022-04-07 17:25:01,300 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 17:25:01,300 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1231601128] [2022-04-07 17:25:01,300 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:25:01,300 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 17:25:01,309 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_1.0))) (+ main_~x~0_5 .cse0 (* (- 4294967296) (div (+ main_~x~0_5 .cse0) 4294967296)))) 0)) [2022-04-07 17:25:01,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:25:01,322 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_1.1))) (+ main_~x~0_5 .cse0 (* (- 4294967296) (div (+ main_~x~0_5 .cse0) 4294967296)))) 0)) [2022-04-07 17:25:01,426 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 17:25:01,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:25:01,433 INFO L290 TraceCheckUtils]: 0: Hoare triple {540#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {529#true} is VALID [2022-04-07 17:25:01,434 INFO L290 TraceCheckUtils]: 1: Hoare triple {529#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {529#true} is VALID [2022-04-07 17:25:01,434 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {529#true} {529#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {529#true} is VALID [2022-04-07 17:25:01,434 INFO L272 TraceCheckUtils]: 0: Hoare triple {529#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {540#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 17:25:01,434 INFO L290 TraceCheckUtils]: 1: Hoare triple {540#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {529#true} is VALID [2022-04-07 17:25:01,434 INFO L290 TraceCheckUtils]: 2: Hoare triple {529#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {529#true} is VALID [2022-04-07 17:25:01,435 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {529#true} {529#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {529#true} is VALID [2022-04-07 17:25:01,435 INFO L272 TraceCheckUtils]: 4: Hoare triple {529#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {529#true} is VALID [2022-04-07 17:25:01,435 INFO L290 TraceCheckUtils]: 5: Hoare triple {529#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {534#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} is VALID [2022-04-07 17:25:01,454 INFO L290 TraceCheckUtils]: 6: Hoare triple {534#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} [83] L16-2-->L16-2: Formula: (let ((.cse0 (mod v_main_~x~0_4 4294967296))) (or (and (= |v_main_#t~post5_3| |v_main_#t~post5_1|) (= v_main_~x~0_4 v_main_~x~0_3) (= |v_main_#t~post6_3| |v_main_#t~post6_1|) (<= .cse0 0) (= v_main_~y~0_6 v_main_~y~0_5)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ v_main_~x~0_4 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)) (not (<= (+ v_main_~y~0_6 v_it_1 1) v_main_~y~0_5)))) (< v_main_~y~0_6 v_main_~y~0_5) (< 0 .cse0) (= v_main_~x~0_3 (+ v_main_~x~0_4 v_main_~y~0_6 (* (- 1) v_main_~y~0_5)))))) InVars {main_~y~0=v_main_~y~0_6, main_#t~post5=|v_main_#t~post5_3|, main_~x~0=v_main_~x~0_4, main_#t~post6=|v_main_#t~post6_3|} OutVars{main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_~x~0=v_main_~x~0_3, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] {535#(or (<= (+ (* (div main_~y~0 4294967296) 4294967296) (* 4294967296 (div main_~x~0 4294967296)) 1) (+ main_~y~0 main_~x~0)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} is VALID [2022-04-07 17:25:01,455 INFO L290 TraceCheckUtils]: 7: Hoare triple {535#(or (<= (+ (* (div main_~y~0 4294967296) 4294967296) (* 4294967296 (div main_~x~0 4294967296)) 1) (+ main_~y~0 main_~x~0)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {536#(or (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= (+ (* (div main_~y~0 4294967296) 4294967296) 1) main_~y~0))} is VALID [2022-04-07 17:25:01,456 INFO L290 TraceCheckUtils]: 8: Hoare triple {536#(or (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= (+ (* (div main_~y~0 4294967296) 4294967296) 1) main_~y~0))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {536#(or (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= (+ (* (div main_~y~0 4294967296) 4294967296) 1) main_~y~0))} is VALID [2022-04-07 17:25:01,459 INFO L290 TraceCheckUtils]: 9: Hoare triple {536#(or (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= (+ (* (div main_~y~0 4294967296) 4294967296) 1) main_~y~0))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {536#(or (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= (+ (* (div main_~y~0 4294967296) 4294967296) 1) main_~y~0))} is VALID [2022-04-07 17:25:01,459 INFO L290 TraceCheckUtils]: 10: Hoare triple {536#(or (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= (+ (* (div main_~y~0 4294967296) 4294967296) 1) main_~y~0))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {537#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is VALID [2022-04-07 17:25:01,463 INFO L290 TraceCheckUtils]: 11: Hoare triple {537#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {537#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is VALID [2022-04-07 17:25:01,464 INFO L272 TraceCheckUtils]: 12: Hoare triple {537#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {538#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-07 17:25:01,465 INFO L290 TraceCheckUtils]: 13: Hoare triple {538#(not (= |__VERIFIER_assert_#in~cond| 0))} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {539#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-07 17:25:01,465 INFO L290 TraceCheckUtils]: 14: Hoare triple {539#(not (= __VERIFIER_assert_~cond 0))} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {530#false} is VALID [2022-04-07 17:25:01,465 INFO L290 TraceCheckUtils]: 15: Hoare triple {530#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {530#false} is VALID [2022-04-07 17:25:01,465 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 17:25:01,465 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 17:25:01,466 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1231601128] [2022-04-07 17:25:01,466 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1231601128] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 17:25:01,466 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1041374244] [2022-04-07 17:25:01,466 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:25:01,466 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 17:25:01,466 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 17:25:01,467 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 17:25:01,468 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-04-07 17:25:01,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:25:01,510 INFO L263 TraceCheckSpWp]: Trace formula consists of 61 conjuncts, 13 conjunts are in the unsatisfiable core [2022-04-07 17:25:01,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:25:01,533 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 17:25:06,345 INFO L272 TraceCheckUtils]: 0: Hoare triple {529#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {529#true} is VALID [2022-04-07 17:25:06,345 INFO L290 TraceCheckUtils]: 1: Hoare triple {529#true} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {529#true} is VALID [2022-04-07 17:25:06,346 INFO L290 TraceCheckUtils]: 2: Hoare triple {529#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {529#true} is VALID [2022-04-07 17:25:06,346 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {529#true} {529#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {529#true} is VALID [2022-04-07 17:25:06,346 INFO L272 TraceCheckUtils]: 4: Hoare triple {529#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {529#true} is VALID [2022-04-07 17:25:06,346 INFO L290 TraceCheckUtils]: 5: Hoare triple {529#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {534#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} is VALID [2022-04-07 17:25:06,358 INFO L290 TraceCheckUtils]: 6: Hoare triple {534#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} [83] L16-2-->L16-2: Formula: (let ((.cse0 (mod v_main_~x~0_4 4294967296))) (or (and (= |v_main_#t~post5_3| |v_main_#t~post5_1|) (= v_main_~x~0_4 v_main_~x~0_3) (= |v_main_#t~post6_3| |v_main_#t~post6_1|) (<= .cse0 0) (= v_main_~y~0_6 v_main_~y~0_5)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ v_main_~x~0_4 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)) (not (<= (+ v_main_~y~0_6 v_it_1 1) v_main_~y~0_5)))) (< v_main_~y~0_6 v_main_~y~0_5) (< 0 .cse0) (= v_main_~x~0_3 (+ v_main_~x~0_4 v_main_~y~0_6 (* (- 1) v_main_~y~0_5)))))) InVars {main_~y~0=v_main_~y~0_6, main_#t~post5=|v_main_#t~post5_3|, main_~x~0=v_main_~x~0_4, main_#t~post6=|v_main_#t~post6_3|} OutVars{main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_~x~0=v_main_~x~0_3, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] {562#(or (and (= main_~x~0 (+ main_~n~0 (* (- 1) main_~y~0))) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)) (and (= main_~n~0 main_~x~0) (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)))} is VALID [2022-04-07 17:25:06,360 INFO L290 TraceCheckUtils]: 7: Hoare triple {562#(or (and (= main_~x~0 (+ main_~n~0 (* (- 1) main_~y~0))) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)) (and (= main_~n~0 main_~x~0) (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {566#(or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (<= (div (+ main_~y~0 (* (- 1) main_~n~0)) (- 4294967296)) (div (+ main_~n~0 (* (- 1) main_~y~0)) 4294967296)) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)))} is VALID [2022-04-07 17:25:06,362 INFO L290 TraceCheckUtils]: 8: Hoare triple {566#(or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (<= (div (+ main_~y~0 (* (- 1) main_~n~0)) (- 4294967296)) (div (+ main_~n~0 (* (- 1) main_~y~0)) 4294967296)) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {570#(and (= main_~z~0 main_~y~0) (or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (<= (div (+ main_~y~0 (* (- 1) main_~n~0)) (- 4294967296)) (div (+ main_~n~0 (* (- 1) main_~y~0)) 4294967296)) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0))))} is VALID [2022-04-07 17:25:06,370 INFO L290 TraceCheckUtils]: 9: Hoare triple {570#(and (= main_~z~0 main_~y~0) (or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (<= (div (+ main_~y~0 (* (- 1) main_~n~0)) (- 4294967296)) (div (+ main_~n~0 (* (- 1) main_~y~0)) 4294967296)) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0))))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {574#(and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0))} is VALID [2022-04-07 17:25:06,371 INFO L290 TraceCheckUtils]: 10: Hoare triple {574#(and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {574#(and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0))} is VALID [2022-04-07 17:25:06,371 INFO L290 TraceCheckUtils]: 11: Hoare triple {574#(and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {574#(and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0))} is VALID [2022-04-07 17:25:06,372 INFO L272 TraceCheckUtils]: 12: Hoare triple {574#(and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {584#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 17:25:06,373 INFO L290 TraceCheckUtils]: 13: Hoare triple {584#(<= 1 |__VERIFIER_assert_#in~cond|)} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {588#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 17:25:06,373 INFO L290 TraceCheckUtils]: 14: Hoare triple {588#(<= 1 __VERIFIER_assert_~cond)} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {530#false} is VALID [2022-04-07 17:25:06,374 INFO L290 TraceCheckUtils]: 15: Hoare triple {530#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {530#false} is VALID [2022-04-07 17:25:06,374 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 17:25:06,374 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-07 17:25:11,029 INFO L290 TraceCheckUtils]: 15: Hoare triple {530#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {530#false} is VALID [2022-04-07 17:25:11,029 INFO L290 TraceCheckUtils]: 14: Hoare triple {588#(<= 1 __VERIFIER_assert_~cond)} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {530#false} is VALID [2022-04-07 17:25:11,030 INFO L290 TraceCheckUtils]: 13: Hoare triple {584#(<= 1 |__VERIFIER_assert_#in~cond|)} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {588#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 17:25:11,031 INFO L272 TraceCheckUtils]: 12: Hoare triple {537#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {584#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 17:25:11,031 INFO L290 TraceCheckUtils]: 11: Hoare triple {537#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {537#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is VALID [2022-04-07 17:25:11,032 INFO L290 TraceCheckUtils]: 10: Hoare triple {536#(or (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= (+ (* (div main_~y~0 4294967296) 4294967296) 1) main_~y~0))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {537#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is VALID [2022-04-07 17:25:11,033 INFO L290 TraceCheckUtils]: 9: Hoare triple {613#(or (< 0 (mod main_~z~0 4294967296)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= (+ (* (div main_~y~0 4294967296) 4294967296) 1) main_~y~0))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {536#(or (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= (+ (* (div main_~y~0 4294967296) 4294967296) 1) main_~y~0))} is VALID [2022-04-07 17:25:11,033 INFO L290 TraceCheckUtils]: 8: Hoare triple {536#(or (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= (+ (* (div main_~y~0 4294967296) 4294967296) 1) main_~y~0))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {613#(or (< 0 (mod main_~z~0 4294967296)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= (+ (* (div main_~y~0 4294967296) 4294967296) 1) main_~y~0))} is VALID [2022-04-07 17:25:11,034 INFO L290 TraceCheckUtils]: 7: Hoare triple {535#(or (<= (+ (* (div main_~y~0 4294967296) 4294967296) (* 4294967296 (div main_~x~0 4294967296)) 1) (+ main_~y~0 main_~x~0)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {536#(or (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= (+ (* (div main_~y~0 4294967296) 4294967296) 1) main_~y~0))} is VALID [2022-04-07 17:25:13,059 WARN L290 TraceCheckUtils]: 6: Hoare triple {623#(or (forall ((aux_mod_v_main_~x~0_21_31 Int)) (or (> 0 aux_mod_v_main_~x~0_21_31) (and (or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_div_v_main_~x~0_21_31 Int) (aux_div_v_main_~y~0_23_31 Int)) (or (<= (+ (* aux_div_v_main_~y~0_23_31 4294967296) (* aux_div_v_main_~x~0_21_31 4294967296) 1) (+ main_~y~0 main_~x~0)) (< (+ main_~y~0 main_~x~0) (+ aux_mod_v_main_~x~0_21_31 (* aux_div_v_main_~y~0_23_31 4294967296) (* aux_div_v_main_~x~0_21_31 4294967296))) (exists ((v_it_1 Int)) (and (<= (+ aux_mod_v_main_~x~0_21_31 v_it_1 (* aux_div_v_main_~x~0_21_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~x~0 (* v_it_1 4294967295)) 4294967296))) (<= 1 v_it_1))) (not (< (+ aux_mod_v_main_~x~0_21_31 (* aux_div_v_main_~x~0_21_31 4294967296)) main_~x~0))))) (or (forall ((aux_div_v_main_~x~0_21_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_21_31 (* aux_div_v_main_~x~0_21_31 4294967296))))) (< 0 (mod main_~x~0 4294967296)) (forall ((aux_div_v_main_~y~0_23_31 Int)) (or (< main_~y~0 (* aux_div_v_main_~y~0_23_31 4294967296)) (<= (+ (* aux_div_v_main_~y~0_23_31 4294967296) 1) (+ aux_mod_v_main_~x~0_21_31 main_~y~0)))))) (>= aux_mod_v_main_~x~0_21_31 4294967296))) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} [83] L16-2-->L16-2: Formula: (let ((.cse0 (mod v_main_~x~0_4 4294967296))) (or (and (= |v_main_#t~post5_3| |v_main_#t~post5_1|) (= v_main_~x~0_4 v_main_~x~0_3) (= |v_main_#t~post6_3| |v_main_#t~post6_1|) (<= .cse0 0) (= v_main_~y~0_6 v_main_~y~0_5)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ v_main_~x~0_4 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)) (not (<= (+ v_main_~y~0_6 v_it_1 1) v_main_~y~0_5)))) (< v_main_~y~0_6 v_main_~y~0_5) (< 0 .cse0) (= v_main_~x~0_3 (+ v_main_~x~0_4 v_main_~y~0_6 (* (- 1) v_main_~y~0_5)))))) InVars {main_~y~0=v_main_~y~0_6, main_#t~post5=|v_main_#t~post5_3|, main_~x~0=v_main_~x~0_4, main_#t~post6=|v_main_#t~post6_3|} OutVars{main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_~x~0=v_main_~x~0_3, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] {535#(or (<= (+ (* (div main_~y~0 4294967296) 4294967296) (* 4294967296 (div main_~x~0 4294967296)) 1) (+ main_~y~0 main_~x~0)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} is UNKNOWN [2022-04-07 17:25:13,070 INFO L290 TraceCheckUtils]: 5: Hoare triple {529#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {623#(or (forall ((aux_mod_v_main_~x~0_21_31 Int)) (or (> 0 aux_mod_v_main_~x~0_21_31) (and (or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_div_v_main_~x~0_21_31 Int) (aux_div_v_main_~y~0_23_31 Int)) (or (<= (+ (* aux_div_v_main_~y~0_23_31 4294967296) (* aux_div_v_main_~x~0_21_31 4294967296) 1) (+ main_~y~0 main_~x~0)) (< (+ main_~y~0 main_~x~0) (+ aux_mod_v_main_~x~0_21_31 (* aux_div_v_main_~y~0_23_31 4294967296) (* aux_div_v_main_~x~0_21_31 4294967296))) (exists ((v_it_1 Int)) (and (<= (+ aux_mod_v_main_~x~0_21_31 v_it_1 (* aux_div_v_main_~x~0_21_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~x~0 (* v_it_1 4294967295)) 4294967296))) (<= 1 v_it_1))) (not (< (+ aux_mod_v_main_~x~0_21_31 (* aux_div_v_main_~x~0_21_31 4294967296)) main_~x~0))))) (or (forall ((aux_div_v_main_~x~0_21_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_21_31 (* aux_div_v_main_~x~0_21_31 4294967296))))) (< 0 (mod main_~x~0 4294967296)) (forall ((aux_div_v_main_~y~0_23_31 Int)) (or (< main_~y~0 (* aux_div_v_main_~y~0_23_31 4294967296)) (<= (+ (* aux_div_v_main_~y~0_23_31 4294967296) 1) (+ aux_mod_v_main_~x~0_21_31 main_~y~0)))))) (>= aux_mod_v_main_~x~0_21_31 4294967296))) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} is VALID [2022-04-07 17:25:13,070 INFO L272 TraceCheckUtils]: 4: Hoare triple {529#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {529#true} is VALID [2022-04-07 17:25:13,070 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {529#true} {529#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {529#true} is VALID [2022-04-07 17:25:13,070 INFO L290 TraceCheckUtils]: 2: Hoare triple {529#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {529#true} is VALID [2022-04-07 17:25:13,070 INFO L290 TraceCheckUtils]: 1: Hoare triple {529#true} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {529#true} is VALID [2022-04-07 17:25:13,071 INFO L272 TraceCheckUtils]: 0: Hoare triple {529#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {529#true} is VALID [2022-04-07 17:25:13,071 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 17:25:13,071 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1041374244] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-07 17:25:13,071 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-07 17:25:13,071 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9] total 17 [2022-04-07 17:25:13,071 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1382907290] [2022-04-07 17:25:13,071 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-07 17:25:13,072 INFO L78 Accepts]: Start accepts. Automaton has has 17 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 14 states have internal predecessors, (25), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 16 [2022-04-07 17:25:13,072 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 17:25:13,072 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 17 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 14 states have internal predecessors, (25), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:25:13,236 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 32 edges. 32 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 17:25:13,237 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 17 states [2022-04-07 17:25:13,237 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 17:25:13,237 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2022-04-07 17:25:13,237 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=212, Unknown=0, NotChecked=0, Total=272 [2022-04-07 17:25:13,237 INFO L87 Difference]: Start difference. First operand 22 states and 28 transitions. Second operand has 17 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 14 states have internal predecessors, (25), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:25:13,785 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:25:13,786 INFO L93 Difference]: Finished difference Result 36 states and 49 transitions. [2022-04-07 17:25:13,786 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2022-04-07 17:25:13,786 INFO L78 Accepts]: Start accepts. Automaton has has 17 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 14 states have internal predecessors, (25), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 16 [2022-04-07 17:25:13,786 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 17:25:13,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 14 states have internal predecessors, (25), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:25:13,787 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 45 transitions. [2022-04-07 17:25:13,787 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 14 states have internal predecessors, (25), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:25:13,788 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 45 transitions. [2022-04-07 17:25:13,788 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 16 states and 45 transitions. [2022-04-07 17:25:14,650 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 45 edges. 45 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 17:25:14,651 INFO L225 Difference]: With dead ends: 36 [2022-04-07 17:25:14,651 INFO L226 Difference]: Without dead ends: 32 [2022-04-07 17:25:14,652 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 21 SyntacticMatches, 6 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 147 ImplicationChecksByTransitivity, 6.7s TimeCoverageRelationStatistics Valid=139, Invalid=461, Unknown=0, NotChecked=0, Total=600 [2022-04-07 17:25:14,652 INFO L913 BasicCegarLoop]: 15 mSDtfsCounter, 35 mSDsluCounter, 54 mSDsCounter, 0 mSdLazyCounter, 68 mSolverCounterSat, 7 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 35 SdHoareTripleChecker+Valid, 69 SdHoareTripleChecker+Invalid, 155 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 7 IncrementalHoareTripleChecker+Valid, 68 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 80 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-07 17:25:14,652 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [35 Valid, 69 Invalid, 155 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [7 Valid, 68 Invalid, 0 Unknown, 80 Unchecked, 0.1s Time] [2022-04-07 17:25:14,653 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states. [2022-04-07 17:25:14,655 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 27. [2022-04-07 17:25:14,655 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 17:25:14,655 INFO L82 GeneralOperation]: Start isEquivalent. First operand 32 states. Second operand has 27 states, 22 states have (on average 1.5) internal successors, (33), 22 states have internal predecessors, (33), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:25:14,655 INFO L74 IsIncluded]: Start isIncluded. First operand 32 states. Second operand has 27 states, 22 states have (on average 1.5) internal successors, (33), 22 states have internal predecessors, (33), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:25:14,655 INFO L87 Difference]: Start difference. First operand 32 states. Second operand has 27 states, 22 states have (on average 1.5) internal successors, (33), 22 states have internal predecessors, (33), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:25:14,656 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:25:14,656 INFO L93 Difference]: Finished difference Result 32 states and 44 transitions. [2022-04-07 17:25:14,657 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 44 transitions. [2022-04-07 17:25:14,657 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:25:14,657 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:25:14,657 INFO L74 IsIncluded]: Start isIncluded. First operand has 27 states, 22 states have (on average 1.5) internal successors, (33), 22 states have internal predecessors, (33), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 32 states. [2022-04-07 17:25:14,657 INFO L87 Difference]: Start difference. First operand has 27 states, 22 states have (on average 1.5) internal successors, (33), 22 states have internal predecessors, (33), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 32 states. [2022-04-07 17:25:14,658 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:25:14,658 INFO L93 Difference]: Finished difference Result 32 states and 44 transitions. [2022-04-07 17:25:14,658 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 44 transitions. [2022-04-07 17:25:14,658 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:25:14,658 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:25:14,658 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 17:25:14,658 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 17:25:14,659 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 22 states have (on average 1.5) internal successors, (33), 22 states have internal predecessors, (33), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:25:14,659 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 37 transitions. [2022-04-07 17:25:14,659 INFO L78 Accepts]: Start accepts. Automaton has 27 states and 37 transitions. Word has length 16 [2022-04-07 17:25:14,659 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 17:25:14,659 INFO L478 AbstractCegarLoop]: Abstraction has 27 states and 37 transitions. [2022-04-07 17:25:14,660 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 17 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 14 states have internal predecessors, (25), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:25:14,660 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states and 37 transitions. [2022-04-07 17:25:14,660 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2022-04-07 17:25:14,660 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 17:25:14,660 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 17:25:14,679 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2022-04-07 17:25:14,863 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4,4 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 17:25:14,863 INFO L403 AbstractCegarLoop]: === Iteration 6 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 17:25:14,864 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 17:25:14,864 INFO L85 PathProgramCache]: Analyzing trace with hash -1930032162, now seen corresponding path program 1 times [2022-04-07 17:25:14,864 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 17:25:14,864 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1281576753] [2022-04-07 17:25:14,864 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:25:14,864 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 17:25:14,872 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_2.0))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-07 17:25:14,873 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.1))) (+ .cse0 main_~x~0_8 (* (- 4294967296) (div (+ .cse0 main_~x~0_8) 4294967296)))) 0)) [2022-04-07 17:25:14,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:25:14,897 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_2.3))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-07 17:25:14,918 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.4))) (+ .cse0 main_~x~0_8 (* (- 4294967296) (div (+ .cse0 main_~x~0_8) 4294967296)))) 0)) [2022-04-07 17:25:15,134 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 17:25:15,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:25:15,141 INFO L290 TraceCheckUtils]: 0: Hoare triple {801#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {788#true} is VALID [2022-04-07 17:25:15,141 INFO L290 TraceCheckUtils]: 1: Hoare triple {788#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {788#true} is VALID [2022-04-07 17:25:15,141 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {788#true} {788#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {788#true} is VALID [2022-04-07 17:25:15,141 INFO L272 TraceCheckUtils]: 0: Hoare triple {788#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {801#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 17:25:15,142 INFO L290 TraceCheckUtils]: 1: Hoare triple {801#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {788#true} is VALID [2022-04-07 17:25:15,142 INFO L290 TraceCheckUtils]: 2: Hoare triple {788#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {788#true} is VALID [2022-04-07 17:25:15,142 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {788#true} {788#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {788#true} is VALID [2022-04-07 17:25:15,142 INFO L272 TraceCheckUtils]: 4: Hoare triple {788#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {788#true} is VALID [2022-04-07 17:25:15,143 INFO L290 TraceCheckUtils]: 5: Hoare triple {788#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {793#(and (= main_~n~0 main_~x~0) (= main_~y~0 0))} is VALID [2022-04-07 17:25:15,143 INFO L290 TraceCheckUtils]: 6: Hoare triple {793#(and (= main_~n~0 main_~x~0) (= main_~y~0 0))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {794#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:25:15,144 INFO L290 TraceCheckUtils]: 7: Hoare triple {794#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {795#(and (= main_~z~0 0) (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:25:15,145 INFO L290 TraceCheckUtils]: 8: Hoare triple {795#(and (= main_~z~0 0) (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [87] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_7 4294967296))) (or (and (= v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_7 v_main_~z~0_6) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|) (<= .cse0 0)) (and (< v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_6 (+ (* (- 1) v_main_~x~0_8) v_main_~x~0_9 v_main_~z~0_7)) (forall ((v_it_2 Int)) (or (not (<= 1 v_it_2)) (not (<= (+ v_main_~x~0_9 v_it_2 1) v_main_~x~0_8)) (< 0 (mod (+ v_main_~z~0_7 (* v_it_2 4294967295)) 4294967296)))) (< 0 .cse0)))) InVars {main_~x~0=v_main_~x~0_9, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_8, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_6, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {796#(and (= main_~z~0 0) (<= (+ main_~z~0 main_~x~0) (* 4294967296 (div main_~x~0 4294967296))) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (= main_~y~0 0))} is VALID [2022-04-07 17:25:15,145 INFO L290 TraceCheckUtils]: 9: Hoare triple {796#(and (= main_~z~0 0) (<= (+ main_~z~0 main_~x~0) (* 4294967296 (div main_~x~0 4294967296))) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (= main_~y~0 0))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {797#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (= main_~y~0 0))} is VALID [2022-04-07 17:25:15,146 INFO L290 TraceCheckUtils]: 10: Hoare triple {797#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (= main_~y~0 0))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {797#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (= main_~y~0 0))} is VALID [2022-04-07 17:25:15,148 INFO L290 TraceCheckUtils]: 11: Hoare triple {797#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (= main_~y~0 0))} [93] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {798#(and (not (<= (+ (div main_~y~0 4294967296) 1) 0)) (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is VALID [2022-04-07 17:25:15,148 INFO L290 TraceCheckUtils]: 12: Hoare triple {798#(and (not (<= (+ (div main_~y~0 4294967296) 1) 0)) (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {798#(and (not (<= (+ (div main_~y~0 4294967296) 1) 0)) (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is VALID [2022-04-07 17:25:15,149 INFO L272 TraceCheckUtils]: 13: Hoare triple {798#(and (not (<= (+ (div main_~y~0 4294967296) 1) 0)) (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {799#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-07 17:25:15,150 INFO L290 TraceCheckUtils]: 14: Hoare triple {799#(not (= |__VERIFIER_assert_#in~cond| 0))} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {800#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-07 17:25:15,150 INFO L290 TraceCheckUtils]: 15: Hoare triple {800#(not (= __VERIFIER_assert_~cond 0))} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {789#false} is VALID [2022-04-07 17:25:15,150 INFO L290 TraceCheckUtils]: 16: Hoare triple {789#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {789#false} is VALID [2022-04-07 17:25:15,150 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 17:25:15,150 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 17:25:15,150 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1281576753] [2022-04-07 17:25:15,151 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1281576753] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 17:25:15,151 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [95850800] [2022-04-07 17:25:15,151 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:25:15,151 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 17:25:15,151 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 17:25:15,153 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 17:25:15,154 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2022-04-07 17:25:15,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:25:15,182 INFO L263 TraceCheckSpWp]: Trace formula consists of 62 conjuncts, 13 conjunts are in the unsatisfiable core [2022-04-07 17:25:15,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:25:15,193 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 17:25:15,591 INFO L272 TraceCheckUtils]: 0: Hoare triple {788#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {788#true} is VALID [2022-04-07 17:25:15,591 INFO L290 TraceCheckUtils]: 1: Hoare triple {788#true} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {788#true} is VALID [2022-04-07 17:25:15,591 INFO L290 TraceCheckUtils]: 2: Hoare triple {788#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {788#true} is VALID [2022-04-07 17:25:15,592 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {788#true} {788#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {788#true} is VALID [2022-04-07 17:25:15,592 INFO L272 TraceCheckUtils]: 4: Hoare triple {788#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {788#true} is VALID [2022-04-07 17:25:15,592 INFO L290 TraceCheckUtils]: 5: Hoare triple {788#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {793#(and (= main_~n~0 main_~x~0) (= main_~y~0 0))} is VALID [2022-04-07 17:25:15,593 INFO L290 TraceCheckUtils]: 6: Hoare triple {793#(and (= main_~n~0 main_~x~0) (= main_~y~0 0))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {794#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:25:15,593 INFO L290 TraceCheckUtils]: 7: Hoare triple {794#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {795#(and (= main_~z~0 0) (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:25:15,594 INFO L290 TraceCheckUtils]: 8: Hoare triple {795#(and (= main_~z~0 0) (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [87] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_7 4294967296))) (or (and (= v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_7 v_main_~z~0_6) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|) (<= .cse0 0)) (and (< v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_6 (+ (* (- 1) v_main_~x~0_8) v_main_~x~0_9 v_main_~z~0_7)) (forall ((v_it_2 Int)) (or (not (<= 1 v_it_2)) (not (<= (+ v_main_~x~0_9 v_it_2 1) v_main_~x~0_8)) (< 0 (mod (+ v_main_~z~0_7 (* v_it_2 4294967295)) 4294967296)))) (< 0 .cse0)))) InVars {main_~x~0=v_main_~x~0_9, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_8, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_6, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {794#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:25:15,595 INFO L290 TraceCheckUtils]: 9: Hoare triple {794#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {794#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:25:15,595 INFO L290 TraceCheckUtils]: 10: Hoare triple {794#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {794#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:25:15,596 INFO L290 TraceCheckUtils]: 11: Hoare triple {794#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [93] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {838#(and (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (= main_~y~0 0))} is VALID [2022-04-07 17:25:15,597 INFO L290 TraceCheckUtils]: 12: Hoare triple {838#(and (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (= main_~y~0 0))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {838#(and (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (= main_~y~0 0))} is VALID [2022-04-07 17:25:15,598 INFO L272 TraceCheckUtils]: 13: Hoare triple {838#(and (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (= main_~y~0 0))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {845#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 17:25:15,598 INFO L290 TraceCheckUtils]: 14: Hoare triple {845#(<= 1 |__VERIFIER_assert_#in~cond|)} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {849#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 17:25:15,598 INFO L290 TraceCheckUtils]: 15: Hoare triple {849#(<= 1 __VERIFIER_assert_~cond)} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {789#false} is VALID [2022-04-07 17:25:15,598 INFO L290 TraceCheckUtils]: 16: Hoare triple {789#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {789#false} is VALID [2022-04-07 17:25:15,599 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 17:25:15,599 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-07 17:25:48,157 INFO L290 TraceCheckUtils]: 16: Hoare triple {789#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {789#false} is VALID [2022-04-07 17:25:48,158 INFO L290 TraceCheckUtils]: 15: Hoare triple {849#(<= 1 __VERIFIER_assert_~cond)} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {789#false} is VALID [2022-04-07 17:25:48,158 INFO L290 TraceCheckUtils]: 14: Hoare triple {845#(<= 1 |__VERIFIER_assert_#in~cond|)} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {849#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 17:25:48,159 INFO L272 TraceCheckUtils]: 13: Hoare triple {865#(= (mod main_~n~0 4294967296) (mod main_~y~0 4294967296))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {845#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 17:25:48,160 INFO L290 TraceCheckUtils]: 12: Hoare triple {865#(= (mod main_~n~0 4294967296) (mod main_~y~0 4294967296))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {865#(= (mod main_~n~0 4294967296) (mod main_~y~0 4294967296))} is VALID [2022-04-07 17:25:50,179 WARN L290 TraceCheckUtils]: 11: Hoare triple {872#(forall ((aux_mod_v_main_~y~0_26_31 Int)) (or (= (mod main_~n~0 4294967296) aux_mod_v_main_~y~0_26_31) (> 0 aux_mod_v_main_~y~0_26_31) (and (or (< 0 (mod main_~x~0 4294967296)) (forall ((aux_div_v_main_~y~0_26_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31))))) (or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_div_v_main_~y~0_26_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31))) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))))))) (>= aux_mod_v_main_~y~0_26_31 4294967296)))} [93] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {865#(= (mod main_~n~0 4294967296) (mod main_~y~0 4294967296))} is UNKNOWN [2022-04-07 17:25:52,188 WARN L290 TraceCheckUtils]: 10: Hoare triple {876#(or (forall ((aux_mod_v_main_~y~0_26_31 Int)) (or (= (mod main_~n~0 4294967296) aux_mod_v_main_~y~0_26_31) (> 0 aux_mod_v_main_~y~0_26_31) (and (or (< 0 (mod main_~x~0 4294967296)) (forall ((aux_div_v_main_~y~0_26_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31))))) (or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_div_v_main_~y~0_26_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31))) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))))))) (>= aux_mod_v_main_~y~0_26_31 4294967296))) (< 0 (mod main_~y~0 4294967296)))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {872#(forall ((aux_mod_v_main_~y~0_26_31 Int)) (or (= (mod main_~n~0 4294967296) aux_mod_v_main_~y~0_26_31) (> 0 aux_mod_v_main_~y~0_26_31) (and (or (< 0 (mod main_~x~0 4294967296)) (forall ((aux_div_v_main_~y~0_26_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31))))) (or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_div_v_main_~y~0_26_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31))) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))))))) (>= aux_mod_v_main_~y~0_26_31 4294967296)))} is UNKNOWN [2022-04-07 17:25:54,196 WARN L290 TraceCheckUtils]: 9: Hoare triple {876#(or (forall ((aux_mod_v_main_~y~0_26_31 Int)) (or (= (mod main_~n~0 4294967296) aux_mod_v_main_~y~0_26_31) (> 0 aux_mod_v_main_~y~0_26_31) (and (or (< 0 (mod main_~x~0 4294967296)) (forall ((aux_div_v_main_~y~0_26_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31))))) (or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_div_v_main_~y~0_26_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31))) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))))))) (>= aux_mod_v_main_~y~0_26_31 4294967296))) (< 0 (mod main_~y~0 4294967296)))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {876#(or (forall ((aux_mod_v_main_~y~0_26_31 Int)) (or (= (mod main_~n~0 4294967296) aux_mod_v_main_~y~0_26_31) (> 0 aux_mod_v_main_~y~0_26_31) (and (or (< 0 (mod main_~x~0 4294967296)) (forall ((aux_div_v_main_~y~0_26_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31))))) (or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_div_v_main_~y~0_26_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31))) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))))))) (>= aux_mod_v_main_~y~0_26_31 4294967296))) (< 0 (mod main_~y~0 4294967296)))} is UNKNOWN [2022-04-07 17:25:56,206 WARN L290 TraceCheckUtils]: 8: Hoare triple {883#(or (forall ((aux_mod_v_main_~y~0_26_31 Int)) (or (= (mod main_~n~0 4294967296) aux_mod_v_main_~y~0_26_31) (> 0 aux_mod_v_main_~y~0_26_31) (and (or (< 0 (mod main_~z~0 4294967296)) (and (or (< 0 (mod main_~x~0 4294967296)) (forall ((aux_div_v_main_~y~0_26_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31))))) (or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_div_v_main_~y~0_26_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31))) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4)))))))) (or (not (< 0 (mod main_~z~0 4294967296))) (and (forall ((aux_mod_v_main_~x~0_26_31 Int) (aux_div_v_main_~x~0_26_31 Int) (aux_div_v_main_~y~0_26_31 Int)) (or (<= (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31) main_~y~0) (<= aux_mod_v_main_~x~0_26_31 0) (<= (+ aux_mod_v_main_~x~0_26_31 (* aux_div_v_main_~x~0_26_31 4294967296)) main_~x~0) (exists ((v_it_2 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_2 4294967295)) 4294967296))) (<= (+ v_it_2 main_~x~0 1) (+ aux_mod_v_main_~x~0_26_31 (* aux_div_v_main_~x~0_26_31 4294967296))) (<= 1 v_it_2))) (<= 4294967296 aux_mod_v_main_~x~0_26_31) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31)) (<= 1 v_it_4) (not (< 0 (mod (+ (* v_it_4 4294967295) aux_mod_v_main_~x~0_26_31) 4294967296))))))) (or (forall ((aux_mod_v_main_~x~0_26_31 Int) (aux_div_v_main_~x~0_26_31 Int)) (or (<= (+ aux_mod_v_main_~x~0_26_31 (* aux_div_v_main_~x~0_26_31 4294967296)) main_~x~0) (exists ((v_it_2 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_2 4294967295)) 4294967296))) (<= (+ v_it_2 main_~x~0 1) (+ aux_mod_v_main_~x~0_26_31 (* aux_div_v_main_~x~0_26_31 4294967296))) (<= 1 v_it_2))) (< 0 aux_mod_v_main_~x~0_26_31) (< aux_mod_v_main_~x~0_26_31 0))) (forall ((aux_div_v_main_~y~0_26_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31)))))))) (>= aux_mod_v_main_~y~0_26_31 4294967296))) (< 0 (mod main_~y~0 4294967296)))} [87] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_7 4294967296))) (or (and (= v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_7 v_main_~z~0_6) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|) (<= .cse0 0)) (and (< v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_6 (+ (* (- 1) v_main_~x~0_8) v_main_~x~0_9 v_main_~z~0_7)) (forall ((v_it_2 Int)) (or (not (<= 1 v_it_2)) (not (<= (+ v_main_~x~0_9 v_it_2 1) v_main_~x~0_8)) (< 0 (mod (+ v_main_~z~0_7 (* v_it_2 4294967295)) 4294967296)))) (< 0 .cse0)))) InVars {main_~x~0=v_main_~x~0_9, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_8, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_6, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {876#(or (forall ((aux_mod_v_main_~y~0_26_31 Int)) (or (= (mod main_~n~0 4294967296) aux_mod_v_main_~y~0_26_31) (> 0 aux_mod_v_main_~y~0_26_31) (and (or (< 0 (mod main_~x~0 4294967296)) (forall ((aux_div_v_main_~y~0_26_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31))))) (or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_div_v_main_~y~0_26_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31))) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))))))) (>= aux_mod_v_main_~y~0_26_31 4294967296))) (< 0 (mod main_~y~0 4294967296)))} is UNKNOWN [2022-04-07 17:25:58,233 WARN L290 TraceCheckUtils]: 7: Hoare triple {876#(or (forall ((aux_mod_v_main_~y~0_26_31 Int)) (or (= (mod main_~n~0 4294967296) aux_mod_v_main_~y~0_26_31) (> 0 aux_mod_v_main_~y~0_26_31) (and (or (< 0 (mod main_~x~0 4294967296)) (forall ((aux_div_v_main_~y~0_26_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31))))) (or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_div_v_main_~y~0_26_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31))) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))))))) (>= aux_mod_v_main_~y~0_26_31 4294967296))) (< 0 (mod main_~y~0 4294967296)))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {883#(or (forall ((aux_mod_v_main_~y~0_26_31 Int)) (or (= (mod main_~n~0 4294967296) aux_mod_v_main_~y~0_26_31) (> 0 aux_mod_v_main_~y~0_26_31) (and (or (< 0 (mod main_~z~0 4294967296)) (and (or (< 0 (mod main_~x~0 4294967296)) (forall ((aux_div_v_main_~y~0_26_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31))))) (or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_div_v_main_~y~0_26_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31))) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4)))))))) (or (not (< 0 (mod main_~z~0 4294967296))) (and (forall ((aux_mod_v_main_~x~0_26_31 Int) (aux_div_v_main_~x~0_26_31 Int) (aux_div_v_main_~y~0_26_31 Int)) (or (<= (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31) main_~y~0) (<= aux_mod_v_main_~x~0_26_31 0) (<= (+ aux_mod_v_main_~x~0_26_31 (* aux_div_v_main_~x~0_26_31 4294967296)) main_~x~0) (exists ((v_it_2 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_2 4294967295)) 4294967296))) (<= (+ v_it_2 main_~x~0 1) (+ aux_mod_v_main_~x~0_26_31 (* aux_div_v_main_~x~0_26_31 4294967296))) (<= 1 v_it_2))) (<= 4294967296 aux_mod_v_main_~x~0_26_31) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31)) (<= 1 v_it_4) (not (< 0 (mod (+ (* v_it_4 4294967295) aux_mod_v_main_~x~0_26_31) 4294967296))))))) (or (forall ((aux_mod_v_main_~x~0_26_31 Int) (aux_div_v_main_~x~0_26_31 Int)) (or (<= (+ aux_mod_v_main_~x~0_26_31 (* aux_div_v_main_~x~0_26_31 4294967296)) main_~x~0) (exists ((v_it_2 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_2 4294967295)) 4294967296))) (<= (+ v_it_2 main_~x~0 1) (+ aux_mod_v_main_~x~0_26_31 (* aux_div_v_main_~x~0_26_31 4294967296))) (<= 1 v_it_2))) (< 0 aux_mod_v_main_~x~0_26_31) (< aux_mod_v_main_~x~0_26_31 0))) (forall ((aux_div_v_main_~y~0_26_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31)))))))) (>= aux_mod_v_main_~y~0_26_31 4294967296))) (< 0 (mod main_~y~0 4294967296)))} is UNKNOWN [2022-04-07 17:25:58,236 INFO L290 TraceCheckUtils]: 6: Hoare triple {890#(or (< 0 (mod main_~x~0 4294967296)) (<= (div (+ (- 1) (* (- 1) main_~y~0)) (- 4294967296)) (+ (div (+ main_~y~0 (* (- 1) (mod main_~n~0 4294967296))) 4294967296) 1)) (< 0 (mod main_~y~0 4294967296)))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {876#(or (forall ((aux_mod_v_main_~y~0_26_31 Int)) (or (= (mod main_~n~0 4294967296) aux_mod_v_main_~y~0_26_31) (> 0 aux_mod_v_main_~y~0_26_31) (and (or (< 0 (mod main_~x~0 4294967296)) (forall ((aux_div_v_main_~y~0_26_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31))))) (or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_div_v_main_~y~0_26_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31))) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))))))) (>= aux_mod_v_main_~y~0_26_31 4294967296))) (< 0 (mod main_~y~0 4294967296)))} is VALID [2022-04-07 17:25:58,237 INFO L290 TraceCheckUtils]: 5: Hoare triple {788#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {890#(or (< 0 (mod main_~x~0 4294967296)) (<= (div (+ (- 1) (* (- 1) main_~y~0)) (- 4294967296)) (+ (div (+ main_~y~0 (* (- 1) (mod main_~n~0 4294967296))) 4294967296) 1)) (< 0 (mod main_~y~0 4294967296)))} is VALID [2022-04-07 17:25:58,237 INFO L272 TraceCheckUtils]: 4: Hoare triple {788#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {788#true} is VALID [2022-04-07 17:25:58,237 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {788#true} {788#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {788#true} is VALID [2022-04-07 17:25:58,237 INFO L290 TraceCheckUtils]: 2: Hoare triple {788#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {788#true} is VALID [2022-04-07 17:25:58,237 INFO L290 TraceCheckUtils]: 1: Hoare triple {788#true} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {788#true} is VALID [2022-04-07 17:25:58,237 INFO L272 TraceCheckUtils]: 0: Hoare triple {788#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {788#true} is VALID [2022-04-07 17:25:58,237 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 1 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 17:25:58,238 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [95850800] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-07 17:25:58,238 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-07 17:25:58,238 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 8, 9] total 19 [2022-04-07 17:25:58,238 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2144713649] [2022-04-07 17:25:58,238 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-07 17:25:58,238 INFO L78 Accepts]: Start accepts. Automaton has has 19 states, 19 states have (on average 1.5263157894736843) internal successors, (29), 16 states have internal predecessors, (29), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-07 17:25:58,239 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 17:25:58,239 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 19 states, 19 states have (on average 1.5263157894736843) internal successors, (29), 16 states have internal predecessors, (29), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:26:06,974 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 36 edges. 32 inductive. 0 not inductive. 4 times theorem prover too weak to decide inductivity. [2022-04-07 17:26:06,975 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 19 states [2022-04-07 17:26:06,975 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 17:26:06,977 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2022-04-07 17:26:06,978 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=80, Invalid=250, Unknown=12, NotChecked=0, Total=342 [2022-04-07 17:26:06,978 INFO L87 Difference]: Start difference. First operand 27 states and 37 transitions. Second operand has 19 states, 19 states have (on average 1.5263157894736843) internal successors, (29), 16 states have internal predecessors, (29), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:26:17,523 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:26:17,524 INFO L93 Difference]: Finished difference Result 36 states and 50 transitions. [2022-04-07 17:26:17,524 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-04-07 17:26:17,524 INFO L78 Accepts]: Start accepts. Automaton has has 19 states, 19 states have (on average 1.5263157894736843) internal successors, (29), 16 states have internal predecessors, (29), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-07 17:26:17,524 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 17:26:17,524 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19 states, 19 states have (on average 1.5263157894736843) internal successors, (29), 16 states have internal predecessors, (29), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:26:17,525 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 39 transitions. [2022-04-07 17:26:17,525 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19 states, 19 states have (on average 1.5263157894736843) internal successors, (29), 16 states have internal predecessors, (29), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:26:17,526 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 39 transitions. [2022-04-07 17:26:17,526 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 11 states and 39 transitions. [2022-04-07 17:26:17,572 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 39 edges. 39 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 17:26:17,572 INFO L225 Difference]: With dead ends: 36 [2022-04-07 17:26:17,572 INFO L226 Difference]: Without dead ends: 33 [2022-04-07 17:26:17,573 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 24 SyntacticMatches, 5 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 127 ImplicationChecksByTransitivity, 31.4s TimeCoverageRelationStatistics Valid=137, Invalid=448, Unknown=15, NotChecked=0, Total=600 [2022-04-07 17:26:17,573 INFO L913 BasicCegarLoop]: 12 mSDtfsCounter, 20 mSDsluCounter, 56 mSDsCounter, 0 mSdLazyCounter, 81 mSolverCounterSat, 13 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 20 SdHoareTripleChecker+Valid, 68 SdHoareTripleChecker+Invalid, 124 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 13 IncrementalHoareTripleChecker+Valid, 81 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 30 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-07 17:26:17,573 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [20 Valid, 68 Invalid, 124 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [13 Valid, 81 Invalid, 0 Unknown, 30 Unchecked, 0.1s Time] [2022-04-07 17:26:17,574 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33 states. [2022-04-07 17:26:17,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33 to 29. [2022-04-07 17:26:17,575 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 17:26:17,575 INFO L82 GeneralOperation]: Start isEquivalent. First operand 33 states. Second operand has 29 states, 24 states have (on average 1.5) internal successors, (36), 24 states have internal predecessors, (36), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:26:17,576 INFO L74 IsIncluded]: Start isIncluded. First operand 33 states. Second operand has 29 states, 24 states have (on average 1.5) internal successors, (36), 24 states have internal predecessors, (36), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:26:17,576 INFO L87 Difference]: Start difference. First operand 33 states. Second operand has 29 states, 24 states have (on average 1.5) internal successors, (36), 24 states have internal predecessors, (36), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:26:17,577 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:26:17,577 INFO L93 Difference]: Finished difference Result 33 states and 47 transitions. [2022-04-07 17:26:17,577 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 47 transitions. [2022-04-07 17:26:17,577 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:26:17,577 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:26:17,577 INFO L74 IsIncluded]: Start isIncluded. First operand has 29 states, 24 states have (on average 1.5) internal successors, (36), 24 states have internal predecessors, (36), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 33 states. [2022-04-07 17:26:17,577 INFO L87 Difference]: Start difference. First operand has 29 states, 24 states have (on average 1.5) internal successors, (36), 24 states have internal predecessors, (36), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 33 states. [2022-04-07 17:26:17,578 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:26:17,578 INFO L93 Difference]: Finished difference Result 33 states and 47 transitions. [2022-04-07 17:26:17,578 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 47 transitions. [2022-04-07 17:26:17,578 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:26:17,578 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:26:17,579 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 17:26:17,579 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 17:26:17,579 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29 states, 24 states have (on average 1.5) internal successors, (36), 24 states have internal predecessors, (36), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:26:17,579 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 40 transitions. [2022-04-07 17:26:17,579 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 40 transitions. Word has length 17 [2022-04-07 17:26:17,580 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 17:26:17,580 INFO L478 AbstractCegarLoop]: Abstraction has 29 states and 40 transitions. [2022-04-07 17:26:17,580 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 19 states, 19 states have (on average 1.5263157894736843) internal successors, (29), 16 states have internal predecessors, (29), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:26:17,580 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 40 transitions. [2022-04-07 17:26:17,580 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2022-04-07 17:26:17,580 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 17:26:17,580 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 17:26:17,599 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2022-04-07 17:26:17,787 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5,5 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 17:26:17,787 INFO L403 AbstractCegarLoop]: === Iteration 7 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 17:26:17,788 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 17:26:17,788 INFO L85 PathProgramCache]: Analyzing trace with hash 2088406878, now seen corresponding path program 1 times [2022-04-07 17:26:17,788 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 17:26:17,788 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2085754737] [2022-04-07 17:26:17,788 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:26:17,788 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 17:26:17,796 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_1.0))) (+ main_~x~0_5 .cse0 (* (- 4294967296) (div (+ main_~x~0_5 .cse0) 4294967296)))) 0)) [2022-04-07 17:26:17,797 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.1))) (+ .cse0 main_~x~0_6 (* (- 4294967296) (div (+ .cse0 main_~x~0_6) 4294967296)))) 0)) [2022-04-07 17:26:17,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:26:17,822 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_1.2))) (+ main_~x~0_5 .cse0 (* (- 4294967296) (div (+ main_~x~0_5 .cse0) 4294967296)))) 0)) [2022-04-07 17:26:17,831 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.3))) (+ .cse0 main_~x~0_6 (* (- 4294967296) (div (+ .cse0 main_~x~0_6) 4294967296)))) 0)) [2022-04-07 17:26:17,991 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 17:26:17,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:26:18,004 INFO L290 TraceCheckUtils]: 0: Hoare triple {1067#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1055#true} is VALID [2022-04-07 17:26:18,004 INFO L290 TraceCheckUtils]: 1: Hoare triple {1055#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1055#true} is VALID [2022-04-07 17:26:18,004 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1055#true} {1055#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1055#true} is VALID [2022-04-07 17:26:18,005 INFO L272 TraceCheckUtils]: 0: Hoare triple {1055#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1067#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 17:26:18,005 INFO L290 TraceCheckUtils]: 1: Hoare triple {1067#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1055#true} is VALID [2022-04-07 17:26:18,005 INFO L290 TraceCheckUtils]: 2: Hoare triple {1055#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1055#true} is VALID [2022-04-07 17:26:18,005 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1055#true} {1055#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1055#true} is VALID [2022-04-07 17:26:18,005 INFO L272 TraceCheckUtils]: 4: Hoare triple {1055#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1055#true} is VALID [2022-04-07 17:26:18,005 INFO L290 TraceCheckUtils]: 5: Hoare triple {1055#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1060#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} is VALID [2022-04-07 17:26:18,027 INFO L290 TraceCheckUtils]: 6: Hoare triple {1060#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} [83] L16-2-->L16-2: Formula: (let ((.cse0 (mod v_main_~x~0_4 4294967296))) (or (and (= |v_main_#t~post5_3| |v_main_#t~post5_1|) (= v_main_~x~0_4 v_main_~x~0_3) (= |v_main_#t~post6_3| |v_main_#t~post6_1|) (<= .cse0 0) (= v_main_~y~0_6 v_main_~y~0_5)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ v_main_~x~0_4 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)) (not (<= (+ v_main_~y~0_6 v_it_1 1) v_main_~y~0_5)))) (< v_main_~y~0_6 v_main_~y~0_5) (< 0 .cse0) (= v_main_~x~0_3 (+ v_main_~x~0_4 v_main_~y~0_6 (* (- 1) v_main_~y~0_5)))))) InVars {main_~y~0=v_main_~y~0_6, main_#t~post5=|v_main_#t~post5_3|, main_~x~0=v_main_~x~0_4, main_#t~post6=|v_main_#t~post6_3|} OutVars{main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_~x~0=v_main_~x~0_3, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] {1061#(or (<= (+ (* (div main_~y~0 4294967296) 4294967296) (* 4294967296 (div main_~x~0 4294967296)) 1) (+ main_~y~0 main_~x~0)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} is VALID [2022-04-07 17:26:18,028 INFO L290 TraceCheckUtils]: 7: Hoare triple {1061#(or (<= (+ (* (div main_~y~0 4294967296) 4294967296) (* 4294967296 (div main_~x~0 4294967296)) 1) (+ main_~y~0 main_~x~0)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1062#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (or (<= (+ (* (div main_~y~0 4294967296) 4294967296) (* 4294967296 (div main_~x~0 4294967296)) 1) (+ main_~y~0 main_~x~0)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))))} is VALID [2022-04-07 17:26:18,029 INFO L290 TraceCheckUtils]: 8: Hoare triple {1062#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (or (<= (+ (* (div main_~y~0 4294967296) 4294967296) (* 4294967296 (div main_~x~0 4294967296)) 1) (+ main_~y~0 main_~x~0)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1062#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (or (<= (+ (* (div main_~y~0 4294967296) 4294967296) (* 4294967296 (div main_~x~0 4294967296)) 1) (+ main_~y~0 main_~x~0)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))))} is VALID [2022-04-07 17:26:18,029 INFO L290 TraceCheckUtils]: 9: Hoare triple {1062#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (or (<= (+ (* (div main_~y~0 4294967296) 4294967296) (* 4294967296 (div main_~x~0 4294967296)) 1) (+ main_~y~0 main_~x~0)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1062#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (or (<= (+ (* (div main_~y~0 4294967296) 4294967296) (* 4294967296 (div main_~x~0 4294967296)) 1) (+ main_~y~0 main_~x~0)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))))} is VALID [2022-04-07 17:26:18,030 INFO L290 TraceCheckUtils]: 10: Hoare triple {1062#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (or (<= (+ (* (div main_~y~0 4294967296) 4294967296) (* 4294967296 (div main_~x~0 4294967296)) 1) (+ main_~y~0 main_~x~0)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1063#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} is VALID [2022-04-07 17:26:18,032 INFO L290 TraceCheckUtils]: 11: Hoare triple {1063#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} [93] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1064#(and (not (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0))) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is VALID [2022-04-07 17:26:18,032 INFO L290 TraceCheckUtils]: 12: Hoare triple {1064#(and (not (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0))) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1064#(and (not (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0))) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is VALID [2022-04-07 17:26:18,033 INFO L272 TraceCheckUtils]: 13: Hoare triple {1064#(and (not (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0))) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {1065#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-07 17:26:18,035 INFO L290 TraceCheckUtils]: 14: Hoare triple {1065#(not (= |__VERIFIER_assert_#in~cond| 0))} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1066#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-07 17:26:18,035 INFO L290 TraceCheckUtils]: 15: Hoare triple {1066#(not (= __VERIFIER_assert_~cond 0))} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1056#false} is VALID [2022-04-07 17:26:18,035 INFO L290 TraceCheckUtils]: 16: Hoare triple {1056#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1056#false} is VALID [2022-04-07 17:26:18,035 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 17:26:18,036 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 17:26:18,036 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2085754737] [2022-04-07 17:26:18,036 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2085754737] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 17:26:18,036 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [87742264] [2022-04-07 17:26:18,036 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:26:18,036 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 17:26:18,036 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 17:26:18,037 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 17:26:18,038 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2022-04-07 17:26:18,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:26:18,178 INFO L263 TraceCheckSpWp]: Trace formula consists of 62 conjuncts, 11 conjunts are in the unsatisfiable core [2022-04-07 17:26:18,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:26:18,195 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 17:26:19,033 INFO L272 TraceCheckUtils]: 0: Hoare triple {1055#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1055#true} is VALID [2022-04-07 17:26:19,033 INFO L290 TraceCheckUtils]: 1: Hoare triple {1055#true} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1055#true} is VALID [2022-04-07 17:26:19,033 INFO L290 TraceCheckUtils]: 2: Hoare triple {1055#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1055#true} is VALID [2022-04-07 17:26:19,034 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1055#true} {1055#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1055#true} is VALID [2022-04-07 17:26:19,034 INFO L272 TraceCheckUtils]: 4: Hoare triple {1055#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1055#true} is VALID [2022-04-07 17:26:19,034 INFO L290 TraceCheckUtils]: 5: Hoare triple {1055#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1060#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} is VALID [2022-04-07 17:26:20,130 INFO L290 TraceCheckUtils]: 6: Hoare triple {1060#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} [83] L16-2-->L16-2: Formula: (let ((.cse0 (mod v_main_~x~0_4 4294967296))) (or (and (= |v_main_#t~post5_3| |v_main_#t~post5_1|) (= v_main_~x~0_4 v_main_~x~0_3) (= |v_main_#t~post6_3| |v_main_#t~post6_1|) (<= .cse0 0) (= v_main_~y~0_6 v_main_~y~0_5)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ v_main_~x~0_4 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)) (not (<= (+ v_main_~y~0_6 v_it_1 1) v_main_~y~0_5)))) (< v_main_~y~0_6 v_main_~y~0_5) (< 0 .cse0) (= v_main_~x~0_3 (+ v_main_~x~0_4 v_main_~y~0_6 (* (- 1) v_main_~y~0_5)))))) InVars {main_~y~0=v_main_~y~0_6, main_#t~post5=|v_main_#t~post5_3|, main_~x~0=v_main_~x~0_4, main_#t~post6=|v_main_#t~post6_3|} OutVars{main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_~x~0=v_main_~x~0_3, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] {1089#(or (and (= main_~x~0 (+ main_~n~0 (* (- 1) main_~y~0))) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)) (and (= main_~n~0 main_~x~0) (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)))} is VALID [2022-04-07 17:26:20,131 INFO L290 TraceCheckUtils]: 7: Hoare triple {1089#(or (and (= main_~x~0 (+ main_~n~0 (* (- 1) main_~y~0))) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)) (and (= main_~n~0 main_~x~0) (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1093#(and (not (< 0 (mod main_~x~0 4294967296))) (or (and (= main_~x~0 (+ main_~n~0 (* (- 1) main_~y~0))) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)) (and (= main_~n~0 main_~x~0) (= main_~y~0 0))))} is VALID [2022-04-07 17:26:20,133 INFO L290 TraceCheckUtils]: 8: Hoare triple {1093#(and (not (< 0 (mod main_~x~0 4294967296))) (or (and (= main_~x~0 (+ main_~n~0 (* (- 1) main_~y~0))) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)) (and (= main_~n~0 main_~x~0) (= main_~y~0 0))))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1093#(and (not (< 0 (mod main_~x~0 4294967296))) (or (and (= main_~x~0 (+ main_~n~0 (* (- 1) main_~y~0))) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)) (and (= main_~n~0 main_~x~0) (= main_~y~0 0))))} is VALID [2022-04-07 17:26:20,134 INFO L290 TraceCheckUtils]: 9: Hoare triple {1093#(and (not (< 0 (mod main_~x~0 4294967296))) (or (and (= main_~x~0 (+ main_~n~0 (* (- 1) main_~y~0))) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)) (and (= main_~n~0 main_~x~0) (= main_~y~0 0))))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1093#(and (not (< 0 (mod main_~x~0 4294967296))) (or (and (= main_~x~0 (+ main_~n~0 (* (- 1) main_~y~0))) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)) (and (= main_~n~0 main_~x~0) (= main_~y~0 0))))} is VALID [2022-04-07 17:26:20,140 INFO L290 TraceCheckUtils]: 10: Hoare triple {1093#(and (not (< 0 (mod main_~x~0 4294967296))) (or (and (= main_~x~0 (+ main_~n~0 (* (- 1) main_~y~0))) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)) (and (= main_~n~0 main_~x~0) (= main_~y~0 0))))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1103#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:26:20,140 INFO L290 TraceCheckUtils]: 11: Hoare triple {1103#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))) (= main_~y~0 0))} [93] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1107#(and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0))} is VALID [2022-04-07 17:26:20,141 INFO L290 TraceCheckUtils]: 12: Hoare triple {1107#(and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1107#(and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0))} is VALID [2022-04-07 17:26:20,141 INFO L272 TraceCheckUtils]: 13: Hoare triple {1107#(and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {1114#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 17:26:20,142 INFO L290 TraceCheckUtils]: 14: Hoare triple {1114#(<= 1 |__VERIFIER_assert_#in~cond|)} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1118#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 17:26:20,142 INFO L290 TraceCheckUtils]: 15: Hoare triple {1118#(<= 1 __VERIFIER_assert_~cond)} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1056#false} is VALID [2022-04-07 17:26:20,142 INFO L290 TraceCheckUtils]: 16: Hoare triple {1056#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1056#false} is VALID [2022-04-07 17:26:20,143 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 17:26:20,143 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-07 17:26:39,861 INFO L290 TraceCheckUtils]: 16: Hoare triple {1056#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1056#false} is VALID [2022-04-07 17:26:39,861 INFO L290 TraceCheckUtils]: 15: Hoare triple {1118#(<= 1 __VERIFIER_assert_~cond)} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1056#false} is VALID [2022-04-07 17:26:39,862 INFO L290 TraceCheckUtils]: 14: Hoare triple {1114#(<= 1 |__VERIFIER_assert_#in~cond|)} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1118#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 17:26:39,863 INFO L272 TraceCheckUtils]: 13: Hoare triple {1064#(and (not (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0))) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {1114#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 17:26:39,863 INFO L290 TraceCheckUtils]: 12: Hoare triple {1064#(and (not (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0))) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1064#(and (not (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0))) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is VALID [2022-04-07 17:26:40,644 INFO L290 TraceCheckUtils]: 11: Hoare triple {1140#(and (or (< 0 (mod main_~x~0 4294967296)) (and (not (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0))) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))) (or (and (forall ((aux_div_v_main_~y~0_30_31 Int) (aux_mod_v_main_~y~0_30_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31))) (< main_~n~0 (+ aux_mod_v_main_~y~0_30_31 (* (div main_~n~0 4294967296) 4294967296) 1)) (> 0 aux_mod_v_main_~y~0_30_31) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))))) (forall ((aux_div_v_main_~y~0_30_31 Int) (aux_mod_v_main_~y~0_30_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31))) (>= aux_mod_v_main_~y~0_30_31 4294967296) (<= (+ aux_mod_v_main_~y~0_30_31 (* (div main_~n~0 4294967296) 4294967296)) main_~n~0) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4)))))) (not (< 0 (mod main_~x~0 4294967296)))))} [93] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1064#(and (not (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0))) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is VALID [2022-04-07 17:26:42,663 WARN L290 TraceCheckUtils]: 10: Hoare triple {1144#(or (and (or (and (forall ((aux_div_v_main_~y~0_30_31 Int) (aux_mod_v_main_~y~0_30_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31))) (< main_~n~0 (+ aux_mod_v_main_~y~0_30_31 (* (div main_~n~0 4294967296) 4294967296) 1)) (> 0 aux_mod_v_main_~y~0_30_31) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))))) (forall ((aux_div_v_main_~y~0_30_31 Int) (aux_mod_v_main_~y~0_30_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31))) (>= aux_mod_v_main_~y~0_30_31 4294967296) (<= (+ aux_mod_v_main_~y~0_30_31 (* (div main_~n~0 4294967296) 4294967296)) main_~n~0) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4)))))) (not (< 0 (mod main_~x~0 4294967296)))) (or (not (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0))) (< 0 (mod main_~x~0 4294967296)))) (< 0 (mod main_~y~0 4294967296)))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1140#(and (or (< 0 (mod main_~x~0 4294967296)) (and (not (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0))) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))) (or (and (forall ((aux_div_v_main_~y~0_30_31 Int) (aux_mod_v_main_~y~0_30_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31))) (< main_~n~0 (+ aux_mod_v_main_~y~0_30_31 (* (div main_~n~0 4294967296) 4294967296) 1)) (> 0 aux_mod_v_main_~y~0_30_31) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))))) (forall ((aux_div_v_main_~y~0_30_31 Int) (aux_mod_v_main_~y~0_30_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31))) (>= aux_mod_v_main_~y~0_30_31 4294967296) (<= (+ aux_mod_v_main_~y~0_30_31 (* (div main_~n~0 4294967296) 4294967296)) main_~n~0) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4)))))) (not (< 0 (mod main_~x~0 4294967296)))))} is UNKNOWN [2022-04-07 17:26:44,673 WARN L290 TraceCheckUtils]: 9: Hoare triple {1144#(or (and (or (and (forall ((aux_div_v_main_~y~0_30_31 Int) (aux_mod_v_main_~y~0_30_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31))) (< main_~n~0 (+ aux_mod_v_main_~y~0_30_31 (* (div main_~n~0 4294967296) 4294967296) 1)) (> 0 aux_mod_v_main_~y~0_30_31) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))))) (forall ((aux_div_v_main_~y~0_30_31 Int) (aux_mod_v_main_~y~0_30_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31))) (>= aux_mod_v_main_~y~0_30_31 4294967296) (<= (+ aux_mod_v_main_~y~0_30_31 (* (div main_~n~0 4294967296) 4294967296)) main_~n~0) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4)))))) (not (< 0 (mod main_~x~0 4294967296)))) (or (not (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0))) (< 0 (mod main_~x~0 4294967296)))) (< 0 (mod main_~y~0 4294967296)))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1144#(or (and (or (and (forall ((aux_div_v_main_~y~0_30_31 Int) (aux_mod_v_main_~y~0_30_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31))) (< main_~n~0 (+ aux_mod_v_main_~y~0_30_31 (* (div main_~n~0 4294967296) 4294967296) 1)) (> 0 aux_mod_v_main_~y~0_30_31) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))))) (forall ((aux_div_v_main_~y~0_30_31 Int) (aux_mod_v_main_~y~0_30_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31))) (>= aux_mod_v_main_~y~0_30_31 4294967296) (<= (+ aux_mod_v_main_~y~0_30_31 (* (div main_~n~0 4294967296) 4294967296)) main_~n~0) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4)))))) (not (< 0 (mod main_~x~0 4294967296)))) (or (not (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0))) (< 0 (mod main_~x~0 4294967296)))) (< 0 (mod main_~y~0 4294967296)))} is UNKNOWN [2022-04-07 17:26:46,680 WARN L290 TraceCheckUtils]: 8: Hoare triple {1144#(or (and (or (and (forall ((aux_div_v_main_~y~0_30_31 Int) (aux_mod_v_main_~y~0_30_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31))) (< main_~n~0 (+ aux_mod_v_main_~y~0_30_31 (* (div main_~n~0 4294967296) 4294967296) 1)) (> 0 aux_mod_v_main_~y~0_30_31) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))))) (forall ((aux_div_v_main_~y~0_30_31 Int) (aux_mod_v_main_~y~0_30_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31))) (>= aux_mod_v_main_~y~0_30_31 4294967296) (<= (+ aux_mod_v_main_~y~0_30_31 (* (div main_~n~0 4294967296) 4294967296)) main_~n~0) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4)))))) (not (< 0 (mod main_~x~0 4294967296)))) (or (not (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0))) (< 0 (mod main_~x~0 4294967296)))) (< 0 (mod main_~y~0 4294967296)))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1144#(or (and (or (and (forall ((aux_div_v_main_~y~0_30_31 Int) (aux_mod_v_main_~y~0_30_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31))) (< main_~n~0 (+ aux_mod_v_main_~y~0_30_31 (* (div main_~n~0 4294967296) 4294967296) 1)) (> 0 aux_mod_v_main_~y~0_30_31) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))))) (forall ((aux_div_v_main_~y~0_30_31 Int) (aux_mod_v_main_~y~0_30_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31))) (>= aux_mod_v_main_~y~0_30_31 4294967296) (<= (+ aux_mod_v_main_~y~0_30_31 (* (div main_~n~0 4294967296) 4294967296)) main_~n~0) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4)))))) (not (< 0 (mod main_~x~0 4294967296)))) (or (not (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0))) (< 0 (mod main_~x~0 4294967296)))) (< 0 (mod main_~y~0 4294967296)))} is UNKNOWN [2022-04-07 17:26:46,682 INFO L290 TraceCheckUtils]: 7: Hoare triple {1061#(or (<= (+ (* (div main_~y~0 4294967296) 4294967296) (* 4294967296 (div main_~x~0 4294967296)) 1) (+ main_~y~0 main_~x~0)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1144#(or (and (or (and (forall ((aux_div_v_main_~y~0_30_31 Int) (aux_mod_v_main_~y~0_30_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31))) (< main_~n~0 (+ aux_mod_v_main_~y~0_30_31 (* (div main_~n~0 4294967296) 4294967296) 1)) (> 0 aux_mod_v_main_~y~0_30_31) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))))) (forall ((aux_div_v_main_~y~0_30_31 Int) (aux_mod_v_main_~y~0_30_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31))) (>= aux_mod_v_main_~y~0_30_31 4294967296) (<= (+ aux_mod_v_main_~y~0_30_31 (* (div main_~n~0 4294967296) 4294967296)) main_~n~0) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4)))))) (not (< 0 (mod main_~x~0 4294967296)))) (or (not (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0))) (< 0 (mod main_~x~0 4294967296)))) (< 0 (mod main_~y~0 4294967296)))} is VALID [2022-04-07 17:26:47,243 INFO L290 TraceCheckUtils]: 6: Hoare triple {1157#(or (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (forall ((aux_mod_v_main_~x~0_31_31 Int)) (or (> 0 aux_mod_v_main_~x~0_31_31) (and (or (forall ((aux_div_v_main_~y~0_31_31 Int) (aux_div_v_main_~x~0_31_31 Int)) (or (not (< (+ aux_mod_v_main_~x~0_31_31 (* aux_div_v_main_~x~0_31_31 4294967296)) main_~x~0)) (< (+ main_~y~0 main_~x~0) (+ aux_mod_v_main_~x~0_31_31 (* aux_div_v_main_~y~0_31_31 4294967296) (* aux_div_v_main_~x~0_31_31 4294967296))) (<= (+ (* aux_div_v_main_~y~0_31_31 4294967296) (* aux_div_v_main_~x~0_31_31 4294967296) 1) (+ main_~y~0 main_~x~0)) (exists ((v_it_1 Int)) (and (<= (+ aux_mod_v_main_~x~0_31_31 v_it_1 (* aux_div_v_main_~x~0_31_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~x~0 (* v_it_1 4294967295)) 4294967296))) (<= 1 v_it_1))))) (not (< 0 (mod main_~x~0 4294967296)))) (or (< 0 (mod main_~x~0 4294967296)) (forall ((aux_div_v_main_~x~0_31_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_31_31 (* aux_div_v_main_~x~0_31_31 4294967296))))) (forall ((aux_div_v_main_~y~0_31_31 Int)) (or (< main_~y~0 (* aux_div_v_main_~y~0_31_31 4294967296)) (<= (+ (* aux_div_v_main_~y~0_31_31 4294967296) 1) (+ aux_mod_v_main_~x~0_31_31 main_~y~0)))))) (>= aux_mod_v_main_~x~0_31_31 4294967296))))} [83] L16-2-->L16-2: Formula: (let ((.cse0 (mod v_main_~x~0_4 4294967296))) (or (and (= |v_main_#t~post5_3| |v_main_#t~post5_1|) (= v_main_~x~0_4 v_main_~x~0_3) (= |v_main_#t~post6_3| |v_main_#t~post6_1|) (<= .cse0 0) (= v_main_~y~0_6 v_main_~y~0_5)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ v_main_~x~0_4 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)) (not (<= (+ v_main_~y~0_6 v_it_1 1) v_main_~y~0_5)))) (< v_main_~y~0_6 v_main_~y~0_5) (< 0 .cse0) (= v_main_~x~0_3 (+ v_main_~x~0_4 v_main_~y~0_6 (* (- 1) v_main_~y~0_5)))))) InVars {main_~y~0=v_main_~y~0_6, main_#t~post5=|v_main_#t~post5_3|, main_~x~0=v_main_~x~0_4, main_#t~post6=|v_main_#t~post6_3|} OutVars{main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_~x~0=v_main_~x~0_3, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] {1061#(or (<= (+ (* (div main_~y~0 4294967296) 4294967296) (* 4294967296 (div main_~x~0 4294967296)) 1) (+ main_~y~0 main_~x~0)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} is VALID [2022-04-07 17:26:47,247 INFO L290 TraceCheckUtils]: 5: Hoare triple {1055#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1157#(or (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (forall ((aux_mod_v_main_~x~0_31_31 Int)) (or (> 0 aux_mod_v_main_~x~0_31_31) (and (or (forall ((aux_div_v_main_~y~0_31_31 Int) (aux_div_v_main_~x~0_31_31 Int)) (or (not (< (+ aux_mod_v_main_~x~0_31_31 (* aux_div_v_main_~x~0_31_31 4294967296)) main_~x~0)) (< (+ main_~y~0 main_~x~0) (+ aux_mod_v_main_~x~0_31_31 (* aux_div_v_main_~y~0_31_31 4294967296) (* aux_div_v_main_~x~0_31_31 4294967296))) (<= (+ (* aux_div_v_main_~y~0_31_31 4294967296) (* aux_div_v_main_~x~0_31_31 4294967296) 1) (+ main_~y~0 main_~x~0)) (exists ((v_it_1 Int)) (and (<= (+ aux_mod_v_main_~x~0_31_31 v_it_1 (* aux_div_v_main_~x~0_31_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~x~0 (* v_it_1 4294967295)) 4294967296))) (<= 1 v_it_1))))) (not (< 0 (mod main_~x~0 4294967296)))) (or (< 0 (mod main_~x~0 4294967296)) (forall ((aux_div_v_main_~x~0_31_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_31_31 (* aux_div_v_main_~x~0_31_31 4294967296))))) (forall ((aux_div_v_main_~y~0_31_31 Int)) (or (< main_~y~0 (* aux_div_v_main_~y~0_31_31 4294967296)) (<= (+ (* aux_div_v_main_~y~0_31_31 4294967296) 1) (+ aux_mod_v_main_~x~0_31_31 main_~y~0)))))) (>= aux_mod_v_main_~x~0_31_31 4294967296))))} is VALID [2022-04-07 17:26:47,247 INFO L272 TraceCheckUtils]: 4: Hoare triple {1055#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1055#true} is VALID [2022-04-07 17:26:47,248 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1055#true} {1055#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1055#true} is VALID [2022-04-07 17:26:47,248 INFO L290 TraceCheckUtils]: 2: Hoare triple {1055#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1055#true} is VALID [2022-04-07 17:26:47,248 INFO L290 TraceCheckUtils]: 1: Hoare triple {1055#true} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1055#true} is VALID [2022-04-07 17:26:47,248 INFO L272 TraceCheckUtils]: 0: Hoare triple {1055#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1055#true} is VALID [2022-04-07 17:26:47,248 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 17:26:47,248 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [87742264] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-07 17:26:47,248 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-07 17:26:47,248 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9, 9] total 19 [2022-04-07 17:26:47,249 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [370392013] [2022-04-07 17:26:47,249 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-07 17:26:47,249 INFO L78 Accepts]: Start accepts. Automaton has has 19 states, 19 states have (on average 1.5789473684210527) internal successors, (30), 16 states have internal predecessors, (30), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-07 17:26:47,249 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 17:26:47,249 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 19 states, 19 states have (on average 1.5789473684210527) internal successors, (30), 16 states have internal predecessors, (30), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:26:57,472 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 37 edges. 32 inductive. 0 not inductive. 5 times theorem prover too weak to decide inductivity. [2022-04-07 17:26:57,472 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 19 states [2022-04-07 17:26:57,472 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 17:26:57,472 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2022-04-07 17:26:57,473 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=77, Invalid=262, Unknown=3, NotChecked=0, Total=342 [2022-04-07 17:26:57,473 INFO L87 Difference]: Start difference. First operand 29 states and 40 transitions. Second operand has 19 states, 19 states have (on average 1.5789473684210527) internal successors, (30), 16 states have internal predecessors, (30), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:26:57,981 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:26:57,981 INFO L93 Difference]: Finished difference Result 37 states and 50 transitions. [2022-04-07 17:26:57,981 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-04-07 17:26:57,981 INFO L78 Accepts]: Start accepts. Automaton has has 19 states, 19 states have (on average 1.5789473684210527) internal successors, (30), 16 states have internal predecessors, (30), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-07 17:26:57,981 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 17:26:57,981 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19 states, 19 states have (on average 1.5789473684210527) internal successors, (30), 16 states have internal predecessors, (30), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:26:57,983 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 36 transitions. [2022-04-07 17:26:57,983 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19 states, 19 states have (on average 1.5789473684210527) internal successors, (30), 16 states have internal predecessors, (30), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:26:57,983 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 36 transitions. [2022-04-07 17:26:57,984 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 11 states and 36 transitions. [2022-04-07 17:26:58,027 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 36 edges. 36 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 17:26:58,028 INFO L225 Difference]: With dead ends: 37 [2022-04-07 17:26:58,028 INFO L226 Difference]: Without dead ends: 34 [2022-04-07 17:26:58,028 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 24 SyntacticMatches, 6 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 165 ImplicationChecksByTransitivity, 15.5s TimeCoverageRelationStatistics Valid=132, Invalid=465, Unknown=3, NotChecked=0, Total=600 [2022-04-07 17:26:58,031 INFO L913 BasicCegarLoop]: 15 mSDtfsCounter, 28 mSDsluCounter, 57 mSDsCounter, 0 mSdLazyCounter, 64 mSolverCounterSat, 6 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 28 SdHoareTripleChecker+Valid, 72 SdHoareTripleChecker+Invalid, 127 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 6 IncrementalHoareTripleChecker+Valid, 64 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 57 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-07 17:26:58,031 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [28 Valid, 72 Invalid, 127 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [6 Valid, 64 Invalid, 0 Unknown, 57 Unchecked, 0.1s Time] [2022-04-07 17:26:58,031 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states. [2022-04-07 17:26:58,033 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 32. [2022-04-07 17:26:58,033 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 17:26:58,033 INFO L82 GeneralOperation]: Start isEquivalent. First operand 34 states. Second operand has 32 states, 27 states have (on average 1.5185185185185186) internal successors, (41), 27 states have internal predecessors, (41), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:26:58,033 INFO L74 IsIncluded]: Start isIncluded. First operand 34 states. Second operand has 32 states, 27 states have (on average 1.5185185185185186) internal successors, (41), 27 states have internal predecessors, (41), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:26:58,033 INFO L87 Difference]: Start difference. First operand 34 states. Second operand has 32 states, 27 states have (on average 1.5185185185185186) internal successors, (41), 27 states have internal predecessors, (41), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:26:58,034 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:26:58,034 INFO L93 Difference]: Finished difference Result 34 states and 47 transitions. [2022-04-07 17:26:58,034 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 47 transitions. [2022-04-07 17:26:58,035 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:26:58,035 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:26:58,035 INFO L74 IsIncluded]: Start isIncluded. First operand has 32 states, 27 states have (on average 1.5185185185185186) internal successors, (41), 27 states have internal predecessors, (41), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 34 states. [2022-04-07 17:26:58,035 INFO L87 Difference]: Start difference. First operand has 32 states, 27 states have (on average 1.5185185185185186) internal successors, (41), 27 states have internal predecessors, (41), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 34 states. [2022-04-07 17:26:58,036 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:26:58,036 INFO L93 Difference]: Finished difference Result 34 states and 47 transitions. [2022-04-07 17:26:58,036 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 47 transitions. [2022-04-07 17:26:58,036 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:26:58,036 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:26:58,036 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 17:26:58,036 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 17:26:58,036 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32 states, 27 states have (on average 1.5185185185185186) internal successors, (41), 27 states have internal predecessors, (41), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:26:58,037 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 45 transitions. [2022-04-07 17:26:58,037 INFO L78 Accepts]: Start accepts. Automaton has 32 states and 45 transitions. Word has length 17 [2022-04-07 17:26:58,037 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 17:26:58,037 INFO L478 AbstractCegarLoop]: Abstraction has 32 states and 45 transitions. [2022-04-07 17:26:58,038 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 19 states, 19 states have (on average 1.5789473684210527) internal successors, (30), 16 states have internal predecessors, (30), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:26:58,038 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 45 transitions. [2022-04-07 17:26:58,038 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2022-04-07 17:26:58,038 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 17:26:58,038 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 17:26:58,057 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Forceful destruction successful, exit code 0 [2022-04-07 17:26:58,257 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6,6 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 17:26:58,257 INFO L403 AbstractCegarLoop]: === Iteration 8 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 17:26:58,258 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 17:26:58,258 INFO L85 PathProgramCache]: Analyzing trace with hash -1433573341, now seen corresponding path program 1 times [2022-04-07 17:26:58,258 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 17:26:58,258 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1403281347] [2022-04-07 17:26:58,258 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:26:58,258 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 17:26:58,266 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_1.0))) (+ main_~x~0_5 .cse0 (* (- 4294967296) (div (+ main_~x~0_5 .cse0) 4294967296)))) 0)) [2022-04-07 17:26:58,267 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.1))) (+ main_~y~0_6 .cse0 (* (- 4294967296) (div (+ main_~y~0_6 .cse0) 4294967296)))) 0)) [2022-04-07 17:26:58,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:26:58,293 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_1.2))) (+ main_~x~0_5 .cse0 (* (- 4294967296) (div (+ main_~x~0_5 .cse0) 4294967296)))) 0)) [2022-04-07 17:26:58,297 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.3))) (+ main_~y~0_6 .cse0 (* (- 4294967296) (div (+ main_~y~0_6 .cse0) 4294967296)))) 0)) [2022-04-07 17:26:58,520 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 17:26:58,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:26:58,529 INFO L290 TraceCheckUtils]: 0: Hoare triple {1344#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1330#true} is VALID [2022-04-07 17:26:58,529 INFO L290 TraceCheckUtils]: 1: Hoare triple {1330#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1330#true} is VALID [2022-04-07 17:26:58,530 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1330#true} {1330#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1330#true} is VALID [2022-04-07 17:26:58,530 INFO L272 TraceCheckUtils]: 0: Hoare triple {1330#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1344#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 17:26:58,530 INFO L290 TraceCheckUtils]: 1: Hoare triple {1344#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1330#true} is VALID [2022-04-07 17:26:58,530 INFO L290 TraceCheckUtils]: 2: Hoare triple {1330#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1330#true} is VALID [2022-04-07 17:26:58,530 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1330#true} {1330#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1330#true} is VALID [2022-04-07 17:26:58,530 INFO L272 TraceCheckUtils]: 4: Hoare triple {1330#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1330#true} is VALID [2022-04-07 17:26:58,531 INFO L290 TraceCheckUtils]: 5: Hoare triple {1330#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1335#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} is VALID [2022-04-07 17:26:58,538 INFO L290 TraceCheckUtils]: 6: Hoare triple {1335#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} [83] L16-2-->L16-2: Formula: (let ((.cse0 (mod v_main_~x~0_4 4294967296))) (or (and (= |v_main_#t~post5_3| |v_main_#t~post5_1|) (= v_main_~x~0_4 v_main_~x~0_3) (= |v_main_#t~post6_3| |v_main_#t~post6_1|) (<= .cse0 0) (= v_main_~y~0_6 v_main_~y~0_5)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ v_main_~x~0_4 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)) (not (<= (+ v_main_~y~0_6 v_it_1 1) v_main_~y~0_5)))) (< v_main_~y~0_6 v_main_~y~0_5) (< 0 .cse0) (= v_main_~x~0_3 (+ v_main_~x~0_4 v_main_~y~0_6 (* (- 1) v_main_~y~0_5)))))) InVars {main_~y~0=v_main_~y~0_6, main_#t~post5=|v_main_#t~post5_3|, main_~x~0=v_main_~x~0_4, main_#t~post6=|v_main_#t~post6_3|} OutVars{main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_~x~0=v_main_~x~0_3, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] {1336#(or (<= (+ (* (div main_~y~0 4294967296) 4294967296) (* 4294967296 (div main_~x~0 4294967296)) 1) (+ main_~y~0 main_~x~0)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} is VALID [2022-04-07 17:26:58,539 INFO L290 TraceCheckUtils]: 7: Hoare triple {1336#(or (<= (+ (* (div main_~y~0 4294967296) 4294967296) (* 4294967296 (div main_~x~0 4294967296)) 1) (+ main_~y~0 main_~x~0)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1337#(or (< (* (div main_~y~0 4294967296) 4294967296) main_~y~0) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} is VALID [2022-04-07 17:26:58,539 INFO L290 TraceCheckUtils]: 8: Hoare triple {1337#(or (< (* (div main_~y~0 4294967296) 4294967296) main_~y~0) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1338#(or (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (and (< (* (div main_~y~0 4294967296) 4294967296) main_~y~0) (= (+ main_~y~0 (* (- 1) main_~z~0)) 0)))} is VALID [2022-04-07 17:26:58,540 INFO L290 TraceCheckUtils]: 9: Hoare triple {1338#(or (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (and (< (* (div main_~y~0 4294967296) 4294967296) main_~y~0) (= (+ main_~y~0 (* (- 1) main_~z~0)) 0)))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1339#(<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))} is VALID [2022-04-07 17:26:58,541 INFO L290 TraceCheckUtils]: 10: Hoare triple {1339#(<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))} [90] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_4 4294967296))) (or (and (= (+ (* (- 1) v_main_~y~0_3) v_main_~y~0_4 v_main_~z~0_3) v_main_~z~0_2) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_4 (* v_it_3 4294967295)) 4294967296)) (not (<= (+ v_main_~y~0_3 v_it_3 1) v_main_~y~0_4)))) (< v_main_~y~0_3 v_main_~y~0_4)) (and (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= v_main_~y~0_4 v_main_~y~0_3) (<= .cse0 0) (= |v_main_#t~post9_3| |v_main_#t~post9_1|)))) InVars {main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_3, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {1340#(< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1))} is VALID [2022-04-07 17:26:58,541 INFO L290 TraceCheckUtils]: 11: Hoare triple {1340#(< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1341#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is VALID [2022-04-07 17:26:58,542 INFO L290 TraceCheckUtils]: 12: Hoare triple {1341#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1341#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is VALID [2022-04-07 17:26:58,543 INFO L272 TraceCheckUtils]: 13: Hoare triple {1341#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {1342#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-07 17:26:58,543 INFO L290 TraceCheckUtils]: 14: Hoare triple {1342#(not (= |__VERIFIER_assert_#in~cond| 0))} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1343#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-07 17:26:58,543 INFO L290 TraceCheckUtils]: 15: Hoare triple {1343#(not (= __VERIFIER_assert_~cond 0))} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1331#false} is VALID [2022-04-07 17:26:58,544 INFO L290 TraceCheckUtils]: 16: Hoare triple {1331#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1331#false} is VALID [2022-04-07 17:26:58,544 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 17:26:58,544 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 17:26:58,544 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1403281347] [2022-04-07 17:26:58,544 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1403281347] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 17:26:58,544 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1998148673] [2022-04-07 17:26:58,544 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:26:58,544 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 17:26:58,544 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 17:26:58,545 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 17:26:58,546 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2022-04-07 17:26:58,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:26:58,596 INFO L263 TraceCheckSpWp]: Trace formula consists of 62 conjuncts, 12 conjunts are in the unsatisfiable core [2022-04-07 17:26:58,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:26:58,610 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 17:26:59,944 INFO L272 TraceCheckUtils]: 0: Hoare triple {1330#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1330#true} is VALID [2022-04-07 17:26:59,944 INFO L290 TraceCheckUtils]: 1: Hoare triple {1330#true} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1330#true} is VALID [2022-04-07 17:26:59,944 INFO L290 TraceCheckUtils]: 2: Hoare triple {1330#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1330#true} is VALID [2022-04-07 17:26:59,945 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1330#true} {1330#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1330#true} is VALID [2022-04-07 17:26:59,945 INFO L272 TraceCheckUtils]: 4: Hoare triple {1330#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1330#true} is VALID [2022-04-07 17:26:59,945 INFO L290 TraceCheckUtils]: 5: Hoare triple {1330#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1335#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} is VALID [2022-04-07 17:26:59,960 INFO L290 TraceCheckUtils]: 6: Hoare triple {1335#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} [83] L16-2-->L16-2: Formula: (let ((.cse0 (mod v_main_~x~0_4 4294967296))) (or (and (= |v_main_#t~post5_3| |v_main_#t~post5_1|) (= v_main_~x~0_4 v_main_~x~0_3) (= |v_main_#t~post6_3| |v_main_#t~post6_1|) (<= .cse0 0) (= v_main_~y~0_6 v_main_~y~0_5)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ v_main_~x~0_4 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)) (not (<= (+ v_main_~y~0_6 v_it_1 1) v_main_~y~0_5)))) (< v_main_~y~0_6 v_main_~y~0_5) (< 0 .cse0) (= v_main_~x~0_3 (+ v_main_~x~0_4 v_main_~y~0_6 (* (- 1) v_main_~y~0_5)))))) InVars {main_~y~0=v_main_~y~0_6, main_#t~post5=|v_main_#t~post5_3|, main_~x~0=v_main_~x~0_4, main_#t~post6=|v_main_#t~post6_3|} OutVars{main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_~x~0=v_main_~x~0_3, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] {1366#(or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)))} is VALID [2022-04-07 17:26:59,961 INFO L290 TraceCheckUtils]: 7: Hoare triple {1366#(or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1366#(or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)))} is VALID [2022-04-07 17:26:59,962 INFO L290 TraceCheckUtils]: 8: Hoare triple {1366#(or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1373#(or (and (= main_~z~0 0) (<= (mod main_~n~0 4294967296) 0)) (and (< 0 main_~z~0) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~z~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296))))} is VALID [2022-04-07 17:26:59,967 INFO L290 TraceCheckUtils]: 9: Hoare triple {1373#(or (and (= main_~z~0 0) (<= (mod main_~n~0 4294967296) 0)) (and (< 0 main_~z~0) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~z~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296))))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1339#(<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))} is VALID [2022-04-07 17:26:59,968 INFO L290 TraceCheckUtils]: 10: Hoare triple {1339#(<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))} [90] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_4 4294967296))) (or (and (= (+ (* (- 1) v_main_~y~0_3) v_main_~y~0_4 v_main_~z~0_3) v_main_~z~0_2) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_4 (* v_it_3 4294967295)) 4294967296)) (not (<= (+ v_main_~y~0_3 v_it_3 1) v_main_~y~0_4)))) (< v_main_~y~0_3 v_main_~y~0_4)) (and (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= v_main_~y~0_4 v_main_~y~0_3) (<= .cse0 0) (= |v_main_#t~post9_3| |v_main_#t~post9_1|)))) InVars {main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_3, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {1339#(<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))} is VALID [2022-04-07 17:26:59,968 INFO L290 TraceCheckUtils]: 11: Hoare triple {1339#(<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1383#(and (not (< 0 (mod main_~y~0 4294967296))) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} is VALID [2022-04-07 17:26:59,968 INFO L290 TraceCheckUtils]: 12: Hoare triple {1383#(and (not (< 0 (mod main_~y~0 4294967296))) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1383#(and (not (< 0 (mod main_~y~0 4294967296))) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} is VALID [2022-04-07 17:26:59,969 INFO L272 TraceCheckUtils]: 13: Hoare triple {1383#(and (not (< 0 (mod main_~y~0 4294967296))) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {1390#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 17:26:59,970 INFO L290 TraceCheckUtils]: 14: Hoare triple {1390#(<= 1 |__VERIFIER_assert_#in~cond|)} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1394#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 17:26:59,970 INFO L290 TraceCheckUtils]: 15: Hoare triple {1394#(<= 1 __VERIFIER_assert_~cond)} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1331#false} is VALID [2022-04-07 17:26:59,970 INFO L290 TraceCheckUtils]: 16: Hoare triple {1331#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1331#false} is VALID [2022-04-07 17:26:59,970 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-07 17:26:59,970 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-07 17:27:01,222 INFO L290 TraceCheckUtils]: 16: Hoare triple {1331#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1331#false} is VALID [2022-04-07 17:27:01,223 INFO L290 TraceCheckUtils]: 15: Hoare triple {1394#(<= 1 __VERIFIER_assert_~cond)} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1331#false} is VALID [2022-04-07 17:27:01,223 INFO L290 TraceCheckUtils]: 14: Hoare triple {1390#(<= 1 |__VERIFIER_assert_#in~cond|)} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1394#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 17:27:01,224 INFO L272 TraceCheckUtils]: 13: Hoare triple {1341#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {1390#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 17:27:01,225 INFO L290 TraceCheckUtils]: 12: Hoare triple {1341#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1341#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is VALID [2022-04-07 17:27:01,225 INFO L290 TraceCheckUtils]: 11: Hoare triple {1339#(<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1341#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is VALID [2022-04-07 17:27:01,226 INFO L290 TraceCheckUtils]: 10: Hoare triple {1339#(<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))} [90] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_4 4294967296))) (or (and (= (+ (* (- 1) v_main_~y~0_3) v_main_~y~0_4 v_main_~z~0_3) v_main_~z~0_2) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_4 (* v_it_3 4294967295)) 4294967296)) (not (<= (+ v_main_~y~0_3 v_it_3 1) v_main_~y~0_4)))) (< v_main_~y~0_3 v_main_~y~0_4)) (and (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= v_main_~y~0_4 v_main_~y~0_3) (<= .cse0 0) (= |v_main_#t~post9_3| |v_main_#t~post9_1|)))) InVars {main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_3, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {1339#(<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))} is VALID [2022-04-07 17:27:01,226 INFO L290 TraceCheckUtils]: 9: Hoare triple {1422#(or (< 0 (mod main_~z~0 4294967296)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1339#(<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))} is VALID [2022-04-07 17:27:01,227 INFO L290 TraceCheckUtils]: 8: Hoare triple {1337#(or (< (* (div main_~y~0 4294967296) 4294967296) main_~y~0) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1422#(or (< 0 (mod main_~z~0 4294967296)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} is VALID [2022-04-07 17:27:01,227 INFO L290 TraceCheckUtils]: 7: Hoare triple {1337#(or (< (* (div main_~y~0 4294967296) 4294967296) main_~y~0) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1337#(or (< (* (div main_~y~0 4294967296) 4294967296) main_~y~0) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} is VALID [2022-04-07 17:27:01,296 INFO L290 TraceCheckUtils]: 6: Hoare triple {1432#(or (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (forall ((aux_mod_v_main_~y~0_35_31 Int)) (or (< aux_mod_v_main_~y~0_35_31 0) (and (or (forall ((aux_div_v_main_~y~0_35_31 Int)) (or (exists ((v_it_1 Int)) (and (not (< 0 (mod (+ main_~x~0 (* v_it_1 4294967295)) 4294967296))) (<= 1 v_it_1) (<= (+ v_it_1 main_~y~0 1) (+ aux_mod_v_main_~y~0_35_31 (* aux_div_v_main_~y~0_35_31 4294967296))))) (not (< main_~y~0 (+ aux_mod_v_main_~y~0_35_31 (* aux_div_v_main_~y~0_35_31 4294967296)))))) (not (< 0 (mod main_~x~0 4294967296)))) (or (< 0 (mod main_~x~0 4294967296)) (forall ((aux_div_v_main_~y~0_35_31 Int)) (not (= (+ aux_mod_v_main_~y~0_35_31 (* aux_div_v_main_~y~0_35_31 4294967296)) main_~y~0))))) (< 0 aux_mod_v_main_~y~0_35_31))))} [83] L16-2-->L16-2: Formula: (let ((.cse0 (mod v_main_~x~0_4 4294967296))) (or (and (= |v_main_#t~post5_3| |v_main_#t~post5_1|) (= v_main_~x~0_4 v_main_~x~0_3) (= |v_main_#t~post6_3| |v_main_#t~post6_1|) (<= .cse0 0) (= v_main_~y~0_6 v_main_~y~0_5)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ v_main_~x~0_4 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)) (not (<= (+ v_main_~y~0_6 v_it_1 1) v_main_~y~0_5)))) (< v_main_~y~0_6 v_main_~y~0_5) (< 0 .cse0) (= v_main_~x~0_3 (+ v_main_~x~0_4 v_main_~y~0_6 (* (- 1) v_main_~y~0_5)))))) InVars {main_~y~0=v_main_~y~0_6, main_#t~post5=|v_main_#t~post5_3|, main_~x~0=v_main_~x~0_4, main_#t~post6=|v_main_#t~post6_3|} OutVars{main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_~x~0=v_main_~x~0_3, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] {1337#(or (< (* (div main_~y~0 4294967296) 4294967296) main_~y~0) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} is VALID [2022-04-07 17:27:01,304 INFO L290 TraceCheckUtils]: 5: Hoare triple {1330#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1432#(or (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (forall ((aux_mod_v_main_~y~0_35_31 Int)) (or (< aux_mod_v_main_~y~0_35_31 0) (and (or (forall ((aux_div_v_main_~y~0_35_31 Int)) (or (exists ((v_it_1 Int)) (and (not (< 0 (mod (+ main_~x~0 (* v_it_1 4294967295)) 4294967296))) (<= 1 v_it_1) (<= (+ v_it_1 main_~y~0 1) (+ aux_mod_v_main_~y~0_35_31 (* aux_div_v_main_~y~0_35_31 4294967296))))) (not (< main_~y~0 (+ aux_mod_v_main_~y~0_35_31 (* aux_div_v_main_~y~0_35_31 4294967296)))))) (not (< 0 (mod main_~x~0 4294967296)))) (or (< 0 (mod main_~x~0 4294967296)) (forall ((aux_div_v_main_~y~0_35_31 Int)) (not (= (+ aux_mod_v_main_~y~0_35_31 (* aux_div_v_main_~y~0_35_31 4294967296)) main_~y~0))))) (< 0 aux_mod_v_main_~y~0_35_31))))} is VALID [2022-04-07 17:27:01,304 INFO L272 TraceCheckUtils]: 4: Hoare triple {1330#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1330#true} is VALID [2022-04-07 17:27:01,304 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1330#true} {1330#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1330#true} is VALID [2022-04-07 17:27:01,305 INFO L290 TraceCheckUtils]: 2: Hoare triple {1330#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1330#true} is VALID [2022-04-07 17:27:01,305 INFO L290 TraceCheckUtils]: 1: Hoare triple {1330#true} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1330#true} is VALID [2022-04-07 17:27:01,305 INFO L272 TraceCheckUtils]: 0: Hoare triple {1330#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1330#true} is VALID [2022-04-07 17:27:01,305 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-07 17:27:01,305 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1998148673] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-07 17:27:01,305 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-07 17:27:01,305 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 9, 9] total 19 [2022-04-07 17:27:01,305 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1820563799] [2022-04-07 17:27:01,305 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-07 17:27:01,307 INFO L78 Accepts]: Start accepts. Automaton has has 19 states, 19 states have (on average 1.5263157894736843) internal successors, (29), 16 states have internal predecessors, (29), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-07 17:27:01,307 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 17:27:01,307 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 19 states, 19 states have (on average 1.5263157894736843) internal successors, (29), 16 states have internal predecessors, (29), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:27:01,490 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 36 edges. 36 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 17:27:01,491 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 19 states [2022-04-07 17:27:01,491 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 17:27:01,491 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2022-04-07 17:27:01,491 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=276, Unknown=0, NotChecked=0, Total=342 [2022-04-07 17:27:01,492 INFO L87 Difference]: Start difference. First operand 32 states and 45 transitions. Second operand has 19 states, 19 states have (on average 1.5263157894736843) internal successors, (29), 16 states have internal predecessors, (29), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:27:02,266 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:27:02,267 INFO L93 Difference]: Finished difference Result 39 states and 54 transitions. [2022-04-07 17:27:02,267 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-04-07 17:27:02,267 INFO L78 Accepts]: Start accepts. Automaton has has 19 states, 19 states have (on average 1.5263157894736843) internal successors, (29), 16 states have internal predecessors, (29), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-07 17:27:02,267 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 17:27:02,267 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19 states, 19 states have (on average 1.5263157894736843) internal successors, (29), 16 states have internal predecessors, (29), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:27:02,268 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 37 transitions. [2022-04-07 17:27:02,268 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19 states, 19 states have (on average 1.5263157894736843) internal successors, (29), 16 states have internal predecessors, (29), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:27:02,269 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 37 transitions. [2022-04-07 17:27:02,269 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 12 states and 37 transitions. [2022-04-07 17:27:02,312 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 37 edges. 37 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 17:27:02,312 INFO L225 Difference]: With dead ends: 39 [2022-04-07 17:27:02,313 INFO L226 Difference]: Without dead ends: 36 [2022-04-07 17:27:02,313 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 55 GetRequests, 24 SyntacticMatches, 6 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 176 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=152, Invalid=550, Unknown=0, NotChecked=0, Total=702 [2022-04-07 17:27:02,313 INFO L913 BasicCegarLoop]: 18 mSDtfsCounter, 25 mSDsluCounter, 49 mSDsCounter, 0 mSdLazyCounter, 69 mSolverCounterSat, 8 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 25 SdHoareTripleChecker+Valid, 67 SdHoareTripleChecker+Invalid, 122 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 8 IncrementalHoareTripleChecker+Valid, 69 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 45 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-07 17:27:02,313 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [25 Valid, 67 Invalid, 122 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [8 Valid, 69 Invalid, 0 Unknown, 45 Unchecked, 0.1s Time] [2022-04-07 17:27:02,314 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2022-04-07 17:27:02,315 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 31. [2022-04-07 17:27:02,315 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 17:27:02,315 INFO L82 GeneralOperation]: Start isEquivalent. First operand 36 states. Second operand has 31 states, 26 states have (on average 1.5) internal successors, (39), 26 states have internal predecessors, (39), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:27:02,315 INFO L74 IsIncluded]: Start isIncluded. First operand 36 states. Second operand has 31 states, 26 states have (on average 1.5) internal successors, (39), 26 states have internal predecessors, (39), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:27:02,315 INFO L87 Difference]: Start difference. First operand 36 states. Second operand has 31 states, 26 states have (on average 1.5) internal successors, (39), 26 states have internal predecessors, (39), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:27:02,316 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:27:02,316 INFO L93 Difference]: Finished difference Result 36 states and 51 transitions. [2022-04-07 17:27:02,316 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 51 transitions. [2022-04-07 17:27:02,317 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:27:02,317 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:27:02,317 INFO L74 IsIncluded]: Start isIncluded. First operand has 31 states, 26 states have (on average 1.5) internal successors, (39), 26 states have internal predecessors, (39), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 36 states. [2022-04-07 17:27:02,317 INFO L87 Difference]: Start difference. First operand has 31 states, 26 states have (on average 1.5) internal successors, (39), 26 states have internal predecessors, (39), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 36 states. [2022-04-07 17:27:02,318 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:27:02,318 INFO L93 Difference]: Finished difference Result 36 states and 51 transitions. [2022-04-07 17:27:02,318 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 51 transitions. [2022-04-07 17:27:02,318 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:27:02,318 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:27:02,318 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 17:27:02,318 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 17:27:02,318 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31 states, 26 states have (on average 1.5) internal successors, (39), 26 states have internal predecessors, (39), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:27:02,319 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 43 transitions. [2022-04-07 17:27:02,319 INFO L78 Accepts]: Start accepts. Automaton has 31 states and 43 transitions. Word has length 17 [2022-04-07 17:27:02,319 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 17:27:02,319 INFO L478 AbstractCegarLoop]: Abstraction has 31 states and 43 transitions. [2022-04-07 17:27:02,319 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 19 states, 19 states have (on average 1.5263157894736843) internal successors, (29), 16 states have internal predecessors, (29), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:27:02,319 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states and 43 transitions. [2022-04-07 17:27:02,320 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2022-04-07 17:27:02,320 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 17:27:02,320 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 17:27:02,341 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Forceful destruction successful, exit code 0 [2022-04-07 17:27:02,535 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7,7 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 17:27:02,535 INFO L403 AbstractCegarLoop]: === Iteration 9 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 17:27:02,536 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 17:27:02,536 INFO L85 PathProgramCache]: Analyzing trace with hash 1054189566, now seen corresponding path program 1 times [2022-04-07 17:27:02,536 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 17:27:02,536 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1107819520] [2022-04-07 17:27:02,536 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:27:02,536 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 17:27:02,548 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_1.0))) (+ main_~x~0_5 .cse0 (* (- 4294967296) (div (+ main_~x~0_5 .cse0) 4294967296)))) 0)) [2022-04-07 17:27:02,548 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_2.1))) (+ main_~z~0_8 .cse0 (* (- 4294967296) (div (+ main_~z~0_8 .cse0) 4294967296)))) 0)) [2022-04-07 17:27:02,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:27:02,565 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_1.3))) (+ main_~x~0_5 .cse0 (* (- 4294967296) (div (+ main_~x~0_5 .cse0) 4294967296)))) 0)) [2022-04-07 17:27:02,600 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_2.4))) (+ main_~z~0_8 .cse0 (* (- 4294967296) (div (+ main_~z~0_8 .cse0) 4294967296)))) 0)) [2022-04-07 17:27:02,889 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 17:27:02,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:27:02,893 INFO L290 TraceCheckUtils]: 0: Hoare triple {1624#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1612#true} is VALID [2022-04-07 17:27:02,893 INFO L290 TraceCheckUtils]: 1: Hoare triple {1612#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1612#true} is VALID [2022-04-07 17:27:02,893 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1612#true} {1612#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1612#true} is VALID [2022-04-07 17:27:02,893 INFO L272 TraceCheckUtils]: 0: Hoare triple {1612#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1624#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 17:27:02,893 INFO L290 TraceCheckUtils]: 1: Hoare triple {1624#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1612#true} is VALID [2022-04-07 17:27:02,894 INFO L290 TraceCheckUtils]: 2: Hoare triple {1612#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1612#true} is VALID [2022-04-07 17:27:02,894 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1612#true} {1612#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1612#true} is VALID [2022-04-07 17:27:02,894 INFO L272 TraceCheckUtils]: 4: Hoare triple {1612#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1612#true} is VALID [2022-04-07 17:27:02,894 INFO L290 TraceCheckUtils]: 5: Hoare triple {1612#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1617#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} is VALID [2022-04-07 17:27:02,913 INFO L290 TraceCheckUtils]: 6: Hoare triple {1617#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} [83] L16-2-->L16-2: Formula: (let ((.cse0 (mod v_main_~x~0_4 4294967296))) (or (and (= |v_main_#t~post5_3| |v_main_#t~post5_1|) (= v_main_~x~0_4 v_main_~x~0_3) (= |v_main_#t~post6_3| |v_main_#t~post6_1|) (<= .cse0 0) (= v_main_~y~0_6 v_main_~y~0_5)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ v_main_~x~0_4 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)) (not (<= (+ v_main_~y~0_6 v_it_1 1) v_main_~y~0_5)))) (< v_main_~y~0_6 v_main_~y~0_5) (< 0 .cse0) (= v_main_~x~0_3 (+ v_main_~x~0_4 v_main_~y~0_6 (* (- 1) v_main_~y~0_5)))))) InVars {main_~y~0=v_main_~y~0_6, main_#t~post5=|v_main_#t~post5_3|, main_~x~0=v_main_~x~0_4, main_#t~post6=|v_main_#t~post6_3|} OutVars{main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_~x~0=v_main_~x~0_3, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] {1618#(or (and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0)) (<= (+ main_~y~0 main_~x~0) (+ (* 4294967296 (div (+ (- 1) main_~y~0 main_~x~0) 4294967296)) 4294967295)))} is VALID [2022-04-07 17:27:02,914 INFO L290 TraceCheckUtils]: 7: Hoare triple {1618#(or (and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0)) (<= (+ main_~y~0 main_~x~0) (+ (* 4294967296 (div (+ (- 1) main_~y~0 main_~x~0) 4294967296)) 4294967295)))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1619#(or (and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0)) (<= (+ main_~y~0 (* 4294967296 (div main_~x~0 4294967296))) (+ 4294967295 (* (div (+ (- 1) main_~y~0 (* 4294967296 (div main_~x~0 4294967296))) 4294967296) 4294967296))))} is VALID [2022-04-07 17:27:02,917 INFO L290 TraceCheckUtils]: 8: Hoare triple {1619#(or (and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0)) (<= (+ main_~y~0 (* 4294967296 (div main_~x~0 4294967296))) (+ 4294967295 (* (div (+ (- 1) main_~y~0 (* 4294967296 (div main_~x~0 4294967296))) 4294967296) 4294967296))))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1620#(and (= (+ main_~y~0 (* (- 1) main_~z~0)) 0) (or (and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0)) (< (* (div main_~z~0 4294967296) 4294967296) main_~z~0)))} is VALID [2022-04-07 17:27:02,936 INFO L290 TraceCheckUtils]: 9: Hoare triple {1620#(and (= (+ main_~y~0 (* (- 1) main_~z~0)) 0) (or (and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0)) (< (* (div main_~z~0 4294967296) 4294967296) main_~z~0)))} [87] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_7 4294967296))) (or (and (= v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_7 v_main_~z~0_6) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|) (<= .cse0 0)) (and (< v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_6 (+ (* (- 1) v_main_~x~0_8) v_main_~x~0_9 v_main_~z~0_7)) (forall ((v_it_2 Int)) (or (not (<= 1 v_it_2)) (not (<= (+ v_main_~x~0_9 v_it_2 1) v_main_~x~0_8)) (< 0 (mod (+ v_main_~z~0_7 (* v_it_2 4294967295)) 4294967296)))) (< 0 .cse0)))) InVars {main_~x~0=v_main_~x~0_9, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_8, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_6, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {1619#(or (and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0)) (<= (+ main_~y~0 (* 4294967296 (div main_~x~0 4294967296))) (+ 4294967295 (* (div (+ (- 1) main_~y~0 (* 4294967296 (div main_~x~0 4294967296))) 4294967296) 4294967296))))} is VALID [2022-04-07 17:27:02,937 INFO L290 TraceCheckUtils]: 10: Hoare triple {1619#(or (and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0)) (<= (+ main_~y~0 (* 4294967296 (div main_~x~0 4294967296))) (+ 4294967295 (* (div (+ (- 1) main_~y~0 (* 4294967296 (div main_~x~0 4294967296))) 4294967296) 4294967296))))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1619#(or (and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0)) (<= (+ main_~y~0 (* 4294967296 (div main_~x~0 4294967296))) (+ 4294967295 (* (div (+ (- 1) main_~y~0 (* 4294967296 (div main_~x~0 4294967296))) 4294967296) 4294967296))))} is VALID [2022-04-07 17:27:02,939 INFO L290 TraceCheckUtils]: 11: Hoare triple {1619#(or (and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0)) (<= (+ main_~y~0 (* 4294967296 (div main_~x~0 4294967296))) (+ 4294967295 (* (div (+ (- 1) main_~y~0 (* 4294967296 (div main_~x~0 4294967296))) 4294967296) 4294967296))))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1621#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0))} is VALID [2022-04-07 17:27:02,941 INFO L290 TraceCheckUtils]: 12: Hoare triple {1621#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1621#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0))} is VALID [2022-04-07 17:27:02,942 INFO L272 TraceCheckUtils]: 13: Hoare triple {1621#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {1622#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-07 17:27:02,943 INFO L290 TraceCheckUtils]: 14: Hoare triple {1622#(not (= |__VERIFIER_assert_#in~cond| 0))} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1623#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-07 17:27:02,943 INFO L290 TraceCheckUtils]: 15: Hoare triple {1623#(not (= __VERIFIER_assert_~cond 0))} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1613#false} is VALID [2022-04-07 17:27:02,943 INFO L290 TraceCheckUtils]: 16: Hoare triple {1613#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1613#false} is VALID [2022-04-07 17:27:02,943 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 17:27:02,943 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 17:27:02,944 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1107819520] [2022-04-07 17:27:02,944 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1107819520] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 17:27:02,944 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2058259720] [2022-04-07 17:27:02,944 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:27:02,944 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 17:27:02,944 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 17:27:02,945 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 17:27:02,949 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2022-04-07 17:27:02,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:27:02,998 INFO L263 TraceCheckSpWp]: Trace formula consists of 62 conjuncts, 9 conjunts are in the unsatisfiable core [2022-04-07 17:27:03,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:27:03,018 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 17:27:03,812 INFO L272 TraceCheckUtils]: 0: Hoare triple {1612#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1612#true} is VALID [2022-04-07 17:27:03,813 INFO L290 TraceCheckUtils]: 1: Hoare triple {1612#true} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1612#true} is VALID [2022-04-07 17:27:03,813 INFO L290 TraceCheckUtils]: 2: Hoare triple {1612#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1612#true} is VALID [2022-04-07 17:27:03,813 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1612#true} {1612#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1612#true} is VALID [2022-04-07 17:27:03,813 INFO L272 TraceCheckUtils]: 4: Hoare triple {1612#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1612#true} is VALID [2022-04-07 17:27:03,814 INFO L290 TraceCheckUtils]: 5: Hoare triple {1612#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1617#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} is VALID [2022-04-07 17:27:03,819 INFO L290 TraceCheckUtils]: 6: Hoare triple {1617#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} [83] L16-2-->L16-2: Formula: (let ((.cse0 (mod v_main_~x~0_4 4294967296))) (or (and (= |v_main_#t~post5_3| |v_main_#t~post5_1|) (= v_main_~x~0_4 v_main_~x~0_3) (= |v_main_#t~post6_3| |v_main_#t~post6_1|) (<= .cse0 0) (= v_main_~y~0_6 v_main_~y~0_5)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ v_main_~x~0_4 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)) (not (<= (+ v_main_~y~0_6 v_it_1 1) v_main_~y~0_5)))) (< v_main_~y~0_6 v_main_~y~0_5) (< 0 .cse0) (= v_main_~x~0_3 (+ v_main_~x~0_4 v_main_~y~0_6 (* (- 1) v_main_~y~0_5)))))) InVars {main_~y~0=v_main_~y~0_6, main_#t~post5=|v_main_#t~post5_3|, main_~x~0=v_main_~x~0_4, main_#t~post6=|v_main_#t~post6_3|} OutVars{main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_~x~0=v_main_~x~0_3, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] {1646#(or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)))} is VALID [2022-04-07 17:27:03,820 INFO L290 TraceCheckUtils]: 7: Hoare triple {1646#(or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1646#(or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)))} is VALID [2022-04-07 17:27:03,821 INFO L290 TraceCheckUtils]: 8: Hoare triple {1646#(or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1646#(or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)))} is VALID [2022-04-07 17:27:03,822 INFO L290 TraceCheckUtils]: 9: Hoare triple {1646#(or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)))} [87] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_7 4294967296))) (or (and (= v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_7 v_main_~z~0_6) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|) (<= .cse0 0)) (and (< v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_6 (+ (* (- 1) v_main_~x~0_8) v_main_~x~0_9 v_main_~z~0_7)) (forall ((v_it_2 Int)) (or (not (<= 1 v_it_2)) (not (<= (+ v_main_~x~0_9 v_it_2 1) v_main_~x~0_8)) (< 0 (mod (+ v_main_~z~0_7 (* v_it_2 4294967295)) 4294967296)))) (< 0 .cse0)))) InVars {main_~x~0=v_main_~x~0_9, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_8, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_6, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {1646#(or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)))} is VALID [2022-04-07 17:27:03,823 INFO L290 TraceCheckUtils]: 10: Hoare triple {1646#(or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1646#(or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)))} is VALID [2022-04-07 17:27:03,825 INFO L290 TraceCheckUtils]: 11: Hoare triple {1646#(or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1621#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0))} is VALID [2022-04-07 17:27:03,825 INFO L290 TraceCheckUtils]: 12: Hoare triple {1621#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1621#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0))} is VALID [2022-04-07 17:27:03,826 INFO L272 TraceCheckUtils]: 13: Hoare triple {1621#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {1668#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 17:27:03,826 INFO L290 TraceCheckUtils]: 14: Hoare triple {1668#(<= 1 |__VERIFIER_assert_#in~cond|)} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1672#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 17:27:03,827 INFO L290 TraceCheckUtils]: 15: Hoare triple {1672#(<= 1 __VERIFIER_assert_~cond)} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1613#false} is VALID [2022-04-07 17:27:03,827 INFO L290 TraceCheckUtils]: 16: Hoare triple {1613#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1613#false} is VALID [2022-04-07 17:27:03,827 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-07 17:27:03,827 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-07 17:27:10,439 INFO L290 TraceCheckUtils]: 16: Hoare triple {1613#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1613#false} is VALID [2022-04-07 17:27:10,439 INFO L290 TraceCheckUtils]: 15: Hoare triple {1672#(<= 1 __VERIFIER_assert_~cond)} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1613#false} is VALID [2022-04-07 17:27:10,439 INFO L290 TraceCheckUtils]: 14: Hoare triple {1668#(<= 1 |__VERIFIER_assert_#in~cond|)} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1672#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 17:27:10,440 INFO L272 TraceCheckUtils]: 13: Hoare triple {1688#(= (mod main_~n~0 4294967296) (mod main_~y~0 4294967296))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {1668#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 17:27:10,440 INFO L290 TraceCheckUtils]: 12: Hoare triple {1688#(= (mod main_~n~0 4294967296) (mod main_~y~0 4294967296))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1688#(= (mod main_~n~0 4294967296) (mod main_~y~0 4294967296))} is VALID [2022-04-07 17:27:10,441 INFO L290 TraceCheckUtils]: 11: Hoare triple {1695#(or (= (mod main_~n~0 4294967296) (mod main_~y~0 4294967296)) (< 0 (mod main_~y~0 4294967296)))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1688#(= (mod main_~n~0 4294967296) (mod main_~y~0 4294967296))} is VALID [2022-04-07 17:27:10,441 INFO L290 TraceCheckUtils]: 10: Hoare triple {1695#(or (= (mod main_~n~0 4294967296) (mod main_~y~0 4294967296)) (< 0 (mod main_~y~0 4294967296)))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1695#(or (= (mod main_~n~0 4294967296) (mod main_~y~0 4294967296)) (< 0 (mod main_~y~0 4294967296)))} is VALID [2022-04-07 17:27:10,442 INFO L290 TraceCheckUtils]: 9: Hoare triple {1695#(or (= (mod main_~n~0 4294967296) (mod main_~y~0 4294967296)) (< 0 (mod main_~y~0 4294967296)))} [87] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_7 4294967296))) (or (and (= v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_7 v_main_~z~0_6) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|) (<= .cse0 0)) (and (< v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_6 (+ (* (- 1) v_main_~x~0_8) v_main_~x~0_9 v_main_~z~0_7)) (forall ((v_it_2 Int)) (or (not (<= 1 v_it_2)) (not (<= (+ v_main_~x~0_9 v_it_2 1) v_main_~x~0_8)) (< 0 (mod (+ v_main_~z~0_7 (* v_it_2 4294967295)) 4294967296)))) (< 0 .cse0)))) InVars {main_~x~0=v_main_~x~0_9, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_8, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_6, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {1695#(or (= (mod main_~n~0 4294967296) (mod main_~y~0 4294967296)) (< 0 (mod main_~y~0 4294967296)))} is VALID [2022-04-07 17:27:10,442 INFO L290 TraceCheckUtils]: 8: Hoare triple {1695#(or (= (mod main_~n~0 4294967296) (mod main_~y~0 4294967296)) (< 0 (mod main_~y~0 4294967296)))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1695#(or (= (mod main_~n~0 4294967296) (mod main_~y~0 4294967296)) (< 0 (mod main_~y~0 4294967296)))} is VALID [2022-04-07 17:27:10,442 INFO L290 TraceCheckUtils]: 7: Hoare triple {1695#(or (= (mod main_~n~0 4294967296) (mod main_~y~0 4294967296)) (< 0 (mod main_~y~0 4294967296)))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1695#(or (= (mod main_~n~0 4294967296) (mod main_~y~0 4294967296)) (< 0 (mod main_~y~0 4294967296)))} is VALID [2022-04-07 17:27:12,459 WARN L290 TraceCheckUtils]: 6: Hoare triple {1711#(forall ((aux_mod_aux_mod_v_main_~y~0_38_31_42 Int) (aux_div_aux_mod_v_main_~y~0_38_31_42 Int)) (or (and (or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_div_v_main_~y~0_38_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_38_31 4294967296) (* aux_div_aux_mod_v_main_~y~0_38_31_42 4294967296) aux_mod_aux_mod_v_main_~y~0_38_31_42))) (exists ((v_it_1 Int)) (and (not (< 0 (mod (+ main_~x~0 (* v_it_1 4294967295)) 4294967296))) (<= 1 v_it_1) (<= (+ v_it_1 main_~y~0 1) (+ (* aux_div_v_main_~y~0_38_31 4294967296) (* aux_div_aux_mod_v_main_~y~0_38_31_42 4294967296) aux_mod_aux_mod_v_main_~y~0_38_31_42))))))) (or (< 0 (mod main_~x~0 4294967296)) (forall ((aux_div_v_main_~y~0_38_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_38_31 4294967296) (* aux_div_aux_mod_v_main_~y~0_38_31_42 4294967296) aux_mod_aux_mod_v_main_~y~0_38_31_42)))))) (>= aux_mod_aux_mod_v_main_~y~0_38_31_42 4294967296) (= (mod main_~n~0 4294967296) aux_mod_aux_mod_v_main_~y~0_38_31_42) (< 0 (+ (* aux_div_aux_mod_v_main_~y~0_38_31_42 4294967296) aux_mod_aux_mod_v_main_~y~0_38_31_42)) (< (+ (* aux_div_aux_mod_v_main_~y~0_38_31_42 4294967296) aux_mod_aux_mod_v_main_~y~0_38_31_42) 0) (> 0 aux_mod_aux_mod_v_main_~y~0_38_31_42)))} [83] L16-2-->L16-2: Formula: (let ((.cse0 (mod v_main_~x~0_4 4294967296))) (or (and (= |v_main_#t~post5_3| |v_main_#t~post5_1|) (= v_main_~x~0_4 v_main_~x~0_3) (= |v_main_#t~post6_3| |v_main_#t~post6_1|) (<= .cse0 0) (= v_main_~y~0_6 v_main_~y~0_5)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ v_main_~x~0_4 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)) (not (<= (+ v_main_~y~0_6 v_it_1 1) v_main_~y~0_5)))) (< v_main_~y~0_6 v_main_~y~0_5) (< 0 .cse0) (= v_main_~x~0_3 (+ v_main_~x~0_4 v_main_~y~0_6 (* (- 1) v_main_~y~0_5)))))) InVars {main_~y~0=v_main_~y~0_6, main_#t~post5=|v_main_#t~post5_3|, main_~x~0=v_main_~x~0_4, main_#t~post6=|v_main_#t~post6_3|} OutVars{main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_~x~0=v_main_~x~0_3, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] {1695#(or (= (mod main_~n~0 4294967296) (mod main_~y~0 4294967296)) (< 0 (mod main_~y~0 4294967296)))} is UNKNOWN [2022-04-07 17:27:12,484 INFO L290 TraceCheckUtils]: 5: Hoare triple {1612#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1711#(forall ((aux_mod_aux_mod_v_main_~y~0_38_31_42 Int) (aux_div_aux_mod_v_main_~y~0_38_31_42 Int)) (or (and (or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_div_v_main_~y~0_38_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_38_31 4294967296) (* aux_div_aux_mod_v_main_~y~0_38_31_42 4294967296) aux_mod_aux_mod_v_main_~y~0_38_31_42))) (exists ((v_it_1 Int)) (and (not (< 0 (mod (+ main_~x~0 (* v_it_1 4294967295)) 4294967296))) (<= 1 v_it_1) (<= (+ v_it_1 main_~y~0 1) (+ (* aux_div_v_main_~y~0_38_31 4294967296) (* aux_div_aux_mod_v_main_~y~0_38_31_42 4294967296) aux_mod_aux_mod_v_main_~y~0_38_31_42))))))) (or (< 0 (mod main_~x~0 4294967296)) (forall ((aux_div_v_main_~y~0_38_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_38_31 4294967296) (* aux_div_aux_mod_v_main_~y~0_38_31_42 4294967296) aux_mod_aux_mod_v_main_~y~0_38_31_42)))))) (>= aux_mod_aux_mod_v_main_~y~0_38_31_42 4294967296) (= (mod main_~n~0 4294967296) aux_mod_aux_mod_v_main_~y~0_38_31_42) (< 0 (+ (* aux_div_aux_mod_v_main_~y~0_38_31_42 4294967296) aux_mod_aux_mod_v_main_~y~0_38_31_42)) (< (+ (* aux_div_aux_mod_v_main_~y~0_38_31_42 4294967296) aux_mod_aux_mod_v_main_~y~0_38_31_42) 0) (> 0 aux_mod_aux_mod_v_main_~y~0_38_31_42)))} is VALID [2022-04-07 17:27:12,484 INFO L272 TraceCheckUtils]: 4: Hoare triple {1612#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1612#true} is VALID [2022-04-07 17:27:12,485 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1612#true} {1612#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1612#true} is VALID [2022-04-07 17:27:12,485 INFO L290 TraceCheckUtils]: 2: Hoare triple {1612#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1612#true} is VALID [2022-04-07 17:27:12,485 INFO L290 TraceCheckUtils]: 1: Hoare triple {1612#true} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1612#true} is VALID [2022-04-07 17:27:12,485 INFO L272 TraceCheckUtils]: 0: Hoare triple {1612#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1612#true} is VALID [2022-04-07 17:27:12,485 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-07 17:27:12,485 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2058259720] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-07 17:27:12,485 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-07 17:27:12,485 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 7, 7] total 16 [2022-04-07 17:27:12,485 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1303400062] [2022-04-07 17:27:12,485 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-07 17:27:12,486 INFO L78 Accepts]: Start accepts. Automaton has has 16 states, 16 states have (on average 1.875) internal successors, (30), 13 states have internal predecessors, (30), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-07 17:27:12,486 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 17:27:12,486 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 16 states, 16 states have (on average 1.875) internal successors, (30), 13 states have internal predecessors, (30), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:27:14,603 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 37 edges. 36 inductive. 0 not inductive. 1 times theorem prover too weak to decide inductivity. [2022-04-07 17:27:14,604 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 16 states [2022-04-07 17:27:14,604 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 17:27:14,604 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2022-04-07 17:27:14,604 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=194, Unknown=1, NotChecked=0, Total=240 [2022-04-07 17:27:14,605 INFO L87 Difference]: Start difference. First operand 31 states and 43 transitions. Second operand has 16 states, 16 states have (on average 1.875) internal successors, (30), 13 states have internal predecessors, (30), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:27:19,985 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:27:19,985 INFO L93 Difference]: Finished difference Result 40 states and 57 transitions. [2022-04-07 17:27:19,985 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-04-07 17:27:19,985 INFO L78 Accepts]: Start accepts. Automaton has has 16 states, 16 states have (on average 1.875) internal successors, (30), 13 states have internal predecessors, (30), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-07 17:27:19,985 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 17:27:19,985 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 1.875) internal successors, (30), 13 states have internal predecessors, (30), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:27:19,986 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 43 transitions. [2022-04-07 17:27:19,986 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 1.875) internal successors, (30), 13 states have internal predecessors, (30), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:27:19,987 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 43 transitions. [2022-04-07 17:27:19,987 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 13 states and 43 transitions. [2022-04-07 17:27:20,102 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 43 edges. 43 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 17:27:20,103 INFO L225 Difference]: With dead ends: 40 [2022-04-07 17:27:20,103 INFO L226 Difference]: Without dead ends: 37 [2022-04-07 17:27:20,103 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 27 SyntacticMatches, 4 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 104 ImplicationChecksByTransitivity, 9.6s TimeCoverageRelationStatistics Valid=119, Invalid=430, Unknown=3, NotChecked=0, Total=552 [2022-04-07 17:27:20,103 INFO L913 BasicCegarLoop]: 12 mSDtfsCounter, 19 mSDsluCounter, 62 mSDsCounter, 0 mSdLazyCounter, 67 mSolverCounterSat, 10 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 19 SdHoareTripleChecker+Valid, 74 SdHoareTripleChecker+Invalid, 111 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 10 IncrementalHoareTripleChecker+Valid, 67 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 34 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-07 17:27:20,104 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [19 Valid, 74 Invalid, 111 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [10 Valid, 67 Invalid, 0 Unknown, 34 Unchecked, 0.1s Time] [2022-04-07 17:27:20,104 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states. [2022-04-07 17:27:20,105 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 32. [2022-04-07 17:27:20,105 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 17:27:20,105 INFO L82 GeneralOperation]: Start isEquivalent. First operand 37 states. Second operand has 32 states, 27 states have (on average 1.5185185185185186) internal successors, (41), 27 states have internal predecessors, (41), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:27:20,105 INFO L74 IsIncluded]: Start isIncluded. First operand 37 states. Second operand has 32 states, 27 states have (on average 1.5185185185185186) internal successors, (41), 27 states have internal predecessors, (41), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:27:20,105 INFO L87 Difference]: Start difference. First operand 37 states. Second operand has 32 states, 27 states have (on average 1.5185185185185186) internal successors, (41), 27 states have internal predecessors, (41), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:27:20,106 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:27:20,106 INFO L93 Difference]: Finished difference Result 37 states and 54 transitions. [2022-04-07 17:27:20,106 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 54 transitions. [2022-04-07 17:27:20,107 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:27:20,107 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:27:20,107 INFO L74 IsIncluded]: Start isIncluded. First operand has 32 states, 27 states have (on average 1.5185185185185186) internal successors, (41), 27 states have internal predecessors, (41), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 37 states. [2022-04-07 17:27:20,107 INFO L87 Difference]: Start difference. First operand has 32 states, 27 states have (on average 1.5185185185185186) internal successors, (41), 27 states have internal predecessors, (41), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 37 states. [2022-04-07 17:27:20,108 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:27:20,108 INFO L93 Difference]: Finished difference Result 37 states and 54 transitions. [2022-04-07 17:27:20,108 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 54 transitions. [2022-04-07 17:27:20,108 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:27:20,108 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:27:20,108 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 17:27:20,108 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 17:27:20,108 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32 states, 27 states have (on average 1.5185185185185186) internal successors, (41), 27 states have internal predecessors, (41), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:27:20,109 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 45 transitions. [2022-04-07 17:27:20,109 INFO L78 Accepts]: Start accepts. Automaton has 32 states and 45 transitions. Word has length 17 [2022-04-07 17:27:20,109 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 17:27:20,109 INFO L478 AbstractCegarLoop]: Abstraction has 32 states and 45 transitions. [2022-04-07 17:27:20,109 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 16 states, 16 states have (on average 1.875) internal successors, (30), 13 states have internal predecessors, (30), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:27:20,109 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 45 transitions. [2022-04-07 17:27:20,109 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2022-04-07 17:27:20,109 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 17:27:20,109 INFO L499 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 17:27:20,129 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Forceful destruction successful, exit code 0 [2022-04-07 17:27:20,327 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8,8 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 17:27:20,327 INFO L403 AbstractCegarLoop]: === Iteration 10 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 17:27:20,328 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 17:27:20,328 INFO L85 PathProgramCache]: Analyzing trace with hash 325265765, now seen corresponding path program 2 times [2022-04-07 17:27:20,328 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 17:27:20,328 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1394898753] [2022-04-07 17:27:20,328 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:27:20,328 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 17:27:20,336 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_2.0))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-07 17:27:20,337 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.1))) (+ .cse0 main_~x~0_8 (* (- 4294967296) (div (+ .cse0 main_~x~0_8) 4294967296)))) 0)) [2022-04-07 17:27:20,337 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.2))) (+ .cse0 main_~x~0_11 (* (- 4294967296) (div (+ .cse0 main_~x~0_11) 4294967296)))) 0)) [2022-04-07 17:27:20,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:27:20,352 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_2.5))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-07 17:27:20,354 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.6))) (+ .cse0 main_~x~0_8 (* (- 4294967296) (div (+ .cse0 main_~x~0_8) 4294967296)))) 0)) [2022-04-07 17:27:20,357 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.7))) (+ .cse0 main_~x~0_11 (* (- 4294967296) (div (+ .cse0 main_~x~0_11) 4294967296)))) 0)) [2022-04-07 17:27:20,574 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 17:27:20,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:27:20,584 INFO L290 TraceCheckUtils]: 0: Hoare triple {1907#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1894#true} is VALID [2022-04-07 17:27:20,584 INFO L290 TraceCheckUtils]: 1: Hoare triple {1894#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1894#true} is VALID [2022-04-07 17:27:20,584 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1894#true} {1894#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1894#true} is VALID [2022-04-07 17:27:20,585 INFO L272 TraceCheckUtils]: 0: Hoare triple {1894#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1907#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 17:27:20,585 INFO L290 TraceCheckUtils]: 1: Hoare triple {1907#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1894#true} is VALID [2022-04-07 17:27:20,585 INFO L290 TraceCheckUtils]: 2: Hoare triple {1894#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1894#true} is VALID [2022-04-07 17:27:20,585 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1894#true} {1894#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1894#true} is VALID [2022-04-07 17:27:20,585 INFO L272 TraceCheckUtils]: 4: Hoare triple {1894#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1894#true} is VALID [2022-04-07 17:27:20,586 INFO L290 TraceCheckUtils]: 5: Hoare triple {1894#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1899#(and (= main_~n~0 main_~x~0) (= main_~y~0 0))} is VALID [2022-04-07 17:27:20,586 INFO L290 TraceCheckUtils]: 6: Hoare triple {1899#(and (= main_~n~0 main_~x~0) (= main_~y~0 0))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1900#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:27:20,587 INFO L290 TraceCheckUtils]: 7: Hoare triple {1900#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1901#(and (= main_~z~0 0) (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:27:20,588 INFO L290 TraceCheckUtils]: 8: Hoare triple {1901#(and (= main_~z~0 0) (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [87] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_7 4294967296))) (or (and (= v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_7 v_main_~z~0_6) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|) (<= .cse0 0)) (and (< v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_6 (+ (* (- 1) v_main_~x~0_8) v_main_~x~0_9 v_main_~z~0_7)) (forall ((v_it_2 Int)) (or (not (<= 1 v_it_2)) (not (<= (+ v_main_~x~0_9 v_it_2 1) v_main_~x~0_8)) (< 0 (mod (+ v_main_~z~0_7 (* v_it_2 4294967295)) 4294967296)))) (< 0 .cse0)))) InVars {main_~x~0=v_main_~x~0_9, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_8, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_6, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {1900#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:27:20,588 INFO L290 TraceCheckUtils]: 9: Hoare triple {1900#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1900#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:27:20,589 INFO L290 TraceCheckUtils]: 10: Hoare triple {1900#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1900#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:27:20,591 INFO L290 TraceCheckUtils]: 11: Hoare triple {1900#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [93] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1902#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~n~0 (+ main_~y~0 main_~x~0 (* (div (+ main_~n~0 (* (- 1) main_~x~0) (* (- 1) main_~y~0)) 4294967296) 4294967296))) (<= (* (div (+ main_~y~0 main_~x~0 4294967295) 4294967296) 4294967296) (+ main_~y~0 main_~x~0)))} is VALID [2022-04-07 17:27:20,597 INFO L290 TraceCheckUtils]: 12: Hoare triple {1902#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~n~0 (+ main_~y~0 main_~x~0 (* (div (+ main_~n~0 (* (- 1) main_~x~0) (* (- 1) main_~y~0)) 4294967296) 4294967296))) (<= (* (div (+ main_~y~0 main_~x~0 4294967295) 4294967296) 4294967296) (+ main_~y~0 main_~x~0)))} [93] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1903#(or (<= (+ (* (div main_~y~0 4294967296) 4294967296) 4294967296 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~y~0 main_~x~0)) (and (<= (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~y~0 main_~x~0 (* (div main_~n~0 4294967296) 4294967296))) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0))))} is VALID [2022-04-07 17:27:20,598 INFO L290 TraceCheckUtils]: 13: Hoare triple {1903#(or (<= (+ (* (div main_~y~0 4294967296) 4294967296) 4294967296 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~y~0 main_~x~0)) (and (<= (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~y~0 main_~x~0 (* (div main_~n~0 4294967296) 4294967296))) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0))))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1904#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is VALID [2022-04-07 17:27:20,599 INFO L272 TraceCheckUtils]: 14: Hoare triple {1904#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {1905#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-07 17:27:20,599 INFO L290 TraceCheckUtils]: 15: Hoare triple {1905#(not (= |__VERIFIER_assert_#in~cond| 0))} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1906#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-07 17:27:20,599 INFO L290 TraceCheckUtils]: 16: Hoare triple {1906#(not (= __VERIFIER_assert_~cond 0))} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1895#false} is VALID [2022-04-07 17:27:20,599 INFO L290 TraceCheckUtils]: 17: Hoare triple {1895#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1895#false} is VALID [2022-04-07 17:27:20,599 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 17:27:20,600 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 17:27:20,600 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1394898753] [2022-04-07 17:27:20,600 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1394898753] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 17:27:20,600 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1262561883] [2022-04-07 17:27:20,600 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-04-07 17:27:20,600 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 17:27:20,600 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 17:27:20,601 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 17:27:20,601 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2022-04-07 17:27:20,631 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-04-07 17:27:20,631 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-07 17:27:20,632 INFO L263 TraceCheckSpWp]: Trace formula consists of 63 conjuncts, 14 conjunts are in the unsatisfiable core [2022-04-07 17:27:20,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:27:20,649 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 17:27:21,133 INFO L272 TraceCheckUtils]: 0: Hoare triple {1894#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1894#true} is VALID [2022-04-07 17:27:21,134 INFO L290 TraceCheckUtils]: 1: Hoare triple {1894#true} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1894#true} is VALID [2022-04-07 17:27:21,134 INFO L290 TraceCheckUtils]: 2: Hoare triple {1894#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1894#true} is VALID [2022-04-07 17:27:21,134 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1894#true} {1894#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1894#true} is VALID [2022-04-07 17:27:21,134 INFO L272 TraceCheckUtils]: 4: Hoare triple {1894#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1894#true} is VALID [2022-04-07 17:27:21,134 INFO L290 TraceCheckUtils]: 5: Hoare triple {1894#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1899#(and (= main_~n~0 main_~x~0) (= main_~y~0 0))} is VALID [2022-04-07 17:27:21,135 INFO L290 TraceCheckUtils]: 6: Hoare triple {1899#(and (= main_~n~0 main_~x~0) (= main_~y~0 0))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1900#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:27:21,135 INFO L290 TraceCheckUtils]: 7: Hoare triple {1900#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1901#(and (= main_~z~0 0) (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:27:21,136 INFO L290 TraceCheckUtils]: 8: Hoare triple {1901#(and (= main_~z~0 0) (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [87] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_7 4294967296))) (or (and (= v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_7 v_main_~z~0_6) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|) (<= .cse0 0)) (and (< v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_6 (+ (* (- 1) v_main_~x~0_8) v_main_~x~0_9 v_main_~z~0_7)) (forall ((v_it_2 Int)) (or (not (<= 1 v_it_2)) (not (<= (+ v_main_~x~0_9 v_it_2 1) v_main_~x~0_8)) (< 0 (mod (+ v_main_~z~0_7 (* v_it_2 4294967295)) 4294967296)))) (< 0 .cse0)))) InVars {main_~x~0=v_main_~x~0_9, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_8, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_6, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {1900#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:27:21,139 INFO L290 TraceCheckUtils]: 9: Hoare triple {1900#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1900#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:27:21,140 INFO L290 TraceCheckUtils]: 10: Hoare triple {1900#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1900#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:27:21,141 INFO L290 TraceCheckUtils]: 11: Hoare triple {1900#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [93] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1900#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:27:21,142 INFO L290 TraceCheckUtils]: 12: Hoare triple {1900#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [93] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1947#(and (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (= main_~y~0 0))} is VALID [2022-04-07 17:27:21,142 INFO L290 TraceCheckUtils]: 13: Hoare triple {1947#(and (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (= main_~y~0 0))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1947#(and (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (= main_~y~0 0))} is VALID [2022-04-07 17:27:21,143 INFO L272 TraceCheckUtils]: 14: Hoare triple {1947#(and (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (= main_~y~0 0))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {1954#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 17:27:21,143 INFO L290 TraceCheckUtils]: 15: Hoare triple {1954#(<= 1 |__VERIFIER_assert_#in~cond|)} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1958#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 17:27:21,143 INFO L290 TraceCheckUtils]: 16: Hoare triple {1958#(<= 1 __VERIFIER_assert_~cond)} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1895#false} is VALID [2022-04-07 17:27:21,144 INFO L290 TraceCheckUtils]: 17: Hoare triple {1895#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1895#false} is VALID [2022-04-07 17:27:21,144 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-07 17:27:21,144 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-07 17:27:59,070 WARN L232 SmtUtils]: Spent 14.48s on a formula simplification that was a NOOP. DAG size: 88 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-07 17:28:22,299 WARN L232 SmtUtils]: Spent 12.02s on a formula simplification that was a NOOP. DAG size: 83 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-07 17:37:53,258 WARN L232 SmtUtils]: Spent 49.15s on a formula simplification that was a NOOP. DAG size: 162 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-07 17:38:05,164 INFO L290 TraceCheckUtils]: 17: Hoare triple {1895#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1895#false} is VALID [2022-04-07 17:38:05,164 INFO L290 TraceCheckUtils]: 16: Hoare triple {1958#(<= 1 __VERIFIER_assert_~cond)} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1895#false} is VALID [2022-04-07 17:38:05,164 INFO L290 TraceCheckUtils]: 15: Hoare triple {1954#(<= 1 |__VERIFIER_assert_#in~cond|)} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1958#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 17:38:05,165 INFO L272 TraceCheckUtils]: 14: Hoare triple {1904#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {1954#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 17:38:05,166 INFO L290 TraceCheckUtils]: 13: Hoare triple {1904#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1904#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is VALID [2022-04-07 17:38:07,180 WARN L290 TraceCheckUtils]: 12: Hoare triple {1980#(and (forall ((aux_mod_v_main_~y~0_42_31 Int)) (or (and (or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_div_v_main_~y~0_42_31 Int)) (or (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4) (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)))) (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)))))) (or (forall ((aux_div_v_main_~y~0_42_31 Int)) (not (= (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31) main_~y~0))) (< 0 (mod main_~x~0 4294967296)))) (< main_~n~0 (+ aux_mod_v_main_~y~0_42_31 (* (div main_~n~0 4294967296) 4294967296) 1)) (< aux_mod_v_main_~y~0_42_31 0))) (forall ((aux_mod_v_main_~y~0_42_31 Int)) (or (and (or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_div_v_main_~y~0_42_31 Int)) (or (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4) (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)))) (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)))))) (or (forall ((aux_div_v_main_~y~0_42_31 Int)) (not (= (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31) main_~y~0))) (< 0 (mod main_~x~0 4294967296)))) (<= 4294967296 aux_mod_v_main_~y~0_42_31) (<= (+ aux_mod_v_main_~y~0_42_31 (* (div main_~n~0 4294967296) 4294967296)) main_~n~0))))} [93] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1904#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is UNKNOWN [2022-04-07 17:38:09,190 WARN L290 TraceCheckUtils]: 11: Hoare triple {1984#(and (or (not (< 0 (mod main_~x~0 4294967296))) (forall ((v_main_~y~0_43 Int)) (or (and (forall ((aux_mod_v_main_~y~0_42_31 Int)) (or (and (or (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_42_31 Int)) (not (= v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (or (forall ((aux_div_v_main_~y~0_42_31 Int)) (or (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))) (<= (+ v_main_~y~0_43 v_it_4 1) (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (<= 1 v_it_4))) (not (< v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (not (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))))) (< main_~n~0 (+ aux_mod_v_main_~y~0_42_31 (* (div main_~n~0 4294967296) 4294967296) 1)) (< aux_mod_v_main_~y~0_42_31 0))) (forall ((aux_mod_v_main_~y~0_42_31 Int)) (or (and (or (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_42_31 Int)) (not (= v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (or (forall ((aux_div_v_main_~y~0_42_31 Int)) (or (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))) (<= (+ v_main_~y~0_43 v_it_4 1) (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (<= 1 v_it_4))) (not (< v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (not (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_42_31) (<= (+ aux_mod_v_main_~y~0_42_31 (* (div main_~n~0 4294967296) 4294967296)) main_~n~0)))) (not (< main_~y~0 v_main_~y~0_43)) (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= (+ v_it_4 main_~y~0 1) v_main_~y~0_43) (<= 1 v_it_4)))))) (or (and (< (div (+ (- 1) (* (- 1) main_~y~0)) (- 4294967296)) (+ (div main_~n~0 4294967296) 2 (div (+ main_~y~0 (* (- 1) main_~n~0)) 4294967296))) (<= (+ (div (+ main_~n~0 (* (- 1) main_~y~0)) (- 4294967296)) (div main_~n~0 4294967296)) (+ (div (+ main_~y~0 (- 4294967296)) 4294967296) 1))) (< 0 (mod main_~x~0 4294967296))))} [93] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1980#(and (forall ((aux_mod_v_main_~y~0_42_31 Int)) (or (and (or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_div_v_main_~y~0_42_31 Int)) (or (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4) (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)))) (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)))))) (or (forall ((aux_div_v_main_~y~0_42_31 Int)) (not (= (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31) main_~y~0))) (< 0 (mod main_~x~0 4294967296)))) (< main_~n~0 (+ aux_mod_v_main_~y~0_42_31 (* (div main_~n~0 4294967296) 4294967296) 1)) (< aux_mod_v_main_~y~0_42_31 0))) (forall ((aux_mod_v_main_~y~0_42_31 Int)) (or (and (or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_div_v_main_~y~0_42_31 Int)) (or (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4) (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)))) (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)))))) (or (forall ((aux_div_v_main_~y~0_42_31 Int)) (not (= (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31) main_~y~0))) (< 0 (mod main_~x~0 4294967296)))) (<= 4294967296 aux_mod_v_main_~y~0_42_31) (<= (+ aux_mod_v_main_~y~0_42_31 (* (div main_~n~0 4294967296) 4294967296)) main_~n~0))))} is UNKNOWN [2022-04-07 17:38:11,213 WARN L290 TraceCheckUtils]: 10: Hoare triple {1988#(or (and (or (not (< 0 (mod main_~x~0 4294967296))) (forall ((v_main_~y~0_43 Int)) (or (and (forall ((aux_mod_v_main_~y~0_42_31 Int)) (or (and (or (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_42_31 Int)) (not (= v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (or (forall ((aux_div_v_main_~y~0_42_31 Int)) (or (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))) (<= (+ v_main_~y~0_43 v_it_4 1) (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (<= 1 v_it_4))) (not (< v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (not (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))))) (< main_~n~0 (+ aux_mod_v_main_~y~0_42_31 (* (div main_~n~0 4294967296) 4294967296) 1)) (< aux_mod_v_main_~y~0_42_31 0))) (forall ((aux_mod_v_main_~y~0_42_31 Int)) (or (and (or (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_42_31 Int)) (not (= v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (or (forall ((aux_div_v_main_~y~0_42_31 Int)) (or (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))) (<= (+ v_main_~y~0_43 v_it_4 1) (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (<= 1 v_it_4))) (not (< v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (not (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_42_31) (<= (+ aux_mod_v_main_~y~0_42_31 (* (div main_~n~0 4294967296) 4294967296)) main_~n~0)))) (not (< main_~y~0 v_main_~y~0_43)) (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= (+ v_it_4 main_~y~0 1) v_main_~y~0_43) (<= 1 v_it_4)))))) (or (< (div (+ (- 1) (* (- 1) main_~y~0)) (- 4294967296)) (+ (div main_~n~0 4294967296) 2 (div (+ main_~y~0 (* (- 1) main_~n~0)) 4294967296))) (< 0 (mod main_~x~0 4294967296)))) (< 0 (mod main_~y~0 4294967296)))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1984#(and (or (not (< 0 (mod main_~x~0 4294967296))) (forall ((v_main_~y~0_43 Int)) (or (and (forall ((aux_mod_v_main_~y~0_42_31 Int)) (or (and (or (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_42_31 Int)) (not (= v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (or (forall ((aux_div_v_main_~y~0_42_31 Int)) (or (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))) (<= (+ v_main_~y~0_43 v_it_4 1) (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (<= 1 v_it_4))) (not (< v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (not (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))))) (< main_~n~0 (+ aux_mod_v_main_~y~0_42_31 (* (div main_~n~0 4294967296) 4294967296) 1)) (< aux_mod_v_main_~y~0_42_31 0))) (forall ((aux_mod_v_main_~y~0_42_31 Int)) (or (and (or (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_42_31 Int)) (not (= v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (or (forall ((aux_div_v_main_~y~0_42_31 Int)) (or (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))) (<= (+ v_main_~y~0_43 v_it_4 1) (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (<= 1 v_it_4))) (not (< v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (not (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_42_31) (<= (+ aux_mod_v_main_~y~0_42_31 (* (div main_~n~0 4294967296) 4294967296)) main_~n~0)))) (not (< main_~y~0 v_main_~y~0_43)) (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= (+ v_it_4 main_~y~0 1) v_main_~y~0_43) (<= 1 v_it_4)))))) (or (and (< (div (+ (- 1) (* (- 1) main_~y~0)) (- 4294967296)) (+ (div main_~n~0 4294967296) 2 (div (+ main_~y~0 (* (- 1) main_~n~0)) 4294967296))) (<= (+ (div (+ main_~n~0 (* (- 1) main_~y~0)) (- 4294967296)) (div main_~n~0 4294967296)) (+ (div (+ main_~y~0 (- 4294967296)) 4294967296) 1))) (< 0 (mod main_~x~0 4294967296))))} is UNKNOWN [2022-04-07 17:38:13,229 WARN L290 TraceCheckUtils]: 9: Hoare triple {1988#(or (and (or (not (< 0 (mod main_~x~0 4294967296))) (forall ((v_main_~y~0_43 Int)) (or (and (forall ((aux_mod_v_main_~y~0_42_31 Int)) (or (and (or (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_42_31 Int)) (not (= v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (or (forall ((aux_div_v_main_~y~0_42_31 Int)) (or (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))) (<= (+ v_main_~y~0_43 v_it_4 1) (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (<= 1 v_it_4))) (not (< v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (not (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))))) (< main_~n~0 (+ aux_mod_v_main_~y~0_42_31 (* (div main_~n~0 4294967296) 4294967296) 1)) (< aux_mod_v_main_~y~0_42_31 0))) (forall ((aux_mod_v_main_~y~0_42_31 Int)) (or (and (or (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_42_31 Int)) (not (= v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (or (forall ((aux_div_v_main_~y~0_42_31 Int)) (or (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))) (<= (+ v_main_~y~0_43 v_it_4 1) (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (<= 1 v_it_4))) (not (< v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (not (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_42_31) (<= (+ aux_mod_v_main_~y~0_42_31 (* (div main_~n~0 4294967296) 4294967296)) main_~n~0)))) (not (< main_~y~0 v_main_~y~0_43)) (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= (+ v_it_4 main_~y~0 1) v_main_~y~0_43) (<= 1 v_it_4)))))) (or (< (div (+ (- 1) (* (- 1) main_~y~0)) (- 4294967296)) (+ (div main_~n~0 4294967296) 2 (div (+ main_~y~0 (* (- 1) main_~n~0)) 4294967296))) (< 0 (mod main_~x~0 4294967296)))) (< 0 (mod main_~y~0 4294967296)))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1988#(or (and (or (not (< 0 (mod main_~x~0 4294967296))) (forall ((v_main_~y~0_43 Int)) (or (and (forall ((aux_mod_v_main_~y~0_42_31 Int)) (or (and (or (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_42_31 Int)) (not (= v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (or (forall ((aux_div_v_main_~y~0_42_31 Int)) (or (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))) (<= (+ v_main_~y~0_43 v_it_4 1) (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (<= 1 v_it_4))) (not (< v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (not (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))))) (< main_~n~0 (+ aux_mod_v_main_~y~0_42_31 (* (div main_~n~0 4294967296) 4294967296) 1)) (< aux_mod_v_main_~y~0_42_31 0))) (forall ((aux_mod_v_main_~y~0_42_31 Int)) (or (and (or (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_42_31 Int)) (not (= v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (or (forall ((aux_div_v_main_~y~0_42_31 Int)) (or (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))) (<= (+ v_main_~y~0_43 v_it_4 1) (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (<= 1 v_it_4))) (not (< v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (not (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_42_31) (<= (+ aux_mod_v_main_~y~0_42_31 (* (div main_~n~0 4294967296) 4294967296)) main_~n~0)))) (not (< main_~y~0 v_main_~y~0_43)) (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= (+ v_it_4 main_~y~0 1) v_main_~y~0_43) (<= 1 v_it_4)))))) (or (< (div (+ (- 1) (* (- 1) main_~y~0)) (- 4294967296)) (+ (div main_~n~0 4294967296) 2 (div (+ main_~y~0 (* (- 1) main_~n~0)) 4294967296))) (< 0 (mod main_~x~0 4294967296)))) (< 0 (mod main_~y~0 4294967296)))} is UNKNOWN [2022-04-07 17:38:15,462 WARN L290 TraceCheckUtils]: 8: Hoare triple {1995#(or (and (or (not (< 0 (mod main_~z~0 4294967296))) (and (forall ((v_main_~y~0_43 Int)) (or (<= v_main_~y~0_43 main_~y~0) (and (forall ((aux_mod_v_main_~y~0_42_31 Int)) (or (and (or (forall ((aux_div_v_main_~x~0_45_31 Int) (aux_mod_aux_mod_v_main_~x~0_45_31_86 Int) (aux_div_aux_mod_v_main_~x~0_45_31_86 Int)) (or (<= (+ aux_mod_aux_mod_v_main_~x~0_45_31_86 (* aux_div_aux_mod_v_main_~x~0_45_31_86 4294967296)) (+ main_~y~0 (* v_main_~y~0_43 4294967295))) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) v_main_~y~0_43) (<= 1 v_it_4) (not (< 0 (mod (+ (* v_it_4 4294967295) v_main_~y~0_43 aux_mod_aux_mod_v_main_~x~0_45_31_86 (* main_~y~0 4294967295)) 4294967296))))) (< aux_mod_aux_mod_v_main_~x~0_45_31_86 0) (<= (+ main_~y~0 (* v_main_~y~0_43 4294967295) 4294967296) (+ aux_mod_aux_mod_v_main_~x~0_45_31_86 (* aux_div_aux_mod_v_main_~x~0_45_31_86 4294967296))) (< 0 aux_mod_aux_mod_v_main_~x~0_45_31_86) (exists ((v_it_2 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_2 4294967295)) 4294967296))) (<= 1 v_it_2) (<= (+ v_it_2 main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295) 1) (+ (* aux_div_v_main_~x~0_45_31 4294967296) aux_mod_aux_mod_v_main_~x~0_45_31_86 (* aux_div_aux_mod_v_main_~x~0_45_31_86 4294967296))))) (<= (+ (* aux_div_v_main_~x~0_45_31 4294967296) aux_mod_aux_mod_v_main_~x~0_45_31_86 (* aux_div_aux_mod_v_main_~x~0_45_31_86 4294967296)) (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295))))) (not (= (mod (+ (* v_main_~y~0_43 4294967295) aux_mod_v_main_~y~0_42_31) 4294967296) 0))) (forall ((aux_div_v_main_~x~0_45_31 Int) (aux_mod_aux_mod_v_main_~x~0_45_31_86 Int) (aux_div_aux_mod_v_main_~x~0_45_31_86 Int) (aux_div_v_main_~y~0_42_31 Int)) (or (<= 4294967296 aux_mod_aux_mod_v_main_~x~0_45_31_86) (<= (+ aux_mod_aux_mod_v_main_~x~0_45_31_86 (* aux_div_aux_mod_v_main_~x~0_45_31_86 4294967296)) (+ main_~y~0 (* v_main_~y~0_43 4294967295))) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) v_main_~y~0_43) (<= 1 v_it_4) (not (< 0 (mod (+ (* v_it_4 4294967295) v_main_~y~0_43 aux_mod_aux_mod_v_main_~x~0_45_31_86 (* main_~y~0 4294967295)) 4294967296))))) (<= (+ main_~y~0 (* v_main_~y~0_43 4294967295) 4294967296) (+ aux_mod_aux_mod_v_main_~x~0_45_31_86 (* aux_div_aux_mod_v_main_~x~0_45_31_86 4294967296))) (exists ((v_it_2 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_2 4294967295)) 4294967296))) (<= 1 v_it_2) (<= (+ v_it_2 main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295) 1) (+ (* aux_div_v_main_~x~0_45_31 4294967296) aux_mod_aux_mod_v_main_~x~0_45_31_86 (* aux_div_aux_mod_v_main_~x~0_45_31_86 4294967296))))) (<= aux_mod_aux_mod_v_main_~x~0_45_31_86 0) (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) aux_mod_aux_mod_v_main_~x~0_45_31_86) 4294967296))) (<= (+ v_main_~y~0_43 v_it_4 1) (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (<= 1 v_it_4))) (<= (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31) v_main_~y~0_43) (<= (+ (* aux_div_v_main_~x~0_45_31 4294967296) aux_mod_aux_mod_v_main_~x~0_45_31_86 (* aux_div_aux_mod_v_main_~x~0_45_31_86 4294967296)) (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)))))) (< main_~n~0 (+ aux_mod_v_main_~y~0_42_31 (* (div main_~n~0 4294967296) 4294967296) 1)) (< aux_mod_v_main_~y~0_42_31 0))) (forall ((aux_mod_v_main_~y~0_42_31 Int)) (or (and (or (forall ((aux_div_v_main_~x~0_45_31 Int) (aux_mod_aux_mod_v_main_~x~0_45_31_86 Int) (aux_div_aux_mod_v_main_~x~0_45_31_86 Int)) (or (<= (+ aux_mod_aux_mod_v_main_~x~0_45_31_86 (* aux_div_aux_mod_v_main_~x~0_45_31_86 4294967296)) (+ main_~y~0 (* v_main_~y~0_43 4294967295))) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) v_main_~y~0_43) (<= 1 v_it_4) (not (< 0 (mod (+ (* v_it_4 4294967295) v_main_~y~0_43 aux_mod_aux_mod_v_main_~x~0_45_31_86 (* main_~y~0 4294967295)) 4294967296))))) (< aux_mod_aux_mod_v_main_~x~0_45_31_86 0) (<= (+ main_~y~0 (* v_main_~y~0_43 4294967295) 4294967296) (+ aux_mod_aux_mod_v_main_~x~0_45_31_86 (* aux_div_aux_mod_v_main_~x~0_45_31_86 4294967296))) (< 0 aux_mod_aux_mod_v_main_~x~0_45_31_86) (exists ((v_it_2 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_2 4294967295)) 4294967296))) (<= 1 v_it_2) (<= (+ v_it_2 main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295) 1) (+ (* aux_div_v_main_~x~0_45_31 4294967296) aux_mod_aux_mod_v_main_~x~0_45_31_86 (* aux_div_aux_mod_v_main_~x~0_45_31_86 4294967296))))) (<= (+ (* aux_div_v_main_~x~0_45_31 4294967296) aux_mod_aux_mod_v_main_~x~0_45_31_86 (* aux_div_aux_mod_v_main_~x~0_45_31_86 4294967296)) (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295))))) (not (= (mod (+ (* v_main_~y~0_43 4294967295) aux_mod_v_main_~y~0_42_31) 4294967296) 0))) (forall ((aux_div_v_main_~x~0_45_31 Int) (aux_mod_aux_mod_v_main_~x~0_45_31_86 Int) (aux_div_aux_mod_v_main_~x~0_45_31_86 Int) (aux_div_v_main_~y~0_42_31 Int)) (or (<= 4294967296 aux_mod_aux_mod_v_main_~x~0_45_31_86) (<= (+ aux_mod_aux_mod_v_main_~x~0_45_31_86 (* aux_div_aux_mod_v_main_~x~0_45_31_86 4294967296)) (+ main_~y~0 (* v_main_~y~0_43 4294967295))) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) v_main_~y~0_43) (<= 1 v_it_4) (not (< 0 (mod (+ (* v_it_4 4294967295) v_main_~y~0_43 aux_mod_aux_mod_v_main_~x~0_45_31_86 (* main_~y~0 4294967295)) 4294967296))))) (<= (+ main_~y~0 (* v_main_~y~0_43 4294967295) 4294967296) (+ aux_mod_aux_mod_v_main_~x~0_45_31_86 (* aux_div_aux_mod_v_main_~x~0_45_31_86 4294967296))) (exists ((v_it_2 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_2 4294967295)) 4294967296))) (<= 1 v_it_2) (<= (+ v_it_2 main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295) 1) (+ (* aux_div_v_main_~x~0_45_31 4294967296) aux_mod_aux_mod_v_main_~x~0_45_31_86 (* aux_div_aux_mod_v_main_~x~0_45_31_86 4294967296))))) (<= aux_mod_aux_mod_v_main_~x~0_45_31_86 0) (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) aux_mod_aux_mod_v_main_~x~0_45_31_86) 4294967296))) (<= (+ v_main_~y~0_43 v_it_4 1) (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (<= 1 v_it_4))) (<= (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31) v_main_~y~0_43) (<= (+ (* aux_div_v_main_~x~0_45_31 4294967296) aux_mod_aux_mod_v_main_~x~0_45_31_86 (* aux_div_aux_mod_v_main_~x~0_45_31_86 4294967296)) (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)))))) (<= 4294967296 aux_mod_v_main_~y~0_42_31) (<= (+ aux_mod_v_main_~y~0_42_31 (* (div main_~n~0 4294967296) 4294967296)) main_~n~0)))))) (or (forall ((aux_mod_v_main_~x~0_45_31 Int) (aux_div_v_main_~x~0_45_31 Int)) (or (<= (+ aux_mod_v_main_~x~0_45_31 (* aux_div_v_main_~x~0_45_31 4294967296)) main_~x~0) (exists ((v_it_2 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_2 4294967295)) 4294967296))) (<= 1 v_it_2) (<= (+ v_it_2 main_~x~0 1) (+ aux_mod_v_main_~x~0_45_31 (* aux_div_v_main_~x~0_45_31 4294967296))))) (< 0 aux_mod_v_main_~x~0_45_31) (< aux_mod_v_main_~x~0_45_31 0))) (< (div (+ (- 1) (* (- 1) main_~y~0)) (- 4294967296)) (+ (div main_~n~0 4294967296) 2 (div (+ main_~y~0 (* (- 1) main_~n~0)) 4294967296)))))) (or (< 0 (mod main_~z~0 4294967296)) (and (or (not (< 0 (mod main_~x~0 4294967296))) (forall ((v_main_~y~0_43 Int)) (or (and (forall ((aux_mod_v_main_~y~0_42_31 Int)) (or (and (or (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_42_31 Int)) (not (= v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (or (forall ((aux_div_v_main_~y~0_42_31 Int)) (or (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))) (<= (+ v_main_~y~0_43 v_it_4 1) (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (<= 1 v_it_4))) (not (< v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (not (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))))) (< main_~n~0 (+ aux_mod_v_main_~y~0_42_31 (* (div main_~n~0 4294967296) 4294967296) 1)) (< aux_mod_v_main_~y~0_42_31 0))) (forall ((aux_mod_v_main_~y~0_42_31 Int)) (or (and (or (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_42_31 Int)) (not (= v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (or (forall ((aux_div_v_main_~y~0_42_31 Int)) (or (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))) (<= (+ v_main_~y~0_43 v_it_4 1) (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (<= 1 v_it_4))) (not (< v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (not (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_42_31) (<= (+ aux_mod_v_main_~y~0_42_31 (* (div main_~n~0 4294967296) 4294967296)) main_~n~0)))) (not (< main_~y~0 v_main_~y~0_43)) (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= (+ v_it_4 main_~y~0 1) v_main_~y~0_43) (<= 1 v_it_4)))))) (or (< (div (+ (- 1) (* (- 1) main_~y~0)) (- 4294967296)) (+ (div main_~n~0 4294967296) 2 (div (+ main_~y~0 (* (- 1) main_~n~0)) 4294967296))) (< 0 (mod main_~x~0 4294967296)))))) (< 0 (mod main_~y~0 4294967296)))} [87] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_7 4294967296))) (or (and (= v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_7 v_main_~z~0_6) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|) (<= .cse0 0)) (and (< v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_6 (+ (* (- 1) v_main_~x~0_8) v_main_~x~0_9 v_main_~z~0_7)) (forall ((v_it_2 Int)) (or (not (<= 1 v_it_2)) (not (<= (+ v_main_~x~0_9 v_it_2 1) v_main_~x~0_8)) (< 0 (mod (+ v_main_~z~0_7 (* v_it_2 4294967295)) 4294967296)))) (< 0 .cse0)))) InVars {main_~x~0=v_main_~x~0_9, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_8, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_6, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {1988#(or (and (or (not (< 0 (mod main_~x~0 4294967296))) (forall ((v_main_~y~0_43 Int)) (or (and (forall ((aux_mod_v_main_~y~0_42_31 Int)) (or (and (or (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_42_31 Int)) (not (= v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (or (forall ((aux_div_v_main_~y~0_42_31 Int)) (or (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))) (<= (+ v_main_~y~0_43 v_it_4 1) (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (<= 1 v_it_4))) (not (< v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (not (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))))) (< main_~n~0 (+ aux_mod_v_main_~y~0_42_31 (* (div main_~n~0 4294967296) 4294967296) 1)) (< aux_mod_v_main_~y~0_42_31 0))) (forall ((aux_mod_v_main_~y~0_42_31 Int)) (or (and (or (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_42_31 Int)) (not (= v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (or (forall ((aux_div_v_main_~y~0_42_31 Int)) (or (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))) (<= (+ v_main_~y~0_43 v_it_4 1) (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (<= 1 v_it_4))) (not (< v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (not (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_42_31) (<= (+ aux_mod_v_main_~y~0_42_31 (* (div main_~n~0 4294967296) 4294967296)) main_~n~0)))) (not (< main_~y~0 v_main_~y~0_43)) (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= (+ v_it_4 main_~y~0 1) v_main_~y~0_43) (<= 1 v_it_4)))))) (or (< (div (+ (- 1) (* (- 1) main_~y~0)) (- 4294967296)) (+ (div main_~n~0 4294967296) 2 (div (+ main_~y~0 (* (- 1) main_~n~0)) 4294967296))) (< 0 (mod main_~x~0 4294967296)))) (< 0 (mod main_~y~0 4294967296)))} is UNKNOWN [2022-04-07 17:38:17,503 WARN L290 TraceCheckUtils]: 7: Hoare triple {1988#(or (and (or (not (< 0 (mod main_~x~0 4294967296))) (forall ((v_main_~y~0_43 Int)) (or (and (forall ((aux_mod_v_main_~y~0_42_31 Int)) (or (and (or (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_42_31 Int)) (not (= v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (or (forall ((aux_div_v_main_~y~0_42_31 Int)) (or (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))) (<= (+ v_main_~y~0_43 v_it_4 1) (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (<= 1 v_it_4))) (not (< v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (not (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))))) (< main_~n~0 (+ aux_mod_v_main_~y~0_42_31 (* (div main_~n~0 4294967296) 4294967296) 1)) (< aux_mod_v_main_~y~0_42_31 0))) (forall ((aux_mod_v_main_~y~0_42_31 Int)) (or (and (or (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_42_31 Int)) (not (= v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (or (forall ((aux_div_v_main_~y~0_42_31 Int)) (or (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))) (<= (+ v_main_~y~0_43 v_it_4 1) (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (<= 1 v_it_4))) (not (< v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (not (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_42_31) (<= (+ aux_mod_v_main_~y~0_42_31 (* (div main_~n~0 4294967296) 4294967296)) main_~n~0)))) (not (< main_~y~0 v_main_~y~0_43)) (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= (+ v_it_4 main_~y~0 1) v_main_~y~0_43) (<= 1 v_it_4)))))) (or (< (div (+ (- 1) (* (- 1) main_~y~0)) (- 4294967296)) (+ (div main_~n~0 4294967296) 2 (div (+ main_~y~0 (* (- 1) main_~n~0)) 4294967296))) (< 0 (mod main_~x~0 4294967296)))) (< 0 (mod main_~y~0 4294967296)))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1995#(or (and (or (not (< 0 (mod main_~z~0 4294967296))) (and (forall ((v_main_~y~0_43 Int)) (or (<= v_main_~y~0_43 main_~y~0) (and (forall ((aux_mod_v_main_~y~0_42_31 Int)) (or (and (or (forall ((aux_div_v_main_~x~0_45_31 Int) (aux_mod_aux_mod_v_main_~x~0_45_31_86 Int) (aux_div_aux_mod_v_main_~x~0_45_31_86 Int)) (or (<= (+ aux_mod_aux_mod_v_main_~x~0_45_31_86 (* aux_div_aux_mod_v_main_~x~0_45_31_86 4294967296)) (+ main_~y~0 (* v_main_~y~0_43 4294967295))) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) v_main_~y~0_43) (<= 1 v_it_4) (not (< 0 (mod (+ (* v_it_4 4294967295) v_main_~y~0_43 aux_mod_aux_mod_v_main_~x~0_45_31_86 (* main_~y~0 4294967295)) 4294967296))))) (< aux_mod_aux_mod_v_main_~x~0_45_31_86 0) (<= (+ main_~y~0 (* v_main_~y~0_43 4294967295) 4294967296) (+ aux_mod_aux_mod_v_main_~x~0_45_31_86 (* aux_div_aux_mod_v_main_~x~0_45_31_86 4294967296))) (< 0 aux_mod_aux_mod_v_main_~x~0_45_31_86) (exists ((v_it_2 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_2 4294967295)) 4294967296))) (<= 1 v_it_2) (<= (+ v_it_2 main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295) 1) (+ (* aux_div_v_main_~x~0_45_31 4294967296) aux_mod_aux_mod_v_main_~x~0_45_31_86 (* aux_div_aux_mod_v_main_~x~0_45_31_86 4294967296))))) (<= (+ (* aux_div_v_main_~x~0_45_31 4294967296) aux_mod_aux_mod_v_main_~x~0_45_31_86 (* aux_div_aux_mod_v_main_~x~0_45_31_86 4294967296)) (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295))))) (not (= (mod (+ (* v_main_~y~0_43 4294967295) aux_mod_v_main_~y~0_42_31) 4294967296) 0))) (forall ((aux_div_v_main_~x~0_45_31 Int) (aux_mod_aux_mod_v_main_~x~0_45_31_86 Int) (aux_div_aux_mod_v_main_~x~0_45_31_86 Int) (aux_div_v_main_~y~0_42_31 Int)) (or (<= 4294967296 aux_mod_aux_mod_v_main_~x~0_45_31_86) (<= (+ aux_mod_aux_mod_v_main_~x~0_45_31_86 (* aux_div_aux_mod_v_main_~x~0_45_31_86 4294967296)) (+ main_~y~0 (* v_main_~y~0_43 4294967295))) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) v_main_~y~0_43) (<= 1 v_it_4) (not (< 0 (mod (+ (* v_it_4 4294967295) v_main_~y~0_43 aux_mod_aux_mod_v_main_~x~0_45_31_86 (* main_~y~0 4294967295)) 4294967296))))) (<= (+ main_~y~0 (* v_main_~y~0_43 4294967295) 4294967296) (+ aux_mod_aux_mod_v_main_~x~0_45_31_86 (* aux_div_aux_mod_v_main_~x~0_45_31_86 4294967296))) (exists ((v_it_2 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_2 4294967295)) 4294967296))) (<= 1 v_it_2) (<= (+ v_it_2 main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295) 1) (+ (* aux_div_v_main_~x~0_45_31 4294967296) aux_mod_aux_mod_v_main_~x~0_45_31_86 (* aux_div_aux_mod_v_main_~x~0_45_31_86 4294967296))))) (<= aux_mod_aux_mod_v_main_~x~0_45_31_86 0) (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) aux_mod_aux_mod_v_main_~x~0_45_31_86) 4294967296))) (<= (+ v_main_~y~0_43 v_it_4 1) (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (<= 1 v_it_4))) (<= (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31) v_main_~y~0_43) (<= (+ (* aux_div_v_main_~x~0_45_31 4294967296) aux_mod_aux_mod_v_main_~x~0_45_31_86 (* aux_div_aux_mod_v_main_~x~0_45_31_86 4294967296)) (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)))))) (< main_~n~0 (+ aux_mod_v_main_~y~0_42_31 (* (div main_~n~0 4294967296) 4294967296) 1)) (< aux_mod_v_main_~y~0_42_31 0))) (forall ((aux_mod_v_main_~y~0_42_31 Int)) (or (and (or (forall ((aux_div_v_main_~x~0_45_31 Int) (aux_mod_aux_mod_v_main_~x~0_45_31_86 Int) (aux_div_aux_mod_v_main_~x~0_45_31_86 Int)) (or (<= (+ aux_mod_aux_mod_v_main_~x~0_45_31_86 (* aux_div_aux_mod_v_main_~x~0_45_31_86 4294967296)) (+ main_~y~0 (* v_main_~y~0_43 4294967295))) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) v_main_~y~0_43) (<= 1 v_it_4) (not (< 0 (mod (+ (* v_it_4 4294967295) v_main_~y~0_43 aux_mod_aux_mod_v_main_~x~0_45_31_86 (* main_~y~0 4294967295)) 4294967296))))) (< aux_mod_aux_mod_v_main_~x~0_45_31_86 0) (<= (+ main_~y~0 (* v_main_~y~0_43 4294967295) 4294967296) (+ aux_mod_aux_mod_v_main_~x~0_45_31_86 (* aux_div_aux_mod_v_main_~x~0_45_31_86 4294967296))) (< 0 aux_mod_aux_mod_v_main_~x~0_45_31_86) (exists ((v_it_2 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_2 4294967295)) 4294967296))) (<= 1 v_it_2) (<= (+ v_it_2 main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295) 1) (+ (* aux_div_v_main_~x~0_45_31 4294967296) aux_mod_aux_mod_v_main_~x~0_45_31_86 (* aux_div_aux_mod_v_main_~x~0_45_31_86 4294967296))))) (<= (+ (* aux_div_v_main_~x~0_45_31 4294967296) aux_mod_aux_mod_v_main_~x~0_45_31_86 (* aux_div_aux_mod_v_main_~x~0_45_31_86 4294967296)) (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295))))) (not (= (mod (+ (* v_main_~y~0_43 4294967295) aux_mod_v_main_~y~0_42_31) 4294967296) 0))) (forall ((aux_div_v_main_~x~0_45_31 Int) (aux_mod_aux_mod_v_main_~x~0_45_31_86 Int) (aux_div_aux_mod_v_main_~x~0_45_31_86 Int) (aux_div_v_main_~y~0_42_31 Int)) (or (<= 4294967296 aux_mod_aux_mod_v_main_~x~0_45_31_86) (<= (+ aux_mod_aux_mod_v_main_~x~0_45_31_86 (* aux_div_aux_mod_v_main_~x~0_45_31_86 4294967296)) (+ main_~y~0 (* v_main_~y~0_43 4294967295))) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) v_main_~y~0_43) (<= 1 v_it_4) (not (< 0 (mod (+ (* v_it_4 4294967295) v_main_~y~0_43 aux_mod_aux_mod_v_main_~x~0_45_31_86 (* main_~y~0 4294967295)) 4294967296))))) (<= (+ main_~y~0 (* v_main_~y~0_43 4294967295) 4294967296) (+ aux_mod_aux_mod_v_main_~x~0_45_31_86 (* aux_div_aux_mod_v_main_~x~0_45_31_86 4294967296))) (exists ((v_it_2 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_2 4294967295)) 4294967296))) (<= 1 v_it_2) (<= (+ v_it_2 main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295) 1) (+ (* aux_div_v_main_~x~0_45_31 4294967296) aux_mod_aux_mod_v_main_~x~0_45_31_86 (* aux_div_aux_mod_v_main_~x~0_45_31_86 4294967296))))) (<= aux_mod_aux_mod_v_main_~x~0_45_31_86 0) (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) aux_mod_aux_mod_v_main_~x~0_45_31_86) 4294967296))) (<= (+ v_main_~y~0_43 v_it_4 1) (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (<= 1 v_it_4))) (<= (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31) v_main_~y~0_43) (<= (+ (* aux_div_v_main_~x~0_45_31 4294967296) aux_mod_aux_mod_v_main_~x~0_45_31_86 (* aux_div_aux_mod_v_main_~x~0_45_31_86 4294967296)) (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)))))) (<= 4294967296 aux_mod_v_main_~y~0_42_31) (<= (+ aux_mod_v_main_~y~0_42_31 (* (div main_~n~0 4294967296) 4294967296)) main_~n~0)))))) (or (forall ((aux_mod_v_main_~x~0_45_31 Int) (aux_div_v_main_~x~0_45_31 Int)) (or (<= (+ aux_mod_v_main_~x~0_45_31 (* aux_div_v_main_~x~0_45_31 4294967296)) main_~x~0) (exists ((v_it_2 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_2 4294967295)) 4294967296))) (<= 1 v_it_2) (<= (+ v_it_2 main_~x~0 1) (+ aux_mod_v_main_~x~0_45_31 (* aux_div_v_main_~x~0_45_31 4294967296))))) (< 0 aux_mod_v_main_~x~0_45_31) (< aux_mod_v_main_~x~0_45_31 0))) (< (div (+ (- 1) (* (- 1) main_~y~0)) (- 4294967296)) (+ (div main_~n~0 4294967296) 2 (div (+ main_~y~0 (* (- 1) main_~n~0)) 4294967296)))))) (or (< 0 (mod main_~z~0 4294967296)) (and (or (not (< 0 (mod main_~x~0 4294967296))) (forall ((v_main_~y~0_43 Int)) (or (and (forall ((aux_mod_v_main_~y~0_42_31 Int)) (or (and (or (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_42_31 Int)) (not (= v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (or (forall ((aux_div_v_main_~y~0_42_31 Int)) (or (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))) (<= (+ v_main_~y~0_43 v_it_4 1) (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (<= 1 v_it_4))) (not (< v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (not (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))))) (< main_~n~0 (+ aux_mod_v_main_~y~0_42_31 (* (div main_~n~0 4294967296) 4294967296) 1)) (< aux_mod_v_main_~y~0_42_31 0))) (forall ((aux_mod_v_main_~y~0_42_31 Int)) (or (and (or (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_42_31 Int)) (not (= v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (or (forall ((aux_div_v_main_~y~0_42_31 Int)) (or (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))) (<= (+ v_main_~y~0_43 v_it_4 1) (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (<= 1 v_it_4))) (not (< v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (not (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_42_31) (<= (+ aux_mod_v_main_~y~0_42_31 (* (div main_~n~0 4294967296) 4294967296)) main_~n~0)))) (not (< main_~y~0 v_main_~y~0_43)) (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= (+ v_it_4 main_~y~0 1) v_main_~y~0_43) (<= 1 v_it_4)))))) (or (< (div (+ (- 1) (* (- 1) main_~y~0)) (- 4294967296)) (+ (div main_~n~0 4294967296) 2 (div (+ main_~y~0 (* (- 1) main_~n~0)) 4294967296))) (< 0 (mod main_~x~0 4294967296)))))) (< 0 (mod main_~y~0 4294967296)))} is UNKNOWN [2022-04-07 17:38:17,505 INFO L290 TraceCheckUtils]: 6: Hoare triple {2002#(or (< (div (+ (- 1) (* (- 1) main_~y~0)) (- 4294967296)) (+ (div main_~n~0 4294967296) 2 (div (+ main_~y~0 (* (- 1) main_~n~0)) 4294967296))) (< 0 (mod main_~x~0 4294967296)) (< 0 (mod main_~y~0 4294967296)))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1988#(or (and (or (not (< 0 (mod main_~x~0 4294967296))) (forall ((v_main_~y~0_43 Int)) (or (and (forall ((aux_mod_v_main_~y~0_42_31 Int)) (or (and (or (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_42_31 Int)) (not (= v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (or (forall ((aux_div_v_main_~y~0_42_31 Int)) (or (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))) (<= (+ v_main_~y~0_43 v_it_4 1) (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (<= 1 v_it_4))) (not (< v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (not (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))))) (< main_~n~0 (+ aux_mod_v_main_~y~0_42_31 (* (div main_~n~0 4294967296) 4294967296) 1)) (< aux_mod_v_main_~y~0_42_31 0))) (forall ((aux_mod_v_main_~y~0_42_31 Int)) (or (and (or (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_42_31 Int)) (not (= v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (or (forall ((aux_div_v_main_~y~0_42_31 Int)) (or (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))) (<= (+ v_main_~y~0_43 v_it_4 1) (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (<= 1 v_it_4))) (not (< v_main_~y~0_43 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31))))) (not (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_43 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_42_31) (<= (+ aux_mod_v_main_~y~0_42_31 (* (div main_~n~0 4294967296) 4294967296)) main_~n~0)))) (not (< main_~y~0 v_main_~y~0_43)) (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= (+ v_it_4 main_~y~0 1) v_main_~y~0_43) (<= 1 v_it_4)))))) (or (< (div (+ (- 1) (* (- 1) main_~y~0)) (- 4294967296)) (+ (div main_~n~0 4294967296) 2 (div (+ main_~y~0 (* (- 1) main_~n~0)) 4294967296))) (< 0 (mod main_~x~0 4294967296)))) (< 0 (mod main_~y~0 4294967296)))} is VALID [2022-04-07 17:38:17,520 INFO L290 TraceCheckUtils]: 5: Hoare triple {1894#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {2002#(or (< (div (+ (- 1) (* (- 1) main_~y~0)) (- 4294967296)) (+ (div main_~n~0 4294967296) 2 (div (+ main_~y~0 (* (- 1) main_~n~0)) 4294967296))) (< 0 (mod main_~x~0 4294967296)) (< 0 (mod main_~y~0 4294967296)))} is VALID [2022-04-07 17:38:17,520 INFO L272 TraceCheckUtils]: 4: Hoare triple {1894#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1894#true} is VALID [2022-04-07 17:38:17,520 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1894#true} {1894#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1894#true} is VALID [2022-04-07 17:38:17,520 INFO L290 TraceCheckUtils]: 2: Hoare triple {1894#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1894#true} is VALID [2022-04-07 17:38:17,521 INFO L290 TraceCheckUtils]: 1: Hoare triple {1894#true} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1894#true} is VALID [2022-04-07 17:38:17,521 INFO L272 TraceCheckUtils]: 0: Hoare triple {1894#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1894#true} is VALID [2022-04-07 17:38:17,521 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 2 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 17:38:17,521 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1262561883] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-07 17:38:17,521 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-07 17:38:17,521 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 8, 10] total 19 [2022-04-07 17:38:17,521 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [661309898] [2022-04-07 17:38:17,522 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-07 17:38:17,522 INFO L78 Accepts]: Start accepts. Automaton has has 19 states, 19 states have (on average 1.5263157894736843) internal successors, (29), 16 states have internal predecessors, (29), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-07 17:38:17,522 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 17:38:17,522 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 19 states, 19 states have (on average 1.5263157894736843) internal successors, (29), 16 states have internal predecessors, (29), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:38:29,773 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 36 edges. 30 inductive. 0 not inductive. 6 times theorem prover too weak to decide inductivity. [2022-04-07 17:38:29,774 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 19 states [2022-04-07 17:38:29,774 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 17:38:29,774 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2022-04-07 17:38:29,774 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=76, Invalid=240, Unknown=26, NotChecked=0, Total=342 [2022-04-07 17:38:29,774 INFO L87 Difference]: Start difference. First operand 32 states and 45 transitions. Second operand has 19 states, 19 states have (on average 1.5263157894736843) internal successors, (29), 16 states have internal predecessors, (29), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:38:46,642 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:38:46,642 INFO L93 Difference]: Finished difference Result 44 states and 62 transitions. [2022-04-07 17:38:46,642 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-04-07 17:38:46,642 INFO L78 Accepts]: Start accepts. Automaton has has 19 states, 19 states have (on average 1.5263157894736843) internal successors, (29), 16 states have internal predecessors, (29), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-07 17:38:46,642 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 17:38:46,643 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19 states, 19 states have (on average 1.5263157894736843) internal successors, (29), 16 states have internal predecessors, (29), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:38:46,643 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 39 transitions. [2022-04-07 17:38:46,643 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19 states, 19 states have (on average 1.5263157894736843) internal successors, (29), 16 states have internal predecessors, (29), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:38:46,644 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 39 transitions. [2022-04-07 17:38:46,644 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 9 states and 39 transitions. [2022-04-07 17:38:46,682 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 39 edges. 39 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 17:38:46,682 INFO L225 Difference]: With dead ends: 44 [2022-04-07 17:38:46,682 INFO L226 Difference]: Without dead ends: 38 [2022-04-07 17:38:46,683 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 54 GetRequests, 25 SyntacticMatches, 7 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 154 ImplicationChecksByTransitivity, 142.4s TimeCoverageRelationStatistics Valid=126, Invalid=395, Unknown=31, NotChecked=0, Total=552 [2022-04-07 17:38:46,683 INFO L913 BasicCegarLoop]: 12 mSDtfsCounter, 30 mSDsluCounter, 44 mSDsCounter, 0 mSdLazyCounter, 65 mSolverCounterSat, 13 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 30 SdHoareTripleChecker+Valid, 56 SdHoareTripleChecker+Invalid, 119 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 13 IncrementalHoareTripleChecker+Valid, 65 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 41 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-07 17:38:46,683 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [30 Valid, 56 Invalid, 119 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [13 Valid, 65 Invalid, 0 Unknown, 41 Unchecked, 0.1s Time] [2022-04-07 17:38:46,684 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38 states. [2022-04-07 17:38:46,685 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38 to 34. [2022-04-07 17:38:46,690 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 17:38:46,692 INFO L82 GeneralOperation]: Start isEquivalent. First operand 38 states. Second operand has 34 states, 29 states have (on average 1.5172413793103448) internal successors, (44), 29 states have internal predecessors, (44), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:38:46,692 INFO L74 IsIncluded]: Start isIncluded. First operand 38 states. Second operand has 34 states, 29 states have (on average 1.5172413793103448) internal successors, (44), 29 states have internal predecessors, (44), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:38:46,697 INFO L87 Difference]: Start difference. First operand 38 states. Second operand has 34 states, 29 states have (on average 1.5172413793103448) internal successors, (44), 29 states have internal predecessors, (44), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:38:46,698 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:38:46,698 INFO L93 Difference]: Finished difference Result 38 states and 55 transitions. [2022-04-07 17:38:46,698 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 55 transitions. [2022-04-07 17:38:46,699 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:38:46,699 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:38:46,699 INFO L74 IsIncluded]: Start isIncluded. First operand has 34 states, 29 states have (on average 1.5172413793103448) internal successors, (44), 29 states have internal predecessors, (44), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 38 states. [2022-04-07 17:38:46,699 INFO L87 Difference]: Start difference. First operand has 34 states, 29 states have (on average 1.5172413793103448) internal successors, (44), 29 states have internal predecessors, (44), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 38 states. [2022-04-07 17:38:46,700 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:38:46,700 INFO L93 Difference]: Finished difference Result 38 states and 55 transitions. [2022-04-07 17:38:46,700 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 55 transitions. [2022-04-07 17:38:46,700 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:38:46,700 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:38:46,701 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 17:38:46,701 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 17:38:46,701 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34 states, 29 states have (on average 1.5172413793103448) internal successors, (44), 29 states have internal predecessors, (44), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:38:46,701 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 48 transitions. [2022-04-07 17:38:46,701 INFO L78 Accepts]: Start accepts. Automaton has 34 states and 48 transitions. Word has length 18 [2022-04-07 17:38:46,701 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 17:38:46,701 INFO L478 AbstractCegarLoop]: Abstraction has 34 states and 48 transitions. [2022-04-07 17:38:46,702 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 19 states, 19 states have (on average 1.5263157894736843) internal successors, (29), 16 states have internal predecessors, (29), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:38:46,702 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 48 transitions. [2022-04-07 17:38:46,703 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2022-04-07 17:38:46,703 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 17:38:46,704 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 17:38:46,723 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Forceful destruction successful, exit code 0 [2022-04-07 17:38:46,915 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable9 [2022-04-07 17:38:46,915 INFO L403 AbstractCegarLoop]: === Iteration 11 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 17:38:46,916 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 17:38:46,916 INFO L85 PathProgramCache]: Analyzing trace with hash -1481938624, now seen corresponding path program 1 times [2022-04-07 17:38:46,916 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 17:38:46,916 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [33931666] [2022-04-07 17:38:46,916 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:38:46,916 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 17:38:46,931 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_2.0))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-07 17:38:46,932 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.1))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-07 17:38:46,933 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.2))) (+ .cse0 main_~x~0_8 (* (- 4294967296) (div (+ .cse0 main_~x~0_8) 4294967296)))) 0)) [2022-04-07 17:38:46,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:38:46,950 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_2.4))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-07 17:38:46,954 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.5))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-07 17:38:46,957 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.6))) (+ .cse0 main_~x~0_8 (* (- 4294967296) (div (+ .cse0 main_~x~0_8) 4294967296)))) 0)) [2022-04-07 17:38:47,182 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 17:38:47,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:38:47,192 INFO L290 TraceCheckUtils]: 0: Hoare triple {2201#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2188#true} is VALID [2022-04-07 17:38:47,192 INFO L290 TraceCheckUtils]: 1: Hoare triple {2188#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2188#true} is VALID [2022-04-07 17:38:47,192 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {2188#true} {2188#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2188#true} is VALID [2022-04-07 17:38:47,193 INFO L272 TraceCheckUtils]: 0: Hoare triple {2188#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2201#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 17:38:47,193 INFO L290 TraceCheckUtils]: 1: Hoare triple {2201#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2188#true} is VALID [2022-04-07 17:38:47,193 INFO L290 TraceCheckUtils]: 2: Hoare triple {2188#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2188#true} is VALID [2022-04-07 17:38:47,193 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2188#true} {2188#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2188#true} is VALID [2022-04-07 17:38:47,193 INFO L272 TraceCheckUtils]: 4: Hoare triple {2188#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2188#true} is VALID [2022-04-07 17:38:47,193 INFO L290 TraceCheckUtils]: 5: Hoare triple {2188#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {2193#(and (= main_~n~0 main_~x~0) (= main_~y~0 0))} is VALID [2022-04-07 17:38:47,194 INFO L290 TraceCheckUtils]: 6: Hoare triple {2193#(and (= main_~n~0 main_~x~0) (= main_~y~0 0))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {2194#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:38:47,195 INFO L290 TraceCheckUtils]: 7: Hoare triple {2194#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {2195#(and (= main_~z~0 0) (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:38:47,196 INFO L290 TraceCheckUtils]: 8: Hoare triple {2195#(and (= main_~z~0 0) (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [87] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_7 4294967296))) (or (and (= v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_7 v_main_~z~0_6) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|) (<= .cse0 0)) (and (< v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_6 (+ (* (- 1) v_main_~x~0_8) v_main_~x~0_9 v_main_~z~0_7)) (forall ((v_it_2 Int)) (or (not (<= 1 v_it_2)) (not (<= (+ v_main_~x~0_9 v_it_2 1) v_main_~x~0_8)) (< 0 (mod (+ v_main_~z~0_7 (* v_it_2 4294967295)) 4294967296)))) (< 0 .cse0)))) InVars {main_~x~0=v_main_~x~0_9, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_8, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_6, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {2196#(and (= main_~z~0 0) (<= (* (div (+ main_~n~0 4294967295) 4294967296) 4294967296) main_~n~0) (<= (+ main_~z~0 main_~x~0) (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:38:47,197 INFO L290 TraceCheckUtils]: 9: Hoare triple {2196#(and (= main_~z~0 0) (<= (* (div (+ main_~n~0 4294967295) 4294967296) 4294967296) main_~n~0) (<= (+ main_~z~0 main_~x~0) (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {2196#(and (= main_~z~0 0) (<= (* (div (+ main_~n~0 4294967295) 4294967296) 4294967296) main_~n~0) (<= (+ main_~z~0 main_~x~0) (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:38:47,198 INFO L290 TraceCheckUtils]: 10: Hoare triple {2196#(and (= main_~z~0 0) (<= (* (div (+ main_~n~0 4294967295) 4294967296) 4294967296) main_~n~0) (<= (+ main_~z~0 main_~x~0) (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [90] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_4 4294967296))) (or (and (= (+ (* (- 1) v_main_~y~0_3) v_main_~y~0_4 v_main_~z~0_3) v_main_~z~0_2) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_4 (* v_it_3 4294967295)) 4294967296)) (not (<= (+ v_main_~y~0_3 v_it_3 1) v_main_~y~0_4)))) (< v_main_~y~0_3 v_main_~y~0_4)) (and (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= v_main_~y~0_4 v_main_~y~0_3) (<= .cse0 0) (= |v_main_#t~post9_3| |v_main_#t~post9_1|)))) InVars {main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_3, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {2197#(and (<= 0 main_~y~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= (+ (* (div (+ main_~n~0 4294967295 (* (- 1) main_~y~0)) 4294967296) 4294967296) main_~y~0) main_~n~0) (<= main_~y~0 0))} is VALID [2022-04-07 17:38:47,199 INFO L290 TraceCheckUtils]: 11: Hoare triple {2197#(and (<= 0 main_~y~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= (+ (* (div (+ main_~n~0 4294967295 (* (- 1) main_~y~0)) 4294967296) 4294967296) main_~y~0) main_~n~0) (<= main_~y~0 0))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {2197#(and (<= 0 main_~y~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= (+ (* (div (+ main_~n~0 4294967295 (* (- 1) main_~y~0)) 4294967296) 4294967296) main_~y~0) main_~n~0) (<= main_~y~0 0))} is VALID [2022-04-07 17:38:47,201 INFO L290 TraceCheckUtils]: 12: Hoare triple {2197#(and (<= 0 main_~y~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= (+ (* (div (+ main_~n~0 4294967295 (* (- 1) main_~y~0)) 4294967296) 4294967296) main_~y~0) main_~n~0) (<= main_~y~0 0))} [93] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {2198#(and (not (<= (+ (div main_~y~0 4294967296) 1) 0)) (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is VALID [2022-04-07 17:38:47,201 INFO L290 TraceCheckUtils]: 13: Hoare triple {2198#(and (not (<= (+ (div main_~y~0 4294967296) 1) 0)) (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {2198#(and (not (<= (+ (div main_~y~0 4294967296) 1) 0)) (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is VALID [2022-04-07 17:38:47,202 INFO L272 TraceCheckUtils]: 14: Hoare triple {2198#(and (not (<= (+ (div main_~y~0 4294967296) 1) 0)) (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {2199#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-07 17:38:47,203 INFO L290 TraceCheckUtils]: 15: Hoare triple {2199#(not (= |__VERIFIER_assert_#in~cond| 0))} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2200#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-07 17:38:47,203 INFO L290 TraceCheckUtils]: 16: Hoare triple {2200#(not (= __VERIFIER_assert_~cond 0))} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {2189#false} is VALID [2022-04-07 17:38:47,203 INFO L290 TraceCheckUtils]: 17: Hoare triple {2189#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2189#false} is VALID [2022-04-07 17:38:47,203 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 17:38:47,203 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 17:38:47,203 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [33931666] [2022-04-07 17:38:47,204 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [33931666] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 17:38:47,204 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1560083558] [2022-04-07 17:38:47,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:38:47,204 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 17:38:47,204 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 17:38:47,205 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 17:38:47,206 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process