/usr/bin/java -ea -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data --core.log.level.for.class de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=WARN -tc ../../../trunk/examples/toolchains/AutomizerCTransformed.xml -s ../../../trunk/examples/settings/automizer/LoopAccelerationJordanC.epf -i ../../../trunk/examples/svcomp/loops-crafted-1/in-de62.c -------------------------------------------------------------------------------- This is Ultimate 0.2.2-dev-34549b5 [2022-04-07 17:33:40,860 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-04-07 17:33:40,862 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-04-07 17:33:40,907 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... 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[2022-04-07 17:33:40,915 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-04-07 17:33:40,918 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-04-07 17:33:40,919 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-04-07 17:33:40,921 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-04-07 17:33:40,922 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-04-07 17:33:40,926 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-04-07 17:33:40,935 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-04-07 17:33:40,936 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-04-07 17:33:40,937 INFO L181 SettingsManager]: Resetting HornVerifier preferences to default values [2022-04-07 17:33:40,939 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-04-07 17:33:40,940 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-04-07 17:33:40,941 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-04-07 17:33:40,941 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-04-07 17:33:40,943 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2022-04-07 17:33:40,956 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/automizer/LoopAccelerationJordanC.epf [2022-04-07 17:33:40,968 INFO L113 SettingsManager]: Loading preferences was successful [2022-04-07 17:33:40,969 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-04-07 17:33:40,969 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-04-07 17:33:40,970 INFO L138 SettingsManager]: * sizeof long=4 [2022-04-07 17:33:40,970 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-04-07 17:33:40,970 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-04-07 17:33:40,970 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-04-07 17:33:40,970 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-04-07 17:33:40,970 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-04-07 17:33:40,971 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-04-07 17:33:40,971 INFO L138 SettingsManager]: * sizeof long double=12 [2022-04-07 17:33:40,971 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-04-07 17:33:40,971 INFO L138 SettingsManager]: * Use constant arrays=true [2022-04-07 17:33:40,972 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-04-07 17:33:40,972 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-04-07 17:33:40,972 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-04-07 17:33:40,972 INFO L138 SettingsManager]: * To the following directory=./dump/ [2022-04-07 17:33:40,972 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-04-07 17:33:40,972 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-04-07 17:33:40,972 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-04-07 17:33:40,972 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-04-07 17:33:40,973 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-04-07 17:33:40,973 INFO L138 SettingsManager]: * TransformationType=LOOP_ACCELERATION_JORDAN WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.core: Log level for class -> de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=WARN; [2022-04-07 17:33:41,168 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-04-07 17:33:41,187 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-04-07 17:33:41,189 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-04-07 17:33:41,190 INFO L271 PluginConnector]: Initializing CDTParser... [2022-04-07 17:33:41,191 INFO L275 PluginConnector]: CDTParser initialized [2022-04-07 17:33:41,191 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loops-crafted-1/in-de62.c [2022-04-07 17:33:41,239 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c4f587594/5d002cdfcb78436290aba91fd4fb4740/FLAG38f491d3a [2022-04-07 17:33:41,607 INFO L306 CDTParser]: Found 1 translation units. [2022-04-07 17:33:41,607 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/loops-crafted-1/in-de62.c [2022-04-07 17:33:41,614 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c4f587594/5d002cdfcb78436290aba91fd4fb4740/FLAG38f491d3a [2022-04-07 17:33:41,625 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c4f587594/5d002cdfcb78436290aba91fd4fb4740 [2022-04-07 17:33:41,627 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-04-07 17:33:41,628 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2022-04-07 17:33:41,631 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-04-07 17:33:41,631 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-04-07 17:33:41,634 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-04-07 17:33:41,635 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.04 05:33:41" (1/1) ... [2022-04-07 17:33:41,636 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@448b3f3e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 05:33:41, skipping insertion in model container [2022-04-07 17:33:41,636 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.04 05:33:41" (1/1) ... [2022-04-07 17:33:41,641 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-04-07 17:33:41,654 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-04-07 17:33:41,780 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loops-crafted-1/in-de62.c[368,381] [2022-04-07 17:33:41,800 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-04-07 17:33:41,807 INFO L203 MainTranslator]: Completed pre-run [2022-04-07 17:33:41,817 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loops-crafted-1/in-de62.c[368,381] [2022-04-07 17:33:41,822 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-04-07 17:33:41,835 INFO L208 MainTranslator]: Completed translation [2022-04-07 17:33:41,835 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 05:33:41 WrapperNode [2022-04-07 17:33:41,836 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-04-07 17:33:41,836 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-04-07 17:33:41,836 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-04-07 17:33:41,837 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-04-07 17:33:41,845 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 05:33:41" (1/1) ... [2022-04-07 17:33:41,845 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 05:33:41" (1/1) ... [2022-04-07 17:33:41,853 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 05:33:41" (1/1) ... [2022-04-07 17:33:41,853 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 05:33:41" (1/1) ... [2022-04-07 17:33:41,858 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 05:33:41" (1/1) ... [2022-04-07 17:33:41,862 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 05:33:41" (1/1) ... [2022-04-07 17:33:41,863 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 05:33:41" (1/1) ... [2022-04-07 17:33:41,864 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-04-07 17:33:41,866 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-04-07 17:33:41,866 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-04-07 17:33:41,866 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-04-07 17:33:41,867 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 05:33:41" (1/1) ... [2022-04-07 17:33:41,877 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-04-07 17:33:41,886 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 17:33:41,896 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-04-07 17:33:41,907 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-04-07 17:33:41,937 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2022-04-07 17:33:41,938 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-04-07 17:33:41,938 INFO L138 BoogieDeclarations]: Found implementation of procedure reach_error [2022-04-07 17:33:41,938 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2022-04-07 17:33:41,938 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2022-04-07 17:33:41,939 INFO L130 BoogieDeclarations]: Found specification of procedure abort [2022-04-07 17:33:41,939 INFO L130 BoogieDeclarations]: Found specification of procedure __assert_fail [2022-04-07 17:33:41,939 INFO L130 BoogieDeclarations]: Found specification of procedure reach_error [2022-04-07 17:33:41,939 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-04-07 17:33:41,939 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_uint [2022-04-07 17:33:41,940 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2022-04-07 17:33:41,940 INFO L130 BoogieDeclarations]: Found specification of procedure main [2022-04-07 17:33:41,940 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2022-04-07 17:33:41,940 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-04-07 17:33:41,941 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-04-07 17:33:41,943 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-04-07 17:33:41,943 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-04-07 17:33:41,943 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-04-07 17:33:41,991 INFO L234 CfgBuilder]: Building ICFG [2022-04-07 17:33:41,992 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-04-07 17:33:42,171 INFO L275 CfgBuilder]: Performing block encoding [2022-04-07 17:33:42,176 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-04-07 17:33:42,176 INFO L299 CfgBuilder]: Removed 6 assume(true) statements. [2022-04-07 17:33:42,177 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.04 05:33:42 BoogieIcfgContainer [2022-04-07 17:33:42,178 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-04-07 17:33:42,178 INFO L113 PluginConnector]: ------------------------IcfgTransformer---------------------------- [2022-04-07 17:33:42,178 INFO L271 PluginConnector]: Initializing IcfgTransformer... [2022-04-07 17:33:42,181 INFO L275 PluginConnector]: IcfgTransformer initialized [2022-04-07 17:33:42,200 INFO L185 PluginConnector]: Executing the observer IcfgTransformationObserver from plugin IcfgTransformer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.04 05:33:42" (1/1) ... [2022-04-07 17:33:42,205 INFO L168 ansformationObserver]: Applying ICFG transformation LOOP_ACCELERATION_JORDAN [2022-04-07 17:33:42,629 INFO L89 elerationTransformer]: Jordan loop acceleration statistics: 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult [2022-04-07 17:33:42,629 INFO L91 elerationTransformer]: Accelerated Formula: (and (= v_main_~x~0_7 (+ v_main_~x~0_6 1)) (< 0 (mod v_main_~x~0_7 4294967296)) (= v_main_~y~0_8 (+ v_main_~y~0_9 1))) InVars {main_~x~0=v_main_~x~0_7, main_~y~0=v_main_~y~0_9} OutVars{main_~x~0=v_main_~x~0_6, main_~y~0=v_main_~y~0_8, main_#t~post5=|v_main_#t~post5_1|, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] to Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (= |v_main_#t~post5_3| |v_main_#t~post5_1|) (= v_main_~y~0_9 v_main_~y~0_8) (= |v_main_#t~post6_3| |v_main_#t~post6_1|) (<= .cse0 0) (= v_main_~x~0_7 v_main_~x~0_6)) (and (< 0 .cse0) (= v_main_~x~0_6 (+ (* (- 1) v_main_~y~0_8) v_main_~x~0_7 v_main_~y~0_9)) (< v_main_~y~0_9 v_main_~y~0_8) (forall ((v_it_1 Int)) (or (< 0 (mod (+ v_main_~x~0_7 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)) (not (<= (+ v_main_~y~0_9 v_it_1 1) v_main_~y~0_8))))))) InVars {main_~y~0=v_main_~y~0_9, main_#t~post5=|v_main_#t~post5_3|, main_~x~0=v_main_~x~0_7, main_#t~post6=|v_main_#t~post6_3|} OutVars{main_~y~0=v_main_~y~0_8, main_#t~post5=|v_main_#t~post5_1|, main_~x~0=v_main_~x~0_6, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] [2022-04-07 17:33:42,945 INFO L89 elerationTransformer]: Jordan loop acceleration statistics: 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult [2022-04-07 17:33:42,946 INFO L91 elerationTransformer]: Accelerated Formula: (and (= v_main_~z~0_8 (+ v_main_~z~0_7 1)) (< 0 (mod v_main_~z~0_8 4294967296)) (= v_main_~x~0_11 (+ v_main_~x~0_12 1))) InVars {main_~x~0=v_main_~x~0_12, main_~z~0=v_main_~z~0_8} OutVars{main_~x~0=v_main_~x~0_11, main_~z~0=v_main_~z~0_7, main_#t~post8=|v_main_#t~post8_1|, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] to Formula: (let ((.cse0 (mod v_main_~z~0_8 4294967296))) (or (and (forall ((v_it_2 Int)) (or (< 0 (mod (+ v_main_~z~0_8 (* v_it_2 4294967295)) 4294967296)) (not (<= (+ v_main_~z~0_7 v_it_2 1) v_main_~z~0_8)) (not (<= 1 v_it_2)))) (= v_main_~x~0_11 (+ v_main_~x~0_12 v_main_~z~0_8 (* (- 1) v_main_~z~0_7))) (< 0 .cse0) (< v_main_~z~0_7 v_main_~z~0_8)) (and (<= .cse0 0) (= v_main_~z~0_8 v_main_~z~0_7) (= v_main_~x~0_12 v_main_~x~0_11) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|)))) InVars {main_~x~0=v_main_~x~0_12, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_8, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_11, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] [2022-04-07 17:33:43,337 INFO L89 elerationTransformer]: Jordan loop acceleration statistics: 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult [2022-04-07 17:33:43,338 INFO L91 elerationTransformer]: Accelerated Formula: (and (< 0 (mod v_main_~y~0_5 4294967296)) (= (+ v_main_~z~0_3 1) v_main_~z~0_2) (= v_main_~y~0_5 (+ v_main_~y~0_4 1))) InVars {main_~z~0=v_main_~z~0_3, main_~y~0=v_main_~y~0_5} OutVars{main_#t~post10=|v_main_#t~post10_1|, main_~z~0=v_main_~z~0_2, main_~y~0=v_main_~y~0_4, main_#t~post9=|v_main_#t~post9_1|} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] to Formula: (let ((.cse0 (mod v_main_~y~0_5 4294967296))) (or (and (= v_main_~y~0_4 v_main_~y~0_5) (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= |v_main_#t~post9_3| |v_main_#t~post9_1|) (<= .cse0 0)) (and (= v_main_~y~0_4 (+ v_main_~y~0_5 v_main_~z~0_3 (* (- 1) v_main_~z~0_2))) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= (+ v_main_~z~0_3 v_it_3 1) v_main_~z~0_2)) (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_5 (* v_it_3 4294967295)) 4294967296)))) (< v_main_~z~0_3 v_main_~z~0_2)))) InVars {main_~y~0=v_main_~y~0_5, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] [2022-04-07 17:33:43,622 INFO L89 elerationTransformer]: Jordan loop acceleration statistics: 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult [2022-04-07 17:33:43,622 INFO L91 elerationTransformer]: Accelerated Formula: (and (< 0 (mod v_main_~x~0_10 4294967296)) (= v_main_~x~0_10 (+ v_main_~x~0_9 1)) (= v_main_~y~0_10 (+ v_main_~y~0_11 1))) InVars {main_~x~0=v_main_~x~0_10, main_~y~0=v_main_~y~0_11} OutVars{main_~x~0=v_main_~x~0_9, main_~y~0=v_main_~y~0_10, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] to Formula: (let ((.cse0 (mod v_main_~x~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~x~0_10 v_main_~x~0_9)) (and (= (+ v_main_~x~0_10 v_main_~y~0_11 (* (- 1) v_main_~x~0_9)) v_main_~y~0_10) (< 0 .cse0) (forall ((v_it_4 Int)) (or (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_10) 4294967296)) (not (<= (+ v_main_~x~0_9 v_it_4 1) v_main_~x~0_10)) (not (<= 1 v_it_4)))) (< v_main_~x~0_9 v_main_~x~0_10)))) InVars {main_~y~0=v_main_~y~0_11, main_~x~0=v_main_~x~0_10, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~x~0=v_main_~x~0_9, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] [2022-04-07 17:33:43,942 INFO L89 elerationTransformer]: Jordan loop acceleration statistics: 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult [2022-04-07 17:33:43,942 INFO L91 elerationTransformer]: Accelerated Formula: (and (= v_main_~z~0_10 (+ v_main_~z~0_9 1)) (< 0 (mod v_main_~z~0_10 4294967296)) (= v_main_~x~0_13 (+ v_main_~x~0_14 1))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] to Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] [2022-04-07 17:33:46,069 WARN L977 rdanLoopAcceleration]: Unable to prove correctness of quantifier elimination. [2022-04-07 17:33:46,284 INFO L89 elerationTransformer]: Jordan loop acceleration statistics: 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult [2022-04-07 17:33:46,285 INFO L91 elerationTransformer]: Accelerated Formula: (and (< 0 (mod v_main_~y~0_7 4294967296)) (= v_main_~y~0_7 (+ v_main_~y~0_6 1)) (= v_main_~x~0_3 (+ v_main_~x~0_2 1))) InVars {main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_7} OutVars{main_~x~0=v_main_~x~0_2, main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] to Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] [2022-04-07 17:33:46,289 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 07.04 05:33:46 BasicIcfg [2022-04-07 17:33:46,289 INFO L132 PluginConnector]: ------------------------ END IcfgTransformer---------------------------- [2022-04-07 17:33:46,290 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-04-07 17:33:46,290 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-04-07 17:33:46,293 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-04-07 17:33:46,293 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.04 05:33:41" (1/4) ... [2022-04-07 17:33:46,293 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6e5ae518 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.04 05:33:46, skipping insertion in model container [2022-04-07 17:33:46,294 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 05:33:41" (2/4) ... [2022-04-07 17:33:46,294 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6e5ae518 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.04 05:33:46, skipping insertion in model container [2022-04-07 17:33:46,294 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.04 05:33:42" (3/4) ... [2022-04-07 17:33:46,294 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6e5ae518 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.04 05:33:46, skipping insertion in model container [2022-04-07 17:33:46,294 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 07.04 05:33:46" (4/4) ... [2022-04-07 17:33:46,295 INFO L111 eAbstractionObserver]: Analyzing ICFG in-de62.cJordan [2022-04-07 17:33:46,301 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:ForwardPredicates Determinization: PREDICATE_ABSTRACTION [2022-04-07 17:33:46,301 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-04-07 17:33:46,330 INFO L339 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-04-07 17:33:46,335 INFO L340 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=ForwardPredicates, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=false, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=All, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP [2022-04-07 17:33:46,335 INFO L341 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-04-07 17:33:46,348 INFO L276 IsEmpty]: Start isEmpty. Operand has 25 states, 17 states have (on average 1.8235294117647058) internal successors, (31), 18 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 3 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 17:33:46,352 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2022-04-07 17:33:46,352 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 17:33:46,353 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 17:33:46,353 INFO L403 AbstractCegarLoop]: === Iteration 1 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 17:33:46,357 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 17:33:46,357 INFO L85 PathProgramCache]: Analyzing trace with hash 430051023, now seen corresponding path program 1 times [2022-04-07 17:33:46,365 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 17:33:46,365 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1405019542] [2022-04-07 17:33:46,365 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:33:46,366 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 17:33:46,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:33:46,472 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 17:33:46,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:33:46,489 INFO L290 TraceCheckUtils]: 0: Hoare triple {33#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {28#true} is VALID [2022-04-07 17:33:46,490 INFO L290 TraceCheckUtils]: 1: Hoare triple {28#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {28#true} is VALID [2022-04-07 17:33:46,490 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {28#true} {28#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {28#true} is VALID [2022-04-07 17:33:46,491 INFO L272 TraceCheckUtils]: 0: Hoare triple {28#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {33#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 17:33:46,492 INFO L290 TraceCheckUtils]: 1: Hoare triple {33#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {28#true} is VALID [2022-04-07 17:33:46,492 INFO L290 TraceCheckUtils]: 2: Hoare triple {28#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {28#true} is VALID [2022-04-07 17:33:46,492 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {28#true} {28#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {28#true} is VALID [2022-04-07 17:33:46,493 INFO L272 TraceCheckUtils]: 4: Hoare triple {28#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {28#true} is VALID [2022-04-07 17:33:46,493 INFO L290 TraceCheckUtils]: 5: Hoare triple {28#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {28#true} is VALID [2022-04-07 17:33:46,493 INFO L290 TraceCheckUtils]: 6: Hoare triple {28#true} [103] L16-2-->L16-3: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {29#false} is VALID [2022-04-07 17:33:46,494 INFO L290 TraceCheckUtils]: 7: Hoare triple {29#false} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {29#false} is VALID [2022-04-07 17:33:46,494 INFO L290 TraceCheckUtils]: 8: Hoare triple {29#false} [107] L23-2-->L29-1: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {29#false} is VALID [2022-04-07 17:33:46,494 INFO L290 TraceCheckUtils]: 9: Hoare triple {29#false} [110] L29-1-->L35-1: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {29#false} is VALID [2022-04-07 17:33:46,494 INFO L290 TraceCheckUtils]: 10: Hoare triple {29#false} [113] L35-1-->L41-1: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {29#false} is VALID [2022-04-07 17:33:46,495 INFO L290 TraceCheckUtils]: 11: Hoare triple {29#false} [116] L41-1-->L47-1: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {29#false} is VALID [2022-04-07 17:33:46,496 INFO L290 TraceCheckUtils]: 12: Hoare triple {29#false} [119] L47-1-->L47-2: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {29#false} is VALID [2022-04-07 17:33:46,496 INFO L272 TraceCheckUtils]: 13: Hoare triple {29#false} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {29#false} is VALID [2022-04-07 17:33:46,496 INFO L290 TraceCheckUtils]: 14: Hoare triple {29#false} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {29#false} is VALID [2022-04-07 17:33:46,497 INFO L290 TraceCheckUtils]: 15: Hoare triple {29#false} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {29#false} is VALID [2022-04-07 17:33:46,497 INFO L290 TraceCheckUtils]: 16: Hoare triple {29#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {29#false} is VALID [2022-04-07 17:33:46,497 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 17:33:46,498 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 17:33:46,498 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1405019542] [2022-04-07 17:33:46,499 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1405019542] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-07 17:33:46,499 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-07 17:33:46,499 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-04-07 17:33:46,502 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [426830358] [2022-04-07 17:33:46,503 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-07 17:33:46,510 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 4.333333333333333) internal successors, (13), 2 states have internal predecessors, (13), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-07 17:33:46,511 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 17:33:46,514 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 4.333333333333333) internal successors, (13), 2 states have internal predecessors, (13), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:33:46,534 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 17 edges. 17 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 17:33:46,534 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-04-07 17:33:46,534 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 17:33:46,561 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-04-07 17:33:46,562 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-04-07 17:33:46,565 INFO L87 Difference]: Start difference. First operand has 25 states, 17 states have (on average 1.8235294117647058) internal successors, (31), 18 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 3 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 3 states, 3 states have (on average 4.333333333333333) internal successors, (13), 2 states have internal predecessors, (13), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:33:46,631 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:33:46,631 INFO L93 Difference]: Finished difference Result 25 states and 30 transitions. [2022-04-07 17:33:46,632 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-04-07 17:33:46,632 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 4.333333333333333) internal successors, (13), 2 states have internal predecessors, (13), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-07 17:33:46,633 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 17:33:46,634 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 4.333333333333333) internal successors, (13), 2 states have internal predecessors, (13), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:33:46,645 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 37 transitions. [2022-04-07 17:33:46,646 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 4.333333333333333) internal successors, (13), 2 states have internal predecessors, (13), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:33:46,651 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 37 transitions. [2022-04-07 17:33:46,651 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 3 states and 37 transitions. [2022-04-07 17:33:46,696 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 37 edges. 37 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 17:33:46,704 INFO L225 Difference]: With dead ends: 25 [2022-04-07 17:33:46,704 INFO L226 Difference]: Without dead ends: 18 [2022-04-07 17:33:46,705 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-04-07 17:33:46,709 INFO L913 BasicCegarLoop]: 29 mSDtfsCounter, 21 mSDsluCounter, 3 mSDsCounter, 0 mSdLazyCounter, 3 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 22 SdHoareTripleChecker+Valid, 32 SdHoareTripleChecker+Invalid, 5 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 3 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-07 17:33:46,710 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [22 Valid, 32 Invalid, 5 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 3 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-07 17:33:46,724 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18 states. [2022-04-07 17:33:46,733 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18 to 18. [2022-04-07 17:33:46,733 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 17:33:46,733 INFO L82 GeneralOperation]: Start isEquivalent. First operand 18 states. Second operand has 18 states, 13 states have (on average 1.4615384615384615) internal successors, (19), 13 states have internal predecessors, (19), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:33:46,734 INFO L74 IsIncluded]: Start isIncluded. First operand 18 states. Second operand has 18 states, 13 states have (on average 1.4615384615384615) internal successors, (19), 13 states have internal predecessors, (19), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:33:46,735 INFO L87 Difference]: Start difference. First operand 18 states. Second operand has 18 states, 13 states have (on average 1.4615384615384615) internal successors, (19), 13 states have internal predecessors, (19), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:33:46,742 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:33:46,742 INFO L93 Difference]: Finished difference Result 18 states and 23 transitions. [2022-04-07 17:33:46,742 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states and 23 transitions. [2022-04-07 17:33:46,742 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:33:46,743 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:33:46,744 INFO L74 IsIncluded]: Start isIncluded. First operand has 18 states, 13 states have (on average 1.4615384615384615) internal successors, (19), 13 states have internal predecessors, (19), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 18 states. [2022-04-07 17:33:46,744 INFO L87 Difference]: Start difference. First operand has 18 states, 13 states have (on average 1.4615384615384615) internal successors, (19), 13 states have internal predecessors, (19), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 18 states. [2022-04-07 17:33:46,750 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:33:46,751 INFO L93 Difference]: Finished difference Result 18 states and 23 transitions. [2022-04-07 17:33:46,754 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states and 23 transitions. [2022-04-07 17:33:46,755 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:33:46,755 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:33:46,755 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 17:33:46,755 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 17:33:46,755 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18 states, 13 states have (on average 1.4615384615384615) internal successors, (19), 13 states have internal predecessors, (19), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:33:46,756 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 23 transitions. [2022-04-07 17:33:46,757 INFO L78 Accepts]: Start accepts. Automaton has 18 states and 23 transitions. Word has length 17 [2022-04-07 17:33:46,757 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 17:33:46,757 INFO L478 AbstractCegarLoop]: Abstraction has 18 states and 23 transitions. [2022-04-07 17:33:46,758 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 4.333333333333333) internal successors, (13), 2 states have internal predecessors, (13), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:33:46,758 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states and 23 transitions. [2022-04-07 17:33:46,758 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2022-04-07 17:33:46,758 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 17:33:46,758 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 17:33:46,759 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-04-07 17:33:46,759 INFO L403 AbstractCegarLoop]: === Iteration 2 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 17:33:46,759 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 17:33:46,760 INFO L85 PathProgramCache]: Analyzing trace with hash -514488111, now seen corresponding path program 1 times [2022-04-07 17:33:46,760 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 17:33:46,760 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [101079373] [2022-04-07 17:33:46,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:33:46,760 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 17:33:46,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:33:46,882 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 17:33:46,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:33:46,901 INFO L290 TraceCheckUtils]: 0: Hoare triple {123#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {115#true} is VALID [2022-04-07 17:33:46,902 INFO L290 TraceCheckUtils]: 1: Hoare triple {115#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {115#true} is VALID [2022-04-07 17:33:46,902 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {115#true} {115#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {115#true} is VALID [2022-04-07 17:33:46,902 INFO L272 TraceCheckUtils]: 0: Hoare triple {115#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {123#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 17:33:46,903 INFO L290 TraceCheckUtils]: 1: Hoare triple {123#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {115#true} is VALID [2022-04-07 17:33:46,903 INFO L290 TraceCheckUtils]: 2: Hoare triple {115#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {115#true} is VALID [2022-04-07 17:33:46,903 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {115#true} {115#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {115#true} is VALID [2022-04-07 17:33:46,903 INFO L272 TraceCheckUtils]: 4: Hoare triple {115#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {115#true} is VALID [2022-04-07 17:33:46,903 INFO L290 TraceCheckUtils]: 5: Hoare triple {115#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {115#true} is VALID [2022-04-07 17:33:46,904 INFO L290 TraceCheckUtils]: 6: Hoare triple {115#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {120#(= (+ (* (- 4294967296) (div main_~x~0 4294967296)) main_~x~0) 0)} is VALID [2022-04-07 17:33:46,905 INFO L290 TraceCheckUtils]: 7: Hoare triple {120#(= (+ (* (- 4294967296) (div main_~x~0 4294967296)) main_~x~0) 0)} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {120#(= (+ (* (- 4294967296) (div main_~x~0 4294967296)) main_~x~0) 0)} is VALID [2022-04-07 17:33:46,905 INFO L290 TraceCheckUtils]: 8: Hoare triple {120#(= (+ (* (- 4294967296) (div main_~x~0 4294967296)) main_~x~0) 0)} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {120#(= (+ (* (- 4294967296) (div main_~x~0 4294967296)) main_~x~0) 0)} is VALID [2022-04-07 17:33:46,906 INFO L290 TraceCheckUtils]: 9: Hoare triple {120#(= (+ (* (- 4294967296) (div main_~x~0 4294967296)) main_~x~0) 0)} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {120#(= (+ (* (- 4294967296) (div main_~x~0 4294967296)) main_~x~0) 0)} is VALID [2022-04-07 17:33:46,906 INFO L290 TraceCheckUtils]: 10: Hoare triple {120#(= (+ (* (- 4294967296) (div main_~x~0 4294967296)) main_~x~0) 0)} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {120#(= (+ (* (- 4294967296) (div main_~x~0 4294967296)) main_~x~0) 0)} is VALID [2022-04-07 17:33:46,907 INFO L290 TraceCheckUtils]: 11: Hoare triple {120#(= (+ (* (- 4294967296) (div main_~x~0 4294967296)) main_~x~0) 0)} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {120#(= (+ (* (- 4294967296) (div main_~x~0 4294967296)) main_~x~0) 0)} is VALID [2022-04-07 17:33:46,907 INFO L290 TraceCheckUtils]: 12: Hoare triple {120#(= (+ (* (- 4294967296) (div main_~x~0 4294967296)) main_~x~0) 0)} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {120#(= (+ (* (- 4294967296) (div main_~x~0 4294967296)) main_~x~0) 0)} is VALID [2022-04-07 17:33:46,908 INFO L272 TraceCheckUtils]: 13: Hoare triple {120#(= (+ (* (- 4294967296) (div main_~x~0 4294967296)) main_~x~0) 0)} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {121#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-07 17:33:46,910 INFO L290 TraceCheckUtils]: 14: Hoare triple {121#(not (= |__VERIFIER_assert_#in~cond| 0))} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {122#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-07 17:33:46,910 INFO L290 TraceCheckUtils]: 15: Hoare triple {122#(not (= __VERIFIER_assert_~cond 0))} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {116#false} is VALID [2022-04-07 17:33:46,910 INFO L290 TraceCheckUtils]: 16: Hoare triple {116#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {116#false} is VALID [2022-04-07 17:33:46,911 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 17:33:46,911 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 17:33:46,911 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [101079373] [2022-04-07 17:33:46,911 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [101079373] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-07 17:33:46,911 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-07 17:33:46,912 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2022-04-07 17:33:46,912 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [639353512] [2022-04-07 17:33:46,914 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-07 17:33:46,919 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 2.1666666666666665) internal successors, (13), 4 states have internal predecessors, (13), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-07 17:33:46,919 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 17:33:46,919 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 6 states, 6 states have (on average 2.1666666666666665) internal successors, (13), 4 states have internal predecessors, (13), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:33:46,936 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 17 edges. 17 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 17:33:46,936 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-04-07 17:33:46,937 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 17:33:46,938 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-04-07 17:33:46,938 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2022-04-07 17:33:46,938 INFO L87 Difference]: Start difference. First operand 18 states and 23 transitions. Second operand has 6 states, 6 states have (on average 2.1666666666666665) internal successors, (13), 4 states have internal predecessors, (13), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:33:47,074 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:33:47,074 INFO L93 Difference]: Finished difference Result 28 states and 39 transitions. [2022-04-07 17:33:47,074 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-04-07 17:33:47,075 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 2.1666666666666665) internal successors, (13), 4 states have internal predecessors, (13), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-07 17:33:47,075 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 17:33:47,075 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 2.1666666666666665) internal successors, (13), 4 states have internal predecessors, (13), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:33:47,077 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 40 transitions. [2022-04-07 17:33:47,077 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 2.1666666666666665) internal successors, (13), 4 states have internal predecessors, (13), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:33:47,079 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 40 transitions. [2022-04-07 17:33:47,079 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 6 states and 40 transitions. [2022-04-07 17:33:47,142 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 40 edges. 40 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 17:33:47,143 INFO L225 Difference]: With dead ends: 28 [2022-04-07 17:33:47,143 INFO L226 Difference]: Without dead ends: 25 [2022-04-07 17:33:47,144 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2022-04-07 17:33:47,146 INFO L913 BasicCegarLoop]: 17 mSDtfsCounter, 18 mSDsluCounter, 20 mSDsCounter, 0 mSdLazyCounter, 34 mSolverCounterSat, 8 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 18 SdHoareTripleChecker+Valid, 37 SdHoareTripleChecker+Invalid, 54 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 8 IncrementalHoareTripleChecker+Valid, 34 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 12 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-07 17:33:47,146 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [18 Valid, 37 Invalid, 54 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [8 Valid, 34 Invalid, 0 Unknown, 12 Unchecked, 0.0s Time] [2022-04-07 17:33:47,148 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2022-04-07 17:33:47,151 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 20. [2022-04-07 17:33:47,151 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 17:33:47,152 INFO L82 GeneralOperation]: Start isEquivalent. First operand 25 states. Second operand has 20 states, 15 states have (on average 1.4666666666666666) internal successors, (22), 15 states have internal predecessors, (22), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:33:47,153 INFO L74 IsIncluded]: Start isIncluded. First operand 25 states. Second operand has 20 states, 15 states have (on average 1.4666666666666666) internal successors, (22), 15 states have internal predecessors, (22), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:33:47,154 INFO L87 Difference]: Start difference. First operand 25 states. Second operand has 20 states, 15 states have (on average 1.4666666666666666) internal successors, (22), 15 states have internal predecessors, (22), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:33:47,156 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:33:47,156 INFO L93 Difference]: Finished difference Result 25 states and 36 transitions. [2022-04-07 17:33:47,156 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 36 transitions. [2022-04-07 17:33:47,157 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:33:47,157 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:33:47,157 INFO L74 IsIncluded]: Start isIncluded. First operand has 20 states, 15 states have (on average 1.4666666666666666) internal successors, (22), 15 states have internal predecessors, (22), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 25 states. [2022-04-07 17:33:47,157 INFO L87 Difference]: Start difference. First operand has 20 states, 15 states have (on average 1.4666666666666666) internal successors, (22), 15 states have internal predecessors, (22), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 25 states. [2022-04-07 17:33:47,160 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:33:47,160 INFO L93 Difference]: Finished difference Result 25 states and 36 transitions. [2022-04-07 17:33:47,160 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 36 transitions. [2022-04-07 17:33:47,161 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:33:47,161 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:33:47,161 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 17:33:47,161 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 17:33:47,162 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20 states, 15 states have (on average 1.4666666666666666) internal successors, (22), 15 states have internal predecessors, (22), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:33:47,163 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 26 transitions. [2022-04-07 17:33:47,164 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 26 transitions. Word has length 17 [2022-04-07 17:33:47,164 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 17:33:47,164 INFO L478 AbstractCegarLoop]: Abstraction has 20 states and 26 transitions. [2022-04-07 17:33:47,164 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 2.1666666666666665) internal successors, (13), 4 states have internal predecessors, (13), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:33:47,164 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 26 transitions. [2022-04-07 17:33:47,165 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2022-04-07 17:33:47,165 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 17:33:47,165 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 17:33:47,165 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-04-07 17:33:47,166 INFO L403 AbstractCegarLoop]: === Iteration 3 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 17:33:47,170 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 17:33:47,170 INFO L85 PathProgramCache]: Analyzing trace with hash 1257458414, now seen corresponding path program 1 times [2022-04-07 17:33:47,170 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 17:33:47,170 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [889644213] [2022-04-07 17:33:47,170 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:33:47,171 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 17:33:47,204 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.0))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-07 17:33:47,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:33:47,248 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.1))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-07 17:33:47,323 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 17:33:47,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:33:47,339 INFO L290 TraceCheckUtils]: 0: Hoare triple {239#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {230#true} is VALID [2022-04-07 17:33:47,339 INFO L290 TraceCheckUtils]: 1: Hoare triple {230#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {230#true} is VALID [2022-04-07 17:33:47,339 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {230#true} {230#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {230#true} is VALID [2022-04-07 17:33:47,343 INFO L272 TraceCheckUtils]: 0: Hoare triple {230#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {239#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 17:33:47,343 INFO L290 TraceCheckUtils]: 1: Hoare triple {239#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {230#true} is VALID [2022-04-07 17:33:47,343 INFO L290 TraceCheckUtils]: 2: Hoare triple {230#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {230#true} is VALID [2022-04-07 17:33:47,344 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {230#true} {230#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {230#true} is VALID [2022-04-07 17:33:47,345 INFO L272 TraceCheckUtils]: 4: Hoare triple {230#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {230#true} is VALID [2022-04-07 17:33:47,347 INFO L290 TraceCheckUtils]: 5: Hoare triple {230#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {230#true} is VALID [2022-04-07 17:33:47,349 INFO L290 TraceCheckUtils]: 6: Hoare triple {230#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:33:47,350 INFO L290 TraceCheckUtils]: 7: Hoare triple {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:33:47,350 INFO L290 TraceCheckUtils]: 8: Hoare triple {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:33:47,352 INFO L290 TraceCheckUtils]: 9: Hoare triple {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {236#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:33:47,353 INFO L290 TraceCheckUtils]: 10: Hoare triple {236#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {236#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:33:47,354 INFO L290 TraceCheckUtils]: 11: Hoare triple {236#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {236#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:33:47,355 INFO L290 TraceCheckUtils]: 12: Hoare triple {236#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:33:47,356 INFO L290 TraceCheckUtils]: 13: Hoare triple {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:33:47,357 INFO L272 TraceCheckUtils]: 14: Hoare triple {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {237#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-07 17:33:47,357 INFO L290 TraceCheckUtils]: 15: Hoare triple {237#(not (= |__VERIFIER_assert_#in~cond| 0))} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {238#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-07 17:33:47,357 INFO L290 TraceCheckUtils]: 16: Hoare triple {238#(not (= __VERIFIER_assert_~cond 0))} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {231#false} is VALID [2022-04-07 17:33:47,358 INFO L290 TraceCheckUtils]: 17: Hoare triple {231#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {231#false} is VALID [2022-04-07 17:33:47,358 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 17:33:47,359 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 17:33:47,360 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [889644213] [2022-04-07 17:33:47,360 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [889644213] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 17:33:47,360 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1655878806] [2022-04-07 17:33:47,360 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:33:47,360 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 17:33:47,360 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 17:33:47,367 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 17:33:47,406 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-04-07 17:33:47,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:33:47,422 INFO L263 TraceCheckSpWp]: Trace formula consists of 63 conjuncts, 6 conjunts are in the unsatisfiable core [2022-04-07 17:33:47,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:33:47,438 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 17:33:48,194 INFO L272 TraceCheckUtils]: 0: Hoare triple {230#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {230#true} is VALID [2022-04-07 17:33:48,194 INFO L290 TraceCheckUtils]: 1: Hoare triple {230#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {230#true} is VALID [2022-04-07 17:33:48,194 INFO L290 TraceCheckUtils]: 2: Hoare triple {230#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {230#true} is VALID [2022-04-07 17:33:48,195 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {230#true} {230#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {230#true} is VALID [2022-04-07 17:33:48,195 INFO L272 TraceCheckUtils]: 4: Hoare triple {230#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {230#true} is VALID [2022-04-07 17:33:48,195 INFO L290 TraceCheckUtils]: 5: Hoare triple {230#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {230#true} is VALID [2022-04-07 17:33:48,196 INFO L290 TraceCheckUtils]: 6: Hoare triple {230#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:33:48,196 INFO L290 TraceCheckUtils]: 7: Hoare triple {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:33:48,197 INFO L290 TraceCheckUtils]: 8: Hoare triple {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:33:48,198 INFO L290 TraceCheckUtils]: 9: Hoare triple {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {236#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:33:48,198 INFO L290 TraceCheckUtils]: 10: Hoare triple {236#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {236#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:33:48,199 INFO L290 TraceCheckUtils]: 11: Hoare triple {236#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {236#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:33:48,200 INFO L290 TraceCheckUtils]: 12: Hoare triple {236#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:33:48,201 INFO L290 TraceCheckUtils]: 13: Hoare triple {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:33:48,202 INFO L272 TraceCheckUtils]: 14: Hoare triple {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {285#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 17:33:48,202 INFO L290 TraceCheckUtils]: 15: Hoare triple {285#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {289#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 17:33:48,203 INFO L290 TraceCheckUtils]: 16: Hoare triple {289#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {231#false} is VALID [2022-04-07 17:33:48,203 INFO L290 TraceCheckUtils]: 17: Hoare triple {231#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {231#false} is VALID [2022-04-07 17:33:48,203 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 17:33:48,204 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-07 17:33:54,114 INFO L290 TraceCheckUtils]: 17: Hoare triple {231#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {231#false} is VALID [2022-04-07 17:33:54,114 INFO L290 TraceCheckUtils]: 16: Hoare triple {289#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {231#false} is VALID [2022-04-07 17:33:54,115 INFO L290 TraceCheckUtils]: 15: Hoare triple {285#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {289#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 17:33:54,116 INFO L272 TraceCheckUtils]: 14: Hoare triple {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {285#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 17:33:54,117 INFO L290 TraceCheckUtils]: 13: Hoare triple {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:33:56,140 WARN L290 TraceCheckUtils]: 12: Hoare triple {311#(forall ((aux_mod_v_main_~x~0_32_31 Int)) (or (<= aux_mod_v_main_~x~0_32_31 0) (and (or (forall ((aux_div_v_main_~x~0_32_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_32_31 (* aux_div_v_main_~x~0_32_31 4294967296))))) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~x~0_32_31 Int)) (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_32_31 v_it_6 (* aux_div_v_main_~x~0_32_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (not (< (+ aux_mod_v_main_~x~0_32_31 (* aux_div_v_main_~x~0_32_31 4294967296)) main_~x~0)))))) (<= 4294967296 aux_mod_v_main_~x~0_32_31)))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is UNKNOWN [2022-04-07 17:33:58,154 WARN L290 TraceCheckUtils]: 11: Hoare triple {311#(forall ((aux_mod_v_main_~x~0_32_31 Int)) (or (<= aux_mod_v_main_~x~0_32_31 0) (and (or (forall ((aux_div_v_main_~x~0_32_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_32_31 (* aux_div_v_main_~x~0_32_31 4294967296))))) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~x~0_32_31 Int)) (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_32_31 v_it_6 (* aux_div_v_main_~x~0_32_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (not (< (+ aux_mod_v_main_~x~0_32_31 (* aux_div_v_main_~x~0_32_31 4294967296)) main_~x~0)))))) (<= 4294967296 aux_mod_v_main_~x~0_32_31)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {311#(forall ((aux_mod_v_main_~x~0_32_31 Int)) (or (<= aux_mod_v_main_~x~0_32_31 0) (and (or (forall ((aux_div_v_main_~x~0_32_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_32_31 (* aux_div_v_main_~x~0_32_31 4294967296))))) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~x~0_32_31 Int)) (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_32_31 v_it_6 (* aux_div_v_main_~x~0_32_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (not (< (+ aux_mod_v_main_~x~0_32_31 (* aux_div_v_main_~x~0_32_31 4294967296)) main_~x~0)))))) (<= 4294967296 aux_mod_v_main_~x~0_32_31)))} is UNKNOWN [2022-04-07 17:33:58,393 INFO L290 TraceCheckUtils]: 10: Hoare triple {311#(forall ((aux_mod_v_main_~x~0_32_31 Int)) (or (<= aux_mod_v_main_~x~0_32_31 0) (and (or (forall ((aux_div_v_main_~x~0_32_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_32_31 (* aux_div_v_main_~x~0_32_31 4294967296))))) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~x~0_32_31 Int)) (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_32_31 v_it_6 (* aux_div_v_main_~x~0_32_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (not (< (+ aux_mod_v_main_~x~0_32_31 (* aux_div_v_main_~x~0_32_31 4294967296)) main_~x~0)))))) (<= 4294967296 aux_mod_v_main_~x~0_32_31)))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {311#(forall ((aux_mod_v_main_~x~0_32_31 Int)) (or (<= aux_mod_v_main_~x~0_32_31 0) (and (or (forall ((aux_div_v_main_~x~0_32_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_32_31 (* aux_div_v_main_~x~0_32_31 4294967296))))) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~x~0_32_31 Int)) (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_32_31 v_it_6 (* aux_div_v_main_~x~0_32_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (not (< (+ aux_mod_v_main_~x~0_32_31 (* aux_div_v_main_~x~0_32_31 4294967296)) main_~x~0)))))) (<= 4294967296 aux_mod_v_main_~x~0_32_31)))} is VALID [2022-04-07 17:33:58,395 INFO L290 TraceCheckUtils]: 9: Hoare triple {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {311#(forall ((aux_mod_v_main_~x~0_32_31 Int)) (or (<= aux_mod_v_main_~x~0_32_31 0) (and (or (forall ((aux_div_v_main_~x~0_32_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_32_31 (* aux_div_v_main_~x~0_32_31 4294967296))))) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~x~0_32_31 Int)) (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_32_31 v_it_6 (* aux_div_v_main_~x~0_32_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (not (< (+ aux_mod_v_main_~x~0_32_31 (* aux_div_v_main_~x~0_32_31 4294967296)) main_~x~0)))))) (<= 4294967296 aux_mod_v_main_~x~0_32_31)))} is VALID [2022-04-07 17:33:58,395 INFO L290 TraceCheckUtils]: 8: Hoare triple {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:33:58,396 INFO L290 TraceCheckUtils]: 7: Hoare triple {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:33:58,396 INFO L290 TraceCheckUtils]: 6: Hoare triple {230#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:33:58,397 INFO L290 TraceCheckUtils]: 5: Hoare triple {230#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {230#true} is VALID [2022-04-07 17:33:58,397 INFO L272 TraceCheckUtils]: 4: Hoare triple {230#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {230#true} is VALID [2022-04-07 17:33:58,397 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {230#true} {230#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {230#true} is VALID [2022-04-07 17:33:58,397 INFO L290 TraceCheckUtils]: 2: Hoare triple {230#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {230#true} is VALID [2022-04-07 17:33:58,397 INFO L290 TraceCheckUtils]: 1: Hoare triple {230#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {230#true} is VALID [2022-04-07 17:33:58,398 INFO L272 TraceCheckUtils]: 0: Hoare triple {230#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {230#true} is VALID [2022-04-07 17:33:58,398 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 17:33:58,398 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1655878806] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-07 17:33:58,398 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-07 17:33:58,399 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6, 6] total 10 [2022-04-07 17:33:58,399 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [923817025] [2022-04-07 17:33:58,399 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-07 17:33:58,399 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 2.1) internal successors, (21), 7 states have internal predecessors, (21), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-07 17:33:58,400 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 17:33:58,400 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 10 states, 10 states have (on average 2.1) internal successors, (21), 7 states have internal predecessors, (21), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:34:01,209 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 27 edges. 26 inductive. 0 not inductive. 1 times theorem prover too weak to decide inductivity. [2022-04-07 17:34:01,209 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2022-04-07 17:34:01,209 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 17:34:01,209 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2022-04-07 17:34:01,210 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=67, Unknown=2, NotChecked=0, Total=90 [2022-04-07 17:34:01,210 INFO L87 Difference]: Start difference. First operand 20 states and 26 transitions. Second operand has 10 states, 10 states have (on average 2.1) internal successors, (21), 7 states have internal predecessors, (21), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:34:02,112 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:34:02,113 INFO L93 Difference]: Finished difference Result 31 states and 43 transitions. [2022-04-07 17:34:02,113 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-04-07 17:34:02,113 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 2.1) internal successors, (21), 7 states have internal predecessors, (21), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-07 17:34:02,113 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 17:34:02,113 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 2.1) internal successors, (21), 7 states have internal predecessors, (21), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:34:02,115 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 44 transitions. [2022-04-07 17:34:02,115 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 2.1) internal successors, (21), 7 states have internal predecessors, (21), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:34:02,116 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 44 transitions. [2022-04-07 17:34:02,116 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 8 states and 44 transitions. [2022-04-07 17:34:02,164 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 44 edges. 44 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 17:34:02,164 INFO L225 Difference]: With dead ends: 31 [2022-04-07 17:34:02,165 INFO L226 Difference]: Without dead ends: 28 [2022-04-07 17:34:02,165 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 30 SyntacticMatches, 6 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 4.9s TimeCoverageRelationStatistics Valid=45, Invalid=135, Unknown=2, NotChecked=0, Total=182 [2022-04-07 17:34:02,166 INFO L913 BasicCegarLoop]: 18 mSDtfsCounter, 23 mSDsluCounter, 34 mSDsCounter, 0 mSdLazyCounter, 52 mSolverCounterSat, 10 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 23 SdHoareTripleChecker+Valid, 52 SdHoareTripleChecker+Invalid, 94 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 10 IncrementalHoareTripleChecker+Valid, 52 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 32 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-07 17:34:02,166 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [23 Valid, 52 Invalid, 94 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [10 Valid, 52 Invalid, 0 Unknown, 32 Unchecked, 0.1s Time] [2022-04-07 17:34:02,167 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states. [2022-04-07 17:34:02,169 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 25. [2022-04-07 17:34:02,169 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 17:34:02,169 INFO L82 GeneralOperation]: Start isEquivalent. First operand 28 states. Second operand has 25 states, 20 states have (on average 1.55) internal successors, (31), 20 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:34:02,169 INFO L74 IsIncluded]: Start isIncluded. First operand 28 states. Second operand has 25 states, 20 states have (on average 1.55) internal successors, (31), 20 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:34:02,170 INFO L87 Difference]: Start difference. First operand 28 states. Second operand has 25 states, 20 states have (on average 1.55) internal successors, (31), 20 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:34:02,171 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:34:02,171 INFO L93 Difference]: Finished difference Result 28 states and 40 transitions. [2022-04-07 17:34:02,171 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 40 transitions. [2022-04-07 17:34:02,172 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:34:02,172 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:34:02,172 INFO L74 IsIncluded]: Start isIncluded. First operand has 25 states, 20 states have (on average 1.55) internal successors, (31), 20 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 28 states. [2022-04-07 17:34:02,172 INFO L87 Difference]: Start difference. First operand has 25 states, 20 states have (on average 1.55) internal successors, (31), 20 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 28 states. [2022-04-07 17:34:02,173 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:34:02,174 INFO L93 Difference]: Finished difference Result 28 states and 40 transitions. [2022-04-07 17:34:02,174 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 40 transitions. [2022-04-07 17:34:02,174 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:34:02,174 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:34:02,174 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 17:34:02,174 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 17:34:02,174 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25 states, 20 states have (on average 1.55) internal successors, (31), 20 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:34:02,175 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 35 transitions. [2022-04-07 17:34:02,175 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 35 transitions. Word has length 18 [2022-04-07 17:34:02,175 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 17:34:02,176 INFO L478 AbstractCegarLoop]: Abstraction has 25 states and 35 transitions. [2022-04-07 17:34:02,176 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 2.1) internal successors, (21), 7 states have internal predecessors, (21), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:34:02,176 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 35 transitions. [2022-04-07 17:34:02,176 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2022-04-07 17:34:02,176 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 17:34:02,176 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 17:34:02,202 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Ended with exit code 0 [2022-04-07 17:34:02,399 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2,2 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 17:34:02,399 INFO L403 AbstractCegarLoop]: === Iteration 4 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 17:34:02,400 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 17:34:02,400 INFO L85 PathProgramCache]: Analyzing trace with hash 2030445491, now seen corresponding path program 1 times [2022-04-07 17:34:02,400 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 17:34:02,400 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [831997566] [2022-04-07 17:34:02,400 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:34:02,400 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 17:34:02,413 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.0))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-07 17:34:02,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:34:02,430 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.1))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-07 17:34:02,487 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 17:34:02,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:34:02,493 INFO L290 TraceCheckUtils]: 0: Hoare triple {479#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {470#true} is VALID [2022-04-07 17:34:02,493 INFO L290 TraceCheckUtils]: 1: Hoare triple {470#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {470#true} is VALID [2022-04-07 17:34:02,494 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {470#true} {470#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {470#true} is VALID [2022-04-07 17:34:02,494 INFO L272 TraceCheckUtils]: 0: Hoare triple {470#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {479#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 17:34:02,494 INFO L290 TraceCheckUtils]: 1: Hoare triple {479#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {470#true} is VALID [2022-04-07 17:34:02,494 INFO L290 TraceCheckUtils]: 2: Hoare triple {470#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {470#true} is VALID [2022-04-07 17:34:02,495 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {470#true} {470#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {470#true} is VALID [2022-04-07 17:34:02,495 INFO L272 TraceCheckUtils]: 4: Hoare triple {470#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {470#true} is VALID [2022-04-07 17:34:02,495 INFO L290 TraceCheckUtils]: 5: Hoare triple {470#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {470#true} is VALID [2022-04-07 17:34:02,498 INFO L290 TraceCheckUtils]: 6: Hoare triple {470#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:34:02,498 INFO L290 TraceCheckUtils]: 7: Hoare triple {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:34:02,499 INFO L290 TraceCheckUtils]: 8: Hoare triple {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {476#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-07 17:34:02,499 INFO L290 TraceCheckUtils]: 9: Hoare triple {476#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {476#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-07 17:34:02,500 INFO L290 TraceCheckUtils]: 10: Hoare triple {476#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {476#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-07 17:34:02,501 INFO L290 TraceCheckUtils]: 11: Hoare triple {476#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:34:02,502 INFO L290 TraceCheckUtils]: 12: Hoare triple {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:34:02,502 INFO L290 TraceCheckUtils]: 13: Hoare triple {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:34:02,503 INFO L272 TraceCheckUtils]: 14: Hoare triple {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {477#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-07 17:34:02,504 INFO L290 TraceCheckUtils]: 15: Hoare triple {477#(not (= |__VERIFIER_assert_#in~cond| 0))} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {478#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-07 17:34:02,505 INFO L290 TraceCheckUtils]: 16: Hoare triple {478#(not (= __VERIFIER_assert_~cond 0))} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {471#false} is VALID [2022-04-07 17:34:02,505 INFO L290 TraceCheckUtils]: 17: Hoare triple {471#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {471#false} is VALID [2022-04-07 17:34:02,505 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 17:34:02,505 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 17:34:02,505 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [831997566] [2022-04-07 17:34:02,506 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [831997566] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 17:34:02,506 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [82311215] [2022-04-07 17:34:02,506 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:34:02,506 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 17:34:02,506 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 17:34:02,507 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 17:34:02,517 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-04-07 17:34:02,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:34:02,553 INFO L263 TraceCheckSpWp]: Trace formula consists of 63 conjuncts, 6 conjunts are in the unsatisfiable core [2022-04-07 17:34:02,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:34:02,575 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 17:34:03,297 INFO L272 TraceCheckUtils]: 0: Hoare triple {470#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {470#true} is VALID [2022-04-07 17:34:03,297 INFO L290 TraceCheckUtils]: 1: Hoare triple {470#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {470#true} is VALID [2022-04-07 17:34:03,297 INFO L290 TraceCheckUtils]: 2: Hoare triple {470#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {470#true} is VALID [2022-04-07 17:34:03,297 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {470#true} {470#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {470#true} is VALID [2022-04-07 17:34:03,298 INFO L272 TraceCheckUtils]: 4: Hoare triple {470#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {470#true} is VALID [2022-04-07 17:34:03,298 INFO L290 TraceCheckUtils]: 5: Hoare triple {470#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {470#true} is VALID [2022-04-07 17:34:03,299 INFO L290 TraceCheckUtils]: 6: Hoare triple {470#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:34:03,300 INFO L290 TraceCheckUtils]: 7: Hoare triple {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:34:03,300 INFO L290 TraceCheckUtils]: 8: Hoare triple {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {476#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-07 17:34:03,301 INFO L290 TraceCheckUtils]: 9: Hoare triple {476#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {476#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-07 17:34:03,302 INFO L290 TraceCheckUtils]: 10: Hoare triple {476#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {476#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-07 17:34:03,303 INFO L290 TraceCheckUtils]: 11: Hoare triple {476#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:34:03,303 INFO L290 TraceCheckUtils]: 12: Hoare triple {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:34:03,304 INFO L290 TraceCheckUtils]: 13: Hoare triple {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:34:03,305 INFO L272 TraceCheckUtils]: 14: Hoare triple {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {525#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 17:34:03,305 INFO L290 TraceCheckUtils]: 15: Hoare triple {525#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {529#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 17:34:03,306 INFO L290 TraceCheckUtils]: 16: Hoare triple {529#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {471#false} is VALID [2022-04-07 17:34:03,306 INFO L290 TraceCheckUtils]: 17: Hoare triple {471#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {471#false} is VALID [2022-04-07 17:34:03,306 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 17:34:03,306 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-07 17:34:08,719 INFO L290 TraceCheckUtils]: 17: Hoare triple {471#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {471#false} is VALID [2022-04-07 17:34:08,719 INFO L290 TraceCheckUtils]: 16: Hoare triple {529#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {471#false} is VALID [2022-04-07 17:34:08,720 INFO L290 TraceCheckUtils]: 15: Hoare triple {525#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {529#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 17:34:08,721 INFO L272 TraceCheckUtils]: 14: Hoare triple {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {525#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 17:34:08,735 INFO L290 TraceCheckUtils]: 13: Hoare triple {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:34:08,736 INFO L290 TraceCheckUtils]: 12: Hoare triple {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:34:10,764 WARN L290 TraceCheckUtils]: 11: Hoare triple {554#(forall ((aux_mod_v_main_~x~0_34_31 Int)) (or (and (or (forall ((aux_div_v_main_~x~0_34_31 Int)) (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_34_31 (* aux_div_v_main_~x~0_34_31 4294967296))))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_34_31 (* aux_div_v_main_~x~0_34_31 4294967296)))))) (not (< 0 (mod main_~z~0 4294967296)))) (or (forall ((aux_div_v_main_~x~0_34_31 Int)) (not (= (+ aux_mod_v_main_~x~0_34_31 (* aux_div_v_main_~x~0_34_31 4294967296)) main_~x~0))) (< 0 (mod main_~z~0 4294967296)))) (<= aux_mod_v_main_~x~0_34_31 0) (<= 4294967296 aux_mod_v_main_~x~0_34_31)))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is UNKNOWN [2022-04-07 17:34:12,770 WARN L290 TraceCheckUtils]: 10: Hoare triple {554#(forall ((aux_mod_v_main_~x~0_34_31 Int)) (or (and (or (forall ((aux_div_v_main_~x~0_34_31 Int)) (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_34_31 (* aux_div_v_main_~x~0_34_31 4294967296))))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_34_31 (* aux_div_v_main_~x~0_34_31 4294967296)))))) (not (< 0 (mod main_~z~0 4294967296)))) (or (forall ((aux_div_v_main_~x~0_34_31 Int)) (not (= (+ aux_mod_v_main_~x~0_34_31 (* aux_div_v_main_~x~0_34_31 4294967296)) main_~x~0))) (< 0 (mod main_~z~0 4294967296)))) (<= aux_mod_v_main_~x~0_34_31 0) (<= 4294967296 aux_mod_v_main_~x~0_34_31)))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {554#(forall ((aux_mod_v_main_~x~0_34_31 Int)) (or (and (or (forall ((aux_div_v_main_~x~0_34_31 Int)) (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_34_31 (* aux_div_v_main_~x~0_34_31 4294967296))))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_34_31 (* aux_div_v_main_~x~0_34_31 4294967296)))))) (not (< 0 (mod main_~z~0 4294967296)))) (or (forall ((aux_div_v_main_~x~0_34_31 Int)) (not (= (+ aux_mod_v_main_~x~0_34_31 (* aux_div_v_main_~x~0_34_31 4294967296)) main_~x~0))) (< 0 (mod main_~z~0 4294967296)))) (<= aux_mod_v_main_~x~0_34_31 0) (<= 4294967296 aux_mod_v_main_~x~0_34_31)))} is UNKNOWN [2022-04-07 17:34:14,788 WARN L290 TraceCheckUtils]: 9: Hoare triple {554#(forall ((aux_mod_v_main_~x~0_34_31 Int)) (or (and (or (forall ((aux_div_v_main_~x~0_34_31 Int)) (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_34_31 (* aux_div_v_main_~x~0_34_31 4294967296))))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_34_31 (* aux_div_v_main_~x~0_34_31 4294967296)))))) (not (< 0 (mod main_~z~0 4294967296)))) (or (forall ((aux_div_v_main_~x~0_34_31 Int)) (not (= (+ aux_mod_v_main_~x~0_34_31 (* aux_div_v_main_~x~0_34_31 4294967296)) main_~x~0))) (< 0 (mod main_~z~0 4294967296)))) (<= aux_mod_v_main_~x~0_34_31 0) (<= 4294967296 aux_mod_v_main_~x~0_34_31)))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {554#(forall ((aux_mod_v_main_~x~0_34_31 Int)) (or (and (or (forall ((aux_div_v_main_~x~0_34_31 Int)) (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_34_31 (* aux_div_v_main_~x~0_34_31 4294967296))))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_34_31 (* aux_div_v_main_~x~0_34_31 4294967296)))))) (not (< 0 (mod main_~z~0 4294967296)))) (or (forall ((aux_div_v_main_~x~0_34_31 Int)) (not (= (+ aux_mod_v_main_~x~0_34_31 (* aux_div_v_main_~x~0_34_31 4294967296)) main_~x~0))) (< 0 (mod main_~z~0 4294967296)))) (<= aux_mod_v_main_~x~0_34_31 0) (<= 4294967296 aux_mod_v_main_~x~0_34_31)))} is UNKNOWN [2022-04-07 17:34:14,791 INFO L290 TraceCheckUtils]: 8: Hoare triple {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {554#(forall ((aux_mod_v_main_~x~0_34_31 Int)) (or (and (or (forall ((aux_div_v_main_~x~0_34_31 Int)) (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_34_31 (* aux_div_v_main_~x~0_34_31 4294967296))))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_34_31 (* aux_div_v_main_~x~0_34_31 4294967296)))))) (not (< 0 (mod main_~z~0 4294967296)))) (or (forall ((aux_div_v_main_~x~0_34_31 Int)) (not (= (+ aux_mod_v_main_~x~0_34_31 (* aux_div_v_main_~x~0_34_31 4294967296)) main_~x~0))) (< 0 (mod main_~z~0 4294967296)))) (<= aux_mod_v_main_~x~0_34_31 0) (<= 4294967296 aux_mod_v_main_~x~0_34_31)))} is VALID [2022-04-07 17:34:14,792 INFO L290 TraceCheckUtils]: 7: Hoare triple {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:34:14,792 INFO L290 TraceCheckUtils]: 6: Hoare triple {470#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:34:14,792 INFO L290 TraceCheckUtils]: 5: Hoare triple {470#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {470#true} is VALID [2022-04-07 17:34:14,793 INFO L272 TraceCheckUtils]: 4: Hoare triple {470#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {470#true} is VALID [2022-04-07 17:34:14,793 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {470#true} {470#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {470#true} is VALID [2022-04-07 17:34:14,793 INFO L290 TraceCheckUtils]: 2: Hoare triple {470#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {470#true} is VALID [2022-04-07 17:34:14,793 INFO L290 TraceCheckUtils]: 1: Hoare triple {470#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {470#true} is VALID [2022-04-07 17:34:14,793 INFO L272 TraceCheckUtils]: 0: Hoare triple {470#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {470#true} is VALID [2022-04-07 17:34:14,793 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 17:34:14,793 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [82311215] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-07 17:34:14,793 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-07 17:34:14,793 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6, 6] total 10 [2022-04-07 17:34:14,794 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1235455575] [2022-04-07 17:34:14,794 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-07 17:34:14,794 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 2.1) internal successors, (21), 7 states have internal predecessors, (21), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-07 17:34:14,795 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 17:34:14,795 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 10 states, 10 states have (on average 2.1) internal successors, (21), 7 states have internal predecessors, (21), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:34:18,861 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 27 edges. 25 inductive. 0 not inductive. 2 times theorem prover too weak to decide inductivity. [2022-04-07 17:34:18,861 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2022-04-07 17:34:18,862 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 17:34:18,862 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2022-04-07 17:34:18,862 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=68, Unknown=1, NotChecked=0, Total=90 [2022-04-07 17:34:18,862 INFO L87 Difference]: Start difference. First operand 25 states and 35 transitions. Second operand has 10 states, 10 states have (on average 2.1) internal successors, (21), 7 states have internal predecessors, (21), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:34:19,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:34:19,016 INFO L93 Difference]: Finished difference Result 38 states and 55 transitions. [2022-04-07 17:34:19,016 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-04-07 17:34:19,016 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 2.1) internal successors, (21), 7 states have internal predecessors, (21), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-07 17:34:19,017 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 17:34:19,017 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 2.1) internal successors, (21), 7 states have internal predecessors, (21), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:34:19,018 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 47 transitions. [2022-04-07 17:34:19,018 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 2.1) internal successors, (21), 7 states have internal predecessors, (21), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:34:19,020 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 47 transitions. [2022-04-07 17:34:19,020 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 8 states and 47 transitions. [2022-04-07 17:34:19,086 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 47 edges. 47 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 17:34:19,090 INFO L225 Difference]: With dead ends: 38 [2022-04-07 17:34:19,090 INFO L226 Difference]: Without dead ends: 35 [2022-04-07 17:34:19,090 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 30 SyntacticMatches, 6 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 3.7s TimeCoverageRelationStatistics Valid=45, Invalid=136, Unknown=1, NotChecked=0, Total=182 [2022-04-07 17:34:19,091 INFO L913 BasicCegarLoop]: 15 mSDtfsCounter, 23 mSDsluCounter, 31 mSDsCounter, 0 mSdLazyCounter, 48 mSolverCounterSat, 11 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 23 SdHoareTripleChecker+Valid, 46 SdHoareTripleChecker+Invalid, 83 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 11 IncrementalHoareTripleChecker+Valid, 48 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 24 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-07 17:34:19,091 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [23 Valid, 46 Invalid, 83 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [11 Valid, 48 Invalid, 0 Unknown, 24 Unchecked, 0.0s Time] [2022-04-07 17:34:19,092 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35 states. [2022-04-07 17:34:19,093 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35 to 28. [2022-04-07 17:34:19,093 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 17:34:19,094 INFO L82 GeneralOperation]: Start isEquivalent. First operand 35 states. Second operand has 28 states, 23 states have (on average 1.608695652173913) internal successors, (37), 23 states have internal predecessors, (37), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:34:19,094 INFO L74 IsIncluded]: Start isIncluded. First operand 35 states. Second operand has 28 states, 23 states have (on average 1.608695652173913) internal successors, (37), 23 states have internal predecessors, (37), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:34:19,094 INFO L87 Difference]: Start difference. First operand 35 states. Second operand has 28 states, 23 states have (on average 1.608695652173913) internal successors, (37), 23 states have internal predecessors, (37), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:34:19,100 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:34:19,100 INFO L93 Difference]: Finished difference Result 35 states and 52 transitions. [2022-04-07 17:34:19,100 INFO L276 IsEmpty]: Start isEmpty. Operand 35 states and 52 transitions. [2022-04-07 17:34:19,102 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:34:19,102 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:34:19,102 INFO L74 IsIncluded]: Start isIncluded. First operand has 28 states, 23 states have (on average 1.608695652173913) internal successors, (37), 23 states have internal predecessors, (37), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 35 states. [2022-04-07 17:34:19,102 INFO L87 Difference]: Start difference. First operand has 28 states, 23 states have (on average 1.608695652173913) internal successors, (37), 23 states have internal predecessors, (37), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 35 states. [2022-04-07 17:34:19,106 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:34:19,106 INFO L93 Difference]: Finished difference Result 35 states and 52 transitions. [2022-04-07 17:34:19,106 INFO L276 IsEmpty]: Start isEmpty. Operand 35 states and 52 transitions. [2022-04-07 17:34:19,106 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:34:19,106 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:34:19,106 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 17:34:19,106 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 17:34:19,106 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 23 states have (on average 1.608695652173913) internal successors, (37), 23 states have internal predecessors, (37), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:34:19,108 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 41 transitions. [2022-04-07 17:34:19,108 INFO L78 Accepts]: Start accepts. Automaton has 28 states and 41 transitions. Word has length 18 [2022-04-07 17:34:19,108 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 17:34:19,108 INFO L478 AbstractCegarLoop]: Abstraction has 28 states and 41 transitions. [2022-04-07 17:34:19,108 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 2.1) internal successors, (21), 7 states have internal predecessors, (21), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:34:19,108 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 41 transitions. [2022-04-07 17:34:19,109 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2022-04-07 17:34:19,109 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 17:34:19,109 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 17:34:19,125 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2022-04-07 17:34:19,315 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable3 [2022-04-07 17:34:19,315 INFO L403 AbstractCegarLoop]: === Iteration 5 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 17:34:19,316 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 17:34:19,316 INFO L85 PathProgramCache]: Analyzing trace with hash 1868584369, now seen corresponding path program 1 times [2022-04-07 17:34:19,316 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 17:34:19,316 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1196370142] [2022-04-07 17:34:19,316 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:34:19,316 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 17:34:19,327 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.0))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-07 17:34:19,331 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.1))) (+ main_~z~0_9 .cse0 (* (- 4294967296) (div (+ main_~z~0_9 .cse0) 4294967296)))) 0)) [2022-04-07 17:34:19,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:34:19,352 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.2))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-07 17:34:19,356 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.3))) (+ main_~z~0_9 .cse0 (* (- 4294967296) (div (+ main_~z~0_9 .cse0) 4294967296)))) 0)) [2022-04-07 17:34:19,451 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 17:34:19,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:34:19,456 INFO L290 TraceCheckUtils]: 0: Hoare triple {746#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {734#true} is VALID [2022-04-07 17:34:19,456 INFO L290 TraceCheckUtils]: 1: Hoare triple {734#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {734#true} is VALID [2022-04-07 17:34:19,456 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {734#true} {734#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {734#true} is VALID [2022-04-07 17:34:19,457 INFO L272 TraceCheckUtils]: 0: Hoare triple {734#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {746#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 17:34:19,457 INFO L290 TraceCheckUtils]: 1: Hoare triple {746#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {734#true} is VALID [2022-04-07 17:34:19,457 INFO L290 TraceCheckUtils]: 2: Hoare triple {734#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {734#true} is VALID [2022-04-07 17:34:19,457 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {734#true} {734#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {734#true} is VALID [2022-04-07 17:34:19,457 INFO L272 TraceCheckUtils]: 4: Hoare triple {734#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {734#true} is VALID [2022-04-07 17:34:19,458 INFO L290 TraceCheckUtils]: 5: Hoare triple {734#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {739#(= main_~y~0 0)} is VALID [2022-04-07 17:34:19,458 INFO L290 TraceCheckUtils]: 6: Hoare triple {739#(= main_~y~0 0)} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {740#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:34:19,458 INFO L290 TraceCheckUtils]: 7: Hoare triple {740#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {741#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:34:19,459 INFO L290 TraceCheckUtils]: 8: Hoare triple {741#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {741#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:34:19,460 INFO L290 TraceCheckUtils]: 9: Hoare triple {741#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [112] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_5 4294967296))) (or (and (= v_main_~y~0_4 v_main_~y~0_5) (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= |v_main_#t~post9_3| |v_main_#t~post9_1|) (<= .cse0 0)) (and (= v_main_~y~0_4 (+ v_main_~y~0_5 v_main_~z~0_3 (* (- 1) v_main_~z~0_2))) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= (+ v_main_~z~0_3 v_it_3 1) v_main_~z~0_2)) (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_5 (* v_it_3 4294967295)) 4294967296)))) (< v_main_~z~0_3 v_main_~z~0_2)))) InVars {main_~y~0=v_main_~y~0_5, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {742#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:34:19,460 INFO L290 TraceCheckUtils]: 10: Hoare triple {742#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {742#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:34:19,461 INFO L290 TraceCheckUtils]: 11: Hoare triple {742#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {742#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:34:19,462 INFO L290 TraceCheckUtils]: 12: Hoare triple {742#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {742#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:34:19,462 INFO L290 TraceCheckUtils]: 13: Hoare triple {742#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {743#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:34:19,463 INFO L290 TraceCheckUtils]: 14: Hoare triple {743#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {743#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:34:19,463 INFO L272 TraceCheckUtils]: 15: Hoare triple {743#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {744#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-07 17:34:19,464 INFO L290 TraceCheckUtils]: 16: Hoare triple {744#(not (= |__VERIFIER_assert_#in~cond| 0))} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {745#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-07 17:34:19,464 INFO L290 TraceCheckUtils]: 17: Hoare triple {745#(not (= __VERIFIER_assert_~cond 0))} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {735#false} is VALID [2022-04-07 17:34:19,464 INFO L290 TraceCheckUtils]: 18: Hoare triple {735#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {735#false} is VALID [2022-04-07 17:34:19,464 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-07 17:34:19,465 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 17:34:19,465 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1196370142] [2022-04-07 17:34:19,465 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1196370142] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 17:34:19,465 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1409503911] [2022-04-07 17:34:19,465 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:34:19,465 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 17:34:19,465 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 17:34:19,472 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 17:34:19,475 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-04-07 17:34:19,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:34:19,507 INFO L263 TraceCheckSpWp]: Trace formula consists of 64 conjuncts, 11 conjunts are in the unsatisfiable core [2022-04-07 17:34:19,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:34:19,520 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 17:34:19,760 INFO L272 TraceCheckUtils]: 0: Hoare triple {734#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {734#true} is VALID [2022-04-07 17:34:19,760 INFO L290 TraceCheckUtils]: 1: Hoare triple {734#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {734#true} is VALID [2022-04-07 17:34:19,760 INFO L290 TraceCheckUtils]: 2: Hoare triple {734#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {734#true} is VALID [2022-04-07 17:34:19,760 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {734#true} {734#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {734#true} is VALID [2022-04-07 17:34:19,761 INFO L272 TraceCheckUtils]: 4: Hoare triple {734#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {734#true} is VALID [2022-04-07 17:34:19,761 INFO L290 TraceCheckUtils]: 5: Hoare triple {734#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {739#(= main_~y~0 0)} is VALID [2022-04-07 17:34:19,762 INFO L290 TraceCheckUtils]: 6: Hoare triple {739#(= main_~y~0 0)} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {740#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:34:19,762 INFO L290 TraceCheckUtils]: 7: Hoare triple {740#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {741#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:34:19,763 INFO L290 TraceCheckUtils]: 8: Hoare triple {741#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {741#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:34:19,764 INFO L290 TraceCheckUtils]: 9: Hoare triple {741#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [112] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_5 4294967296))) (or (and (= v_main_~y~0_4 v_main_~y~0_5) (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= |v_main_#t~post9_3| |v_main_#t~post9_1|) (<= .cse0 0)) (and (= v_main_~y~0_4 (+ v_main_~y~0_5 v_main_~z~0_3 (* (- 1) v_main_~z~0_2))) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= (+ v_main_~z~0_3 v_it_3 1) v_main_~z~0_2)) (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_5 (* v_it_3 4294967295)) 4294967296)))) (< v_main_~z~0_3 v_main_~z~0_2)))) InVars {main_~y~0=v_main_~y~0_5, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {742#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:34:19,764 INFO L290 TraceCheckUtils]: 10: Hoare triple {742#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {742#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:34:19,765 INFO L290 TraceCheckUtils]: 11: Hoare triple {742#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {742#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:34:19,766 INFO L290 TraceCheckUtils]: 12: Hoare triple {742#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {743#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:34:19,766 INFO L290 TraceCheckUtils]: 13: Hoare triple {743#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {743#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:34:19,767 INFO L290 TraceCheckUtils]: 14: Hoare triple {743#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {743#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:34:19,768 INFO L272 TraceCheckUtils]: 15: Hoare triple {743#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {795#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 17:34:19,768 INFO L290 TraceCheckUtils]: 16: Hoare triple {795#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {799#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 17:34:19,769 INFO L290 TraceCheckUtils]: 17: Hoare triple {799#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {735#false} is VALID [2022-04-07 17:34:19,769 INFO L290 TraceCheckUtils]: 18: Hoare triple {735#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {735#false} is VALID [2022-04-07 17:34:19,769 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 17:34:19,769 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-07 17:34:33,922 WARN L833 $PredicateComparison]: unable to prove that (forall ((aux_mod_v_main_~x~0_36_31 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_36_31) (<= aux_mod_v_main_~x~0_36_31 0) (and (forall ((aux_div_v_main_~x~0_36_31 Int) (aux_mod_v_main_~z~0_27_31 Int)) (or (<= (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)) c_main_~x~0) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 c_main_~x~0 1) (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296))) (not (< 0 (mod (+ aux_mod_v_main_~z~0_27_31 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (let ((.cse0 (< 0 (mod c_main_~y~0 4294967296)))) (and (or (not .cse0) (forall ((aux_div_v_main_~z~0_27_31 Int)) (or (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31))))) (not (< c_main_~z~0 (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31))))))) (or .cse0 (forall ((aux_div_v_main_~z~0_27_31 Int)) (not (= (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31)) c_main_~z~0)))))) (<= 4294967296 aux_mod_v_main_~z~0_27_31) (<= aux_mod_v_main_~z~0_27_31 0))) (or (forall ((aux_mod_v_main_~z~0_27_31 Int)) (or (let ((.cse1 (< 0 (mod c_main_~y~0 4294967296)))) (and (or (not .cse1) (forall ((aux_div_v_main_~z~0_27_31 Int)) (or (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31))))) (not (< c_main_~z~0 (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31))))))) (or .cse1 (forall ((aux_div_v_main_~z~0_27_31 Int)) (not (= (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31)) c_main_~z~0)))))) (< 0 aux_mod_v_main_~z~0_27_31) (< aux_mod_v_main_~z~0_27_31 0))) (forall ((aux_div_v_main_~x~0_36_31 Int)) (not (= (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)) c_main_~x~0))))))) is different from false [2022-04-07 17:34:38,290 WARN L855 $PredicateComparison]: unable to prove that (or (forall ((aux_mod_v_main_~x~0_36_31 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_36_31) (and (or (forall ((aux_mod_v_main_~z~0_27_31 Int)) (or (let ((.cse0 (< 0 (mod c_main_~y~0 4294967296)))) (and (or (not .cse0) (forall ((aux_div_v_main_~z~0_27_31 Int)) (or (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31))))) (not (< c_main_~z~0 (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31))))))) (or .cse0 (forall ((aux_div_v_main_~z~0_27_31 Int)) (not (= (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31)) c_main_~z~0)))))) (< 0 aux_mod_v_main_~z~0_27_31) (< aux_mod_v_main_~z~0_27_31 0))) (forall ((aux_div_v_main_~x~0_36_31 Int)) (not (= (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)) c_main_~x~0)))) (forall ((aux_div_v_main_~x~0_36_31 Int) (aux_mod_v_main_~z~0_27_31 Int)) (or (<= (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)) c_main_~x~0) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 c_main_~x~0 1) (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296))) (not (< 0 (mod (+ aux_mod_v_main_~z~0_27_31 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (<= 4294967296 aux_mod_v_main_~z~0_27_31) (not (< 0 (mod c_main_~y~0 4294967296))) (<= aux_mod_v_main_~z~0_27_31 0) (forall ((aux_div_v_main_~z~0_27_31 Int)) (or (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31))))) (not (< c_main_~z~0 (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31))))))))) (<= aux_mod_v_main_~x~0_36_31 0))) (< 0 (mod c_main_~z~0 4294967296))) is different from true [2022-04-07 17:34:40,744 INFO L290 TraceCheckUtils]: 18: Hoare triple {735#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {735#false} is VALID [2022-04-07 17:34:40,745 INFO L290 TraceCheckUtils]: 17: Hoare triple {799#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {735#false} is VALID [2022-04-07 17:34:40,745 INFO L290 TraceCheckUtils]: 16: Hoare triple {795#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {799#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 17:34:40,746 INFO L272 TraceCheckUtils]: 15: Hoare triple {743#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {795#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 17:34:40,746 INFO L290 TraceCheckUtils]: 14: Hoare triple {743#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {743#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:34:40,747 INFO L290 TraceCheckUtils]: 13: Hoare triple {743#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {743#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:34:42,778 WARN L290 TraceCheckUtils]: 12: Hoare triple {824#(forall ((aux_mod_v_main_~x~0_36_31 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_36_31) (and (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~x~0_36_31 Int)) (or (not (< main_~x~0 (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5)))))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~x~0_36_31 Int)) (not (= (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)) main_~x~0))))) (<= aux_mod_v_main_~x~0_36_31 0)))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {743#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is UNKNOWN [2022-04-07 17:34:44,783 WARN L290 TraceCheckUtils]: 11: Hoare triple {824#(forall ((aux_mod_v_main_~x~0_36_31 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_36_31) (and (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~x~0_36_31 Int)) (or (not (< main_~x~0 (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5)))))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~x~0_36_31 Int)) (not (= (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)) main_~x~0))))) (<= aux_mod_v_main_~x~0_36_31 0)))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {824#(forall ((aux_mod_v_main_~x~0_36_31 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_36_31) (and (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~x~0_36_31 Int)) (or (not (< main_~x~0 (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5)))))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~x~0_36_31 Int)) (not (= (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)) main_~x~0))))) (<= aux_mod_v_main_~x~0_36_31 0)))} is UNKNOWN [2022-04-07 17:34:46,790 WARN L290 TraceCheckUtils]: 10: Hoare triple {824#(forall ((aux_mod_v_main_~x~0_36_31 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_36_31) (and (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~x~0_36_31 Int)) (or (not (< main_~x~0 (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5)))))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~x~0_36_31 Int)) (not (= (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)) main_~x~0))))) (<= aux_mod_v_main_~x~0_36_31 0)))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {824#(forall ((aux_mod_v_main_~x~0_36_31 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_36_31) (and (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~x~0_36_31 Int)) (or (not (< main_~x~0 (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5)))))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~x~0_36_31 Int)) (not (= (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)) main_~x~0))))) (<= aux_mod_v_main_~x~0_36_31 0)))} is UNKNOWN [2022-04-07 17:34:48,800 WARN L290 TraceCheckUtils]: 9: Hoare triple {834#(forall ((aux_mod_v_main_~x~0_36_31 Int)) (or (and (forall ((aux_div_v_main_~x~0_36_31 Int) (aux_mod_v_main_~z~0_27_31 Int)) (or (<= (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)) main_~x~0) (<= 4294967296 aux_mod_v_main_~z~0_27_31) (and (or (forall ((aux_div_v_main_~z~0_27_31 Int)) (not (= (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31)) main_~z~0))) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~z~0_27_31 Int)) (or (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (not (< main_~z~0 (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31)))))))) (<= aux_mod_v_main_~z~0_27_31 0) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~z~0_27_31 (* v_it_5 4294967295)) 4294967296))) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296))) (<= 1 v_it_5))))) (or (forall ((aux_mod_v_main_~z~0_27_31 Int)) (or (< 0 aux_mod_v_main_~z~0_27_31) (and (or (forall ((aux_div_v_main_~z~0_27_31 Int)) (not (= (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31)) main_~z~0))) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~z~0_27_31 Int)) (or (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (not (< main_~z~0 (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31)))))))) (< aux_mod_v_main_~z~0_27_31 0))) (forall ((aux_div_v_main_~x~0_36_31 Int)) (not (= (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)) main_~x~0))))) (<= 4294967296 aux_mod_v_main_~x~0_36_31) (<= aux_mod_v_main_~x~0_36_31 0)))} [112] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_5 4294967296))) (or (and (= v_main_~y~0_4 v_main_~y~0_5) (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= |v_main_#t~post9_3| |v_main_#t~post9_1|) (<= .cse0 0)) (and (= v_main_~y~0_4 (+ v_main_~y~0_5 v_main_~z~0_3 (* (- 1) v_main_~z~0_2))) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= (+ v_main_~z~0_3 v_it_3 1) v_main_~z~0_2)) (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_5 (* v_it_3 4294967295)) 4294967296)))) (< v_main_~z~0_3 v_main_~z~0_2)))) InVars {main_~y~0=v_main_~y~0_5, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {824#(forall ((aux_mod_v_main_~x~0_36_31 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_36_31) (and (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~x~0_36_31 Int)) (or (not (< main_~x~0 (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5)))))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~x~0_36_31 Int)) (not (= (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)) main_~x~0))))) (<= aux_mod_v_main_~x~0_36_31 0)))} is UNKNOWN [2022-04-07 17:34:50,814 WARN L290 TraceCheckUtils]: 8: Hoare triple {838#(or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_mod_v_main_~x~0_36_31 Int)) (or (and (forall ((aux_div_v_main_~x~0_36_31 Int) (aux_mod_v_main_~z~0_27_31 Int)) (or (<= (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)) main_~x~0) (not (< 0 (mod main_~y~0 4294967296))) (<= 4294967296 aux_mod_v_main_~z~0_27_31) (forall ((aux_div_v_main_~z~0_27_31 Int)) (or (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (not (< main_~z~0 (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31)))))) (<= aux_mod_v_main_~z~0_27_31 0) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~z~0_27_31 (* v_it_5 4294967295)) 4294967296))) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296))) (<= 1 v_it_5))))) (or (forall ((aux_mod_v_main_~z~0_27_31 Int)) (or (< 0 aux_mod_v_main_~z~0_27_31) (and (or (forall ((aux_div_v_main_~z~0_27_31 Int)) (not (= (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31)) main_~z~0))) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~z~0_27_31 Int)) (or (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (not (< main_~z~0 (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31)))))))) (< aux_mod_v_main_~z~0_27_31 0))) (forall ((aux_div_v_main_~x~0_36_31 Int)) (not (= (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)) main_~x~0))))) (<= 4294967296 aux_mod_v_main_~x~0_36_31) (<= aux_mod_v_main_~x~0_36_31 0))))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {834#(forall ((aux_mod_v_main_~x~0_36_31 Int)) (or (and (forall ((aux_div_v_main_~x~0_36_31 Int) (aux_mod_v_main_~z~0_27_31 Int)) (or (<= (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)) main_~x~0) (<= 4294967296 aux_mod_v_main_~z~0_27_31) (and (or (forall ((aux_div_v_main_~z~0_27_31 Int)) (not (= (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31)) main_~z~0))) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~z~0_27_31 Int)) (or (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (not (< main_~z~0 (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31)))))))) (<= aux_mod_v_main_~z~0_27_31 0) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~z~0_27_31 (* v_it_5 4294967295)) 4294967296))) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296))) (<= 1 v_it_5))))) (or (forall ((aux_mod_v_main_~z~0_27_31 Int)) (or (< 0 aux_mod_v_main_~z~0_27_31) (and (or (forall ((aux_div_v_main_~z~0_27_31 Int)) (not (= (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31)) main_~z~0))) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~z~0_27_31 Int)) (or (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (not (< main_~z~0 (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31)))))))) (< aux_mod_v_main_~z~0_27_31 0))) (forall ((aux_div_v_main_~x~0_36_31 Int)) (not (= (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)) main_~x~0))))) (<= 4294967296 aux_mod_v_main_~x~0_36_31) (<= aux_mod_v_main_~x~0_36_31 0)))} is UNKNOWN [2022-04-07 17:34:50,818 INFO L290 TraceCheckUtils]: 7: Hoare triple {842#(or (<= (div (* (- 1) main_~x~0) (- 4294967296)) (+ (div (+ main_~x~0 (- 4294967296)) 4294967296) 1)) (< 0 (mod main_~y~0 4294967296)))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {838#(or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_mod_v_main_~x~0_36_31 Int)) (or (and (forall ((aux_div_v_main_~x~0_36_31 Int) (aux_mod_v_main_~z~0_27_31 Int)) (or (<= (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)) main_~x~0) (not (< 0 (mod main_~y~0 4294967296))) (<= 4294967296 aux_mod_v_main_~z~0_27_31) (forall ((aux_div_v_main_~z~0_27_31 Int)) (or (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (not (< main_~z~0 (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31)))))) (<= aux_mod_v_main_~z~0_27_31 0) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~z~0_27_31 (* v_it_5 4294967295)) 4294967296))) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296))) (<= 1 v_it_5))))) (or (forall ((aux_mod_v_main_~z~0_27_31 Int)) (or (< 0 aux_mod_v_main_~z~0_27_31) (and (or (forall ((aux_div_v_main_~z~0_27_31 Int)) (not (= (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31)) main_~z~0))) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~z~0_27_31 Int)) (or (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (not (< main_~z~0 (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31)))))))) (< aux_mod_v_main_~z~0_27_31 0))) (forall ((aux_div_v_main_~x~0_36_31 Int)) (not (= (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)) main_~x~0))))) (<= 4294967296 aux_mod_v_main_~x~0_36_31) (<= aux_mod_v_main_~x~0_36_31 0))))} is VALID [2022-04-07 17:34:50,819 INFO L290 TraceCheckUtils]: 6: Hoare triple {734#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {842#(or (<= (div (* (- 1) main_~x~0) (- 4294967296)) (+ (div (+ main_~x~0 (- 4294967296)) 4294967296) 1)) (< 0 (mod main_~y~0 4294967296)))} is VALID [2022-04-07 17:34:50,819 INFO L290 TraceCheckUtils]: 5: Hoare triple {734#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {734#true} is VALID [2022-04-07 17:34:50,819 INFO L272 TraceCheckUtils]: 4: Hoare triple {734#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {734#true} is VALID [2022-04-07 17:34:50,819 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {734#true} {734#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {734#true} is VALID [2022-04-07 17:34:50,819 INFO L290 TraceCheckUtils]: 2: Hoare triple {734#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {734#true} is VALID [2022-04-07 17:34:50,819 INFO L290 TraceCheckUtils]: 1: Hoare triple {734#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {734#true} is VALID [2022-04-07 17:34:50,820 INFO L272 TraceCheckUtils]: 0: Hoare triple {734#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {734#true} is VALID [2022-04-07 17:34:50,820 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 1 not checked. [2022-04-07 17:34:50,820 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1409503911] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-07 17:34:50,820 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-07 17:34:50,820 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9, 9] total 16 [2022-04-07 17:34:50,820 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [967240620] [2022-04-07 17:34:50,820 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-07 17:34:50,821 INFO L78 Accepts]: Start accepts. Automaton has has 16 states, 16 states have (on average 1.75) internal successors, (28), 13 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 19 [2022-04-07 17:34:50,821 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 17:34:50,821 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 16 states, 16 states have (on average 1.75) internal successors, (28), 13 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:34:57,028 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 34 edges. 31 inductive. 0 not inductive. 3 times theorem prover too weak to decide inductivity. [2022-04-07 17:34:57,028 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 16 states [2022-04-07 17:34:57,028 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 17:34:57,029 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2022-04-07 17:34:57,029 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=44, Invalid=141, Unknown=5, NotChecked=50, Total=240 [2022-04-07 17:34:57,029 INFO L87 Difference]: Start difference. First operand 28 states and 41 transitions. Second operand has 16 states, 16 states have (on average 1.75) internal successors, (28), 13 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:35:05,556 WARN L232 SmtUtils]: Spent 6.30s on a formula simplification that was a NOOP. DAG size: 87 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-07 17:35:07,604 WARN L833 $PredicateComparison]: unable to prove that (and (= |c_#NULL.base| |c_old(#NULL.base)|) (forall ((aux_mod_v_main_~x~0_36_31 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_36_31) (<= aux_mod_v_main_~x~0_36_31 0) (and (forall ((aux_div_v_main_~x~0_36_31 Int) (aux_mod_v_main_~z~0_27_31 Int)) (or (<= (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)) c_main_~x~0) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 c_main_~x~0 1) (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296))) (not (< 0 (mod (+ aux_mod_v_main_~z~0_27_31 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (let ((.cse0 (< 0 (mod c_main_~y~0 4294967296)))) (and (or (not .cse0) (forall ((aux_div_v_main_~z~0_27_31 Int)) (or (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31))))) (not (< c_main_~z~0 (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31))))))) (or .cse0 (forall ((aux_div_v_main_~z~0_27_31 Int)) (not (= (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31)) c_main_~z~0)))))) (<= 4294967296 aux_mod_v_main_~z~0_27_31) (<= aux_mod_v_main_~z~0_27_31 0))) (or (forall ((aux_mod_v_main_~z~0_27_31 Int)) (or (let ((.cse1 (< 0 (mod c_main_~y~0 4294967296)))) (and (or (not .cse1) (forall ((aux_div_v_main_~z~0_27_31 Int)) (or (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31))))) (not (< c_main_~z~0 (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31))))))) (or .cse1 (forall ((aux_div_v_main_~z~0_27_31 Int)) (not (= (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31)) c_main_~z~0)))))) (< 0 aux_mod_v_main_~z~0_27_31) (< aux_mod_v_main_~z~0_27_31 0))) (forall ((aux_div_v_main_~x~0_36_31 Int)) (not (= (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)) c_main_~x~0))))))) (= |c_#NULL.offset| |c_old(#NULL.offset)|)) is different from false [2022-04-07 17:35:23,191 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:35:23,191 INFO L93 Difference]: Finished difference Result 59 states and 91 transitions. [2022-04-07 17:35:23,191 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2022-04-07 17:35:23,191 INFO L78 Accepts]: Start accepts. Automaton has has 16 states, 16 states have (on average 1.75) internal successors, (28), 13 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 19 [2022-04-07 17:35:23,192 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 17:35:23,192 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 1.75) internal successors, (28), 13 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:35:23,194 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 72 transitions. [2022-04-07 17:35:23,194 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 1.75) internal successors, (28), 13 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:35:23,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 72 transitions. [2022-04-07 17:35:23,196 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 18 states and 72 transitions. [2022-04-07 17:35:29,358 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 72 edges. 69 inductive. 0 not inductive. 3 times theorem prover too weak to decide inductivity. [2022-04-07 17:35:29,359 INFO L225 Difference]: With dead ends: 59 [2022-04-07 17:35:29,359 INFO L226 Difference]: Without dead ends: 55 [2022-04-07 17:35:29,360 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 64 GetRequests, 33 SyntacticMatches, 5 SemanticMatches, 26 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 131 ImplicationChecksByTransitivity, 34.8s TimeCoverageRelationStatistics Valid=131, Invalid=469, Unknown=12, NotChecked=144, Total=756 [2022-04-07 17:35:29,361 INFO L913 BasicCegarLoop]: 11 mSDtfsCounter, 45 mSDsluCounter, 48 mSDsCounter, 0 mSdLazyCounter, 71 mSolverCounterSat, 13 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 45 SdHoareTripleChecker+Valid, 59 SdHoareTripleChecker+Invalid, 165 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 13 IncrementalHoareTripleChecker+Valid, 71 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 81 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-07 17:35:29,361 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [45 Valid, 59 Invalid, 165 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [13 Valid, 71 Invalid, 0 Unknown, 81 Unchecked, 0.1s Time] [2022-04-07 17:35:29,361 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55 states. [2022-04-07 17:35:29,364 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55 to 37. [2022-04-07 17:35:29,364 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 17:35:29,365 INFO L82 GeneralOperation]: Start isEquivalent. First operand 55 states. Second operand has 37 states, 32 states have (on average 1.6875) internal successors, (54), 32 states have internal predecessors, (54), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:35:29,365 INFO L74 IsIncluded]: Start isIncluded. First operand 55 states. Second operand has 37 states, 32 states have (on average 1.6875) internal successors, (54), 32 states have internal predecessors, (54), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:35:29,365 INFO L87 Difference]: Start difference. First operand 55 states. Second operand has 37 states, 32 states have (on average 1.6875) internal successors, (54), 32 states have internal predecessors, (54), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:35:29,367 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:35:29,367 INFO L93 Difference]: Finished difference Result 55 states and 86 transitions. [2022-04-07 17:35:29,367 INFO L276 IsEmpty]: Start isEmpty. Operand 55 states and 86 transitions. [2022-04-07 17:35:29,367 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:35:29,368 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:35:29,368 INFO L74 IsIncluded]: Start isIncluded. First operand has 37 states, 32 states have (on average 1.6875) internal successors, (54), 32 states have internal predecessors, (54), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 55 states. [2022-04-07 17:35:29,368 INFO L87 Difference]: Start difference. First operand has 37 states, 32 states have (on average 1.6875) internal successors, (54), 32 states have internal predecessors, (54), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 55 states. [2022-04-07 17:35:29,370 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:35:29,370 INFO L93 Difference]: Finished difference Result 55 states and 86 transitions. [2022-04-07 17:35:29,370 INFO L276 IsEmpty]: Start isEmpty. Operand 55 states and 86 transitions. [2022-04-07 17:35:29,370 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:35:29,370 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:35:29,370 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 17:35:29,370 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 17:35:29,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37 states, 32 states have (on average 1.6875) internal successors, (54), 32 states have internal predecessors, (54), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:35:29,372 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 58 transitions. [2022-04-07 17:35:29,372 INFO L78 Accepts]: Start accepts. Automaton has 37 states and 58 transitions. Word has length 19 [2022-04-07 17:35:29,372 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 17:35:29,372 INFO L478 AbstractCegarLoop]: Abstraction has 37 states and 58 transitions. [2022-04-07 17:35:29,372 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 16 states, 16 states have (on average 1.75) internal successors, (28), 13 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:35:29,372 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 58 transitions. [2022-04-07 17:35:29,373 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2022-04-07 17:35:29,373 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 17:35:29,373 INFO L499 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 17:35:29,399 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2022-04-07 17:35:29,573 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4,4 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 17:35:29,574 INFO L403 AbstractCegarLoop]: === Iteration 6 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 17:35:29,574 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 17:35:29,574 INFO L85 PathProgramCache]: Analyzing trace with hash 353225841, now seen corresponding path program 2 times [2022-04-07 17:35:29,574 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 17:35:29,574 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [252182638] [2022-04-07 17:35:29,574 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:35:29,574 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 17:35:29,586 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.0))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-07 17:35:29,595 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.1))) (+ main_~y~0_12 .cse0 (* (- 4294967296) (div (+ main_~y~0_12 .cse0) 4294967296)))) 0)) [2022-04-07 17:35:29,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:35:29,616 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.5))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-07 17:35:29,620 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.6))) (+ main_~y~0_12 .cse0 (* (- 4294967296) (div (+ main_~y~0_12 .cse0) 4294967296)))) 0)) [2022-04-07 17:35:29,700 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 17:35:29,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:35:29,705 INFO L290 TraceCheckUtils]: 0: Hoare triple {1109#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1099#true} is VALID [2022-04-07 17:35:29,705 INFO L290 TraceCheckUtils]: 1: Hoare triple {1099#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1099#true} is VALID [2022-04-07 17:35:29,705 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1099#true} {1099#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1099#true} is VALID [2022-04-07 17:35:29,706 INFO L272 TraceCheckUtils]: 0: Hoare triple {1099#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1109#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 17:35:29,706 INFO L290 TraceCheckUtils]: 1: Hoare triple {1109#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1099#true} is VALID [2022-04-07 17:35:29,706 INFO L290 TraceCheckUtils]: 2: Hoare triple {1099#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1099#true} is VALID [2022-04-07 17:35:29,706 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1099#true} {1099#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1099#true} is VALID [2022-04-07 17:35:29,707 INFO L272 TraceCheckUtils]: 4: Hoare triple {1099#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1099#true} is VALID [2022-04-07 17:35:29,707 INFO L290 TraceCheckUtils]: 5: Hoare triple {1099#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1104#(= main_~y~0 0)} is VALID [2022-04-07 17:35:29,708 INFO L290 TraceCheckUtils]: 6: Hoare triple {1104#(= main_~y~0 0)} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1105#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:35:29,708 INFO L290 TraceCheckUtils]: 7: Hoare triple {1105#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1105#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:35:29,709 INFO L290 TraceCheckUtils]: 8: Hoare triple {1105#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1105#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:35:29,709 INFO L290 TraceCheckUtils]: 9: Hoare triple {1105#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1105#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:35:29,710 INFO L290 TraceCheckUtils]: 10: Hoare triple {1105#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {1105#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:35:29,710 INFO L290 TraceCheckUtils]: 11: Hoare triple {1105#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1105#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:35:29,711 INFO L290 TraceCheckUtils]: 12: Hoare triple {1105#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {1105#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:35:29,712 INFO L290 TraceCheckUtils]: 13: Hoare triple {1105#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {1105#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:35:29,713 INFO L290 TraceCheckUtils]: 14: Hoare triple {1105#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {1106#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:35:29,714 INFO L272 TraceCheckUtils]: 15: Hoare triple {1106#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {1107#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-07 17:35:29,714 INFO L290 TraceCheckUtils]: 16: Hoare triple {1107#(not (= |__VERIFIER_assert_#in~cond| 0))} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1108#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-07 17:35:29,714 INFO L290 TraceCheckUtils]: 17: Hoare triple {1108#(not (= __VERIFIER_assert_~cond 0))} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1100#false} is VALID [2022-04-07 17:35:29,714 INFO L290 TraceCheckUtils]: 18: Hoare triple {1100#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1100#false} is VALID [2022-04-07 17:35:29,715 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2022-04-07 17:35:29,715 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 17:35:29,715 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [252182638] [2022-04-07 17:35:29,715 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [252182638] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-07 17:35:29,715 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-07 17:35:29,715 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2022-04-07 17:35:29,715 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1355552635] [2022-04-07 17:35:29,715 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-07 17:35:29,716 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 7 states have (on average 2.0) internal successors, (14), 6 states have internal predecessors, (14), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 19 [2022-04-07 17:35:29,716 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 17:35:29,716 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 8 states, 7 states have (on average 2.0) internal successors, (14), 6 states have internal predecessors, (14), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:35:29,729 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 18 edges. 18 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 17:35:29,729 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-04-07 17:35:29,729 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 17:35:29,729 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-04-07 17:35:29,730 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2022-04-07 17:35:29,730 INFO L87 Difference]: Start difference. First operand 37 states and 58 transitions. Second operand has 8 states, 7 states have (on average 2.0) internal successors, (14), 6 states have internal predecessors, (14), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:35:29,895 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:35:29,895 INFO L93 Difference]: Finished difference Result 52 states and 80 transitions. [2022-04-07 17:35:29,895 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-04-07 17:35:29,895 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 7 states have (on average 2.0) internal successors, (14), 6 states have internal predecessors, (14), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 19 [2022-04-07 17:35:29,895 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 17:35:29,896 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 7 states have (on average 2.0) internal successors, (14), 6 states have internal predecessors, (14), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:35:29,897 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 55 transitions. [2022-04-07 17:35:29,897 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 7 states have (on average 2.0) internal successors, (14), 6 states have internal predecessors, (14), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:35:29,898 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 55 transitions. [2022-04-07 17:35:29,899 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 9 states and 55 transitions. [2022-04-07 17:35:29,954 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 55 edges. 55 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 17:35:29,955 INFO L225 Difference]: With dead ends: 52 [2022-04-07 17:35:29,955 INFO L226 Difference]: Without dead ends: 46 [2022-04-07 17:35:29,956 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=41, Invalid=115, Unknown=0, NotChecked=0, Total=156 [2022-04-07 17:35:29,957 INFO L913 BasicCegarLoop]: 13 mSDtfsCounter, 31 mSDsluCounter, 34 mSDsCounter, 0 mSdLazyCounter, 69 mSolverCounterSat, 14 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 31 SdHoareTripleChecker+Valid, 47 SdHoareTripleChecker+Invalid, 89 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 14 IncrementalHoareTripleChecker+Valid, 69 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 6 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-07 17:35:29,958 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [31 Valid, 47 Invalid, 89 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [14 Valid, 69 Invalid, 0 Unknown, 6 Unchecked, 0.1s Time] [2022-04-07 17:35:29,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46 states. [2022-04-07 17:35:29,960 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46 to 39. [2022-04-07 17:35:29,960 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 17:35:29,961 INFO L82 GeneralOperation]: Start isEquivalent. First operand 46 states. Second operand has 39 states, 34 states have (on average 1.6764705882352942) internal successors, (57), 34 states have internal predecessors, (57), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:35:29,961 INFO L74 IsIncluded]: Start isIncluded. First operand 46 states. Second operand has 39 states, 34 states have (on average 1.6764705882352942) internal successors, (57), 34 states have internal predecessors, (57), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:35:29,961 INFO L87 Difference]: Start difference. First operand 46 states. Second operand has 39 states, 34 states have (on average 1.6764705882352942) internal successors, (57), 34 states have internal predecessors, (57), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:35:29,963 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:35:29,963 INFO L93 Difference]: Finished difference Result 46 states and 73 transitions. [2022-04-07 17:35:29,963 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 73 transitions. [2022-04-07 17:35:29,963 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:35:29,963 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:35:29,963 INFO L74 IsIncluded]: Start isIncluded. First operand has 39 states, 34 states have (on average 1.6764705882352942) internal successors, (57), 34 states have internal predecessors, (57), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 46 states. [2022-04-07 17:35:29,964 INFO L87 Difference]: Start difference. First operand has 39 states, 34 states have (on average 1.6764705882352942) internal successors, (57), 34 states have internal predecessors, (57), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 46 states. [2022-04-07 17:35:29,965 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:35:29,965 INFO L93 Difference]: Finished difference Result 46 states and 73 transitions. [2022-04-07 17:35:29,965 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 73 transitions. [2022-04-07 17:35:29,966 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:35:29,966 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:35:29,966 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 17:35:29,966 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 17:35:29,966 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39 states, 34 states have (on average 1.6764705882352942) internal successors, (57), 34 states have internal predecessors, (57), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:35:29,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 61 transitions. [2022-04-07 17:35:29,967 INFO L78 Accepts]: Start accepts. Automaton has 39 states and 61 transitions. Word has length 19 [2022-04-07 17:35:29,967 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 17:35:29,967 INFO L478 AbstractCegarLoop]: Abstraction has 39 states and 61 transitions. [2022-04-07 17:35:29,967 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 7 states have (on average 2.0) internal successors, (14), 6 states have internal predecessors, (14), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:35:29,968 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 61 transitions. [2022-04-07 17:35:29,968 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2022-04-07 17:35:29,968 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 17:35:29,968 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 17:35:29,968 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5 [2022-04-07 17:35:29,968 INFO L403 AbstractCegarLoop]: === Iteration 7 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 17:35:29,969 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 17:35:29,969 INFO L85 PathProgramCache]: Analyzing trace with hash -1453978548, now seen corresponding path program 1 times [2022-04-07 17:35:29,969 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 17:35:29,969 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1430828853] [2022-04-07 17:35:29,969 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:35:29,969 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 17:35:29,984 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.0))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-07 17:35:29,985 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.1))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-07 17:35:29,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:35:29,997 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.5))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-07 17:35:30,000 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.6))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-07 17:35:30,089 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 17:35:30,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:35:30,096 INFO L290 TraceCheckUtils]: 0: Hoare triple {1316#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1305#true} is VALID [2022-04-07 17:35:30,097 INFO L290 TraceCheckUtils]: 1: Hoare triple {1305#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1305#true} is VALID [2022-04-07 17:35:30,097 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1305#true} {1305#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1305#true} is VALID [2022-04-07 17:35:30,097 INFO L272 TraceCheckUtils]: 0: Hoare triple {1305#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1316#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 17:35:30,098 INFO L290 TraceCheckUtils]: 1: Hoare triple {1316#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1305#true} is VALID [2022-04-07 17:35:30,098 INFO L290 TraceCheckUtils]: 2: Hoare triple {1305#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1305#true} is VALID [2022-04-07 17:35:30,098 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1305#true} {1305#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1305#true} is VALID [2022-04-07 17:35:30,098 INFO L272 TraceCheckUtils]: 4: Hoare triple {1305#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1305#true} is VALID [2022-04-07 17:35:30,098 INFO L290 TraceCheckUtils]: 5: Hoare triple {1305#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1305#true} is VALID [2022-04-07 17:35:30,104 INFO L290 TraceCheckUtils]: 6: Hoare triple {1305#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1310#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:35:30,105 INFO L290 TraceCheckUtils]: 7: Hoare triple {1310#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1310#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:35:30,106 INFO L290 TraceCheckUtils]: 8: Hoare triple {1310#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1311#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-07 17:35:30,107 INFO L290 TraceCheckUtils]: 9: Hoare triple {1311#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1312#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-07 17:35:30,107 INFO L290 TraceCheckUtils]: 10: Hoare triple {1312#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {1312#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-07 17:35:30,110 INFO L290 TraceCheckUtils]: 11: Hoare triple {1312#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {1313#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:35:30,111 INFO L290 TraceCheckUtils]: 12: Hoare triple {1313#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1313#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:35:30,112 INFO L290 TraceCheckUtils]: 13: Hoare triple {1313#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {1310#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:35:30,113 INFO L290 TraceCheckUtils]: 14: Hoare triple {1310#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {1310#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:35:30,114 INFO L272 TraceCheckUtils]: 15: Hoare triple {1310#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {1314#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-07 17:35:30,116 INFO L290 TraceCheckUtils]: 16: Hoare triple {1314#(not (= |__VERIFIER_assert_#in~cond| 0))} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1315#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-07 17:35:30,117 INFO L290 TraceCheckUtils]: 17: Hoare triple {1315#(not (= __VERIFIER_assert_~cond 0))} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1306#false} is VALID [2022-04-07 17:35:30,117 INFO L290 TraceCheckUtils]: 18: Hoare triple {1306#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1306#false} is VALID [2022-04-07 17:35:30,117 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 17:35:30,118 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 17:35:30,118 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1430828853] [2022-04-07 17:35:30,118 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1430828853] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 17:35:30,118 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [998097356] [2022-04-07 17:35:30,118 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:35:30,118 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 17:35:30,118 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 17:35:30,119 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 17:35:30,154 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2022-04-07 17:35:30,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:35:30,167 INFO L263 TraceCheckSpWp]: Trace formula consists of 64 conjuncts, 8 conjunts are in the unsatisfiable core [2022-04-07 17:35:30,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:35:30,177 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 17:35:31,215 INFO L272 TraceCheckUtils]: 0: Hoare triple {1305#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1305#true} is VALID [2022-04-07 17:35:31,215 INFO L290 TraceCheckUtils]: 1: Hoare triple {1305#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1305#true} is VALID [2022-04-07 17:35:31,216 INFO L290 TraceCheckUtils]: 2: Hoare triple {1305#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1305#true} is VALID [2022-04-07 17:35:31,216 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1305#true} {1305#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1305#true} is VALID [2022-04-07 17:35:31,216 INFO L272 TraceCheckUtils]: 4: Hoare triple {1305#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1305#true} is VALID [2022-04-07 17:35:31,216 INFO L290 TraceCheckUtils]: 5: Hoare triple {1305#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1305#true} is VALID [2022-04-07 17:35:31,217 INFO L290 TraceCheckUtils]: 6: Hoare triple {1305#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1310#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:35:31,217 INFO L290 TraceCheckUtils]: 7: Hoare triple {1310#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1310#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:35:31,218 INFO L290 TraceCheckUtils]: 8: Hoare triple {1310#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1311#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-07 17:35:31,218 INFO L290 TraceCheckUtils]: 9: Hoare triple {1311#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1312#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-07 17:35:31,219 INFO L290 TraceCheckUtils]: 10: Hoare triple {1312#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {1312#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-07 17:35:31,221 INFO L290 TraceCheckUtils]: 11: Hoare triple {1312#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {1313#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:35:31,221 INFO L290 TraceCheckUtils]: 12: Hoare triple {1313#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1313#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:35:31,223 INFO L290 TraceCheckUtils]: 13: Hoare triple {1313#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {1310#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:35:31,223 INFO L290 TraceCheckUtils]: 14: Hoare triple {1310#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {1310#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:35:31,224 INFO L272 TraceCheckUtils]: 15: Hoare triple {1310#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {1365#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 17:35:31,224 INFO L290 TraceCheckUtils]: 16: Hoare triple {1365#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1369#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 17:35:31,225 INFO L290 TraceCheckUtils]: 17: Hoare triple {1369#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1306#false} is VALID [2022-04-07 17:35:31,225 INFO L290 TraceCheckUtils]: 18: Hoare triple {1306#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1306#false} is VALID [2022-04-07 17:35:31,225 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 17:35:31,225 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-07 17:35:59,830 INFO L290 TraceCheckUtils]: 18: Hoare triple {1306#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1306#false} is VALID [2022-04-07 17:35:59,830 INFO L290 TraceCheckUtils]: 17: Hoare triple {1369#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1306#false} is VALID [2022-04-07 17:35:59,831 INFO L290 TraceCheckUtils]: 16: Hoare triple {1365#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1369#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 17:35:59,831 INFO L272 TraceCheckUtils]: 15: Hoare triple {1310#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {1365#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 17:35:59,832 INFO L290 TraceCheckUtils]: 14: Hoare triple {1310#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {1310#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:36:01,846 WARN L290 TraceCheckUtils]: 13: Hoare triple {1391#(forall ((aux_mod_v_main_~x~0_39_31 Int)) (or (<= aux_mod_v_main_~x~0_39_31 0) (<= 4294967296 aux_mod_v_main_~x~0_39_31) (and (or (forall ((aux_div_v_main_~x~0_39_31 Int)) (not (= (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296)) main_~x~0))) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~x~0_39_31 Int)) (or (not (< (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296)) main_~x~0)) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))) (<= (+ aux_mod_v_main_~x~0_39_31 v_it_6 (* aux_div_v_main_~x~0_39_31 4294967296) 1) main_~x~0)))))))))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {1310#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is UNKNOWN [2022-04-07 17:36:03,862 WARN L290 TraceCheckUtils]: 12: Hoare triple {1391#(forall ((aux_mod_v_main_~x~0_39_31 Int)) (or (<= aux_mod_v_main_~x~0_39_31 0) (<= 4294967296 aux_mod_v_main_~x~0_39_31) (and (or (forall ((aux_div_v_main_~x~0_39_31 Int)) (not (= (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296)) main_~x~0))) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~x~0_39_31 Int)) (or (not (< (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296)) main_~x~0)) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))) (<= (+ aux_mod_v_main_~x~0_39_31 v_it_6 (* aux_div_v_main_~x~0_39_31 4294967296) 1) main_~x~0)))))))))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1391#(forall ((aux_mod_v_main_~x~0_39_31 Int)) (or (<= aux_mod_v_main_~x~0_39_31 0) (<= 4294967296 aux_mod_v_main_~x~0_39_31) (and (or (forall ((aux_div_v_main_~x~0_39_31 Int)) (not (= (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296)) main_~x~0))) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~x~0_39_31 Int)) (or (not (< (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296)) main_~x~0)) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))) (<= (+ aux_mod_v_main_~x~0_39_31 v_it_6 (* aux_div_v_main_~x~0_39_31 4294967296) 1) main_~x~0)))))))))} is UNKNOWN [2022-04-07 17:36:05,874 WARN L290 TraceCheckUtils]: 11: Hoare triple {1398#(forall ((aux_mod_v_main_~x~0_39_31 Int) (v_main_~x~0_40 Int)) (or (<= aux_mod_v_main_~x~0_39_31 0) (and (or (not (< main_~x~0 v_main_~x~0_40)) (not (< 0 (mod main_~z~0 4294967296))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) v_main_~x~0_40) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5)))) (or (< 0 (mod main_~z~0 4294967296)) (not (= v_main_~x~0_40 main_~x~0)))) (<= 4294967296 aux_mod_v_main_~x~0_39_31) (and (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~x~0_39_31 Int)) (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_39_31 v_it_6 (* aux_div_v_main_~x~0_39_31 4294967296) 1) v_main_~x~0_40) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (not (< (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296)) v_main_~x~0_40))))) (or (forall ((aux_div_v_main_~x~0_39_31 Int)) (not (= v_main_~x~0_40 (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296))))) (< 0 (mod main_~y~0 4294967296))))))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {1391#(forall ((aux_mod_v_main_~x~0_39_31 Int)) (or (<= aux_mod_v_main_~x~0_39_31 0) (<= 4294967296 aux_mod_v_main_~x~0_39_31) (and (or (forall ((aux_div_v_main_~x~0_39_31 Int)) (not (= (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296)) main_~x~0))) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~x~0_39_31 Int)) (or (not (< (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296)) main_~x~0)) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))) (<= (+ aux_mod_v_main_~x~0_39_31 v_it_6 (* aux_div_v_main_~x~0_39_31 4294967296) 1) main_~x~0)))))))))} is UNKNOWN [2022-04-07 17:36:07,894 WARN L290 TraceCheckUtils]: 10: Hoare triple {1398#(forall ((aux_mod_v_main_~x~0_39_31 Int) (v_main_~x~0_40 Int)) (or (<= aux_mod_v_main_~x~0_39_31 0) (and (or (not (< main_~x~0 v_main_~x~0_40)) (not (< 0 (mod main_~z~0 4294967296))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) v_main_~x~0_40) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5)))) (or (< 0 (mod main_~z~0 4294967296)) (not (= v_main_~x~0_40 main_~x~0)))) (<= 4294967296 aux_mod_v_main_~x~0_39_31) (and (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~x~0_39_31 Int)) (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_39_31 v_it_6 (* aux_div_v_main_~x~0_39_31 4294967296) 1) v_main_~x~0_40) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (not (< (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296)) v_main_~x~0_40))))) (or (forall ((aux_div_v_main_~x~0_39_31 Int)) (not (= v_main_~x~0_40 (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296))))) (< 0 (mod main_~y~0 4294967296))))))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {1398#(forall ((aux_mod_v_main_~x~0_39_31 Int) (v_main_~x~0_40 Int)) (or (<= aux_mod_v_main_~x~0_39_31 0) (and (or (not (< main_~x~0 v_main_~x~0_40)) (not (< 0 (mod main_~z~0 4294967296))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) v_main_~x~0_40) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5)))) (or (< 0 (mod main_~z~0 4294967296)) (not (= v_main_~x~0_40 main_~x~0)))) (<= 4294967296 aux_mod_v_main_~x~0_39_31) (and (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~x~0_39_31 Int)) (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_39_31 v_it_6 (* aux_div_v_main_~x~0_39_31 4294967296) 1) v_main_~x~0_40) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (not (< (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296)) v_main_~x~0_40))))) (or (forall ((aux_div_v_main_~x~0_39_31 Int)) (not (= v_main_~x~0_40 (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296))))) (< 0 (mod main_~y~0 4294967296))))))} is UNKNOWN [2022-04-07 17:36:08,240 INFO L290 TraceCheckUtils]: 9: Hoare triple {1405#(forall ((aux_mod_v_main_~x~0_39_31 Int)) (or (<= aux_mod_v_main_~x~0_39_31 0) (and (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~x~0_39_31 Int)) (not (= (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296)) main_~x~0)))) (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~x~0_39_31 Int)) (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296))))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296)))))))) (<= 4294967296 aux_mod_v_main_~x~0_39_31)))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1398#(forall ((aux_mod_v_main_~x~0_39_31 Int) (v_main_~x~0_40 Int)) (or (<= aux_mod_v_main_~x~0_39_31 0) (and (or (not (< main_~x~0 v_main_~x~0_40)) (not (< 0 (mod main_~z~0 4294967296))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) v_main_~x~0_40) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5)))) (or (< 0 (mod main_~z~0 4294967296)) (not (= v_main_~x~0_40 main_~x~0)))) (<= 4294967296 aux_mod_v_main_~x~0_39_31) (and (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~x~0_39_31 Int)) (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_39_31 v_it_6 (* aux_div_v_main_~x~0_39_31 4294967296) 1) v_main_~x~0_40) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (not (< (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296)) v_main_~x~0_40))))) (or (forall ((aux_div_v_main_~x~0_39_31 Int)) (not (= v_main_~x~0_40 (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296))))) (< 0 (mod main_~y~0 4294967296))))))} is VALID [2022-04-07 17:36:08,242 INFO L290 TraceCheckUtils]: 8: Hoare triple {1310#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1405#(forall ((aux_mod_v_main_~x~0_39_31 Int)) (or (<= aux_mod_v_main_~x~0_39_31 0) (and (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~x~0_39_31 Int)) (not (= (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296)) main_~x~0)))) (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~x~0_39_31 Int)) (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296))))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296)))))))) (<= 4294967296 aux_mod_v_main_~x~0_39_31)))} is VALID [2022-04-07 17:36:08,242 INFO L290 TraceCheckUtils]: 7: Hoare triple {1310#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1310#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:36:08,242 INFO L290 TraceCheckUtils]: 6: Hoare triple {1305#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1310#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:36:08,242 INFO L290 TraceCheckUtils]: 5: Hoare triple {1305#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1305#true} is VALID [2022-04-07 17:36:08,243 INFO L272 TraceCheckUtils]: 4: Hoare triple {1305#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1305#true} is VALID [2022-04-07 17:36:08,243 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1305#true} {1305#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1305#true} is VALID [2022-04-07 17:36:08,243 INFO L290 TraceCheckUtils]: 2: Hoare triple {1305#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1305#true} is VALID [2022-04-07 17:36:08,243 INFO L290 TraceCheckUtils]: 1: Hoare triple {1305#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1305#true} is VALID [2022-04-07 17:36:08,243 INFO L272 TraceCheckUtils]: 0: Hoare triple {1305#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1305#true} is VALID [2022-04-07 17:36:08,243 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 17:36:08,243 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [998097356] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-07 17:36:08,243 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-07 17:36:08,243 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 8, 8] total 14 [2022-04-07 17:36:08,244 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [915708805] [2022-04-07 17:36:08,244 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-07 17:36:08,244 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 1.7142857142857142) internal successors, (24), 11 states have internal predecessors, (24), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 19 [2022-04-07 17:36:08,244 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 17:36:08,245 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 14 states, 14 states have (on average 1.7142857142857142) internal successors, (24), 11 states have internal predecessors, (24), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:36:18,368 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 30 edges. 25 inductive. 0 not inductive. 5 times theorem prover too weak to decide inductivity. [2022-04-07 17:36:18,368 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-04-07 17:36:18,368 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 17:36:18,369 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-04-07 17:36:18,369 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=135, Unknown=10, NotChecked=0, Total=182 [2022-04-07 17:36:18,369 INFO L87 Difference]: Start difference. First operand 39 states and 61 transitions. Second operand has 14 states, 14 states have (on average 1.7142857142857142) internal successors, (24), 11 states have internal predecessors, (24), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:36:18,725 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:36:18,726 INFO L93 Difference]: Finished difference Result 56 states and 86 transitions. [2022-04-07 17:36:18,726 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-04-07 17:36:18,726 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 1.7142857142857142) internal successors, (24), 11 states have internal predecessors, (24), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 19 [2022-04-07 17:36:18,726 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 17:36:18,726 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 1.7142857142857142) internal successors, (24), 11 states have internal predecessors, (24), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:36:18,728 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 48 transitions. [2022-04-07 17:36:18,728 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 1.7142857142857142) internal successors, (24), 11 states have internal predecessors, (24), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:36:18,729 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 48 transitions. [2022-04-07 17:36:18,729 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 10 states and 48 transitions. [2022-04-07 17:36:18,782 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 48 edges. 48 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 17:36:18,783 INFO L225 Difference]: With dead ends: 56 [2022-04-07 17:36:18,783 INFO L226 Difference]: Without dead ends: 53 [2022-04-07 17:36:18,783 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 54 GetRequests, 29 SyntacticMatches, 8 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 73 ImplicationChecksByTransitivity, 21.0s TimeCoverageRelationStatistics Valid=73, Invalid=259, Unknown=10, NotChecked=0, Total=342 [2022-04-07 17:36:18,784 INFO L913 BasicCegarLoop]: 18 mSDtfsCounter, 24 mSDsluCounter, 49 mSDsCounter, 0 mSdLazyCounter, 54 mSolverCounterSat, 15 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 24 SdHoareTripleChecker+Valid, 67 SdHoareTripleChecker+Invalid, 127 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 15 IncrementalHoareTripleChecker+Valid, 54 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 58 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-07 17:36:18,784 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [24 Valid, 67 Invalid, 127 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [15 Valid, 54 Invalid, 0 Unknown, 58 Unchecked, 0.0s Time] [2022-04-07 17:36:18,785 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states. [2022-04-07 17:36:18,787 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 41. [2022-04-07 17:36:18,787 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 17:36:18,787 INFO L82 GeneralOperation]: Start isEquivalent. First operand 53 states. Second operand has 41 states, 36 states have (on average 1.6944444444444444) internal successors, (61), 36 states have internal predecessors, (61), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:36:18,788 INFO L74 IsIncluded]: Start isIncluded. First operand 53 states. Second operand has 41 states, 36 states have (on average 1.6944444444444444) internal successors, (61), 36 states have internal predecessors, (61), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:36:18,788 INFO L87 Difference]: Start difference. First operand 53 states. Second operand has 41 states, 36 states have (on average 1.6944444444444444) internal successors, (61), 36 states have internal predecessors, (61), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:36:18,789 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:36:18,790 INFO L93 Difference]: Finished difference Result 53 states and 83 transitions. [2022-04-07 17:36:18,790 INFO L276 IsEmpty]: Start isEmpty. Operand 53 states and 83 transitions. [2022-04-07 17:36:18,790 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:36:18,790 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:36:18,790 INFO L74 IsIncluded]: Start isIncluded. First operand has 41 states, 36 states have (on average 1.6944444444444444) internal successors, (61), 36 states have internal predecessors, (61), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 53 states. [2022-04-07 17:36:18,790 INFO L87 Difference]: Start difference. First operand has 41 states, 36 states have (on average 1.6944444444444444) internal successors, (61), 36 states have internal predecessors, (61), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 53 states. [2022-04-07 17:36:18,792 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:36:18,792 INFO L93 Difference]: Finished difference Result 53 states and 83 transitions. [2022-04-07 17:36:18,792 INFO L276 IsEmpty]: Start isEmpty. Operand 53 states and 83 transitions. [2022-04-07 17:36:18,793 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:36:18,793 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:36:18,793 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 17:36:18,793 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 17:36:18,793 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41 states, 36 states have (on average 1.6944444444444444) internal successors, (61), 36 states have internal predecessors, (61), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:36:18,794 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 65 transitions. [2022-04-07 17:36:18,794 INFO L78 Accepts]: Start accepts. Automaton has 41 states and 65 transitions. Word has length 19 [2022-04-07 17:36:18,795 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 17:36:18,795 INFO L478 AbstractCegarLoop]: Abstraction has 41 states and 65 transitions. [2022-04-07 17:36:18,795 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 14 states have (on average 1.7142857142857142) internal successors, (24), 11 states have internal predecessors, (24), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:36:18,795 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 65 transitions. [2022-04-07 17:36:18,795 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2022-04-07 17:36:18,795 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 17:36:18,795 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 17:36:18,814 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2022-04-07 17:36:19,007 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6,5 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 17:36:19,007 INFO L403 AbstractCegarLoop]: === Iteration 8 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 17:36:19,008 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 17:36:19,008 INFO L85 PathProgramCache]: Analyzing trace with hash -1642739759, now seen corresponding path program 1 times [2022-04-07 17:36:19,008 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 17:36:19,008 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1493191924] [2022-04-07 17:36:19,008 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:36:19,008 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 17:36:19,021 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.0))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-07 17:36:19,022 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.1))) (+ main_~y~0_10 .cse0 (* (- 4294967296) (div (+ main_~y~0_10 .cse0) 4294967296)))) 0)) [2022-04-07 17:36:19,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:36:19,057 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.5))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-07 17:36:19,067 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.6))) (+ main_~y~0_10 .cse0 (* (- 4294967296) (div (+ main_~y~0_10 .cse0) 4294967296)))) 0)) [2022-04-07 17:36:19,133 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 17:36:19,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:36:19,137 INFO L290 TraceCheckUtils]: 0: Hoare triple {1659#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1649#true} is VALID [2022-04-07 17:36:19,137 INFO L290 TraceCheckUtils]: 1: Hoare triple {1649#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1649#true} is VALID [2022-04-07 17:36:19,138 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1649#true} {1649#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1649#true} is VALID [2022-04-07 17:36:19,138 INFO L272 TraceCheckUtils]: 0: Hoare triple {1649#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1659#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 17:36:19,138 INFO L290 TraceCheckUtils]: 1: Hoare triple {1659#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1649#true} is VALID [2022-04-07 17:36:19,138 INFO L290 TraceCheckUtils]: 2: Hoare triple {1649#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1649#true} is VALID [2022-04-07 17:36:19,139 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1649#true} {1649#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1649#true} is VALID [2022-04-07 17:36:19,139 INFO L272 TraceCheckUtils]: 4: Hoare triple {1649#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1649#true} is VALID [2022-04-07 17:36:19,139 INFO L290 TraceCheckUtils]: 5: Hoare triple {1649#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1654#(= main_~y~0 0)} is VALID [2022-04-07 17:36:19,140 INFO L290 TraceCheckUtils]: 6: Hoare triple {1654#(= main_~y~0 0)} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1655#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:36:19,140 INFO L290 TraceCheckUtils]: 7: Hoare triple {1655#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1655#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:36:19,141 INFO L290 TraceCheckUtils]: 8: Hoare triple {1655#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1655#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:36:19,141 INFO L290 TraceCheckUtils]: 9: Hoare triple {1655#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1655#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:36:19,143 INFO L290 TraceCheckUtils]: 10: Hoare triple {1655#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [115] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~x~0_10 v_main_~x~0_9)) (and (= (+ v_main_~x~0_10 v_main_~y~0_11 (* (- 1) v_main_~x~0_9)) v_main_~y~0_10) (< 0 .cse0) (forall ((v_it_4 Int)) (or (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_10) 4294967296)) (not (<= (+ v_main_~x~0_9 v_it_4 1) v_main_~x~0_10)) (not (<= 1 v_it_4)))) (< v_main_~x~0_9 v_main_~x~0_10)))) InVars {main_~y~0=v_main_~y~0_11, main_~x~0=v_main_~x~0_10, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~x~0=v_main_~x~0_9, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1655#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:36:19,144 INFO L290 TraceCheckUtils]: 11: Hoare triple {1655#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {1655#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:36:19,144 INFO L290 TraceCheckUtils]: 12: Hoare triple {1655#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1655#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:36:19,145 INFO L290 TraceCheckUtils]: 13: Hoare triple {1655#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {1655#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:36:19,146 INFO L290 TraceCheckUtils]: 14: Hoare triple {1655#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {1656#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:36:19,147 INFO L272 TraceCheckUtils]: 15: Hoare triple {1656#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {1657#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-07 17:36:19,147 INFO L290 TraceCheckUtils]: 16: Hoare triple {1657#(not (= |__VERIFIER_assert_#in~cond| 0))} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1658#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-07 17:36:19,148 INFO L290 TraceCheckUtils]: 17: Hoare triple {1658#(not (= __VERIFIER_assert_~cond 0))} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1650#false} is VALID [2022-04-07 17:36:19,148 INFO L290 TraceCheckUtils]: 18: Hoare triple {1650#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1650#false} is VALID [2022-04-07 17:36:19,148 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-04-07 17:36:19,148 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 17:36:19,148 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1493191924] [2022-04-07 17:36:19,148 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1493191924] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-07 17:36:19,148 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-07 17:36:19,148 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2022-04-07 17:36:19,148 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [622772087] [2022-04-07 17:36:19,149 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-07 17:36:19,149 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 7 states have (on average 2.142857142857143) internal successors, (15), 6 states have internal predecessors, (15), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 19 [2022-04-07 17:36:19,149 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 17:36:19,149 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 8 states, 7 states have (on average 2.142857142857143) internal successors, (15), 6 states have internal predecessors, (15), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:36:19,171 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 19 edges. 19 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 17:36:19,171 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-04-07 17:36:19,171 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 17:36:19,172 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-04-07 17:36:19,172 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2022-04-07 17:36:19,172 INFO L87 Difference]: Start difference. First operand 41 states and 65 transitions. Second operand has 8 states, 7 states have (on average 2.142857142857143) internal successors, (15), 6 states have internal predecessors, (15), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:36:19,357 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:36:19,357 INFO L93 Difference]: Finished difference Result 57 states and 89 transitions. [2022-04-07 17:36:19,357 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-04-07 17:36:19,357 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 7 states have (on average 2.142857142857143) internal successors, (15), 6 states have internal predecessors, (15), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 19 [2022-04-07 17:36:19,358 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 17:36:19,358 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 7 states have (on average 2.142857142857143) internal successors, (15), 6 states have internal predecessors, (15), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:36:19,359 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 57 transitions. [2022-04-07 17:36:19,359 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 7 states have (on average 2.142857142857143) internal successors, (15), 6 states have internal predecessors, (15), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:36:19,360 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 57 transitions. [2022-04-07 17:36:19,360 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 9 states and 57 transitions. [2022-04-07 17:36:19,428 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 57 edges. 57 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 17:36:19,429 INFO L225 Difference]: With dead ends: 57 [2022-04-07 17:36:19,430 INFO L226 Difference]: Without dead ends: 52 [2022-04-07 17:36:19,430 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=41, Invalid=115, Unknown=0, NotChecked=0, Total=156 [2022-04-07 17:36:19,430 INFO L913 BasicCegarLoop]: 14 mSDtfsCounter, 33 mSDsluCounter, 27 mSDsCounter, 0 mSdLazyCounter, 54 mSolverCounterSat, 15 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 33 SdHoareTripleChecker+Valid, 41 SdHoareTripleChecker+Invalid, 75 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 15 IncrementalHoareTripleChecker+Valid, 54 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 6 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-07 17:36:19,431 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [33 Valid, 41 Invalid, 75 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [15 Valid, 54 Invalid, 0 Unknown, 6 Unchecked, 0.1s Time] [2022-04-07 17:36:19,431 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states. [2022-04-07 17:36:19,433 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 43. [2022-04-07 17:36:19,433 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 17:36:19,434 INFO L82 GeneralOperation]: Start isEquivalent. First operand 52 states. Second operand has 43 states, 38 states have (on average 1.6842105263157894) internal successors, (64), 38 states have internal predecessors, (64), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:36:19,434 INFO L74 IsIncluded]: Start isIncluded. First operand 52 states. Second operand has 43 states, 38 states have (on average 1.6842105263157894) internal successors, (64), 38 states have internal predecessors, (64), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:36:19,434 INFO L87 Difference]: Start difference. First operand 52 states. Second operand has 43 states, 38 states have (on average 1.6842105263157894) internal successors, (64), 38 states have internal predecessors, (64), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:36:19,436 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:36:19,436 INFO L93 Difference]: Finished difference Result 52 states and 83 transitions. [2022-04-07 17:36:19,436 INFO L276 IsEmpty]: Start isEmpty. Operand 52 states and 83 transitions. [2022-04-07 17:36:19,436 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:36:19,436 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:36:19,437 INFO L74 IsIncluded]: Start isIncluded. First operand has 43 states, 38 states have (on average 1.6842105263157894) internal successors, (64), 38 states have internal predecessors, (64), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 52 states. [2022-04-07 17:36:19,437 INFO L87 Difference]: Start difference. First operand has 43 states, 38 states have (on average 1.6842105263157894) internal successors, (64), 38 states have internal predecessors, (64), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 52 states. [2022-04-07 17:36:19,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:36:19,439 INFO L93 Difference]: Finished difference Result 52 states and 83 transitions. [2022-04-07 17:36:19,439 INFO L276 IsEmpty]: Start isEmpty. Operand 52 states and 83 transitions. [2022-04-07 17:36:19,439 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:36:19,439 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:36:19,439 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 17:36:19,439 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 17:36:19,439 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43 states, 38 states have (on average 1.6842105263157894) internal successors, (64), 38 states have internal predecessors, (64), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:36:19,440 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 68 transitions. [2022-04-07 17:36:19,440 INFO L78 Accepts]: Start accepts. Automaton has 43 states and 68 transitions. Word has length 19 [2022-04-07 17:36:19,440 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 17:36:19,441 INFO L478 AbstractCegarLoop]: Abstraction has 43 states and 68 transitions. [2022-04-07 17:36:19,441 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 7 states have (on average 2.142857142857143) internal successors, (15), 6 states have internal predecessors, (15), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:36:19,441 INFO L276 IsEmpty]: Start isEmpty. Operand 43 states and 68 transitions. [2022-04-07 17:36:19,442 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2022-04-07 17:36:19,442 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 17:36:19,442 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 17:36:19,442 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7 [2022-04-07 17:36:19,442 INFO L403 AbstractCegarLoop]: === Iteration 9 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 17:36:19,442 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 17:36:19,442 INFO L85 PathProgramCache]: Analyzing trace with hash -869752682, now seen corresponding path program 1 times [2022-04-07 17:36:19,442 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 17:36:19,443 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2088927144] [2022-04-07 17:36:19,443 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:36:19,443 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 17:36:19,454 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.0))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-07 17:36:19,456 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.1))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-07 17:36:19,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:36:19,482 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.5))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-07 17:36:19,484 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.6))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-07 17:36:19,541 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 17:36:19,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:36:19,546 INFO L290 TraceCheckUtils]: 0: Hoare triple {1885#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1876#true} is VALID [2022-04-07 17:36:19,546 INFO L290 TraceCheckUtils]: 1: Hoare triple {1876#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1876#true} is VALID [2022-04-07 17:36:19,546 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1876#true} {1876#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1876#true} is VALID [2022-04-07 17:36:19,546 INFO L272 TraceCheckUtils]: 0: Hoare triple {1876#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1885#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 17:36:19,547 INFO L290 TraceCheckUtils]: 1: Hoare triple {1885#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1876#true} is VALID [2022-04-07 17:36:19,547 INFO L290 TraceCheckUtils]: 2: Hoare triple {1876#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1876#true} is VALID [2022-04-07 17:36:19,547 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1876#true} {1876#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1876#true} is VALID [2022-04-07 17:36:19,547 INFO L272 TraceCheckUtils]: 4: Hoare triple {1876#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1876#true} is VALID [2022-04-07 17:36:19,547 INFO L290 TraceCheckUtils]: 5: Hoare triple {1876#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1876#true} is VALID [2022-04-07 17:36:19,547 INFO L290 TraceCheckUtils]: 6: Hoare triple {1876#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1881#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:36:19,548 INFO L290 TraceCheckUtils]: 7: Hoare triple {1881#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1881#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:36:19,548 INFO L290 TraceCheckUtils]: 8: Hoare triple {1881#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1882#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-07 17:36:19,549 INFO L290 TraceCheckUtils]: 9: Hoare triple {1882#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1882#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-07 17:36:19,550 INFO L290 TraceCheckUtils]: 10: Hoare triple {1882#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [115] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~x~0_10 v_main_~x~0_9)) (and (= (+ v_main_~x~0_10 v_main_~y~0_11 (* (- 1) v_main_~x~0_9)) v_main_~y~0_10) (< 0 .cse0) (forall ((v_it_4 Int)) (or (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_10) 4294967296)) (not (<= (+ v_main_~x~0_9 v_it_4 1) v_main_~x~0_10)) (not (<= 1 v_it_4)))) (< v_main_~x~0_9 v_main_~x~0_10)))) InVars {main_~y~0=v_main_~y~0_11, main_~x~0=v_main_~x~0_10, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~x~0=v_main_~x~0_9, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1882#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-07 17:36:19,551 INFO L290 TraceCheckUtils]: 11: Hoare triple {1882#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {1882#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-07 17:36:19,552 INFO L290 TraceCheckUtils]: 12: Hoare triple {1882#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {1881#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:36:19,552 INFO L290 TraceCheckUtils]: 13: Hoare triple {1881#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1881#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:36:19,552 INFO L290 TraceCheckUtils]: 14: Hoare triple {1881#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {1881#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:36:19,553 INFO L272 TraceCheckUtils]: 15: Hoare triple {1881#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {1883#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-07 17:36:19,553 INFO L290 TraceCheckUtils]: 16: Hoare triple {1883#(not (= |__VERIFIER_assert_#in~cond| 0))} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1884#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-07 17:36:19,553 INFO L290 TraceCheckUtils]: 17: Hoare triple {1884#(not (= __VERIFIER_assert_~cond 0))} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1877#false} is VALID [2022-04-07 17:36:19,554 INFO L290 TraceCheckUtils]: 18: Hoare triple {1877#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1877#false} is VALID [2022-04-07 17:36:19,554 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-07 17:36:19,554 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 17:36:19,554 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2088927144] [2022-04-07 17:36:19,554 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2088927144] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 17:36:19,554 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2138999277] [2022-04-07 17:36:19,554 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:36:19,554 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 17:36:19,554 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 17:36:19,555 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 17:36:19,556 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2022-04-07 17:36:19,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:36:19,586 INFO L263 TraceCheckSpWp]: Trace formula consists of 64 conjuncts, 7 conjunts are in the unsatisfiable core [2022-04-07 17:36:19,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:36:19,598 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 17:36:20,376 INFO L272 TraceCheckUtils]: 0: Hoare triple {1876#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1876#true} is VALID [2022-04-07 17:36:20,376 INFO L290 TraceCheckUtils]: 1: Hoare triple {1876#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1876#true} is VALID [2022-04-07 17:36:20,376 INFO L290 TraceCheckUtils]: 2: Hoare triple {1876#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1876#true} is VALID [2022-04-07 17:36:20,376 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1876#true} {1876#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1876#true} is VALID [2022-04-07 17:36:20,376 INFO L272 TraceCheckUtils]: 4: Hoare triple {1876#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1876#true} is VALID [2022-04-07 17:36:20,377 INFO L290 TraceCheckUtils]: 5: Hoare triple {1876#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1876#true} is VALID [2022-04-07 17:36:20,377 INFO L290 TraceCheckUtils]: 6: Hoare triple {1876#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1881#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:36:20,378 INFO L290 TraceCheckUtils]: 7: Hoare triple {1881#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1881#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:36:20,378 INFO L290 TraceCheckUtils]: 8: Hoare triple {1881#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1882#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-07 17:36:20,379 INFO L290 TraceCheckUtils]: 9: Hoare triple {1882#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1882#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-07 17:36:20,380 INFO L290 TraceCheckUtils]: 10: Hoare triple {1882#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [115] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~x~0_10 v_main_~x~0_9)) (and (= (+ v_main_~x~0_10 v_main_~y~0_11 (* (- 1) v_main_~x~0_9)) v_main_~y~0_10) (< 0 .cse0) (forall ((v_it_4 Int)) (or (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_10) 4294967296)) (not (<= (+ v_main_~x~0_9 v_it_4 1) v_main_~x~0_10)) (not (<= 1 v_it_4)))) (< v_main_~x~0_9 v_main_~x~0_10)))) InVars {main_~y~0=v_main_~y~0_11, main_~x~0=v_main_~x~0_10, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~x~0=v_main_~x~0_9, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1882#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-07 17:36:20,380 INFO L290 TraceCheckUtils]: 11: Hoare triple {1882#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {1882#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-07 17:36:20,381 INFO L290 TraceCheckUtils]: 12: Hoare triple {1882#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {1881#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:36:20,382 INFO L290 TraceCheckUtils]: 13: Hoare triple {1881#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1881#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:36:20,382 INFO L290 TraceCheckUtils]: 14: Hoare triple {1881#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {1881#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:36:20,383 INFO L272 TraceCheckUtils]: 15: Hoare triple {1881#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {1934#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 17:36:20,384 INFO L290 TraceCheckUtils]: 16: Hoare triple {1934#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1938#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 17:36:20,384 INFO L290 TraceCheckUtils]: 17: Hoare triple {1938#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1877#false} is VALID [2022-04-07 17:36:20,384 INFO L290 TraceCheckUtils]: 18: Hoare triple {1877#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1877#false} is VALID [2022-04-07 17:36:20,384 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-07 17:36:20,384 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-07 17:36:51,829 INFO L290 TraceCheckUtils]: 18: Hoare triple {1877#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1877#false} is VALID [2022-04-07 17:36:51,829 INFO L290 TraceCheckUtils]: 17: Hoare triple {1938#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1877#false} is VALID [2022-04-07 17:36:51,830 INFO L290 TraceCheckUtils]: 16: Hoare triple {1934#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1938#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 17:36:51,831 INFO L272 TraceCheckUtils]: 15: Hoare triple {1881#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {1934#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 17:36:51,831 INFO L290 TraceCheckUtils]: 14: Hoare triple {1881#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {1881#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:36:51,831 INFO L290 TraceCheckUtils]: 13: Hoare triple {1881#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1881#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:36:51,901 INFO L290 TraceCheckUtils]: 12: Hoare triple {1963#(forall ((aux_mod_v_main_~x~0_43_31 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_43_31) (and (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~x~0_43_31 Int)) (not (= (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296)) main_~x~0)))) (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~x~0_43_31 Int)) (or (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296)))))))) (<= aux_mod_v_main_~x~0_43_31 0)))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {1881#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:36:51,902 INFO L290 TraceCheckUtils]: 11: Hoare triple {1963#(forall ((aux_mod_v_main_~x~0_43_31 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_43_31) (and (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~x~0_43_31 Int)) (not (= (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296)) main_~x~0)))) (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~x~0_43_31 Int)) (or (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296)))))))) (<= aux_mod_v_main_~x~0_43_31 0)))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {1963#(forall ((aux_mod_v_main_~x~0_43_31 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_43_31) (and (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~x~0_43_31 Int)) (not (= (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296)) main_~x~0)))) (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~x~0_43_31 Int)) (or (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296)))))))) (<= aux_mod_v_main_~x~0_43_31 0)))} is VALID [2022-04-07 17:36:53,912 WARN L290 TraceCheckUtils]: 10: Hoare triple {1970#(forall ((v_main_~x~0_44 Int) (aux_mod_v_main_~x~0_43_31 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_43_31) (and (or (< 0 (mod main_~x~0 4294967296)) (not (= v_main_~x~0_44 main_~x~0))) (or (not (< 0 (mod main_~x~0 4294967296))) (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= (+ v_main_~x~0_44 v_it_4 1) main_~x~0) (<= 1 v_it_4))) (not (< v_main_~x~0_44 main_~x~0)))) (and (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~x~0_43_31 Int)) (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_main_~x~0_44 v_it_5 1) (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296))))) (not (< v_main_~x~0_44 (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296))))))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~x~0_43_31 Int)) (not (= v_main_~x~0_44 (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296))))))) (<= aux_mod_v_main_~x~0_43_31 0)))} [115] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~x~0_10 v_main_~x~0_9)) (and (= (+ v_main_~x~0_10 v_main_~y~0_11 (* (- 1) v_main_~x~0_9)) v_main_~y~0_10) (< 0 .cse0) (forall ((v_it_4 Int)) (or (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_10) 4294967296)) (not (<= (+ v_main_~x~0_9 v_it_4 1) v_main_~x~0_10)) (not (<= 1 v_it_4)))) (< v_main_~x~0_9 v_main_~x~0_10)))) InVars {main_~y~0=v_main_~y~0_11, main_~x~0=v_main_~x~0_10, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~x~0=v_main_~x~0_9, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1963#(forall ((aux_mod_v_main_~x~0_43_31 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_43_31) (and (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~x~0_43_31 Int)) (not (= (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296)) main_~x~0)))) (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~x~0_43_31 Int)) (or (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296)))))))) (<= aux_mod_v_main_~x~0_43_31 0)))} is UNKNOWN [2022-04-07 17:36:53,913 INFO L290 TraceCheckUtils]: 9: Hoare triple {1970#(forall ((v_main_~x~0_44 Int) (aux_mod_v_main_~x~0_43_31 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_43_31) (and (or (< 0 (mod main_~x~0 4294967296)) (not (= v_main_~x~0_44 main_~x~0))) (or (not (< 0 (mod main_~x~0 4294967296))) (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= (+ v_main_~x~0_44 v_it_4 1) main_~x~0) (<= 1 v_it_4))) (not (< v_main_~x~0_44 main_~x~0)))) (and (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~x~0_43_31 Int)) (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_main_~x~0_44 v_it_5 1) (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296))))) (not (< v_main_~x~0_44 (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296))))))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~x~0_43_31 Int)) (not (= v_main_~x~0_44 (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296))))))) (<= aux_mod_v_main_~x~0_43_31 0)))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1970#(forall ((v_main_~x~0_44 Int) (aux_mod_v_main_~x~0_43_31 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_43_31) (and (or (< 0 (mod main_~x~0 4294967296)) (not (= v_main_~x~0_44 main_~x~0))) (or (not (< 0 (mod main_~x~0 4294967296))) (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= (+ v_main_~x~0_44 v_it_4 1) main_~x~0) (<= 1 v_it_4))) (not (< v_main_~x~0_44 main_~x~0)))) (and (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~x~0_43_31 Int)) (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_main_~x~0_44 v_it_5 1) (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296))))) (not (< v_main_~x~0_44 (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296))))))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~x~0_43_31 Int)) (not (= v_main_~x~0_44 (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296))))))) (<= aux_mod_v_main_~x~0_43_31 0)))} is VALID [2022-04-07 17:36:53,921 INFO L290 TraceCheckUtils]: 8: Hoare triple {1977#(forall ((v_main_~x~0_44 Int) (aux_div_v_main_~x~0_43_31 Int)) (or (<= v_main_~x~0_44 (* aux_div_v_main_~x~0_43_31 4294967296)) (<= (+ (* aux_div_v_main_~x~0_43_31 4294967296) 4294967296) v_main_~x~0_44) (not (< 0 (mod main_~x~0 4294967296))) (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= (+ v_main_~x~0_44 v_it_4 1) main_~x~0) (<= 1 v_it_4))) (not (< v_main_~x~0_44 main_~x~0))))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1970#(forall ((v_main_~x~0_44 Int) (aux_mod_v_main_~x~0_43_31 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_43_31) (and (or (< 0 (mod main_~x~0 4294967296)) (not (= v_main_~x~0_44 main_~x~0))) (or (not (< 0 (mod main_~x~0 4294967296))) (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= (+ v_main_~x~0_44 v_it_4 1) main_~x~0) (<= 1 v_it_4))) (not (< v_main_~x~0_44 main_~x~0)))) (and (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~x~0_43_31 Int)) (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_main_~x~0_44 v_it_5 1) (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296))))) (not (< v_main_~x~0_44 (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296))))))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~x~0_43_31 Int)) (not (= v_main_~x~0_44 (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296))))))) (<= aux_mod_v_main_~x~0_43_31 0)))} is VALID [2022-04-07 17:36:53,922 INFO L290 TraceCheckUtils]: 7: Hoare triple {1977#(forall ((v_main_~x~0_44 Int) (aux_div_v_main_~x~0_43_31 Int)) (or (<= v_main_~x~0_44 (* aux_div_v_main_~x~0_43_31 4294967296)) (<= (+ (* aux_div_v_main_~x~0_43_31 4294967296) 4294967296) v_main_~x~0_44) (not (< 0 (mod main_~x~0 4294967296))) (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= (+ v_main_~x~0_44 v_it_4 1) main_~x~0) (<= 1 v_it_4))) (not (< v_main_~x~0_44 main_~x~0))))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1977#(forall ((v_main_~x~0_44 Int) (aux_div_v_main_~x~0_43_31 Int)) (or (<= v_main_~x~0_44 (* aux_div_v_main_~x~0_43_31 4294967296)) (<= (+ (* aux_div_v_main_~x~0_43_31 4294967296) 4294967296) v_main_~x~0_44) (not (< 0 (mod main_~x~0 4294967296))) (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= (+ v_main_~x~0_44 v_it_4 1) main_~x~0) (<= 1 v_it_4))) (not (< v_main_~x~0_44 main_~x~0))))} is VALID [2022-04-07 17:36:53,923 INFO L290 TraceCheckUtils]: 6: Hoare triple {1876#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1977#(forall ((v_main_~x~0_44 Int) (aux_div_v_main_~x~0_43_31 Int)) (or (<= v_main_~x~0_44 (* aux_div_v_main_~x~0_43_31 4294967296)) (<= (+ (* aux_div_v_main_~x~0_43_31 4294967296) 4294967296) v_main_~x~0_44) (not (< 0 (mod main_~x~0 4294967296))) (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= (+ v_main_~x~0_44 v_it_4 1) main_~x~0) (<= 1 v_it_4))) (not (< v_main_~x~0_44 main_~x~0))))} is VALID [2022-04-07 17:36:53,923 INFO L290 TraceCheckUtils]: 5: Hoare triple {1876#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1876#true} is VALID [2022-04-07 17:36:53,923 INFO L272 TraceCheckUtils]: 4: Hoare triple {1876#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1876#true} is VALID [2022-04-07 17:36:53,923 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1876#true} {1876#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1876#true} is VALID [2022-04-07 17:36:53,923 INFO L290 TraceCheckUtils]: 2: Hoare triple {1876#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1876#true} is VALID [2022-04-07 17:36:53,924 INFO L290 TraceCheckUtils]: 1: Hoare triple {1876#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1876#true} is VALID [2022-04-07 17:36:53,924 INFO L272 TraceCheckUtils]: 0: Hoare triple {1876#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1876#true} is VALID [2022-04-07 17:36:53,924 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 1 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 17:36:53,924 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2138999277] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-07 17:36:53,924 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-07 17:36:53,924 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6, 8] total 12 [2022-04-07 17:36:53,924 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [190964743] [2022-04-07 17:36:53,925 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-07 17:36:53,925 INFO L78 Accepts]: Start accepts. Automaton has has 12 states, 12 states have (on average 2.0833333333333335) internal successors, (25), 9 states have internal predecessors, (25), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 19 [2022-04-07 17:36:53,925 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 17:36:53,925 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 12 states, 12 states have (on average 2.0833333333333335) internal successors, (25), 9 states have internal predecessors, (25), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:37:02,128 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 31 edges. 27 inductive. 0 not inductive. 4 times theorem prover too weak to decide inductivity. [2022-04-07 17:37:02,128 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 12 states [2022-04-07 17:37:02,128 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 17:37:02,128 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2022-04-07 17:37:02,128 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=96, Unknown=8, NotChecked=0, Total=132 [2022-04-07 17:37:02,129 INFO L87 Difference]: Start difference. First operand 43 states and 68 transitions. Second operand has 12 states, 12 states have (on average 2.0833333333333335) internal successors, (25), 9 states have internal predecessors, (25), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:37:04,597 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:37:04,598 INFO L93 Difference]: Finished difference Result 61 states and 96 transitions. [2022-04-07 17:37:04,598 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-04-07 17:37:04,598 INFO L78 Accepts]: Start accepts. Automaton has has 12 states, 12 states have (on average 2.0833333333333335) internal successors, (25), 9 states have internal predecessors, (25), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 19 [2022-04-07 17:37:04,598 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 17:37:04,598 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 12 states have (on average 2.0833333333333335) internal successors, (25), 9 states have internal predecessors, (25), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:37:04,599 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 51 transitions. [2022-04-07 17:37:04,599 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 12 states have (on average 2.0833333333333335) internal successors, (25), 9 states have internal predecessors, (25), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:37:04,601 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 51 transitions. [2022-04-07 17:37:04,601 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 9 states and 51 transitions. [2022-04-07 17:37:04,651 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 51 edges. 51 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 17:37:04,652 INFO L225 Difference]: With dead ends: 61 [2022-04-07 17:37:04,653 INFO L226 Difference]: Without dead ends: 58 [2022-04-07 17:37:04,653 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 32 SyntacticMatches, 7 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 35 ImplicationChecksByTransitivity, 24.4s TimeCoverageRelationStatistics Valid=55, Invalid=177, Unknown=8, NotChecked=0, Total=240 [2022-04-07 17:37:04,653 INFO L913 BasicCegarLoop]: 16 mSDtfsCounter, 28 mSDsluCounter, 38 mSDsCounter, 0 mSdLazyCounter, 46 mSolverCounterSat, 11 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 28 SdHoareTripleChecker+Valid, 54 SdHoareTripleChecker+Invalid, 93 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 11 IncrementalHoareTripleChecker+Valid, 46 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 36 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-07 17:37:04,654 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [28 Valid, 54 Invalid, 93 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [11 Valid, 46 Invalid, 0 Unknown, 36 Unchecked, 0.1s Time] [2022-04-07 17:37:04,654 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58 states. [2022-04-07 17:37:04,656 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58 to 45. [2022-04-07 17:37:04,657 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 17:37:04,657 INFO L82 GeneralOperation]: Start isEquivalent. First operand 58 states. Second operand has 45 states, 40 states have (on average 1.7) internal successors, (68), 40 states have internal predecessors, (68), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:37:04,657 INFO L74 IsIncluded]: Start isIncluded. First operand 58 states. Second operand has 45 states, 40 states have (on average 1.7) internal successors, (68), 40 states have internal predecessors, (68), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:37:04,657 INFO L87 Difference]: Start difference. First operand 58 states. Second operand has 45 states, 40 states have (on average 1.7) internal successors, (68), 40 states have internal predecessors, (68), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:37:04,659 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:37:04,659 INFO L93 Difference]: Finished difference Result 58 states and 93 transitions. [2022-04-07 17:37:04,659 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states and 93 transitions. [2022-04-07 17:37:04,659 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:37:04,659 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:37:04,659 INFO L74 IsIncluded]: Start isIncluded. First operand has 45 states, 40 states have (on average 1.7) internal successors, (68), 40 states have internal predecessors, (68), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 58 states. [2022-04-07 17:37:04,660 INFO L87 Difference]: Start difference. First operand has 45 states, 40 states have (on average 1.7) internal successors, (68), 40 states have internal predecessors, (68), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 58 states. [2022-04-07 17:37:04,661 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:37:04,661 INFO L93 Difference]: Finished difference Result 58 states and 93 transitions. [2022-04-07 17:37:04,661 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states and 93 transitions. [2022-04-07 17:37:04,661 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:37:04,662 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:37:04,662 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 17:37:04,662 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 17:37:04,662 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45 states, 40 states have (on average 1.7) internal successors, (68), 40 states have internal predecessors, (68), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:37:04,663 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 72 transitions. [2022-04-07 17:37:04,663 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 72 transitions. Word has length 19 [2022-04-07 17:37:04,663 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 17:37:04,663 INFO L478 AbstractCegarLoop]: Abstraction has 45 states and 72 transitions. [2022-04-07 17:37:04,663 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 12 states, 12 states have (on average 2.0833333333333335) internal successors, (25), 9 states have internal predecessors, (25), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:37:04,664 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 72 transitions. [2022-04-07 17:37:04,664 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2022-04-07 17:37:04,664 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 17:37:04,664 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 17:37:04,684 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Forceful destruction successful, exit code 0 [2022-04-07 17:37:04,879 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8,6 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 17:37:04,880 INFO L403 AbstractCegarLoop]: === Iteration 10 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 17:37:04,880 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 17:37:04,880 INFO L85 PathProgramCache]: Analyzing trace with hash 84699953, now seen corresponding path program 1 times [2022-04-07 17:37:04,880 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 17:37:04,880 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [621033828] [2022-04-07 17:37:04,880 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:37:04,880 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 17:37:04,896 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_2.0))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-07 17:37:04,897 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.1))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-07 17:37:04,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:37:04,924 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_2.3))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-07 17:37:04,928 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.4))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-07 17:37:05,048 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 17:37:05,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:37:05,054 INFO L290 TraceCheckUtils]: 0: Hoare triple {2248#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2236#true} is VALID [2022-04-07 17:37:05,054 INFO L290 TraceCheckUtils]: 1: Hoare triple {2236#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2236#true} is VALID [2022-04-07 17:37:05,054 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {2236#true} {2236#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2236#true} is VALID [2022-04-07 17:37:05,054 INFO L272 TraceCheckUtils]: 0: Hoare triple {2236#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2248#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 17:37:05,055 INFO L290 TraceCheckUtils]: 1: Hoare triple {2248#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2236#true} is VALID [2022-04-07 17:37:05,055 INFO L290 TraceCheckUtils]: 2: Hoare triple {2236#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2236#true} is VALID [2022-04-07 17:37:05,055 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2236#true} {2236#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2236#true} is VALID [2022-04-07 17:37:05,055 INFO L272 TraceCheckUtils]: 4: Hoare triple {2236#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2236#true} is VALID [2022-04-07 17:37:05,055 INFO L290 TraceCheckUtils]: 5: Hoare triple {2236#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {2241#(= main_~y~0 0)} is VALID [2022-04-07 17:37:05,056 INFO L290 TraceCheckUtils]: 6: Hoare triple {2241#(= main_~y~0 0)} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {2242#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:37:05,057 INFO L290 TraceCheckUtils]: 7: Hoare triple {2242#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {2243#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:37:05,058 INFO L290 TraceCheckUtils]: 8: Hoare triple {2243#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [109] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_8 4294967296))) (or (and (forall ((v_it_2 Int)) (or (< 0 (mod (+ v_main_~z~0_8 (* v_it_2 4294967295)) 4294967296)) (not (<= (+ v_main_~z~0_7 v_it_2 1) v_main_~z~0_8)) (not (<= 1 v_it_2)))) (= v_main_~x~0_11 (+ v_main_~x~0_12 v_main_~z~0_8 (* (- 1) v_main_~z~0_7))) (< 0 .cse0) (< v_main_~z~0_7 v_main_~z~0_8)) (and (<= .cse0 0) (= v_main_~z~0_8 v_main_~z~0_7) (= v_main_~x~0_12 v_main_~x~0_11) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|)))) InVars {main_~x~0=v_main_~x~0_12, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_8, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_11, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {2244#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:37:05,058 INFO L290 TraceCheckUtils]: 9: Hoare triple {2244#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {2244#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:37:05,059 INFO L290 TraceCheckUtils]: 10: Hoare triple {2244#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {2245#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:37:05,059 INFO L290 TraceCheckUtils]: 11: Hoare triple {2245#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {2245#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:37:05,060 INFO L290 TraceCheckUtils]: 12: Hoare triple {2245#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {2245#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:37:05,061 INFO L290 TraceCheckUtils]: 13: Hoare triple {2245#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {2244#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:37:05,062 INFO L290 TraceCheckUtils]: 14: Hoare triple {2244#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {2244#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:37:05,063 INFO L272 TraceCheckUtils]: 15: Hoare triple {2244#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {2246#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-07 17:37:05,063 INFO L290 TraceCheckUtils]: 16: Hoare triple {2246#(not (= |__VERIFIER_assert_#in~cond| 0))} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2247#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-07 17:37:05,063 INFO L290 TraceCheckUtils]: 17: Hoare triple {2247#(not (= __VERIFIER_assert_~cond 0))} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2237#false} is VALID [2022-04-07 17:37:05,064 INFO L290 TraceCheckUtils]: 18: Hoare triple {2237#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2237#false} is VALID [2022-04-07 17:37:05,064 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 17:37:05,064 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 17:37:05,064 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [621033828] [2022-04-07 17:37:05,064 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [621033828] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 17:37:05,064 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [460670126] [2022-04-07 17:37:05,064 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:37:05,064 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 17:37:05,065 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 17:37:05,068 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 17:37:05,072 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2022-04-07 17:37:05,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:37:05,108 INFO L263 TraceCheckSpWp]: Trace formula consists of 64 conjuncts, 6 conjunts are in the unsatisfiable core [2022-04-07 17:37:05,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:37:05,118 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 17:37:05,747 INFO L272 TraceCheckUtils]: 0: Hoare triple {2236#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2236#true} is VALID [2022-04-07 17:37:05,747 INFO L290 TraceCheckUtils]: 1: Hoare triple {2236#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2236#true} is VALID [2022-04-07 17:37:05,747 INFO L290 TraceCheckUtils]: 2: Hoare triple {2236#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2236#true} is VALID [2022-04-07 17:37:05,747 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2236#true} {2236#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2236#true} is VALID [2022-04-07 17:37:05,748 INFO L272 TraceCheckUtils]: 4: Hoare triple {2236#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2236#true} is VALID [2022-04-07 17:37:05,748 INFO L290 TraceCheckUtils]: 5: Hoare triple {2236#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {2236#true} is VALID [2022-04-07 17:37:05,748 INFO L290 TraceCheckUtils]: 6: Hoare triple {2236#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {2236#true} is VALID [2022-04-07 17:37:05,748 INFO L290 TraceCheckUtils]: 7: Hoare triple {2236#true} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {2236#true} is VALID [2022-04-07 17:37:05,748 INFO L290 TraceCheckUtils]: 8: Hoare triple {2236#true} [109] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_8 4294967296))) (or (and (forall ((v_it_2 Int)) (or (< 0 (mod (+ v_main_~z~0_8 (* v_it_2 4294967295)) 4294967296)) (not (<= (+ v_main_~z~0_7 v_it_2 1) v_main_~z~0_8)) (not (<= 1 v_it_2)))) (= v_main_~x~0_11 (+ v_main_~x~0_12 v_main_~z~0_8 (* (- 1) v_main_~z~0_7))) (< 0 .cse0) (< v_main_~z~0_7 v_main_~z~0_8)) (and (<= .cse0 0) (= v_main_~z~0_8 v_main_~z~0_7) (= v_main_~x~0_12 v_main_~x~0_11) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|)))) InVars {main_~x~0=v_main_~x~0_12, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_8, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_11, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {2236#true} is VALID [2022-04-07 17:37:05,748 INFO L290 TraceCheckUtils]: 9: Hoare triple {2236#true} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {2236#true} is VALID [2022-04-07 17:37:05,750 INFO L290 TraceCheckUtils]: 10: Hoare triple {2236#true} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {2282#(not (< 0 (mod main_~y~0 4294967296)))} is VALID [2022-04-07 17:37:05,751 INFO L290 TraceCheckUtils]: 11: Hoare triple {2282#(not (< 0 (mod main_~y~0 4294967296)))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {2245#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:37:05,751 INFO L290 TraceCheckUtils]: 12: Hoare triple {2245#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {2245#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:37:05,753 INFO L290 TraceCheckUtils]: 13: Hoare triple {2245#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {2244#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:37:05,753 INFO L290 TraceCheckUtils]: 14: Hoare triple {2244#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {2244#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:37:05,754 INFO L272 TraceCheckUtils]: 15: Hoare triple {2244#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {2298#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 17:37:05,754 INFO L290 TraceCheckUtils]: 16: Hoare triple {2298#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2302#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 17:37:05,754 INFO L290 TraceCheckUtils]: 17: Hoare triple {2302#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2237#false} is VALID [2022-04-07 17:37:05,754 INFO L290 TraceCheckUtils]: 18: Hoare triple {2237#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2237#false} is VALID [2022-04-07 17:37:05,754 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-07 17:37:05,754 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-07 17:37:08,644 INFO L290 TraceCheckUtils]: 18: Hoare triple {2237#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2237#false} is VALID [2022-04-07 17:37:08,644 INFO L290 TraceCheckUtils]: 17: Hoare triple {2302#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2237#false} is VALID [2022-04-07 17:37:08,645 INFO L290 TraceCheckUtils]: 16: Hoare triple {2298#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2302#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 17:37:08,645 INFO L272 TraceCheckUtils]: 15: Hoare triple {2244#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {2298#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 17:37:08,646 INFO L290 TraceCheckUtils]: 14: Hoare triple {2244#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {2244#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:37:08,662 INFO L290 TraceCheckUtils]: 13: Hoare triple {2324#(forall ((aux_mod_v_main_~x~0_46_31 Int)) (or (<= aux_mod_v_main_~x~0_46_31 0) (<= 4294967296 aux_mod_v_main_~x~0_46_31) (and (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~x~0_46_31 Int)) (or (not (< (+ aux_mod_v_main_~x~0_46_31 (* aux_div_v_main_~x~0_46_31 4294967296)) main_~x~0)) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))) (<= (+ aux_mod_v_main_~x~0_46_31 v_it_6 (* aux_div_v_main_~x~0_46_31 4294967296) 1) main_~x~0)))))) (or (forall ((aux_div_v_main_~x~0_46_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_46_31 (* aux_div_v_main_~x~0_46_31 4294967296))))) (< 0 (mod main_~y~0 4294967296))))))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {2244#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:37:08,663 INFO L290 TraceCheckUtils]: 12: Hoare triple {2324#(forall ((aux_mod_v_main_~x~0_46_31 Int)) (or (<= aux_mod_v_main_~x~0_46_31 0) (<= 4294967296 aux_mod_v_main_~x~0_46_31) (and (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~x~0_46_31 Int)) (or (not (< (+ aux_mod_v_main_~x~0_46_31 (* aux_div_v_main_~x~0_46_31 4294967296)) main_~x~0)) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))) (<= (+ aux_mod_v_main_~x~0_46_31 v_it_6 (* aux_div_v_main_~x~0_46_31 4294967296) 1) main_~x~0)))))) (or (forall ((aux_div_v_main_~x~0_46_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_46_31 (* aux_div_v_main_~x~0_46_31 4294967296))))) (< 0 (mod main_~y~0 4294967296))))))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {2324#(forall ((aux_mod_v_main_~x~0_46_31 Int)) (or (<= aux_mod_v_main_~x~0_46_31 0) (<= 4294967296 aux_mod_v_main_~x~0_46_31) (and (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~x~0_46_31 Int)) (or (not (< (+ aux_mod_v_main_~x~0_46_31 (* aux_div_v_main_~x~0_46_31 4294967296)) main_~x~0)) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))) (<= (+ aux_mod_v_main_~x~0_46_31 v_it_6 (* aux_div_v_main_~x~0_46_31 4294967296) 1) main_~x~0)))))) (or (forall ((aux_div_v_main_~x~0_46_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_46_31 (* aux_div_v_main_~x~0_46_31 4294967296))))) (< 0 (mod main_~y~0 4294967296))))))} is VALID [2022-04-07 17:37:08,664 INFO L290 TraceCheckUtils]: 11: Hoare triple {2282#(not (< 0 (mod main_~y~0 4294967296)))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {2324#(forall ((aux_mod_v_main_~x~0_46_31 Int)) (or (<= aux_mod_v_main_~x~0_46_31 0) (<= 4294967296 aux_mod_v_main_~x~0_46_31) (and (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~x~0_46_31 Int)) (or (not (< (+ aux_mod_v_main_~x~0_46_31 (* aux_div_v_main_~x~0_46_31 4294967296)) main_~x~0)) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))) (<= (+ aux_mod_v_main_~x~0_46_31 v_it_6 (* aux_div_v_main_~x~0_46_31 4294967296) 1) main_~x~0)))))) (or (forall ((aux_div_v_main_~x~0_46_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_46_31 (* aux_div_v_main_~x~0_46_31 4294967296))))) (< 0 (mod main_~y~0 4294967296))))))} is VALID [2022-04-07 17:37:08,667 INFO L290 TraceCheckUtils]: 10: Hoare triple {2236#true} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {2282#(not (< 0 (mod main_~y~0 4294967296)))} is VALID [2022-04-07 17:37:08,667 INFO L290 TraceCheckUtils]: 9: Hoare triple {2236#true} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {2236#true} is VALID [2022-04-07 17:37:08,667 INFO L290 TraceCheckUtils]: 8: Hoare triple {2236#true} [109] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_8 4294967296))) (or (and (forall ((v_it_2 Int)) (or (< 0 (mod (+ v_main_~z~0_8 (* v_it_2 4294967295)) 4294967296)) (not (<= (+ v_main_~z~0_7 v_it_2 1) v_main_~z~0_8)) (not (<= 1 v_it_2)))) (= v_main_~x~0_11 (+ v_main_~x~0_12 v_main_~z~0_8 (* (- 1) v_main_~z~0_7))) (< 0 .cse0) (< v_main_~z~0_7 v_main_~z~0_8)) (and (<= .cse0 0) (= v_main_~z~0_8 v_main_~z~0_7) (= v_main_~x~0_12 v_main_~x~0_11) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|)))) InVars {main_~x~0=v_main_~x~0_12, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_8, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_11, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {2236#true} is VALID [2022-04-07 17:37:08,668 INFO L290 TraceCheckUtils]: 7: Hoare triple {2236#true} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {2236#true} is VALID [2022-04-07 17:37:08,668 INFO L290 TraceCheckUtils]: 6: Hoare triple {2236#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {2236#true} is VALID [2022-04-07 17:37:08,668 INFO L290 TraceCheckUtils]: 5: Hoare triple {2236#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {2236#true} is VALID [2022-04-07 17:37:08,668 INFO L272 TraceCheckUtils]: 4: Hoare triple {2236#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2236#true} is VALID [2022-04-07 17:37:08,668 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2236#true} {2236#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2236#true} is VALID [2022-04-07 17:37:08,668 INFO L290 TraceCheckUtils]: 2: Hoare triple {2236#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2236#true} is VALID [2022-04-07 17:37:08,668 INFO L290 TraceCheckUtils]: 1: Hoare triple {2236#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2236#true} is VALID [2022-04-07 17:37:08,668 INFO L272 TraceCheckUtils]: 0: Hoare triple {2236#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2236#true} is VALID [2022-04-07 17:37:08,668 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-07 17:37:08,669 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [460670126] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-07 17:37:08,669 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-07 17:37:08,669 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 7, 7] total 14 [2022-04-07 17:37:08,669 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [916074828] [2022-04-07 17:37:08,669 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-07 17:37:08,670 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 19 [2022-04-07 17:37:08,670 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 17:37:08,670 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:37:11,439 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 34 edges. 33 inductive. 0 not inductive. 1 times theorem prover too weak to decide inductivity. [2022-04-07 17:37:11,439 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-04-07 17:37:11,439 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 17:37:11,439 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-04-07 17:37:11,439 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=145, Unknown=0, NotChecked=0, Total=182 [2022-04-07 17:37:11,440 INFO L87 Difference]: Start difference. First operand 45 states and 72 transitions. Second operand has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:37:11,686 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:37:11,686 INFO L93 Difference]: Finished difference Result 64 states and 101 transitions. [2022-04-07 17:37:11,686 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-04-07 17:37:11,686 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 19 [2022-04-07 17:37:11,687 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 17:37:11,687 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:37:11,688 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 58 transitions. [2022-04-07 17:37:11,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:37:11,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 58 transitions. [2022-04-07 17:37:11,689 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 12 states and 58 transitions. [2022-04-07 17:37:11,765 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 58 edges. 58 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 17:37:11,766 INFO L225 Difference]: With dead ends: 64 [2022-04-07 17:37:11,766 INFO L226 Difference]: Without dead ends: 61 [2022-04-07 17:37:11,766 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 60 GetRequests, 35 SyntacticMatches, 5 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 107 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=101, Invalid=361, Unknown=0, NotChecked=0, Total=462 [2022-04-07 17:37:11,767 INFO L913 BasicCegarLoop]: 13 mSDtfsCounter, 44 mSDsluCounter, 39 mSDsCounter, 0 mSdLazyCounter, 59 mSolverCounterSat, 21 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 44 SdHoareTripleChecker+Valid, 52 SdHoareTripleChecker+Invalid, 103 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 21 IncrementalHoareTripleChecker+Valid, 59 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 23 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-07 17:37:11,767 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [44 Valid, 52 Invalid, 103 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [21 Valid, 59 Invalid, 0 Unknown, 23 Unchecked, 0.1s Time] [2022-04-07 17:37:11,767 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states. [2022-04-07 17:37:11,769 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 44. [2022-04-07 17:37:11,769 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 17:37:11,770 INFO L82 GeneralOperation]: Start isEquivalent. First operand 61 states. Second operand has 44 states, 39 states have (on average 1.6923076923076923) internal successors, (66), 39 states have internal predecessors, (66), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:37:11,770 INFO L74 IsIncluded]: Start isIncluded. First operand 61 states. Second operand has 44 states, 39 states have (on average 1.6923076923076923) internal successors, (66), 39 states have internal predecessors, (66), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:37:11,770 INFO L87 Difference]: Start difference. First operand 61 states. Second operand has 44 states, 39 states have (on average 1.6923076923076923) internal successors, (66), 39 states have internal predecessors, (66), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:37:11,775 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:37:11,775 INFO L93 Difference]: Finished difference Result 61 states and 98 transitions. [2022-04-07 17:37:11,775 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 98 transitions. [2022-04-07 17:37:11,775 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:37:11,775 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:37:11,775 INFO L74 IsIncluded]: Start isIncluded. First operand has 44 states, 39 states have (on average 1.6923076923076923) internal successors, (66), 39 states have internal predecessors, (66), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 61 states. [2022-04-07 17:37:11,776 INFO L87 Difference]: Start difference. First operand has 44 states, 39 states have (on average 1.6923076923076923) internal successors, (66), 39 states have internal predecessors, (66), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 61 states. [2022-04-07 17:37:11,777 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:37:11,777 INFO L93 Difference]: Finished difference Result 61 states and 98 transitions. [2022-04-07 17:37:11,777 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 98 transitions. [2022-04-07 17:37:11,777 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:37:11,778 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:37:11,778 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 17:37:11,778 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 17:37:11,778 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44 states, 39 states have (on average 1.6923076923076923) internal successors, (66), 39 states have internal predecessors, (66), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:37:11,779 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 70 transitions. [2022-04-07 17:37:11,779 INFO L78 Accepts]: Start accepts. Automaton has 44 states and 70 transitions. Word has length 19 [2022-04-07 17:37:11,779 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 17:37:11,779 INFO L478 AbstractCegarLoop]: Abstraction has 44 states and 70 transitions. [2022-04-07 17:37:11,779 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:37:11,779 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 70 transitions. [2022-04-07 17:37:11,780 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2022-04-07 17:37:11,780 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 17:37:11,780 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 17:37:11,806 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Forceful destruction successful, exit code 0 [2022-04-07 17:37:11,980 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9,7 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 17:37:11,981 INFO L403 AbstractCegarLoop]: === Iteration 11 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 17:37:11,981 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 17:37:11,981 INFO L85 PathProgramCache]: Analyzing trace with hash 857687030, now seen corresponding path program 1 times [2022-04-07 17:37:11,981 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 17:37:11,981 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [166343087] [2022-04-07 17:37:11,981 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:37:11,981 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 17:37:11,995 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_2.0))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-07 17:37:11,997 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.1))) (+ main_~z~0_8 .cse0 (* (- 4294967296) (div (+ main_~z~0_8 .cse0) 4294967296)))) 0)) [2022-04-07 17:37:12,000 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:37:12,007 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_2.3))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-07 17:37:12,011 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.4))) (+ main_~z~0_8 .cse0 (* (- 4294967296) (div (+ main_~z~0_8 .cse0) 4294967296)))) 0)) [2022-04-07 17:37:12,095 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 17:37:12,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:37:12,100 INFO L290 TraceCheckUtils]: 0: Hoare triple {2627#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2615#true} is VALID [2022-04-07 17:37:12,100 INFO L290 TraceCheckUtils]: 1: Hoare triple {2615#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2615#true} is VALID [2022-04-07 17:37:12,100 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {2615#true} {2615#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2615#true} is VALID [2022-04-07 17:37:12,101 INFO L272 TraceCheckUtils]: 0: Hoare triple {2615#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2627#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 17:37:12,101 INFO L290 TraceCheckUtils]: 1: Hoare triple {2627#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2615#true} is VALID [2022-04-07 17:37:12,101 INFO L290 TraceCheckUtils]: 2: Hoare triple {2615#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2615#true} is VALID [2022-04-07 17:37:12,101 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2615#true} {2615#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2615#true} is VALID [2022-04-07 17:37:12,101 INFO L272 TraceCheckUtils]: 4: Hoare triple {2615#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2615#true} is VALID [2022-04-07 17:37:12,101 INFO L290 TraceCheckUtils]: 5: Hoare triple {2615#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {2620#(= main_~y~0 0)} is VALID [2022-04-07 17:37:12,102 INFO L290 TraceCheckUtils]: 6: Hoare triple {2620#(= main_~y~0 0)} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {2621#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:37:12,103 INFO L290 TraceCheckUtils]: 7: Hoare triple {2621#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {2622#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:37:12,103 INFO L290 TraceCheckUtils]: 8: Hoare triple {2622#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [109] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_8 4294967296))) (or (and (forall ((v_it_2 Int)) (or (< 0 (mod (+ v_main_~z~0_8 (* v_it_2 4294967295)) 4294967296)) (not (<= (+ v_main_~z~0_7 v_it_2 1) v_main_~z~0_8)) (not (<= 1 v_it_2)))) (= v_main_~x~0_11 (+ v_main_~x~0_12 v_main_~z~0_8 (* (- 1) v_main_~z~0_7))) (< 0 .cse0) (< v_main_~z~0_7 v_main_~z~0_8)) (and (<= .cse0 0) (= v_main_~z~0_8 v_main_~z~0_7) (= v_main_~x~0_12 v_main_~x~0_11) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|)))) InVars {main_~x~0=v_main_~x~0_12, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_8, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_11, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {2623#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:37:12,104 INFO L290 TraceCheckUtils]: 9: Hoare triple {2623#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {2624#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-07 17:37:12,104 INFO L290 TraceCheckUtils]: 10: Hoare triple {2624#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {2624#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-07 17:37:12,106 INFO L290 TraceCheckUtils]: 11: Hoare triple {2624#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {2624#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-07 17:37:12,107 INFO L290 TraceCheckUtils]: 12: Hoare triple {2624#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {2623#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:37:12,108 INFO L290 TraceCheckUtils]: 13: Hoare triple {2623#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {2623#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:37:12,108 INFO L290 TraceCheckUtils]: 14: Hoare triple {2623#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {2623#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:37:12,109 INFO L272 TraceCheckUtils]: 15: Hoare triple {2623#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {2625#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-07 17:37:12,109 INFO L290 TraceCheckUtils]: 16: Hoare triple {2625#(not (= |__VERIFIER_assert_#in~cond| 0))} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2626#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-07 17:37:12,109 INFO L290 TraceCheckUtils]: 17: Hoare triple {2626#(not (= __VERIFIER_assert_~cond 0))} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2616#false} is VALID [2022-04-07 17:37:12,109 INFO L290 TraceCheckUtils]: 18: Hoare triple {2616#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2616#false} is VALID [2022-04-07 17:37:12,109 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 17:37:12,110 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 17:37:12,110 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [166343087] [2022-04-07 17:37:12,110 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [166343087] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 17:37:12,110 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1038402181] [2022-04-07 17:37:12,110 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:37:12,110 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 17:37:12,110 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 17:37:12,111 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 17:37:12,111 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2022-04-07 17:37:12,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:37:12,145 INFO L263 TraceCheckSpWp]: Trace formula consists of 64 conjuncts, 6 conjunts are in the unsatisfiable core [2022-04-07 17:37:12,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:37:12,153 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 17:37:12,695 INFO L272 TraceCheckUtils]: 0: Hoare triple {2615#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2615#true} is VALID [2022-04-07 17:37:12,696 INFO L290 TraceCheckUtils]: 1: Hoare triple {2615#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2615#true} is VALID [2022-04-07 17:37:12,696 INFO L290 TraceCheckUtils]: 2: Hoare triple {2615#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2615#true} is VALID [2022-04-07 17:37:12,696 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2615#true} {2615#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2615#true} is VALID [2022-04-07 17:37:12,696 INFO L272 TraceCheckUtils]: 4: Hoare triple {2615#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2615#true} is VALID [2022-04-07 17:37:12,696 INFO L290 TraceCheckUtils]: 5: Hoare triple {2615#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {2615#true} is VALID [2022-04-07 17:37:12,696 INFO L290 TraceCheckUtils]: 6: Hoare triple {2615#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {2615#true} is VALID [2022-04-07 17:37:12,696 INFO L290 TraceCheckUtils]: 7: Hoare triple {2615#true} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {2615#true} is VALID [2022-04-07 17:37:12,696 INFO L290 TraceCheckUtils]: 8: Hoare triple {2615#true} [109] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_8 4294967296))) (or (and (forall ((v_it_2 Int)) (or (< 0 (mod (+ v_main_~z~0_8 (* v_it_2 4294967295)) 4294967296)) (not (<= (+ v_main_~z~0_7 v_it_2 1) v_main_~z~0_8)) (not (<= 1 v_it_2)))) (= v_main_~x~0_11 (+ v_main_~x~0_12 v_main_~z~0_8 (* (- 1) v_main_~z~0_7))) (< 0 .cse0) (< v_main_~z~0_7 v_main_~z~0_8)) (and (<= .cse0 0) (= v_main_~z~0_8 v_main_~z~0_7) (= v_main_~x~0_12 v_main_~x~0_11) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|)))) InVars {main_~x~0=v_main_~x~0_12, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_8, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_11, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {2615#true} is VALID [2022-04-07 17:37:12,698 INFO L290 TraceCheckUtils]: 9: Hoare triple {2615#true} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {2658#(not (< 0 (mod main_~z~0 4294967296)))} is VALID [2022-04-07 17:37:12,698 INFO L290 TraceCheckUtils]: 10: Hoare triple {2658#(not (< 0 (mod main_~z~0 4294967296)))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {2658#(not (< 0 (mod main_~z~0 4294967296)))} is VALID [2022-04-07 17:37:12,698 INFO L290 TraceCheckUtils]: 11: Hoare triple {2658#(not (< 0 (mod main_~z~0 4294967296)))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {2624#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-07 17:37:12,700 INFO L290 TraceCheckUtils]: 12: Hoare triple {2624#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {2623#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:37:12,700 INFO L290 TraceCheckUtils]: 13: Hoare triple {2623#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {2623#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:37:12,700 INFO L290 TraceCheckUtils]: 14: Hoare triple {2623#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {2623#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:37:12,701 INFO L272 TraceCheckUtils]: 15: Hoare triple {2623#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {2677#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 17:37:12,701 INFO L290 TraceCheckUtils]: 16: Hoare triple {2677#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2681#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 17:37:12,702 INFO L290 TraceCheckUtils]: 17: Hoare triple {2681#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2616#false} is VALID [2022-04-07 17:37:12,702 INFO L290 TraceCheckUtils]: 18: Hoare triple {2616#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2616#false} is VALID [2022-04-07 17:37:12,702 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-07 17:37:12,702 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-07 17:37:20,520 INFO L290 TraceCheckUtils]: 18: Hoare triple {2616#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2616#false} is VALID [2022-04-07 17:37:20,521 INFO L290 TraceCheckUtils]: 17: Hoare triple {2681#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2616#false} is VALID [2022-04-07 17:37:20,521 INFO L290 TraceCheckUtils]: 16: Hoare triple {2677#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2681#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 17:37:20,522 INFO L272 TraceCheckUtils]: 15: Hoare triple {2623#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {2677#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 17:37:20,522 INFO L290 TraceCheckUtils]: 14: Hoare triple {2623#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {2623#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:37:20,523 INFO L290 TraceCheckUtils]: 13: Hoare triple {2623#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {2623#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:37:20,624 INFO L290 TraceCheckUtils]: 12: Hoare triple {2706#(forall ((aux_mod_v_main_~x~0_48_31 Int)) (or (<= aux_mod_v_main_~x~0_48_31 0) (<= 4294967296 aux_mod_v_main_~x~0_48_31) (and (or (forall ((aux_div_v_main_~x~0_48_31 Int)) (or (not (< main_~x~0 (+ aux_mod_v_main_~x~0_48_31 (* aux_div_v_main_~x~0_48_31 4294967296)))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_48_31 (* aux_div_v_main_~x~0_48_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))))) (not (< 0 (mod main_~z~0 4294967296)))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~x~0_48_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_48_31 (* aux_div_v_main_~x~0_48_31 4294967296)))))))))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {2623#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:37:20,625 INFO L290 TraceCheckUtils]: 11: Hoare triple {2658#(not (< 0 (mod main_~z~0 4294967296)))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {2706#(forall ((aux_mod_v_main_~x~0_48_31 Int)) (or (<= aux_mod_v_main_~x~0_48_31 0) (<= 4294967296 aux_mod_v_main_~x~0_48_31) (and (or (forall ((aux_div_v_main_~x~0_48_31 Int)) (or (not (< main_~x~0 (+ aux_mod_v_main_~x~0_48_31 (* aux_div_v_main_~x~0_48_31 4294967296)))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_48_31 (* aux_div_v_main_~x~0_48_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))))) (not (< 0 (mod main_~z~0 4294967296)))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~x~0_48_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_48_31 (* aux_div_v_main_~x~0_48_31 4294967296)))))))))} is VALID [2022-04-07 17:37:20,626 INFO L290 TraceCheckUtils]: 10: Hoare triple {2658#(not (< 0 (mod main_~z~0 4294967296)))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {2658#(not (< 0 (mod main_~z~0 4294967296)))} is VALID [2022-04-07 17:37:20,626 INFO L290 TraceCheckUtils]: 9: Hoare triple {2615#true} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {2658#(not (< 0 (mod main_~z~0 4294967296)))} is VALID [2022-04-07 17:37:20,626 INFO L290 TraceCheckUtils]: 8: Hoare triple {2615#true} [109] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_8 4294967296))) (or (and (forall ((v_it_2 Int)) (or (< 0 (mod (+ v_main_~z~0_8 (* v_it_2 4294967295)) 4294967296)) (not (<= (+ v_main_~z~0_7 v_it_2 1) v_main_~z~0_8)) (not (<= 1 v_it_2)))) (= v_main_~x~0_11 (+ v_main_~x~0_12 v_main_~z~0_8 (* (- 1) v_main_~z~0_7))) (< 0 .cse0) (< v_main_~z~0_7 v_main_~z~0_8)) (and (<= .cse0 0) (= v_main_~z~0_8 v_main_~z~0_7) (= v_main_~x~0_12 v_main_~x~0_11) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|)))) InVars {main_~x~0=v_main_~x~0_12, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_8, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_11, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {2615#true} is VALID [2022-04-07 17:37:20,626 INFO L290 TraceCheckUtils]: 7: Hoare triple {2615#true} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {2615#true} is VALID [2022-04-07 17:37:20,626 INFO L290 TraceCheckUtils]: 6: Hoare triple {2615#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {2615#true} is VALID [2022-04-07 17:37:20,626 INFO L290 TraceCheckUtils]: 5: Hoare triple {2615#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {2615#true} is VALID [2022-04-07 17:37:20,626 INFO L272 TraceCheckUtils]: 4: Hoare triple {2615#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2615#true} is VALID [2022-04-07 17:37:20,627 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2615#true} {2615#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2615#true} is VALID [2022-04-07 17:37:20,627 INFO L290 TraceCheckUtils]: 2: Hoare triple {2615#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2615#true} is VALID [2022-04-07 17:37:20,627 INFO L290 TraceCheckUtils]: 1: Hoare triple {2615#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2615#true} is VALID [2022-04-07 17:37:20,627 INFO L272 TraceCheckUtils]: 0: Hoare triple {2615#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2615#true} is VALID [2022-04-07 17:37:20,627 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-07 17:37:20,627 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1038402181] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-07 17:37:20,627 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-07 17:37:20,627 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 7, 7] total 14 [2022-04-07 17:37:20,627 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1926960138] [2022-04-07 17:37:20,627 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-07 17:37:20,628 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 1.9285714285714286) internal successors, (27), 11 states have internal predecessors, (27), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 19 [2022-04-07 17:37:20,628 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 17:37:20,628 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 14 states, 14 states have (on average 1.9285714285714286) internal successors, (27), 11 states have internal predecessors, (27), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:37:22,668 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 33 edges. 32 inductive. 0 not inductive. 1 times theorem prover too weak to decide inductivity. [2022-04-07 17:37:22,668 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-04-07 17:37:22,668 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 17:37:22,668 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-04-07 17:37:22,668 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=143, Unknown=3, NotChecked=0, Total=182 [2022-04-07 17:37:22,669 INFO L87 Difference]: Start difference. First operand 44 states and 70 transitions. Second operand has 14 states, 14 states have (on average 1.9285714285714286) internal successors, (27), 11 states have internal predecessors, (27), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:37:22,989 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:37:22,989 INFO L93 Difference]: Finished difference Result 62 states and 99 transitions. [2022-04-07 17:37:22,989 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-04-07 17:37:22,990 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 1.9285714285714286) internal successors, (27), 11 states have internal predecessors, (27), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 19 [2022-04-07 17:37:22,990 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 17:37:22,990 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 1.9285714285714286) internal successors, (27), 11 states have internal predecessors, (27), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:37:22,991 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 61 transitions. [2022-04-07 17:37:22,991 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 1.9285714285714286) internal successors, (27), 11 states have internal predecessors, (27), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:37:22,992 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 61 transitions. [2022-04-07 17:37:22,992 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 12 states and 61 transitions. [2022-04-07 17:37:23,051 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 61 edges. 61 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 17:37:23,052 INFO L225 Difference]: With dead ends: 62 [2022-04-07 17:37:23,052 INFO L226 Difference]: Without dead ends: 59 [2022-04-07 17:37:23,053 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 60 GetRequests, 35 SyntacticMatches, 5 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 98 ImplicationChecksByTransitivity, 6.3s TimeCoverageRelationStatistics Valid=93, Invalid=366, Unknown=3, NotChecked=0, Total=462 [2022-04-07 17:37:23,053 INFO L913 BasicCegarLoop]: 12 mSDtfsCounter, 36 mSDsluCounter, 57 mSDsCounter, 0 mSdLazyCounter, 109 mSolverCounterSat, 23 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 36 SdHoareTripleChecker+Valid, 69 SdHoareTripleChecker+Invalid, 157 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 23 IncrementalHoareTripleChecker+Valid, 109 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 25 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-07 17:37:23,053 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [36 Valid, 69 Invalid, 157 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [23 Valid, 109 Invalid, 0 Unknown, 25 Unchecked, 0.1s Time] [2022-04-07 17:37:23,054 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2022-04-07 17:37:23,056 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 44. [2022-04-07 17:37:23,056 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 17:37:23,056 INFO L82 GeneralOperation]: Start isEquivalent. First operand 59 states. Second operand has 44 states, 39 states have (on average 1.6923076923076923) internal successors, (66), 39 states have internal predecessors, (66), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:37:23,056 INFO L74 IsIncluded]: Start isIncluded. First operand 59 states. Second operand has 44 states, 39 states have (on average 1.6923076923076923) internal successors, (66), 39 states have internal predecessors, (66), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:37:23,057 INFO L87 Difference]: Start difference. First operand 59 states. Second operand has 44 states, 39 states have (on average 1.6923076923076923) internal successors, (66), 39 states have internal predecessors, (66), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:37:23,058 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:37:23,058 INFO L93 Difference]: Finished difference Result 59 states and 96 transitions. [2022-04-07 17:37:23,058 INFO L276 IsEmpty]: Start isEmpty. Operand 59 states and 96 transitions. [2022-04-07 17:37:23,058 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:37:23,058 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:37:23,059 INFO L74 IsIncluded]: Start isIncluded. First operand has 44 states, 39 states have (on average 1.6923076923076923) internal successors, (66), 39 states have internal predecessors, (66), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 59 states. [2022-04-07 17:37:23,059 INFO L87 Difference]: Start difference. First operand has 44 states, 39 states have (on average 1.6923076923076923) internal successors, (66), 39 states have internal predecessors, (66), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 59 states. [2022-04-07 17:37:23,060 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:37:23,060 INFO L93 Difference]: Finished difference Result 59 states and 96 transitions. [2022-04-07 17:37:23,060 INFO L276 IsEmpty]: Start isEmpty. Operand 59 states and 96 transitions. [2022-04-07 17:37:23,060 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:37:23,060 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:37:23,060 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 17:37:23,060 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 17:37:23,060 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44 states, 39 states have (on average 1.6923076923076923) internal successors, (66), 39 states have internal predecessors, (66), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:37:23,061 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 70 transitions. [2022-04-07 17:37:23,061 INFO L78 Accepts]: Start accepts. Automaton has 44 states and 70 transitions. Word has length 19 [2022-04-07 17:37:23,061 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 17:37:23,061 INFO L478 AbstractCegarLoop]: Abstraction has 44 states and 70 transitions. [2022-04-07 17:37:23,062 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 14 states have (on average 1.9285714285714286) internal successors, (27), 11 states have internal predecessors, (27), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:37:23,062 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 70 transitions. [2022-04-07 17:37:23,062 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2022-04-07 17:37:23,062 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 17:37:23,062 INFO L499 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 17:37:23,082 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Ended with exit code 0 [2022-04-07 17:37:23,275 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10,8 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 17:37:23,275 INFO L403 AbstractCegarLoop]: === Iteration 12 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 17:37:23,275 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 17:37:23,276 INFO L85 PathProgramCache]: Analyzing trace with hash 1145856883, now seen corresponding path program 2 times [2022-04-07 17:37:23,276 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 17:37:23,276 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1297606910] [2022-04-07 17:37:23,276 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:37:23,276 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 17:37:23,287 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.0))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-07 17:37:23,288 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.1))) (+ main_~y~0_9 .cse0 (* (- 4294967296) (div (+ main_~y~0_9 .cse0) 4294967296)))) 0)) [2022-04-07 17:37:23,289 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.2))) (+ main_~z~0_10 .cse0 (* (- 4294967296) (div (+ main_~z~0_10 .cse0) 4294967296)))) 0)) [2022-04-07 17:37:23,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:37:23,309 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.3))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-07 17:37:23,311 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.4))) (+ main_~y~0_9 .cse0 (* (- 4294967296) (div (+ main_~y~0_9 .cse0) 4294967296)))) 0)) [2022-04-07 17:37:23,314 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.5))) (+ main_~z~0_10 .cse0 (* (- 4294967296) (div (+ main_~z~0_10 .cse0) 4294967296)))) 0)) [2022-04-07 17:37:23,432 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 17:37:23,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:37:23,438 INFO L290 TraceCheckUtils]: 0: Hoare triple {3000#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2988#true} is VALID [2022-04-07 17:37:23,439 INFO L290 TraceCheckUtils]: 1: Hoare triple {2988#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2988#true} is VALID [2022-04-07 17:37:23,439 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {2988#true} {2988#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2988#true} is VALID [2022-04-07 17:37:23,442 INFO L272 TraceCheckUtils]: 0: Hoare triple {2988#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3000#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 17:37:23,442 INFO L290 TraceCheckUtils]: 1: Hoare triple {3000#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2988#true} is VALID [2022-04-07 17:37:23,442 INFO L290 TraceCheckUtils]: 2: Hoare triple {2988#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2988#true} is VALID [2022-04-07 17:37:23,442 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2988#true} {2988#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2988#true} is VALID [2022-04-07 17:37:23,442 INFO L272 TraceCheckUtils]: 4: Hoare triple {2988#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2988#true} is VALID [2022-04-07 17:37:23,445 INFO L290 TraceCheckUtils]: 5: Hoare triple {2988#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {2993#(= main_~y~0 0)} is VALID [2022-04-07 17:37:23,446 INFO L290 TraceCheckUtils]: 6: Hoare triple {2993#(= main_~y~0 0)} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {2994#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:37:23,446 INFO L290 TraceCheckUtils]: 7: Hoare triple {2994#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {2995#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:37:23,446 INFO L290 TraceCheckUtils]: 8: Hoare triple {2995#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {2995#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:37:23,447 INFO L290 TraceCheckUtils]: 9: Hoare triple {2995#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [112] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_5 4294967296))) (or (and (= v_main_~y~0_4 v_main_~y~0_5) (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= |v_main_#t~post9_3| |v_main_#t~post9_1|) (<= .cse0 0)) (and (= v_main_~y~0_4 (+ v_main_~y~0_5 v_main_~z~0_3 (* (- 1) v_main_~z~0_2))) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= (+ v_main_~z~0_3 v_it_3 1) v_main_~z~0_2)) (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_5 (* v_it_3 4294967295)) 4294967296)))) (< v_main_~z~0_3 v_main_~z~0_2)))) InVars {main_~y~0=v_main_~y~0_5, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {2995#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:37:23,448 INFO L290 TraceCheckUtils]: 10: Hoare triple {2995#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [112] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_5 4294967296))) (or (and (= v_main_~y~0_4 v_main_~y~0_5) (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= |v_main_#t~post9_3| |v_main_#t~post9_1|) (<= .cse0 0)) (and (= v_main_~y~0_4 (+ v_main_~y~0_5 v_main_~z~0_3 (* (- 1) v_main_~z~0_2))) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= (+ v_main_~z~0_3 v_it_3 1) v_main_~z~0_2)) (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_5 (* v_it_3 4294967295)) 4294967296)))) (< v_main_~z~0_3 v_main_~z~0_2)))) InVars {main_~y~0=v_main_~y~0_5, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {2996#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:37:23,449 INFO L290 TraceCheckUtils]: 11: Hoare triple {2996#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {2996#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:37:23,449 INFO L290 TraceCheckUtils]: 12: Hoare triple {2996#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {2996#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:37:23,450 INFO L290 TraceCheckUtils]: 13: Hoare triple {2996#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {2997#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:37:23,451 INFO L290 TraceCheckUtils]: 14: Hoare triple {2997#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {2997#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:37:23,451 INFO L290 TraceCheckUtils]: 15: Hoare triple {2997#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {2997#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:37:23,452 INFO L272 TraceCheckUtils]: 16: Hoare triple {2997#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {2998#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-07 17:37:23,452 INFO L290 TraceCheckUtils]: 17: Hoare triple {2998#(not (= |__VERIFIER_assert_#in~cond| 0))} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2999#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-07 17:37:23,453 INFO L290 TraceCheckUtils]: 18: Hoare triple {2999#(not (= __VERIFIER_assert_~cond 0))} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2989#false} is VALID [2022-04-07 17:37:23,453 INFO L290 TraceCheckUtils]: 19: Hoare triple {2989#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2989#false} is VALID [2022-04-07 17:37:23,453 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-07 17:37:23,453 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 17:37:23,453 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1297606910] [2022-04-07 17:37:23,453 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1297606910] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 17:37:23,453 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [760801205] [2022-04-07 17:37:23,454 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-04-07 17:37:23,454 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 17:37:23,454 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 17:37:23,456 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 17:37:23,481 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2022-04-07 17:37:23,502 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-04-07 17:37:23,502 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-07 17:37:23,503 INFO L263 TraceCheckSpWp]: Trace formula consists of 65 conjuncts, 12 conjunts are in the unsatisfiable core [2022-04-07 17:37:23,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:37:23,522 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 17:37:23,763 INFO L272 TraceCheckUtils]: 0: Hoare triple {2988#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2988#true} is VALID [2022-04-07 17:37:23,764 INFO L290 TraceCheckUtils]: 1: Hoare triple {2988#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2988#true} is VALID [2022-04-07 17:37:23,764 INFO L290 TraceCheckUtils]: 2: Hoare triple {2988#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2988#true} is VALID [2022-04-07 17:37:23,764 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2988#true} {2988#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2988#true} is VALID [2022-04-07 17:37:23,764 INFO L272 TraceCheckUtils]: 4: Hoare triple {2988#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2988#true} is VALID [2022-04-07 17:37:23,765 INFO L290 TraceCheckUtils]: 5: Hoare triple {2988#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {2993#(= main_~y~0 0)} is VALID [2022-04-07 17:37:23,765 INFO L290 TraceCheckUtils]: 6: Hoare triple {2993#(= main_~y~0 0)} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {2994#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:37:23,766 INFO L290 TraceCheckUtils]: 7: Hoare triple {2994#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {2995#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:37:23,766 INFO L290 TraceCheckUtils]: 8: Hoare triple {2995#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {2995#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:37:23,767 INFO L290 TraceCheckUtils]: 9: Hoare triple {2995#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [112] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_5 4294967296))) (or (and (= v_main_~y~0_4 v_main_~y~0_5) (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= |v_main_#t~post9_3| |v_main_#t~post9_1|) (<= .cse0 0)) (and (= v_main_~y~0_4 (+ v_main_~y~0_5 v_main_~z~0_3 (* (- 1) v_main_~z~0_2))) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= (+ v_main_~z~0_3 v_it_3 1) v_main_~z~0_2)) (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_5 (* v_it_3 4294967295)) 4294967296)))) (< v_main_~z~0_3 v_main_~z~0_2)))) InVars {main_~y~0=v_main_~y~0_5, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {2995#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:37:23,767 INFO L290 TraceCheckUtils]: 10: Hoare triple {2995#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [112] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_5 4294967296))) (or (and (= v_main_~y~0_4 v_main_~y~0_5) (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= |v_main_#t~post9_3| |v_main_#t~post9_1|) (<= .cse0 0)) (and (= v_main_~y~0_4 (+ v_main_~y~0_5 v_main_~z~0_3 (* (- 1) v_main_~z~0_2))) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= (+ v_main_~z~0_3 v_it_3 1) v_main_~z~0_2)) (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_5 (* v_it_3 4294967295)) 4294967296)))) (< v_main_~z~0_3 v_main_~z~0_2)))) InVars {main_~y~0=v_main_~y~0_5, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {2996#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:37:23,768 INFO L290 TraceCheckUtils]: 11: Hoare triple {2996#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {2996#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:37:23,768 INFO L290 TraceCheckUtils]: 12: Hoare triple {2996#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {2996#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:37:23,769 INFO L290 TraceCheckUtils]: 13: Hoare triple {2996#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {2997#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:37:23,769 INFO L290 TraceCheckUtils]: 14: Hoare triple {2997#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {2997#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:37:23,770 INFO L290 TraceCheckUtils]: 15: Hoare triple {2997#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {2997#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:37:23,770 INFO L272 TraceCheckUtils]: 16: Hoare triple {2997#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {3052#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 17:37:23,771 INFO L290 TraceCheckUtils]: 17: Hoare triple {3052#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3056#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 17:37:23,771 INFO L290 TraceCheckUtils]: 18: Hoare triple {3056#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2989#false} is VALID [2022-04-07 17:37:23,771 INFO L290 TraceCheckUtils]: 19: Hoare triple {2989#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2989#false} is VALID [2022-04-07 17:37:23,771 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-07 17:37:23,771 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-07 17:37:36,799 WARN L833 $PredicateComparison]: unable to prove that (forall ((aux_mod_v_main_~x~0_50_31 Int)) (or (and (or (forall ((aux_div_v_main_~x~0_50_31 Int)) (not (= (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)) c_main_~x~0))) (forall ((aux_mod_v_main_~z~0_41_31 Int)) (or (let ((.cse0 (< 0 (mod c_main_~y~0 4294967296)))) (and (or .cse0 (forall ((aux_div_v_main_~z~0_41_31 Int)) (not (= (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31)) c_main_~z~0)))) (or (forall ((aux_div_v_main_~z~0_41_31 Int)) (or (not (< c_main_~z~0 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31)))) (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31))))))) (not .cse0)))) (< 0 aux_mod_v_main_~z~0_41_31) (< aux_mod_v_main_~z~0_41_31 0)))) (forall ((aux_div_v_main_~x~0_50_31 Int) (aux_mod_v_main_~z~0_41_31 Int)) (or (let ((.cse1 (< 0 (mod c_main_~y~0 4294967296)))) (and (or .cse1 (forall ((aux_div_v_main_~z~0_41_31 Int)) (not (= (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31)) c_main_~z~0)))) (or (forall ((aux_div_v_main_~z~0_41_31 Int)) (or (not (< c_main_~z~0 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31)))) (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31))))))) (not .cse1)))) (<= aux_mod_v_main_~z~0_41_31 0) (<= (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)) c_main_~x~0) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~z~0_41_31 (* v_it_5 4294967295)) 4294967296))) (<= (+ v_it_5 c_main_~x~0 1) (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (<= 1 v_it_5))) (<= 4294967296 aux_mod_v_main_~z~0_41_31)))) (<= aux_mod_v_main_~x~0_50_31 0) (<= 4294967296 aux_mod_v_main_~x~0_50_31))) is different from false [2022-04-07 17:39:32,952 INFO L290 TraceCheckUtils]: 19: Hoare triple {2989#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2989#false} is VALID [2022-04-07 17:39:32,953 INFO L290 TraceCheckUtils]: 18: Hoare triple {3056#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2989#false} is VALID [2022-04-07 17:39:32,953 INFO L290 TraceCheckUtils]: 17: Hoare triple {3052#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3056#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 17:39:32,954 INFO L272 TraceCheckUtils]: 16: Hoare triple {2997#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {3052#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 17:39:32,954 INFO L290 TraceCheckUtils]: 15: Hoare triple {2997#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {2997#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:39:32,955 INFO L290 TraceCheckUtils]: 14: Hoare triple {2997#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {2997#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:39:34,966 WARN L290 TraceCheckUtils]: 13: Hoare triple {3081#(forall ((aux_mod_v_main_~x~0_50_31 Int)) (or (<= aux_mod_v_main_~x~0_50_31 0) (<= 4294967296 aux_mod_v_main_~x~0_50_31) (and (or (forall ((aux_div_v_main_~x~0_50_31 Int)) (or (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)))))) (not (< 0 (mod main_~z~0 4294967296)))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~x~0_50_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)))))))))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {2997#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is UNKNOWN [2022-04-07 17:39:35,002 INFO L290 TraceCheckUtils]: 12: Hoare triple {3081#(forall ((aux_mod_v_main_~x~0_50_31 Int)) (or (<= aux_mod_v_main_~x~0_50_31 0) (<= 4294967296 aux_mod_v_main_~x~0_50_31) (and (or (forall ((aux_div_v_main_~x~0_50_31 Int)) (or (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)))))) (not (< 0 (mod main_~z~0 4294967296)))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~x~0_50_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)))))))))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {3081#(forall ((aux_mod_v_main_~x~0_50_31 Int)) (or (<= aux_mod_v_main_~x~0_50_31 0) (<= 4294967296 aux_mod_v_main_~x~0_50_31) (and (or (forall ((aux_div_v_main_~x~0_50_31 Int)) (or (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)))))) (not (< 0 (mod main_~z~0 4294967296)))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~x~0_50_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)))))))))} is VALID [2022-04-07 17:39:37,012 WARN L290 TraceCheckUtils]: 11: Hoare triple {3081#(forall ((aux_mod_v_main_~x~0_50_31 Int)) (or (<= aux_mod_v_main_~x~0_50_31 0) (<= 4294967296 aux_mod_v_main_~x~0_50_31) (and (or (forall ((aux_div_v_main_~x~0_50_31 Int)) (or (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)))))) (not (< 0 (mod main_~z~0 4294967296)))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~x~0_50_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)))))))))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {3081#(forall ((aux_mod_v_main_~x~0_50_31 Int)) (or (<= aux_mod_v_main_~x~0_50_31 0) (<= 4294967296 aux_mod_v_main_~x~0_50_31) (and (or (forall ((aux_div_v_main_~x~0_50_31 Int)) (or (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)))))) (not (< 0 (mod main_~z~0 4294967296)))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~x~0_50_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)))))))))} is UNKNOWN [2022-04-07 17:39:39,038 WARN L290 TraceCheckUtils]: 10: Hoare triple {3091#(forall ((aux_mod_v_main_~x~0_50_31 Int)) (or (<= aux_mod_v_main_~x~0_50_31 0) (<= 4294967296 aux_mod_v_main_~x~0_50_31) (and (forall ((aux_div_v_main_~x~0_50_31 Int) (aux_mod_v_main_~z~0_41_31 Int)) (or (<= aux_mod_v_main_~z~0_41_31 0) (<= 4294967296 aux_mod_v_main_~z~0_41_31) (and (or (forall ((aux_div_v_main_~z~0_41_31 Int)) (or (not (< main_~z~0 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31)))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))))) (not (< 0 (mod main_~y~0 4294967296)))) (or (forall ((aux_div_v_main_~z~0_41_31 Int)) (not (= main_~z~0 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31))))) (< 0 (mod main_~y~0 4294967296)))) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~z~0_41_31 (* v_it_5 4294967295)) 4294967296))) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (<= 1 v_it_5))) (<= (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)) main_~x~0))) (or (forall ((aux_div_v_main_~x~0_50_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))))) (forall ((aux_mod_v_main_~z~0_41_31 Int)) (or (and (or (forall ((aux_div_v_main_~z~0_41_31 Int)) (or (not (< main_~z~0 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31)))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))))) (not (< 0 (mod main_~y~0 4294967296)))) (or (forall ((aux_div_v_main_~z~0_41_31 Int)) (not (= main_~z~0 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31))))) (< 0 (mod main_~y~0 4294967296)))) (< 0 aux_mod_v_main_~z~0_41_31) (< aux_mod_v_main_~z~0_41_31 0)))))))} [112] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_5 4294967296))) (or (and (= v_main_~y~0_4 v_main_~y~0_5) (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= |v_main_#t~post9_3| |v_main_#t~post9_1|) (<= .cse0 0)) (and (= v_main_~y~0_4 (+ v_main_~y~0_5 v_main_~z~0_3 (* (- 1) v_main_~z~0_2))) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= (+ v_main_~z~0_3 v_it_3 1) v_main_~z~0_2)) (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_5 (* v_it_3 4294967295)) 4294967296)))) (< v_main_~z~0_3 v_main_~z~0_2)))) InVars {main_~y~0=v_main_~y~0_5, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {3081#(forall ((aux_mod_v_main_~x~0_50_31 Int)) (or (<= aux_mod_v_main_~x~0_50_31 0) (<= 4294967296 aux_mod_v_main_~x~0_50_31) (and (or (forall ((aux_div_v_main_~x~0_50_31 Int)) (or (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)))))) (not (< 0 (mod main_~z~0 4294967296)))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~x~0_50_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)))))))))} is UNKNOWN [2022-04-07 17:39:41,064 WARN L290 TraceCheckUtils]: 9: Hoare triple {3095#(forall ((aux_mod_v_main_~x~0_50_31 Int)) (or (<= aux_mod_v_main_~x~0_50_31 0) (<= 4294967296 aux_mod_v_main_~x~0_50_31) (and (or (not (< 0 (mod main_~y~0 4294967296))) (and (or (forall ((aux_mod_v_main_~z~0_41_31 Int)) (or (and (or (forall ((aux_div_v_main_~z~0_41_31 Int)) (or (not (< main_~z~0 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31)))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))))) (< 0 (mod (+ main_~z~0 main_~y~0 (* aux_mod_v_main_~z~0_41_31 4294967295)) 4294967296))) (forall ((aux_div_v_main_~z~0_41_31 Int) (aux_div_v_main_~y~0_38_31 Int) (aux_mod_v_main_~y~0_38_31 Int)) (or (<= aux_mod_v_main_~y~0_38_31 0) (<= (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31) (+ main_~z~0 main_~y~0)) (<= main_~y~0 (+ (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 main_~y~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (not (< 0 (mod (+ (* v_it_3 4294967295) aux_mod_v_main_~y~0_38_31) 4294967296))) (<= 1 v_it_3))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31 1) main_~y~0) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_38_31)))) (< 0 aux_mod_v_main_~z~0_41_31) (< aux_mod_v_main_~z~0_41_31 0))) (forall ((aux_div_v_main_~x~0_50_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)))))) (forall ((aux_div_v_main_~x~0_50_31 Int) (aux_mod_v_main_~z~0_41_31 Int)) (or (<= aux_mod_v_main_~z~0_41_31 0) (and (or (forall ((aux_div_v_main_~z~0_41_31 Int)) (or (not (< main_~z~0 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31)))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))))) (< 0 (mod (+ main_~z~0 main_~y~0 (* aux_mod_v_main_~z~0_41_31 4294967295)) 4294967296))) (forall ((aux_div_v_main_~z~0_41_31 Int) (aux_div_v_main_~y~0_38_31 Int) (aux_mod_v_main_~y~0_38_31 Int)) (or (<= aux_mod_v_main_~y~0_38_31 0) (<= (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31) (+ main_~z~0 main_~y~0)) (<= main_~y~0 (+ (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 main_~y~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (not (< 0 (mod (+ (* v_it_3 4294967295) aux_mod_v_main_~y~0_38_31) 4294967296))) (<= 1 v_it_3))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31 1) main_~y~0) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_38_31)))) (<= 4294967296 aux_mod_v_main_~z~0_41_31) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~z~0_41_31 (* v_it_5 4294967295)) 4294967296))) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (<= 1 v_it_5))) (<= (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)) main_~x~0))))) (or (and (or (< (div (+ (- 1) (* (- 1) main_~z~0)) (- 4294967296)) (+ 2 (div (+ (- 1) main_~z~0) 4294967296))) (forall ((aux_div_v_main_~x~0_50_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)))))) (or (forall ((aux_div_v_main_~x~0_50_31 Int)) (or (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (<= (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)) main_~x~0))) (<= (div (- main_~z~0) (- 4294967296)) (+ (div (+ main_~z~0 (- 4294967296)) 4294967296) 1)))) (< 0 (mod main_~y~0 4294967296))))))} [112] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_5 4294967296))) (or (and (= v_main_~y~0_4 v_main_~y~0_5) (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= |v_main_#t~post9_3| |v_main_#t~post9_1|) (<= .cse0 0)) (and (= v_main_~y~0_4 (+ v_main_~y~0_5 v_main_~z~0_3 (* (- 1) v_main_~z~0_2))) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= (+ v_main_~z~0_3 v_it_3 1) v_main_~z~0_2)) (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_5 (* v_it_3 4294967295)) 4294967296)))) (< v_main_~z~0_3 v_main_~z~0_2)))) InVars {main_~y~0=v_main_~y~0_5, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {3091#(forall ((aux_mod_v_main_~x~0_50_31 Int)) (or (<= aux_mod_v_main_~x~0_50_31 0) (<= 4294967296 aux_mod_v_main_~x~0_50_31) (and (forall ((aux_div_v_main_~x~0_50_31 Int) (aux_mod_v_main_~z~0_41_31 Int)) (or (<= aux_mod_v_main_~z~0_41_31 0) (<= 4294967296 aux_mod_v_main_~z~0_41_31) (and (or (forall ((aux_div_v_main_~z~0_41_31 Int)) (or (not (< main_~z~0 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31)))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))))) (not (< 0 (mod main_~y~0 4294967296)))) (or (forall ((aux_div_v_main_~z~0_41_31 Int)) (not (= main_~z~0 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31))))) (< 0 (mod main_~y~0 4294967296)))) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~z~0_41_31 (* v_it_5 4294967295)) 4294967296))) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (<= 1 v_it_5))) (<= (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)) main_~x~0))) (or (forall ((aux_div_v_main_~x~0_50_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))))) (forall ((aux_mod_v_main_~z~0_41_31 Int)) (or (and (or (forall ((aux_div_v_main_~z~0_41_31 Int)) (or (not (< main_~z~0 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31)))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))))) (not (< 0 (mod main_~y~0 4294967296)))) (or (forall ((aux_div_v_main_~z~0_41_31 Int)) (not (= main_~z~0 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31))))) (< 0 (mod main_~y~0 4294967296)))) (< 0 aux_mod_v_main_~z~0_41_31) (< aux_mod_v_main_~z~0_41_31 0)))))))} is UNKNOWN [2022-04-07 17:39:43,119 WARN L290 TraceCheckUtils]: 8: Hoare triple {3099#(or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_mod_v_main_~x~0_50_31 Int)) (or (<= aux_mod_v_main_~x~0_50_31 0) (and (or (not (< 0 (mod main_~y~0 4294967296))) (and (or (forall ((aux_mod_v_main_~z~0_41_31 Int)) (or (forall ((aux_div_v_main_~z~0_41_31 Int) (aux_div_v_main_~y~0_38_31 Int) (aux_mod_v_main_~y~0_38_31 Int)) (or (<= aux_mod_v_main_~y~0_38_31 0) (<= (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31) (+ main_~z~0 main_~y~0)) (<= main_~y~0 (+ (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 main_~y~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (not (< 0 (mod (+ (* v_it_3 4294967295) aux_mod_v_main_~y~0_38_31) 4294967296))) (<= 1 v_it_3))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31 1) main_~y~0) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_38_31))) (< 0 aux_mod_v_main_~z~0_41_31) (< aux_mod_v_main_~z~0_41_31 0))) (forall ((aux_div_v_main_~x~0_50_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)))))) (forall ((aux_div_v_main_~x~0_50_31 Int) (aux_mod_v_main_~z~0_41_31 Int)) (or (<= aux_mod_v_main_~z~0_41_31 0) (and (or (forall ((aux_div_v_main_~z~0_41_31 Int)) (or (not (< main_~z~0 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31)))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))))) (< 0 (mod (+ main_~z~0 main_~y~0 (* aux_mod_v_main_~z~0_41_31 4294967295)) 4294967296))) (forall ((aux_div_v_main_~z~0_41_31 Int) (aux_div_v_main_~y~0_38_31 Int) (aux_mod_v_main_~y~0_38_31 Int)) (or (<= aux_mod_v_main_~y~0_38_31 0) (<= (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31) (+ main_~z~0 main_~y~0)) (<= main_~y~0 (+ (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 main_~y~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (not (< 0 (mod (+ (* v_it_3 4294967295) aux_mod_v_main_~y~0_38_31) 4294967296))) (<= 1 v_it_3))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31 1) main_~y~0) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_38_31)))) (<= 4294967296 aux_mod_v_main_~z~0_41_31) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~z~0_41_31 (* v_it_5 4294967295)) 4294967296))) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (<= 1 v_it_5))) (<= (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)) main_~x~0))))) (or (forall ((aux_div_v_main_~x~0_50_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))))) (< 0 (mod main_~y~0 4294967296)))) (<= 4294967296 aux_mod_v_main_~x~0_50_31))))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {3095#(forall ((aux_mod_v_main_~x~0_50_31 Int)) (or (<= aux_mod_v_main_~x~0_50_31 0) (<= 4294967296 aux_mod_v_main_~x~0_50_31) (and (or (not (< 0 (mod main_~y~0 4294967296))) (and (or (forall ((aux_mod_v_main_~z~0_41_31 Int)) (or (and (or (forall ((aux_div_v_main_~z~0_41_31 Int)) (or (not (< main_~z~0 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31)))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))))) (< 0 (mod (+ main_~z~0 main_~y~0 (* aux_mod_v_main_~z~0_41_31 4294967295)) 4294967296))) (forall ((aux_div_v_main_~z~0_41_31 Int) (aux_div_v_main_~y~0_38_31 Int) (aux_mod_v_main_~y~0_38_31 Int)) (or (<= aux_mod_v_main_~y~0_38_31 0) (<= (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31) (+ main_~z~0 main_~y~0)) (<= main_~y~0 (+ (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 main_~y~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (not (< 0 (mod (+ (* v_it_3 4294967295) aux_mod_v_main_~y~0_38_31) 4294967296))) (<= 1 v_it_3))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31 1) main_~y~0) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_38_31)))) (< 0 aux_mod_v_main_~z~0_41_31) (< aux_mod_v_main_~z~0_41_31 0))) (forall ((aux_div_v_main_~x~0_50_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)))))) (forall ((aux_div_v_main_~x~0_50_31 Int) (aux_mod_v_main_~z~0_41_31 Int)) (or (<= aux_mod_v_main_~z~0_41_31 0) (and (or (forall ((aux_div_v_main_~z~0_41_31 Int)) (or (not (< main_~z~0 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31)))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))))) (< 0 (mod (+ main_~z~0 main_~y~0 (* aux_mod_v_main_~z~0_41_31 4294967295)) 4294967296))) (forall ((aux_div_v_main_~z~0_41_31 Int) (aux_div_v_main_~y~0_38_31 Int) (aux_mod_v_main_~y~0_38_31 Int)) (or (<= aux_mod_v_main_~y~0_38_31 0) (<= (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31) (+ main_~z~0 main_~y~0)) (<= main_~y~0 (+ (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 main_~y~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (not (< 0 (mod (+ (* v_it_3 4294967295) aux_mod_v_main_~y~0_38_31) 4294967296))) (<= 1 v_it_3))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31 1) main_~y~0) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_38_31)))) (<= 4294967296 aux_mod_v_main_~z~0_41_31) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~z~0_41_31 (* v_it_5 4294967295)) 4294967296))) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (<= 1 v_it_5))) (<= (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)) main_~x~0))))) (or (and (or (< (div (+ (- 1) (* (- 1) main_~z~0)) (- 4294967296)) (+ 2 (div (+ (- 1) main_~z~0) 4294967296))) (forall ((aux_div_v_main_~x~0_50_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)))))) (or (forall ((aux_div_v_main_~x~0_50_31 Int)) (or (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (<= (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)) main_~x~0))) (<= (div (- main_~z~0) (- 4294967296)) (+ (div (+ main_~z~0 (- 4294967296)) 4294967296) 1)))) (< 0 (mod main_~y~0 4294967296))))))} is UNKNOWN [2022-04-07 17:39:43,140 INFO L290 TraceCheckUtils]: 7: Hoare triple {3103#(or (<= (div (- main_~x~0) (- 4294967296)) (+ (div (+ main_~x~0 (- 4294967296)) 4294967296) 1)) (< 0 (mod main_~y~0 4294967296)))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {3099#(or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_mod_v_main_~x~0_50_31 Int)) (or (<= aux_mod_v_main_~x~0_50_31 0) (and (or (not (< 0 (mod main_~y~0 4294967296))) (and (or (forall ((aux_mod_v_main_~z~0_41_31 Int)) (or (forall ((aux_div_v_main_~z~0_41_31 Int) (aux_div_v_main_~y~0_38_31 Int) (aux_mod_v_main_~y~0_38_31 Int)) (or (<= aux_mod_v_main_~y~0_38_31 0) (<= (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31) (+ main_~z~0 main_~y~0)) (<= main_~y~0 (+ (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 main_~y~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (not (< 0 (mod (+ (* v_it_3 4294967295) aux_mod_v_main_~y~0_38_31) 4294967296))) (<= 1 v_it_3))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31 1) main_~y~0) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_38_31))) (< 0 aux_mod_v_main_~z~0_41_31) (< aux_mod_v_main_~z~0_41_31 0))) (forall ((aux_div_v_main_~x~0_50_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)))))) (forall ((aux_div_v_main_~x~0_50_31 Int) (aux_mod_v_main_~z~0_41_31 Int)) (or (<= aux_mod_v_main_~z~0_41_31 0) (and (or (forall ((aux_div_v_main_~z~0_41_31 Int)) (or (not (< main_~z~0 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31)))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))))) (< 0 (mod (+ main_~z~0 main_~y~0 (* aux_mod_v_main_~z~0_41_31 4294967295)) 4294967296))) (forall ((aux_div_v_main_~z~0_41_31 Int) (aux_div_v_main_~y~0_38_31 Int) (aux_mod_v_main_~y~0_38_31 Int)) (or (<= aux_mod_v_main_~y~0_38_31 0) (<= (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31) (+ main_~z~0 main_~y~0)) (<= main_~y~0 (+ (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 main_~y~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (not (< 0 (mod (+ (* v_it_3 4294967295) aux_mod_v_main_~y~0_38_31) 4294967296))) (<= 1 v_it_3))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31 1) main_~y~0) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_38_31)))) (<= 4294967296 aux_mod_v_main_~z~0_41_31) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~z~0_41_31 (* v_it_5 4294967295)) 4294967296))) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (<= 1 v_it_5))) (<= (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)) main_~x~0))))) (or (forall ((aux_div_v_main_~x~0_50_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))))) (< 0 (mod main_~y~0 4294967296)))) (<= 4294967296 aux_mod_v_main_~x~0_50_31))))} is VALID [2022-04-07 17:39:43,141 INFO L290 TraceCheckUtils]: 6: Hoare triple {2988#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {3103#(or (<= (div (- main_~x~0) (- 4294967296)) (+ (div (+ main_~x~0 (- 4294967296)) 4294967296) 1)) (< 0 (mod main_~y~0 4294967296)))} is VALID [2022-04-07 17:39:43,141 INFO L290 TraceCheckUtils]: 5: Hoare triple {2988#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {2988#true} is VALID [2022-04-07 17:39:43,141 INFO L272 TraceCheckUtils]: 4: Hoare triple {2988#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2988#true} is VALID [2022-04-07 17:39:43,141 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2988#true} {2988#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2988#true} is VALID [2022-04-07 17:39:43,142 INFO L290 TraceCheckUtils]: 2: Hoare triple {2988#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2988#true} is VALID [2022-04-07 17:39:43,142 INFO L290 TraceCheckUtils]: 1: Hoare triple {2988#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2988#true} is VALID [2022-04-07 17:39:43,142 INFO L272 TraceCheckUtils]: 0: Hoare triple {2988#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2988#true} is VALID [2022-04-07 17:39:43,142 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 1 refuted. 1 times theorem prover too weak. 0 trivial. 2 not checked. [2022-04-07 17:39:43,142 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [760801205] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-07 17:39:43,142 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-07 17:39:43,142 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9, 10] total 17 [2022-04-07 17:39:43,142 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [308427648] [2022-04-07 17:39:43,142 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-07 17:39:43,143 INFO L78 Accepts]: Start accepts. Automaton has has 17 states, 17 states have (on average 1.6470588235294117) internal successors, (28), 14 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 20 [2022-04-07 17:39:43,143 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 17:39:43,143 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 17 states, 17 states have (on average 1.6470588235294117) internal successors, (28), 14 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:39:53,593 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 34 edges. 29 inductive. 0 not inductive. 5 times theorem prover too weak to decide inductivity. [2022-04-07 17:39:53,593 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 17 states [2022-04-07 17:39:53,593 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 17:39:53,593 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2022-04-07 17:39:53,593 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=49, Invalid=177, Unknown=18, NotChecked=28, Total=272 [2022-04-07 17:39:53,594 INFO L87 Difference]: Start difference. First operand 44 states and 70 transitions. Second operand has 17 states, 17 states have (on average 1.6470588235294117) internal successors, (28), 14 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:40:16,687 WARN L232 SmtUtils]: Spent 10.21s on a formula simplification that was a NOOP. DAG size: 108 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-07 17:40:20,920 WARN L833 $PredicateComparison]: unable to prove that (and (= |c_#NULL.base| |c_old(#NULL.base)|) (or (forall ((aux_mod_v_main_~x~0_50_31 Int)) (or (<= aux_mod_v_main_~x~0_50_31 0) (<= 4294967296 aux_mod_v_main_~x~0_50_31) (let ((.cse3 (< 0 (mod c_main_~y~0 4294967296))) (.cse0 (forall ((aux_div_v_main_~x~0_50_31 Int)) (not (= (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)) c_main_~x~0))))) (and (or (and (or .cse0 (forall ((aux_mod_v_main_~z~0_41_31 Int)) (or (forall ((aux_div_v_main_~z~0_41_31 Int) (aux_div_v_main_~y~0_38_31 Int) (aux_mod_v_main_~y~0_38_31 Int)) (let ((.cse1 (* aux_div_v_main_~y~0_38_31 4294967296))) (or (<= aux_mod_v_main_~y~0_38_31 0) (<= c_main_~y~0 (+ .cse1 aux_mod_v_main_~y~0_38_31)) (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31 1) c_main_~y~0))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 c_main_~y~0 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (not (< 0 (mod (+ (* v_it_3 4294967295) aux_mod_v_main_~y~0_38_31) 4294967296))) (<= 1 v_it_3))) (<= (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) .cse1 aux_mod_v_main_~y~0_38_31) (+ c_main_~y~0 c_main_~z~0)) (<= 4294967296 aux_mod_v_main_~y~0_38_31)))) (< 0 aux_mod_v_main_~z~0_41_31) (< aux_mod_v_main_~z~0_41_31 0)))) (forall ((aux_div_v_main_~x~0_50_31 Int) (aux_mod_v_main_~z~0_41_31 Int)) (or (<= aux_mod_v_main_~z~0_41_31 0) (<= (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)) c_main_~x~0) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~z~0_41_31 (* v_it_5 4294967295)) 4294967296))) (<= (+ v_it_5 c_main_~x~0 1) (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (<= 1 v_it_5))) (and (or (forall ((aux_div_v_main_~z~0_41_31 Int)) (or (not (< c_main_~z~0 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31)))) (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31))))))) (< 0 (mod (+ (* aux_mod_v_main_~z~0_41_31 4294967295) c_main_~y~0 c_main_~z~0) 4294967296))) (forall ((aux_div_v_main_~z~0_41_31 Int) (aux_div_v_main_~y~0_38_31 Int) (aux_mod_v_main_~y~0_38_31 Int)) (let ((.cse2 (* aux_div_v_main_~y~0_38_31 4294967296))) (or (<= aux_mod_v_main_~y~0_38_31 0) (<= c_main_~y~0 (+ .cse2 aux_mod_v_main_~y~0_38_31)) (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31 1) c_main_~y~0))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 c_main_~y~0 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (not (< 0 (mod (+ (* v_it_3 4294967295) aux_mod_v_main_~y~0_38_31) 4294967296))) (<= 1 v_it_3))) (<= (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) .cse2 aux_mod_v_main_~y~0_38_31) (+ c_main_~y~0 c_main_~z~0)) (<= 4294967296 aux_mod_v_main_~y~0_38_31))))) (<= 4294967296 aux_mod_v_main_~z~0_41_31)))) (not .cse3)) (or .cse3 .cse0))))) (< 0 (mod c_main_~z~0 4294967296))) (or (< 0 (mod c_main_~y~0 4294967296)) (<= (div (* (- 1) c_main_~x~0) (- 4294967296)) (+ 1 (div (+ (- 4294967296) c_main_~x~0) 4294967296)))) (forall ((aux_mod_v_main_~x~0_50_31 Int)) (or (<= aux_mod_v_main_~x~0_50_31 0) (<= 4294967296 aux_mod_v_main_~x~0_50_31) (let ((.cse4 (< 0 (mod c_main_~y~0 4294967296))) (.cse5 (forall ((aux_div_v_main_~x~0_50_31 Int)) (not (= (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)) c_main_~x~0))))) (and (or (not .cse4) (and (or .cse5 (forall ((aux_mod_v_main_~z~0_41_31 Int)) (or (and (or (forall ((aux_div_v_main_~z~0_41_31 Int)) (or (not (< c_main_~z~0 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31)))) (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31))))))) (< 0 (mod (+ (* aux_mod_v_main_~z~0_41_31 4294967295) c_main_~y~0 c_main_~z~0) 4294967296))) (forall ((aux_div_v_main_~z~0_41_31 Int) (aux_div_v_main_~y~0_38_31 Int) (aux_mod_v_main_~y~0_38_31 Int)) (let ((.cse6 (* aux_div_v_main_~y~0_38_31 4294967296))) (or (<= aux_mod_v_main_~y~0_38_31 0) (<= c_main_~y~0 (+ .cse6 aux_mod_v_main_~y~0_38_31)) (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31 1) c_main_~y~0))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 c_main_~y~0 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (not (< 0 (mod (+ (* v_it_3 4294967295) aux_mod_v_main_~y~0_38_31) 4294967296))) (<= 1 v_it_3))) (<= (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) .cse6 aux_mod_v_main_~y~0_38_31) (+ c_main_~y~0 c_main_~z~0)) (<= 4294967296 aux_mod_v_main_~y~0_38_31))))) (< 0 aux_mod_v_main_~z~0_41_31) (< aux_mod_v_main_~z~0_41_31 0)))) (forall ((aux_div_v_main_~x~0_50_31 Int) (aux_mod_v_main_~z~0_41_31 Int)) (or (<= aux_mod_v_main_~z~0_41_31 0) (<= (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)) c_main_~x~0) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~z~0_41_31 (* v_it_5 4294967295)) 4294967296))) (<= (+ v_it_5 c_main_~x~0 1) (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (<= 1 v_it_5))) (and (or (forall ((aux_div_v_main_~z~0_41_31 Int)) (or (not (< c_main_~z~0 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31)))) (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31))))))) (< 0 (mod (+ (* aux_mod_v_main_~z~0_41_31 4294967295) c_main_~y~0 c_main_~z~0) 4294967296))) (forall ((aux_div_v_main_~z~0_41_31 Int) (aux_div_v_main_~y~0_38_31 Int) (aux_mod_v_main_~y~0_38_31 Int)) (let ((.cse7 (* aux_div_v_main_~y~0_38_31 4294967296))) (or (<= aux_mod_v_main_~y~0_38_31 0) (<= c_main_~y~0 (+ .cse7 aux_mod_v_main_~y~0_38_31)) (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31 1) c_main_~y~0))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 c_main_~y~0 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (not (< 0 (mod (+ (* v_it_3 4294967295) aux_mod_v_main_~y~0_38_31) 4294967296))) (<= 1 v_it_3))) (<= (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) .cse7 aux_mod_v_main_~y~0_38_31) (+ c_main_~y~0 c_main_~z~0)) (<= 4294967296 aux_mod_v_main_~y~0_38_31))))) (<= 4294967296 aux_mod_v_main_~z~0_41_31))))) (or .cse4 (let ((.cse8 (* (- 1) c_main_~z~0))) (and (or (<= (div .cse8 (- 4294967296)) (+ (div (+ (- 4294967296) c_main_~z~0) 4294967296) 1)) (forall ((aux_div_v_main_~x~0_50_31 Int)) (or (<= (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)) c_main_~x~0) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ (* v_it_5 4294967295) c_main_~z~0) 4294967296))) (<= (+ v_it_5 c_main_~x~0 1) (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (<= 1 v_it_5)))))) (or .cse5 (< (div (+ (- 1) .cse8) (- 4294967296)) (+ 2 (div (+ (- 1) c_main_~z~0) 4294967296))))))))))) (= |c_#NULL.offset| |c_old(#NULL.offset)|)) is different from false [2022-04-07 17:40:43,510 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:40:43,510 INFO L93 Difference]: Finished difference Result 66 states and 105 transitions. [2022-04-07 17:40:43,510 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2022-04-07 17:40:43,511 INFO L78 Accepts]: Start accepts. Automaton has has 17 states, 17 states have (on average 1.6470588235294117) internal successors, (28), 14 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 20 [2022-04-07 17:40:43,511 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 17:40:43,511 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17 states, 17 states have (on average 1.6470588235294117) internal successors, (28), 14 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:40:43,512 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 65 transitions. [2022-04-07 17:40:43,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17 states, 17 states have (on average 1.6470588235294117) internal successors, (28), 14 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:40:43,513 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 65 transitions. [2022-04-07 17:40:43,513 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 17 states and 65 transitions. [2022-04-07 17:40:52,175 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 65 edges. 61 inductive. 0 not inductive. 4 times theorem prover too weak to decide inductivity. [2022-04-07 17:40:52,176 INFO L225 Difference]: With dead ends: 66 [2022-04-07 17:40:52,176 INFO L226 Difference]: Without dead ends: 63 [2022-04-07 17:40:52,177 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 64 GetRequests, 33 SyntacticMatches, 6 SemanticMatches, 25 ConstructedPredicates, 2 IntricatePredicates, 0 DeprecatedPredicates, 117 ImplicationChecksByTransitivity, 92.4s TimeCoverageRelationStatistics Valid=121, Invalid=453, Unknown=34, NotChecked=94, Total=702 [2022-04-07 17:40:52,177 INFO L913 BasicCegarLoop]: 11 mSDtfsCounter, 31 mSDsluCounter, 70 mSDsCounter, 0 mSdLazyCounter, 106 mSolverCounterSat, 16 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 31 SdHoareTripleChecker+Valid, 81 SdHoareTripleChecker+Invalid, 211 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 16 IncrementalHoareTripleChecker+Valid, 106 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 89 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-04-07 17:40:52,177 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [31 Valid, 81 Invalid, 211 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [16 Valid, 106 Invalid, 0 Unknown, 89 Unchecked, 0.2s Time] [2022-04-07 17:40:52,178 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63 states. [2022-04-07 17:40:52,179 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63 to 46. [2022-04-07 17:40:52,179 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 17:40:52,180 INFO L82 GeneralOperation]: Start isEquivalent. First operand 63 states. Second operand has 46 states, 41 states have (on average 1.7073170731707317) internal successors, (70), 41 states have internal predecessors, (70), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:40:52,180 INFO L74 IsIncluded]: Start isIncluded. First operand 63 states. Second operand has 46 states, 41 states have (on average 1.7073170731707317) internal successors, (70), 41 states have internal predecessors, (70), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:40:52,180 INFO L87 Difference]: Start difference. First operand 63 states. Second operand has 46 states, 41 states have (on average 1.7073170731707317) internal successors, (70), 41 states have internal predecessors, (70), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:40:52,181 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:40:52,181 INFO L93 Difference]: Finished difference Result 63 states and 102 transitions. [2022-04-07 17:40:52,182 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 102 transitions. [2022-04-07 17:40:52,182 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:40:52,182 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:40:52,182 INFO L74 IsIncluded]: Start isIncluded. First operand has 46 states, 41 states have (on average 1.7073170731707317) internal successors, (70), 41 states have internal predecessors, (70), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 63 states. [2022-04-07 17:40:52,182 INFO L87 Difference]: Start difference. First operand has 46 states, 41 states have (on average 1.7073170731707317) internal successors, (70), 41 states have internal predecessors, (70), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 63 states. [2022-04-07 17:40:52,183 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:40:52,184 INFO L93 Difference]: Finished difference Result 63 states and 102 transitions. [2022-04-07 17:40:52,184 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 102 transitions. [2022-04-07 17:40:52,184 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:40:52,184 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:40:52,184 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 17:40:52,184 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 17:40:52,184 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46 states, 41 states have (on average 1.7073170731707317) internal successors, (70), 41 states have internal predecessors, (70), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:40:52,185 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 74 transitions. [2022-04-07 17:40:52,185 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 74 transitions. Word has length 20 [2022-04-07 17:40:52,185 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 17:40:52,185 INFO L478 AbstractCegarLoop]: Abstraction has 46 states and 74 transitions. [2022-04-07 17:40:52,185 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 17 states, 17 states have (on average 1.6470588235294117) internal successors, (28), 14 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:40:52,186 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 74 transitions. [2022-04-07 17:40:52,186 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2022-04-07 17:40:52,186 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 17:40:52,186 INFO L499 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 17:40:52,207 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Ended with exit code 0 [2022-04-07 17:40:52,399 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable11 [2022-04-07 17:40:52,400 INFO L403 AbstractCegarLoop]: === Iteration 13 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 17:40:52,400 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 17:40:52,400 INFO L85 PathProgramCache]: Analyzing trace with hash -369501645, now seen corresponding path program 1 times [2022-04-07 17:40:52,400 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 17:40:52,400 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [971685018] [2022-04-07 17:40:52,400 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:40:52,400 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 17:40:52,410 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.0))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-07 17:40:52,411 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.1))) (+ main_~y~0_9 .cse0 (* (- 4294967296) (div (+ main_~y~0_9 .cse0) 4294967296)))) 0)) [2022-04-07 17:40:52,412 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.2))) (+ main_~y~0_13 .cse0 (* (- 4294967296) (div (+ main_~y~0_13 .cse0) 4294967296)))) 0)) [2022-04-07 17:40:52,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:40:52,436 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.6))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-07 17:40:52,439 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.7))) (+ main_~y~0_9 .cse0 (* (- 4294967296) (div (+ main_~y~0_9 .cse0) 4294967296)))) 0)) [2022-04-07 17:40:52,442 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.8))) (+ main_~y~0_13 .cse0 (* (- 4294967296) (div (+ main_~y~0_13 .cse0) 4294967296)))) 0)) [2022-04-07 17:40:52,606 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 17:40:52,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:40:52,611 INFO L290 TraceCheckUtils]: 0: Hoare triple {3398#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3388#true} is VALID [2022-04-07 17:40:52,611 INFO L290 TraceCheckUtils]: 1: Hoare triple {3388#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3388#true} is VALID [2022-04-07 17:40:52,611 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {3388#true} {3388#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3388#true} is VALID [2022-04-07 17:40:52,612 INFO L272 TraceCheckUtils]: 0: Hoare triple {3388#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3398#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 17:40:52,612 INFO L290 TraceCheckUtils]: 1: Hoare triple {3398#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3388#true} is VALID [2022-04-07 17:40:52,612 INFO L290 TraceCheckUtils]: 2: Hoare triple {3388#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3388#true} is VALID [2022-04-07 17:40:52,612 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3388#true} {3388#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3388#true} is VALID [2022-04-07 17:40:52,612 INFO L272 TraceCheckUtils]: 4: Hoare triple {3388#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3388#true} is VALID [2022-04-07 17:40:52,613 INFO L290 TraceCheckUtils]: 5: Hoare triple {3388#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {3393#(= main_~y~0 0)} is VALID [2022-04-07 17:40:52,614 INFO L290 TraceCheckUtils]: 6: Hoare triple {3393#(= main_~y~0 0)} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {3394#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:40:52,614 INFO L290 TraceCheckUtils]: 7: Hoare triple {3394#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {3394#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:40:52,615 INFO L290 TraceCheckUtils]: 8: Hoare triple {3394#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {3394#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:40:52,623 INFO L290 TraceCheckUtils]: 9: Hoare triple {3394#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [112] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_5 4294967296))) (or (and (= v_main_~y~0_4 v_main_~y~0_5) (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= |v_main_#t~post9_3| |v_main_#t~post9_1|) (<= .cse0 0)) (and (= v_main_~y~0_4 (+ v_main_~y~0_5 v_main_~z~0_3 (* (- 1) v_main_~z~0_2))) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= (+ v_main_~z~0_3 v_it_3 1) v_main_~z~0_2)) (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_5 (* v_it_3 4294967295)) 4294967296)))) (< v_main_~z~0_3 v_main_~z~0_2)))) InVars {main_~y~0=v_main_~y~0_5, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {3394#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:40:52,624 INFO L290 TraceCheckUtils]: 10: Hoare triple {3394#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {3394#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:40:52,624 INFO L290 TraceCheckUtils]: 11: Hoare triple {3394#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {3394#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:40:52,625 INFO L290 TraceCheckUtils]: 12: Hoare triple {3394#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {3394#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:40:52,626 INFO L290 TraceCheckUtils]: 13: Hoare triple {3394#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {3394#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:40:52,627 INFO L290 TraceCheckUtils]: 14: Hoare triple {3394#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {3395#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:40:52,628 INFO L290 TraceCheckUtils]: 15: Hoare triple {3395#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {3395#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:40:52,629 INFO L272 TraceCheckUtils]: 16: Hoare triple {3395#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {3396#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-07 17:40:52,629 INFO L290 TraceCheckUtils]: 17: Hoare triple {3396#(not (= |__VERIFIER_assert_#in~cond| 0))} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3397#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-07 17:40:52,630 INFO L290 TraceCheckUtils]: 18: Hoare triple {3397#(not (= __VERIFIER_assert_~cond 0))} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {3389#false} is VALID [2022-04-07 17:40:52,630 INFO L290 TraceCheckUtils]: 19: Hoare triple {3389#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3389#false} is VALID [2022-04-07 17:40:52,630 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-04-07 17:40:52,630 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 17:40:52,630 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [971685018] [2022-04-07 17:40:52,630 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [971685018] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 17:40:52,630 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1767127502] [2022-04-07 17:40:52,630 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:40:52,630 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 17:40:52,631 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 17:40:52,632 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 17:40:52,640 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2022-04-07 17:40:52,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:40:52,680 INFO L263 TraceCheckSpWp]: Trace formula consists of 65 conjuncts, 7 conjunts are in the unsatisfiable core [2022-04-07 17:40:52,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:40:52,694 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 17:40:53,202 INFO L272 TraceCheckUtils]: 0: Hoare triple {3388#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3388#true} is VALID [2022-04-07 17:40:53,203 INFO L290 TraceCheckUtils]: 1: Hoare triple {3388#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3388#true} is VALID [2022-04-07 17:40:53,203 INFO L290 TraceCheckUtils]: 2: Hoare triple {3388#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3388#true} is VALID [2022-04-07 17:40:53,203 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3388#true} {3388#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3388#true} is VALID [2022-04-07 17:40:53,203 INFO L272 TraceCheckUtils]: 4: Hoare triple {3388#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3388#true} is VALID [2022-04-07 17:40:53,203 INFO L290 TraceCheckUtils]: 5: Hoare triple {3388#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {3388#true} is VALID [2022-04-07 17:40:53,204 INFO L290 TraceCheckUtils]: 6: Hoare triple {3388#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {3395#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:40:53,204 INFO L290 TraceCheckUtils]: 7: Hoare triple {3395#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {3395#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:40:53,204 INFO L290 TraceCheckUtils]: 8: Hoare triple {3395#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {3395#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:40:53,205 INFO L290 TraceCheckUtils]: 9: Hoare triple {3395#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [112] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_5 4294967296))) (or (and (= v_main_~y~0_4 v_main_~y~0_5) (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= |v_main_#t~post9_3| |v_main_#t~post9_1|) (<= .cse0 0)) (and (= v_main_~y~0_4 (+ v_main_~y~0_5 v_main_~z~0_3 (* (- 1) v_main_~z~0_2))) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= (+ v_main_~z~0_3 v_it_3 1) v_main_~z~0_2)) (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_5 (* v_it_3 4294967295)) 4294967296)))) (< v_main_~z~0_3 v_main_~z~0_2)))) InVars {main_~y~0=v_main_~y~0_5, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {3395#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:40:53,205 INFO L290 TraceCheckUtils]: 10: Hoare triple {3395#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {3432#(and (not (< 0 (mod main_~y~0 4294967296))) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:40:53,206 INFO L290 TraceCheckUtils]: 11: Hoare triple {3432#(and (not (< 0 (mod main_~y~0 4294967296))) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {3432#(and (not (< 0 (mod main_~y~0 4294967296))) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:40:53,206 INFO L290 TraceCheckUtils]: 12: Hoare triple {3432#(and (not (< 0 (mod main_~y~0 4294967296))) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {3432#(and (not (< 0 (mod main_~y~0 4294967296))) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:40:53,207 INFO L290 TraceCheckUtils]: 13: Hoare triple {3432#(and (not (< 0 (mod main_~y~0 4294967296))) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {3432#(and (not (< 0 (mod main_~y~0 4294967296))) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:40:53,208 INFO L290 TraceCheckUtils]: 14: Hoare triple {3432#(and (not (< 0 (mod main_~y~0 4294967296))) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {3395#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:40:53,209 INFO L290 TraceCheckUtils]: 15: Hoare triple {3395#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {3395#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:40:53,209 INFO L272 TraceCheckUtils]: 16: Hoare triple {3395#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {3451#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 17:40:53,210 INFO L290 TraceCheckUtils]: 17: Hoare triple {3451#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3455#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 17:40:53,210 INFO L290 TraceCheckUtils]: 18: Hoare triple {3455#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {3389#false} is VALID [2022-04-07 17:40:53,210 INFO L290 TraceCheckUtils]: 19: Hoare triple {3389#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3389#false} is VALID [2022-04-07 17:40:53,210 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-04-07 17:40:53,210 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-07 17:41:16,533 WARN L833 $PredicateComparison]: unable to prove that (forall ((aux_mod_v_main_~x~0_53_31 Int)) (or (<= aux_mod_v_main_~x~0_53_31 0) (<= 4294967296 aux_mod_v_main_~x~0_53_31) (let ((.cse0 (< 0 (mod c_main_~y~0 4294967296)))) (and (or .cse0 (forall ((aux_div_v_main_~x~0_53_31 Int)) (not (= (+ aux_mod_v_main_~x~0_53_31 (* aux_div_v_main_~x~0_53_31 4294967296)) c_main_~x~0)))) (or (and (forall ((aux_div_v_main_~x~0_53_31 Int) (aux_mod_v_main_~y~0_42_31 Int) (aux_div_v_main_~y~0_42_31 Int)) (let ((.cse1 (* aux_div_v_main_~y~0_42_31 4294967296))) (or (<= (+ .cse1 aux_mod_v_main_~y~0_42_31 c_main_~x~0) (+ aux_mod_v_main_~x~0_53_31 c_main_~y~0 (* aux_div_v_main_~x~0_53_31 4294967296))) (<= 4294967296 aux_mod_v_main_~y~0_42_31) (<= aux_mod_v_main_~y~0_42_31 0) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (not (< 0 (mod (+ (* v_it_6 4294967295) c_main_~y~0) 4294967296))) (<= (+ v_it_6 (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31 1) c_main_~y~0))) (exists ((v_it_6 Int)) (and (<= (+ aux_mod_v_main_~x~0_53_31 v_it_6 c_main_~y~0 (* aux_div_v_main_~x~0_53_31 4294967296) 1) (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31 c_main_~x~0)) (<= 1 v_it_6) (not (< 0 (mod (+ aux_mod_v_main_~y~0_42_31 (* v_it_6 4294967295)) 4294967296))))) (<= c_main_~y~0 (+ .cse1 aux_mod_v_main_~y~0_42_31))))) (or (< 0 (mod (+ aux_mod_v_main_~x~0_53_31 (* 4294967295 c_main_~x~0) c_main_~y~0) 4294967296)) (forall ((aux_div_v_main_~x~0_53_31 Int)) (or (not (< (+ aux_mod_v_main_~x~0_53_31 (* aux_div_v_main_~x~0_53_31 4294967296)) c_main_~x~0)) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (not (< 0 (mod (+ (* v_it_6 4294967295) c_main_~y~0) 4294967296))) (<= (+ aux_mod_v_main_~x~0_53_31 v_it_6 (* aux_div_v_main_~x~0_53_31 4294967296) 1) c_main_~x~0))))))) (not .cse0)))))) is different from false [2022-04-07 17:41:46,250 INFO L290 TraceCheckUtils]: 19: Hoare triple {3389#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3389#false} is VALID [2022-04-07 17:41:46,250 INFO L290 TraceCheckUtils]: 18: Hoare triple {3455#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {3389#false} is VALID [2022-04-07 17:41:46,251 INFO L290 TraceCheckUtils]: 17: Hoare triple {3451#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3455#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 17:41:46,252 INFO L272 TraceCheckUtils]: 16: Hoare triple {3395#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {3451#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 17:41:46,252 INFO L290 TraceCheckUtils]: 15: Hoare triple {3395#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {3395#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:41:48,267 WARN L290 TraceCheckUtils]: 14: Hoare triple {3477#(forall ((aux_mod_v_main_~x~0_53_31 Int)) (or (and (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~x~0_53_31 Int)) (or (not (< (+ aux_mod_v_main_~x~0_53_31 (* aux_div_v_main_~x~0_53_31 4294967296)) main_~x~0)) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_53_31 v_it_6 (* aux_div_v_main_~x~0_53_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296)))))))) (or (forall ((aux_div_v_main_~x~0_53_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_53_31 (* aux_div_v_main_~x~0_53_31 4294967296))))) (< 0 (mod main_~y~0 4294967296)))) (<= aux_mod_v_main_~x~0_53_31 0) (<= 4294967296 aux_mod_v_main_~x~0_53_31)))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {3395#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is UNKNOWN [2022-04-07 17:41:50,285 WARN L290 TraceCheckUtils]: 13: Hoare triple {3481#(forall ((aux_mod_v_main_~x~0_53_31 Int)) (or (and (or (not (< 0 (mod main_~y~0 4294967296))) (and (or (forall ((aux_div_v_main_~x~0_53_31 Int)) (or (not (< (+ aux_mod_v_main_~x~0_53_31 (* aux_div_v_main_~x~0_53_31 4294967296)) main_~x~0)) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_53_31 v_it_6 (* aux_div_v_main_~x~0_53_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))))) (< 0 (mod (+ aux_mod_v_main_~x~0_53_31 main_~y~0 (* main_~x~0 4294967295)) 4294967296))) (forall ((aux_div_v_main_~x~0_53_31 Int) (aux_mod_v_main_~y~0_42_31 Int) (aux_div_v_main_~y~0_42_31 Int)) (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ v_it_6 (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31 1) main_~y~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_42_31) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_53_31 v_it_6 main_~y~0 (* aux_div_v_main_~x~0_53_31 4294967296) 1) (+ main_~x~0 (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (not (< 0 (mod (+ aux_mod_v_main_~y~0_42_31 (* v_it_6 4294967295)) 4294967296))))) (<= aux_mod_v_main_~y~0_42_31 0) (<= main_~y~0 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (<= (+ main_~x~0 (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31) (+ aux_mod_v_main_~x~0_53_31 main_~y~0 (* aux_div_v_main_~x~0_53_31 4294967296))))))) (or (forall ((aux_div_v_main_~x~0_53_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_53_31 (* aux_div_v_main_~x~0_53_31 4294967296))))) (< 0 (mod main_~y~0 4294967296)))) (<= aux_mod_v_main_~x~0_53_31 0) (<= 4294967296 aux_mod_v_main_~x~0_53_31)))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {3477#(forall ((aux_mod_v_main_~x~0_53_31 Int)) (or (and (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~x~0_53_31 Int)) (or (not (< (+ aux_mod_v_main_~x~0_53_31 (* aux_div_v_main_~x~0_53_31 4294967296)) main_~x~0)) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_53_31 v_it_6 (* aux_div_v_main_~x~0_53_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296)))))))) (or (forall ((aux_div_v_main_~x~0_53_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_53_31 (* aux_div_v_main_~x~0_53_31 4294967296))))) (< 0 (mod main_~y~0 4294967296)))) (<= aux_mod_v_main_~x~0_53_31 0) (<= 4294967296 aux_mod_v_main_~x~0_53_31)))} is UNKNOWN [2022-04-07 17:41:52,302 WARN L290 TraceCheckUtils]: 12: Hoare triple {3481#(forall ((aux_mod_v_main_~x~0_53_31 Int)) (or (and (or (not (< 0 (mod main_~y~0 4294967296))) (and (or (forall ((aux_div_v_main_~x~0_53_31 Int)) (or (not (< (+ aux_mod_v_main_~x~0_53_31 (* aux_div_v_main_~x~0_53_31 4294967296)) main_~x~0)) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_53_31 v_it_6 (* aux_div_v_main_~x~0_53_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))))) (< 0 (mod (+ aux_mod_v_main_~x~0_53_31 main_~y~0 (* main_~x~0 4294967295)) 4294967296))) (forall ((aux_div_v_main_~x~0_53_31 Int) (aux_mod_v_main_~y~0_42_31 Int) (aux_div_v_main_~y~0_42_31 Int)) (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ v_it_6 (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31 1) main_~y~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_42_31) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_53_31 v_it_6 main_~y~0 (* aux_div_v_main_~x~0_53_31 4294967296) 1) (+ main_~x~0 (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (not (< 0 (mod (+ aux_mod_v_main_~y~0_42_31 (* v_it_6 4294967295)) 4294967296))))) (<= aux_mod_v_main_~y~0_42_31 0) (<= main_~y~0 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (<= (+ main_~x~0 (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31) (+ aux_mod_v_main_~x~0_53_31 main_~y~0 (* aux_div_v_main_~x~0_53_31 4294967296))))))) (or (forall ((aux_div_v_main_~x~0_53_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_53_31 (* aux_div_v_main_~x~0_53_31 4294967296))))) (< 0 (mod main_~y~0 4294967296)))) (<= aux_mod_v_main_~x~0_53_31 0) (<= 4294967296 aux_mod_v_main_~x~0_53_31)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {3481#(forall ((aux_mod_v_main_~x~0_53_31 Int)) (or (and (or (not (< 0 (mod main_~y~0 4294967296))) (and (or (forall ((aux_div_v_main_~x~0_53_31 Int)) (or (not (< (+ aux_mod_v_main_~x~0_53_31 (* aux_div_v_main_~x~0_53_31 4294967296)) main_~x~0)) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_53_31 v_it_6 (* aux_div_v_main_~x~0_53_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))))) (< 0 (mod (+ aux_mod_v_main_~x~0_53_31 main_~y~0 (* main_~x~0 4294967295)) 4294967296))) (forall ((aux_div_v_main_~x~0_53_31 Int) (aux_mod_v_main_~y~0_42_31 Int) (aux_div_v_main_~y~0_42_31 Int)) (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ v_it_6 (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31 1) main_~y~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_42_31) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_53_31 v_it_6 main_~y~0 (* aux_div_v_main_~x~0_53_31 4294967296) 1) (+ main_~x~0 (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (not (< 0 (mod (+ aux_mod_v_main_~y~0_42_31 (* v_it_6 4294967295)) 4294967296))))) (<= aux_mod_v_main_~y~0_42_31 0) (<= main_~y~0 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (<= (+ main_~x~0 (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31) (+ aux_mod_v_main_~x~0_53_31 main_~y~0 (* aux_div_v_main_~x~0_53_31 4294967296))))))) (or (forall ((aux_div_v_main_~x~0_53_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_53_31 (* aux_div_v_main_~x~0_53_31 4294967296))))) (< 0 (mod main_~y~0 4294967296)))) (<= aux_mod_v_main_~x~0_53_31 0) (<= 4294967296 aux_mod_v_main_~x~0_53_31)))} is UNKNOWN [2022-04-07 17:41:54,356 WARN L290 TraceCheckUtils]: 11: Hoare triple {3481#(forall ((aux_mod_v_main_~x~0_53_31 Int)) (or (and (or (not (< 0 (mod main_~y~0 4294967296))) (and (or (forall ((aux_div_v_main_~x~0_53_31 Int)) (or (not (< (+ aux_mod_v_main_~x~0_53_31 (* aux_div_v_main_~x~0_53_31 4294967296)) main_~x~0)) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_53_31 v_it_6 (* aux_div_v_main_~x~0_53_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))))) (< 0 (mod (+ aux_mod_v_main_~x~0_53_31 main_~y~0 (* main_~x~0 4294967295)) 4294967296))) (forall ((aux_div_v_main_~x~0_53_31 Int) (aux_mod_v_main_~y~0_42_31 Int) (aux_div_v_main_~y~0_42_31 Int)) (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ v_it_6 (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31 1) main_~y~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_42_31) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_53_31 v_it_6 main_~y~0 (* aux_div_v_main_~x~0_53_31 4294967296) 1) (+ main_~x~0 (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (not (< 0 (mod (+ aux_mod_v_main_~y~0_42_31 (* v_it_6 4294967295)) 4294967296))))) (<= aux_mod_v_main_~y~0_42_31 0) (<= main_~y~0 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (<= (+ main_~x~0 (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31) (+ aux_mod_v_main_~x~0_53_31 main_~y~0 (* aux_div_v_main_~x~0_53_31 4294967296))))))) (or (forall ((aux_div_v_main_~x~0_53_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_53_31 (* aux_div_v_main_~x~0_53_31 4294967296))))) (< 0 (mod main_~y~0 4294967296)))) (<= aux_mod_v_main_~x~0_53_31 0) (<= 4294967296 aux_mod_v_main_~x~0_53_31)))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {3481#(forall ((aux_mod_v_main_~x~0_53_31 Int)) (or (and (or (not (< 0 (mod main_~y~0 4294967296))) (and (or (forall ((aux_div_v_main_~x~0_53_31 Int)) (or (not (< (+ aux_mod_v_main_~x~0_53_31 (* aux_div_v_main_~x~0_53_31 4294967296)) main_~x~0)) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_53_31 v_it_6 (* aux_div_v_main_~x~0_53_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))))) (< 0 (mod (+ aux_mod_v_main_~x~0_53_31 main_~y~0 (* main_~x~0 4294967295)) 4294967296))) (forall ((aux_div_v_main_~x~0_53_31 Int) (aux_mod_v_main_~y~0_42_31 Int) (aux_div_v_main_~y~0_42_31 Int)) (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ v_it_6 (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31 1) main_~y~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_42_31) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_53_31 v_it_6 main_~y~0 (* aux_div_v_main_~x~0_53_31 4294967296) 1) (+ main_~x~0 (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (not (< 0 (mod (+ aux_mod_v_main_~y~0_42_31 (* v_it_6 4294967295)) 4294967296))))) (<= aux_mod_v_main_~y~0_42_31 0) (<= main_~y~0 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (<= (+ main_~x~0 (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31) (+ aux_mod_v_main_~x~0_53_31 main_~y~0 (* aux_div_v_main_~x~0_53_31 4294967296))))))) (or (forall ((aux_div_v_main_~x~0_53_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_53_31 (* aux_div_v_main_~x~0_53_31 4294967296))))) (< 0 (mod main_~y~0 4294967296)))) (<= aux_mod_v_main_~x~0_53_31 0) (<= 4294967296 aux_mod_v_main_~x~0_53_31)))} is UNKNOWN [2022-04-07 17:41:54,369 INFO L290 TraceCheckUtils]: 10: Hoare triple {3395#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {3481#(forall ((aux_mod_v_main_~x~0_53_31 Int)) (or (and (or (not (< 0 (mod main_~y~0 4294967296))) (and (or (forall ((aux_div_v_main_~x~0_53_31 Int)) (or (not (< (+ aux_mod_v_main_~x~0_53_31 (* aux_div_v_main_~x~0_53_31 4294967296)) main_~x~0)) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_53_31 v_it_6 (* aux_div_v_main_~x~0_53_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))))) (< 0 (mod (+ aux_mod_v_main_~x~0_53_31 main_~y~0 (* main_~x~0 4294967295)) 4294967296))) (forall ((aux_div_v_main_~x~0_53_31 Int) (aux_mod_v_main_~y~0_42_31 Int) (aux_div_v_main_~y~0_42_31 Int)) (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ v_it_6 (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31 1) main_~y~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_42_31) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_53_31 v_it_6 main_~y~0 (* aux_div_v_main_~x~0_53_31 4294967296) 1) (+ main_~x~0 (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (not (< 0 (mod (+ aux_mod_v_main_~y~0_42_31 (* v_it_6 4294967295)) 4294967296))))) (<= aux_mod_v_main_~y~0_42_31 0) (<= main_~y~0 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (<= (+ main_~x~0 (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31) (+ aux_mod_v_main_~x~0_53_31 main_~y~0 (* aux_div_v_main_~x~0_53_31 4294967296))))))) (or (forall ((aux_div_v_main_~x~0_53_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_53_31 (* aux_div_v_main_~x~0_53_31 4294967296))))) (< 0 (mod main_~y~0 4294967296)))) (<= aux_mod_v_main_~x~0_53_31 0) (<= 4294967296 aux_mod_v_main_~x~0_53_31)))} is VALID [2022-04-07 17:41:54,370 INFO L290 TraceCheckUtils]: 9: Hoare triple {3395#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [112] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_5 4294967296))) (or (and (= v_main_~y~0_4 v_main_~y~0_5) (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= |v_main_#t~post9_3| |v_main_#t~post9_1|) (<= .cse0 0)) (and (= v_main_~y~0_4 (+ v_main_~y~0_5 v_main_~z~0_3 (* (- 1) v_main_~z~0_2))) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= (+ v_main_~z~0_3 v_it_3 1) v_main_~z~0_2)) (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_5 (* v_it_3 4294967295)) 4294967296)))) (< v_main_~z~0_3 v_main_~z~0_2)))) InVars {main_~y~0=v_main_~y~0_5, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {3395#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:41:54,370 INFO L290 TraceCheckUtils]: 8: Hoare triple {3395#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {3395#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:41:54,371 INFO L290 TraceCheckUtils]: 7: Hoare triple {3395#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {3395#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:41:54,371 INFO L290 TraceCheckUtils]: 6: Hoare triple {3388#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {3395#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:41:54,371 INFO L290 TraceCheckUtils]: 5: Hoare triple {3388#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {3388#true} is VALID [2022-04-07 17:41:54,371 INFO L272 TraceCheckUtils]: 4: Hoare triple {3388#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3388#true} is VALID [2022-04-07 17:41:54,371 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3388#true} {3388#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3388#true} is VALID [2022-04-07 17:41:54,371 INFO L290 TraceCheckUtils]: 2: Hoare triple {3388#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3388#true} is VALID [2022-04-07 17:41:54,372 INFO L290 TraceCheckUtils]: 1: Hoare triple {3388#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3388#true} is VALID [2022-04-07 17:41:54,372 INFO L272 TraceCheckUtils]: 0: Hoare triple {3388#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3388#true} is VALID [2022-04-07 17:41:54,372 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 2 not checked. [2022-04-07 17:41:54,372 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1767127502] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-07 17:41:54,372 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-07 17:41:54,372 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 6, 7] total 13 [2022-04-07 17:41:54,372 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [696612006] [2022-04-07 17:41:54,372 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-07 17:41:54,373 INFO L78 Accepts]: Start accepts. Automaton has has 13 states, 13 states have (on average 2.6153846153846154) internal successors, (34), 10 states have internal predecessors, (34), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 20 [2022-04-07 17:41:54,373 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 17:41:54,373 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 13 states, 13 states have (on average 2.6153846153846154) internal successors, (34), 10 states have internal predecessors, (34), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:42:02,576 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 40 edges. 36 inductive. 0 not inductive. 4 times theorem prover too weak to decide inductivity. [2022-04-07 17:42:02,577 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 13 states [2022-04-07 17:42:02,577 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 17:42:02,577 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2022-04-07 17:42:02,577 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=102, Unknown=3, NotChecked=20, Total=156 [2022-04-07 17:42:02,577 INFO L87 Difference]: Start difference. First operand 46 states and 74 transitions. Second operand has 13 states, 13 states have (on average 2.6153846153846154) internal successors, (34), 10 states have internal predecessors, (34), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:42:17,539 WARN L232 SmtUtils]: Spent 12.60s on a formula simplification. DAG size of input: 78 DAG size of output: 75 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-07 17:42:17,826 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:42:17,826 INFO L93 Difference]: Finished difference Result 71 states and 112 transitions. [2022-04-07 17:42:17,826 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-04-07 17:42:17,826 INFO L78 Accepts]: Start accepts. Automaton has has 13 states, 13 states have (on average 2.6153846153846154) internal successors, (34), 10 states have internal predecessors, (34), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 20 [2022-04-07 17:42:17,826 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 17:42:17,827 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13 states, 13 states have (on average 2.6153846153846154) internal successors, (34), 10 states have internal predecessors, (34), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:42:17,828 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 65 transitions. [2022-04-07 17:42:17,828 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13 states, 13 states have (on average 2.6153846153846154) internal successors, (34), 10 states have internal predecessors, (34), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:42:17,829 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 65 transitions. [2022-04-07 17:42:17,829 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 13 states and 65 transitions. [2022-04-07 17:42:17,942 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 65 edges. 65 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 17:42:17,943 INFO L225 Difference]: With dead ends: 71 [2022-04-07 17:42:17,943 INFO L226 Difference]: Without dead ends: 61 [2022-04-07 17:42:17,943 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 60 GetRequests, 35 SyntacticMatches, 7 SemanticMatches, 18 ConstructedPredicates, 1 IntricatePredicates, 1 DeprecatedPredicates, 68 ImplicationChecksByTransitivity, 19.1s TimeCoverageRelationStatistics Valid=80, Invalid=263, Unknown=3, NotChecked=34, Total=380 [2022-04-07 17:42:17,943 INFO L913 BasicCegarLoop]: 13 mSDtfsCounter, 38 mSDsluCounter, 52 mSDsCounter, 0 mSdLazyCounter, 84 mSolverCounterSat, 13 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 38 SdHoareTripleChecker+Valid, 65 SdHoareTripleChecker+Invalid, 140 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 13 IncrementalHoareTripleChecker+Valid, 84 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 43 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-04-07 17:42:17,944 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [38 Valid, 65 Invalid, 140 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [13 Valid, 84 Invalid, 0 Unknown, 43 Unchecked, 0.2s Time] [2022-04-07 17:42:17,944 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states. [2022-04-07 17:42:17,946 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 52. [2022-04-07 17:42:17,946 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 17:42:17,946 INFO L82 GeneralOperation]: Start isEquivalent. First operand 61 states. Second operand has 52 states, 47 states have (on average 1.6808510638297873) internal successors, (79), 47 states have internal predecessors, (79), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:42:17,946 INFO L74 IsIncluded]: Start isIncluded. First operand 61 states. Second operand has 52 states, 47 states have (on average 1.6808510638297873) internal successors, (79), 47 states have internal predecessors, (79), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:42:17,947 INFO L87 Difference]: Start difference. First operand 61 states. Second operand has 52 states, 47 states have (on average 1.6808510638297873) internal successors, (79), 47 states have internal predecessors, (79), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:42:17,948 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:42:17,948 INFO L93 Difference]: Finished difference Result 61 states and 96 transitions. [2022-04-07 17:42:17,948 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 96 transitions. [2022-04-07 17:42:17,948 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:42:17,948 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:42:17,948 INFO L74 IsIncluded]: Start isIncluded. First operand has 52 states, 47 states have (on average 1.6808510638297873) internal successors, (79), 47 states have internal predecessors, (79), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 61 states. [2022-04-07 17:42:17,948 INFO L87 Difference]: Start difference. First operand has 52 states, 47 states have (on average 1.6808510638297873) internal successors, (79), 47 states have internal predecessors, (79), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 61 states. [2022-04-07 17:42:17,949 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:42:17,950 INFO L93 Difference]: Finished difference Result 61 states and 96 transitions. [2022-04-07 17:42:17,950 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 96 transitions. [2022-04-07 17:42:17,950 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:42:17,950 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:42:17,950 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 17:42:17,950 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 17:42:17,950 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52 states, 47 states have (on average 1.6808510638297873) internal successors, (79), 47 states have internal predecessors, (79), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:42:17,951 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 83 transitions. [2022-04-07 17:42:17,951 INFO L78 Accepts]: Start accepts. Automaton has 52 states and 83 transitions. Word has length 20 [2022-04-07 17:42:17,951 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 17:42:17,951 INFO L478 AbstractCegarLoop]: Abstraction has 52 states and 83 transitions. [2022-04-07 17:42:17,951 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 13 states, 13 states have (on average 2.6153846153846154) internal successors, (34), 10 states have internal predecessors, (34), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:42:17,952 INFO L276 IsEmpty]: Start isEmpty. Operand 52 states and 83 transitions. [2022-04-07 17:42:17,952 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2022-04-07 17:42:17,952 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 17:42:17,952 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 17:42:17,973 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Ended with exit code 0 [2022-04-07 17:42:18,167 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable12 [2022-04-07 17:42:18,167 INFO L403 AbstractCegarLoop]: === Iteration 14 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 17:42:18,168 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 17:42:18,168 INFO L85 PathProgramCache]: Analyzing trace with hash 2118261262, now seen corresponding path program 1 times [2022-04-07 17:42:18,168 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 17:42:18,168 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1363716474] [2022-04-07 17:42:18,168 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:42:18,168 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 17:42:18,180 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.0))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-07 17:42:18,183 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.1))) (+ main_~z~0_9 .cse0 (* (- 4294967296) (div (+ main_~z~0_9 .cse0) 4294967296)))) 0)) [2022-04-07 17:42:18,183 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.2))) (+ main_~y~0_9 .cse0 (* (- 4294967296) (div (+ main_~y~0_9 .cse0) 4294967296)))) 0)) [2022-04-07 17:42:18,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:42:18,216 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.4))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-07 17:42:18,219 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.5))) (+ main_~z~0_9 .cse0 (* (- 4294967296) (div (+ main_~z~0_9 .cse0) 4294967296)))) 0)) [2022-04-07 17:42:18,223 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.6))) (+ main_~y~0_9 .cse0 (* (- 4294967296) (div (+ main_~y~0_9 .cse0) 4294967296)))) 0)) [2022-04-07 17:42:18,497 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 17:42:18,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:42:18,501 INFO L290 TraceCheckUtils]: 0: Hoare triple {3798#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3784#true} is VALID [2022-04-07 17:42:18,501 INFO L290 TraceCheckUtils]: 1: Hoare triple {3784#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3784#true} is VALID [2022-04-07 17:42:18,501 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {3784#true} {3784#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3784#true} is VALID [2022-04-07 17:42:18,502 INFO L272 TraceCheckUtils]: 0: Hoare triple {3784#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3798#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 17:42:18,502 INFO L290 TraceCheckUtils]: 1: Hoare triple {3798#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3784#true} is VALID [2022-04-07 17:42:18,502 INFO L290 TraceCheckUtils]: 2: Hoare triple {3784#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3784#true} is VALID [2022-04-07 17:42:18,502 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3784#true} {3784#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3784#true} is VALID [2022-04-07 17:42:18,502 INFO L272 TraceCheckUtils]: 4: Hoare triple {3784#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3784#true} is VALID [2022-04-07 17:42:18,503 INFO L290 TraceCheckUtils]: 5: Hoare triple {3784#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {3789#(= main_~y~0 0)} is VALID [2022-04-07 17:42:18,504 INFO L290 TraceCheckUtils]: 6: Hoare triple {3789#(= main_~y~0 0)} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {3790#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:42:18,504 INFO L290 TraceCheckUtils]: 7: Hoare triple {3790#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {3791#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:42:18,505 INFO L290 TraceCheckUtils]: 8: Hoare triple {3791#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {3791#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:42:18,506 INFO L290 TraceCheckUtils]: 9: Hoare triple {3791#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [112] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_5 4294967296))) (or (and (= v_main_~y~0_4 v_main_~y~0_5) (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= |v_main_#t~post9_3| |v_main_#t~post9_1|) (<= .cse0 0)) (and (= v_main_~y~0_4 (+ v_main_~y~0_5 v_main_~z~0_3 (* (- 1) v_main_~z~0_2))) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= (+ v_main_~z~0_3 v_it_3 1) v_main_~z~0_2)) (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_5 (* v_it_3 4294967295)) 4294967296)))) (< v_main_~z~0_3 v_main_~z~0_2)))) InVars {main_~y~0=v_main_~y~0_5, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {3792#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:42:18,507 INFO L290 TraceCheckUtils]: 10: Hoare triple {3792#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {3793#(and (= main_~z~0 0) (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:42:18,507 INFO L290 TraceCheckUtils]: 11: Hoare triple {3793#(and (= main_~z~0 0) (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {3793#(and (= main_~z~0 0) (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:42:18,509 INFO L290 TraceCheckUtils]: 12: Hoare triple {3793#(and (= main_~z~0 0) (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {3793#(and (= main_~z~0 0) (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:42:18,509 INFO L290 TraceCheckUtils]: 13: Hoare triple {3793#(and (= main_~z~0 0) (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {3794#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:42:18,511 INFO L290 TraceCheckUtils]: 14: Hoare triple {3794#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {3795#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:42:18,512 INFO L290 TraceCheckUtils]: 15: Hoare triple {3795#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {3795#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:42:18,513 INFO L272 TraceCheckUtils]: 16: Hoare triple {3795#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {3796#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-07 17:42:18,513 INFO L290 TraceCheckUtils]: 17: Hoare triple {3796#(not (= |__VERIFIER_assert_#in~cond| 0))} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3797#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-07 17:42:18,514 INFO L290 TraceCheckUtils]: 18: Hoare triple {3797#(not (= __VERIFIER_assert_~cond 0))} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {3785#false} is VALID [2022-04-07 17:42:18,514 INFO L290 TraceCheckUtils]: 19: Hoare triple {3785#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3785#false} is VALID [2022-04-07 17:42:18,514 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-07 17:42:18,514 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 17:42:18,514 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1363716474] [2022-04-07 17:42:18,514 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1363716474] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 17:42:18,514 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [149430010] [2022-04-07 17:42:18,514 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:42:18,514 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 17:42:18,515 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 17:42:18,517 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 17:42:18,525 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2022-04-07 17:42:18,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:42:18,561 INFO L263 TraceCheckSpWp]: Trace formula consists of 65 conjuncts, 13 conjunts are in the unsatisfiable core [2022-04-07 17:42:18,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:42:18,574 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 17:42:19,066 INFO L272 TraceCheckUtils]: 0: Hoare triple {3784#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3784#true} is VALID [2022-04-07 17:42:19,067 INFO L290 TraceCheckUtils]: 1: Hoare triple {3784#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3784#true} is VALID [2022-04-07 17:42:19,067 INFO L290 TraceCheckUtils]: 2: Hoare triple {3784#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3784#true} is VALID [2022-04-07 17:42:19,067 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3784#true} {3784#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3784#true} is VALID [2022-04-07 17:42:19,067 INFO L272 TraceCheckUtils]: 4: Hoare triple {3784#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3784#true} is VALID [2022-04-07 17:42:19,067 INFO L290 TraceCheckUtils]: 5: Hoare triple {3784#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {3789#(= main_~y~0 0)} is VALID [2022-04-07 17:42:19,068 INFO L290 TraceCheckUtils]: 6: Hoare triple {3789#(= main_~y~0 0)} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {3790#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:42:19,068 INFO L290 TraceCheckUtils]: 7: Hoare triple {3790#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {3791#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:42:19,069 INFO L290 TraceCheckUtils]: 8: Hoare triple {3791#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {3791#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:42:19,070 INFO L290 TraceCheckUtils]: 9: Hoare triple {3791#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [112] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_5 4294967296))) (or (and (= v_main_~y~0_4 v_main_~y~0_5) (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= |v_main_#t~post9_3| |v_main_#t~post9_1|) (<= .cse0 0)) (and (= v_main_~y~0_4 (+ v_main_~y~0_5 v_main_~z~0_3 (* (- 1) v_main_~z~0_2))) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= (+ v_main_~z~0_3 v_it_3 1) v_main_~z~0_2)) (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_5 (* v_it_3 4294967295)) 4294967296)))) (< v_main_~z~0_3 v_main_~z~0_2)))) InVars {main_~y~0=v_main_~y~0_5, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {3791#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:42:19,070 INFO L290 TraceCheckUtils]: 10: Hoare triple {3791#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {3791#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:42:19,070 INFO L290 TraceCheckUtils]: 11: Hoare triple {3791#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {3791#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:42:19,071 INFO L290 TraceCheckUtils]: 12: Hoare triple {3791#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {3790#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:42:19,072 INFO L290 TraceCheckUtils]: 13: Hoare triple {3790#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {3790#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:42:19,073 INFO L290 TraceCheckUtils]: 14: Hoare triple {3790#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {3795#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:42:19,073 INFO L290 TraceCheckUtils]: 15: Hoare triple {3795#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {3795#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:42:19,074 INFO L272 TraceCheckUtils]: 16: Hoare triple {3795#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {3850#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 17:42:19,074 INFO L290 TraceCheckUtils]: 17: Hoare triple {3850#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3854#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 17:42:19,075 INFO L290 TraceCheckUtils]: 18: Hoare triple {3854#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {3785#false} is VALID [2022-04-07 17:42:19,075 INFO L290 TraceCheckUtils]: 19: Hoare triple {3785#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3785#false} is VALID [2022-04-07 17:42:19,075 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-07 17:42:19,075 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-07 17:43:35,577 INFO L290 TraceCheckUtils]: 19: Hoare triple {3785#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3785#false} is VALID [2022-04-07 17:43:35,578 INFO L290 TraceCheckUtils]: 18: Hoare triple {3854#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {3785#false} is VALID [2022-04-07 17:43:35,578 INFO L290 TraceCheckUtils]: 17: Hoare triple {3850#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3854#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 17:43:35,580 INFO L272 TraceCheckUtils]: 16: Hoare triple {3795#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {3850#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 17:43:35,580 INFO L290 TraceCheckUtils]: 15: Hoare triple {3795#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {3795#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:43:37,593 WARN L290 TraceCheckUtils]: 14: Hoare triple {3876#(forall ((aux_mod_v_main_~x~0_57_31 Int)) (or (and (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~x~0_57_31 Int)) (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_57_31 v_it_6 (* aux_div_v_main_~x~0_57_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (not (< (+ aux_mod_v_main_~x~0_57_31 (* aux_div_v_main_~x~0_57_31 4294967296)) main_~x~0))))) (or (forall ((aux_div_v_main_~x~0_57_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_57_31 (* aux_div_v_main_~x~0_57_31 4294967296))))) (< 0 (mod main_~y~0 4294967296)))) (<= aux_mod_v_main_~x~0_57_31 0) (<= 4294967296 aux_mod_v_main_~x~0_57_31)))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {3795#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is UNKNOWN [2022-04-07 17:43:39,627 WARN L290 TraceCheckUtils]: 13: Hoare triple {3876#(forall ((aux_mod_v_main_~x~0_57_31 Int)) (or (and (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~x~0_57_31 Int)) (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_57_31 v_it_6 (* aux_div_v_main_~x~0_57_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (not (< (+ aux_mod_v_main_~x~0_57_31 (* aux_div_v_main_~x~0_57_31 4294967296)) main_~x~0))))) (or (forall ((aux_div_v_main_~x~0_57_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_57_31 (* aux_div_v_main_~x~0_57_31 4294967296))))) (< 0 (mod main_~y~0 4294967296)))) (<= aux_mod_v_main_~x~0_57_31 0) (<= 4294967296 aux_mod_v_main_~x~0_57_31)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {3876#(forall ((aux_mod_v_main_~x~0_57_31 Int)) (or (and (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~x~0_57_31 Int)) (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_57_31 v_it_6 (* aux_div_v_main_~x~0_57_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (not (< (+ aux_mod_v_main_~x~0_57_31 (* aux_div_v_main_~x~0_57_31 4294967296)) main_~x~0))))) (or (forall ((aux_div_v_main_~x~0_57_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_57_31 (* aux_div_v_main_~x~0_57_31 4294967296))))) (< 0 (mod main_~y~0 4294967296)))) (<= aux_mod_v_main_~x~0_57_31 0) (<= 4294967296 aux_mod_v_main_~x~0_57_31)))} is UNKNOWN [2022-04-07 17:43:41,635 WARN L290 TraceCheckUtils]: 12: Hoare triple {3883#(forall ((aux_mod_v_main_~x~0_57_31 Int) (v_main_~x~0_58 Int)) (or (and (or (not (< 0 (mod main_~z~0 4294967296))) (not (< main_~x~0 v_main_~x~0_58)) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) v_main_~x~0_58) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5)))) (or (< 0 (mod main_~z~0 4294967296)) (not (= v_main_~x~0_58 main_~x~0)))) (and (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~x~0_57_31 Int)) (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_57_31 v_it_6 (* aux_div_v_main_~x~0_57_31 4294967296) 1) v_main_~x~0_58) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (not (< (+ aux_mod_v_main_~x~0_57_31 (* aux_div_v_main_~x~0_57_31 4294967296)) v_main_~x~0_58))))) (or (forall ((aux_div_v_main_~x~0_57_31 Int)) (not (= v_main_~x~0_58 (+ aux_mod_v_main_~x~0_57_31 (* aux_div_v_main_~x~0_57_31 4294967296))))) (< 0 (mod main_~y~0 4294967296)))) (<= aux_mod_v_main_~x~0_57_31 0) (<= 4294967296 aux_mod_v_main_~x~0_57_31)))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {3876#(forall ((aux_mod_v_main_~x~0_57_31 Int)) (or (and (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~x~0_57_31 Int)) (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_57_31 v_it_6 (* aux_div_v_main_~x~0_57_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (not (< (+ aux_mod_v_main_~x~0_57_31 (* aux_div_v_main_~x~0_57_31 4294967296)) main_~x~0))))) (or (forall ((aux_div_v_main_~x~0_57_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_57_31 (* aux_div_v_main_~x~0_57_31 4294967296))))) (< 0 (mod main_~y~0 4294967296)))) (<= aux_mod_v_main_~x~0_57_31 0) (<= 4294967296 aux_mod_v_main_~x~0_57_31)))} is UNKNOWN [2022-04-07 17:43:43,643 WARN L290 TraceCheckUtils]: 11: Hoare triple {3883#(forall ((aux_mod_v_main_~x~0_57_31 Int) (v_main_~x~0_58 Int)) (or (and (or (not (< 0 (mod main_~z~0 4294967296))) (not (< main_~x~0 v_main_~x~0_58)) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) v_main_~x~0_58) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5)))) (or (< 0 (mod main_~z~0 4294967296)) (not (= v_main_~x~0_58 main_~x~0)))) (and (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~x~0_57_31 Int)) (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_57_31 v_it_6 (* aux_div_v_main_~x~0_57_31 4294967296) 1) v_main_~x~0_58) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (not (< (+ aux_mod_v_main_~x~0_57_31 (* aux_div_v_main_~x~0_57_31 4294967296)) v_main_~x~0_58))))) (or (forall ((aux_div_v_main_~x~0_57_31 Int)) (not (= v_main_~x~0_58 (+ aux_mod_v_main_~x~0_57_31 (* aux_div_v_main_~x~0_57_31 4294967296))))) (< 0 (mod main_~y~0 4294967296)))) (<= aux_mod_v_main_~x~0_57_31 0) (<= 4294967296 aux_mod_v_main_~x~0_57_31)))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {3883#(forall ((aux_mod_v_main_~x~0_57_31 Int) (v_main_~x~0_58 Int)) (or (and (or (not (< 0 (mod main_~z~0 4294967296))) (not (< main_~x~0 v_main_~x~0_58)) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) v_main_~x~0_58) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5)))) (or (< 0 (mod main_~z~0 4294967296)) (not (= v_main_~x~0_58 main_~x~0)))) (and (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~x~0_57_31 Int)) (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_57_31 v_it_6 (* aux_div_v_main_~x~0_57_31 4294967296) 1) v_main_~x~0_58) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (not (< (+ aux_mod_v_main_~x~0_57_31 (* aux_div_v_main_~x~0_57_31 4294967296)) v_main_~x~0_58))))) (or (forall ((aux_div_v_main_~x~0_57_31 Int)) (not (= v_main_~x~0_58 (+ aux_mod_v_main_~x~0_57_31 (* aux_div_v_main_~x~0_57_31 4294967296))))) (< 0 (mod main_~y~0 4294967296)))) (<= aux_mod_v_main_~x~0_57_31 0) (<= 4294967296 aux_mod_v_main_~x~0_57_31)))} is UNKNOWN [2022-04-07 17:43:43,928 INFO L290 TraceCheckUtils]: 10: Hoare triple {3890#(or (forall ((aux_div_v_main_~x~0_57_31 Int) (v_main_~x~0_58 Int)) (or (and (or (not (< 0 (mod main_~z~0 4294967296))) (not (< main_~x~0 v_main_~x~0_58)) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) v_main_~x~0_58) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5)))) (or (< 0 (mod main_~z~0 4294967296)) (not (= v_main_~x~0_58 main_~x~0)))) (<= (+ 4294967296 (* aux_div_v_main_~x~0_57_31 4294967296)) v_main_~x~0_58) (<= v_main_~x~0_58 (* aux_div_v_main_~x~0_57_31 4294967296)))) (< 0 (mod main_~y~0 4294967296)))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {3883#(forall ((aux_mod_v_main_~x~0_57_31 Int) (v_main_~x~0_58 Int)) (or (and (or (not (< 0 (mod main_~z~0 4294967296))) (not (< main_~x~0 v_main_~x~0_58)) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) v_main_~x~0_58) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5)))) (or (< 0 (mod main_~z~0 4294967296)) (not (= v_main_~x~0_58 main_~x~0)))) (and (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~x~0_57_31 Int)) (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_57_31 v_it_6 (* aux_div_v_main_~x~0_57_31 4294967296) 1) v_main_~x~0_58) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (not (< (+ aux_mod_v_main_~x~0_57_31 (* aux_div_v_main_~x~0_57_31 4294967296)) v_main_~x~0_58))))) (or (forall ((aux_div_v_main_~x~0_57_31 Int)) (not (= v_main_~x~0_58 (+ aux_mod_v_main_~x~0_57_31 (* aux_div_v_main_~x~0_57_31 4294967296))))) (< 0 (mod main_~y~0 4294967296)))) (<= aux_mod_v_main_~x~0_57_31 0) (<= 4294967296 aux_mod_v_main_~x~0_57_31)))} is VALID [2022-04-07 17:43:45,949 WARN L290 TraceCheckUtils]: 9: Hoare triple {3894#(forall ((aux_mod_v_main_~y~0_47_31 Int) (aux_div_v_main_~x~0_57_31 Int) (v_main_~x~0_58 Int)) (or (and (or (and (or (not (< 0 (mod main_~y~0 4294967296))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) v_main_~x~0_58) (not (< 0 (mod (+ main_~z~0 main_~y~0 (* v_it_5 4294967295) (* 4294967295 aux_mod_v_main_~y~0_47_31)) 4294967296))) (<= 1 v_it_5))) (forall ((aux_div_v_main_~y~0_47_31 Int) (aux_div_v_main_~z~0_49_31 Int)) (or (<= (+ main_~z~0 main_~y~0) (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 (* 4294967296 aux_div_v_main_~z~0_49_31))) (not (< (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31) main_~y~0)) (exists ((v_it_3 Int)) (and (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))) (<= (+ v_it_3 (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 1) main_~y~0))) (<= (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 4294967296 (* 4294967296 aux_div_v_main_~z~0_49_31)) (+ main_~z~0 main_~y~0))))) (or (forall ((aux_div_v_main_~y~0_47_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31)))) (<= (div (- main_~z~0) (- 4294967296)) (+ (div (+ main_~z~0 (- 4294967296)) 4294967296) 1)) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) v_main_~x~0_58) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (< 0 (mod main_~y~0 4294967296)))) (not (< main_~x~0 v_main_~x~0_58))) (or (and (or (< (div (+ (- 1) (* (- 1) main_~z~0)) (- 4294967296)) (+ 2 (div (+ (- 1) main_~z~0) 4294967296))) (forall ((aux_div_v_main_~y~0_47_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31)))) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~y~0_47_31 Int) (aux_div_v_main_~z~0_49_31 Int)) (or (< (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 (* 4294967296 aux_div_v_main_~z~0_49_31)) (+ main_~z~0 main_~y~0)) (not (< (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31) main_~y~0)) (exists ((v_it_3 Int)) (and (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))) (<= (+ v_it_3 (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 1) main_~y~0))) (< (+ main_~z~0 main_~y~0) (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 (* 4294967296 aux_div_v_main_~z~0_49_31))))))) (not (= v_main_~x~0_58 main_~x~0)))) (<= (+ 4294967296 (* aux_div_v_main_~x~0_57_31 4294967296)) v_main_~x~0_58) (<= v_main_~x~0_58 (* aux_div_v_main_~x~0_57_31 4294967296)) (< aux_mod_v_main_~y~0_47_31 0) (< 0 aux_mod_v_main_~y~0_47_31)))} [112] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_5 4294967296))) (or (and (= v_main_~y~0_4 v_main_~y~0_5) (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= |v_main_#t~post9_3| |v_main_#t~post9_1|) (<= .cse0 0)) (and (= v_main_~y~0_4 (+ v_main_~y~0_5 v_main_~z~0_3 (* (- 1) v_main_~z~0_2))) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= (+ v_main_~z~0_3 v_it_3 1) v_main_~z~0_2)) (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_5 (* v_it_3 4294967295)) 4294967296)))) (< v_main_~z~0_3 v_main_~z~0_2)))) InVars {main_~y~0=v_main_~y~0_5, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {3890#(or (forall ((aux_div_v_main_~x~0_57_31 Int) (v_main_~x~0_58 Int)) (or (and (or (not (< 0 (mod main_~z~0 4294967296))) (not (< main_~x~0 v_main_~x~0_58)) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) v_main_~x~0_58) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5)))) (or (< 0 (mod main_~z~0 4294967296)) (not (= v_main_~x~0_58 main_~x~0)))) (<= (+ 4294967296 (* aux_div_v_main_~x~0_57_31 4294967296)) v_main_~x~0_58) (<= v_main_~x~0_58 (* aux_div_v_main_~x~0_57_31 4294967296)))) (< 0 (mod main_~y~0 4294967296)))} is UNKNOWN [2022-04-07 17:43:47,959 WARN L290 TraceCheckUtils]: 8: Hoare triple {3898#(or (forall ((aux_mod_v_main_~y~0_47_31 Int) (aux_div_v_main_~x~0_57_31 Int) (v_main_~x~0_58 Int)) (or (and (or (not (< 0 (mod main_~y~0 4294967296))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) v_main_~x~0_58) (not (< 0 (mod (+ main_~z~0 main_~y~0 (* v_it_5 4294967295) (* 4294967295 aux_mod_v_main_~y~0_47_31)) 4294967296))) (<= 1 v_it_5))) (forall ((aux_div_v_main_~y~0_47_31 Int) (aux_div_v_main_~z~0_49_31 Int)) (or (<= (+ main_~z~0 main_~y~0) (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 (* 4294967296 aux_div_v_main_~z~0_49_31))) (not (< (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31) main_~y~0)) (exists ((v_it_3 Int)) (and (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))) (<= (+ v_it_3 (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 1) main_~y~0))) (<= (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 4294967296 (* 4294967296 aux_div_v_main_~z~0_49_31)) (+ main_~z~0 main_~y~0)))) (not (< main_~x~0 v_main_~x~0_58))) (or (forall ((aux_div_v_main_~y~0_47_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31)))) (not (= v_main_~x~0_58 main_~x~0)) (< 0 (mod main_~y~0 4294967296)))) (<= (+ 4294967296 (* aux_div_v_main_~x~0_57_31 4294967296)) v_main_~x~0_58) (<= v_main_~x~0_58 (* aux_div_v_main_~x~0_57_31 4294967296)) (< aux_mod_v_main_~y~0_47_31 0) (< 0 aux_mod_v_main_~y~0_47_31))) (< 0 (mod main_~z~0 4294967296)))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {3894#(forall ((aux_mod_v_main_~y~0_47_31 Int) (aux_div_v_main_~x~0_57_31 Int) (v_main_~x~0_58 Int)) (or (and (or (and (or (not (< 0 (mod main_~y~0 4294967296))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) v_main_~x~0_58) (not (< 0 (mod (+ main_~z~0 main_~y~0 (* v_it_5 4294967295) (* 4294967295 aux_mod_v_main_~y~0_47_31)) 4294967296))) (<= 1 v_it_5))) (forall ((aux_div_v_main_~y~0_47_31 Int) (aux_div_v_main_~z~0_49_31 Int)) (or (<= (+ main_~z~0 main_~y~0) (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 (* 4294967296 aux_div_v_main_~z~0_49_31))) (not (< (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31) main_~y~0)) (exists ((v_it_3 Int)) (and (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))) (<= (+ v_it_3 (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 1) main_~y~0))) (<= (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 4294967296 (* 4294967296 aux_div_v_main_~z~0_49_31)) (+ main_~z~0 main_~y~0))))) (or (forall ((aux_div_v_main_~y~0_47_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31)))) (<= (div (- main_~z~0) (- 4294967296)) (+ (div (+ main_~z~0 (- 4294967296)) 4294967296) 1)) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) v_main_~x~0_58) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (< 0 (mod main_~y~0 4294967296)))) (not (< main_~x~0 v_main_~x~0_58))) (or (and (or (< (div (+ (- 1) (* (- 1) main_~z~0)) (- 4294967296)) (+ 2 (div (+ (- 1) main_~z~0) 4294967296))) (forall ((aux_div_v_main_~y~0_47_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31)))) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~y~0_47_31 Int) (aux_div_v_main_~z~0_49_31 Int)) (or (< (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 (* 4294967296 aux_div_v_main_~z~0_49_31)) (+ main_~z~0 main_~y~0)) (not (< (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31) main_~y~0)) (exists ((v_it_3 Int)) (and (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))) (<= (+ v_it_3 (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 1) main_~y~0))) (< (+ main_~z~0 main_~y~0) (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 (* 4294967296 aux_div_v_main_~z~0_49_31))))))) (not (= v_main_~x~0_58 main_~x~0)))) (<= (+ 4294967296 (* aux_div_v_main_~x~0_57_31 4294967296)) v_main_~x~0_58) (<= v_main_~x~0_58 (* aux_div_v_main_~x~0_57_31 4294967296)) (< aux_mod_v_main_~y~0_47_31 0) (< 0 aux_mod_v_main_~y~0_47_31)))} is UNKNOWN [2022-04-07 17:43:47,963 INFO L290 TraceCheckUtils]: 7: Hoare triple {3902#(or (<= (div (* (- 1) main_~x~0) (- 4294967296)) (+ (div (+ main_~x~0 (- 4294967296)) 4294967296) 1)) (< 0 (mod main_~y~0 4294967296)))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {3898#(or (forall ((aux_mod_v_main_~y~0_47_31 Int) (aux_div_v_main_~x~0_57_31 Int) (v_main_~x~0_58 Int)) (or (and (or (not (< 0 (mod main_~y~0 4294967296))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) v_main_~x~0_58) (not (< 0 (mod (+ main_~z~0 main_~y~0 (* v_it_5 4294967295) (* 4294967295 aux_mod_v_main_~y~0_47_31)) 4294967296))) (<= 1 v_it_5))) (forall ((aux_div_v_main_~y~0_47_31 Int) (aux_div_v_main_~z~0_49_31 Int)) (or (<= (+ main_~z~0 main_~y~0) (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 (* 4294967296 aux_div_v_main_~z~0_49_31))) (not (< (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31) main_~y~0)) (exists ((v_it_3 Int)) (and (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))) (<= (+ v_it_3 (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 1) main_~y~0))) (<= (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 4294967296 (* 4294967296 aux_div_v_main_~z~0_49_31)) (+ main_~z~0 main_~y~0)))) (not (< main_~x~0 v_main_~x~0_58))) (or (forall ((aux_div_v_main_~y~0_47_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31)))) (not (= v_main_~x~0_58 main_~x~0)) (< 0 (mod main_~y~0 4294967296)))) (<= (+ 4294967296 (* aux_div_v_main_~x~0_57_31 4294967296)) v_main_~x~0_58) (<= v_main_~x~0_58 (* aux_div_v_main_~x~0_57_31 4294967296)) (< aux_mod_v_main_~y~0_47_31 0) (< 0 aux_mod_v_main_~y~0_47_31))) (< 0 (mod main_~z~0 4294967296)))} is VALID [2022-04-07 17:43:47,964 INFO L290 TraceCheckUtils]: 6: Hoare triple {3784#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {3902#(or (<= (div (* (- 1) main_~x~0) (- 4294967296)) (+ (div (+ main_~x~0 (- 4294967296)) 4294967296) 1)) (< 0 (mod main_~y~0 4294967296)))} is VALID [2022-04-07 17:43:47,964 INFO L290 TraceCheckUtils]: 5: Hoare triple {3784#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {3784#true} is VALID [2022-04-07 17:43:47,964 INFO L272 TraceCheckUtils]: 4: Hoare triple {3784#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3784#true} is VALID [2022-04-07 17:43:47,964 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3784#true} {3784#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3784#true} is VALID [2022-04-07 17:43:47,964 INFO L290 TraceCheckUtils]: 2: Hoare triple {3784#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3784#true} is VALID [2022-04-07 17:43:47,965 INFO L290 TraceCheckUtils]: 1: Hoare triple {3784#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3784#true} is VALID [2022-04-07 17:43:47,965 INFO L272 TraceCheckUtils]: 0: Hoare triple {3784#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3784#true} is VALID [2022-04-07 17:43:47,965 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 17:43:47,965 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [149430010] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-07 17:43:47,965 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-07 17:43:47,965 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 8, 11] total 20 [2022-04-07 17:43:47,965 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [402935891] [2022-04-07 17:43:47,966 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-07 17:43:47,966 INFO L78 Accepts]: Start accepts. Automaton has has 20 states, 20 states have (on average 1.75) internal successors, (35), 17 states have internal predecessors, (35), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 20 [2022-04-07 17:43:47,966 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 17:43:47,966 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 20 states, 20 states have (on average 1.75) internal successors, (35), 17 states have internal predecessors, (35), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:43:58,990 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 41 edges. 36 inductive. 0 not inductive. 5 times theorem prover too weak to decide inductivity. [2022-04-07 17:43:58,990 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 20 states [2022-04-07 17:43:58,990 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 17:43:58,991 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2022-04-07 17:43:58,991 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=76, Invalid=284, Unknown=20, NotChecked=0, Total=380 [2022-04-07 17:43:58,991 INFO L87 Difference]: Start difference. First operand 52 states and 83 transitions. Second operand has 20 states, 20 states have (on average 1.75) internal successors, (35), 17 states have internal predecessors, (35), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:44:40,783 WARN L232 SmtUtils]: Spent 5.03s on a formula simplification that was a NOOP. DAG size: 143 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-07 17:45:55,092 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:45:55,092 INFO L93 Difference]: Finished difference Result 75 states and 115 transitions. [2022-04-07 17:45:55,092 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2022-04-07 17:45:55,092 INFO L78 Accepts]: Start accepts. Automaton has has 20 states, 20 states have (on average 1.75) internal successors, (35), 17 states have internal predecessors, (35), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 20 [2022-04-07 17:45:55,093 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 17:45:55,093 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20 states, 20 states have (on average 1.75) internal successors, (35), 17 states have internal predecessors, (35), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:45:55,097 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 69 transitions. [2022-04-07 17:45:55,097 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20 states, 20 states have (on average 1.75) internal successors, (35), 17 states have internal predecessors, (35), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:45:55,098 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 69 transitions. [2022-04-07 17:45:55,098 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 20 states and 69 transitions. [2022-04-07 17:46:15,118 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 69 edges. 60 inductive. 0 not inductive. 9 times theorem prover too weak to decide inductivity. [2022-04-07 17:46:15,119 INFO L225 Difference]: With dead ends: 75 [2022-04-07 17:46:15,119 INFO L226 Difference]: Without dead ends: 71 [2022-04-07 17:46:15,119 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 68 GetRequests, 31 SyntacticMatches, 6 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 246 ImplicationChecksByTransitivity, 151.4s TimeCoverageRelationStatistics Valid=195, Invalid=805, Unknown=56, NotChecked=0, Total=1056 [2022-04-07 17:46:15,120 INFO L913 BasicCegarLoop]: 14 mSDtfsCounter, 61 mSDsluCounter, 75 mSDsCounter, 0 mSdLazyCounter, 114 mSolverCounterSat, 19 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 61 SdHoareTripleChecker+Valid, 89 SdHoareTripleChecker+Invalid, 248 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 19 IncrementalHoareTripleChecker+Valid, 114 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 115 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-04-07 17:46:15,120 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [61 Valid, 89 Invalid, 248 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [19 Valid, 114 Invalid, 0 Unknown, 115 Unchecked, 0.3s Time] [2022-04-07 17:46:15,120 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71 states. [2022-04-07 17:46:15,122 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71 to 50. [2022-04-07 17:46:15,122 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 17:46:15,122 INFO L82 GeneralOperation]: Start isEquivalent. First operand 71 states. Second operand has 50 states, 45 states have (on average 1.6888888888888889) internal successors, (76), 45 states have internal predecessors, (76), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:46:15,123 INFO L74 IsIncluded]: Start isIncluded. First operand 71 states. Second operand has 50 states, 45 states have (on average 1.6888888888888889) internal successors, (76), 45 states have internal predecessors, (76), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:46:15,123 INFO L87 Difference]: Start difference. First operand 71 states. Second operand has 50 states, 45 states have (on average 1.6888888888888889) internal successors, (76), 45 states have internal predecessors, (76), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:46:15,124 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:46:15,124 INFO L93 Difference]: Finished difference Result 71 states and 110 transitions. [2022-04-07 17:46:15,124 INFO L276 IsEmpty]: Start isEmpty. Operand 71 states and 110 transitions. [2022-04-07 17:46:15,124 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:46:15,124 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:46:15,125 INFO L74 IsIncluded]: Start isIncluded. First operand has 50 states, 45 states have (on average 1.6888888888888889) internal successors, (76), 45 states have internal predecessors, (76), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 71 states. [2022-04-07 17:46:15,125 INFO L87 Difference]: Start difference. First operand has 50 states, 45 states have (on average 1.6888888888888889) internal successors, (76), 45 states have internal predecessors, (76), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 71 states. [2022-04-07 17:46:15,126 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:46:15,126 INFO L93 Difference]: Finished difference Result 71 states and 110 transitions. [2022-04-07 17:46:15,126 INFO L276 IsEmpty]: Start isEmpty. Operand 71 states and 110 transitions. [2022-04-07 17:46:15,126 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:46:15,126 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:46:15,126 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 17:46:15,126 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 17:46:15,127 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50 states, 45 states have (on average 1.6888888888888889) internal successors, (76), 45 states have internal predecessors, (76), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:46:15,127 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 80 transitions. [2022-04-07 17:46:15,127 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 80 transitions. Word has length 20 [2022-04-07 17:46:15,127 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 17:46:15,128 INFO L478 AbstractCegarLoop]: Abstraction has 50 states and 80 transitions. [2022-04-07 17:46:15,128 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 20 states, 20 states have (on average 1.75) internal successors, (35), 17 states have internal predecessors, (35), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:46:15,128 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 80 transitions. [2022-04-07 17:46:15,128 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2022-04-07 17:46:15,128 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 17:46:15,128 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 17:46:15,144 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Ended with exit code 0 [2022-04-07 17:46:15,328 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable13 [2022-04-07 17:46:15,329 INFO L403 AbstractCegarLoop]: === Iteration 15 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 17:46:15,329 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 17:46:15,329 INFO L85 PathProgramCache]: Analyzing trace with hash 1929500051, now seen corresponding path program 1 times [2022-04-07 17:46:15,329 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 17:46:15,329 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [501183306] [2022-04-07 17:46:15,329 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:46:15,329 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 17:46:15,339 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.0))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-07 17:46:15,340 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.1))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-07 17:46:15,341 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.2))) (+ main_~y~0_11 .cse0 (* (- 4294967296) (div (+ main_~y~0_11 .cse0) 4294967296)))) 0)) [2022-04-07 17:46:15,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:46:15,356 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.6))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-07 17:46:15,358 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.7))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-07 17:46:15,371 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.8))) (+ main_~y~0_11 .cse0 (* (- 4294967296) (div (+ main_~y~0_11 .cse0) 4294967296)))) 0)) [2022-04-07 17:46:15,649 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 17:46:15,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:46:15,653 INFO L290 TraceCheckUtils]: 0: Hoare triple {4231#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4221#true} is VALID [2022-04-07 17:46:15,653 INFO L290 TraceCheckUtils]: 1: Hoare triple {4221#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4221#true} is VALID [2022-04-07 17:46:15,653 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {4221#true} {4221#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4221#true} is VALID [2022-04-07 17:46:15,653 INFO L272 TraceCheckUtils]: 0: Hoare triple {4221#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4231#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 17:46:15,653 INFO L290 TraceCheckUtils]: 1: Hoare triple {4231#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4221#true} is VALID [2022-04-07 17:46:15,653 INFO L290 TraceCheckUtils]: 2: Hoare triple {4221#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4221#true} is VALID [2022-04-07 17:46:15,653 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {4221#true} {4221#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4221#true} is VALID [2022-04-07 17:46:15,654 INFO L272 TraceCheckUtils]: 4: Hoare triple {4221#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4221#true} is VALID [2022-04-07 17:46:15,654 INFO L290 TraceCheckUtils]: 5: Hoare triple {4221#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {4226#(= main_~y~0 0)} is VALID [2022-04-07 17:46:15,655 INFO L290 TraceCheckUtils]: 6: Hoare triple {4226#(= main_~y~0 0)} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {4227#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:46:15,655 INFO L290 TraceCheckUtils]: 7: Hoare triple {4227#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {4227#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:46:15,655 INFO L290 TraceCheckUtils]: 8: Hoare triple {4227#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {4227#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:46:15,656 INFO L290 TraceCheckUtils]: 9: Hoare triple {4227#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [112] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_5 4294967296))) (or (and (= v_main_~y~0_4 v_main_~y~0_5) (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= |v_main_#t~post9_3| |v_main_#t~post9_1|) (<= .cse0 0)) (and (= v_main_~y~0_4 (+ v_main_~y~0_5 v_main_~z~0_3 (* (- 1) v_main_~z~0_2))) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= (+ v_main_~z~0_3 v_it_3 1) v_main_~z~0_2)) (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_5 (* v_it_3 4294967295)) 4294967296)))) (< v_main_~z~0_3 v_main_~z~0_2)))) InVars {main_~y~0=v_main_~y~0_5, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {4227#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:46:15,656 INFO L290 TraceCheckUtils]: 10: Hoare triple {4227#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {4227#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:46:15,658 INFO L290 TraceCheckUtils]: 11: Hoare triple {4227#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [115] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~x~0_10 v_main_~x~0_9)) (and (= (+ v_main_~x~0_10 v_main_~y~0_11 (* (- 1) v_main_~x~0_9)) v_main_~y~0_10) (< 0 .cse0) (forall ((v_it_4 Int)) (or (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_10) 4294967296)) (not (<= (+ v_main_~x~0_9 v_it_4 1) v_main_~x~0_10)) (not (<= 1 v_it_4)))) (< v_main_~x~0_9 v_main_~x~0_10)))) InVars {main_~y~0=v_main_~y~0_11, main_~x~0=v_main_~x~0_10, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~x~0=v_main_~x~0_9, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {4227#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:46:15,658 INFO L290 TraceCheckUtils]: 12: Hoare triple {4227#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {4227#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:46:15,659 INFO L290 TraceCheckUtils]: 13: Hoare triple {4227#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {4227#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:46:15,660 INFO L290 TraceCheckUtils]: 14: Hoare triple {4227#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {4227#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:46:15,660 INFO L290 TraceCheckUtils]: 15: Hoare triple {4227#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {4228#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:46:15,661 INFO L272 TraceCheckUtils]: 16: Hoare triple {4228#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {4229#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-07 17:46:15,661 INFO L290 TraceCheckUtils]: 17: Hoare triple {4229#(not (= |__VERIFIER_assert_#in~cond| 0))} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {4230#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-07 17:46:15,661 INFO L290 TraceCheckUtils]: 18: Hoare triple {4230#(not (= __VERIFIER_assert_~cond 0))} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {4222#false} is VALID [2022-04-07 17:46:15,662 INFO L290 TraceCheckUtils]: 19: Hoare triple {4222#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4222#false} is VALID [2022-04-07 17:46:15,662 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2022-04-07 17:46:15,662 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 17:46:15,662 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [501183306] [2022-04-07 17:46:15,662 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [501183306] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-07 17:46:15,662 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-07 17:46:15,662 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2022-04-07 17:46:15,662 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1365640102] [2022-04-07 17:46:15,662 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-07 17:46:15,663 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 7 states have (on average 2.2857142857142856) internal successors, (16), 6 states have internal predecessors, (16), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 20 [2022-04-07 17:46:15,663 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 17:46:15,663 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 8 states, 7 states have (on average 2.2857142857142856) internal successors, (16), 6 states have internal predecessors, (16), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:46:15,685 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 20 edges. 20 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 17:46:15,685 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-04-07 17:46:15,685 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 17:46:15,685 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-04-07 17:46:15,685 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2022-04-07 17:46:15,686 INFO L87 Difference]: Start difference. First operand 50 states and 80 transitions. Second operand has 8 states, 7 states have (on average 2.2857142857142856) internal successors, (16), 6 states have internal predecessors, (16), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:46:16,262 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:46:16,262 INFO L93 Difference]: Finished difference Result 62 states and 96 transitions. [2022-04-07 17:46:16,262 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-04-07 17:46:16,263 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 7 states have (on average 2.2857142857142856) internal successors, (16), 6 states have internal predecessors, (16), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 20 [2022-04-07 17:46:16,263 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 17:46:16,263 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 7 states have (on average 2.2857142857142856) internal successors, (16), 6 states have internal predecessors, (16), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:46:16,264 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 56 transitions. [2022-04-07 17:46:16,265 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 7 states have (on average 2.2857142857142856) internal successors, (16), 6 states have internal predecessors, (16), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:46:16,265 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 56 transitions. [2022-04-07 17:46:16,265 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 9 states and 56 transitions. [2022-04-07 17:46:16,327 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 56 edges. 56 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 17:46:16,328 INFO L225 Difference]: With dead ends: 62 [2022-04-07 17:46:16,328 INFO L226 Difference]: Without dead ends: 57 [2022-04-07 17:46:16,328 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 6 SyntacticMatches, 1 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=41, Invalid=115, Unknown=0, NotChecked=0, Total=156 [2022-04-07 17:46:16,328 INFO L913 BasicCegarLoop]: 15 mSDtfsCounter, 37 mSDsluCounter, 29 mSDsCounter, 0 mSdLazyCounter, 51 mSolverCounterSat, 14 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 37 SdHoareTripleChecker+Valid, 44 SdHoareTripleChecker+Invalid, 75 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 14 IncrementalHoareTripleChecker+Valid, 51 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 10 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-07 17:46:16,329 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [37 Valid, 44 Invalid, 75 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [14 Valid, 51 Invalid, 0 Unknown, 10 Unchecked, 0.1s Time] [2022-04-07 17:46:16,329 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57 states. [2022-04-07 17:46:16,330 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57 to 51. [2022-04-07 17:46:16,330 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 17:46:16,331 INFO L82 GeneralOperation]: Start isEquivalent. First operand 57 states. Second operand has 51 states, 46 states have (on average 1.6956521739130435) internal successors, (78), 46 states have internal predecessors, (78), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:46:16,331 INFO L74 IsIncluded]: Start isIncluded. First operand 57 states. Second operand has 51 states, 46 states have (on average 1.6956521739130435) internal successors, (78), 46 states have internal predecessors, (78), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:46:16,333 INFO L87 Difference]: Start difference. First operand 57 states. Second operand has 51 states, 46 states have (on average 1.6956521739130435) internal successors, (78), 46 states have internal predecessors, (78), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:46:16,334 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:46:16,334 INFO L93 Difference]: Finished difference Result 57 states and 90 transitions. [2022-04-07 17:46:16,334 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 90 transitions. [2022-04-07 17:46:16,334 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:46:16,335 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:46:16,335 INFO L74 IsIncluded]: Start isIncluded. First operand has 51 states, 46 states have (on average 1.6956521739130435) internal successors, (78), 46 states have internal predecessors, (78), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 57 states. [2022-04-07 17:46:16,335 INFO L87 Difference]: Start difference. First operand has 51 states, 46 states have (on average 1.6956521739130435) internal successors, (78), 46 states have internal predecessors, (78), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 57 states. [2022-04-07 17:46:16,336 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 17:46:16,336 INFO L93 Difference]: Finished difference Result 57 states and 90 transitions. [2022-04-07 17:46:16,336 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 90 transitions. [2022-04-07 17:46:16,336 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 17:46:16,336 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 17:46:16,336 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 17:46:16,336 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 17:46:16,337 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51 states, 46 states have (on average 1.6956521739130435) internal successors, (78), 46 states have internal predecessors, (78), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:46:16,337 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 82 transitions. [2022-04-07 17:46:16,337 INFO L78 Accepts]: Start accepts. Automaton has 51 states and 82 transitions. Word has length 20 [2022-04-07 17:46:16,337 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 17:46:16,338 INFO L478 AbstractCegarLoop]: Abstraction has 51 states and 82 transitions. [2022-04-07 17:46:16,338 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 7 states have (on average 2.2857142857142856) internal successors, (16), 6 states have internal predecessors, (16), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 17:46:16,338 INFO L276 IsEmpty]: Start isEmpty. Operand 51 states and 82 transitions. [2022-04-07 17:46:16,338 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2022-04-07 17:46:16,338 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 17:46:16,338 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 17:46:16,338 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable14 [2022-04-07 17:46:16,338 INFO L403 AbstractCegarLoop]: === Iteration 16 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 17:46:16,339 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 17:46:16,339 INFO L85 PathProgramCache]: Analyzing trace with hash -1592480168, now seen corresponding path program 1 times [2022-04-07 17:46:16,339 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 17:46:16,339 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [136552231] [2022-04-07 17:46:16,339 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:46:16,339 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 17:46:16,353 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.0))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-07 17:46:16,354 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.1))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-07 17:46:16,355 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.2))) (+ main_~z~0_9 .cse0 (* (- 4294967296) (div (+ main_~z~0_9 .cse0) 4294967296)))) 0)) [2022-04-07 17:46:16,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:46:16,368 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.6))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-07 17:46:16,370 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.7))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-07 17:46:16,372 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.8))) (+ main_~z~0_9 .cse0 (* (- 4294967296) (div (+ main_~z~0_9 .cse0) 4294967296)))) 0)) [2022-04-07 17:46:16,720 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 17:46:16,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:46:16,740 INFO L290 TraceCheckUtils]: 0: Hoare triple {4484#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4472#true} is VALID [2022-04-07 17:46:16,740 INFO L290 TraceCheckUtils]: 1: Hoare triple {4472#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4472#true} is VALID [2022-04-07 17:46:16,740 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {4472#true} {4472#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4472#true} is VALID [2022-04-07 17:46:16,741 INFO L272 TraceCheckUtils]: 0: Hoare triple {4472#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4484#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 17:46:16,741 INFO L290 TraceCheckUtils]: 1: Hoare triple {4484#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4472#true} is VALID [2022-04-07 17:46:16,741 INFO L290 TraceCheckUtils]: 2: Hoare triple {4472#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4472#true} is VALID [2022-04-07 17:46:16,741 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {4472#true} {4472#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4472#true} is VALID [2022-04-07 17:46:16,741 INFO L272 TraceCheckUtils]: 4: Hoare triple {4472#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4472#true} is VALID [2022-04-07 17:46:16,742 INFO L290 TraceCheckUtils]: 5: Hoare triple {4472#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {4477#(= main_~y~0 0)} is VALID [2022-04-07 17:46:16,743 INFO L290 TraceCheckUtils]: 6: Hoare triple {4477#(= main_~y~0 0)} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {4478#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:46:16,743 INFO L290 TraceCheckUtils]: 7: Hoare triple {4478#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {4479#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:46:16,744 INFO L290 TraceCheckUtils]: 8: Hoare triple {4479#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {4479#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:46:16,745 INFO L290 TraceCheckUtils]: 9: Hoare triple {4479#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [112] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_5 4294967296))) (or (and (= v_main_~y~0_4 v_main_~y~0_5) (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= |v_main_#t~post9_3| |v_main_#t~post9_1|) (<= .cse0 0)) (and (= v_main_~y~0_4 (+ v_main_~y~0_5 v_main_~z~0_3 (* (- 1) v_main_~z~0_2))) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= (+ v_main_~z~0_3 v_it_3 1) v_main_~z~0_2)) (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_5 (* v_it_3 4294967295)) 4294967296)))) (< v_main_~z~0_3 v_main_~z~0_2)))) InVars {main_~y~0=v_main_~y~0_5, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {4480#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:46:16,745 INFO L290 TraceCheckUtils]: 10: Hoare triple {4480#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {4480#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:46:16,747 INFO L290 TraceCheckUtils]: 11: Hoare triple {4480#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [115] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~x~0_10 v_main_~x~0_9)) (and (= (+ v_main_~x~0_10 v_main_~y~0_11 (* (- 1) v_main_~x~0_9)) v_main_~y~0_10) (< 0 .cse0) (forall ((v_it_4 Int)) (or (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_10) 4294967296)) (not (<= (+ v_main_~x~0_9 v_it_4 1) v_main_~x~0_10)) (not (<= 1 v_it_4)))) (< v_main_~x~0_9 v_main_~x~0_10)))) InVars {main_~y~0=v_main_~y~0_11, main_~x~0=v_main_~x~0_10, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~x~0=v_main_~x~0_9, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {4480#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:46:16,747 INFO L290 TraceCheckUtils]: 12: Hoare triple {4480#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {4480#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:46:16,749 INFO L290 TraceCheckUtils]: 13: Hoare triple {4480#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {4481#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:46:16,749 INFO L290 TraceCheckUtils]: 14: Hoare triple {4481#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {4481#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:46:16,750 INFO L290 TraceCheckUtils]: 15: Hoare triple {4481#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {4481#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:46:16,751 INFO L272 TraceCheckUtils]: 16: Hoare triple {4481#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {4482#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-07 17:46:16,751 INFO L290 TraceCheckUtils]: 17: Hoare triple {4482#(not (= |__VERIFIER_assert_#in~cond| 0))} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {4483#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-07 17:46:16,751 INFO L290 TraceCheckUtils]: 18: Hoare triple {4483#(not (= __VERIFIER_assert_~cond 0))} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {4473#false} is VALID [2022-04-07 17:46:16,752 INFO L290 TraceCheckUtils]: 19: Hoare triple {4473#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4473#false} is VALID [2022-04-07 17:46:16,752 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-07 17:46:16,752 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 17:46:16,752 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [136552231] [2022-04-07 17:46:16,752 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [136552231] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 17:46:16,752 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1869743758] [2022-04-07 17:46:16,752 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 17:46:16,752 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 17:46:16,752 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 17:46:16,753 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 17:46:16,754 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2022-04-07 17:46:16,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:46:16,791 INFO L263 TraceCheckSpWp]: Trace formula consists of 65 conjuncts, 12 conjunts are in the unsatisfiable core [2022-04-07 17:46:16,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 17:46:16,810 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 17:46:17,741 INFO L272 TraceCheckUtils]: 0: Hoare triple {4472#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4472#true} is VALID [2022-04-07 17:46:17,741 INFO L290 TraceCheckUtils]: 1: Hoare triple {4472#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4472#true} is VALID [2022-04-07 17:46:17,741 INFO L290 TraceCheckUtils]: 2: Hoare triple {4472#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4472#true} is VALID [2022-04-07 17:46:17,741 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {4472#true} {4472#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4472#true} is VALID [2022-04-07 17:46:17,741 INFO L272 TraceCheckUtils]: 4: Hoare triple {4472#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4472#true} is VALID [2022-04-07 17:46:17,742 INFO L290 TraceCheckUtils]: 5: Hoare triple {4472#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {4477#(= main_~y~0 0)} is VALID [2022-04-07 17:46:17,742 INFO L290 TraceCheckUtils]: 6: Hoare triple {4477#(= main_~y~0 0)} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {4478#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:46:17,743 INFO L290 TraceCheckUtils]: 7: Hoare triple {4478#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {4479#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:46:17,743 INFO L290 TraceCheckUtils]: 8: Hoare triple {4479#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {4479#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:46:17,744 INFO L290 TraceCheckUtils]: 9: Hoare triple {4479#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [112] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_5 4294967296))) (or (and (= v_main_~y~0_4 v_main_~y~0_5) (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= |v_main_#t~post9_3| |v_main_#t~post9_1|) (<= .cse0 0)) (and (= v_main_~y~0_4 (+ v_main_~y~0_5 v_main_~z~0_3 (* (- 1) v_main_~z~0_2))) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= (+ v_main_~z~0_3 v_it_3 1) v_main_~z~0_2)) (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_5 (* v_it_3 4294967295)) 4294967296)))) (< v_main_~z~0_3 v_main_~z~0_2)))) InVars {main_~y~0=v_main_~y~0_5, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {4479#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:46:17,744 INFO L290 TraceCheckUtils]: 10: Hoare triple {4479#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {4479#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-07 17:46:17,746 INFO L290 TraceCheckUtils]: 11: Hoare triple {4479#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [115] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~x~0_10 v_main_~x~0_9)) (and (= (+ v_main_~x~0_10 v_main_~y~0_11 (* (- 1) v_main_~x~0_9)) v_main_~y~0_10) (< 0 .cse0) (forall ((v_it_4 Int)) (or (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_10) 4294967296)) (not (<= (+ v_main_~x~0_9 v_it_4 1) v_main_~x~0_10)) (not (<= 1 v_it_4)))) (< v_main_~x~0_9 v_main_~x~0_10)))) InVars {main_~y~0=v_main_~y~0_11, main_~x~0=v_main_~x~0_10, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~x~0=v_main_~x~0_9, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {4480#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:46:17,746 INFO L290 TraceCheckUtils]: 12: Hoare triple {4480#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {4480#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-07 17:46:17,747 INFO L290 TraceCheckUtils]: 13: Hoare triple {4480#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {4481#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:46:17,748 INFO L290 TraceCheckUtils]: 14: Hoare triple {4481#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {4481#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:46:17,748 INFO L290 TraceCheckUtils]: 15: Hoare triple {4481#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {4481#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-07 17:46:17,749 INFO L272 TraceCheckUtils]: 16: Hoare triple {4481#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {4536#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 17:46:17,749 INFO L290 TraceCheckUtils]: 17: Hoare triple {4536#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {4540#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 17:46:17,750 INFO L290 TraceCheckUtils]: 18: Hoare triple {4540#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {4473#false} is VALID [2022-04-07 17:46:17,750 INFO L290 TraceCheckUtils]: 19: Hoare triple {4473#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4473#false} is VALID [2022-04-07 17:46:17,750 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-07 17:46:17,750 INFO L328 TraceCheckSpWp]: Computing backward predicates...