/usr/bin/java -ea -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data --core.log.level.for.class de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=WARN -tc ../../../trunk/examples/toolchains/AutomizerCTransformed.xml -s ../../../trunk/examples/settings/automizer/LoopAccelerationJordanC.epf -i ../../../trunk/examples/svcomp/loops/insertion_sort-1.c -------------------------------------------------------------------------------- This is Ultimate 0.2.2-dev-34549b5 [2022-04-07 16:41:48,502 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-04-07 16:41:48,504 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-04-07 16:41:48,549 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... 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[2022-04-07 16:41:48,554 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-04-07 16:41:48,555 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-04-07 16:41:48,555 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-04-07 16:41:48,556 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-04-07 16:41:48,556 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-04-07 16:41:48,557 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-04-07 16:41:48,558 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-04-07 16:41:48,559 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-04-07 16:41:48,560 INFO L181 SettingsManager]: Resetting HornVerifier preferences to default values [2022-04-07 16:41:48,561 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-04-07 16:41:48,561 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-04-07 16:41:48,562 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-04-07 16:41:48,563 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-04-07 16:41:48,564 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2022-04-07 16:41:48,568 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-04-07 16:41:48,569 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-04-07 16:41:48,573 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-04-07 16:41:48,574 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/automizer/LoopAccelerationJordanC.epf [2022-04-07 16:41:48,579 INFO L113 SettingsManager]: Loading preferences was successful [2022-04-07 16:41:48,579 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-04-07 16:41:48,580 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-04-07 16:41:48,580 INFO L138 SettingsManager]: * sizeof long=4 [2022-04-07 16:41:48,580 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-04-07 16:41:48,581 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-04-07 16:41:48,581 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-04-07 16:41:48,581 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-04-07 16:41:48,581 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-04-07 16:41:48,581 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-04-07 16:41:48,581 INFO L138 SettingsManager]: * sizeof long double=12 [2022-04-07 16:41:48,581 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-04-07 16:41:48,581 INFO L138 SettingsManager]: * Use constant arrays=true [2022-04-07 16:41:48,582 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-04-07 16:41:48,582 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-04-07 16:41:48,582 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-04-07 16:41:48,582 INFO L138 SettingsManager]: * To the following directory=./dump/ [2022-04-07 16:41:48,582 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-04-07 16:41:48,582 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-04-07 16:41:48,582 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-04-07 16:41:48,582 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-04-07 16:41:48,599 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-04-07 16:41:48,600 INFO L138 SettingsManager]: * TransformationType=LOOP_ACCELERATION_JORDAN WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.core: Log level for class -> de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=WARN; [2022-04-07 16:41:48,762 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-04-07 16:41:48,783 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-04-07 16:41:48,785 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-04-07 16:41:48,785 INFO L271 PluginConnector]: Initializing CDTParser... [2022-04-07 16:41:48,789 INFO L275 PluginConnector]: CDTParser initialized [2022-04-07 16:41:48,790 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loops/insertion_sort-1.c [2022-04-07 16:41:48,850 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/b7321708a/54437cfaf7104fec9b23b0fbb179b93e/FLAGebf267ff7 [2022-04-07 16:41:49,173 INFO L306 CDTParser]: Found 1 translation units. [2022-04-07 16:41:49,173 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/loops/insertion_sort-1.c [2022-04-07 16:41:49,180 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/b7321708a/54437cfaf7104fec9b23b0fbb179b93e/FLAGebf267ff7 [2022-04-07 16:41:49,584 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/b7321708a/54437cfaf7104fec9b23b0fbb179b93e [2022-04-07 16:41:49,586 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-04-07 16:41:49,587 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2022-04-07 16:41:49,588 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-04-07 16:41:49,588 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-04-07 16:41:49,591 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-04-07 16:41:49,591 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.04 04:41:49" (1/1) ... [2022-04-07 16:41:49,592 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@9f32ef9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 04:41:49, skipping insertion in model container [2022-04-07 16:41:49,592 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.04 04:41:49" (1/1) ... [2022-04-07 16:41:49,596 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-04-07 16:41:49,604 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-04-07 16:41:49,786 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loops/insertion_sort-1.c[328,341] [2022-04-07 16:41:49,800 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-04-07 16:41:49,818 INFO L203 MainTranslator]: Completed pre-run [2022-04-07 16:41:49,826 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loops/insertion_sort-1.c[328,341] [2022-04-07 16:41:49,848 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-04-07 16:41:49,859 INFO L208 MainTranslator]: Completed translation [2022-04-07 16:41:49,859 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 04:41:49 WrapperNode [2022-04-07 16:41:49,859 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-04-07 16:41:49,860 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-04-07 16:41:49,860 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-04-07 16:41:49,860 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-04-07 16:41:49,882 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 04:41:49" (1/1) ... [2022-04-07 16:41:49,883 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 04:41:49" (1/1) ... [2022-04-07 16:41:49,901 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 04:41:49" (1/1) ... [2022-04-07 16:41:49,901 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 04:41:49" (1/1) ... [2022-04-07 16:41:49,927 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 04:41:49" (1/1) ... [2022-04-07 16:41:49,937 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 04:41:49" (1/1) ... [2022-04-07 16:41:49,943 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 04:41:49" (1/1) ... [2022-04-07 16:41:49,944 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-04-07 16:41:49,945 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-04-07 16:41:49,945 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-04-07 16:41:49,945 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-04-07 16:41:49,950 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 04:41:49" (1/1) ... [2022-04-07 16:41:49,968 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-04-07 16:41:49,989 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 16:41:50,006 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-04-07 16:41:50,009 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-04-07 16:41:50,062 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2022-04-07 16:41:50,062 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-04-07 16:41:50,066 INFO L138 BoogieDeclarations]: Found implementation of procedure reach_error [2022-04-07 16:41:50,066 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2022-04-07 16:41:50,066 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2022-04-07 16:41:50,066 INFO L130 BoogieDeclarations]: Found specification of procedure abort [2022-04-07 16:41:50,066 INFO L130 BoogieDeclarations]: Found specification of procedure __assert_fail [2022-04-07 16:41:50,067 INFO L130 BoogieDeclarations]: Found specification of procedure reach_error [2022-04-07 16:41:50,067 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-04-07 16:41:50,067 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2022-04-07 16:41:50,067 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_uint [2022-04-07 16:41:50,067 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2022-04-07 16:41:50,067 INFO L130 BoogieDeclarations]: Found specification of procedure main [2022-04-07 16:41:50,068 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-04-07 16:41:50,068 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-04-07 16:41:50,069 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-04-07 16:41:50,069 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-04-07 16:41:50,069 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2022-04-07 16:41:50,069 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-04-07 16:41:50,069 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-04-07 16:41:50,153 INFO L234 CfgBuilder]: Building ICFG [2022-04-07 16:41:50,154 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-04-07 16:41:50,426 INFO L275 CfgBuilder]: Performing block encoding [2022-04-07 16:41:50,431 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-04-07 16:41:50,431 INFO L299 CfgBuilder]: Removed 4 assume(true) statements. [2022-04-07 16:41:50,440 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.04 04:41:50 BoogieIcfgContainer [2022-04-07 16:41:50,440 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-04-07 16:41:50,440 INFO L113 PluginConnector]: ------------------------IcfgTransformer---------------------------- [2022-04-07 16:41:50,440 INFO L271 PluginConnector]: Initializing IcfgTransformer... [2022-04-07 16:41:50,441 INFO L275 PluginConnector]: IcfgTransformer initialized [2022-04-07 16:41:50,444 INFO L185 PluginConnector]: Executing the observer IcfgTransformationObserver from plugin IcfgTransformer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.04 04:41:50" (1/1) ... [2022-04-07 16:41:50,445 INFO L168 ansformationObserver]: Applying ICFG transformation LOOP_ACCELERATION_JORDAN [2022-04-07 16:41:50,495 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 07.04 04:41:50 BasicIcfg [2022-04-07 16:41:50,495 INFO L132 PluginConnector]: ------------------------ END IcfgTransformer---------------------------- [2022-04-07 16:41:50,496 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-04-07 16:41:50,496 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-04-07 16:41:50,502 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-04-07 16:41:50,502 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.04 04:41:49" (1/4) ... [2022-04-07 16:41:50,502 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@721e5aaa and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.04 04:41:50, skipping insertion in model container [2022-04-07 16:41:50,502 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 04:41:49" (2/4) ... [2022-04-07 16:41:50,503 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@721e5aaa and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.04 04:41:50, skipping insertion in model container [2022-04-07 16:41:50,503 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.04 04:41:50" (3/4) ... [2022-04-07 16:41:50,503 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@721e5aaa and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.04 04:41:50, skipping insertion in model container [2022-04-07 16:41:50,503 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 07.04 04:41:50" (4/4) ... [2022-04-07 16:41:50,504 INFO L111 eAbstractionObserver]: Analyzing ICFG insertion_sort-1.cJordan [2022-04-07 16:41:50,522 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:ForwardPredicates Determinization: PREDICATE_ABSTRACTION [2022-04-07 16:41:50,522 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-04-07 16:41:50,552 INFO L339 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-04-07 16:41:50,573 INFO L340 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=ForwardPredicates, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=false, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=All, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP [2022-04-07 16:41:50,574 INFO L341 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-04-07 16:41:50,586 INFO L276 IsEmpty]: Start isEmpty. Operand has 33 states, 25 states have (on average 1.48) internal successors, (37), 26 states have internal predecessors, (37), 3 states have call successors, (3), 3 states have call predecessors, (3), 3 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 16:41:50,590 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2022-04-07 16:41:50,591 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 16:41:50,591 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 16:41:50,591 INFO L403 AbstractCegarLoop]: === Iteration 1 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 16:41:50,594 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 16:41:50,595 INFO L85 PathProgramCache]: Analyzing trace with hash -1926103570, now seen corresponding path program 1 times [2022-04-07 16:41:50,602 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 16:41:50,602 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1615986877] [2022-04-07 16:41:50,602 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 16:41:50,603 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 16:41:50,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 16:41:50,786 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 16:41:50,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 16:41:50,813 INFO L290 TraceCheckUtils]: 0: Hoare triple {41#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {36#true} is VALID [2022-04-07 16:41:50,813 INFO L290 TraceCheckUtils]: 1: Hoare triple {36#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {36#true} is VALID [2022-04-07 16:41:50,814 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {36#true} {36#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {36#true} is VALID [2022-04-07 16:41:50,817 INFO L272 TraceCheckUtils]: 0: Hoare triple {36#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {41#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 16:41:50,818 INFO L290 TraceCheckUtils]: 1: Hoare triple {41#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {36#true} is VALID [2022-04-07 16:41:50,818 INFO L290 TraceCheckUtils]: 2: Hoare triple {36#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {36#true} is VALID [2022-04-07 16:41:50,818 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {36#true} {36#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {36#true} is VALID [2022-04-07 16:41:50,818 INFO L272 TraceCheckUtils]: 4: Hoare triple {36#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {36#true} is VALID [2022-04-07 16:41:50,819 INFO L290 TraceCheckUtils]: 5: Hoare triple {36#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (= (store |v_#length_2| |v_main_~#v~0.base_2| (* 4 (let ((.cse0 (mod v_main_~SIZE~0_2 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))))) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {36#true} is VALID [2022-04-07 16:41:50,820 INFO L290 TraceCheckUtils]: 6: Hoare triple {36#true} [103] L17-3-->L17-4: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {37#false} is VALID [2022-04-07 16:41:50,820 INFO L290 TraceCheckUtils]: 7: Hoare triple {37#false} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {37#false} is VALID [2022-04-07 16:41:50,820 INFO L290 TraceCheckUtils]: 8: Hoare triple {37#false} [108] L19-3-->L19-4: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {37#false} is VALID [2022-04-07 16:41:50,821 INFO L290 TraceCheckUtils]: 9: Hoare triple {37#false} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {37#false} is VALID [2022-04-07 16:41:50,821 INFO L290 TraceCheckUtils]: 10: Hoare triple {37#false} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {37#false} is VALID [2022-04-07 16:41:50,821 INFO L272 TraceCheckUtils]: 11: Hoare triple {37#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {37#false} is VALID [2022-04-07 16:41:50,821 INFO L290 TraceCheckUtils]: 12: Hoare triple {37#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {37#false} is VALID [2022-04-07 16:41:50,821 INFO L290 TraceCheckUtils]: 13: Hoare triple {37#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {37#false} is VALID [2022-04-07 16:41:50,822 INFO L290 TraceCheckUtils]: 14: Hoare triple {37#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {37#false} is VALID [2022-04-07 16:41:50,822 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 16:41:50,822 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 16:41:50,823 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1615986877] [2022-04-07 16:41:50,823 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1615986877] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-07 16:41:50,824 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-07 16:41:50,824 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-04-07 16:41:50,826 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [886427632] [2022-04-07 16:41:50,826 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-07 16:41:50,831 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 15 [2022-04-07 16:41:50,832 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 16:41:50,835 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:41:50,858 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 15 edges. 15 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 16:41:50,858 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-04-07 16:41:50,858 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 16:41:50,882 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-04-07 16:41:50,883 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-04-07 16:41:50,886 INFO L87 Difference]: Start difference. First operand has 33 states, 25 states have (on average 1.48) internal successors, (37), 26 states have internal predecessors, (37), 3 states have call successors, (3), 3 states have call predecessors, (3), 3 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:41:50,971 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 16:41:50,971 INFO L93 Difference]: Finished difference Result 33 states and 38 transitions. [2022-04-07 16:41:50,971 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-04-07 16:41:50,972 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 15 [2022-04-07 16:41:50,972 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 16:41:50,973 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:41:50,986 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 43 transitions. [2022-04-07 16:41:50,987 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:41:50,990 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 43 transitions. [2022-04-07 16:41:50,990 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 3 states and 43 transitions. [2022-04-07 16:41:51,039 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 43 edges. 43 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 16:41:51,046 INFO L225 Difference]: With dead ends: 33 [2022-04-07 16:41:51,046 INFO L226 Difference]: Without dead ends: 28 [2022-04-07 16:41:51,047 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-04-07 16:41:51,052 INFO L913 BasicCegarLoop]: 37 mSDtfsCounter, 29 mSDsluCounter, 3 mSDsCounter, 0 mSdLazyCounter, 3 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 30 SdHoareTripleChecker+Valid, 40 SdHoareTripleChecker+Invalid, 5 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 3 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-07 16:41:51,052 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [30 Valid, 40 Invalid, 5 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 3 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-07 16:41:51,066 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states. [2022-04-07 16:41:51,074 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 28. [2022-04-07 16:41:51,075 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 16:41:51,075 INFO L82 GeneralOperation]: Start isEquivalent. First operand 28 states. Second operand has 28 states, 22 states have (on average 1.2727272727272727) internal successors, (28), 22 states have internal predecessors, (28), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-07 16:41:51,076 INFO L74 IsIncluded]: Start isIncluded. First operand 28 states. Second operand has 28 states, 22 states have (on average 1.2727272727272727) internal successors, (28), 22 states have internal predecessors, (28), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-07 16:41:51,077 INFO L87 Difference]: Start difference. First operand 28 states. Second operand has 28 states, 22 states have (on average 1.2727272727272727) internal successors, (28), 22 states have internal predecessors, (28), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-07 16:41:51,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 16:41:51,083 INFO L93 Difference]: Finished difference Result 28 states and 33 transitions. [2022-04-07 16:41:51,083 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 33 transitions. [2022-04-07 16:41:51,083 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 16:41:51,084 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 16:41:51,084 INFO L74 IsIncluded]: Start isIncluded. First operand has 28 states, 22 states have (on average 1.2727272727272727) internal successors, (28), 22 states have internal predecessors, (28), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 28 states. [2022-04-07 16:41:51,084 INFO L87 Difference]: Start difference. First operand has 28 states, 22 states have (on average 1.2727272727272727) internal successors, (28), 22 states have internal predecessors, (28), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 28 states. [2022-04-07 16:41:51,086 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 16:41:51,086 INFO L93 Difference]: Finished difference Result 28 states and 33 transitions. [2022-04-07 16:41:51,086 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 33 transitions. [2022-04-07 16:41:51,087 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 16:41:51,087 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 16:41:51,087 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 16:41:51,087 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 16:41:51,087 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 22 states have (on average 1.2727272727272727) internal successors, (28), 22 states have internal predecessors, (28), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-07 16:41:51,088 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 33 transitions. [2022-04-07 16:41:51,089 INFO L78 Accepts]: Start accepts. Automaton has 28 states and 33 transitions. Word has length 15 [2022-04-07 16:41:51,089 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 16:41:51,089 INFO L478 AbstractCegarLoop]: Abstraction has 28 states and 33 transitions. [2022-04-07 16:41:51,090 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:41:51,090 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 33 transitions. [2022-04-07 16:41:51,090 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2022-04-07 16:41:51,090 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 16:41:51,090 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 16:41:51,091 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-04-07 16:41:51,091 INFO L403 AbstractCegarLoop]: === Iteration 2 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 16:41:51,093 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 16:41:51,094 INFO L85 PathProgramCache]: Analyzing trace with hash 1448912944, now seen corresponding path program 1 times [2022-04-07 16:41:51,094 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 16:41:51,094 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [546226591] [2022-04-07 16:41:51,094 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 16:41:51,094 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 16:41:51,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 16:41:51,275 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 16:41:51,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 16:41:51,298 INFO L290 TraceCheckUtils]: 0: Hoare triple {169#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {161#true} is VALID [2022-04-07 16:41:51,299 INFO L290 TraceCheckUtils]: 1: Hoare triple {161#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {161#true} is VALID [2022-04-07 16:41:51,299 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {161#true} {161#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {161#true} is VALID [2022-04-07 16:41:51,300 INFO L272 TraceCheckUtils]: 0: Hoare triple {161#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {169#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 16:41:51,300 INFO L290 TraceCheckUtils]: 1: Hoare triple {169#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {161#true} is VALID [2022-04-07 16:41:51,301 INFO L290 TraceCheckUtils]: 2: Hoare triple {161#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {161#true} is VALID [2022-04-07 16:41:51,301 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {161#true} {161#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {161#true} is VALID [2022-04-07 16:41:51,301 INFO L272 TraceCheckUtils]: 4: Hoare triple {161#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {161#true} is VALID [2022-04-07 16:41:51,301 INFO L290 TraceCheckUtils]: 5: Hoare triple {161#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (= (store |v_#length_2| |v_main_~#v~0.base_2| (* 4 (let ((.cse0 (mod v_main_~SIZE~0_2 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))))) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {166#(= main_~j~0 0)} is VALID [2022-04-07 16:41:51,302 INFO L290 TraceCheckUtils]: 6: Hoare triple {166#(= main_~j~0 0)} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {167#(<= main_~SIZE~0 (* (div main_~SIZE~0 4294967296) 4294967296))} is VALID [2022-04-07 16:41:51,303 INFO L290 TraceCheckUtils]: 7: Hoare triple {167#(<= main_~SIZE~0 (* (div main_~SIZE~0 4294967296) 4294967296))} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {167#(<= main_~SIZE~0 (* (div main_~SIZE~0 4294967296) 4294967296))} is VALID [2022-04-07 16:41:51,303 INFO L290 TraceCheckUtils]: 8: Hoare triple {167#(<= main_~SIZE~0 (* (div main_~SIZE~0 4294967296) 4294967296))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {167#(<= main_~SIZE~0 (* (div main_~SIZE~0 4294967296) 4294967296))} is VALID [2022-04-07 16:41:51,304 INFO L290 TraceCheckUtils]: 9: Hoare triple {167#(<= main_~SIZE~0 (* (div main_~SIZE~0 4294967296) 4294967296))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {168#(and (<= (+ main_~SIZE~0 (* (div main_~k~0 4294967296) 4294967296)) (* (div main_~SIZE~0 4294967296) 4294967296)) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-07 16:41:51,304 INFO L290 TraceCheckUtils]: 10: Hoare triple {168#(and (<= (+ main_~SIZE~0 (* (div main_~k~0 4294967296) 4294967296)) (* (div main_~SIZE~0 4294967296) 4294967296)) (= (+ (- 1) main_~k~0) 0))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {162#false} is VALID [2022-04-07 16:41:51,305 INFO L272 TraceCheckUtils]: 11: Hoare triple {162#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {162#false} is VALID [2022-04-07 16:41:51,305 INFO L290 TraceCheckUtils]: 12: Hoare triple {162#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {162#false} is VALID [2022-04-07 16:41:51,305 INFO L290 TraceCheckUtils]: 13: Hoare triple {162#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {162#false} is VALID [2022-04-07 16:41:51,306 INFO L290 TraceCheckUtils]: 14: Hoare triple {162#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {162#false} is VALID [2022-04-07 16:41:51,306 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 16:41:51,306 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 16:41:51,306 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [546226591] [2022-04-07 16:41:51,307 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [546226591] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-07 16:41:51,307 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-07 16:41:51,307 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2022-04-07 16:41:51,307 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [340937373] [2022-04-07 16:41:51,307 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-07 16:41:51,308 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 5 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 15 [2022-04-07 16:41:51,309 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 16:41:51,309 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 5 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:41:51,321 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 15 edges. 15 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 16:41:51,321 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-04-07 16:41:51,321 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 16:41:51,321 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-04-07 16:41:51,322 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2022-04-07 16:41:51,322 INFO L87 Difference]: Start difference. First operand 28 states and 33 transitions. Second operand has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 5 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:41:51,548 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 16:41:51,548 INFO L93 Difference]: Finished difference Result 34 states and 39 transitions. [2022-04-07 16:41:51,548 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-04-07 16:41:51,549 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 5 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 15 [2022-04-07 16:41:51,549 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 16:41:51,549 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 5 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:41:51,550 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 41 transitions. [2022-04-07 16:41:51,551 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 5 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:41:51,552 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 41 transitions. [2022-04-07 16:41:51,552 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 7 states and 41 transitions. [2022-04-07 16:41:51,592 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 41 edges. 41 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 16:41:51,594 INFO L225 Difference]: With dead ends: 34 [2022-04-07 16:41:51,594 INFO L226 Difference]: Without dead ends: 30 [2022-04-07 16:41:51,594 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=31, Invalid=59, Unknown=0, NotChecked=0, Total=90 [2022-04-07 16:41:51,595 INFO L913 BasicCegarLoop]: 28 mSDtfsCounter, 34 mSDsluCounter, 17 mSDsCounter, 0 mSdLazyCounter, 89 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 35 SdHoareTripleChecker+Valid, 45 SdHoareTripleChecker+Invalid, 93 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 89 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-07 16:41:51,595 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [35 Valid, 45 Invalid, 93 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 89 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-04-07 16:41:51,596 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30 states. [2022-04-07 16:41:51,598 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30 to 29. [2022-04-07 16:41:51,598 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 16:41:51,598 INFO L82 GeneralOperation]: Start isEquivalent. First operand 30 states. Second operand has 29 states, 23 states have (on average 1.2608695652173914) internal successors, (29), 23 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-07 16:41:51,598 INFO L74 IsIncluded]: Start isIncluded. First operand 30 states. Second operand has 29 states, 23 states have (on average 1.2608695652173914) internal successors, (29), 23 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-07 16:41:51,599 INFO L87 Difference]: Start difference. First operand 30 states. Second operand has 29 states, 23 states have (on average 1.2608695652173914) internal successors, (29), 23 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-07 16:41:51,600 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 16:41:51,600 INFO L93 Difference]: Finished difference Result 30 states and 35 transitions. [2022-04-07 16:41:51,600 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 35 transitions. [2022-04-07 16:41:51,601 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 16:41:51,601 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 16:41:51,601 INFO L74 IsIncluded]: Start isIncluded. First operand has 29 states, 23 states have (on average 1.2608695652173914) internal successors, (29), 23 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 30 states. [2022-04-07 16:41:51,601 INFO L87 Difference]: Start difference. First operand has 29 states, 23 states have (on average 1.2608695652173914) internal successors, (29), 23 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 30 states. [2022-04-07 16:41:51,602 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 16:41:51,603 INFO L93 Difference]: Finished difference Result 30 states and 35 transitions. [2022-04-07 16:41:51,603 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 35 transitions. [2022-04-07 16:41:51,603 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 16:41:51,603 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 16:41:51,603 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 16:41:51,603 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 16:41:51,603 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29 states, 23 states have (on average 1.2608695652173914) internal successors, (29), 23 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-07 16:41:51,604 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 34 transitions. [2022-04-07 16:41:51,605 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 34 transitions. Word has length 15 [2022-04-07 16:41:51,605 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 16:41:51,605 INFO L478 AbstractCegarLoop]: Abstraction has 29 states and 34 transitions. [2022-04-07 16:41:51,605 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 5 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:41:51,605 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 34 transitions. [2022-04-07 16:41:51,606 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2022-04-07 16:41:51,606 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 16:41:51,606 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 16:41:51,606 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-04-07 16:41:51,606 INFO L403 AbstractCegarLoop]: === Iteration 3 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 16:41:51,607 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 16:41:51,607 INFO L85 PathProgramCache]: Analyzing trace with hash 1246349198, now seen corresponding path program 1 times [2022-04-07 16:41:51,607 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 16:41:51,607 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [542501569] [2022-04-07 16:41:51,607 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 16:41:51,607 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 16:41:51,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 16:41:51,742 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 16:41:51,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 16:41:51,748 INFO L290 TraceCheckUtils]: 0: Hoare triple {313#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {303#true} is VALID [2022-04-07 16:41:51,748 INFO L290 TraceCheckUtils]: 1: Hoare triple {303#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {303#true} is VALID [2022-04-07 16:41:51,748 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {303#true} {303#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {303#true} is VALID [2022-04-07 16:41:51,749 INFO L272 TraceCheckUtils]: 0: Hoare triple {303#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {313#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 16:41:51,749 INFO L290 TraceCheckUtils]: 1: Hoare triple {313#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {303#true} is VALID [2022-04-07 16:41:51,749 INFO L290 TraceCheckUtils]: 2: Hoare triple {303#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {303#true} is VALID [2022-04-07 16:41:51,749 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {303#true} {303#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {303#true} is VALID [2022-04-07 16:41:51,749 INFO L272 TraceCheckUtils]: 4: Hoare triple {303#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {303#true} is VALID [2022-04-07 16:41:51,750 INFO L290 TraceCheckUtils]: 5: Hoare triple {303#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (= (store |v_#length_2| |v_main_~#v~0.base_2| (* 4 (let ((.cse0 (mod v_main_~SIZE~0_2 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))))) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {308#(= main_~j~0 0)} is VALID [2022-04-07 16:41:51,751 INFO L290 TraceCheckUtils]: 6: Hoare triple {308#(= main_~j~0 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {309#(and (<= (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1) (+ main_~SIZE~0 (* 4294967296 (div main_~j~0 4294967296)))) (= main_~j~0 0))} is VALID [2022-04-07 16:41:51,752 INFO L290 TraceCheckUtils]: 7: Hoare triple {309#(and (<= (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1) (+ main_~SIZE~0 (* 4294967296 (div main_~j~0 4294967296)))) (= main_~j~0 0))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {310#(and (not (<= (+ (div main_~j~0 4294967296) 1) 0)) (<= (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296)) (+ main_~SIZE~0 (* (div (+ (* (- 1) main_~j~0) 1) 4294967296) 4294967296))))} is VALID [2022-04-07 16:41:51,752 INFO L290 TraceCheckUtils]: 8: Hoare triple {310#(and (not (<= (+ (div main_~j~0 4294967296) 1) 0)) (<= (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296)) (+ main_~SIZE~0 (* (div (+ (* (- 1) main_~j~0) 1) 4294967296) 4294967296))))} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {311#(<= 0 (div (+ (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296))} is VALID [2022-04-07 16:41:51,753 INFO L290 TraceCheckUtils]: 9: Hoare triple {311#(<= 0 (div (+ (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296))} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {311#(<= 0 (div (+ (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296))} is VALID [2022-04-07 16:41:51,753 INFO L290 TraceCheckUtils]: 10: Hoare triple {311#(<= 0 (div (+ (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {311#(<= 0 (div (+ (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296))} is VALID [2022-04-07 16:41:51,754 INFO L290 TraceCheckUtils]: 11: Hoare triple {311#(<= 0 (div (+ (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {312#(and (= (+ (- 1) main_~k~0) 0) (<= (+ main_~SIZE~0 (* (div main_~k~0 4294967296) 4294967296)) (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} is VALID [2022-04-07 16:41:51,755 INFO L290 TraceCheckUtils]: 12: Hoare triple {312#(and (= (+ (- 1) main_~k~0) 0) (<= (+ main_~SIZE~0 (* (div main_~k~0 4294967296) 4294967296)) (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {304#false} is VALID [2022-04-07 16:41:51,755 INFO L272 TraceCheckUtils]: 13: Hoare triple {304#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {304#false} is VALID [2022-04-07 16:41:51,755 INFO L290 TraceCheckUtils]: 14: Hoare triple {304#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {304#false} is VALID [2022-04-07 16:41:51,755 INFO L290 TraceCheckUtils]: 15: Hoare triple {304#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {304#false} is VALID [2022-04-07 16:41:51,756 INFO L290 TraceCheckUtils]: 16: Hoare triple {304#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {304#false} is VALID [2022-04-07 16:41:51,756 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 16:41:51,756 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 16:41:51,756 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [542501569] [2022-04-07 16:41:51,756 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [542501569] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 16:41:51,757 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1503963604] [2022-04-07 16:41:51,757 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 16:41:51,757 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 16:41:51,757 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 16:41:51,758 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 16:41:51,794 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-04-07 16:41:51,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 16:41:51,835 INFO L263 TraceCheckSpWp]: Trace formula consists of 88 conjuncts, 6 conjunts are in the unsatisfiable core [2022-04-07 16:41:51,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 16:41:51,845 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 16:41:52,199 INFO L272 TraceCheckUtils]: 0: Hoare triple {303#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {303#true} is VALID [2022-04-07 16:41:52,200 INFO L290 TraceCheckUtils]: 1: Hoare triple {303#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {303#true} is VALID [2022-04-07 16:41:52,200 INFO L290 TraceCheckUtils]: 2: Hoare triple {303#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {303#true} is VALID [2022-04-07 16:41:52,200 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {303#true} {303#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {303#true} is VALID [2022-04-07 16:41:52,200 INFO L272 TraceCheckUtils]: 4: Hoare triple {303#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {303#true} is VALID [2022-04-07 16:41:52,201 INFO L290 TraceCheckUtils]: 5: Hoare triple {303#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (= (store |v_#length_2| |v_main_~#v~0.base_2| (* 4 (let ((.cse0 (mod v_main_~SIZE~0_2 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))))) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {303#true} is VALID [2022-04-07 16:41:52,201 INFO L290 TraceCheckUtils]: 6: Hoare triple {303#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {303#true} is VALID [2022-04-07 16:41:52,201 INFO L290 TraceCheckUtils]: 7: Hoare triple {303#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {303#true} is VALID [2022-04-07 16:41:52,201 INFO L290 TraceCheckUtils]: 8: Hoare triple {303#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {303#true} is VALID [2022-04-07 16:41:52,201 INFO L290 TraceCheckUtils]: 9: Hoare triple {303#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {344#(= main_~j~0 1)} is VALID [2022-04-07 16:41:52,202 INFO L290 TraceCheckUtils]: 10: Hoare triple {344#(= main_~j~0 1)} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {311#(<= 0 (div (+ (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296))} is VALID [2022-04-07 16:41:52,203 INFO L290 TraceCheckUtils]: 11: Hoare triple {311#(<= 0 (div (+ (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {312#(and (= (+ (- 1) main_~k~0) 0) (<= (+ main_~SIZE~0 (* (div main_~k~0 4294967296) 4294967296)) (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} is VALID [2022-04-07 16:41:52,204 INFO L290 TraceCheckUtils]: 12: Hoare triple {312#(and (= (+ (- 1) main_~k~0) 0) (<= (+ main_~SIZE~0 (* (div main_~k~0 4294967296) 4294967296)) (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {304#false} is VALID [2022-04-07 16:41:52,204 INFO L272 TraceCheckUtils]: 13: Hoare triple {304#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {304#false} is VALID [2022-04-07 16:41:52,204 INFO L290 TraceCheckUtils]: 14: Hoare triple {304#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {304#false} is VALID [2022-04-07 16:41:52,204 INFO L290 TraceCheckUtils]: 15: Hoare triple {304#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {304#false} is VALID [2022-04-07 16:41:52,204 INFO L290 TraceCheckUtils]: 16: Hoare triple {304#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {304#false} is VALID [2022-04-07 16:41:52,205 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-07 16:41:52,205 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-04-07 16:41:52,205 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1503963604] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-07 16:41:52,205 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-04-07 16:41:52,205 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [8] total 9 [2022-04-07 16:41:52,205 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [703247952] [2022-04-07 16:41:52,205 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-07 16:41:52,206 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-07 16:41:52,206 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 16:41:52,206 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:41:52,218 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 17 edges. 17 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 16:41:52,218 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-04-07 16:41:52,218 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 16:41:52,218 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-04-07 16:41:52,219 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2022-04-07 16:41:52,219 INFO L87 Difference]: Start difference. First operand 29 states and 34 transitions. Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:41:52,343 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 16:41:52,343 INFO L93 Difference]: Finished difference Result 39 states and 47 transitions. [2022-04-07 16:41:52,343 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-04-07 16:41:52,343 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-07 16:41:52,343 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 16:41:52,344 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:41:52,346 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 47 transitions. [2022-04-07 16:41:52,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:41:52,347 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 47 transitions. [2022-04-07 16:41:52,347 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 5 states and 47 transitions. [2022-04-07 16:41:52,391 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 47 edges. 47 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 16:41:52,392 INFO L225 Difference]: With dead ends: 39 [2022-04-07 16:41:52,392 INFO L226 Difference]: Without dead ends: 37 [2022-04-07 16:41:52,392 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 16 SyntacticMatches, 2 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=29, Invalid=81, Unknown=0, NotChecked=0, Total=110 [2022-04-07 16:41:52,393 INFO L913 BasicCegarLoop]: 30 mSDtfsCounter, 13 mSDsluCounter, 75 mSDsCounter, 0 mSdLazyCounter, 26 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 13 SdHoareTripleChecker+Valid, 105 SdHoareTripleChecker+Invalid, 26 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 26 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-07 16:41:52,393 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [13 Valid, 105 Invalid, 26 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 26 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-07 16:41:52,394 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states. [2022-04-07 16:41:52,395 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 30. [2022-04-07 16:41:52,395 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 16:41:52,396 INFO L82 GeneralOperation]: Start isEquivalent. First operand 37 states. Second operand has 30 states, 24 states have (on average 1.25) internal successors, (30), 24 states have internal predecessors, (30), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-07 16:41:52,396 INFO L74 IsIncluded]: Start isIncluded. First operand 37 states. Second operand has 30 states, 24 states have (on average 1.25) internal successors, (30), 24 states have internal predecessors, (30), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-07 16:41:52,396 INFO L87 Difference]: Start difference. First operand 37 states. Second operand has 30 states, 24 states have (on average 1.25) internal successors, (30), 24 states have internal predecessors, (30), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-07 16:41:52,398 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 16:41:52,398 INFO L93 Difference]: Finished difference Result 37 states and 45 transitions. [2022-04-07 16:41:52,398 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 45 transitions. [2022-04-07 16:41:52,399 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 16:41:52,400 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 16:41:52,400 INFO L74 IsIncluded]: Start isIncluded. First operand has 30 states, 24 states have (on average 1.25) internal successors, (30), 24 states have internal predecessors, (30), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 37 states. [2022-04-07 16:41:52,402 INFO L87 Difference]: Start difference. First operand has 30 states, 24 states have (on average 1.25) internal successors, (30), 24 states have internal predecessors, (30), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 37 states. [2022-04-07 16:41:52,405 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 16:41:52,406 INFO L93 Difference]: Finished difference Result 37 states and 45 transitions. [2022-04-07 16:41:52,406 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 45 transitions. [2022-04-07 16:41:52,406 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 16:41:52,406 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 16:41:52,406 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 16:41:52,406 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 16:41:52,407 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30 states, 24 states have (on average 1.25) internal successors, (30), 24 states have internal predecessors, (30), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-07 16:41:52,407 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 35 transitions. [2022-04-07 16:41:52,408 INFO L78 Accepts]: Start accepts. Automaton has 30 states and 35 transitions. Word has length 17 [2022-04-07 16:41:52,408 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 16:41:52,408 INFO L478 AbstractCegarLoop]: Abstraction has 30 states and 35 transitions. [2022-04-07 16:41:52,408 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:41:52,408 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 35 transitions. [2022-04-07 16:41:52,408 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2022-04-07 16:41:52,408 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 16:41:52,409 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 16:41:52,426 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Ended with exit code 0 [2022-04-07 16:41:52,619 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2,2 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 16:41:52,620 INFO L403 AbstractCegarLoop]: === Iteration 4 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 16:41:52,620 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 16:41:52,620 INFO L85 PathProgramCache]: Analyzing trace with hash 931318849, now seen corresponding path program 1 times [2022-04-07 16:41:52,621 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 16:41:52,621 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1755989029] [2022-04-07 16:41:52,621 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 16:41:52,621 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 16:41:52,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 16:41:52,736 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 16:41:52,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 16:41:52,752 INFO L290 TraceCheckUtils]: 0: Hoare triple {521#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {512#true} is VALID [2022-04-07 16:41:52,752 INFO L290 TraceCheckUtils]: 1: Hoare triple {512#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {512#true} is VALID [2022-04-07 16:41:52,752 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {512#true} {512#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {512#true} is VALID [2022-04-07 16:41:52,753 INFO L272 TraceCheckUtils]: 0: Hoare triple {512#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {521#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 16:41:52,753 INFO L290 TraceCheckUtils]: 1: Hoare triple {521#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {512#true} is VALID [2022-04-07 16:41:52,753 INFO L290 TraceCheckUtils]: 2: Hoare triple {512#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {512#true} is VALID [2022-04-07 16:41:52,754 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {512#true} {512#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {512#true} is VALID [2022-04-07 16:41:52,754 INFO L272 TraceCheckUtils]: 4: Hoare triple {512#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {512#true} is VALID [2022-04-07 16:41:52,754 INFO L290 TraceCheckUtils]: 5: Hoare triple {512#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (= (store |v_#length_2| |v_main_~#v~0.base_2| (* 4 (let ((.cse0 (mod v_main_~SIZE~0_2 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))))) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {517#(= main_~j~0 0)} is VALID [2022-04-07 16:41:52,754 INFO L290 TraceCheckUtils]: 6: Hoare triple {517#(= main_~j~0 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {517#(= main_~j~0 0)} is VALID [2022-04-07 16:41:52,755 INFO L290 TraceCheckUtils]: 7: Hoare triple {517#(= main_~j~0 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {518#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 16:41:52,756 INFO L290 TraceCheckUtils]: 8: Hoare triple {518#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {519#(<= 0 (div (+ (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296))} is VALID [2022-04-07 16:41:52,756 INFO L290 TraceCheckUtils]: 9: Hoare triple {519#(<= 0 (div (+ (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296))} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {520#(and (= (+ (- 1) main_~j~0) 0) (<= (+ main_~SIZE~0 (* 4294967296 (div main_~j~0 4294967296))) (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} is VALID [2022-04-07 16:41:52,757 INFO L290 TraceCheckUtils]: 10: Hoare triple {520#(and (= (+ (- 1) main_~j~0) 0) (<= (+ main_~SIZE~0 (* 4294967296 (div main_~j~0 4294967296))) (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {513#false} is VALID [2022-04-07 16:41:52,758 INFO L290 TraceCheckUtils]: 11: Hoare triple {513#false} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {513#false} is VALID [2022-04-07 16:41:52,758 INFO L290 TraceCheckUtils]: 12: Hoare triple {513#false} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {513#false} is VALID [2022-04-07 16:41:52,759 INFO L290 TraceCheckUtils]: 13: Hoare triple {513#false} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {513#false} is VALID [2022-04-07 16:41:52,759 INFO L290 TraceCheckUtils]: 14: Hoare triple {513#false} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {513#false} is VALID [2022-04-07 16:41:52,759 INFO L290 TraceCheckUtils]: 15: Hoare triple {513#false} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {513#false} is VALID [2022-04-07 16:41:52,759 INFO L290 TraceCheckUtils]: 16: Hoare triple {513#false} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {513#false} is VALID [2022-04-07 16:41:52,759 INFO L290 TraceCheckUtils]: 17: Hoare triple {513#false} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {513#false} is VALID [2022-04-07 16:41:52,760 INFO L290 TraceCheckUtils]: 18: Hoare triple {513#false} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {513#false} is VALID [2022-04-07 16:41:52,760 INFO L272 TraceCheckUtils]: 19: Hoare triple {513#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {513#false} is VALID [2022-04-07 16:41:52,760 INFO L290 TraceCheckUtils]: 20: Hoare triple {513#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {513#false} is VALID [2022-04-07 16:41:52,761 INFO L290 TraceCheckUtils]: 21: Hoare triple {513#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {513#false} is VALID [2022-04-07 16:41:52,761 INFO L290 TraceCheckUtils]: 22: Hoare triple {513#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {513#false} is VALID [2022-04-07 16:41:52,765 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 16:41:52,765 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 16:41:52,765 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1755989029] [2022-04-07 16:41:52,766 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1755989029] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 16:41:52,766 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1594356394] [2022-04-07 16:41:52,766 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 16:41:52,766 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 16:41:52,766 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 16:41:52,790 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 16:41:52,835 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-04-07 16:41:52,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 16:41:52,877 INFO L263 TraceCheckSpWp]: Trace formula consists of 105 conjuncts, 8 conjunts are in the unsatisfiable core [2022-04-07 16:41:52,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 16:41:52,891 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 16:41:53,313 INFO L272 TraceCheckUtils]: 0: Hoare triple {512#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {512#true} is VALID [2022-04-07 16:41:53,314 INFO L290 TraceCheckUtils]: 1: Hoare triple {512#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {512#true} is VALID [2022-04-07 16:41:53,314 INFO L290 TraceCheckUtils]: 2: Hoare triple {512#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {512#true} is VALID [2022-04-07 16:41:53,317 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {512#true} {512#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {512#true} is VALID [2022-04-07 16:41:53,317 INFO L272 TraceCheckUtils]: 4: Hoare triple {512#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {512#true} is VALID [2022-04-07 16:41:53,318 INFO L290 TraceCheckUtils]: 5: Hoare triple {512#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (= (store |v_#length_2| |v_main_~#v~0.base_2| (* 4 (let ((.cse0 (mod v_main_~SIZE~0_2 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))))) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {517#(= main_~j~0 0)} is VALID [2022-04-07 16:41:53,318 INFO L290 TraceCheckUtils]: 6: Hoare triple {517#(= main_~j~0 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {517#(= main_~j~0 0)} is VALID [2022-04-07 16:41:53,319 INFO L290 TraceCheckUtils]: 7: Hoare triple {517#(= main_~j~0 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {518#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 16:41:53,320 INFO L290 TraceCheckUtils]: 8: Hoare triple {518#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {519#(<= 0 (div (+ (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296))} is VALID [2022-04-07 16:41:53,322 INFO L290 TraceCheckUtils]: 9: Hoare triple {519#(<= 0 (div (+ (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296))} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {520#(and (= (+ (- 1) main_~j~0) 0) (<= (+ main_~SIZE~0 (* 4294967296 (div main_~j~0 4294967296))) (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} is VALID [2022-04-07 16:41:53,323 INFO L290 TraceCheckUtils]: 10: Hoare triple {520#(and (= (+ (- 1) main_~j~0) 0) (<= (+ main_~SIZE~0 (* 4294967296 (div main_~j~0 4294967296))) (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {513#false} is VALID [2022-04-07 16:41:53,323 INFO L290 TraceCheckUtils]: 11: Hoare triple {513#false} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {513#false} is VALID [2022-04-07 16:41:53,325 INFO L290 TraceCheckUtils]: 12: Hoare triple {513#false} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {513#false} is VALID [2022-04-07 16:41:53,327 INFO L290 TraceCheckUtils]: 13: Hoare triple {513#false} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {513#false} is VALID [2022-04-07 16:41:53,327 INFO L290 TraceCheckUtils]: 14: Hoare triple {513#false} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {513#false} is VALID [2022-04-07 16:41:53,328 INFO L290 TraceCheckUtils]: 15: Hoare triple {513#false} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {513#false} is VALID [2022-04-07 16:41:53,328 INFO L290 TraceCheckUtils]: 16: Hoare triple {513#false} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {513#false} is VALID [2022-04-07 16:41:53,328 INFO L290 TraceCheckUtils]: 17: Hoare triple {513#false} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {513#false} is VALID [2022-04-07 16:41:53,331 INFO L290 TraceCheckUtils]: 18: Hoare triple {513#false} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {513#false} is VALID [2022-04-07 16:41:53,331 INFO L272 TraceCheckUtils]: 19: Hoare triple {513#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {513#false} is VALID [2022-04-07 16:41:53,331 INFO L290 TraceCheckUtils]: 20: Hoare triple {513#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {513#false} is VALID [2022-04-07 16:41:53,331 INFO L290 TraceCheckUtils]: 21: Hoare triple {513#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {513#false} is VALID [2022-04-07 16:41:53,331 INFO L290 TraceCheckUtils]: 22: Hoare triple {513#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {513#false} is VALID [2022-04-07 16:41:53,332 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 16:41:53,332 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-07 16:42:10,478 INFO L290 TraceCheckUtils]: 22: Hoare triple {513#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {513#false} is VALID [2022-04-07 16:42:10,479 INFO L290 TraceCheckUtils]: 21: Hoare triple {513#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {513#false} is VALID [2022-04-07 16:42:10,479 INFO L290 TraceCheckUtils]: 20: Hoare triple {513#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {513#false} is VALID [2022-04-07 16:42:10,479 INFO L272 TraceCheckUtils]: 19: Hoare triple {513#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {513#false} is VALID [2022-04-07 16:42:10,479 INFO L290 TraceCheckUtils]: 18: Hoare triple {513#false} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {513#false} is VALID [2022-04-07 16:42:10,480 INFO L290 TraceCheckUtils]: 17: Hoare triple {513#false} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {513#false} is VALID [2022-04-07 16:42:10,480 INFO L290 TraceCheckUtils]: 16: Hoare triple {513#false} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {513#false} is VALID [2022-04-07 16:42:10,480 INFO L290 TraceCheckUtils]: 15: Hoare triple {513#false} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {513#false} is VALID [2022-04-07 16:42:10,480 INFO L290 TraceCheckUtils]: 14: Hoare triple {513#false} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {513#false} is VALID [2022-04-07 16:42:10,480 INFO L290 TraceCheckUtils]: 13: Hoare triple {513#false} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {513#false} is VALID [2022-04-07 16:42:10,481 INFO L290 TraceCheckUtils]: 12: Hoare triple {513#false} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {513#false} is VALID [2022-04-07 16:42:10,481 INFO L290 TraceCheckUtils]: 11: Hoare triple {513#false} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {513#false} is VALID [2022-04-07 16:42:10,482 INFO L290 TraceCheckUtils]: 10: Hoare triple {627#(not (< (mod main_~j~0 4294967296) (mod main_~SIZE~0 4294967296)))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {513#false} is VALID [2022-04-07 16:42:10,483 INFO L290 TraceCheckUtils]: 9: Hoare triple {519#(<= 0 (div (+ (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296))} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {627#(not (< (mod main_~j~0 4294967296) (mod main_~SIZE~0 4294967296)))} is VALID [2022-04-07 16:42:11,101 INFO L290 TraceCheckUtils]: 8: Hoare triple {634#(forall ((aux_div_aux_mod_main_~SIZE~0_29_56 Int) (aux_mod_aux_mod_main_~SIZE~0_29_56 Int)) (or (<= 0 aux_div_aux_mod_main_~SIZE~0_29_56) (< (mod main_~j~0 4294967296) (mod (+ (* 4294967295 aux_mod_aux_mod_main_~SIZE~0_29_56) 1) 4294967296)) (<= (+ 4294967295 (* aux_div_aux_mod_main_~SIZE~0_29_56 4294967296) aux_mod_aux_mod_main_~SIZE~0_29_56) 0) (<= 4294967296 aux_mod_aux_mod_main_~SIZE~0_29_56)))} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {519#(<= 0 (div (+ (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296))} is VALID [2022-04-07 16:42:11,105 INFO L290 TraceCheckUtils]: 7: Hoare triple {638#(forall ((aux_div_aux_mod_main_~SIZE~0_29_56 Int) (aux_mod_aux_mod_main_~SIZE~0_29_56 Int)) (or (<= 0 aux_div_aux_mod_main_~SIZE~0_29_56) (<= (+ 4294967295 (* aux_div_aux_mod_main_~SIZE~0_29_56 4294967296) aux_mod_aux_mod_main_~SIZE~0_29_56) 0) (<= 4294967296 aux_mod_aux_mod_main_~SIZE~0_29_56) (< (mod (+ main_~j~0 1) 4294967296) (mod (+ (* 4294967295 aux_mod_aux_mod_main_~SIZE~0_29_56) 1) 4294967296))))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {634#(forall ((aux_div_aux_mod_main_~SIZE~0_29_56 Int) (aux_mod_aux_mod_main_~SIZE~0_29_56 Int)) (or (<= 0 aux_div_aux_mod_main_~SIZE~0_29_56) (< (mod main_~j~0 4294967296) (mod (+ (* 4294967295 aux_mod_aux_mod_main_~SIZE~0_29_56) 1) 4294967296)) (<= (+ 4294967295 (* aux_div_aux_mod_main_~SIZE~0_29_56 4294967296) aux_mod_aux_mod_main_~SIZE~0_29_56) 0) (<= 4294967296 aux_mod_aux_mod_main_~SIZE~0_29_56)))} is VALID [2022-04-07 16:42:11,106 INFO L290 TraceCheckUtils]: 6: Hoare triple {638#(forall ((aux_div_aux_mod_main_~SIZE~0_29_56 Int) (aux_mod_aux_mod_main_~SIZE~0_29_56 Int)) (or (<= 0 aux_div_aux_mod_main_~SIZE~0_29_56) (<= (+ 4294967295 (* aux_div_aux_mod_main_~SIZE~0_29_56 4294967296) aux_mod_aux_mod_main_~SIZE~0_29_56) 0) (<= 4294967296 aux_mod_aux_mod_main_~SIZE~0_29_56) (< (mod (+ main_~j~0 1) 4294967296) (mod (+ (* 4294967295 aux_mod_aux_mod_main_~SIZE~0_29_56) 1) 4294967296))))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {638#(forall ((aux_div_aux_mod_main_~SIZE~0_29_56 Int) (aux_mod_aux_mod_main_~SIZE~0_29_56 Int)) (or (<= 0 aux_div_aux_mod_main_~SIZE~0_29_56) (<= (+ 4294967295 (* aux_div_aux_mod_main_~SIZE~0_29_56 4294967296) aux_mod_aux_mod_main_~SIZE~0_29_56) 0) (<= 4294967296 aux_mod_aux_mod_main_~SIZE~0_29_56) (< (mod (+ main_~j~0 1) 4294967296) (mod (+ (* 4294967295 aux_mod_aux_mod_main_~SIZE~0_29_56) 1) 4294967296))))} is VALID [2022-04-07 16:42:11,108 INFO L290 TraceCheckUtils]: 5: Hoare triple {512#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (= (store |v_#length_2| |v_main_~#v~0.base_2| (* 4 (let ((.cse0 (mod v_main_~SIZE~0_2 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))))) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {638#(forall ((aux_div_aux_mod_main_~SIZE~0_29_56 Int) (aux_mod_aux_mod_main_~SIZE~0_29_56 Int)) (or (<= 0 aux_div_aux_mod_main_~SIZE~0_29_56) (<= (+ 4294967295 (* aux_div_aux_mod_main_~SIZE~0_29_56 4294967296) aux_mod_aux_mod_main_~SIZE~0_29_56) 0) (<= 4294967296 aux_mod_aux_mod_main_~SIZE~0_29_56) (< (mod (+ main_~j~0 1) 4294967296) (mod (+ (* 4294967295 aux_mod_aux_mod_main_~SIZE~0_29_56) 1) 4294967296))))} is VALID [2022-04-07 16:42:11,108 INFO L272 TraceCheckUtils]: 4: Hoare triple {512#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {512#true} is VALID [2022-04-07 16:42:11,108 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {512#true} {512#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {512#true} is VALID [2022-04-07 16:42:11,108 INFO L290 TraceCheckUtils]: 2: Hoare triple {512#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {512#true} is VALID [2022-04-07 16:42:11,109 INFO L290 TraceCheckUtils]: 1: Hoare triple {512#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {512#true} is VALID [2022-04-07 16:42:11,109 INFO L272 TraceCheckUtils]: 0: Hoare triple {512#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {512#true} is VALID [2022-04-07 16:42:11,109 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 16:42:11,111 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1594356394] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-07 16:42:11,111 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-07 16:42:11,111 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6, 6] total 10 [2022-04-07 16:42:11,111 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1558815511] [2022-04-07 16:42:11,112 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-07 16:42:11,112 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 2.6) internal successors, (26), 9 states have internal predecessors, (26), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 23 [2022-04-07 16:42:11,112 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 16:42:11,113 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 10 states, 10 states have (on average 2.6) internal successors, (26), 9 states have internal predecessors, (26), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:42:14,733 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 31 edges. 30 inductive. 0 not inductive. 1 times theorem prover too weak to decide inductivity. [2022-04-07 16:42:14,733 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2022-04-07 16:42:14,733 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 16:42:14,734 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2022-04-07 16:42:14,734 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=60, Unknown=6, NotChecked=0, Total=90 [2022-04-07 16:42:14,734 INFO L87 Difference]: Start difference. First operand 30 states and 35 transitions. Second operand has 10 states, 10 states have (on average 2.6) internal successors, (26), 9 states have internal predecessors, (26), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:42:16,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 16:42:16,078 INFO L93 Difference]: Finished difference Result 35 states and 40 transitions. [2022-04-07 16:42:16,078 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-04-07 16:42:16,079 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 2.6) internal successors, (26), 9 states have internal predecessors, (26), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 23 [2022-04-07 16:42:16,079 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 16:42:16,079 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 2.6) internal successors, (26), 9 states have internal predecessors, (26), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:42:16,080 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 40 transitions. [2022-04-07 16:42:16,080 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 2.6) internal successors, (26), 9 states have internal predecessors, (26), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:42:16,081 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 40 transitions. [2022-04-07 16:42:16,081 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 7 states and 40 transitions. [2022-04-07 16:42:16,115 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 40 edges. 40 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 16:42:16,116 INFO L225 Difference]: With dead ends: 35 [2022-04-07 16:42:16,116 INFO L226 Difference]: Without dead ends: 33 [2022-04-07 16:42:16,116 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 60 GetRequests, 44 SyntacticMatches, 4 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 16.1s TimeCoverageRelationStatistics Valid=49, Invalid=127, Unknown=6, NotChecked=0, Total=182 [2022-04-07 16:42:16,117 INFO L913 BasicCegarLoop]: 28 mSDtfsCounter, 40 mSDsluCounter, 22 mSDsCounter, 0 mSdLazyCounter, 64 mSolverCounterSat, 10 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 40 SdHoareTripleChecker+Valid, 50 SdHoareTripleChecker+Invalid, 134 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 10 IncrementalHoareTripleChecker+Valid, 64 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 60 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-07 16:42:16,117 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [40 Valid, 50 Invalid, 134 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [10 Valid, 64 Invalid, 0 Unknown, 60 Unchecked, 0.1s Time] [2022-04-07 16:42:16,117 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33 states. [2022-04-07 16:42:16,119 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33 to 32. [2022-04-07 16:42:16,119 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 16:42:16,119 INFO L82 GeneralOperation]: Start isEquivalent. First operand 33 states. Second operand has 32 states, 26 states have (on average 1.2307692307692308) internal successors, (32), 26 states have internal predecessors, (32), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-07 16:42:16,119 INFO L74 IsIncluded]: Start isIncluded. First operand 33 states. Second operand has 32 states, 26 states have (on average 1.2307692307692308) internal successors, (32), 26 states have internal predecessors, (32), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-07 16:42:16,119 INFO L87 Difference]: Start difference. First operand 33 states. Second operand has 32 states, 26 states have (on average 1.2307692307692308) internal successors, (32), 26 states have internal predecessors, (32), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-07 16:42:16,120 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 16:42:16,120 INFO L93 Difference]: Finished difference Result 33 states and 38 transitions. [2022-04-07 16:42:16,120 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 38 transitions. [2022-04-07 16:42:16,121 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 16:42:16,121 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 16:42:16,121 INFO L74 IsIncluded]: Start isIncluded. First operand has 32 states, 26 states have (on average 1.2307692307692308) internal successors, (32), 26 states have internal predecessors, (32), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 33 states. [2022-04-07 16:42:16,121 INFO L87 Difference]: Start difference. First operand has 32 states, 26 states have (on average 1.2307692307692308) internal successors, (32), 26 states have internal predecessors, (32), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 33 states. [2022-04-07 16:42:16,124 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 16:42:16,124 INFO L93 Difference]: Finished difference Result 33 states and 38 transitions. [2022-04-07 16:42:16,124 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 38 transitions. [2022-04-07 16:42:16,124 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 16:42:16,124 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 16:42:16,124 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 16:42:16,124 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 16:42:16,125 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32 states, 26 states have (on average 1.2307692307692308) internal successors, (32), 26 states have internal predecessors, (32), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-07 16:42:16,125 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 37 transitions. [2022-04-07 16:42:16,125 INFO L78 Accepts]: Start accepts. Automaton has 32 states and 37 transitions. Word has length 23 [2022-04-07 16:42:16,126 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 16:42:16,126 INFO L478 AbstractCegarLoop]: Abstraction has 32 states and 37 transitions. [2022-04-07 16:42:16,126 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 2.6) internal successors, (26), 9 states have internal predecessors, (26), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:42:16,126 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 37 transitions. [2022-04-07 16:42:16,126 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2022-04-07 16:42:16,126 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 16:42:16,126 INFO L499 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 16:42:16,149 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2022-04-07 16:42:16,341 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable3 [2022-04-07 16:42:16,341 INFO L403 AbstractCegarLoop]: === Iteration 5 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 16:42:16,341 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 16:42:16,341 INFO L85 PathProgramCache]: Analyzing trace with hash -1459507809, now seen corresponding path program 2 times [2022-04-07 16:42:16,341 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 16:42:16,342 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [271310126] [2022-04-07 16:42:16,342 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 16:42:16,342 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 16:42:16,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 16:42:16,829 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 16:42:16,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 16:42:16,848 INFO L290 TraceCheckUtils]: 0: Hoare triple {823#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {805#true} is VALID [2022-04-07 16:42:16,848 INFO L290 TraceCheckUtils]: 1: Hoare triple {805#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {805#true} is VALID [2022-04-07 16:42:16,849 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {805#true} {805#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {805#true} is VALID [2022-04-07 16:42:16,849 INFO L272 TraceCheckUtils]: 0: Hoare triple {805#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {823#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 16:42:16,849 INFO L290 TraceCheckUtils]: 1: Hoare triple {823#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {805#true} is VALID [2022-04-07 16:42:16,849 INFO L290 TraceCheckUtils]: 2: Hoare triple {805#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {805#true} is VALID [2022-04-07 16:42:16,849 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {805#true} {805#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {805#true} is VALID [2022-04-07 16:42:16,850 INFO L272 TraceCheckUtils]: 4: Hoare triple {805#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {805#true} is VALID [2022-04-07 16:42:16,850 INFO L290 TraceCheckUtils]: 5: Hoare triple {805#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (= (store |v_#length_2| |v_main_~#v~0.base_2| (* 4 (let ((.cse0 (mod v_main_~SIZE~0_2 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))))) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {810#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-07 16:42:16,851 INFO L290 TraceCheckUtils]: 6: Hoare triple {810#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {810#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-07 16:42:16,851 INFO L290 TraceCheckUtils]: 7: Hoare triple {810#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {811#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 16:42:16,852 INFO L290 TraceCheckUtils]: 8: Hoare triple {811#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {811#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 16:42:16,852 INFO L290 TraceCheckUtils]: 9: Hoare triple {811#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {812#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 16:42:16,852 INFO L290 TraceCheckUtils]: 10: Hoare triple {812#(= |main_~#v~0.offset| 0)} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {812#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 16:42:16,853 INFO L290 TraceCheckUtils]: 11: Hoare triple {812#(= |main_~#v~0.offset| 0)} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {811#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 16:42:16,854 INFO L290 TraceCheckUtils]: 12: Hoare triple {811#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {813#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-07 16:42:16,854 INFO L290 TraceCheckUtils]: 13: Hoare triple {813#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~i~0 1) main_~j~0))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {814#(and (= (+ (- 1) main_~j~0) 0) (or (not |main_#t~short10|) (and (= |main_~#v~0.offset| 0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0))))} is VALID [2022-04-07 16:42:16,855 INFO L290 TraceCheckUtils]: 14: Hoare triple {814#(and (= (+ (- 1) main_~j~0) 0) (or (not |main_#t~short10|) (and (= |main_~#v~0.offset| 0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {815#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} is VALID [2022-04-07 16:42:16,855 INFO L290 TraceCheckUtils]: 15: Hoare triple {815#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {816#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-07 16:42:16,856 INFO L290 TraceCheckUtils]: 16: Hoare triple {816#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {817#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:42:16,857 INFO L290 TraceCheckUtils]: 17: Hoare triple {817#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {818#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:42:16,857 INFO L290 TraceCheckUtils]: 18: Hoare triple {818#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {818#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:42:16,858 INFO L290 TraceCheckUtils]: 19: Hoare triple {818#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {819#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-07 16:42:16,858 INFO L290 TraceCheckUtils]: 20: Hoare triple {819#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {820#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-07 16:42:16,859 INFO L272 TraceCheckUtils]: 21: Hoare triple {820#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {821#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-07 16:42:16,859 INFO L290 TraceCheckUtils]: 22: Hoare triple {821#(not (= |__VERIFIER_assert_#in~cond| 0))} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {822#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-07 16:42:16,860 INFO L290 TraceCheckUtils]: 23: Hoare triple {822#(not (= __VERIFIER_assert_~cond 0))} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {806#false} is VALID [2022-04-07 16:42:16,860 INFO L290 TraceCheckUtils]: 24: Hoare triple {806#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {806#false} is VALID [2022-04-07 16:42:16,860 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 16:42:16,860 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 16:42:16,860 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [271310126] [2022-04-07 16:42:16,860 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [271310126] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 16:42:16,860 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [328820169] [2022-04-07 16:42:16,861 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-04-07 16:42:16,861 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 16:42:16,861 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 16:42:16,862 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 16:42:16,862 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-04-07 16:42:16,933 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-04-07 16:42:16,933 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-07 16:42:16,934 INFO L263 TraceCheckSpWp]: Trace formula consists of 114 conjuncts, 21 conjunts are in the unsatisfiable core [2022-04-07 16:42:16,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 16:42:16,947 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 16:42:17,278 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-04-07 16:42:17,280 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-04-07 16:42:17,402 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-04-07 16:42:17,402 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 10 [2022-04-07 16:42:17,488 INFO L272 TraceCheckUtils]: 0: Hoare triple {805#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {805#true} is VALID [2022-04-07 16:42:17,489 INFO L290 TraceCheckUtils]: 1: Hoare triple {805#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {805#true} is VALID [2022-04-07 16:42:17,489 INFO L290 TraceCheckUtils]: 2: Hoare triple {805#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {805#true} is VALID [2022-04-07 16:42:17,489 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {805#true} {805#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {805#true} is VALID [2022-04-07 16:42:17,489 INFO L272 TraceCheckUtils]: 4: Hoare triple {805#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {805#true} is VALID [2022-04-07 16:42:17,490 INFO L290 TraceCheckUtils]: 5: Hoare triple {805#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (= (store |v_#length_2| |v_main_~#v~0.base_2| (* 4 (let ((.cse0 (mod v_main_~SIZE~0_2 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))))) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {812#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 16:42:17,490 INFO L290 TraceCheckUtils]: 6: Hoare triple {812#(= |main_~#v~0.offset| 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {812#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 16:42:17,490 INFO L290 TraceCheckUtils]: 7: Hoare triple {812#(= |main_~#v~0.offset| 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {812#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 16:42:17,491 INFO L290 TraceCheckUtils]: 8: Hoare triple {812#(= |main_~#v~0.offset| 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {812#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 16:42:17,491 INFO L290 TraceCheckUtils]: 9: Hoare triple {812#(= |main_~#v~0.offset| 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {812#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 16:42:17,492 INFO L290 TraceCheckUtils]: 10: Hoare triple {812#(= |main_~#v~0.offset| 0)} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {812#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 16:42:17,492 INFO L290 TraceCheckUtils]: 11: Hoare triple {812#(= |main_~#v~0.offset| 0)} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {811#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 16:42:17,493 INFO L290 TraceCheckUtils]: 12: Hoare triple {811#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {863#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= 0 main_~i~0))} is VALID [2022-04-07 16:42:17,494 INFO L290 TraceCheckUtils]: 13: Hoare triple {863#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= 0 main_~i~0))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {867#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= 0 main_~i~0) |main_#t~short10|)} is VALID [2022-04-07 16:42:17,494 INFO L290 TraceCheckUtils]: 14: Hoare triple {867#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= 0 main_~i~0) |main_#t~short10|)} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {871#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= 0 main_~i~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} is VALID [2022-04-07 16:42:17,495 INFO L290 TraceCheckUtils]: 15: Hoare triple {871#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= 0 main_~i~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {875#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0))} is VALID [2022-04-07 16:42:17,496 INFO L290 TraceCheckUtils]: 16: Hoare triple {875#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {818#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:42:17,496 INFO L290 TraceCheckUtils]: 17: Hoare triple {818#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {818#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:42:17,497 INFO L290 TraceCheckUtils]: 18: Hoare triple {818#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {818#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:42:17,497 INFO L290 TraceCheckUtils]: 19: Hoare triple {818#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {819#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-07 16:42:17,498 INFO L290 TraceCheckUtils]: 20: Hoare triple {819#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {820#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-07 16:42:17,499 INFO L272 TraceCheckUtils]: 21: Hoare triple {820#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {894#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 16:42:17,499 INFO L290 TraceCheckUtils]: 22: Hoare triple {894#(<= 1 |__VERIFIER_assert_#in~cond|)} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {898#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 16:42:17,499 INFO L290 TraceCheckUtils]: 23: Hoare triple {898#(<= 1 __VERIFIER_assert_~cond)} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {806#false} is VALID [2022-04-07 16:42:17,500 INFO L290 TraceCheckUtils]: 24: Hoare triple {806#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {806#false} is VALID [2022-04-07 16:42:17,500 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-07 16:42:17,500 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-07 16:42:17,934 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 41 treesize of output 35 [2022-04-07 16:42:17,970 INFO L356 Elim1Store]: treesize reduction 21, result has 43.2 percent of original size [2022-04-07 16:42:17,971 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 93 treesize of output 90 [2022-04-07 16:42:18,143 INFO L290 TraceCheckUtils]: 24: Hoare triple {806#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {806#false} is VALID [2022-04-07 16:42:18,143 INFO L290 TraceCheckUtils]: 23: Hoare triple {898#(<= 1 __VERIFIER_assert_~cond)} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {806#false} is VALID [2022-04-07 16:42:18,144 INFO L290 TraceCheckUtils]: 22: Hoare triple {894#(<= 1 |__VERIFIER_assert_#in~cond|)} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {898#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 16:42:18,145 INFO L272 TraceCheckUtils]: 21: Hoare triple {820#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {894#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 16:42:18,145 INFO L290 TraceCheckUtils]: 20: Hoare triple {917#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {820#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-07 16:42:18,146 INFO L290 TraceCheckUtils]: 19: Hoare triple {921#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {917#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} is VALID [2022-04-07 16:42:18,146 INFO L290 TraceCheckUtils]: 18: Hoare triple {921#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {921#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-07 16:42:18,146 INFO L290 TraceCheckUtils]: 17: Hoare triple {921#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {921#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-07 16:42:18,147 INFO L290 TraceCheckUtils]: 16: Hoare triple {931#(forall ((v_ArrVal_41 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_41) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_41) (+ |main_~#v~0.offset| 4))) (not (<= main_~key~0 v_ArrVal_41))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {921#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-07 16:42:18,148 INFO L290 TraceCheckUtils]: 15: Hoare triple {935#(or (forall ((v_ArrVal_41 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_41) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_41) (+ |main_~#v~0.offset| 4))) (not (<= main_~key~0 v_ArrVal_41)))) |main_#t~short10|)} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {931#(forall ((v_ArrVal_41 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_41) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_41) (+ |main_~#v~0.offset| 4))) (not (<= main_~key~0 v_ArrVal_41))))} is VALID [2022-04-07 16:42:18,149 INFO L290 TraceCheckUtils]: 14: Hoare triple {939#(or (not |main_#t~short10|) (= 0 (* main_~i~0 4)))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {935#(or (forall ((v_ArrVal_41 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_41) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_41) (+ |main_~#v~0.offset| 4))) (not (<= main_~key~0 v_ArrVal_41)))) |main_#t~short10|)} is VALID [2022-04-07 16:42:18,149 INFO L290 TraceCheckUtils]: 13: Hoare triple {943#(or (not (<= 0 main_~i~0)) (= 0 (* main_~i~0 4)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {939#(or (not |main_#t~short10|) (= 0 (* main_~i~0 4)))} is VALID [2022-04-07 16:42:18,150 INFO L290 TraceCheckUtils]: 12: Hoare triple {947#(or (not (<= 1 main_~j~0)) (= (+ (* main_~j~0 4) (- 4)) 0))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {943#(or (not (<= 0 main_~i~0)) (= 0 (* main_~i~0 4)))} is VALID [2022-04-07 16:42:18,150 INFO L290 TraceCheckUtils]: 11: Hoare triple {805#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {947#(or (not (<= 1 main_~j~0)) (= (+ (* main_~j~0 4) (- 4)) 0))} is VALID [2022-04-07 16:42:18,151 INFO L290 TraceCheckUtils]: 10: Hoare triple {805#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {805#true} is VALID [2022-04-07 16:42:18,151 INFO L290 TraceCheckUtils]: 9: Hoare triple {805#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {805#true} is VALID [2022-04-07 16:42:18,151 INFO L290 TraceCheckUtils]: 8: Hoare triple {805#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {805#true} is VALID [2022-04-07 16:42:18,151 INFO L290 TraceCheckUtils]: 7: Hoare triple {805#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {805#true} is VALID [2022-04-07 16:42:18,151 INFO L290 TraceCheckUtils]: 6: Hoare triple {805#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {805#true} is VALID [2022-04-07 16:42:18,151 INFO L290 TraceCheckUtils]: 5: Hoare triple {805#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (= (store |v_#length_2| |v_main_~#v~0.base_2| (* 4 (let ((.cse0 (mod v_main_~SIZE~0_2 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))))) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {805#true} is VALID [2022-04-07 16:42:18,151 INFO L272 TraceCheckUtils]: 4: Hoare triple {805#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {805#true} is VALID [2022-04-07 16:42:18,151 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {805#true} {805#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {805#true} is VALID [2022-04-07 16:42:18,151 INFO L290 TraceCheckUtils]: 2: Hoare triple {805#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {805#true} is VALID [2022-04-07 16:42:18,152 INFO L290 TraceCheckUtils]: 1: Hoare triple {805#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {805#true} is VALID [2022-04-07 16:42:18,152 INFO L272 TraceCheckUtils]: 0: Hoare triple {805#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {805#true} is VALID [2022-04-07 16:42:18,152 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-07 16:42:18,152 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [328820169] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-07 16:42:18,152 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-07 16:42:18,152 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 13, 12] total 29 [2022-04-07 16:42:18,152 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [819867056] [2022-04-07 16:42:18,152 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-07 16:42:18,153 INFO L78 Accepts]: Start accepts. Automaton has has 29 states, 28 states have (on average 1.6785714285714286) internal successors, (47), 26 states have internal predecessors, (47), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 25 [2022-04-07 16:42:18,153 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 16:42:18,154 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 29 states, 28 states have (on average 1.6785714285714286) internal successors, (47), 26 states have internal predecessors, (47), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:42:18,195 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 53 edges. 53 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 16:42:18,196 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 29 states [2022-04-07 16:42:18,196 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 16:42:18,196 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2022-04-07 16:42:18,196 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=123, Invalid=689, Unknown=0, NotChecked=0, Total=812 [2022-04-07 16:42:18,197 INFO L87 Difference]: Start difference. First operand 32 states and 37 transitions. Second operand has 29 states, 28 states have (on average 1.6785714285714286) internal successors, (47), 26 states have internal predecessors, (47), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:42:20,367 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 16:42:20,367 INFO L93 Difference]: Finished difference Result 87 states and 108 transitions. [2022-04-07 16:42:20,367 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2022-04-07 16:42:20,367 INFO L78 Accepts]: Start accepts. Automaton has has 29 states, 28 states have (on average 1.6785714285714286) internal successors, (47), 26 states have internal predecessors, (47), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 25 [2022-04-07 16:42:20,367 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 16:42:20,368 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29 states, 28 states have (on average 1.6785714285714286) internal successors, (47), 26 states have internal predecessors, (47), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:42:20,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 114 transitions. [2022-04-07 16:42:20,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29 states, 28 states have (on average 1.6785714285714286) internal successors, (47), 26 states have internal predecessors, (47), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:42:20,373 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 114 transitions. [2022-04-07 16:42:20,373 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 31 states and 114 transitions. [2022-04-07 16:42:20,512 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 114 edges. 114 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 16:42:20,513 INFO L225 Difference]: With dead ends: 87 [2022-04-07 16:42:20,514 INFO L226 Difference]: Without dead ends: 87 [2022-04-07 16:42:20,515 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 102 GetRequests, 42 SyntacticMatches, 5 SemanticMatches, 55 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 873 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=575, Invalid=2617, Unknown=0, NotChecked=0, Total=3192 [2022-04-07 16:42:20,516 INFO L913 BasicCegarLoop]: 16 mSDtfsCounter, 152 mSDsluCounter, 71 mSDsCounter, 0 mSdLazyCounter, 528 mSolverCounterSat, 127 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 152 SdHoareTripleChecker+Valid, 87 SdHoareTripleChecker+Invalid, 772 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 127 IncrementalHoareTripleChecker+Valid, 528 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 117 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2022-04-07 16:42:20,517 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [152 Valid, 87 Invalid, 772 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [127 Valid, 528 Invalid, 0 Unknown, 117 Unchecked, 0.7s Time] [2022-04-07 16:42:20,517 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states. [2022-04-07 16:42:20,529 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 50. [2022-04-07 16:42:20,529 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 16:42:20,530 INFO L82 GeneralOperation]: Start isEquivalent. First operand 87 states. Second operand has 50 states, 42 states have (on average 1.2380952380952381) internal successors, (52), 43 states have internal predecessors, (52), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 16:42:20,530 INFO L74 IsIncluded]: Start isIncluded. First operand 87 states. Second operand has 50 states, 42 states have (on average 1.2380952380952381) internal successors, (52), 43 states have internal predecessors, (52), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 16:42:20,530 INFO L87 Difference]: Start difference. First operand 87 states. Second operand has 50 states, 42 states have (on average 1.2380952380952381) internal successors, (52), 43 states have internal predecessors, (52), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 16:42:20,534 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 16:42:20,534 INFO L93 Difference]: Finished difference Result 87 states and 108 transitions. [2022-04-07 16:42:20,534 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 108 transitions. [2022-04-07 16:42:20,536 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 16:42:20,536 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 16:42:20,537 INFO L74 IsIncluded]: Start isIncluded. First operand has 50 states, 42 states have (on average 1.2380952380952381) internal successors, (52), 43 states have internal predecessors, (52), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 87 states. [2022-04-07 16:42:20,537 INFO L87 Difference]: Start difference. First operand has 50 states, 42 states have (on average 1.2380952380952381) internal successors, (52), 43 states have internal predecessors, (52), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 87 states. [2022-04-07 16:42:20,540 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 16:42:20,540 INFO L93 Difference]: Finished difference Result 87 states and 108 transitions. [2022-04-07 16:42:20,540 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 108 transitions. [2022-04-07 16:42:20,543 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 16:42:20,543 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 16:42:20,543 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 16:42:20,543 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 16:42:20,543 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50 states, 42 states have (on average 1.2380952380952381) internal successors, (52), 43 states have internal predecessors, (52), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 16:42:20,545 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 59 transitions. [2022-04-07 16:42:20,545 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 59 transitions. Word has length 25 [2022-04-07 16:42:20,546 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 16:42:20,546 INFO L478 AbstractCegarLoop]: Abstraction has 50 states and 59 transitions. [2022-04-07 16:42:20,546 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 29 states, 28 states have (on average 1.6785714285714286) internal successors, (47), 26 states have internal predecessors, (47), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:42:20,546 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 59 transitions. [2022-04-07 16:42:20,547 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2022-04-07 16:42:20,547 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 16:42:20,547 INFO L499 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 16:42:20,564 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2022-04-07 16:42:20,763 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4,4 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 16:42:20,764 INFO L403 AbstractCegarLoop]: === Iteration 6 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 16:42:20,764 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 16:42:20,764 INFO L85 PathProgramCache]: Analyzing trace with hash -765262082, now seen corresponding path program 1 times [2022-04-07 16:42:20,764 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 16:42:20,764 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [32805092] [2022-04-07 16:42:20,764 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 16:42:20,764 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 16:42:20,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 16:42:21,232 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 16:42:21,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 16:42:21,238 INFO L290 TraceCheckUtils]: 0: Hoare triple {1379#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1358#true} is VALID [2022-04-07 16:42:21,238 INFO L290 TraceCheckUtils]: 1: Hoare triple {1358#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1358#true} is VALID [2022-04-07 16:42:21,238 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1358#true} {1358#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1358#true} is VALID [2022-04-07 16:42:21,239 INFO L272 TraceCheckUtils]: 0: Hoare triple {1358#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1379#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 16:42:21,239 INFO L290 TraceCheckUtils]: 1: Hoare triple {1379#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1358#true} is VALID [2022-04-07 16:42:21,239 INFO L290 TraceCheckUtils]: 2: Hoare triple {1358#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1358#true} is VALID [2022-04-07 16:42:21,239 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1358#true} {1358#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1358#true} is VALID [2022-04-07 16:42:21,239 INFO L272 TraceCheckUtils]: 4: Hoare triple {1358#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1358#true} is VALID [2022-04-07 16:42:21,240 INFO L290 TraceCheckUtils]: 5: Hoare triple {1358#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (= (store |v_#length_2| |v_main_~#v~0.base_2| (* 4 (let ((.cse0 (mod v_main_~SIZE~0_2 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))))) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {1363#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-07 16:42:21,240 INFO L290 TraceCheckUtils]: 6: Hoare triple {1363#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1363#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-07 16:42:21,241 INFO L290 TraceCheckUtils]: 7: Hoare triple {1363#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1364#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 16:42:21,241 INFO L290 TraceCheckUtils]: 8: Hoare triple {1364#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1364#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 16:42:21,241 INFO L290 TraceCheckUtils]: 9: Hoare triple {1364#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1365#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 16:42:21,242 INFO L290 TraceCheckUtils]: 10: Hoare triple {1365#(= |main_~#v~0.offset| 0)} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {1365#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 16:42:21,242 INFO L290 TraceCheckUtils]: 11: Hoare triple {1365#(= |main_~#v~0.offset| 0)} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {1364#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 16:42:21,243 INFO L290 TraceCheckUtils]: 12: Hoare triple {1364#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {1366#(and (= |main_~#v~0.offset| 0) (or (<= (+ main_~i~0 1) 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:42:21,245 INFO L290 TraceCheckUtils]: 13: Hoare triple {1366#(and (= |main_~#v~0.offset| 0) (or (<= (+ main_~i~0 1) 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1367#(or (not |main_#t~short10|) (and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:42:21,245 INFO L290 TraceCheckUtils]: 14: Hoare triple {1367#(or (not |main_#t~short10|) (and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1368#(and (= |main_~#v~0.offset| 0) (or (not |main_#t~short10|) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))))) (= 0 (* main_~i~0 4)))} is VALID [2022-04-07 16:42:21,246 INFO L290 TraceCheckUtils]: 15: Hoare triple {1368#(and (= |main_~#v~0.offset| 0) (or (not |main_#t~short10|) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))))) (= 0 (* main_~i~0 4)))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1369#(and (= |main_~#v~0.offset| 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 0 (* main_~i~0 4)))} is VALID [2022-04-07 16:42:21,246 INFO L290 TraceCheckUtils]: 16: Hoare triple {1369#(and (= |main_~#v~0.offset| 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 0 (* main_~i~0 4)))} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {1370#(and (= |main_~#v~0.offset| 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)))) (= 0 (* main_~i~0 4)))} is VALID [2022-04-07 16:42:21,247 INFO L290 TraceCheckUtils]: 17: Hoare triple {1370#(and (= |main_~#v~0.offset| 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)))) (= 0 (* main_~i~0 4)))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {1371#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ main_~i~0 1)))} is VALID [2022-04-07 16:42:21,247 INFO L290 TraceCheckUtils]: 18: Hoare triple {1371#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ main_~i~0 1)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1372#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (or (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (and (<= 0 (+ main_~i~0 1)) |main_#t~short10|)))} is VALID [2022-04-07 16:42:21,248 INFO L290 TraceCheckUtils]: 19: Hoare triple {1372#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (or (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (and (<= 0 (+ main_~i~0 1)) |main_#t~short10|)))} [119] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {1373#(and (= |main_~#v~0.offset| 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= 0 (+ main_~i~0 1)))} is VALID [2022-04-07 16:42:21,248 INFO L290 TraceCheckUtils]: 20: Hoare triple {1373#(and (= |main_~#v~0.offset| 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= 0 (+ main_~i~0 1)))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1373#(and (= |main_~#v~0.offset| 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= 0 (+ main_~i~0 1)))} is VALID [2022-04-07 16:42:21,251 INFO L290 TraceCheckUtils]: 21: Hoare triple {1373#(and (= |main_~#v~0.offset| 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= 0 (+ main_~i~0 1)))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {1374#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:42:21,253 INFO L290 TraceCheckUtils]: 22: Hoare triple {1374#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {1374#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:42:21,254 INFO L290 TraceCheckUtils]: 23: Hoare triple {1374#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {1374#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:42:21,255 INFO L290 TraceCheckUtils]: 24: Hoare triple {1374#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {1375#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-07 16:42:21,256 INFO L290 TraceCheckUtils]: 25: Hoare triple {1375#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {1376#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} is VALID [2022-04-07 16:42:21,256 INFO L272 TraceCheckUtils]: 26: Hoare triple {1376#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {1377#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-07 16:42:21,257 INFO L290 TraceCheckUtils]: 27: Hoare triple {1377#(not (= |__VERIFIER_assert_#in~cond| 0))} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1378#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-07 16:42:21,257 INFO L290 TraceCheckUtils]: 28: Hoare triple {1378#(not (= __VERIFIER_assert_~cond 0))} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1359#false} is VALID [2022-04-07 16:42:21,257 INFO L290 TraceCheckUtils]: 29: Hoare triple {1359#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1359#false} is VALID [2022-04-07 16:42:21,257 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 16:42:21,257 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 16:42:21,258 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [32805092] [2022-04-07 16:42:21,258 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [32805092] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 16:42:21,258 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1831291584] [2022-04-07 16:42:21,258 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 16:42:21,258 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 16:42:21,258 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 16:42:21,260 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 16:42:21,289 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2022-04-07 16:42:21,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 16:42:21,329 INFO L263 TraceCheckSpWp]: Trace formula consists of 124 conjuncts, 23 conjunts are in the unsatisfiable core [2022-04-07 16:42:21,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 16:42:21,343 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 16:42:21,613 INFO L356 Elim1Store]: treesize reduction 39, result has 22.0 percent of original size [2022-04-07 16:42:21,614 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 30 [2022-04-07 16:42:22,365 INFO L356 Elim1Store]: treesize reduction 108, result has 10.0 percent of original size [2022-04-07 16:42:22,366 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 48 treesize of output 31 [2022-04-07 16:42:23,458 INFO L356 Elim1Store]: treesize reduction 78, result has 8.2 percent of original size [2022-04-07 16:42:23,458 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 38 treesize of output 16 [2022-04-07 16:42:23,618 INFO L272 TraceCheckUtils]: 0: Hoare triple {1358#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1358#true} is VALID [2022-04-07 16:42:23,618 INFO L290 TraceCheckUtils]: 1: Hoare triple {1358#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1358#true} is VALID [2022-04-07 16:42:23,619 INFO L290 TraceCheckUtils]: 2: Hoare triple {1358#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1358#true} is VALID [2022-04-07 16:42:23,619 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1358#true} {1358#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1358#true} is VALID [2022-04-07 16:42:23,619 INFO L272 TraceCheckUtils]: 4: Hoare triple {1358#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1358#true} is VALID [2022-04-07 16:42:23,619 INFO L290 TraceCheckUtils]: 5: Hoare triple {1358#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (= (store |v_#length_2| |v_main_~#v~0.base_2| (* 4 (let ((.cse0 (mod v_main_~SIZE~0_2 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))))) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {1358#true} is VALID [2022-04-07 16:42:23,619 INFO L290 TraceCheckUtils]: 6: Hoare triple {1358#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1358#true} is VALID [2022-04-07 16:42:23,619 INFO L290 TraceCheckUtils]: 7: Hoare triple {1358#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1358#true} is VALID [2022-04-07 16:42:23,619 INFO L290 TraceCheckUtils]: 8: Hoare triple {1358#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1358#true} is VALID [2022-04-07 16:42:23,619 INFO L290 TraceCheckUtils]: 9: Hoare triple {1358#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1358#true} is VALID [2022-04-07 16:42:23,620 INFO L290 TraceCheckUtils]: 10: Hoare triple {1358#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {1358#true} is VALID [2022-04-07 16:42:23,620 INFO L290 TraceCheckUtils]: 11: Hoare triple {1358#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {1416#(<= main_~j~0 1)} is VALID [2022-04-07 16:42:23,621 INFO L290 TraceCheckUtils]: 12: Hoare triple {1416#(<= main_~j~0 1)} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {1420#(<= main_~i~0 0)} is VALID [2022-04-07 16:42:23,621 INFO L290 TraceCheckUtils]: 13: Hoare triple {1420#(<= main_~i~0 0)} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1424#(and (<= main_~i~0 0) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} is VALID [2022-04-07 16:42:23,622 INFO L290 TraceCheckUtils]: 14: Hoare triple {1424#(and (<= main_~i~0 0) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1428#(and (<= main_~i~0 0) (or (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (not |main_#t~short10|)) (<= 0 main_~i~0))} is VALID [2022-04-07 16:42:23,622 INFO L290 TraceCheckUtils]: 15: Hoare triple {1428#(and (<= main_~i~0 0) (or (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (not |main_#t~short10|)) (<= 0 main_~i~0))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1432#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= main_~i~0 0) (<= 0 main_~i~0))} is VALID [2022-04-07 16:42:23,623 INFO L290 TraceCheckUtils]: 16: Hoare triple {1432#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= main_~i~0 0) (<= 0 main_~i~0))} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {1436#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= main_~i~0 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)))) (<= 0 main_~i~0))} is VALID [2022-04-07 16:42:23,626 INFO L290 TraceCheckUtils]: 17: Hoare triple {1436#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= main_~i~0 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)))) (<= 0 main_~i~0))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {1440#(exists ((v_main_~i~0_13 Int)) (and (<= v_main_~i~0_13 (+ main_~i~0 1)) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_13 4)))) (<= v_main_~i~0_13 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_13 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_13 4) 4))) (<= 0 v_main_~i~0_13)))} is VALID [2022-04-07 16:42:23,627 INFO L290 TraceCheckUtils]: 18: Hoare triple {1440#(exists ((v_main_~i~0_13 Int)) (and (<= v_main_~i~0_13 (+ main_~i~0 1)) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_13 4)))) (<= v_main_~i~0_13 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_13 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_13 4) 4))) (<= 0 v_main_~i~0_13)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1444#(and (exists ((v_main_~i~0_13 Int)) (and (<= v_main_~i~0_13 (+ main_~i~0 1)) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_13 4)))) (<= v_main_~i~0_13 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_13 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_13 4) 4))) (<= 0 v_main_~i~0_13))) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} is VALID [2022-04-07 16:42:23,628 INFO L290 TraceCheckUtils]: 19: Hoare triple {1444#(and (exists ((v_main_~i~0_13 Int)) (and (<= v_main_~i~0_13 (+ main_~i~0 1)) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_13 4)))) (<= v_main_~i~0_13 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_13 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_13 4) 4))) (<= 0 v_main_~i~0_13))) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} [119] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {1448#(and (< main_~i~0 0) (exists ((v_main_~i~0_13 Int)) (and (<= v_main_~i~0_13 (+ main_~i~0 1)) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_13 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_13 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_13 4) 4))) (<= 0 v_main_~i~0_13))))} is VALID [2022-04-07 16:42:23,629 INFO L290 TraceCheckUtils]: 20: Hoare triple {1448#(and (< main_~i~0 0) (exists ((v_main_~i~0_13 Int)) (and (<= v_main_~i~0_13 (+ main_~i~0 1)) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_13 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_13 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_13 4) 4))) (<= 0 v_main_~i~0_13))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1448#(and (< main_~i~0 0) (exists ((v_main_~i~0_13 Int)) (and (<= v_main_~i~0_13 (+ main_~i~0 1)) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_13 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_13 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_13 4) 4))) (<= 0 v_main_~i~0_13))))} is VALID [2022-04-07 16:42:23,632 INFO L290 TraceCheckUtils]: 21: Hoare triple {1448#(and (< main_~i~0 0) (exists ((v_main_~i~0_13 Int)) (and (<= v_main_~i~0_13 (+ main_~i~0 1)) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_13 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_13 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_13 4) 4))) (<= 0 v_main_~i~0_13))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {1455#(exists ((main_~i~0 Int) (v_main_~i~0_13 Int)) (and (<= v_main_~i~0_13 (+ main_~i~0 1)) (< main_~i~0 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_13 4) 4))) (<= 0 v_main_~i~0_13)))} is VALID [2022-04-07 16:42:23,633 INFO L290 TraceCheckUtils]: 22: Hoare triple {1455#(exists ((main_~i~0 Int) (v_main_~i~0_13 Int)) (and (<= v_main_~i~0_13 (+ main_~i~0 1)) (< main_~i~0 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_13 4) 4))) (<= 0 v_main_~i~0_13)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {1455#(exists ((main_~i~0 Int) (v_main_~i~0_13 Int)) (and (<= v_main_~i~0_13 (+ main_~i~0 1)) (< main_~i~0 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_13 4) 4))) (<= 0 v_main_~i~0_13)))} is VALID [2022-04-07 16:42:23,634 INFO L290 TraceCheckUtils]: 23: Hoare triple {1455#(exists ((main_~i~0 Int) (v_main_~i~0_13 Int)) (and (<= v_main_~i~0_13 (+ main_~i~0 1)) (< main_~i~0 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_13 4) 4))) (<= 0 v_main_~i~0_13)))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {1455#(exists ((main_~i~0 Int) (v_main_~i~0_13 Int)) (and (<= v_main_~i~0_13 (+ main_~i~0 1)) (< main_~i~0 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_13 4) 4))) (<= 0 v_main_~i~0_13)))} is VALID [2022-04-07 16:42:23,635 INFO L290 TraceCheckUtils]: 24: Hoare triple {1455#(exists ((main_~i~0 Int) (v_main_~i~0_13 Int)) (and (<= v_main_~i~0_13 (+ main_~i~0 1)) (< main_~i~0 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_13 4) 4))) (<= 0 v_main_~i~0_13)))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {1465#(and (exists ((main_~i~0 Int) (v_main_~i~0_13 Int)) (and (<= v_main_~i~0_13 (+ main_~i~0 1)) (< main_~i~0 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_13 4) 4))) (<= 0 v_main_~i~0_13))) (= main_~k~0 1))} is VALID [2022-04-07 16:42:23,636 INFO L290 TraceCheckUtils]: 25: Hoare triple {1465#(and (exists ((main_~i~0 Int) (v_main_~i~0_13 Int)) (and (<= v_main_~i~0_13 (+ main_~i~0 1)) (< main_~i~0 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_13 4) 4))) (<= 0 v_main_~i~0_13))) (= main_~k~0 1))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {1376#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} is VALID [2022-04-07 16:42:23,637 INFO L272 TraceCheckUtils]: 26: Hoare triple {1376#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {1472#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 16:42:23,637 INFO L290 TraceCheckUtils]: 27: Hoare triple {1472#(<= 1 |__VERIFIER_assert_#in~cond|)} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1476#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 16:42:23,637 INFO L290 TraceCheckUtils]: 28: Hoare triple {1476#(<= 1 __VERIFIER_assert_~cond)} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1359#false} is VALID [2022-04-07 16:42:23,637 INFO L290 TraceCheckUtils]: 29: Hoare triple {1359#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1359#false} is VALID [2022-04-07 16:42:23,638 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-07 16:42:23,638 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-07 16:42:25,537 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 69 treesize of output 61 [2022-04-07 16:42:25,607 INFO L356 Elim1Store]: treesize reduction 36, result has 2.7 percent of original size [2022-04-07 16:42:25,608 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 771 treesize of output 711 [2022-04-07 16:42:28,050 INFO L290 TraceCheckUtils]: 29: Hoare triple {1359#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1359#false} is VALID [2022-04-07 16:42:28,051 INFO L290 TraceCheckUtils]: 28: Hoare triple {1476#(<= 1 __VERIFIER_assert_~cond)} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1359#false} is VALID [2022-04-07 16:42:28,051 INFO L290 TraceCheckUtils]: 27: Hoare triple {1472#(<= 1 |__VERIFIER_assert_#in~cond|)} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1476#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 16:42:28,052 INFO L272 TraceCheckUtils]: 26: Hoare triple {1492#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {1472#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 16:42:28,052 INFO L290 TraceCheckUtils]: 25: Hoare triple {1496#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {1492#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-07 16:42:28,053 INFO L290 TraceCheckUtils]: 24: Hoare triple {1500#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {1496#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} is VALID [2022-04-07 16:42:28,053 INFO L290 TraceCheckUtils]: 23: Hoare triple {1500#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {1500#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-07 16:42:28,053 INFO L290 TraceCheckUtils]: 22: Hoare triple {1500#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {1500#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-07 16:42:28,054 INFO L290 TraceCheckUtils]: 21: Hoare triple {1510#(forall ((v_ArrVal_66 Int)) (or (not (<= v_ArrVal_66 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_66) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_66) (+ |main_~#v~0.offset| 4)))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {1500#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-07 16:42:28,055 INFO L290 TraceCheckUtils]: 20: Hoare triple {1510#(forall ((v_ArrVal_66 Int)) (or (not (<= v_ArrVal_66 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_66) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_66) (+ |main_~#v~0.offset| 4)))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1510#(forall ((v_ArrVal_66 Int)) (or (not (<= v_ArrVal_66 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_66) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_66) (+ |main_~#v~0.offset| 4)))))} is VALID [2022-04-07 16:42:28,055 INFO L290 TraceCheckUtils]: 19: Hoare triple {1517#(or (forall ((v_ArrVal_66 Int)) (or (not (<= v_ArrVal_66 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_66) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_66) (+ |main_~#v~0.offset| 4))))) |main_#t~short10|)} [119] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {1510#(forall ((v_ArrVal_66 Int)) (or (not (<= v_ArrVal_66 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_66) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_66) (+ |main_~#v~0.offset| 4)))))} is VALID [2022-04-07 16:42:28,056 INFO L290 TraceCheckUtils]: 18: Hoare triple {1521#(or (forall ((v_ArrVal_66 Int)) (or (not (<= v_ArrVal_66 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_66) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_66) (+ |main_~#v~0.offset| 4))))) (<= 0 main_~i~0))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1517#(or (forall ((v_ArrVal_66 Int)) (or (not (<= v_ArrVal_66 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_66) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_66) (+ |main_~#v~0.offset| 4))))) |main_#t~short10|)} is VALID [2022-04-07 16:42:28,057 INFO L290 TraceCheckUtils]: 17: Hoare triple {1525#(forall ((v_main_~i~0_14 Int)) (or (forall ((v_ArrVal_66 Int)) (or (not (<= v_ArrVal_66 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ (* v_main_~i~0_14 4) |main_~#v~0.offset| 4) v_ArrVal_66) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ (* v_main_~i~0_14 4) |main_~#v~0.offset| 4) v_ArrVal_66) (+ |main_~#v~0.offset| 4))))) (not (<= main_~i~0 (+ v_main_~i~0_14 1))) (<= 0 v_main_~i~0_14)))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {1521#(or (forall ((v_ArrVal_66 Int)) (or (not (<= v_ArrVal_66 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_66) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_66) (+ |main_~#v~0.offset| 4))))) (<= 0 main_~i~0))} is VALID [2022-04-07 16:42:28,059 INFO L290 TraceCheckUtils]: 16: Hoare triple {1529#(forall ((v_main_~i~0_14 Int) (v_ArrVal_64 Int) (v_ArrVal_66 Int)) (or (not (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) v_ArrVal_64)) (not (<= v_ArrVal_66 main_~key~0)) (not (<= main_~i~0 (+ v_main_~i~0_14 1))) (<= 0 v_main_~i~0_14) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_64) (+ (* v_main_~i~0_14 4) |main_~#v~0.offset| 4) v_ArrVal_66) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_64) (+ (* v_main_~i~0_14 4) |main_~#v~0.offset| 4) v_ArrVal_66) (+ |main_~#v~0.offset| 4)))))} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {1525#(forall ((v_main_~i~0_14 Int)) (or (forall ((v_ArrVal_66 Int)) (or (not (<= v_ArrVal_66 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ (* v_main_~i~0_14 4) |main_~#v~0.offset| 4) v_ArrVal_66) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ (* v_main_~i~0_14 4) |main_~#v~0.offset| 4) v_ArrVal_66) (+ |main_~#v~0.offset| 4))))) (not (<= main_~i~0 (+ v_main_~i~0_14 1))) (<= 0 v_main_~i~0_14)))} is VALID [2022-04-07 16:42:28,060 INFO L290 TraceCheckUtils]: 15: Hoare triple {1533#(or (not |main_#t~short10|) (forall ((v_main_~i~0_14 Int) (v_ArrVal_64 Int) (v_ArrVal_66 Int)) (or (not (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) v_ArrVal_64)) (not (<= v_ArrVal_66 main_~key~0)) (not (<= main_~i~0 (+ v_main_~i~0_14 1))) (<= 0 v_main_~i~0_14) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_64) (+ (* v_main_~i~0_14 4) |main_~#v~0.offset| 4) v_ArrVal_66) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_64) (+ (* v_main_~i~0_14 4) |main_~#v~0.offset| 4) v_ArrVal_66) (+ |main_~#v~0.offset| 4))))))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1529#(forall ((v_main_~i~0_14 Int) (v_ArrVal_64 Int) (v_ArrVal_66 Int)) (or (not (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) v_ArrVal_64)) (not (<= v_ArrVal_66 main_~key~0)) (not (<= main_~i~0 (+ v_main_~i~0_14 1))) (<= 0 v_main_~i~0_14) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_64) (+ (* v_main_~i~0_14 4) |main_~#v~0.offset| 4) v_ArrVal_66) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_64) (+ (* v_main_~i~0_14 4) |main_~#v~0.offset| 4) v_ArrVal_66) (+ |main_~#v~0.offset| 4)))))} is VALID [2022-04-07 16:42:28,061 INFO L290 TraceCheckUtils]: 14: Hoare triple {1537#(or (not |main_#t~short10|) (<= 1 main_~i~0) (= 0 (* main_~i~0 4)))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1533#(or (not |main_#t~short10|) (forall ((v_main_~i~0_14 Int) (v_ArrVal_64 Int) (v_ArrVal_66 Int)) (or (not (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) v_ArrVal_64)) (not (<= v_ArrVal_66 main_~key~0)) (not (<= main_~i~0 (+ v_main_~i~0_14 1))) (<= 0 v_main_~i~0_14) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_64) (+ (* v_main_~i~0_14 4) |main_~#v~0.offset| 4) v_ArrVal_66) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_64) (+ (* v_main_~i~0_14 4) |main_~#v~0.offset| 4) v_ArrVal_66) (+ |main_~#v~0.offset| 4))))))} is VALID [2022-04-07 16:42:28,061 INFO L290 TraceCheckUtils]: 13: Hoare triple {1358#true} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1537#(or (not |main_#t~short10|) (<= 1 main_~i~0) (= 0 (* main_~i~0 4)))} is VALID [2022-04-07 16:42:28,061 INFO L290 TraceCheckUtils]: 12: Hoare triple {1358#true} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {1358#true} is VALID [2022-04-07 16:42:28,062 INFO L290 TraceCheckUtils]: 11: Hoare triple {1358#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {1358#true} is VALID [2022-04-07 16:42:28,062 INFO L290 TraceCheckUtils]: 10: Hoare triple {1358#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {1358#true} is VALID [2022-04-07 16:42:28,062 INFO L290 TraceCheckUtils]: 9: Hoare triple {1358#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1358#true} is VALID [2022-04-07 16:42:28,062 INFO L290 TraceCheckUtils]: 8: Hoare triple {1358#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1358#true} is VALID [2022-04-07 16:42:28,062 INFO L290 TraceCheckUtils]: 7: Hoare triple {1358#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1358#true} is VALID [2022-04-07 16:42:28,062 INFO L290 TraceCheckUtils]: 6: Hoare triple {1358#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1358#true} is VALID [2022-04-07 16:42:28,062 INFO L290 TraceCheckUtils]: 5: Hoare triple {1358#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (= (store |v_#length_2| |v_main_~#v~0.base_2| (* 4 (let ((.cse0 (mod v_main_~SIZE~0_2 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))))) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {1358#true} is VALID [2022-04-07 16:42:28,062 INFO L272 TraceCheckUtils]: 4: Hoare triple {1358#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1358#true} is VALID [2022-04-07 16:42:28,062 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1358#true} {1358#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1358#true} is VALID [2022-04-07 16:42:28,063 INFO L290 TraceCheckUtils]: 2: Hoare triple {1358#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1358#true} is VALID [2022-04-07 16:42:28,063 INFO L290 TraceCheckUtils]: 1: Hoare triple {1358#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1358#true} is VALID [2022-04-07 16:42:28,063 INFO L272 TraceCheckUtils]: 0: Hoare triple {1358#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1358#true} is VALID [2022-04-07 16:42:28,063 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-07 16:42:28,063 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1831291584] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-07 16:42:28,063 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-07 16:42:28,063 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 16, 14] total 42 [2022-04-07 16:42:28,063 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1121680628] [2022-04-07 16:42:28,064 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-07 16:42:28,064 INFO L78 Accepts]: Start accepts. Automaton has has 42 states, 40 states have (on average 1.575) internal successors, (63), 39 states have internal predecessors, (63), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 30 [2022-04-07 16:42:28,065 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 16:42:28,066 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 42 states, 40 states have (on average 1.575) internal successors, (63), 39 states have internal predecessors, (63), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:42:28,133 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 70 edges. 70 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 16:42:28,134 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 42 states [2022-04-07 16:42:28,134 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 16:42:28,134 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2022-04-07 16:42:28,135 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=188, Invalid=1532, Unknown=2, NotChecked=0, Total=1722 [2022-04-07 16:42:28,135 INFO L87 Difference]: Start difference. First operand 50 states and 59 transitions. Second operand has 42 states, 40 states have (on average 1.575) internal successors, (63), 39 states have internal predecessors, (63), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:42:41,923 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 16:42:41,923 INFO L93 Difference]: Finished difference Result 132 states and 165 transitions. [2022-04-07 16:42:41,923 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2022-04-07 16:42:41,923 INFO L78 Accepts]: Start accepts. Automaton has has 42 states, 40 states have (on average 1.575) internal successors, (63), 39 states have internal predecessors, (63), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 30 [2022-04-07 16:42:41,923 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 16:42:41,924 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42 states, 40 states have (on average 1.575) internal successors, (63), 39 states have internal predecessors, (63), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:42:41,926 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 138 transitions. [2022-04-07 16:42:41,927 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42 states, 40 states have (on average 1.575) internal successors, (63), 39 states have internal predecessors, (63), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:42:41,929 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 138 transitions. [2022-04-07 16:42:41,929 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 52 states and 138 transitions. [2022-04-07 16:42:42,070 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 138 edges. 138 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 16:42:42,072 INFO L225 Difference]: With dead ends: 132 [2022-04-07 16:42:42,072 INFO L226 Difference]: Without dead ends: 132 [2022-04-07 16:42:42,074 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 131 GetRequests, 44 SyntacticMatches, 3 SemanticMatches, 84 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2296 ImplicationChecksByTransitivity, 12.6s TimeCoverageRelationStatistics Valid=757, Invalid=6551, Unknown=2, NotChecked=0, Total=7310 [2022-04-07 16:42:42,075 INFO L913 BasicCegarLoop]: 35 mSDtfsCounter, 115 mSDsluCounter, 171 mSDsCounter, 0 mSdLazyCounter, 838 mSolverCounterSat, 77 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 116 SdHoareTripleChecker+Valid, 206 SdHoareTripleChecker+Invalid, 1473 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 77 IncrementalHoareTripleChecker+Valid, 838 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 558 IncrementalHoareTripleChecker+Unchecked, 1.0s IncrementalHoareTripleChecker+Time [2022-04-07 16:42:42,075 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [116 Valid, 206 Invalid, 1473 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [77 Valid, 838 Invalid, 0 Unknown, 558 Unchecked, 1.0s Time] [2022-04-07 16:42:42,075 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states. [2022-04-07 16:42:42,078 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 58. [2022-04-07 16:42:42,078 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 16:42:42,079 INFO L82 GeneralOperation]: Start isEquivalent. First operand 132 states. Second operand has 58 states, 50 states have (on average 1.26) internal successors, (63), 51 states have internal predecessors, (63), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 16:42:42,079 INFO L74 IsIncluded]: Start isIncluded. First operand 132 states. Second operand has 58 states, 50 states have (on average 1.26) internal successors, (63), 51 states have internal predecessors, (63), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 16:42:42,079 INFO L87 Difference]: Start difference. First operand 132 states. Second operand has 58 states, 50 states have (on average 1.26) internal successors, (63), 51 states have internal predecessors, (63), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 16:42:42,082 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 16:42:42,083 INFO L93 Difference]: Finished difference Result 132 states and 165 transitions. [2022-04-07 16:42:42,083 INFO L276 IsEmpty]: Start isEmpty. Operand 132 states and 165 transitions. [2022-04-07 16:42:42,083 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 16:42:42,083 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 16:42:42,083 INFO L74 IsIncluded]: Start isIncluded. First operand has 58 states, 50 states have (on average 1.26) internal successors, (63), 51 states have internal predecessors, (63), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 132 states. [2022-04-07 16:42:42,083 INFO L87 Difference]: Start difference. First operand has 58 states, 50 states have (on average 1.26) internal successors, (63), 51 states have internal predecessors, (63), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 132 states. [2022-04-07 16:42:42,087 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 16:42:42,087 INFO L93 Difference]: Finished difference Result 132 states and 165 transitions. [2022-04-07 16:42:42,087 INFO L276 IsEmpty]: Start isEmpty. Operand 132 states and 165 transitions. [2022-04-07 16:42:42,087 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 16:42:42,087 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 16:42:42,088 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 16:42:42,088 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 16:42:42,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 58 states, 50 states have (on average 1.26) internal successors, (63), 51 states have internal predecessors, (63), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 16:42:42,089 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 70 transitions. [2022-04-07 16:42:42,089 INFO L78 Accepts]: Start accepts. Automaton has 58 states and 70 transitions. Word has length 30 [2022-04-07 16:42:42,089 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 16:42:42,089 INFO L478 AbstractCegarLoop]: Abstraction has 58 states and 70 transitions. [2022-04-07 16:42:42,089 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 42 states, 40 states have (on average 1.575) internal successors, (63), 39 states have internal predecessors, (63), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:42:42,090 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states and 70 transitions. [2022-04-07 16:42:42,090 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2022-04-07 16:42:42,090 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 16:42:42,090 INFO L499 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 16:42:42,119 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Ended with exit code 0 [2022-04-07 16:42:42,307 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5,5 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 16:42:42,308 INFO L403 AbstractCegarLoop]: === Iteration 7 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 16:42:42,308 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 16:42:42,308 INFO L85 PathProgramCache]: Analyzing trace with hash -847240814, now seen corresponding path program 3 times [2022-04-07 16:42:42,308 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 16:42:42,308 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [390985486] [2022-04-07 16:42:42,308 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 16:42:42,308 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 16:42:42,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 16:42:42,468 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 16:42:42,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 16:42:42,472 INFO L290 TraceCheckUtils]: 0: Hoare triple {2141#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2130#true} is VALID [2022-04-07 16:42:42,473 INFO L290 TraceCheckUtils]: 1: Hoare triple {2130#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2130#true} is VALID [2022-04-07 16:42:42,473 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {2130#true} {2130#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2130#true} is VALID [2022-04-07 16:42:42,473 INFO L272 TraceCheckUtils]: 0: Hoare triple {2130#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2141#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 16:42:42,473 INFO L290 TraceCheckUtils]: 1: Hoare triple {2141#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2130#true} is VALID [2022-04-07 16:42:42,473 INFO L290 TraceCheckUtils]: 2: Hoare triple {2130#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2130#true} is VALID [2022-04-07 16:42:42,474 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2130#true} {2130#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2130#true} is VALID [2022-04-07 16:42:42,474 INFO L272 TraceCheckUtils]: 4: Hoare triple {2130#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2130#true} is VALID [2022-04-07 16:42:42,474 INFO L290 TraceCheckUtils]: 5: Hoare triple {2130#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (= (store |v_#length_2| |v_main_~#v~0.base_2| (* 4 (let ((.cse0 (mod v_main_~SIZE~0_2 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))))) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {2135#(= main_~j~0 0)} is VALID [2022-04-07 16:42:42,474 INFO L290 TraceCheckUtils]: 6: Hoare triple {2135#(= main_~j~0 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2135#(= main_~j~0 0)} is VALID [2022-04-07 16:42:42,475 INFO L290 TraceCheckUtils]: 7: Hoare triple {2135#(= main_~j~0 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2136#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 16:42:42,475 INFO L290 TraceCheckUtils]: 8: Hoare triple {2136#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2136#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 16:42:42,476 INFO L290 TraceCheckUtils]: 9: Hoare triple {2136#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2137#(and (<= main_~j~0 2) (not (<= (+ (div main_~j~0 4294967296) 1) 0)))} is VALID [2022-04-07 16:42:42,477 INFO L290 TraceCheckUtils]: 10: Hoare triple {2137#(and (<= main_~j~0 2) (not (<= (+ (div main_~j~0 4294967296) 1) 0)))} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {2138#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-07 16:42:42,477 INFO L290 TraceCheckUtils]: 11: Hoare triple {2138#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {2139#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-07 16:42:42,478 INFO L290 TraceCheckUtils]: 12: Hoare triple {2139#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {2139#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-07 16:42:42,478 INFO L290 TraceCheckUtils]: 13: Hoare triple {2139#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2139#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-07 16:42:42,479 INFO L290 TraceCheckUtils]: 14: Hoare triple {2139#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2139#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-07 16:42:42,479 INFO L290 TraceCheckUtils]: 15: Hoare triple {2139#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2139#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-07 16:42:42,479 INFO L290 TraceCheckUtils]: 16: Hoare triple {2139#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {2139#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-07 16:42:42,480 INFO L290 TraceCheckUtils]: 17: Hoare triple {2139#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {2140#(<= (+ main_~SIZE~0 (* 4294967296 (div main_~j~0 4294967296))) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-07 16:42:42,481 INFO L290 TraceCheckUtils]: 18: Hoare triple {2140#(<= (+ main_~SIZE~0 (* 4294967296 (div main_~j~0 4294967296))) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296)))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {2131#false} is VALID [2022-04-07 16:42:42,481 INFO L290 TraceCheckUtils]: 19: Hoare triple {2131#false} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2131#false} is VALID [2022-04-07 16:42:42,481 INFO L290 TraceCheckUtils]: 20: Hoare triple {2131#false} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2131#false} is VALID [2022-04-07 16:42:42,481 INFO L290 TraceCheckUtils]: 21: Hoare triple {2131#false} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2131#false} is VALID [2022-04-07 16:42:42,481 INFO L290 TraceCheckUtils]: 22: Hoare triple {2131#false} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {2131#false} is VALID [2022-04-07 16:42:42,481 INFO L290 TraceCheckUtils]: 23: Hoare triple {2131#false} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {2131#false} is VALID [2022-04-07 16:42:42,481 INFO L290 TraceCheckUtils]: 24: Hoare triple {2131#false} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {2131#false} is VALID [2022-04-07 16:42:42,481 INFO L290 TraceCheckUtils]: 25: Hoare triple {2131#false} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {2131#false} is VALID [2022-04-07 16:42:42,481 INFO L290 TraceCheckUtils]: 26: Hoare triple {2131#false} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {2131#false} is VALID [2022-04-07 16:42:42,481 INFO L272 TraceCheckUtils]: 27: Hoare triple {2131#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {2131#false} is VALID [2022-04-07 16:42:42,482 INFO L290 TraceCheckUtils]: 28: Hoare triple {2131#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2131#false} is VALID [2022-04-07 16:42:42,482 INFO L290 TraceCheckUtils]: 29: Hoare triple {2131#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2131#false} is VALID [2022-04-07 16:42:42,482 INFO L290 TraceCheckUtils]: 30: Hoare triple {2131#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2131#false} is VALID [2022-04-07 16:42:42,482 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 7 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 16:42:42,482 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 16:42:42,482 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [390985486] [2022-04-07 16:42:42,482 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [390985486] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 16:42:42,482 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1500185219] [2022-04-07 16:42:42,482 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-04-07 16:42:42,482 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 16:42:42,482 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 16:42:42,483 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 16:42:42,484 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2022-04-07 16:42:42,537 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2022-04-07 16:42:42,537 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-07 16:42:42,538 INFO L263 TraceCheckSpWp]: Trace formula consists of 131 conjuncts, 12 conjunts are in the unsatisfiable core [2022-04-07 16:42:42,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 16:42:42,549 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 16:42:42,964 INFO L272 TraceCheckUtils]: 0: Hoare triple {2130#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2130#true} is VALID [2022-04-07 16:42:42,965 INFO L290 TraceCheckUtils]: 1: Hoare triple {2130#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2130#true} is VALID [2022-04-07 16:42:42,965 INFO L290 TraceCheckUtils]: 2: Hoare triple {2130#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2130#true} is VALID [2022-04-07 16:42:42,965 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2130#true} {2130#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2130#true} is VALID [2022-04-07 16:42:42,965 INFO L272 TraceCheckUtils]: 4: Hoare triple {2130#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2130#true} is VALID [2022-04-07 16:42:42,965 INFO L290 TraceCheckUtils]: 5: Hoare triple {2130#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (= (store |v_#length_2| |v_main_~#v~0.base_2| (* 4 (let ((.cse0 (mod v_main_~SIZE~0_2 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))))) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {2135#(= main_~j~0 0)} is VALID [2022-04-07 16:42:42,966 INFO L290 TraceCheckUtils]: 6: Hoare triple {2135#(= main_~j~0 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2135#(= main_~j~0 0)} is VALID [2022-04-07 16:42:42,966 INFO L290 TraceCheckUtils]: 7: Hoare triple {2135#(= main_~j~0 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2136#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 16:42:42,966 INFO L290 TraceCheckUtils]: 8: Hoare triple {2136#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2136#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 16:42:42,967 INFO L290 TraceCheckUtils]: 9: Hoare triple {2136#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2172#(and (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-07 16:42:42,968 INFO L290 TraceCheckUtils]: 10: Hoare triple {2172#(and (<= main_~j~0 2) (<= 2 main_~j~0))} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {2138#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-07 16:42:42,968 INFO L290 TraceCheckUtils]: 11: Hoare triple {2138#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {2139#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-07 16:42:42,969 INFO L290 TraceCheckUtils]: 12: Hoare triple {2139#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {2139#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-07 16:42:42,969 INFO L290 TraceCheckUtils]: 13: Hoare triple {2139#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2139#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-07 16:42:42,970 INFO L290 TraceCheckUtils]: 14: Hoare triple {2139#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2139#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-07 16:42:42,970 INFO L290 TraceCheckUtils]: 15: Hoare triple {2139#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2139#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-07 16:42:42,970 INFO L290 TraceCheckUtils]: 16: Hoare triple {2139#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {2139#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-07 16:42:42,971 INFO L290 TraceCheckUtils]: 17: Hoare triple {2139#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {2197#(and (= (+ (- 2) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-07 16:42:42,971 INFO L290 TraceCheckUtils]: 18: Hoare triple {2197#(and (= (+ (- 2) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {2131#false} is VALID [2022-04-07 16:42:42,972 INFO L290 TraceCheckUtils]: 19: Hoare triple {2131#false} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2131#false} is VALID [2022-04-07 16:42:42,972 INFO L290 TraceCheckUtils]: 20: Hoare triple {2131#false} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2131#false} is VALID [2022-04-07 16:42:42,972 INFO L290 TraceCheckUtils]: 21: Hoare triple {2131#false} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2131#false} is VALID [2022-04-07 16:42:42,972 INFO L290 TraceCheckUtils]: 22: Hoare triple {2131#false} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {2131#false} is VALID [2022-04-07 16:42:42,972 INFO L290 TraceCheckUtils]: 23: Hoare triple {2131#false} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {2131#false} is VALID [2022-04-07 16:42:42,972 INFO L290 TraceCheckUtils]: 24: Hoare triple {2131#false} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {2131#false} is VALID [2022-04-07 16:42:42,972 INFO L290 TraceCheckUtils]: 25: Hoare triple {2131#false} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {2131#false} is VALID [2022-04-07 16:42:42,972 INFO L290 TraceCheckUtils]: 26: Hoare triple {2131#false} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {2131#false} is VALID [2022-04-07 16:42:42,972 INFO L272 TraceCheckUtils]: 27: Hoare triple {2131#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {2131#false} is VALID [2022-04-07 16:42:42,972 INFO L290 TraceCheckUtils]: 28: Hoare triple {2131#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2131#false} is VALID [2022-04-07 16:42:42,972 INFO L290 TraceCheckUtils]: 29: Hoare triple {2131#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2131#false} is VALID [2022-04-07 16:42:42,973 INFO L290 TraceCheckUtils]: 30: Hoare triple {2131#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2131#false} is VALID [2022-04-07 16:42:42,973 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 7 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 16:42:42,973 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-07 16:42:44,057 INFO L290 TraceCheckUtils]: 30: Hoare triple {2131#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2131#false} is VALID [2022-04-07 16:42:44,057 INFO L290 TraceCheckUtils]: 29: Hoare triple {2131#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2131#false} is VALID [2022-04-07 16:42:44,057 INFO L290 TraceCheckUtils]: 28: Hoare triple {2131#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2131#false} is VALID [2022-04-07 16:42:44,057 INFO L272 TraceCheckUtils]: 27: Hoare triple {2131#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {2131#false} is VALID [2022-04-07 16:42:44,058 INFO L290 TraceCheckUtils]: 26: Hoare triple {2131#false} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {2131#false} is VALID [2022-04-07 16:42:44,058 INFO L290 TraceCheckUtils]: 25: Hoare triple {2131#false} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {2131#false} is VALID [2022-04-07 16:42:44,058 INFO L290 TraceCheckUtils]: 24: Hoare triple {2131#false} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {2131#false} is VALID [2022-04-07 16:42:44,058 INFO L290 TraceCheckUtils]: 23: Hoare triple {2131#false} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {2131#false} is VALID [2022-04-07 16:42:44,058 INFO L290 TraceCheckUtils]: 22: Hoare triple {2131#false} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {2131#false} is VALID [2022-04-07 16:42:44,058 INFO L290 TraceCheckUtils]: 21: Hoare triple {2131#false} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2131#false} is VALID [2022-04-07 16:42:44,058 INFO L290 TraceCheckUtils]: 20: Hoare triple {2131#false} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2131#false} is VALID [2022-04-07 16:42:44,058 INFO L290 TraceCheckUtils]: 19: Hoare triple {2131#false} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2131#false} is VALID [2022-04-07 16:42:44,059 INFO L290 TraceCheckUtils]: 18: Hoare triple {2140#(<= (+ main_~SIZE~0 (* 4294967296 (div main_~j~0 4294967296))) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296)))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {2131#false} is VALID [2022-04-07 16:42:44,060 INFO L290 TraceCheckUtils]: 17: Hoare triple {2276#(<= (+ main_~SIZE~0 (* (div (+ main_~j~0 1) 4294967296) 4294967296)) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {2140#(<= (+ main_~SIZE~0 (* 4294967296 (div main_~j~0 4294967296))) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-07 16:42:44,060 INFO L290 TraceCheckUtils]: 16: Hoare triple {2276#(<= (+ main_~SIZE~0 (* (div (+ main_~j~0 1) 4294967296) 4294967296)) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {2276#(<= (+ main_~SIZE~0 (* (div (+ main_~j~0 1) 4294967296) 4294967296)) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-07 16:42:44,061 INFO L290 TraceCheckUtils]: 15: Hoare triple {2276#(<= (+ main_~SIZE~0 (* (div (+ main_~j~0 1) 4294967296) 4294967296)) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2276#(<= (+ main_~SIZE~0 (* (div (+ main_~j~0 1) 4294967296) 4294967296)) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-07 16:42:44,061 INFO L290 TraceCheckUtils]: 14: Hoare triple {2276#(<= (+ main_~SIZE~0 (* (div (+ main_~j~0 1) 4294967296) 4294967296)) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2276#(<= (+ main_~SIZE~0 (* (div (+ main_~j~0 1) 4294967296) 4294967296)) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-07 16:42:44,061 INFO L290 TraceCheckUtils]: 13: Hoare triple {2276#(<= (+ main_~SIZE~0 (* (div (+ main_~j~0 1) 4294967296) 4294967296)) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2276#(<= (+ main_~SIZE~0 (* (div (+ main_~j~0 1) 4294967296) 4294967296)) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-07 16:42:44,062 INFO L290 TraceCheckUtils]: 12: Hoare triple {2276#(<= (+ main_~SIZE~0 (* (div (+ main_~j~0 1) 4294967296) 4294967296)) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {2276#(<= (+ main_~SIZE~0 (* (div (+ main_~j~0 1) 4294967296) 4294967296)) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-07 16:42:44,062 INFO L290 TraceCheckUtils]: 11: Hoare triple {2138#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {2276#(<= (+ main_~SIZE~0 (* (div (+ main_~j~0 1) 4294967296) 4294967296)) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-07 16:42:44,063 INFO L290 TraceCheckUtils]: 10: Hoare triple {2298#(<= 0 (div (+ 2 (* (- 1) (mod main_~j~0 4294967296))) 4294967296))} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {2138#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-07 16:42:44,064 INFO L290 TraceCheckUtils]: 9: Hoare triple {2302#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) 2) 4294967296))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2298#(<= 0 (div (+ 2 (* (- 1) (mod main_~j~0 4294967296))) 4294967296))} is VALID [2022-04-07 16:42:44,064 INFO L290 TraceCheckUtils]: 8: Hoare triple {2302#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) 2) 4294967296))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2302#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) 2) 4294967296))} is VALID [2022-04-07 16:42:44,065 INFO L290 TraceCheckUtils]: 7: Hoare triple {2309#(<= 0 (div (+ 2 (* (- 1) (mod (+ main_~j~0 2) 4294967296))) 4294967296))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2302#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) 2) 4294967296))} is VALID [2022-04-07 16:42:44,065 INFO L290 TraceCheckUtils]: 6: Hoare triple {2309#(<= 0 (div (+ 2 (* (- 1) (mod (+ main_~j~0 2) 4294967296))) 4294967296))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2309#(<= 0 (div (+ 2 (* (- 1) (mod (+ main_~j~0 2) 4294967296))) 4294967296))} is VALID [2022-04-07 16:42:44,066 INFO L290 TraceCheckUtils]: 5: Hoare triple {2130#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (= (store |v_#length_2| |v_main_~#v~0.base_2| (* 4 (let ((.cse0 (mod v_main_~SIZE~0_2 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))))) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {2309#(<= 0 (div (+ 2 (* (- 1) (mod (+ main_~j~0 2) 4294967296))) 4294967296))} is VALID [2022-04-07 16:42:44,066 INFO L272 TraceCheckUtils]: 4: Hoare triple {2130#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2130#true} is VALID [2022-04-07 16:42:44,066 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2130#true} {2130#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2130#true} is VALID [2022-04-07 16:42:44,066 INFO L290 TraceCheckUtils]: 2: Hoare triple {2130#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2130#true} is VALID [2022-04-07 16:42:44,066 INFO L290 TraceCheckUtils]: 1: Hoare triple {2130#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2130#true} is VALID [2022-04-07 16:42:44,067 INFO L272 TraceCheckUtils]: 0: Hoare triple {2130#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2130#true} is VALID [2022-04-07 16:42:44,085 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 7 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 16:42:44,085 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1500185219] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-07 16:42:44,085 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-07 16:42:44,085 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 8, 8] total 15 [2022-04-07 16:42:44,085 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [340743310] [2022-04-07 16:42:44,085 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-07 16:42:44,086 INFO L78 Accepts]: Start accepts. Automaton has has 15 states, 15 states have (on average 3.0) internal successors, (45), 14 states have internal predecessors, (45), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 31 [2022-04-07 16:42:44,086 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 16:42:44,086 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 15 states, 15 states have (on average 3.0) internal successors, (45), 14 states have internal predecessors, (45), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:42:44,127 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 50 edges. 50 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 16:42:44,127 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 15 states [2022-04-07 16:42:44,127 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 16:42:44,128 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2022-04-07 16:42:44,128 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=49, Invalid=161, Unknown=0, NotChecked=0, Total=210 [2022-04-07 16:42:44,128 INFO L87 Difference]: Start difference. First operand 58 states and 70 transitions. Second operand has 15 states, 15 states have (on average 3.0) internal successors, (45), 14 states have internal predecessors, (45), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:42:44,924 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 16:42:44,924 INFO L93 Difference]: Finished difference Result 130 states and 166 transitions. [2022-04-07 16:42:44,925 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-04-07 16:42:44,925 INFO L78 Accepts]: Start accepts. Automaton has has 15 states, 15 states have (on average 3.0) internal successors, (45), 14 states have internal predecessors, (45), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 31 [2022-04-07 16:42:44,925 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 16:42:44,925 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15 states, 15 states have (on average 3.0) internal successors, (45), 14 states have internal predecessors, (45), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:42:44,926 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 81 transitions. [2022-04-07 16:42:44,926 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15 states, 15 states have (on average 3.0) internal successors, (45), 14 states have internal predecessors, (45), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:42:44,927 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 81 transitions. [2022-04-07 16:42:44,927 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 9 states and 81 transitions. [2022-04-07 16:42:45,009 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 81 edges. 81 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 16:42:45,011 INFO L225 Difference]: With dead ends: 130 [2022-04-07 16:42:45,011 INFO L226 Difference]: Without dead ends: 130 [2022-04-07 16:42:45,011 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 77 GetRequests, 54 SyntacticMatches, 4 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 72 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=97, Invalid=323, Unknown=0, NotChecked=0, Total=420 [2022-04-07 16:42:45,012 INFO L913 BasicCegarLoop]: 33 mSDtfsCounter, 187 mSDsluCounter, 37 mSDsCounter, 0 mSdLazyCounter, 273 mSolverCounterSat, 42 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 187 SdHoareTripleChecker+Valid, 70 SdHoareTripleChecker+Invalid, 315 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 42 IncrementalHoareTripleChecker+Valid, 273 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-04-07 16:42:45,012 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [187 Valid, 70 Invalid, 315 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [42 Valid, 273 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-04-07 16:42:45,013 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 130 states. [2022-04-07 16:42:45,020 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 130 to 81. [2022-04-07 16:42:45,020 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 16:42:45,021 INFO L82 GeneralOperation]: Start isEquivalent. First operand 130 states. Second operand has 81 states, 73 states have (on average 1.2602739726027397) internal successors, (92), 74 states have internal predecessors, (92), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 16:42:45,021 INFO L74 IsIncluded]: Start isIncluded. First operand 130 states. Second operand has 81 states, 73 states have (on average 1.2602739726027397) internal successors, (92), 74 states have internal predecessors, (92), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 16:42:45,021 INFO L87 Difference]: Start difference. First operand 130 states. Second operand has 81 states, 73 states have (on average 1.2602739726027397) internal successors, (92), 74 states have internal predecessors, (92), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 16:42:45,025 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 16:42:45,025 INFO L93 Difference]: Finished difference Result 130 states and 166 transitions. [2022-04-07 16:42:45,025 INFO L276 IsEmpty]: Start isEmpty. Operand 130 states and 166 transitions. [2022-04-07 16:42:45,025 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 16:42:45,025 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 16:42:45,026 INFO L74 IsIncluded]: Start isIncluded. First operand has 81 states, 73 states have (on average 1.2602739726027397) internal successors, (92), 74 states have internal predecessors, (92), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 130 states. [2022-04-07 16:42:45,026 INFO L87 Difference]: Start difference. First operand has 81 states, 73 states have (on average 1.2602739726027397) internal successors, (92), 74 states have internal predecessors, (92), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 130 states. [2022-04-07 16:42:45,032 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 16:42:45,032 INFO L93 Difference]: Finished difference Result 130 states and 166 transitions. [2022-04-07 16:42:45,032 INFO L276 IsEmpty]: Start isEmpty. Operand 130 states and 166 transitions. [2022-04-07 16:42:45,032 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 16:42:45,032 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 16:42:45,033 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 16:42:45,033 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 16:42:45,033 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 81 states, 73 states have (on average 1.2602739726027397) internal successors, (92), 74 states have internal predecessors, (92), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 16:42:45,035 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 99 transitions. [2022-04-07 16:42:45,035 INFO L78 Accepts]: Start accepts. Automaton has 81 states and 99 transitions. Word has length 31 [2022-04-07 16:42:45,035 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 16:42:45,035 INFO L478 AbstractCegarLoop]: Abstraction has 81 states and 99 transitions. [2022-04-07 16:42:45,035 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 15 states, 15 states have (on average 3.0) internal successors, (45), 14 states have internal predecessors, (45), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:42:45,035 INFO L276 IsEmpty]: Start isEmpty. Operand 81 states and 99 transitions. [2022-04-07 16:42:45,035 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2022-04-07 16:42:45,035 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 16:42:45,036 INFO L499 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 16:42:45,054 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Forceful destruction successful, exit code 0 [2022-04-07 16:42:45,254 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6,6 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 16:42:45,254 INFO L403 AbstractCegarLoop]: === Iteration 8 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 16:42:45,255 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 16:42:45,255 INFO L85 PathProgramCache]: Analyzing trace with hash -547485170, now seen corresponding path program 1 times [2022-04-07 16:42:45,255 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 16:42:45,255 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2103247700] [2022-04-07 16:42:45,255 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 16:42:45,255 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 16:42:45,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 16:42:45,379 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 16:42:45,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 16:42:45,382 INFO L290 TraceCheckUtils]: 0: Hoare triple {2831#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2816#true} is VALID [2022-04-07 16:42:45,383 INFO L290 TraceCheckUtils]: 1: Hoare triple {2816#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2816#true} is VALID [2022-04-07 16:42:45,383 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {2816#true} {2816#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2816#true} is VALID [2022-04-07 16:42:45,383 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 21 [2022-04-07 16:42:45,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 16:42:45,386 INFO L290 TraceCheckUtils]: 0: Hoare triple {2816#true} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2816#true} is VALID [2022-04-07 16:42:45,386 INFO L290 TraceCheckUtils]: 1: Hoare triple {2816#true} [132] L6-->L6-2: Formula: (not (= v___VERIFIER_assert_~cond_3 0)) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {2816#true} is VALID [2022-04-07 16:42:45,386 INFO L290 TraceCheckUtils]: 2: Hoare triple {2816#true} [136] L6-2-->__VERIFIER_assertEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2816#true} is VALID [2022-04-07 16:42:45,387 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2816#true} {2825#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [139] __VERIFIER_assertEXIT-->L30-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {2825#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-07 16:42:45,387 INFO L272 TraceCheckUtils]: 0: Hoare triple {2816#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2831#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 16:42:45,388 INFO L290 TraceCheckUtils]: 1: Hoare triple {2831#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2816#true} is VALID [2022-04-07 16:42:45,388 INFO L290 TraceCheckUtils]: 2: Hoare triple {2816#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2816#true} is VALID [2022-04-07 16:42:45,388 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2816#true} {2816#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2816#true} is VALID [2022-04-07 16:42:45,388 INFO L272 TraceCheckUtils]: 4: Hoare triple {2816#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2816#true} is VALID [2022-04-07 16:42:45,388 INFO L290 TraceCheckUtils]: 5: Hoare triple {2816#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (= (store |v_#length_2| |v_main_~#v~0.base_2| (* 4 (let ((.cse0 (mod v_main_~SIZE~0_2 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))))) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {2821#(= main_~j~0 0)} is VALID [2022-04-07 16:42:45,388 INFO L290 TraceCheckUtils]: 6: Hoare triple {2821#(= main_~j~0 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2821#(= main_~j~0 0)} is VALID [2022-04-07 16:42:45,389 INFO L290 TraceCheckUtils]: 7: Hoare triple {2821#(= main_~j~0 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2822#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 16:42:45,389 INFO L290 TraceCheckUtils]: 8: Hoare triple {2822#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2822#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 16:42:45,390 INFO L290 TraceCheckUtils]: 9: Hoare triple {2822#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2823#(and (<= main_~j~0 2) (not (<= (+ (div main_~j~0 4294967296) 1) 0)))} is VALID [2022-04-07 16:42:45,391 INFO L290 TraceCheckUtils]: 10: Hoare triple {2823#(and (<= main_~j~0 2) (not (<= (+ (div main_~j~0 4294967296) 1) 0)))} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-07 16:42:45,391 INFO L290 TraceCheckUtils]: 11: Hoare triple {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-07 16:42:45,391 INFO L290 TraceCheckUtils]: 12: Hoare triple {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-07 16:42:45,392 INFO L290 TraceCheckUtils]: 13: Hoare triple {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-07 16:42:45,392 INFO L290 TraceCheckUtils]: 14: Hoare triple {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-07 16:42:45,392 INFO L290 TraceCheckUtils]: 15: Hoare triple {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-07 16:42:45,393 INFO L290 TraceCheckUtils]: 16: Hoare triple {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-07 16:42:45,393 INFO L290 TraceCheckUtils]: 17: Hoare triple {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-07 16:42:45,393 INFO L290 TraceCheckUtils]: 18: Hoare triple {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-07 16:42:45,393 INFO L290 TraceCheckUtils]: 19: Hoare triple {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {2825#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-07 16:42:45,394 INFO L290 TraceCheckUtils]: 20: Hoare triple {2825#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {2825#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-07 16:42:45,394 INFO L272 TraceCheckUtils]: 21: Hoare triple {2825#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {2816#true} is VALID [2022-04-07 16:42:45,394 INFO L290 TraceCheckUtils]: 22: Hoare triple {2816#true} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2816#true} is VALID [2022-04-07 16:42:45,394 INFO L290 TraceCheckUtils]: 23: Hoare triple {2816#true} [132] L6-->L6-2: Formula: (not (= v___VERIFIER_assert_~cond_3 0)) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {2816#true} is VALID [2022-04-07 16:42:45,394 INFO L290 TraceCheckUtils]: 24: Hoare triple {2816#true} [136] L6-2-->__VERIFIER_assertEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2816#true} is VALID [2022-04-07 16:42:45,395 INFO L284 TraceCheckUtils]: 25: Hoare quadruple {2816#true} {2825#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [139] __VERIFIER_assertEXIT-->L30-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {2825#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-07 16:42:45,395 INFO L290 TraceCheckUtils]: 26: Hoare triple {2825#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [126] L30-1-->L29-2: Formula: true InVars {} OutVars{main_#t~mem13=|v_main_#t~mem13_3|, main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {2825#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-07 16:42:45,396 INFO L290 TraceCheckUtils]: 27: Hoare triple {2825#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [130] L29-2-->L29-3: Formula: (= v_main_~k~0_3 (+ v_main_~k~0_4 1)) InVars {main_~k~0=v_main_~k~0_4} OutVars{main_#t~post12=|v_main_#t~post12_1|, main_~k~0=v_main_~k~0_3} AuxVars[] AssignedVars[main_~k~0, main_#t~post12] {2830#(and (<= (div main_~k~0 4294967296) 0) (<= main_~SIZE~0 (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-07 16:42:45,397 INFO L290 TraceCheckUtils]: 28: Hoare triple {2830#(and (<= (div main_~k~0 4294967296) 0) (<= main_~SIZE~0 (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {2817#false} is VALID [2022-04-07 16:42:45,397 INFO L272 TraceCheckUtils]: 29: Hoare triple {2817#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {2817#false} is VALID [2022-04-07 16:42:45,397 INFO L290 TraceCheckUtils]: 30: Hoare triple {2817#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2817#false} is VALID [2022-04-07 16:42:45,397 INFO L290 TraceCheckUtils]: 31: Hoare triple {2817#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2817#false} is VALID [2022-04-07 16:42:45,397 INFO L290 TraceCheckUtils]: 32: Hoare triple {2817#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2817#false} is VALID [2022-04-07 16:42:45,397 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-07 16:42:45,397 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 16:42:45,397 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2103247700] [2022-04-07 16:42:45,397 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2103247700] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 16:42:45,397 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1867483632] [2022-04-07 16:42:45,397 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 16:42:45,398 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 16:42:45,398 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 16:42:45,401 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 16:42:45,402 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2022-04-07 16:42:45,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 16:42:45,451 INFO L263 TraceCheckSpWp]: Trace formula consists of 131 conjuncts, 12 conjunts are in the unsatisfiable core [2022-04-07 16:42:45,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 16:42:45,459 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 16:42:45,945 INFO L272 TraceCheckUtils]: 0: Hoare triple {2816#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2816#true} is VALID [2022-04-07 16:42:45,945 INFO L290 TraceCheckUtils]: 1: Hoare triple {2816#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2816#true} is VALID [2022-04-07 16:42:45,945 INFO L290 TraceCheckUtils]: 2: Hoare triple {2816#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2816#true} is VALID [2022-04-07 16:42:45,945 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2816#true} {2816#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2816#true} is VALID [2022-04-07 16:42:45,945 INFO L272 TraceCheckUtils]: 4: Hoare triple {2816#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2816#true} is VALID [2022-04-07 16:42:45,945 INFO L290 TraceCheckUtils]: 5: Hoare triple {2816#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (= (store |v_#length_2| |v_main_~#v~0.base_2| (* 4 (let ((.cse0 (mod v_main_~SIZE~0_2 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))))) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {2821#(= main_~j~0 0)} is VALID [2022-04-07 16:42:45,946 INFO L290 TraceCheckUtils]: 6: Hoare triple {2821#(= main_~j~0 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2821#(= main_~j~0 0)} is VALID [2022-04-07 16:42:45,946 INFO L290 TraceCheckUtils]: 7: Hoare triple {2821#(= main_~j~0 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2822#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 16:42:45,947 INFO L290 TraceCheckUtils]: 8: Hoare triple {2822#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2822#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 16:42:45,947 INFO L290 TraceCheckUtils]: 9: Hoare triple {2822#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2862#(and (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-07 16:42:45,948 INFO L290 TraceCheckUtils]: 10: Hoare triple {2862#(and (<= main_~j~0 2) (<= 2 main_~j~0))} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-07 16:42:45,948 INFO L290 TraceCheckUtils]: 11: Hoare triple {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-07 16:42:45,948 INFO L290 TraceCheckUtils]: 12: Hoare triple {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-07 16:42:45,949 INFO L290 TraceCheckUtils]: 13: Hoare triple {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-07 16:42:45,949 INFO L290 TraceCheckUtils]: 14: Hoare triple {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-07 16:42:45,949 INFO L290 TraceCheckUtils]: 15: Hoare triple {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-07 16:42:45,950 INFO L290 TraceCheckUtils]: 16: Hoare triple {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-07 16:42:45,950 INFO L290 TraceCheckUtils]: 17: Hoare triple {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-07 16:42:45,950 INFO L290 TraceCheckUtils]: 18: Hoare triple {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-07 16:42:45,951 INFO L290 TraceCheckUtils]: 19: Hoare triple {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {2825#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-07 16:42:45,951 INFO L290 TraceCheckUtils]: 20: Hoare triple {2825#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {2825#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-07 16:42:45,951 INFO L272 TraceCheckUtils]: 21: Hoare triple {2825#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {2816#true} is VALID [2022-04-07 16:42:45,951 INFO L290 TraceCheckUtils]: 22: Hoare triple {2816#true} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2816#true} is VALID [2022-04-07 16:42:45,951 INFO L290 TraceCheckUtils]: 23: Hoare triple {2816#true} [132] L6-->L6-2: Formula: (not (= v___VERIFIER_assert_~cond_3 0)) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {2816#true} is VALID [2022-04-07 16:42:45,952 INFO L290 TraceCheckUtils]: 24: Hoare triple {2816#true} [136] L6-2-->__VERIFIER_assertEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2816#true} is VALID [2022-04-07 16:42:45,952 INFO L284 TraceCheckUtils]: 25: Hoare quadruple {2816#true} {2825#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [139] __VERIFIER_assertEXIT-->L30-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {2825#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-07 16:42:45,952 INFO L290 TraceCheckUtils]: 26: Hoare triple {2825#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [126] L30-1-->L29-2: Formula: true InVars {} OutVars{main_#t~mem13=|v_main_#t~mem13_3|, main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {2825#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-07 16:42:45,953 INFO L290 TraceCheckUtils]: 27: Hoare triple {2825#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [130] L29-2-->L29-3: Formula: (= v_main_~k~0_3 (+ v_main_~k~0_4 1)) InVars {main_~k~0=v_main_~k~0_4} OutVars{main_#t~post12=|v_main_#t~post12_1|, main_~k~0=v_main_~k~0_3} AuxVars[] AssignedVars[main_~k~0, main_#t~post12] {2917#(and (= main_~k~0 2) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-07 16:42:45,954 INFO L290 TraceCheckUtils]: 28: Hoare triple {2917#(and (= main_~k~0 2) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {2817#false} is VALID [2022-04-07 16:42:45,954 INFO L272 TraceCheckUtils]: 29: Hoare triple {2817#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {2817#false} is VALID [2022-04-07 16:42:45,954 INFO L290 TraceCheckUtils]: 30: Hoare triple {2817#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2817#false} is VALID [2022-04-07 16:42:45,954 INFO L290 TraceCheckUtils]: 31: Hoare triple {2817#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2817#false} is VALID [2022-04-07 16:42:45,954 INFO L290 TraceCheckUtils]: 32: Hoare triple {2817#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2817#false} is VALID [2022-04-07 16:42:45,954 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-07 16:42:45,954 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-07 16:42:47,107 INFO L290 TraceCheckUtils]: 32: Hoare triple {2817#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2817#false} is VALID [2022-04-07 16:42:47,107 INFO L290 TraceCheckUtils]: 31: Hoare triple {2817#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2817#false} is VALID [2022-04-07 16:42:47,107 INFO L290 TraceCheckUtils]: 30: Hoare triple {2817#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2817#false} is VALID [2022-04-07 16:42:47,107 INFO L272 TraceCheckUtils]: 29: Hoare triple {2817#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {2817#false} is VALID [2022-04-07 16:42:47,108 INFO L290 TraceCheckUtils]: 28: Hoare triple {2945#(not (< (mod main_~k~0 4294967296) (mod main_~SIZE~0 4294967296)))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {2817#false} is VALID [2022-04-07 16:42:47,109 INFO L290 TraceCheckUtils]: 27: Hoare triple {2949#(not (< (mod (+ main_~k~0 1) 4294967296) (mod main_~SIZE~0 4294967296)))} [130] L29-2-->L29-3: Formula: (= v_main_~k~0_3 (+ v_main_~k~0_4 1)) InVars {main_~k~0=v_main_~k~0_4} OutVars{main_#t~post12=|v_main_#t~post12_1|, main_~k~0=v_main_~k~0_3} AuxVars[] AssignedVars[main_~k~0, main_#t~post12] {2945#(not (< (mod main_~k~0 4294967296) (mod main_~SIZE~0 4294967296)))} is VALID [2022-04-07 16:42:47,115 INFO L290 TraceCheckUtils]: 26: Hoare triple {2949#(not (< (mod (+ main_~k~0 1) 4294967296) (mod main_~SIZE~0 4294967296)))} [126] L30-1-->L29-2: Formula: true InVars {} OutVars{main_#t~mem13=|v_main_#t~mem13_3|, main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {2949#(not (< (mod (+ main_~k~0 1) 4294967296) (mod main_~SIZE~0 4294967296)))} is VALID [2022-04-07 16:42:47,116 INFO L284 TraceCheckUtils]: 25: Hoare quadruple {2816#true} {2949#(not (< (mod (+ main_~k~0 1) 4294967296) (mod main_~SIZE~0 4294967296)))} [139] __VERIFIER_assertEXIT-->L30-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {2949#(not (< (mod (+ main_~k~0 1) 4294967296) (mod main_~SIZE~0 4294967296)))} is VALID [2022-04-07 16:42:47,116 INFO L290 TraceCheckUtils]: 24: Hoare triple {2816#true} [136] L6-2-->__VERIFIER_assertEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2816#true} is VALID [2022-04-07 16:42:47,116 INFO L290 TraceCheckUtils]: 23: Hoare triple {2816#true} [132] L6-->L6-2: Formula: (not (= v___VERIFIER_assert_~cond_3 0)) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {2816#true} is VALID [2022-04-07 16:42:47,116 INFO L290 TraceCheckUtils]: 22: Hoare triple {2816#true} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2816#true} is VALID [2022-04-07 16:42:47,116 INFO L272 TraceCheckUtils]: 21: Hoare triple {2949#(not (< (mod (+ main_~k~0 1) 4294967296) (mod main_~SIZE~0 4294967296)))} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {2816#true} is VALID [2022-04-07 16:42:47,117 INFO L290 TraceCheckUtils]: 20: Hoare triple {2949#(not (< (mod (+ main_~k~0 1) 4294967296) (mod main_~SIZE~0 4294967296)))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {2949#(not (< (mod (+ main_~k~0 1) 4294967296) (mod main_~SIZE~0 4294967296)))} is VALID [2022-04-07 16:42:47,117 INFO L290 TraceCheckUtils]: 19: Hoare triple {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {2949#(not (< (mod (+ main_~k~0 1) 4294967296) (mod main_~SIZE~0 4294967296)))} is VALID [2022-04-07 16:42:47,117 INFO L290 TraceCheckUtils]: 18: Hoare triple {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-07 16:42:47,118 INFO L290 TraceCheckUtils]: 17: Hoare triple {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-07 16:42:47,118 INFO L290 TraceCheckUtils]: 16: Hoare triple {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-07 16:42:47,118 INFO L290 TraceCheckUtils]: 15: Hoare triple {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-07 16:42:47,119 INFO L290 TraceCheckUtils]: 14: Hoare triple {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-07 16:42:47,120 INFO L290 TraceCheckUtils]: 13: Hoare triple {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-07 16:42:47,120 INFO L290 TraceCheckUtils]: 12: Hoare triple {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-07 16:42:47,122 INFO L290 TraceCheckUtils]: 11: Hoare triple {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-07 16:42:47,122 INFO L290 TraceCheckUtils]: 10: Hoare triple {3001#(<= 0 (div (+ 2 (* (- 1) (mod main_~j~0 4294967296))) 4294967296))} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {2824#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-07 16:42:47,123 INFO L290 TraceCheckUtils]: 9: Hoare triple {3005#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) 2) 4294967296))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3001#(<= 0 (div (+ 2 (* (- 1) (mod main_~j~0 4294967296))) 4294967296))} is VALID [2022-04-07 16:42:47,124 INFO L290 TraceCheckUtils]: 8: Hoare triple {3005#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) 2) 4294967296))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3005#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) 2) 4294967296))} is VALID [2022-04-07 16:42:47,125 INFO L290 TraceCheckUtils]: 7: Hoare triple {3012#(<= 0 (div (+ 2 (* (- 1) (mod (+ main_~j~0 2) 4294967296))) 4294967296))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3005#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) 2) 4294967296))} is VALID [2022-04-07 16:42:47,126 INFO L290 TraceCheckUtils]: 6: Hoare triple {3012#(<= 0 (div (+ 2 (* (- 1) (mod (+ main_~j~0 2) 4294967296))) 4294967296))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3012#(<= 0 (div (+ 2 (* (- 1) (mod (+ main_~j~0 2) 4294967296))) 4294967296))} is VALID [2022-04-07 16:42:47,126 INFO L290 TraceCheckUtils]: 5: Hoare triple {2816#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (= (store |v_#length_2| |v_main_~#v~0.base_2| (* 4 (let ((.cse0 (mod v_main_~SIZE~0_2 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))))) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {3012#(<= 0 (div (+ 2 (* (- 1) (mod (+ main_~j~0 2) 4294967296))) 4294967296))} is VALID [2022-04-07 16:42:47,126 INFO L272 TraceCheckUtils]: 4: Hoare triple {2816#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2816#true} is VALID [2022-04-07 16:42:47,126 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2816#true} {2816#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2816#true} is VALID [2022-04-07 16:42:47,126 INFO L290 TraceCheckUtils]: 2: Hoare triple {2816#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2816#true} is VALID [2022-04-07 16:42:47,126 INFO L290 TraceCheckUtils]: 1: Hoare triple {2816#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2816#true} is VALID [2022-04-07 16:42:47,127 INFO L272 TraceCheckUtils]: 0: Hoare triple {2816#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2816#true} is VALID [2022-04-07 16:42:47,127 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-07 16:42:47,127 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1867483632] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-07 16:42:47,127 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-07 16:42:47,127 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 8, 8] total 16 [2022-04-07 16:42:47,127 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [39198860] [2022-04-07 16:42:47,127 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-07 16:42:47,128 INFO L78 Accepts]: Start accepts. Automaton has has 16 states, 16 states have (on average 2.6875) internal successors, (43), 15 states have internal predecessors, (43), 4 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Word has length 33 [2022-04-07 16:42:47,128 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 16:42:47,128 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 16 states, 16 states have (on average 2.6875) internal successors, (43), 15 states have internal predecessors, (43), 4 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 16:42:47,162 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 52 edges. 52 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 16:42:47,162 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 16 states [2022-04-07 16:42:47,163 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 16:42:47,163 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2022-04-07 16:42:47,163 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=194, Unknown=0, NotChecked=0, Total=240 [2022-04-07 16:42:47,163 INFO L87 Difference]: Start difference. First operand 81 states and 99 transitions. Second operand has 16 states, 16 states have (on average 2.6875) internal successors, (43), 15 states have internal predecessors, (43), 4 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 16:42:48,243 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 16:42:48,243 INFO L93 Difference]: Finished difference Result 131 states and 166 transitions. [2022-04-07 16:42:48,243 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-04-07 16:42:48,243 INFO L78 Accepts]: Start accepts. Automaton has has 16 states, 16 states have (on average 2.6875) internal successors, (43), 15 states have internal predecessors, (43), 4 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Word has length 33 [2022-04-07 16:42:48,243 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 16:42:48,243 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 2.6875) internal successors, (43), 15 states have internal predecessors, (43), 4 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 16:42:48,244 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 81 transitions. [2022-04-07 16:42:48,245 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 2.6875) internal successors, (43), 15 states have internal predecessors, (43), 4 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 16:42:48,245 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 81 transitions. [2022-04-07 16:42:48,246 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 10 states and 81 transitions. [2022-04-07 16:42:48,310 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 81 edges. 81 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 16:42:48,316 INFO L225 Difference]: With dead ends: 131 [2022-04-07 16:42:48,316 INFO L226 Difference]: Without dead ends: 122 [2022-04-07 16:42:48,316 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 84 GetRequests, 59 SyntacticMatches, 4 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 75 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=108, Invalid=398, Unknown=0, NotChecked=0, Total=506 [2022-04-07 16:42:48,316 INFO L913 BasicCegarLoop]: 32 mSDtfsCounter, 198 mSDsluCounter, 42 mSDsCounter, 0 mSdLazyCounter, 341 mSolverCounterSat, 39 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 199 SdHoareTripleChecker+Valid, 74 SdHoareTripleChecker+Invalid, 380 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 39 IncrementalHoareTripleChecker+Valid, 341 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-04-07 16:42:48,317 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [199 Valid, 74 Invalid, 380 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [39 Valid, 341 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2022-04-07 16:42:48,317 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 122 states. [2022-04-07 16:42:48,319 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 122 to 98. [2022-04-07 16:42:48,319 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 16:42:48,320 INFO L82 GeneralOperation]: Start isEquivalent. First operand 122 states. Second operand has 98 states, 89 states have (on average 1.2584269662921348) internal successors, (112), 91 states have internal predecessors, (112), 5 states have call successors, (5), 4 states have call predecessors, (5), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 16:42:48,320 INFO L74 IsIncluded]: Start isIncluded. First operand 122 states. Second operand has 98 states, 89 states have (on average 1.2584269662921348) internal successors, (112), 91 states have internal predecessors, (112), 5 states have call successors, (5), 4 states have call predecessors, (5), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 16:42:48,320 INFO L87 Difference]: Start difference. First operand 122 states. Second operand has 98 states, 89 states have (on average 1.2584269662921348) internal successors, (112), 91 states have internal predecessors, (112), 5 states have call successors, (5), 4 states have call predecessors, (5), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 16:42:48,322 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 16:42:48,322 INFO L93 Difference]: Finished difference Result 122 states and 153 transitions. [2022-04-07 16:42:48,322 INFO L276 IsEmpty]: Start isEmpty. Operand 122 states and 153 transitions. [2022-04-07 16:42:48,322 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 16:42:48,322 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 16:42:48,323 INFO L74 IsIncluded]: Start isIncluded. First operand has 98 states, 89 states have (on average 1.2584269662921348) internal successors, (112), 91 states have internal predecessors, (112), 5 states have call successors, (5), 4 states have call predecessors, (5), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 122 states. [2022-04-07 16:42:48,323 INFO L87 Difference]: Start difference. First operand has 98 states, 89 states have (on average 1.2584269662921348) internal successors, (112), 91 states have internal predecessors, (112), 5 states have call successors, (5), 4 states have call predecessors, (5), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 122 states. [2022-04-07 16:42:48,325 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 16:42:48,325 INFO L93 Difference]: Finished difference Result 122 states and 153 transitions. [2022-04-07 16:42:48,325 INFO L276 IsEmpty]: Start isEmpty. Operand 122 states and 153 transitions. [2022-04-07 16:42:48,325 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 16:42:48,325 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 16:42:48,325 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 16:42:48,325 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 16:42:48,326 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 98 states, 89 states have (on average 1.2584269662921348) internal successors, (112), 91 states have internal predecessors, (112), 5 states have call successors, (5), 4 states have call predecessors, (5), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 16:42:48,327 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98 states to 98 states and 120 transitions. [2022-04-07 16:42:48,327 INFO L78 Accepts]: Start accepts. Automaton has 98 states and 120 transitions. Word has length 33 [2022-04-07 16:42:48,327 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 16:42:48,328 INFO L478 AbstractCegarLoop]: Abstraction has 98 states and 120 transitions. [2022-04-07 16:42:48,328 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 16 states, 16 states have (on average 2.6875) internal successors, (43), 15 states have internal predecessors, (43), 4 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 16:42:48,328 INFO L276 IsEmpty]: Start isEmpty. Operand 98 states and 120 transitions. [2022-04-07 16:42:48,328 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2022-04-07 16:42:48,328 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 16:42:48,328 INFO L499 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 16:42:48,346 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Ended with exit code 0 [2022-04-07 16:42:48,544 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7,7 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 16:42:48,544 INFO L403 AbstractCegarLoop]: === Iteration 9 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 16:42:48,545 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 16:42:48,545 INFO L85 PathProgramCache]: Analyzing trace with hash 2007942384, now seen corresponding path program 4 times [2022-04-07 16:42:48,545 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 16:42:48,545 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [63260666] [2022-04-07 16:42:48,545 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 16:42:48,545 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 16:42:48,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 16:42:49,083 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 16:42:49,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 16:42:49,088 INFO L290 TraceCheckUtils]: 0: Hoare triple {3544#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3523#true} is VALID [2022-04-07 16:42:49,088 INFO L290 TraceCheckUtils]: 1: Hoare triple {3523#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3523#true} is VALID [2022-04-07 16:42:49,088 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {3523#true} {3523#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3523#true} is VALID [2022-04-07 16:42:49,088 INFO L272 TraceCheckUtils]: 0: Hoare triple {3523#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3544#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 16:42:49,088 INFO L290 TraceCheckUtils]: 1: Hoare triple {3544#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3523#true} is VALID [2022-04-07 16:42:49,089 INFO L290 TraceCheckUtils]: 2: Hoare triple {3523#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3523#true} is VALID [2022-04-07 16:42:49,089 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3523#true} {3523#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3523#true} is VALID [2022-04-07 16:42:49,089 INFO L272 TraceCheckUtils]: 4: Hoare triple {3523#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3523#true} is VALID [2022-04-07 16:42:49,089 INFO L290 TraceCheckUtils]: 5: Hoare triple {3523#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (= (store |v_#length_2| |v_main_~#v~0.base_2| (* 4 (let ((.cse0 (mod v_main_~SIZE~0_2 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))))) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {3528#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-07 16:42:49,090 INFO L290 TraceCheckUtils]: 6: Hoare triple {3528#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3528#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-07 16:42:49,090 INFO L290 TraceCheckUtils]: 7: Hoare triple {3528#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3529#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 16:42:49,091 INFO L290 TraceCheckUtils]: 8: Hoare triple {3529#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3529#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 16:42:49,091 INFO L290 TraceCheckUtils]: 9: Hoare triple {3529#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3530#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| (* main_~j~0 4)) 0)))} is VALID [2022-04-07 16:42:49,091 INFO L290 TraceCheckUtils]: 10: Hoare triple {3530#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| (* main_~j~0 4)) 0)))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3531#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 16:42:49,092 INFO L290 TraceCheckUtils]: 11: Hoare triple {3531#(= |main_~#v~0.offset| 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3531#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 16:42:49,092 INFO L290 TraceCheckUtils]: 12: Hoare triple {3531#(= |main_~#v~0.offset| 0)} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {3531#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 16:42:49,092 INFO L290 TraceCheckUtils]: 13: Hoare triple {3531#(= |main_~#v~0.offset| 0)} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {3529#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 16:42:49,093 INFO L290 TraceCheckUtils]: 14: Hoare triple {3529#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {3532#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-07 16:42:49,094 INFO L290 TraceCheckUtils]: 15: Hoare triple {3532#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~i~0 1) main_~j~0))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {3533#(and (= |main_~#v~0.offset| 0) (or (not |main_#t~short10|) (and (= (+ (- 1) main_~j~0) 0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0))))} is VALID [2022-04-07 16:42:49,094 INFO L290 TraceCheckUtils]: 16: Hoare triple {3533#(and (= |main_~#v~0.offset| 0) (or (not |main_#t~short10|) (and (= (+ (- 1) main_~j~0) 0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3534#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} is VALID [2022-04-07 16:42:49,095 INFO L290 TraceCheckUtils]: 17: Hoare triple {3534#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3535#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-07 16:42:49,096 INFO L290 TraceCheckUtils]: 18: Hoare triple {3535#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {3536#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:42:49,096 INFO L290 TraceCheckUtils]: 19: Hoare triple {3536#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {3537#(and (= |main_~#v~0.offset| 0) (<= (+ (div (* (- 1) |main_~#v~0.offset|) 4) 2) main_~j~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:42:49,097 INFO L290 TraceCheckUtils]: 20: Hoare triple {3537#(and (= |main_~#v~0.offset| 0) (<= (+ (div (* (- 1) |main_~#v~0.offset|) 4) 2) main_~j~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {3538#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:42:49,098 INFO L290 TraceCheckUtils]: 21: Hoare triple {3538#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {3538#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:42:49,098 INFO L290 TraceCheckUtils]: 22: Hoare triple {3538#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3538#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:42:49,099 INFO L290 TraceCheckUtils]: 23: Hoare triple {3538#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3538#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:42:49,100 INFO L290 TraceCheckUtils]: 24: Hoare triple {3538#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {3539#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:42:49,100 INFO L290 TraceCheckUtils]: 25: Hoare triple {3539#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {3539#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:42:49,101 INFO L290 TraceCheckUtils]: 26: Hoare triple {3539#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {3539#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:42:49,101 INFO L290 TraceCheckUtils]: 27: Hoare triple {3539#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {3540#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-07 16:42:49,102 INFO L290 TraceCheckUtils]: 28: Hoare triple {3540#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3541#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-07 16:42:49,102 INFO L272 TraceCheckUtils]: 29: Hoare triple {3541#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3542#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-07 16:42:49,102 INFO L290 TraceCheckUtils]: 30: Hoare triple {3542#(not (= |__VERIFIER_assert_#in~cond| 0))} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3543#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-07 16:42:49,103 INFO L290 TraceCheckUtils]: 31: Hoare triple {3543#(not (= __VERIFIER_assert_~cond 0))} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {3524#false} is VALID [2022-04-07 16:42:49,103 INFO L290 TraceCheckUtils]: 32: Hoare triple {3524#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3524#false} is VALID [2022-04-07 16:42:49,103 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 17 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 16:42:49,103 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 16:42:49,103 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [63260666] [2022-04-07 16:42:49,103 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [63260666] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 16:42:49,103 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [454512591] [2022-04-07 16:42:49,104 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-04-07 16:42:49,104 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 16:42:49,104 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 16:42:49,124 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 16:42:49,157 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2022-04-07 16:42:49,200 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-04-07 16:42:49,200 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-07 16:42:49,201 INFO L263 TraceCheckSpWp]: Trace formula consists of 140 conjuncts, 28 conjunts are in the unsatisfiable core [2022-04-07 16:42:49,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 16:42:49,216 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 16:42:49,424 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-04-07 16:42:49,424 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-04-07 16:42:49,581 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-04-07 16:42:49,581 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-04-07 16:42:49,582 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-04-07 16:42:49,583 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-04-07 16:42:49,583 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 29 [2022-04-07 16:42:49,628 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-04-07 16:42:49,628 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 10 [2022-04-07 16:42:49,678 INFO L272 TraceCheckUtils]: 0: Hoare triple {3523#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3523#true} is VALID [2022-04-07 16:42:49,678 INFO L290 TraceCheckUtils]: 1: Hoare triple {3523#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3523#true} is VALID [2022-04-07 16:42:49,678 INFO L290 TraceCheckUtils]: 2: Hoare triple {3523#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3523#true} is VALID [2022-04-07 16:42:49,678 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3523#true} {3523#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3523#true} is VALID [2022-04-07 16:42:49,678 INFO L272 TraceCheckUtils]: 4: Hoare triple {3523#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3523#true} is VALID [2022-04-07 16:42:49,678 INFO L290 TraceCheckUtils]: 5: Hoare triple {3523#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (= (store |v_#length_2| |v_main_~#v~0.base_2| (* 4 (let ((.cse0 (mod v_main_~SIZE~0_2 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))))) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {3531#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 16:42:49,679 INFO L290 TraceCheckUtils]: 6: Hoare triple {3531#(= |main_~#v~0.offset| 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3531#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 16:42:49,679 INFO L290 TraceCheckUtils]: 7: Hoare triple {3531#(= |main_~#v~0.offset| 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3531#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 16:42:49,679 INFO L290 TraceCheckUtils]: 8: Hoare triple {3531#(= |main_~#v~0.offset| 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3531#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 16:42:49,679 INFO L290 TraceCheckUtils]: 9: Hoare triple {3531#(= |main_~#v~0.offset| 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3531#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 16:42:49,679 INFO L290 TraceCheckUtils]: 10: Hoare triple {3531#(= |main_~#v~0.offset| 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3531#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 16:42:49,680 INFO L290 TraceCheckUtils]: 11: Hoare triple {3531#(= |main_~#v~0.offset| 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3531#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 16:42:49,680 INFO L290 TraceCheckUtils]: 12: Hoare triple {3531#(= |main_~#v~0.offset| 0)} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {3531#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 16:42:49,680 INFO L290 TraceCheckUtils]: 13: Hoare triple {3531#(= |main_~#v~0.offset| 0)} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {3529#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 16:42:49,681 INFO L290 TraceCheckUtils]: 14: Hoare triple {3529#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {3532#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-07 16:42:49,681 INFO L290 TraceCheckUtils]: 15: Hoare triple {3532#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~i~0 1) main_~j~0))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {3593#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~i~0 1) main_~j~0) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} is VALID [2022-04-07 16:42:49,682 INFO L290 TraceCheckUtils]: 16: Hoare triple {3593#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~i~0 1) main_~j~0) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3534#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} is VALID [2022-04-07 16:42:49,682 INFO L290 TraceCheckUtils]: 17: Hoare triple {3534#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3535#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-07 16:42:49,683 INFO L290 TraceCheckUtils]: 18: Hoare triple {3535#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {3536#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:42:49,683 INFO L290 TraceCheckUtils]: 19: Hoare triple {3536#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {3606#(and (= |main_~#v~0.offset| 0) (= main_~j~0 2) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:42:49,683 INFO L290 TraceCheckUtils]: 20: Hoare triple {3606#(and (= |main_~#v~0.offset| 0) (= main_~j~0 2) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {3610#(and (= |main_~#v~0.offset| 0) (= 2 (+ main_~i~0 1)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:42:49,684 INFO L290 TraceCheckUtils]: 21: Hoare triple {3610#(and (= |main_~#v~0.offset| 0) (= 2 (+ main_~i~0 1)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {3614#(and (= |main_~#v~0.offset| 0) (= 2 (+ main_~i~0 1)) |main_#t~short10| (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:42:49,684 INFO L290 TraceCheckUtils]: 22: Hoare triple {3614#(and (= |main_~#v~0.offset| 0) (= 2 (+ main_~i~0 1)) |main_#t~short10| (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3610#(and (= |main_~#v~0.offset| 0) (= 2 (+ main_~i~0 1)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:42:49,684 INFO L290 TraceCheckUtils]: 23: Hoare triple {3610#(and (= |main_~#v~0.offset| 0) (= 2 (+ main_~i~0 1)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3610#(and (= |main_~#v~0.offset| 0) (= 2 (+ main_~i~0 1)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:42:49,685 INFO L290 TraceCheckUtils]: 24: Hoare triple {3610#(and (= |main_~#v~0.offset| 0) (= 2 (+ main_~i~0 1)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {3539#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:42:49,685 INFO L290 TraceCheckUtils]: 25: Hoare triple {3539#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {3539#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:42:49,686 INFO L290 TraceCheckUtils]: 26: Hoare triple {3539#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {3539#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:42:49,686 INFO L290 TraceCheckUtils]: 27: Hoare triple {3539#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {3540#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-07 16:42:49,686 INFO L290 TraceCheckUtils]: 28: Hoare triple {3540#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3541#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-07 16:42:49,687 INFO L272 TraceCheckUtils]: 29: Hoare triple {3541#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3639#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 16:42:49,687 INFO L290 TraceCheckUtils]: 30: Hoare triple {3639#(<= 1 |__VERIFIER_assert_#in~cond|)} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3643#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 16:42:49,687 INFO L290 TraceCheckUtils]: 31: Hoare triple {3643#(<= 1 __VERIFIER_assert_~cond)} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {3524#false} is VALID [2022-04-07 16:42:49,687 INFO L290 TraceCheckUtils]: 32: Hoare triple {3524#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3524#false} is VALID [2022-04-07 16:42:49,688 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2022-04-07 16:42:49,688 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-07 16:42:50,214 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 51 [2022-04-07 16:42:50,253 INFO L356 Elim1Store]: treesize reduction 16, result has 56.8 percent of original size [2022-04-07 16:42:50,253 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 1429 treesize of output 1347 [2022-04-07 16:43:23,534 INFO L290 TraceCheckUtils]: 32: Hoare triple {3524#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3524#false} is VALID [2022-04-07 16:43:23,535 INFO L290 TraceCheckUtils]: 31: Hoare triple {3643#(<= 1 __VERIFIER_assert_~cond)} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {3524#false} is VALID [2022-04-07 16:43:23,536 INFO L290 TraceCheckUtils]: 30: Hoare triple {3639#(<= 1 |__VERIFIER_assert_#in~cond|)} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3643#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 16:43:23,536 INFO L272 TraceCheckUtils]: 29: Hoare triple {3541#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3639#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 16:43:23,536 INFO L290 TraceCheckUtils]: 28: Hoare triple {3662#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3541#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-07 16:43:23,537 INFO L290 TraceCheckUtils]: 27: Hoare triple {3666#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {3662#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} is VALID [2022-04-07 16:43:23,537 INFO L290 TraceCheckUtils]: 26: Hoare triple {3666#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {3666#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-07 16:43:23,537 INFO L290 TraceCheckUtils]: 25: Hoare triple {3666#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {3666#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-07 16:43:23,538 INFO L290 TraceCheckUtils]: 24: Hoare triple {3676#(forall ((v_ArrVal_129 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_129) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_129) (+ |main_~#v~0.offset| 4))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {3666#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-07 16:43:23,538 INFO L290 TraceCheckUtils]: 23: Hoare triple {3676#(forall ((v_ArrVal_129 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_129) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_129) (+ |main_~#v~0.offset| 4))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3676#(forall ((v_ArrVal_129 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_129) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_129) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:43:23,539 INFO L290 TraceCheckUtils]: 22: Hoare triple {3683#(or (forall ((v_ArrVal_129 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_129) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_129) (+ |main_~#v~0.offset| 4)))) (not |main_#t~short10|))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3676#(forall ((v_ArrVal_129 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_129) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_129) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:43:23,540 INFO L290 TraceCheckUtils]: 21: Hoare triple {3687#(or (forall ((v_ArrVal_129 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_129) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_129) (+ |main_~#v~0.offset| 4)))) (not (<= 0 main_~i~0)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {3683#(or (forall ((v_ArrVal_129 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_129) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_129) (+ |main_~#v~0.offset| 4)))) (not |main_#t~short10|))} is VALID [2022-04-07 16:43:23,541 INFO L290 TraceCheckUtils]: 20: Hoare triple {3691#(or (not (<= 1 main_~j~0)) (forall ((v_ArrVal_129 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)) v_ArrVal_129) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)) v_ArrVal_129) (+ |main_~#v~0.offset| 4)))))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {3687#(or (forall ((v_ArrVal_129 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_129) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_129) (+ |main_~#v~0.offset| 4)))) (not (<= 0 main_~i~0)))} is VALID [2022-04-07 16:43:23,543 INFO L290 TraceCheckUtils]: 19: Hoare triple {3695#(or (not (<= 0 main_~j~0)) (forall ((v_ArrVal_129 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_129) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_129) (+ |main_~#v~0.offset| 4)))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {3691#(or (not (<= 1 main_~j~0)) (forall ((v_ArrVal_129 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)) v_ArrVal_129) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)) v_ArrVal_129) (+ |main_~#v~0.offset| 4)))))} is VALID [2022-04-07 16:43:23,544 INFO L290 TraceCheckUtils]: 18: Hoare triple {3699#(or (not (<= 0 main_~j~0)) (forall ((v_ArrVal_129 Int) (v_ArrVal_127 Int)) (or (not (<= main_~key~0 v_ArrVal_127)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_127) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_129) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_127) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_129) (+ |main_~#v~0.offset| 4))))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {3695#(or (not (<= 0 main_~j~0)) (forall ((v_ArrVal_129 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_129) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_129) (+ |main_~#v~0.offset| 4)))))} is VALID [2022-04-07 16:43:23,545 INFO L290 TraceCheckUtils]: 17: Hoare triple {3703#(or (not (<= 0 main_~j~0)) (forall ((v_ArrVal_129 Int) (v_ArrVal_127 Int)) (or (not (<= main_~key~0 v_ArrVal_127)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_127) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_129) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_127) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_129) (+ |main_~#v~0.offset| 4))))) |main_#t~short10|)} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3699#(or (not (<= 0 main_~j~0)) (forall ((v_ArrVal_129 Int) (v_ArrVal_127 Int)) (or (not (<= main_~key~0 v_ArrVal_127)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_127) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_129) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_127) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_129) (+ |main_~#v~0.offset| 4))))))} is VALID [2022-04-07 16:43:23,546 INFO L290 TraceCheckUtils]: 16: Hoare triple {3707#(or (not (<= 0 main_~j~0)) (and (not (= (* main_~j~0 4) 0)) (= 0 (* main_~i~0 4))) (not |main_#t~short10|))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3703#(or (not (<= 0 main_~j~0)) (forall ((v_ArrVal_129 Int) (v_ArrVal_127 Int)) (or (not (<= main_~key~0 v_ArrVal_127)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_127) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_129) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_127) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_129) (+ |main_~#v~0.offset| 4))))) |main_#t~short10|)} is VALID [2022-04-07 16:43:23,546 INFO L290 TraceCheckUtils]: 15: Hoare triple {3711#(or (not (<= 0 main_~j~0)) (not (<= 0 main_~i~0)) (and (not (= (* main_~j~0 4) 0)) (= 0 (* main_~i~0 4))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {3707#(or (not (<= 0 main_~j~0)) (and (not (= (* main_~j~0 4) 0)) (= 0 (* main_~i~0 4))) (not |main_#t~short10|))} is VALID [2022-04-07 16:43:23,561 INFO L290 TraceCheckUtils]: 14: Hoare triple {3715#(<= main_~j~0 1)} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {3711#(or (not (<= 0 main_~j~0)) (not (<= 0 main_~i~0)) (and (not (= (* main_~j~0 4) 0)) (= 0 (* main_~i~0 4))))} is VALID [2022-04-07 16:43:23,561 INFO L290 TraceCheckUtils]: 13: Hoare triple {3523#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {3715#(<= main_~j~0 1)} is VALID [2022-04-07 16:43:23,561 INFO L290 TraceCheckUtils]: 12: Hoare triple {3523#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {3523#true} is VALID [2022-04-07 16:43:23,561 INFO L290 TraceCheckUtils]: 11: Hoare triple {3523#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3523#true} is VALID [2022-04-07 16:43:23,561 INFO L290 TraceCheckUtils]: 10: Hoare triple {3523#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3523#true} is VALID [2022-04-07 16:43:23,561 INFO L290 TraceCheckUtils]: 9: Hoare triple {3523#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3523#true} is VALID [2022-04-07 16:43:23,562 INFO L290 TraceCheckUtils]: 8: Hoare triple {3523#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3523#true} is VALID [2022-04-07 16:43:23,562 INFO L290 TraceCheckUtils]: 7: Hoare triple {3523#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3523#true} is VALID [2022-04-07 16:43:23,562 INFO L290 TraceCheckUtils]: 6: Hoare triple {3523#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3523#true} is VALID [2022-04-07 16:43:23,562 INFO L290 TraceCheckUtils]: 5: Hoare triple {3523#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (= (store |v_#length_2| |v_main_~#v~0.base_2| (* 4 (let ((.cse0 (mod v_main_~SIZE~0_2 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))))) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {3523#true} is VALID [2022-04-07 16:43:23,562 INFO L272 TraceCheckUtils]: 4: Hoare triple {3523#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3523#true} is VALID [2022-04-07 16:43:23,562 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3523#true} {3523#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3523#true} is VALID [2022-04-07 16:43:23,562 INFO L290 TraceCheckUtils]: 2: Hoare triple {3523#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3523#true} is VALID [2022-04-07 16:43:23,563 INFO L290 TraceCheckUtils]: 1: Hoare triple {3523#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3523#true} is VALID [2022-04-07 16:43:23,563 INFO L272 TraceCheckUtils]: 0: Hoare triple {3523#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3523#true} is VALID [2022-04-07 16:43:23,563 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2022-04-07 16:43:23,563 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [454512591] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-07 16:43:23,563 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-07 16:43:23,563 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 17, 17] total 37 [2022-04-07 16:43:23,570 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [577107918] [2022-04-07 16:43:23,570 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-07 16:43:23,571 INFO L78 Accepts]: Start accepts. Automaton has has 37 states, 36 states have (on average 1.7222222222222223) internal successors, (62), 34 states have internal predecessors, (62), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 33 [2022-04-07 16:43:23,571 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 16:43:23,572 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 37 states, 36 states have (on average 1.7222222222222223) internal successors, (62), 34 states have internal predecessors, (62), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:43:23,615 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 68 edges. 68 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 16:43:23,615 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 37 states [2022-04-07 16:43:23,615 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 16:43:23,616 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2022-04-07 16:43:23,616 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=167, Invalid=1164, Unknown=1, NotChecked=0, Total=1332 [2022-04-07 16:43:23,616 INFO L87 Difference]: Start difference. First operand 98 states and 120 transitions. Second operand has 37 states, 36 states have (on average 1.7222222222222223) internal successors, (62), 34 states have internal predecessors, (62), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:44:09,477 WARN L232 SmtUtils]: Spent 14.24s on a formula simplification that was a NOOP. DAG size: 37 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-07 16:44:23,350 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 16:44:23,351 INFO L93 Difference]: Finished difference Result 298 states and 390 transitions. [2022-04-07 16:44:23,351 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 70 states. [2022-04-07 16:44:23,351 INFO L78 Accepts]: Start accepts. Automaton has has 37 states, 36 states have (on average 1.7222222222222223) internal successors, (62), 34 states have internal predecessors, (62), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 33 [2022-04-07 16:44:23,351 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 16:44:23,351 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37 states, 36 states have (on average 1.7222222222222223) internal successors, (62), 34 states have internal predecessors, (62), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:44:23,355 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70 states to 70 states and 258 transitions. [2022-04-07 16:44:23,355 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37 states, 36 states have (on average 1.7222222222222223) internal successors, (62), 34 states have internal predecessors, (62), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:44:23,364 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70 states to 70 states and 258 transitions. [2022-04-07 16:44:23,365 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 70 states and 258 transitions. [2022-04-07 16:44:23,657 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 258 edges. 258 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 16:44:23,660 INFO L225 Difference]: With dead ends: 298 [2022-04-07 16:44:23,661 INFO L226 Difference]: Without dead ends: 298 [2022-04-07 16:44:23,663 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 162 GetRequests, 52 SyntacticMatches, 16 SemanticMatches, 94 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3273 ImplicationChecksByTransitivity, 53.6s TimeCoverageRelationStatistics Valid=1081, Invalid=8032, Unknown=7, NotChecked=0, Total=9120 [2022-04-07 16:44:23,664 INFO L913 BasicCegarLoop]: 24 mSDtfsCounter, 220 mSDsluCounter, 124 mSDsCounter, 0 mSdLazyCounter, 1020 mSolverCounterSat, 205 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 221 SdHoareTripleChecker+Valid, 148 SdHoareTripleChecker+Invalid, 2187 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 205 IncrementalHoareTripleChecker+Valid, 1020 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 962 IncrementalHoareTripleChecker+Unchecked, 1.3s IncrementalHoareTripleChecker+Time [2022-04-07 16:44:23,665 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [221 Valid, 148 Invalid, 2187 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [205 Valid, 1020 Invalid, 0 Unknown, 962 Unchecked, 1.3s Time] [2022-04-07 16:44:23,665 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 298 states. [2022-04-07 16:44:23,672 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 298 to 186. [2022-04-07 16:44:23,672 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 16:44:23,672 INFO L82 GeneralOperation]: Start isEquivalent. First operand 298 states. Second operand has 186 states, 177 states have (on average 1.3389830508474576) internal successors, (237), 179 states have internal predecessors, (237), 5 states have call successors, (5), 4 states have call predecessors, (5), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 16:44:23,673 INFO L74 IsIncluded]: Start isIncluded. First operand 298 states. Second operand has 186 states, 177 states have (on average 1.3389830508474576) internal successors, (237), 179 states have internal predecessors, (237), 5 states have call successors, (5), 4 states have call predecessors, (5), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 16:44:23,673 INFO L87 Difference]: Start difference. First operand 298 states. Second operand has 186 states, 177 states have (on average 1.3389830508474576) internal successors, (237), 179 states have internal predecessors, (237), 5 states have call successors, (5), 4 states have call predecessors, (5), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 16:44:23,685 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 16:44:23,685 INFO L93 Difference]: Finished difference Result 298 states and 390 transitions. [2022-04-07 16:44:23,685 INFO L276 IsEmpty]: Start isEmpty. Operand 298 states and 390 transitions. [2022-04-07 16:44:23,686 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 16:44:23,686 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 16:44:23,687 INFO L74 IsIncluded]: Start isIncluded. First operand has 186 states, 177 states have (on average 1.3389830508474576) internal successors, (237), 179 states have internal predecessors, (237), 5 states have call successors, (5), 4 states have call predecessors, (5), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 298 states. [2022-04-07 16:44:23,693 INFO L87 Difference]: Start difference. First operand has 186 states, 177 states have (on average 1.3389830508474576) internal successors, (237), 179 states have internal predecessors, (237), 5 states have call successors, (5), 4 states have call predecessors, (5), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 298 states. [2022-04-07 16:44:23,698 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 16:44:23,698 INFO L93 Difference]: Finished difference Result 298 states and 390 transitions. [2022-04-07 16:44:23,698 INFO L276 IsEmpty]: Start isEmpty. Operand 298 states and 390 transitions. [2022-04-07 16:44:23,698 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 16:44:23,698 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 16:44:23,698 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 16:44:23,698 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 16:44:23,699 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 186 states, 177 states have (on average 1.3389830508474576) internal successors, (237), 179 states have internal predecessors, (237), 5 states have call successors, (5), 4 states have call predecessors, (5), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 16:44:23,701 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 245 transitions. [2022-04-07 16:44:23,701 INFO L78 Accepts]: Start accepts. Automaton has 186 states and 245 transitions. Word has length 33 [2022-04-07 16:44:23,702 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 16:44:23,702 INFO L478 AbstractCegarLoop]: Abstraction has 186 states and 245 transitions. [2022-04-07 16:44:23,702 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 37 states, 36 states have (on average 1.7222222222222223) internal successors, (62), 34 states have internal predecessors, (62), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:44:23,702 INFO L276 IsEmpty]: Start isEmpty. Operand 186 states and 245 transitions. [2022-04-07 16:44:23,702 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2022-04-07 16:44:23,702 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 16:44:23,702 INFO L499 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 16:44:23,722 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Forceful destruction successful, exit code 0 [2022-04-07 16:44:23,904 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8,8 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 16:44:23,904 INFO L403 AbstractCegarLoop]: === Iteration 10 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 16:44:23,904 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 16:44:23,905 INFO L85 PathProgramCache]: Analyzing trace with hash -552750849, now seen corresponding path program 2 times [2022-04-07 16:44:23,905 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 16:44:23,905 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [870056443] [2022-04-07 16:44:23,905 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 16:44:23,905 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 16:44:23,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 16:44:23,946 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 16:44:23,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 16:44:23,955 INFO L290 TraceCheckUtils]: 0: Hoare triple {4979#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4973#true} is VALID [2022-04-07 16:44:23,955 INFO L290 TraceCheckUtils]: 1: Hoare triple {4973#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4973#true} is VALID [2022-04-07 16:44:23,955 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {4973#true} {4973#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4973#true} is VALID [2022-04-07 16:44:23,956 INFO L272 TraceCheckUtils]: 0: Hoare triple {4973#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4979#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 16:44:23,956 INFO L290 TraceCheckUtils]: 1: Hoare triple {4979#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4973#true} is VALID [2022-04-07 16:44:23,956 INFO L290 TraceCheckUtils]: 2: Hoare triple {4973#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4973#true} is VALID [2022-04-07 16:44:23,956 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {4973#true} {4973#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4973#true} is VALID [2022-04-07 16:44:23,956 INFO L272 TraceCheckUtils]: 4: Hoare triple {4973#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4973#true} is VALID [2022-04-07 16:44:23,957 INFO L290 TraceCheckUtils]: 5: Hoare triple {4973#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (= (store |v_#length_2| |v_main_~#v~0.base_2| (* 4 (let ((.cse0 (mod v_main_~SIZE~0_2 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))))) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {4973#true} is VALID [2022-04-07 16:44:23,957 INFO L290 TraceCheckUtils]: 6: Hoare triple {4973#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4973#true} is VALID [2022-04-07 16:44:23,957 INFO L290 TraceCheckUtils]: 7: Hoare triple {4973#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4973#true} is VALID [2022-04-07 16:44:23,957 INFO L290 TraceCheckUtils]: 8: Hoare triple {4973#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4973#true} is VALID [2022-04-07 16:44:23,957 INFO L290 TraceCheckUtils]: 9: Hoare triple {4973#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4973#true} is VALID [2022-04-07 16:44:23,957 INFO L290 TraceCheckUtils]: 10: Hoare triple {4973#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {4973#true} is VALID [2022-04-07 16:44:23,957 INFO L290 TraceCheckUtils]: 11: Hoare triple {4973#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {4973#true} is VALID [2022-04-07 16:44:23,957 INFO L290 TraceCheckUtils]: 12: Hoare triple {4973#true} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {4973#true} is VALID [2022-04-07 16:44:23,957 INFO L290 TraceCheckUtils]: 13: Hoare triple {4973#true} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {4973#true} is VALID [2022-04-07 16:44:23,957 INFO L290 TraceCheckUtils]: 14: Hoare triple {4973#true} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4973#true} is VALID [2022-04-07 16:44:23,958 INFO L290 TraceCheckUtils]: 15: Hoare triple {4973#true} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4973#true} is VALID [2022-04-07 16:44:23,958 INFO L290 TraceCheckUtils]: 16: Hoare triple {4973#true} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {4973#true} is VALID [2022-04-07 16:44:23,958 INFO L290 TraceCheckUtils]: 17: Hoare triple {4973#true} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {4973#true} is VALID [2022-04-07 16:44:23,958 INFO L290 TraceCheckUtils]: 18: Hoare triple {4973#true} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {4973#true} is VALID [2022-04-07 16:44:23,958 INFO L290 TraceCheckUtils]: 19: Hoare triple {4973#true} [119] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {4978#(not |main_#t~short10|)} is VALID [2022-04-07 16:44:23,958 INFO L290 TraceCheckUtils]: 20: Hoare triple {4978#(not |main_#t~short10|)} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4974#false} is VALID [2022-04-07 16:44:23,959 INFO L290 TraceCheckUtils]: 21: Hoare triple {4974#false} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {4974#false} is VALID [2022-04-07 16:44:23,959 INFO L290 TraceCheckUtils]: 22: Hoare triple {4974#false} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {4974#false} is VALID [2022-04-07 16:44:23,959 INFO L290 TraceCheckUtils]: 23: Hoare triple {4974#false} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {4974#false} is VALID [2022-04-07 16:44:23,959 INFO L290 TraceCheckUtils]: 24: Hoare triple {4974#false} [119] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {4974#false} is VALID [2022-04-07 16:44:23,959 INFO L290 TraceCheckUtils]: 25: Hoare triple {4974#false} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4974#false} is VALID [2022-04-07 16:44:23,959 INFO L290 TraceCheckUtils]: 26: Hoare triple {4974#false} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {4974#false} is VALID [2022-04-07 16:44:23,959 INFO L290 TraceCheckUtils]: 27: Hoare triple {4974#false} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {4974#false} is VALID [2022-04-07 16:44:23,959 INFO L290 TraceCheckUtils]: 28: Hoare triple {4974#false} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {4974#false} is VALID [2022-04-07 16:44:23,959 INFO L290 TraceCheckUtils]: 29: Hoare triple {4974#false} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {4974#false} is VALID [2022-04-07 16:44:23,960 INFO L290 TraceCheckUtils]: 30: Hoare triple {4974#false} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {4974#false} is VALID [2022-04-07 16:44:23,960 INFO L272 TraceCheckUtils]: 31: Hoare triple {4974#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {4974#false} is VALID [2022-04-07 16:44:23,960 INFO L290 TraceCheckUtils]: 32: Hoare triple {4974#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {4974#false} is VALID [2022-04-07 16:44:23,960 INFO L290 TraceCheckUtils]: 33: Hoare triple {4974#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {4974#false} is VALID [2022-04-07 16:44:23,960 INFO L290 TraceCheckUtils]: 34: Hoare triple {4974#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4974#false} is VALID [2022-04-07 16:44:23,960 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2022-04-07 16:44:23,960 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 16:44:23,960 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [870056443] [2022-04-07 16:44:23,961 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [870056443] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-07 16:44:23,961 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-07 16:44:23,961 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-04-07 16:44:23,961 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [126065573] [2022-04-07 16:44:23,961 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-07 16:44:23,961 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 7.0) internal successors, (28), 3 states have internal predecessors, (28), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 35 [2022-04-07 16:44:23,962 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 16:44:23,962 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 7.0) internal successors, (28), 3 states have internal predecessors, (28), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:44:23,984 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 32 edges. 32 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 16:44:23,985 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-04-07 16:44:23,985 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 16:44:23,985 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-04-07 16:44:23,985 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-04-07 16:44:23,985 INFO L87 Difference]: Start difference. First operand 186 states and 245 transitions. Second operand has 4 states, 4 states have (on average 7.0) internal successors, (28), 3 states have internal predecessors, (28), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:44:24,110 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 16:44:24,110 INFO L93 Difference]: Finished difference Result 107 states and 130 transitions. [2022-04-07 16:44:24,110 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-04-07 16:44:24,110 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 7.0) internal successors, (28), 3 states have internal predecessors, (28), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 35 [2022-04-07 16:44:24,110 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 16:44:24,111 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 7.0) internal successors, (28), 3 states have internal predecessors, (28), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:44:24,111 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 35 transitions. [2022-04-07 16:44:24,111 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 7.0) internal successors, (28), 3 states have internal predecessors, (28), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:44:24,111 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 35 transitions. [2022-04-07 16:44:24,112 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 4 states and 35 transitions. [2022-04-07 16:44:24,140 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 35 edges. 35 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 16:44:24,141 INFO L225 Difference]: With dead ends: 107 [2022-04-07 16:44:24,141 INFO L226 Difference]: Without dead ends: 97 [2022-04-07 16:44:24,141 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-04-07 16:44:24,142 INFO L913 BasicCegarLoop]: 32 mSDtfsCounter, 26 mSDsluCounter, 7 mSDsCounter, 0 mSdLazyCounter, 31 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 27 SdHoareTripleChecker+Valid, 39 SdHoareTripleChecker+Invalid, 33 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 31 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-07 16:44:24,142 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [27 Valid, 39 Invalid, 33 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 31 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-07 16:44:24,142 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states. [2022-04-07 16:44:24,144 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 80. [2022-04-07 16:44:24,144 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 16:44:24,144 INFO L82 GeneralOperation]: Start isEquivalent. First operand 97 states. Second operand has 80 states, 72 states have (on average 1.2361111111111112) internal successors, (89), 73 states have internal predecessors, (89), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 16:44:24,144 INFO L74 IsIncluded]: Start isIncluded. First operand 97 states. Second operand has 80 states, 72 states have (on average 1.2361111111111112) internal successors, (89), 73 states have internal predecessors, (89), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 16:44:24,145 INFO L87 Difference]: Start difference. First operand 97 states. Second operand has 80 states, 72 states have (on average 1.2361111111111112) internal successors, (89), 73 states have internal predecessors, (89), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 16:44:24,146 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 16:44:24,146 INFO L93 Difference]: Finished difference Result 97 states and 119 transitions. [2022-04-07 16:44:24,146 INFO L276 IsEmpty]: Start isEmpty. Operand 97 states and 119 transitions. [2022-04-07 16:44:24,146 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 16:44:24,146 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 16:44:24,146 INFO L74 IsIncluded]: Start isIncluded. First operand has 80 states, 72 states have (on average 1.2361111111111112) internal successors, (89), 73 states have internal predecessors, (89), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 97 states. [2022-04-07 16:44:24,147 INFO L87 Difference]: Start difference. First operand has 80 states, 72 states have (on average 1.2361111111111112) internal successors, (89), 73 states have internal predecessors, (89), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 97 states. [2022-04-07 16:44:24,148 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 16:44:24,148 INFO L93 Difference]: Finished difference Result 97 states and 119 transitions. [2022-04-07 16:44:24,148 INFO L276 IsEmpty]: Start isEmpty. Operand 97 states and 119 transitions. [2022-04-07 16:44:24,148 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 16:44:24,148 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 16:44:24,148 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 16:44:24,148 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 16:44:24,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 80 states, 72 states have (on average 1.2361111111111112) internal successors, (89), 73 states have internal predecessors, (89), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 16:44:24,149 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 96 transitions. [2022-04-07 16:44:24,149 INFO L78 Accepts]: Start accepts. Automaton has 80 states and 96 transitions. Word has length 35 [2022-04-07 16:44:24,149 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 16:44:24,150 INFO L478 AbstractCegarLoop]: Abstraction has 80 states and 96 transitions. [2022-04-07 16:44:24,150 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 7.0) internal successors, (28), 3 states have internal predecessors, (28), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:44:24,150 INFO L276 IsEmpty]: Start isEmpty. Operand 80 states and 96 transitions. [2022-04-07 16:44:24,150 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2022-04-07 16:44:24,150 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 16:44:24,150 INFO L499 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 16:44:24,150 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9 [2022-04-07 16:44:24,151 INFO L403 AbstractCegarLoop]: === Iteration 11 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 16:44:24,151 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 16:44:24,151 INFO L85 PathProgramCache]: Analyzing trace with hash 1553999756, now seen corresponding path program 1 times [2022-04-07 16:44:24,151 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 16:44:24,151 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [66607965] [2022-04-07 16:44:24,151 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 16:44:24,151 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 16:44:24,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 16:44:24,515 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 16:44:24,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 16:44:24,521 INFO L290 TraceCheckUtils]: 0: Hoare triple {5383#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {5365#true} is VALID [2022-04-07 16:44:24,521 INFO L290 TraceCheckUtils]: 1: Hoare triple {5365#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5365#true} is VALID [2022-04-07 16:44:24,522 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {5365#true} {5365#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5365#true} is VALID [2022-04-07 16:44:24,522 INFO L272 TraceCheckUtils]: 0: Hoare triple {5365#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5383#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 16:44:24,522 INFO L290 TraceCheckUtils]: 1: Hoare triple {5383#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {5365#true} is VALID [2022-04-07 16:44:24,522 INFO L290 TraceCheckUtils]: 2: Hoare triple {5365#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5365#true} is VALID [2022-04-07 16:44:24,522 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {5365#true} {5365#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5365#true} is VALID [2022-04-07 16:44:24,522 INFO L272 TraceCheckUtils]: 4: Hoare triple {5365#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5365#true} is VALID [2022-04-07 16:44:24,523 INFO L290 TraceCheckUtils]: 5: Hoare triple {5365#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (= (store |v_#length_2| |v_main_~#v~0.base_2| (* 4 (let ((.cse0 (mod v_main_~SIZE~0_2 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))))) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {5370#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-07 16:44:24,523 INFO L290 TraceCheckUtils]: 6: Hoare triple {5370#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5370#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-07 16:44:24,524 INFO L290 TraceCheckUtils]: 7: Hoare triple {5370#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5371#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 16:44:24,524 INFO L290 TraceCheckUtils]: 8: Hoare triple {5371#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5371#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 16:44:24,524 INFO L290 TraceCheckUtils]: 9: Hoare triple {5371#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5372#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 16:44:24,525 INFO L290 TraceCheckUtils]: 10: Hoare triple {5372#(= |main_~#v~0.offset| 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5372#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 16:44:24,525 INFO L290 TraceCheckUtils]: 11: Hoare triple {5372#(= |main_~#v~0.offset| 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5372#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 16:44:24,525 INFO L290 TraceCheckUtils]: 12: Hoare triple {5372#(= |main_~#v~0.offset| 0)} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {5372#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 16:44:24,526 INFO L290 TraceCheckUtils]: 13: Hoare triple {5372#(= |main_~#v~0.offset| 0)} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {5371#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 16:44:24,526 INFO L290 TraceCheckUtils]: 14: Hoare triple {5371#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {5371#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 16:44:24,526 INFO L290 TraceCheckUtils]: 15: Hoare triple {5371#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5371#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 16:44:24,527 INFO L290 TraceCheckUtils]: 16: Hoare triple {5371#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5371#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 16:44:24,527 INFO L290 TraceCheckUtils]: 17: Hoare triple {5371#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5371#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 16:44:24,539 INFO L290 TraceCheckUtils]: 18: Hoare triple {5371#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {5371#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 16:44:24,540 INFO L290 TraceCheckUtils]: 19: Hoare triple {5371#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {5373#(and (= |main_~#v~0.offset| 0) (= (* main_~j~0 4) 8))} is VALID [2022-04-07 16:44:24,541 INFO L290 TraceCheckUtils]: 20: Hoare triple {5373#(and (= |main_~#v~0.offset| 0) (= (* main_~j~0 4) 8))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {5374#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} is VALID [2022-04-07 16:44:24,541 INFO L290 TraceCheckUtils]: 21: Hoare triple {5374#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5374#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} is VALID [2022-04-07 16:44:24,541 INFO L290 TraceCheckUtils]: 22: Hoare triple {5374#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5374#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} is VALID [2022-04-07 16:44:24,542 INFO L290 TraceCheckUtils]: 23: Hoare triple {5374#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5374#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} is VALID [2022-04-07 16:44:24,542 INFO L290 TraceCheckUtils]: 24: Hoare triple {5374#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {5374#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} is VALID [2022-04-07 16:44:24,543 INFO L290 TraceCheckUtils]: 25: Hoare triple {5374#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {5375#(and (= |main_~#v~0.offset| 0) (= 0 (* main_~i~0 4)))} is VALID [2022-04-07 16:44:24,543 INFO L290 TraceCheckUtils]: 26: Hoare triple {5375#(and (= |main_~#v~0.offset| 0) (= 0 (* main_~i~0 4)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5375#(and (= |main_~#v~0.offset| 0) (= 0 (* main_~i~0 4)))} is VALID [2022-04-07 16:44:24,543 INFO L290 TraceCheckUtils]: 27: Hoare triple {5375#(and (= |main_~#v~0.offset| 0) (= 0 (* main_~i~0 4)))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5376#(and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4)) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} is VALID [2022-04-07 16:44:24,544 INFO L290 TraceCheckUtils]: 28: Hoare triple {5376#(and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4)) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5377#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0))} is VALID [2022-04-07 16:44:24,545 INFO L290 TraceCheckUtils]: 29: Hoare triple {5377#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {5378#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:44:24,545 INFO L290 TraceCheckUtils]: 30: Hoare triple {5378#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {5378#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:44:24,546 INFO L290 TraceCheckUtils]: 31: Hoare triple {5378#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {5378#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:44:24,546 INFO L290 TraceCheckUtils]: 32: Hoare triple {5378#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {5379#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-07 16:44:24,546 INFO L290 TraceCheckUtils]: 33: Hoare triple {5379#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {5380#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-07 16:44:24,547 INFO L272 TraceCheckUtils]: 34: Hoare triple {5380#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {5381#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-07 16:44:24,547 INFO L290 TraceCheckUtils]: 35: Hoare triple {5381#(not (= |__VERIFIER_assert_#in~cond| 0))} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {5382#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-07 16:44:24,548 INFO L290 TraceCheckUtils]: 36: Hoare triple {5382#(not (= __VERIFIER_assert_~cond 0))} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {5366#false} is VALID [2022-04-07 16:44:24,548 INFO L290 TraceCheckUtils]: 37: Hoare triple {5366#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5366#false} is VALID [2022-04-07 16:44:24,548 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 22 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-07 16:44:24,548 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 16:44:24,548 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [66607965] [2022-04-07 16:44:24,548 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [66607965] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 16:44:24,548 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1874783063] [2022-04-07 16:44:24,548 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 16:44:24,548 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 16:44:24,549 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 16:44:24,549 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 16:44:24,551 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2022-04-07 16:44:24,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 16:44:24,600 INFO L263 TraceCheckSpWp]: Trace formula consists of 153 conjuncts, 21 conjunts are in the unsatisfiable core [2022-04-07 16:44:24,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 16:44:24,619 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 16:44:25,077 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-04-07 16:44:25,078 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-04-07 16:44:25,211 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-04-07 16:44:25,212 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 10 [2022-04-07 16:44:25,293 INFO L272 TraceCheckUtils]: 0: Hoare triple {5365#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5365#true} is VALID [2022-04-07 16:44:25,293 INFO L290 TraceCheckUtils]: 1: Hoare triple {5365#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {5365#true} is VALID [2022-04-07 16:44:25,293 INFO L290 TraceCheckUtils]: 2: Hoare triple {5365#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5365#true} is VALID [2022-04-07 16:44:25,293 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {5365#true} {5365#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5365#true} is VALID [2022-04-07 16:44:25,293 INFO L272 TraceCheckUtils]: 4: Hoare triple {5365#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5365#true} is VALID [2022-04-07 16:44:25,293 INFO L290 TraceCheckUtils]: 5: Hoare triple {5365#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (= (store |v_#length_2| |v_main_~#v~0.base_2| (* 4 (let ((.cse0 (mod v_main_~SIZE~0_2 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))))) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {5372#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 16:44:25,294 INFO L290 TraceCheckUtils]: 6: Hoare triple {5372#(= |main_~#v~0.offset| 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5372#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 16:44:25,294 INFO L290 TraceCheckUtils]: 7: Hoare triple {5372#(= |main_~#v~0.offset| 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5372#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 16:44:25,294 INFO L290 TraceCheckUtils]: 8: Hoare triple {5372#(= |main_~#v~0.offset| 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5372#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 16:44:25,295 INFO L290 TraceCheckUtils]: 9: Hoare triple {5372#(= |main_~#v~0.offset| 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5372#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 16:44:25,295 INFO L290 TraceCheckUtils]: 10: Hoare triple {5372#(= |main_~#v~0.offset| 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5372#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 16:44:25,295 INFO L290 TraceCheckUtils]: 11: Hoare triple {5372#(= |main_~#v~0.offset| 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5372#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 16:44:25,296 INFO L290 TraceCheckUtils]: 12: Hoare triple {5372#(= |main_~#v~0.offset| 0)} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {5372#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 16:44:25,296 INFO L290 TraceCheckUtils]: 13: Hoare triple {5372#(= |main_~#v~0.offset| 0)} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {5426#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} is VALID [2022-04-07 16:44:25,296 INFO L290 TraceCheckUtils]: 14: Hoare triple {5426#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {5426#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} is VALID [2022-04-07 16:44:25,297 INFO L290 TraceCheckUtils]: 15: Hoare triple {5426#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5426#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} is VALID [2022-04-07 16:44:25,297 INFO L290 TraceCheckUtils]: 16: Hoare triple {5426#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5426#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} is VALID [2022-04-07 16:44:25,298 INFO L290 TraceCheckUtils]: 17: Hoare triple {5426#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5426#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} is VALID [2022-04-07 16:44:25,298 INFO L290 TraceCheckUtils]: 18: Hoare triple {5426#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {5426#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} is VALID [2022-04-07 16:44:25,299 INFO L290 TraceCheckUtils]: 19: Hoare triple {5426#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {5445#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2))} is VALID [2022-04-07 16:44:25,299 INFO L290 TraceCheckUtils]: 20: Hoare triple {5445#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {5449#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} is VALID [2022-04-07 16:44:25,300 INFO L290 TraceCheckUtils]: 21: Hoare triple {5449#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5449#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} is VALID [2022-04-07 16:44:25,300 INFO L290 TraceCheckUtils]: 22: Hoare triple {5449#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5449#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} is VALID [2022-04-07 16:44:25,300 INFO L290 TraceCheckUtils]: 23: Hoare triple {5449#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5449#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} is VALID [2022-04-07 16:44:25,301 INFO L290 TraceCheckUtils]: 24: Hoare triple {5449#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {5449#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} is VALID [2022-04-07 16:44:25,301 INFO L290 TraceCheckUtils]: 25: Hoare triple {5449#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {5465#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0))} is VALID [2022-04-07 16:44:25,302 INFO L290 TraceCheckUtils]: 26: Hoare triple {5465#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5469#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} is VALID [2022-04-07 16:44:25,303 INFO L290 TraceCheckUtils]: 27: Hoare triple {5469#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5376#(and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4)) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} is VALID [2022-04-07 16:44:25,303 INFO L290 TraceCheckUtils]: 28: Hoare triple {5376#(and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4)) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5377#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0))} is VALID [2022-04-07 16:44:25,304 INFO L290 TraceCheckUtils]: 29: Hoare triple {5377#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {5378#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:44:25,304 INFO L290 TraceCheckUtils]: 30: Hoare triple {5378#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {5378#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:44:25,305 INFO L290 TraceCheckUtils]: 31: Hoare triple {5378#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {5378#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:44:25,305 INFO L290 TraceCheckUtils]: 32: Hoare triple {5378#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {5379#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-07 16:44:25,306 INFO L290 TraceCheckUtils]: 33: Hoare triple {5379#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {5380#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-07 16:44:25,306 INFO L272 TraceCheckUtils]: 34: Hoare triple {5380#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {5494#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 16:44:25,307 INFO L290 TraceCheckUtils]: 35: Hoare triple {5494#(<= 1 |__VERIFIER_assert_#in~cond|)} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {5498#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 16:44:25,307 INFO L290 TraceCheckUtils]: 36: Hoare triple {5498#(<= 1 __VERIFIER_assert_~cond)} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {5366#false} is VALID [2022-04-07 16:44:25,307 INFO L290 TraceCheckUtils]: 37: Hoare triple {5366#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5366#false} is VALID [2022-04-07 16:44:25,307 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 3 proven. 11 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2022-04-07 16:44:25,308 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-07 16:44:25,649 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 41 treesize of output 35 [2022-04-07 16:44:25,686 INFO L356 Elim1Store]: treesize reduction 21, result has 43.2 percent of original size [2022-04-07 16:44:25,687 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 93 treesize of output 90 [2022-04-07 16:44:25,901 INFO L290 TraceCheckUtils]: 37: Hoare triple {5366#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5366#false} is VALID [2022-04-07 16:44:25,902 INFO L290 TraceCheckUtils]: 36: Hoare triple {5498#(<= 1 __VERIFIER_assert_~cond)} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {5366#false} is VALID [2022-04-07 16:44:25,902 INFO L290 TraceCheckUtils]: 35: Hoare triple {5494#(<= 1 |__VERIFIER_assert_#in~cond|)} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {5498#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 16:44:25,903 INFO L272 TraceCheckUtils]: 34: Hoare triple {5380#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {5494#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 16:44:25,903 INFO L290 TraceCheckUtils]: 33: Hoare triple {5517#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {5380#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-07 16:44:25,904 INFO L290 TraceCheckUtils]: 32: Hoare triple {5521#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {5517#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} is VALID [2022-04-07 16:44:25,904 INFO L290 TraceCheckUtils]: 31: Hoare triple {5521#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {5521#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-07 16:44:25,904 INFO L290 TraceCheckUtils]: 30: Hoare triple {5521#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {5521#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-07 16:44:25,905 INFO L290 TraceCheckUtils]: 29: Hoare triple {5531#(forall ((v_ArrVal_171 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_171) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_171) (+ |main_~#v~0.offset| 4))) (not (<= main_~key~0 v_ArrVal_171))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {5521#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-07 16:44:25,905 INFO L290 TraceCheckUtils]: 28: Hoare triple {5535#(or (forall ((v_ArrVal_171 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_171) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_171) (+ |main_~#v~0.offset| 4))) (not (<= main_~key~0 v_ArrVal_171)))) |main_#t~short10|)} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5531#(forall ((v_ArrVal_171 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_171) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_171) (+ |main_~#v~0.offset| 4))) (not (<= main_~key~0 v_ArrVal_171))))} is VALID [2022-04-07 16:44:25,906 INFO L290 TraceCheckUtils]: 27: Hoare triple {5539#(or (not |main_#t~short10|) (= 0 (* main_~i~0 4)))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5535#(or (forall ((v_ArrVal_171 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_171) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_171) (+ |main_~#v~0.offset| 4))) (not (<= main_~key~0 v_ArrVal_171)))) |main_#t~short10|)} is VALID [2022-04-07 16:44:25,907 INFO L290 TraceCheckUtils]: 26: Hoare triple {5543#(or (not (<= 0 main_~i~0)) (= 0 (* main_~i~0 4)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5539#(or (not |main_#t~short10|) (= 0 (* main_~i~0 4)))} is VALID [2022-04-07 16:44:25,907 INFO L290 TraceCheckUtils]: 25: Hoare triple {5547#(<= main_~i~0 1)} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {5543#(or (not (<= 0 main_~i~0)) (= 0 (* main_~i~0 4)))} is VALID [2022-04-07 16:44:25,907 INFO L290 TraceCheckUtils]: 24: Hoare triple {5547#(<= main_~i~0 1)} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {5547#(<= main_~i~0 1)} is VALID [2022-04-07 16:44:25,907 INFO L290 TraceCheckUtils]: 23: Hoare triple {5547#(<= main_~i~0 1)} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5547#(<= main_~i~0 1)} is VALID [2022-04-07 16:44:25,908 INFO L290 TraceCheckUtils]: 22: Hoare triple {5547#(<= main_~i~0 1)} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5547#(<= main_~i~0 1)} is VALID [2022-04-07 16:44:25,908 INFO L290 TraceCheckUtils]: 21: Hoare triple {5547#(<= main_~i~0 1)} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5547#(<= main_~i~0 1)} is VALID [2022-04-07 16:44:25,909 INFO L290 TraceCheckUtils]: 20: Hoare triple {5563#(<= main_~j~0 2)} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {5547#(<= main_~i~0 1)} is VALID [2022-04-07 16:44:25,909 INFO L290 TraceCheckUtils]: 19: Hoare triple {5567#(<= main_~j~0 1)} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {5563#(<= main_~j~0 2)} is VALID [2022-04-07 16:44:25,909 INFO L290 TraceCheckUtils]: 18: Hoare triple {5567#(<= main_~j~0 1)} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {5567#(<= main_~j~0 1)} is VALID [2022-04-07 16:44:25,909 INFO L290 TraceCheckUtils]: 17: Hoare triple {5567#(<= main_~j~0 1)} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5567#(<= main_~j~0 1)} is VALID [2022-04-07 16:44:25,910 INFO L290 TraceCheckUtils]: 16: Hoare triple {5567#(<= main_~j~0 1)} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5567#(<= main_~j~0 1)} is VALID [2022-04-07 16:44:25,910 INFO L290 TraceCheckUtils]: 15: Hoare triple {5567#(<= main_~j~0 1)} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5567#(<= main_~j~0 1)} is VALID [2022-04-07 16:44:25,910 INFO L290 TraceCheckUtils]: 14: Hoare triple {5567#(<= main_~j~0 1)} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {5567#(<= main_~j~0 1)} is VALID [2022-04-07 16:44:25,910 INFO L290 TraceCheckUtils]: 13: Hoare triple {5365#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {5567#(<= main_~j~0 1)} is VALID [2022-04-07 16:44:25,910 INFO L290 TraceCheckUtils]: 12: Hoare triple {5365#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {5365#true} is VALID [2022-04-07 16:44:25,910 INFO L290 TraceCheckUtils]: 11: Hoare triple {5365#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5365#true} is VALID [2022-04-07 16:44:25,910 INFO L290 TraceCheckUtils]: 10: Hoare triple {5365#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5365#true} is VALID [2022-04-07 16:44:25,911 INFO L290 TraceCheckUtils]: 9: Hoare triple {5365#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5365#true} is VALID [2022-04-07 16:44:25,911 INFO L290 TraceCheckUtils]: 8: Hoare triple {5365#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5365#true} is VALID [2022-04-07 16:44:25,911 INFO L290 TraceCheckUtils]: 7: Hoare triple {5365#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5365#true} is VALID [2022-04-07 16:44:25,911 INFO L290 TraceCheckUtils]: 6: Hoare triple {5365#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5365#true} is VALID [2022-04-07 16:44:25,911 INFO L290 TraceCheckUtils]: 5: Hoare triple {5365#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (= (store |v_#length_2| |v_main_~#v~0.base_2| (* 4 (let ((.cse0 (mod v_main_~SIZE~0_2 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))))) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {5365#true} is VALID [2022-04-07 16:44:25,911 INFO L272 TraceCheckUtils]: 4: Hoare triple {5365#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5365#true} is VALID [2022-04-07 16:44:25,911 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {5365#true} {5365#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5365#true} is VALID [2022-04-07 16:44:25,911 INFO L290 TraceCheckUtils]: 2: Hoare triple {5365#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5365#true} is VALID [2022-04-07 16:44:25,911 INFO L290 TraceCheckUtils]: 1: Hoare triple {5365#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {5365#true} is VALID [2022-04-07 16:44:25,911 INFO L272 TraceCheckUtils]: 0: Hoare triple {5365#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5365#true} is VALID [2022-04-07 16:44:25,912 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 1 proven. 13 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2022-04-07 16:44:25,912 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1874783063] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-07 16:44:25,912 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-07 16:44:25,912 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 15, 14] total 32 [2022-04-07 16:44:25,913 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1923478801] [2022-04-07 16:44:25,913 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-07 16:44:25,913 INFO L78 Accepts]: Start accepts. Automaton has has 32 states, 31 states have (on average 2.5161290322580645) internal successors, (78), 29 states have internal predecessors, (78), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 38 [2022-04-07 16:44:25,914 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 16:44:25,914 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 32 states, 31 states have (on average 2.5161290322580645) internal successors, (78), 29 states have internal predecessors, (78), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:44:25,984 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 84 edges. 84 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 16:44:25,984 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 32 states [2022-04-07 16:44:25,984 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 16:44:25,985 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2022-04-07 16:44:25,985 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=130, Invalid=862, Unknown=0, NotChecked=0, Total=992 [2022-04-07 16:44:25,985 INFO L87 Difference]: Start difference. First operand 80 states and 96 transitions. Second operand has 32 states, 31 states have (on average 2.5161290322580645) internal successors, (78), 29 states have internal predecessors, (78), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:44:29,994 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 16:44:29,994 INFO L93 Difference]: Finished difference Result 169 states and 204 transitions. [2022-04-07 16:44:29,994 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2022-04-07 16:44:29,994 INFO L78 Accepts]: Start accepts. Automaton has has 32 states, 31 states have (on average 2.5161290322580645) internal successors, (78), 29 states have internal predecessors, (78), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 38 [2022-04-07 16:44:29,994 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 16:44:29,995 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32 states, 31 states have (on average 2.5161290322580645) internal successors, (78), 29 states have internal predecessors, (78), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:44:29,996 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 184 transitions. [2022-04-07 16:44:29,996 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32 states, 31 states have (on average 2.5161290322580645) internal successors, (78), 29 states have internal predecessors, (78), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:44:29,998 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 184 transitions. [2022-04-07 16:44:29,998 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 54 states and 184 transitions. [2022-04-07 16:44:30,172 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 184 edges. 184 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 16:44:30,174 INFO L225 Difference]: With dead ends: 169 [2022-04-07 16:44:30,174 INFO L226 Difference]: Without dead ends: 169 [2022-04-07 16:44:30,175 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 150 GetRequests, 60 SyntacticMatches, 9 SemanticMatches, 81 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1949 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=1155, Invalid=5651, Unknown=0, NotChecked=0, Total=6806 [2022-04-07 16:44:30,176 INFO L913 BasicCegarLoop]: 23 mSDtfsCounter, 288 mSDsluCounter, 58 mSDsCounter, 0 mSdLazyCounter, 1082 mSolverCounterSat, 262 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 288 SdHoareTripleChecker+Valid, 81 SdHoareTripleChecker+Invalid, 1476 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 262 IncrementalHoareTripleChecker+Valid, 1082 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 132 IncrementalHoareTripleChecker+Unchecked, 1.4s IncrementalHoareTripleChecker+Time [2022-04-07 16:44:30,176 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [288 Valid, 81 Invalid, 1476 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [262 Valid, 1082 Invalid, 0 Unknown, 132 Unchecked, 1.4s Time] [2022-04-07 16:44:30,176 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 169 states. [2022-04-07 16:44:30,178 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 169 to 86. [2022-04-07 16:44:30,178 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 16:44:30,178 INFO L82 GeneralOperation]: Start isEquivalent. First operand 169 states. Second operand has 86 states, 78 states have (on average 1.2307692307692308) internal successors, (96), 79 states have internal predecessors, (96), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 16:44:30,178 INFO L74 IsIncluded]: Start isIncluded. First operand 169 states. Second operand has 86 states, 78 states have (on average 1.2307692307692308) internal successors, (96), 79 states have internal predecessors, (96), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 16:44:30,179 INFO L87 Difference]: Start difference. First operand 169 states. Second operand has 86 states, 78 states have (on average 1.2307692307692308) internal successors, (96), 79 states have internal predecessors, (96), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 16:44:30,181 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 16:44:30,181 INFO L93 Difference]: Finished difference Result 169 states and 204 transitions. [2022-04-07 16:44:30,181 INFO L276 IsEmpty]: Start isEmpty. Operand 169 states and 204 transitions. [2022-04-07 16:44:30,181 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 16:44:30,181 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 16:44:30,181 INFO L74 IsIncluded]: Start isIncluded. First operand has 86 states, 78 states have (on average 1.2307692307692308) internal successors, (96), 79 states have internal predecessors, (96), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 169 states. [2022-04-07 16:44:30,182 INFO L87 Difference]: Start difference. First operand has 86 states, 78 states have (on average 1.2307692307692308) internal successors, (96), 79 states have internal predecessors, (96), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 169 states. [2022-04-07 16:44:30,184 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 16:44:30,184 INFO L93 Difference]: Finished difference Result 169 states and 204 transitions. [2022-04-07 16:44:30,184 INFO L276 IsEmpty]: Start isEmpty. Operand 169 states and 204 transitions. [2022-04-07 16:44:30,184 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 16:44:30,184 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 16:44:30,184 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 16:44:30,184 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 16:44:30,185 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 86 states, 78 states have (on average 1.2307692307692308) internal successors, (96), 79 states have internal predecessors, (96), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 16:44:30,185 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 103 transitions. [2022-04-07 16:44:30,185 INFO L78 Accepts]: Start accepts. Automaton has 86 states and 103 transitions. Word has length 38 [2022-04-07 16:44:30,185 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 16:44:30,186 INFO L478 AbstractCegarLoop]: Abstraction has 86 states and 103 transitions. [2022-04-07 16:44:30,186 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 32 states, 31 states have (on average 2.5161290322580645) internal successors, (78), 29 states have internal predecessors, (78), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 16:44:30,186 INFO L276 IsEmpty]: Start isEmpty. Operand 86 states and 103 transitions. [2022-04-07 16:44:30,186 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2022-04-07 16:44:30,186 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 16:44:30,186 INFO L499 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 16:44:30,219 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Forceful destruction successful, exit code 0 [2022-04-07 16:44:30,387 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable10 [2022-04-07 16:44:30,387 INFO L403 AbstractCegarLoop]: === Iteration 12 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 16:44:30,387 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 16:44:30,387 INFO L85 PathProgramCache]: Analyzing trace with hash -1626243309, now seen corresponding path program 3 times [2022-04-07 16:44:30,388 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 16:44:30,388 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1166240788] [2022-04-07 16:44:30,388 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 16:44:30,388 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 16:44:30,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 16:44:31,034 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 16:44:31,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 16:44:31,040 INFO L290 TraceCheckUtils]: 0: Hoare triple {6352#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {6327#true} is VALID [2022-04-07 16:44:31,040 INFO L290 TraceCheckUtils]: 1: Hoare triple {6327#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6327#true} is VALID [2022-04-07 16:44:31,041 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {6327#true} {6327#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6327#true} is VALID [2022-04-07 16:44:31,041 INFO L272 TraceCheckUtils]: 0: Hoare triple {6327#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6352#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 16:44:31,041 INFO L290 TraceCheckUtils]: 1: Hoare triple {6352#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {6327#true} is VALID [2022-04-07 16:44:31,041 INFO L290 TraceCheckUtils]: 2: Hoare triple {6327#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6327#true} is VALID [2022-04-07 16:44:31,041 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {6327#true} {6327#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6327#true} is VALID [2022-04-07 16:44:31,041 INFO L272 TraceCheckUtils]: 4: Hoare triple {6327#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6327#true} is VALID [2022-04-07 16:44:31,042 INFO L290 TraceCheckUtils]: 5: Hoare triple {6327#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (= (store |v_#length_2| |v_main_~#v~0.base_2| (* 4 (let ((.cse0 (mod v_main_~SIZE~0_2 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))))) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {6332#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-07 16:44:31,043 INFO L290 TraceCheckUtils]: 6: Hoare triple {6332#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {6332#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-07 16:44:31,043 INFO L290 TraceCheckUtils]: 7: Hoare triple {6332#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {6333#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 16:44:31,044 INFO L290 TraceCheckUtils]: 8: Hoare triple {6333#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {6333#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 16:44:31,044 INFO L290 TraceCheckUtils]: 9: Hoare triple {6333#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {6334#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-07 16:44:31,045 INFO L290 TraceCheckUtils]: 10: Hoare triple {6334#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2) (<= 2 main_~j~0))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {6334#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-07 16:44:31,045 INFO L290 TraceCheckUtils]: 11: Hoare triple {6334#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2) (<= 2 main_~j~0))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {6335#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 16:44:31,045 INFO L290 TraceCheckUtils]: 12: Hoare triple {6335#(= |main_~#v~0.offset| 0)} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {6335#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 16:44:31,046 INFO L290 TraceCheckUtils]: 13: Hoare triple {6335#(= |main_~#v~0.offset| 0)} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {6333#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 16:44:31,047 INFO L290 TraceCheckUtils]: 14: Hoare triple {6333#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {6336#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (or (<= (+ main_~i~0 1) 0) (= 0 (* main_~i~0 4))))} is VALID [2022-04-07 16:44:31,047 INFO L290 TraceCheckUtils]: 15: Hoare triple {6336#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (or (<= (+ main_~i~0 1) 0) (= 0 (* main_~i~0 4))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {6337#(or (and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (not |main_#t~short10|))} is VALID [2022-04-07 16:44:31,048 INFO L290 TraceCheckUtils]: 16: Hoare triple {6337#(or (and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (not |main_#t~short10|))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6338#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (or (not |main_#t~short10|) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))))) (= 0 (* main_~i~0 4)))} is VALID [2022-04-07 16:44:31,048 INFO L290 TraceCheckUtils]: 17: Hoare triple {6338#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (or (not |main_#t~short10|) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))))) (= 0 (* main_~i~0 4)))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6339#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 0 (* main_~i~0 4)))} is VALID [2022-04-07 16:44:31,049 INFO L290 TraceCheckUtils]: 18: Hoare triple {6339#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 0 (* main_~i~0 4)))} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {6340#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)))) (= 0 (* main_~i~0 4)))} is VALID [2022-04-07 16:44:31,050 INFO L290 TraceCheckUtils]: 19: Hoare triple {6340#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)))) (= 0 (* main_~i~0 4)))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {6341#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (or (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= 0 main_~i~0)))} is VALID [2022-04-07 16:44:31,051 INFO L290 TraceCheckUtils]: 20: Hoare triple {6341#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (or (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= 0 main_~i~0)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {6342#(and (= |main_~#v~0.offset| 0) (or (and (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))) |main_#t~short10|) (= (+ (- 1) main_~j~0) 0))} is VALID [2022-04-07 16:44:31,051 INFO L290 TraceCheckUtils]: 21: Hoare triple {6342#(and (= |main_~#v~0.offset| 0) (or (and (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))) |main_#t~short10|) (= (+ (- 1) main_~j~0) 0))} [119] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {6343#(and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:44:31,052 INFO L290 TraceCheckUtils]: 22: Hoare triple {6343#(and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6343#(and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:44:31,053 INFO L290 TraceCheckUtils]: 23: Hoare triple {6343#(and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {6344#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:44:31,053 INFO L290 TraceCheckUtils]: 24: Hoare triple {6344#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {6345#(and (= |main_~#v~0.offset| 0) (= (* main_~j~0 4) 8) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))} is VALID [2022-04-07 16:44:31,054 INFO L290 TraceCheckUtils]: 25: Hoare triple {6345#(and (= |main_~#v~0.offset| 0) (= (* main_~j~0 4) 8) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {6346#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 4 (* main_~i~0 4)))} is VALID [2022-04-07 16:44:31,054 INFO L290 TraceCheckUtils]: 26: Hoare triple {6346#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 4 (* main_~i~0 4)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {6346#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 4 (* main_~i~0 4)))} is VALID [2022-04-07 16:44:31,055 INFO L290 TraceCheckUtils]: 27: Hoare triple {6346#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 4 (* main_~i~0 4)))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6346#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 4 (* main_~i~0 4)))} is VALID [2022-04-07 16:44:31,055 INFO L290 TraceCheckUtils]: 28: Hoare triple {6346#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 4 (* main_~i~0 4)))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6346#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 4 (* main_~i~0 4)))} is VALID [2022-04-07 16:44:31,056 INFO L290 TraceCheckUtils]: 29: Hoare triple {6346#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 4 (* main_~i~0 4)))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {6347#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:44:31,057 INFO L290 TraceCheckUtils]: 30: Hoare triple {6347#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {6347#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:44:31,057 INFO L290 TraceCheckUtils]: 31: Hoare triple {6347#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {6347#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 16:44:31,057 INFO L290 TraceCheckUtils]: 32: Hoare triple {6347#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {6348#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-07 16:44:31,058 INFO L290 TraceCheckUtils]: 33: Hoare triple {6348#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {6349#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} is VALID [2022-04-07 16:44:31,059 INFO L272 TraceCheckUtils]: 34: Hoare triple {6349#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {6350#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-07 16:44:31,059 INFO L290 TraceCheckUtils]: 35: Hoare triple {6350#(not (= |__VERIFIER_assert_#in~cond| 0))} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {6351#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-07 16:44:31,059 INFO L290 TraceCheckUtils]: 36: Hoare triple {6351#(not (= __VERIFIER_assert_~cond 0))} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {6328#false} is VALID [2022-04-07 16:44:31,059 INFO L290 TraceCheckUtils]: 37: Hoare triple {6328#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6328#false} is VALID [2022-04-07 16:44:31,060 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 16:44:31,060 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 16:44:31,060 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1166240788] [2022-04-07 16:44:31,060 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1166240788] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 16:44:31,060 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1620800182] [2022-04-07 16:44:31,060 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-04-07 16:44:31,060 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 16:44:31,060 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 16:44:31,061 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 16:44:31,063 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2022-04-07 16:44:31,150 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2022-04-07 16:44:31,150 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-07 16:44:31,151 INFO L263 TraceCheckSpWp]: Trace formula consists of 150 conjuncts, 31 conjunts are in the unsatisfiable core [2022-04-07 16:44:31,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 16:44:31,162 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 16:44:31,365 INFO L356 Elim1Store]: treesize reduction 39, result has 22.0 percent of original size [2022-04-07 16:44:31,366 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 30 [2022-04-07 16:44:31,649 INFO L356 Elim1Store]: treesize reduction 109, result has 9.2 percent of original size [2022-04-07 16:44:31,649 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 49 treesize of output 30 [2022-04-07 16:44:32,065 INFO L356 Elim1Store]: treesize reduction 76, result has 22.4 percent of original size [2022-04-07 16:44:32,065 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 32 treesize of output 34 [2022-04-07 16:44:32,404 INFO L356 Elim1Store]: treesize reduction 36, result has 7.7 percent of original size [2022-04-07 16:44:32,404 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 35 treesize of output 13 [2022-04-07 16:44:32,491 INFO L272 TraceCheckUtils]: 0: Hoare triple {6327#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6327#true} is VALID [2022-04-07 16:44:32,491 INFO L290 TraceCheckUtils]: 1: Hoare triple {6327#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {6327#true} is VALID [2022-04-07 16:44:32,491 INFO L290 TraceCheckUtils]: 2: Hoare triple {6327#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6327#true} is VALID [2022-04-07 16:44:32,491 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {6327#true} {6327#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6327#true} is VALID [2022-04-07 16:44:32,491 INFO L272 TraceCheckUtils]: 4: Hoare triple {6327#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6327#true} is VALID [2022-04-07 16:44:32,491 INFO L290 TraceCheckUtils]: 5: Hoare triple {6327#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (= (store |v_#length_2| |v_main_~#v~0.base_2| (* 4 (let ((.cse0 (mod v_main_~SIZE~0_2 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))))) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {6327#true} is VALID [2022-04-07 16:44:32,491 INFO L290 TraceCheckUtils]: 6: Hoare triple {6327#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {6327#true} is VALID [2022-04-07 16:44:32,491 INFO L290 TraceCheckUtils]: 7: Hoare triple {6327#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {6327#true} is VALID [2022-04-07 16:44:32,491 INFO L290 TraceCheckUtils]: 8: Hoare triple {6327#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {6327#true} is VALID [2022-04-07 16:44:32,491 INFO L290 TraceCheckUtils]: 9: Hoare triple {6327#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {6327#true} is VALID [2022-04-07 16:44:32,492 INFO L290 TraceCheckUtils]: 10: Hoare triple {6327#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {6327#true} is VALID [2022-04-07 16:44:32,492 INFO L290 TraceCheckUtils]: 11: Hoare triple {6327#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {6327#true} is VALID [2022-04-07 16:44:32,492 INFO L290 TraceCheckUtils]: 12: Hoare triple {6327#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {6327#true} is VALID [2022-04-07 16:44:32,492 INFO L290 TraceCheckUtils]: 13: Hoare triple {6327#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {6395#(= main_~j~0 1)} is VALID [2022-04-07 16:44:32,493 INFO L290 TraceCheckUtils]: 14: Hoare triple {6395#(= main_~j~0 1)} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {6399#(and (= (+ (- 1) main_~j~0) main_~i~0) (= main_~j~0 1))} is VALID [2022-04-07 16:44:32,496 INFO L290 TraceCheckUtils]: 15: Hoare triple {6399#(and (= (+ (- 1) main_~j~0) main_~i~0) (= main_~j~0 1))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {6399#(and (= (+ (- 1) main_~j~0) main_~i~0) (= main_~j~0 1))} is VALID [2022-04-07 16:44:32,496 INFO L290 TraceCheckUtils]: 16: Hoare triple {6399#(and (= (+ (- 1) main_~j~0) main_~i~0) (= main_~j~0 1))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6406#(and (= (+ (- 1) main_~j~0) main_~i~0) (= main_~j~0 1) (or (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (not |main_#t~short10|)))} is VALID [2022-04-07 16:44:32,507 INFO L290 TraceCheckUtils]: 17: Hoare triple {6406#(and (= (+ (- 1) main_~j~0) main_~i~0) (= main_~j~0 1) (or (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (not |main_#t~short10|)))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6410#(and (= main_~j~0 1) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= main_~j~0 (+ main_~i~0 1)))} is VALID [2022-04-07 16:44:32,508 INFO L290 TraceCheckUtils]: 18: Hoare triple {6410#(and (= main_~j~0 1) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= main_~j~0 (+ main_~i~0 1)))} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {6414#(and (= main_~j~0 1) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)))) (= main_~j~0 (+ main_~i~0 1)))} is VALID [2022-04-07 16:44:32,508 INFO L290 TraceCheckUtils]: 19: Hoare triple {6414#(and (= main_~j~0 1) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)))) (= main_~j~0 (+ main_~i~0 1)))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {6418#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (<= main_~j~0 (+ main_~i~0 2)))} is VALID [2022-04-07 16:44:32,509 INFO L290 TraceCheckUtils]: 20: Hoare triple {6418#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (<= main_~j~0 (+ main_~i~0 2)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {6422#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (<= main_~j~0 (+ main_~i~0 2)) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} is VALID [2022-04-07 16:44:32,509 INFO L290 TraceCheckUtils]: 21: Hoare triple {6422#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (<= main_~j~0 (+ main_~i~0 2)) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} [119] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {6426#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (< main_~i~0 0) (<= main_~j~0 (+ main_~i~0 2)))} is VALID [2022-04-07 16:44:32,510 INFO L290 TraceCheckUtils]: 22: Hoare triple {6426#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (< main_~i~0 0) (<= main_~j~0 (+ main_~i~0 2)))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6426#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (< main_~i~0 0) (<= main_~j~0 (+ main_~i~0 2)))} is VALID [2022-04-07 16:44:32,512 INFO L290 TraceCheckUtils]: 23: Hoare triple {6426#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (< main_~i~0 0) (<= main_~j~0 (+ main_~i~0 2)))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {6433#(and (= main_~j~0 1) (exists ((main_~i~0 Int)) (and (< main_~i~0 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (<= main_~j~0 (+ main_~i~0 2)))))} is VALID [2022-04-07 16:44:32,512 INFO L290 TraceCheckUtils]: 24: Hoare triple {6433#(and (= main_~j~0 1) (exists ((main_~i~0 Int)) (and (< main_~i~0 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (<= main_~j~0 (+ main_~i~0 2)))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {6437#(and (= main_~j~0 2) (exists ((main_~i~0 Int)) (and (< main_~i~0 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ main_~i~0 1)))))} is VALID [2022-04-07 16:44:32,513 INFO L290 TraceCheckUtils]: 25: Hoare triple {6437#(and (= main_~j~0 2) (exists ((main_~i~0 Int)) (and (< main_~i~0 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ main_~i~0 1)))))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {6441#(and (= 2 (+ main_~i~0 1)) (exists ((v_main_~i~0_27 Int)) (and (< v_main_~i~0_27 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_27 1)))))} is VALID [2022-04-07 16:44:32,514 INFO L290 TraceCheckUtils]: 26: Hoare triple {6441#(and (= 2 (+ main_~i~0 1)) (exists ((v_main_~i~0_27 Int)) (and (< v_main_~i~0_27 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_27 1)))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {6445#(and (= 2 (+ main_~i~0 1)) |main_#t~short10| (exists ((v_main_~i~0_27 Int)) (and (< v_main_~i~0_27 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_27 1)))))} is VALID [2022-04-07 16:44:32,515 INFO L290 TraceCheckUtils]: 27: Hoare triple {6445#(and (= 2 (+ main_~i~0 1)) |main_#t~short10| (exists ((v_main_~i~0_27 Int)) (and (< v_main_~i~0_27 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_27 1)))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6441#(and (= 2 (+ main_~i~0 1)) (exists ((v_main_~i~0_27 Int)) (and (< v_main_~i~0_27 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_27 1)))))} is VALID [2022-04-07 16:44:32,516 INFO L290 TraceCheckUtils]: 28: Hoare triple {6441#(and (= 2 (+ main_~i~0 1)) (exists ((v_main_~i~0_27 Int)) (and (< v_main_~i~0_27 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_27 1)))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6441#(and (= 2 (+ main_~i~0 1)) (exists ((v_main_~i~0_27 Int)) (and (< v_main_~i~0_27 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_27 1)))))} is VALID [2022-04-07 16:44:32,517 INFO L290 TraceCheckUtils]: 29: Hoare triple {6441#(and (= 2 (+ main_~i~0 1)) (exists ((v_main_~i~0_27 Int)) (and (< v_main_~i~0_27 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_27 1)))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {6455#(exists ((v_main_~i~0_27 Int)) (and (< v_main_~i~0_27 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_27 1))))} is VALID [2022-04-07 16:44:32,517 INFO L290 TraceCheckUtils]: 30: Hoare triple {6455#(exists ((v_main_~i~0_27 Int)) (and (< v_main_~i~0_27 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_27 1))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {6455#(exists ((v_main_~i~0_27 Int)) (and (< v_main_~i~0_27 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_27 1))))} is VALID [2022-04-07 16:44:32,517 INFO L290 TraceCheckUtils]: 31: Hoare triple {6455#(exists ((v_main_~i~0_27 Int)) (and (< v_main_~i~0_27 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_27 1))))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {6455#(exists ((v_main_~i~0_27 Int)) (and (< v_main_~i~0_27 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_27 1))))} is VALID [2022-04-07 16:44:32,518 INFO L290 TraceCheckUtils]: 32: Hoare triple {6455#(exists ((v_main_~i~0_27 Int)) (and (< v_main_~i~0_27 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_27 1))))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {6465#(and (= main_~k~0 1) (exists ((v_main_~i~0_27 Int)) (and (< v_main_~i~0_27 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_27 1)))))} is VALID [2022-04-07 16:44:32,518 INFO L290 TraceCheckUtils]: 33: Hoare triple {6465#(and (= main_~k~0 1) (exists ((v_main_~i~0_27 Int)) (and (< v_main_~i~0_27 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_27 1)))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {6349#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} is VALID [2022-04-07 16:44:32,519 INFO L272 TraceCheckUtils]: 34: Hoare triple {6349#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {6472#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 16:44:32,519 INFO L290 TraceCheckUtils]: 35: Hoare triple {6472#(<= 1 |__VERIFIER_assert_#in~cond|)} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {6476#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 16:44:32,519 INFO L290 TraceCheckUtils]: 36: Hoare triple {6476#(<= 1 __VERIFIER_assert_~cond)} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {6328#false} is VALID [2022-04-07 16:44:32,519 INFO L290 TraceCheckUtils]: 37: Hoare triple {6328#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6328#false} is VALID [2022-04-07 16:44:32,520 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2022-04-07 16:44:32,520 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-07 16:44:51,678 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 85 treesize of output 77 [2022-04-07 16:44:51,798 INFO L356 Elim1Store]: treesize reduction 27, result has 27.0 percent of original size [2022-04-07 16:44:51,799 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 42731 treesize of output 41193